SERCON410B

SERCON410B DATASHEET USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED. SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein : 1. Life support devices or systems are those which (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided with the product, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can reasonably be expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. SERCON410B DATASHEET INDEX Page Number SERCON410B .................................... 1 5 6 9 9 9 9 11 11 11 12 12 13 14 15 16 17 17 23 23 25 26 26 29 29 29 29 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 RECOMMENDED OPERATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Clock Input MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Clock Input SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Read Access of Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 Read Access of Dual Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.7 Write Access to Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 3.4.8 Write Access to Dual Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 4 CONTROL REGISTERS AND RAM DATA STRUCTURES . . . . . . . . . . . . . . . . . . . . 4.1 CONTROL REGISTER ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 DATA STRUCTURES WITHIN THE RAM . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Telegram Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Data Containers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 End Marker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 Service Containers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ADDITIONAL SUPPORT AND TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 SERCOS INTERFACE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 SOFTWARE AND BOARDS FOR THE SERCON410B . . . . . . . . . . . . . . . . . . ® SERCON410B NOTES: ® ® SERCON410B SERCOS INTERFACE CONTROLLER PRELIMINARY DATA Single-chip controller for SERCOS interface Real time communication for industrial control systems 8/16-bit bus interface, Intel and Motorola control signals Dual port RAM with 1024 words * 16-bit Data communications via optical fiber rings, RS 485 rings and RS 485 busses Maximum transmission rate of 4 Mbaud with internal clock recovery Maximum transmission rate of 10 Mbaud with external clock recovery Internal repeater for ring connections Full duplex operation Modulation of power of optical transmitter diode Automatic transmission of synchronous and data telegrams in the communication cycle Flexible RAM configuration, communication data stored in RAM (single or double buffer) or transfer via DMA Synchronization by external signal Timing control signals Automatic service channel transmission 100-pin plastic flat-pack casing PQFP100 (Ordering Number: SERGBQA) May 1994 This is Preliminary Data from SGS-THOMSON. Details are subject to change without notice. 1/30 SERCON410B Figure 1. SERCON410B Block Diagram 2/30 ® SERCON410B Figure 2. SERCON410B Pin Configuration 3/30 ® SERCON410B Figure 3. SERCOS Interface with Ring Connection Figure 4. SERCON410B with RS-485 bus Connection 4/30 ® SERCON410B 1 GENERAL DESCRIPTION The SERCOS interface controller SERCON410B is an integrated circuit for SERCOS interface communication systems. The SERCOS interface is a digital interface for communication between systems which have to exchange information cyclically at short, fixed intervals (65 µs to 65 ms). It is appropriate for the synchronous operation of distributed control or test equipment (e.g. connection between drives and numeric control). A SERCOS interface communication system consists of one master and several slaves (Fig. 3). These units are connected by a fiber optical ring. This ring starts and ends at the master. The slaves regenerate and repeat their received data or send their own telegrams. By this method the telegrams sent by the master are received by all slaves while the master receives data telegrams from the slaves. The optical fiber assures a reliable highspeed data transmission with excellent noise immunity. The SERCOS interface controller contains all the hardware-related functions of the SERCOS interface and considerably reduces the hardware costs and the computing time requirements of the microprocessor. It is the direct link between the electro-optical receiver and transmitter and the microprocessor that executes the control algorithms. The SERCON410B can be used both for SERCOS interface masters and slaves. The circuit contains the following functions (Fig. 1): Interface to microprocessor with a data - bus width of 8the 16 bits and with control lines or according to Intel or Motorola standards. a - A serial interface for makinganddirect connection with the optical receiver transmitter of the fiber optic ring or with drivers to an electric ring or bus. Data and clock regeneration, the repeater for ring topologies and the serial transmitter and receiver are integrated. The signals are monitored and test signals generated. The serial interface operates up to 4Mbaud without external circuitry and up to 10 Mbaud with external clock regeneration. (1024 * 16 bit) for control - A dual port RAMdata. The organization of and communication the memory is flexible. processing - Telegram monitoring offor automatic transmission and synchronous and data telegrams. Only transmission data which is intended for the particular interface user is processed. The transmitted data is either stored in the internal RAM (single or double buffer) or transferred via direct memory access (DMA). The transmission of service channel information over several communication cycles is executed automatically. In addition to the SERCOS interface the SERCON410B can also be used for other real-time communications tasks. As an alternative to the fiberoptical ring also bus topologies with RS-485 signals are supported (Fig. 4). The SERCON410B is therefore suitable for a wide range of applications. 5/30 ® SERCON410B 2 PIN DESCRIPTION Table 1. SERCON410B I/O Port Function Summary Signal (s) Pin (s) 77-80, 82-85, 87-90, 92-95 56-59, 61-64, 66-69, 71-74 IO Function Data bus: for 8-bit-wide bus interfaces, data is written to and read via D7-0, for 16-bit-wide bus interfaces via D15-0. When ADMUX is 1, the address which is stored in the address latch with ALEL and ALEH is input via D15-0. Address bus: when ADMUX is 0 the pins are inputs, when ADMUX is 1, they are outputs for the address stored with ALEL (A7-0) and ALEH (A15-8). In the 8-bit bus mode, A0 distinguishes which byte is transmitted via D7-0 (depends on BYTEDIR). In the 16-bit bus mode, data is tansferred via D7-0 only when A0 is 0. A10-1 selects the words of the internal RAM; A61the control registers. Address latch enable, low and high, active high: they are only used when ADMUX is 1. When ALEL/ALEH is 1, the signals go from the data bus to the address bus, when ALEL/ALEH = 0, they store the address. When ADMUX is 0, ALEL/ALEH have to be connected to VDD . Read: for the Intel bus interface, data is read when RDN is 0. For the Motorola bus interface, data is read or written to when RDN is 0 (BUSMODE1 = 0) or RDN is 1 (BUSMODE1 = 1). Write: for the Intel bus interface, data is written to when WRN is 0. For the Motorola bus interface, WRN selects read (WRN = 1) and write (WRN = 0) operations of the data bus. Byte high enable, active low: in the 16-bit bus mode, data is transferred via D15-8 when BHEN is 0. Memory chip select, active low: to access the internal RAM MCSN0 and MCSN1 must be 0. Periphery chip select, active low (PCSN0) and active high (PCSN1): to access the control registers PCSN0 must equal 0 and PCS1 must equal 1. RAM busy, active low: becomes active if an access to an address of the dual port RAM is performed simultaneously to an access to the same memory location by the internal telegram processing. DMA request receive, active high: becomes active if data from the receive FIFO can be read. At the beginning of the read operation of the last word of the receive FIFO, DMAREQR becomes inactive. DMA acknowledge receive, active low: when DMAACKRN is 0, the receive FIFO is read, independent of the levels on A6-1 and the chip select signals. DMA request transmit, active high: becomes active when data can be written to the transmit FIFO. DMAREQT becomes inactive again at the beginning of the last write access to the transmit FIFO. DMA acknowledge transmit, active low: when DMAACKTN is 0, the transmit FIFO is written to when there is a bus write access independent of the levels on A6-1 and the chip select signals. Address data bus: when ADMUX is 0 A15-0 are the address inputs, when ADMUX is 1 A15-0 are the outputs of the address latch. Bus mode: BUSMODE0 = 0 turns on the Intel bus interface (RDN = read, WRN = write), BUSMODE0 = 1 selects the Motorola interface (RDN = data strobe, WRN = read/write). BUSMODE1 selects the 0-active data strobe (BUSMODE1 = 0) or the 1-active data strobe (BUSMODE1 = 1). Bus width: selects the 8-bit- (0) or the 16-bit-wide interface (1). D15-0 I/O A15-0 I/O ALEL, ALEH 54, 53 I RDN 51 I WRN 52 I BHEN MCSN0, MCSN1 PCSN0, PCS1 BUSYN 75 46,47 48,49 I I I 45 O DMAREQR 38 O DMAACKRN 40 I DMAREQT 39 O DMAREQTN 41 I ADMUX 96 I BUSMODE0, BUSMODE1 BUSWIDTH 97,98 I 99 I 6/30 ® SERCON410B PIN DESCRIPTION (Continued) Table 1. SERCON410B I/O Port Function Summary (Continued) Signal (s) BYTEDIR Pin (s) 100 IO I Function Byte address sequence: when BYTEDIR is 0, A0 = 0 addresses the lower 8 bits of a word (low byte first), when BYTEDIR is 1, the upper 8 bits of a word are addressed (high byte first). Interrupts, active low or active high. Interrupt sources and signal polarity are programmable. Internal regeneration. When SREGEN is 0, clock and data regeneration are turned off. RxC and TxC are clock inputs. When SREGEN is 1, clock and data regeneration are turned on. RxC and TxC output the internally generated clocks. Baud rate. When regeneration is turned on, SBAUD selects the baud rate (fSCLK/16 when SBAUD is 0, fSCLK/32 when SBAUD is 1). Can be overwritten by the microprocessor. Receive data for the serial interface. Receive clock for the serial interface. When regeneration is turned off (SREGEN = 0), clock input for the serial receiver and transmitter (only when repeater is turned on); when regeneration is turned on (SREGEN = 1) output of the internally generated receive clock. The maximum frequency is 10 MHz. Receive active, active low. Indicates that the serial receiver is receiving a telegram. Transmit data. The pin can be switched to a high impedance state. Transmit data or output port. The pins either output the serial data or can be used as parallel output ports. When they output transmit data, each pin can be switched to a high impedance state individually. NRZ-coded transmit data. Transmit clock for the serial interface. When regeneration is turned off (SREGEN = 0) and the repeater is turned off, it is the clock input for the serial transmitter; when regeneration is turned on (SREGEN = 1) it is the output for the internally generated transmit clock. The maximum frequency is 10 MHz. Transmitter active, active low. When transmitting own data IDLE is 0. Turn on test generator: TM0 = 0 switches TxD1-6 to continuous signal light, TM1 = 0 switch-over to zero bit stream. The processor can overwrite the level of TM1-0. Line error, active low: goes low when signal distortion is too high or when the receive signal is missing. The operating mode is programmed by the processor. SERCOS interface cycle clock: CYC_CLK synchronizes the communication cycles. The polarity is programmable. Control clock: becomes active within a communication cycle. Time, polarity and width are programmable. Divided control clock: becomes active several times within a ommunication cycle. Number of pulses, start time, repetition rate and polarity are programmable, the pulse width is 1µs. Serial clock for clock regeneration: the frequency is 16 or 32 times the baud rate, the maximum frequency is 64 MHz. 7/30 ® INT0, INT1 44,43 O SREGEN 28 I SBAUD RxD 29 I I 14 12 RxC I/O RECACTN TxD1 TxD6-2 TxDNRZ 26 16 22,21,2 0, 18,17 24 13 O O O O TxC I/O IDLE TM0, TM1 25 30,31 O I L_ERRN 32 O CYC_CLK CON_CLK 34 35 36 I O DIV_CLK O SCLK 2 I SERCON410B PIN DESCRIPTION (Continued) Table 1. SERCON410B I/O Port Function Summary (Continued) Signal (s) SCLKO2 SCLKO4 MCLK RSTN TEST OUTZ Pin (s) 6 5 4 10 7 11 IO O O I I I I Function Clock output: outputs the SCLK clock divided by 2. Clock output: outputs the SCLK clock divided by 4. Master clock for telegram processing and timing control, frequency 12 to 20 MHz. Reset, active low. Must be zero for at least 50 ns after power on. Test, active high. Has to be tied to VSS. Puts outputs into high impedance state, active high: OUTZ is 1 puts all pins into a high impedance state. The clocks are turned off and the circuit is reset. For the in-circuit test and for turning on the powerdown mode. NAND tree output. For the test at the semiconductor manufacturers and for the connection test after board production. NDTRO is not set to a high impedance state. NDTRO 9 3,15,23, 33,42, 50,60, 70,81, 91 1,8,19, 27,37, 55,65, 76,86 O VSS Ground pins. VDD Power supply +5 V ± 5%. 8/30 ® SERCON410B 3 ELECTRICAL CHARACTERISTICS 3.1 ABSOLUTE MAXIMUM RATINGS Symbol VDD VI VO TSTG Supply Voltage Input Voltage Output Voltage Storage Temperature Parameter Value -0.3 to 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 -55 to +150 Unit V V V °C 3.2 RECOMMENDED OPERATING CONDITIONS Symbol TA VDD fSCLK fMCLK fTxC, fRxC Parameter Min. Operating Temperature Operating Supply Voltage Clock Frequency SCLK Clock Frequency MCLK Clock Frequency TxC, RxC -40 4.75 Value Max. 85 5.25 64 20 10 °C V MHz MHz MHz Unit 3.3 DC ELECTRICAL CHARACTERISTICS (VDD = 5V ± 5% TA = -40°C to +85°C, unless otherwise specified) Value Symbol Parameter Test Conditions Min. VIL Input Low Level Voltage Input High Level Voltage Typ. Max. 0.8 V Unit VIH 2.4 All pins except D15-0, A15-0, ALEL, ALEH, RDN, WRN, BHEN, MCSN0-1, PCSN0, PCS1, DMAACKTN, DMAACKRN 0.6 2.0 2.4 V V Schmitt trig. +ve threshold VT+ VT- Schmitt trig. +ve threshold 0.8 V 9/30 ® SERCON410B DC ELECTRICAL CHARACTERISTICS (Continued) Value Symbol Parameter Test Conditions Min. IIL Low Level Input Current (Pull-up resistor) High Level Input Current VI = VSS -450 Typ. -50 Max. -30 µA µA Unit IIH VOL VI = VDD -10