SMP100LC-160

® SMP100LC TRISIL™ FOR TELECOM EQUIPMENT PROTECTION FEATURES ■ Bidirectional crowbar protection ■ Voltage range from 8V to 400V ■ Low capacitance from 20pF to 45pF @ 50V ■ Low leakage current : IR = 2µA max ■ Holding current: IH = 150 mA min ■ Repetitive peak pulse current: IPP = 100 A (10/1000µs) MAIN APPLICATIONS Any sensitive equipment requiring protection against lightning strikes and power crossing. These devices are dedicated to central office protection as they comply with the most stressfull standards. Their Low Capacitances make them suitable for ADSL. DESCRIPTION The SMP100LC is a series of low capacitance transient surge arrestors designed for the protection of high debit rate communication equipment. Its low capacitance avoids any distortion of the signal and is compatible with digital transmission line cards (xDSL, ISDN...). SMP100LC series tested and confirmed compatible with Cooper Bussmann Telecom Circuit Protector TCP 1.25A. BENEFITS Trisils are not subject to ageing and provide a fail safe mode in short circuit for a better protection. They are used to help equipment to meet main standards such as UL60950, IEC950 / CSA C22.2 and UL1459. They have UL94 V0 approved resin. SMB package is JEDEC registered (DO-214AA). Trisils comply with the following standards GR1089 Core, ITU-T-K20/K21, VDE0433, VDE0878, IEC61000-4-5 and FCC part 68. SMB (JEDEC DO-214AA) Table 1: Order Codes Part Number SMP100LC-8 SMP100LC-25 SMP100LC-35 SMP100LC-65 SMP100LC-90 SMP100LC-120 SMP100LC-140 SMP100LC-160 SMP100LC-200 SMP100LC-230 SMP100LC-270 SMP100LC-320 SMP100LC-360 SMP100LC-400 Figure 1: Schematic Diagram Marking PL8 L25 L35 L06 L09 L12 L14 L16 L20 L23 L27 L32 L36 L40 June 2005 REV. 11 1/10 SMP100LC Table 2: In compliance with the following standards STANDARD GR-1089 Core First level GR-1089 Core Second level GR-1089 Core Intra-building ITU-T-K20/K21 ITU-T-K20 (IEC61000-4-2) VDE0433 VDE0878 IEC61000-4-5 FCC Part 68, lightning surge type A FCC Part 68, lightning surge type B Peak Surge Voltage (V) 2500 1000 5000 1500 6000 1500 8000 15000 4000 2000 4000 2000 4000 4000 1500 800 1000 Waveform Voltage 2/10 µs 10/1000 µs 2/10 µs 2/10 µs 10/700 µs 1/60 ns 10/700 µs 1.2/50 µs 10/700 µs 1.2/50 µs 10/160 µs 10/560 µs 9/720 µs Required peak current (A) 500 100 500 100 150 37.5 Current waveform 2/10 µs 10/1000 µs 2/10 µs 2/10 µs 5/310 µs Minimum serial resistor to meet standard (Ω) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ESD contact discharge ESD air discharge 100 50 100 50 100 100 200 100 25 5/310 µs 1/20 µs 5/310 µs 8/20 µs 10/160 µs 10/560 µs 5/320 µs Table 3: Absolute Ratings (Tamb = 25°C) Symbol IPP Parameter Repetitive peak pulse current (see figure 2) 10/1000 µs 8/20 µs 10/560 µs 5/310 µs 10/160 µs 1/20 µs 2/10 µs 8/20 µs t = 0.2 s t=1s t=2s t = 15 mn t = 16.6 ms t = 20 ms Value 100 400 140 150 200 400 500 5 24 15 12 4 20 21 -55 to 150 150 260 Unit A IFS ITSM Fail-safe mode : maximum current (note 1) Non repetitive surge peak on-state current (sinusoidal) kA A I2t Tstg Tj TL I2t value for fusing Storage temperature range Maximum junction temperature Maximum lead temperature for soldering during 10 s. A2s °C °C Note 1: in fail safe mode, the device acts as a short circuit 2/10 SMP100LC Table 4: Thermal Resistances Symbol Parameter Rth(j-a) Junction to ambient (with recommended footprint) Rth(j-l) Junction to leads Table 5: Electrical Characteristics (Tamb = 25°C) Symbol VRM VBR VBO IRM IPP IBO IH VR IR C Parameter Stand-off voltage Breakdown voltage Breakover voltage Leakage current Peak pulse current Breakover current Holding current Continuous reverse voltage Leakage current at VR Capacitance Dynamic VBO max. note 2 Value 100 20 Unit °C/W °C/W IRM @ VRM Types µA SMP100LC-8 SMP100LC-25 SMP100LC-35 SMP100LC-65 SMP100LC-90 SMP100LC-120 SMP100LC-140 SMP100LC-160 SMP100LC-200 SMP100LC-230 SMP100LC-270 SMP100LC-320 SMP100LC-360 SMP100LC-400 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: IR @ VR max. note1 Static VBO @ IBO max. V 15 35 55 85 125 160 190 200 250 285 335 390 450 530 800 max. mA note 3 IH min. note 4 C typ. note 5 C typ. note 6 max. V 6 22 32 55 81 108 2 120 144 180 207 243 290 325 360 µA V 8 25 35 65 90 120 140 160 200 230 270 320 360 400 V 25 40 55 85 120 155 185 205 255 295 345 400 460 540 mA 50 (typ.) pF NA NA NA 45 40 35 30 30 30 30 30 25 25 20 pF 75 65 55 90 80 75 65 65 60 60 60 50 50 45 5 150 IR measured at VR guarantee VBR min ≥ VR see functional test circuit 1 see test circuit 2 see functional holding current test circuit 3 VR = 50V bias, VRMS=1V, F=1MHz VR = 2V bias, VRMS=1V, F=1MHz 3/10 SMP100LC Figure 2: Pulse waveform Figure 3: Non repetitive surge peak on-state current versus overload duration ITSM(A) 70 60 50 40 F=50Hz Tj initial = 25°C %IPP 100 Repetitive peak pulse current tr = rise time (µs) tp = pulse duration time (µs) 50 30 20 0 tr tp 10 t t(s) 0 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3 Figure 4: On-state voltage versus on-state current (typical values) IT(A) 100 Tj initial = 25°C Figure 5: Relative variation of holding current versus junction temperature IH[Tj] / IH[Tj=25°C] 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 VT(V) 10 0 1 2 3 4 5 6 7 8 0.2 0.0 -25 0 25 Tj(°C) 50 75 100 125 Figure 6: Relative variation of breakover voltage versus junction temperature VBO[Tj] / VBO[Tj=25°C] 1.08 1.06 1.04 Figure 7: Relative variation of leakage current versus junction temperature (typical values) IR[Tj] / IR[Tj=25°C] 2000 1000 100 1.02 1.00 0.98 10 Tj(°C) 0.96 -25 0 25 50 75 100 125 Tj(°C) 1 25 50 75 100 125 4/10 SMP100LC Figure 8: Variation of thermal impedance junction to ambient versus pulse duration (Printed circuit board FR4, SCu=35µm, recommended pad layout) Zth(j-a)/Rth(j-a) 100 1.4 1.2 1.0 0.8 0.6 0.4 0.2 F =1MHz VRMS = 1V Tj = 25°C Figure 9: Relative variation of junction capacitance versus reverse voltage applied (typical values) C [VR] / C [VR=2V] 10 tp(s) 1 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 5E+2 VR(V) 0.0 1 2 5 10 20 50 100 300 APPLICATION NOTE In wireline applications, analog or digital, both central office and subscriber sides have to be protected. This function is assumed by a combined series / parallel protection stage. Ring relay Protection stage Line Line Ex. Analog line card Ex. ADSL line card or terminal In such a stage, parallel function is assumed by one or several Trisil, and is used to protect against short duration surge (lightning). During this kind of surges the Trisil limits the voltage across the device to be protected at its break over value and then fires. The fuse assumes the series function, and is used to protect the module against long duration or very high current mains disturbances (50/60Hz). It acts by safe circuits opening. Lightning surge and mains disturbance surges are defined by standards like GR1089, FCC part 68, ITU-T K20. Fuse TCP 1.25A Tip L Tip S Fuse TCP 1.25A T1 Protection stage SMP100LC-xxx Gnd Gnd SMP100LC-xxx T2 SMP100LC-xxx Fuse TCP 1.25A Ring L Ring S Typical circuit for subscriber side Typical circuit for central office side 5/10 SMP100LC Following figure shows the test method of the board having Fuse and Trisil. I surge Surge Generator Line side Test board V Following curve shows the turn on of the Trisil during lightning surge. Device to be protected I surge (100A/div) Oscilloscope V (50V/div) Current probe Voltage probe These topologies, using SMP100LC from ST and TCP1.25A from Cooper Bussmann, have been functionally validated with a Trisil glued on the PCB. Following example was performed with SMP100LC-270 Trisil. For more information, see Application Note AN2064. Following curve shows Trisil action while the fuse remains operational. Test conditions: 2/10µs + and -2.5 and 5kV 500A (10 pulses of each polarity), Tamb = 25°C Test result: Fuse and Trisil OK after test in accordance with GR1089 requirements In case of high current power cross test, the fuse acts like a switch by opening the circuit. I surge (2A/div) I surge (10A/div) V (100V/div) V (100V/div) Test conditions: 600V 3A 1.1s (first level), Tamb = 25°C Test result: Fuse and Trisil OK after test in accordance with GR1089 requirements Test conditions: 277V 25A (second level), Tamb = 25°C Test result: Fuse safety opened and Trisil OK after test in accordance with GR1089 requirements 6/10 SMP100LC Figure 10: Test circuit 1 for Dynamic IBO and VBO parameters 100 V / µs, di /dt < 10 A / µs, Ipp = 100 A 2Ω 45 Ω 66 Ω 470 Ω 83 Ω 0.36 nF 46 µH U 10 µF KeyTek 'System 2' generator with PN246I module 1 kV / µs, di /dt < 10 A / µs, Ipp = 10 A 26 µH 250 Ω 12 Ω 47 Ω 46 µH U 60 µF KeyTek 'System 2' generator with PN246I module Figure 11: Test circuit 2 for IBO and VBO parameters K ton = 20ms R1 = 140Ω R2 = 240Ω 220V 50Hz Vout DUT VBO measurement 1/4 IBO measurement TEST PROCEDURE Pulse test duration (tp = 20ms): ● for Bidirectional devices = Switch K is closed ● for Unidirectional devices = Switch K is open VOUT selection: ● Device with VBO < 200V ➔ VOUT = 250 VRMS, R1 = 140Ω ● Device with VBO ≥ 200V ➔ VOUT = 480 VRMS, R2 = 240Ω 7/10 SMP100LC Figure 12: Test circuit 3 for dynamic IH parameter R Surge generator VBAT = - 48 V D.U.T This is a GO-NOGO test which allows to confirm the holding current (IH) level in a functional test circuit. TEST PROCEDURE 1/ Adjust the current level at the IH value by short circuiting the AK of the D.U.T. 2/ Fire the D.U.T. with a surge current ➔ IPP = 10A, 10/1000µs. 3/ The D.U.T. will come back off-state within 50ms maximum. Figure 13: Ordering Information Scheme SMP Trisil Surface Mount Repetitive Peak Pulse Current 100 = 100A Capacitance LC = Low Capacitance Voltage 65 = 65V 100 LC - xxx 8/10 SMP100LC Figure 14: SMB Package Mechanical data E1 REF. D E A1 C L A2 b A1 A2 b c E E1 D L DIMENSIONS Millimeters Inches Min. Max. Min. Max. 1.90 2.45 0.075 0.096 0.05 0.20 0.002 0.008 1.95 2.20 0.077 0.087 0.15 0.41 0.006 0.016 5.10 5.60 0.201 0.220 4.05 4.60 0.159 0.181 3.30 3.95 0.130 0.156 0.75 1.60 0.030 0.063 Figure 15: Foot Print Dimensions (in millimeters) 2.3 1.52 2.75 1.52 Table 6: Ordering Information Part Number SMP100LC-8 SMP100LC-25 SMP100LC-35 SMP100LC-65 SMP100LC-90 SMP100LC-120 SMP100LC-140 SMP100LC-160 SMP100LC-200 SMP100LC-230 SMP100LC-270 SMP100LC-320 SMP100LC-360 SMP100LC-400 Table 7: Revision History Date 09-Nov-2004 07-Dec-2004 20-Jun-2005 Revision 9 10 11 Description of Changes Absolute ratings values, table 3 on page 2, updated. SMP100LC-320, SMP100LC-360 and SMP100LC-400 addition. Telecom Circuit Protector added 9/10 Marking PL8 L25 L35 L06 L09 L12 L14 L16 L20 L23 L27 L32 L36 L40 Package Weight Base qty Delivery mode SMB 0.11 g 2500 Tape & reel SMP100LC Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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