SPC560B40L3B3E0X

SPC560B40x, SPC560B50x SPC560C40x, SPC560C50x 32-bit MCU family built on the Power Architecture® for automotive body electronics applications Datasheet - production data – Up to 6 FlexCAN interfaces (2.0B active) with 64-message objects each – Up to 4 LINFlex/UART – 3 DSPI / I2C LQFP100 (14 x 14 x 1.4 mm) LQFP64 (10 x 10 x 1.4 mm) LQFP144 (20 x 20 x 1.4 mm)  10-bit analog-to-digital converter (ADC) with up to 36 channels – Extendable to 64 channels via external multiplexing – Individual conversion registers – Cross triggering unit (CTU) Features  High-performance 64 MHz e200z0h CPU – 32-bit Power Architecture® technology – Up to 60 DMIPs operation – Variable length encoding (VLE)  Memory – Up to 512 KB Code Flash with ECC – 64 KB Data Flash with ECC – Up to 48 KB SRAM with ECC – 8-entry memory protection unit (MPU)  Interrupts – 16 priority levels – Non-maskable interrupt (NMI) – Up to 34 external interrupts incl. 18 wakeup lines  GPIO: 45(LQFP64), 75(LQFP100), 123(LQFP144)  Timer units – 6-channel 32-bit periodic interrupt timers – 4-channel 32-bit system timer module – Software watchdog timer – Real-time clock timer  16-bit counter time-triggered I/Os – Up to 56 channels with PWM/MC/IC/OC – ADC diagnostic via CTU  Communications interface Package LQFP144 LQFP100 LQFP64(1)  Single 5 V or 3.3 V supply  Dedicated diagnostic module for lighting – Advanced PWM generation – Time-triggered diagnostic – PWM-synchronized ADC measurements  Clock generation – 4 to 16 MHz fast external crystal oscillator (FXOSC) – 32 kHz slow external crystal oscillator (SXOSC) – 16 MHz fast internal RC oscillator (FIRC) – 128 kHz slow internal RC oscillator (SIRC) – Software-controlled FMPLL – Clock monitor unit (CMU)  Exhaustive debugging capability – Nexus1 on all devices – Nexus2+ available on emulation package (LBGA208)  Low power capabilities – Ultra-low power standby with RTC, SRAM and CAN monitoring – Fast wakeup schemes  Operating temp. range up to -40 to 125 °C Table 1. Device summary Part number 256 KB code Flash memory SPC560B40L5 SPC560B40L3 SPC560B40L1 — SPC560C40L3 SPC560C40L1 512 KB code Flash memory SPC560B50L5 SPC560B50L3 SPC560B50L1 — SPC560C50L3 SPC560C50L1 1. All LQFP64information is indicative and must be confirmed during silicon validation. February 2015 This is information on a product in full production. DocID14619 Rev 13 1/116 www.st.com Contents SPC560B40x/50x, SPC560C40x/50x Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7 Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.10 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.11 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.11.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . 41 3.11.3 NVUSRO[WATCHDOG_EN] field description . . . . . . . . . . . . . . . . . . . . 41 3.12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.13 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.14 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.15 2/116 3.11.1 3.14.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.14.2 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.15.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.15.2 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.15.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.15.4 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.15.5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x 3.16 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.17 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 60 3.17.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 60 3.17.2 Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . 65 3.18 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.19 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.20 3.19.1 Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.19.2 Flash power supply DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.19.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . . 70 3.20.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 70 3.20.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.20.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 71 3.21 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . 72 3.22 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . 75 3.23 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.24 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . 78 3.25 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 79 3.26 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.27 4 Contents 3.26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.26.2 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.26.3 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.27.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.27.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.27.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.27.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.2.1 LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.2.2 LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.2.3 LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.2.4 LBGA208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 DocID14619 Rev 13 3/116 4 Contents 5 SPC560B40x/50x, SPC560C40x/50x Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Appendix A Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPC560B40x/50x and SPC560C40x/50x device comparison . . . . . . . . . . . . . . . . . . . . . . . 9 SPC560B40x/50x and SPC560C40x/50x series block summary . . . . . . . . . . . . . . . . . . . . 13 Voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Nexus 2+ pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 OSCILLATOR_MARGIN field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 WATCHDOG_EN field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 48 MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 49 FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 50 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I/O supply segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Power consumption on VDD_BV and VDD_HV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Flash memory power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 69 Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 74 Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 77 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 78 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 79 ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 DocID14619 Rev 13 5/116 6 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. 6/116 SPC560B40x/50x, SPC560C40x/50x JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. SPC560B40x/50x and SPC560C40x/50x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LQFP 64-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LQFP 100-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 LQFP 144-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 LBGA208 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 VDD_HV and VDD_BV maximum slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 VDD_HV and VDD_BV supply constraints during STANDBY mode exit . . . . . . . . . . . . . . . . 62 Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Fast external crystal oscillator (4 to 16 MHz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . 74 Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Slow external crystal oscillator (32 kHz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ADC characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DSPI classic SPI timing – master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 DSPI classic SPI timing – master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 DSPI classic SPI timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 DSPI classic SPI timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 DSPI modified transfer format timing – master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 94 DSPI modified transfer format timing – master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 95 DSPI modified transfer format timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 95 DSPI modified transfer format timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 96 DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Timing diagram – JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 LQFP64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 LBGA208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 DocID14619 Rev 13 7/116 7 Introduction 1 Introduction 1.1 Document overview SPC560B40x/50x, SPC560C40x/50x This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet. 1.2 Description The SPC560B40x/50x and SPC560C40x/50x is a family of next generation microcontrollers built on the Power Architecture embedded category. The SPC560B40x/50x and SPC560C40x/50x family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU, providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. 8/116 DocID14619 Rev 13 Device Feature SPC560B SPC560B SPC560B SPC560C SPC560C SPC560B SPC560B SPC560B SPC560C SPC560C SPC560B 40L1 40L3 40L5 40L1 40L3 50L1 50L3 50L5 50L1 50L3 50B2 CPU e200z0h Execution speed(2) Static – up to 64 MHz Code Flash 256 KB 512 KB Data Flash 64 KB (4 × 16 KB) RAM 24 KB 32 KB 32 KB MPU 48 KB 8-entry DocID14619 Rev 13 ADC (10-bit) 12 ch 28 ch 36 ch 8 ch 28 ch CTU 12 ch 28 ch 36 ch 8 ch 28 ch 36 ch Yes (3) 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit – PWM + MC + IC/OC(4) 2 ch 5 ch 10 ch 2 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 10 ch – PWM + IC/OC(4) 10 ch 20 ch 40 ch 10 ch 20 ch 10 ch 20 ch 40 ch 10 ch 20 ch 40 ch – IC/OC(4) — 3 ch 6 ch — 3 ch — 3 ch 6 ch — 3 ch 6 ch Total timer I/O eMIOS 3(5) SCI (LINFlex) SPI (DSPI) 2 4 3 2 2(6) CAN (FlexCAN) 5 3 2 3 3(7) 6 I2C 2 3 5 6 1 Yes 45 79 123 45 79 45 79 123 45 79 123 9/116 Introduction 32 kHz oscillator GPIO(8) SPC560B40x/50x, SPC560C40x/50x Table 2. SPC560B40x/50x and SPC560C40x/50x device comparison(1) Device Feature SPC560B SPC560B SPC560B SPC560C SPC560C SPC560B SPC560B SPC560B SPC560C SPC560C SPC560B 40L1 40L3 40L5 40L1 40L3 50L1 50L3 50L5 50L1 50L3 50B2 Debug Package JTAG LQFP64(9) LQFP100 LQFP144 LQFP64(9) LQFP100 LQFP64(9) Introduction 10/116 Table 2. SPC560B40x/50x and SPC560C40x/50x device comparison(1) (continued) Nexus2+ LQFP100 LQFP144 LQFP64(9) LQFP100 LBGA208 (10) 1. Feature set dependent on selected peripheral multiplexing—table shows example implementation. 2. Based on 125 °C ambient operating temperature. 3. See the eMIOS section of the device reference manual for information on the channel configuration and functions. 4. IC – Input Capture; OC – Output Compare; PWM – Pulse Width Modulation; MC – Modulus counter. 5. SCI0, SCI1 and SCI2 are available. SCI3 is not available. DocID14619 Rev 13 6. CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available. 7. CAN0, CAN1 and CAN2 are available. CAN3, CAN4 and CAN5 are not available. 8. I/O count based on multiplexing with peripherals. 9. All LQFP64 information is indicative and must be confirmed during silicon validation. 10. LBGA208 available only as development package for Nexus2+. SPC560B40x/50x, SPC560C40x/50x SPC560B40x/50x, SPC560C40x/50x 2 Block diagram Block diagram Figure 1 shows a top-level block diagram of the SPC560B40x/50x and SPC560C40x/50x device series. DocID14619 Rev 13 11/116 115 Block diagram SPC560B40x/50x, SPC560C40x/50x Figure 1. SPC560B40x/50x and SPC560C40x/50x block diagram SRAM 48 KB Code Flash Data Flash 512 KB 64 KB SRAM controller Flash controller JTAG e200z0h Nexus (Master) Data NMI Nexus 2+ (Master) SIUL Voltage regulator Interrupt requests from peripheral blocks NMI INTC Clocks MPU Instructions Nexus port 64-bit 2 x 3 Crossbar Switch JTAG port (Slave) (Slave) (Slave) MPU registers CMU FMPLL RTC STM SWT ECSM MC_RGM MC_CGM MC_ME MC_PCU PIT SSCM BAM Peripheral bridge Interrupt request SIUL Reset control 36 Ch. ADC 2x eMIOS CTU 4x LINFlex 3x DSPI 6x FlexCAN I2C External interrupt request IMUX WKPU GPIO and pad control I/O ... ... ... ... ... Interrupt request with wakeup functionality Legend: ADC BAM FlexCAN CMU CTU DSPI eMIOS FMPLL I2C IMUX INTC JTAG LINFlex ECSM MC_CGM Analog-to-Digital Converter Boot Assist Module Controller Area Network Clock Monitor Unit Cross Triggering Unit Deserial Serial Peripheral Interface Enhanced Modular Input Output System Frequency-Modulated Phase-Locked Loop Inter-integrated Circuit Bus Internal Multiplexer Interrupt Controller JTAG controller Serial Communication Interface (LIN support) Error Correction Status Module Clock Generation Module MC_ME MC_PCU MC_RGM MPU Nexus NMI PIT RTC SIUL SRAM SSCM STM SWT WKPU Mode Entry Module Power Control Unit Reset Generation Module Memory Protection Unit Nexus Development Interface (NDI) Level Non-Maskable Interrupt Periodic Interrupt Timer Real-Time Clock System Integration Unit Lite Static Random-Access Memory System Status Configuration Module System Timer Module Software Watchdog Timer Wakeup Unit Table 3 summarizes the functions of all blocks present in the SPC560B40x/50x and SPC560C40x/50x series of microcontrollers. Please note that the presence and number of blocks vary by device and package. 12/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Block diagram Table 3. SPC560B40x/50x and SPC560C40x/50x series block summary Block Function Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according to the boot mode of the device Clock monitor unit (CMU) Monitors clock source (internal and external) integrity Cross triggering unit (CTU) Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices (DSPI) Error Correction Status Module (ECSM) Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host (eDMA) processor via “n” programmable channels. Enhanced modular input output system (eMIOS) Provides the functionality to generate or measure events Flash memory Provides non-volatile storage for program code, constants and variables FlexCAN (controller area network) Supports the standard CAN communications protocol Frequency-modulated phaselocked loop (FMPLL) Generates high-speed system clocks and supports programmable frequency modulation Internal multiplexer (IMUX) SIU subblock Allows flexible mapping of peripheral interface on the different pins of the device Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests JTAG controller Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode LINFlex controller Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Clock generation module (MC_CGM) Provides logic and control required for the generation of system and peripheral clocks Mode entry module (MC_ME) Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Power control unit (MC_PCU) Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called “power domains” which are controlled by the PCU Reset generation module (MC_RGM) Centralizes reset sources and manages the device reset sequence of the device DocID14619 Rev 13 13/116 115 Block diagram SPC560B40x/50x, SPC560C40x/50x Table 3. SPC560B40x/50x and SPC560C40x/50x series block summary (continued) Block Function Memory protection unit (MPU) Provides hardware access control for all memory references generated in a device Nexus development interface (NDI) Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2003 standard Periodic interrupt timer (PIT) Produces periodic interrupts and triggers Real-time counter (RTC) A free running counter used for time keeping applications, the RTC can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) System integration unit (SIU) Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration Static random-access memory (SRAM) Provides storage for program code, constants, and variables System status configuration module (SSCM) Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable System timer module (STM) Provides a set of output compare events to support AUTOSAR (Automotive Open System Architecture) and operating system tasks Software watchdog timer (SWT) Provides protection from runaway code Wakeup unit (WKPU) The wakeup unit supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. Crossbar (XBAR) switch Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. 14/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions 3 Package pinouts and signal descriptions 3.1 Package pinouts The available LQFP pinouts and the LBGA208 ballmap are provided in the following figures. For pin signal descriptions, please refer to the device reference manual (RM0017). 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PB[2] PC[8] PC[4] PC[5] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] Figure 2. LQFP 64-pin configuration(a) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LQFP64 Top view 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PA[11] PA[10] PA[9] PA[8] PA[7] PA[3] PB[15] PB[14] PB[13] PB[12] PB[11] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PB[4] 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PB[3] PC[9] PA[2] PA[1] PA[0] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[10] PB[0] PB[1] PC[6] a. All LQFP64 information is indicative and must be confirmed during silicon validation. DocID14619 Rev 13 15/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PE[12] Figure 3. LQFP 100-pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 Top view 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PA[11] PA[10] PA[9] PA[8] PA[7] VDD_HV VSS_HV PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PB[3] PC[9] PC[14] PC[15] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[11] PC[10] PB[0] PB[1] PC[6] Note: Availability of port pin alternate functions depends on product selection. 16/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 Top view 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC PC[7] PF[10] PF[11] PA[15] PF[13] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PB[3] PC[9] PC[14] PC[15] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] PC[6] 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12] Figure 4. LQFP 144-pin configuration Note: Availability of port pin alternate functions depends on product selection. DocID14619 Rev 13 17/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Figure 5. LBGA208 configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A PC[8] PC[13] NC NC PH[8] PH[4] PC[5] PC[0] NC NC PC[2] NC PE[15] NC NC NC A B PC[9] PB[2] NC PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] NC PC[3] PG[11] PG[15] PG[14] PA[11] PA[10] B C PC[14] VDD_HV PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV PC[1] NC PA[5] NC PE[14] PE[12] PA[9] PA[8] C D NC NC PC[15] NC PH[6] PE[4] PE[2] VDD_LV VDD_HV NC PA[6] NC PG[10] PF[14] PE[13] PA[7] D E PG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15] VDD_HV E F PE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2] F G PE[9] PE[8] PE[10] PA[0] VSS_HV VSS_HV VSS_HV VSS_HV VDD_HV NC NC MSEO G H VSS_HV PE[11] VDD_HV NC VSS_HV VSS_HV VSS_HV VSS_HV MDO3 MDO2 MDO0 MDO1 H J RESET VSS_LV NC NC VSS_HV VSS_HV VSS_HV VSS_HV NC NC NC NC J K EVTI NC VDD_BV VDD_LV VSS_HV VSS_HV VSS_HV VSS_HV NC PG[12] PA[3] PG[13] K L PG[9] PG[8] NC EVTO PB[15] PD[15] PD[14] PB[14] L M PG[7] PG[6] PC[10] PC[11] PB[13] PD[13] PD[12] PB[12] M N PB[1] PF[9] PB[0] NC NC PA[4] VSS_LV EXTAL VDD_HV PF[0] PF[4] NC PB[11] PD[10] PD[9] PD[11] N P PF[8] NC PC[7] NC NC PA[14] VDD_LV XTAL PB[10] PF[1] PF[5] PD[0] PD[3] VDD_HV _ADC PB[6] PB[7] P R PF[12] PC[6] PF[10] PF[11] VDD_HV PA[15] PA[13] NC OSC32K _XTAL PF[3] PF[7] PD[2] PD[4] PD[7] VSS_HV _ADC PB[5] R T NC NC NC MCKO NC PF[13] PA[12] NC OSC32K _EXTAL PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4] T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1. Note: LBGA208 available only as development package for Nexus 2+. 3.2 NC = Not connected Pad configuration during reset phases All pads have a fixed configuration under reset. During the power-up phase, all pads are forced to tristate. After power-up phase, all pads are forced to tristate with the following exceptions: 18/116  PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash.  PA[8] (ABS[0]) is pull-up.  RESET pad is driven low. This is pull-up only after PHASE2 reset completion.  JTAG pads (TCK, TMS and TDI) are pull-up whilst TDO remains tristate.  Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available).  Main oscillator pads (EXTAL, XTAL) are tristate.  Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output. DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x 3.3 Package pinouts and signal descriptions Voltage supply pins Voltage supply pins are used to provide power to the device. Three dedicated VDD_LV/VSS_LV supply pairs are used for 1.2 V regulator stabilization. Table 4. Voltage supply pin descriptions Pin number Port pin Function LQFP64 VDD_HV Digital supply voltage LQFP100 LQFP144 LBGA208(1) 15, 37, 70, 84 C2, D9, E16, 19, 51, 100, G13, H3, N9, 123 R5 6, 8, 26, 55 14, 16, 35, 69, 83 G7, G8, G9, G10, H1, H7, 18, 20, 49, H8, H9, H10, 99, 122 J7, J8, J9, J10, K7, K8, K9, K10 7, 28, 56 VSS_HV Digital ground VDD_LV 1.2V decoupling pins. Decoupling capacitor must be connected between these pins and the nearest VSS_LV pin.(2) 11, 23, 57 19, 32, 85 23, 46, 124 D8, K4, P7 VSS_LV 1.2V decoupling pins. Decoupling capacitor must be connected between these pins and the nearest VDD_LV pin.(2) 10, 24, 58 18, 33, 86 22, 47, 125 C8, J2, N7 VDD_BV Internal regulator supply voltage 12 20 24 K3 VSS_HV_ADC Reference ground and analog ground for the ADC 33 51 73 R15 VDD_HV_ADC Reference voltage and analog supply for the ADC 34 52 74 P14 1. LBGA208 available only as development package for Nexus2+ 2. A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see the recommended operating conditions in the device datasheet for details). 3.4 Pad types In the device the following types of pads are available for system pins and functional port pins: S = Slow(b) M = Medium(b) (c) F = Fast(b) (c) I = Input only with analog feature(b) J = Input/Output (‘S’ pad) with analog feature X = Oscillator b. See the I/O pad electrical characteristics in the device datasheet for details. DocID14619 Rev 13 19/116 115 Package pinouts and signal descriptions 3.5 SPC560B40x/50x, SPC560C40x/50x System pins The system pins are listed in Table 5. Table 5. System pin descriptions RESET configuration LQFP64 LQFP100 LQFP144 LBGA208(1) I/O M Input, weak pull-up only after PHASE2 9 17 21 J1 I/O X Tristate 27 36 50 N8 I X Tristate 25 34 48 P8 Function Bidirectional reset with Schmitt-Trigger characteristics and noise filter. Analog output of the oscillator amplifier circuit, when the oscillator is not in bypass mode. EXTAL Analog input for the clock generator when the oscillator is in bypass mode.(2) XTAL Pad type RESET I/O direction System pin Pin number Analog input of the oscillator amplifier circuit. Needs to be grounded if oscillator is used in bypass mode.(2) 1. LBGA208 available only as development package for Nexus2+ 2. See the relevant section of the datasheet 3.6 Functional ports The functional port pins are listed in Table 6. c. 20/116 All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see PCR.SRC in section Pad Configuration Registers (PCR0–PCR122) in the device reference manual). DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions Tristate 5 12 16 G4 PCR[1] AF0 AF1 AF2 AF3 — — GPIO[1] E0UC[1] — — (5) NMI WKPU[2](4) SIUL eMIOS_0 — — WKPU WKPU I/O I/O — — I I S Tristate 4 7 11 F3 PCR[2] AF0 AF1 AF2 AF3 — GPIO[2] E0UC[2] — — WKPU[3](4) SIUL eMIOS_0 — — WKPU I/O I/O — — I S Tristate 3 5 9 F2 PCR[3] AF0 AF1 AF2 AF3 — GPIO[3] E0UC[3] — — EIRQ[0] SIUL eMIOS_0 — — SIUL I/O I/O — — I S Tristate 43 68 90 K15 PCR[4] AF0 AF1 AF2 AF3 — GPIO[4] E0UC[4] — — WKPU[9](4) SIUL eMIOS_0 — — WKPU I/O I/O — — I S Tristate 20 29 43 N6 PCR[5] AF0 AF1 AF2 AF3 GPIO[5] E0UC[5] — — SIUL eMIOS_0 — — I/O I/O — — M Tristate 51 79 118 C11 PCR[6] AF0 AF1 AF2 AF3 — GPIO[6] E0UC[6] — — EIRQ[1] SIUL eMIOS_0 — — SIUL I/O I/O — — I S Tristate 52 80 119 D11 DocID14619 Rev 13 configuration M RESET I/O I/O O — I Function SIUL eMIOS_0 CGL — WKPU Alternate PCR[0] GPIO[0] E0UC[0] CLKOUT — WKPU[19](4) function(1) LBGA208(3) PA[6] LQFP144 PA[5] LQFP100 PA[4] LQFP64 PA[3] Pad type PA[2] I/O direction(2) PA[1] Peripheral PA[0] AF0 AF1 AF2 AF3 — PCR Port pin Pin number 21/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 6. Functional port pin descriptions (continued) 22/116 Tristate 44 71 104 D16 PCR[8] AF0 AF1 AF2 AF3 — N/A(6) — GPIO[8] E0UC[8] — — EIRQ[3] ABS[0] LIN3RX SIUL eMIOS_0 — — SIUL BAM LINFlex_3 I/O I/O — — I I I S Input, weak pull-up 45 72 105 C16 PCR[9] AF0 AF1 AF2 AF3 N/A(6) GPIO[9] E0UC[9] — — FAB SIUL eMIOS_0 — — BAM I/O I/O — — I S Pull-down 46 73 106 C15 PCR[10] AF0 AF1 AF2 AF3 GPIO[10] E0UC[10] SDA — SIUL eMIOS_0 I2C_0 — I/O I/O I/O — S Tristate 47 74 107 B16 PCR[11] AF0 AF1 AF2 AF3 GPIO[11] E0UC[11] SCL — SIUL eMIOS_0 I2C_0 — I/O I/O I/O — S Tristate 48 75 108 B15 PCR[12] AF0 AF1 AF2 AF3 — GPIO[12] — — — SIN_0 SIUL — — — DSPI0 I/O — — — I S Tristate 22 31 45 T7 PCR[13] AF0 AF1 AF2 AF3 GPIO[13] SOUT_0 — — SIUL DSPI_0 — — I/O O — — M Tristate 21 30 44 R7 DocID14619 Rev 13 configuration S RESET I/O I/O O — I Function SIUL eMIOS_0 LINFlex_3 — SIUL Alternate PCR[7] GPIO[7] E0UC[7] LIN3TX — EIRQ[2] function(1) LBGA208(3) PA[13] LQFP144 PA[12] LQFP100 PA[11] LQFP64 PA[10] Pad type PA[9] I/O direction(2) PA[8] Peripheral PA[7] AF0 AF1 AF2 AF3 — PCR Port pin Pin number SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) Tristate 19 28 42 P6 PCR[15] AF0 AF1 AF2 AF3 — GPIO[15] CS0_0 SCK_0 — WKPU[10](4) SIUL DSPI_0 DSPI_0 — WKPU I/O I/O I/O — I M Tristate 18 27 40 R6 PCR[16] AF0 AF1 AF2 AF3 GPIO[16] CAN0TX — — SIUL I/O FlexCAN_0 O — — — — M Tristate 14 23 31 N3 PCR[17] AF0 AF1 AF2 AF3 — — GPIO[17] — — — WKPU[4](4) CAN0RX SIUL — — — WKPU FlexCAN_0 I/O — — — I I S Tristate 15 24 32 N1 PCR[18] AF0 AF1 AF2 AF3 GPIO[18] LIN0TX SDA — SIUL LINFlex_0 I2C_0 — I/O O I/O — M Tristate 64 100 144 B2 PCR[19] AF0 AF1 AF2 AF3 — — GPIO[19] — SCL — WKPU[11](4) LIN0RX SIUL — I2C_0 — WKPU LINFlex_0 I/O — I/O — I I S Tristate 1 1 1 C3 PCR[20] AF0 AF1 AF2 AF3 — GPIO[20] — — — GPI[0] SIUL — — — ADC I — — — I I Tristate 32 50 72 T16 DocID14619 Rev 13 configuration M RESET I/O I/O I/O — I Function SIUL DSPI_0 DSPI_0 — SIUL Alternate PCR[14] GPIO[14] SCK_0 CS0_0 — EIRQ[4] function(1) LBGA208(3) PB[4] LQFP144 PB[3] LQFP100 PB[2] LQFP64 PB[1] Pad type PB[0] I/O direction(2) PA[15] Peripheral PA[14] AF0 AF1 AF2 AF3 — PCR Port pin Pin number 23/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 6. Functional port pin descriptions (continued) 24/116 LBGA208(3) I Tristate 35 53 75 R16 PCR[22] AF0 AF1 AF2 AF3 — GPIO[22] — — — GPI[2] SIUL — — — ADC I — — — I I Tristate 36 54 76 P15 PCR[23] AF0 AF1 AF2 AF3 — GPIO[23] — — — GPI[3] SIUL — — — ADC I — — — I I Tristate 37 55 77 P16 PCR[24] AF0 AF1 AF2 AF3 — — GPIO[24] — — — ANS[0] OSC32K_XTAL(7) SIUL — — — ADC SXOSC I — — — I I/O I Tristate 30 39 53 R9 PCR[25] AF0 AF1 AF2 AF3 — — SIUL — — — ADC SXOSC I — — — I I/O I Tristate 29 38 52 T9 SIUL — — — ADC WKPU I/O — — — I I J Tristate 31 40 54 P9 PCR[26] AF0 AF1 AF2 AF3 — — Function GPIO[25] — — — ANS[1] OSC32K_EXTAL( 7) GPIO[26] — — — ANS[2] WKPU[8](4) DocID14619 Rev 13 configuration I — — — I RESET SIUL — — — ADC Alternate PCR[21] GPIO[21] — — — GPI[1] function(1) LQFP144 PB[10] LQFP100 PB[9] LQFP64 PB[8] Pad type PB[7] I/O direction(2) PB[6] Peripheral PB[5] AF0 AF1 AF2 AF3 — PCR Port pin Pin number SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) LQFP64 LQFP100 LQFP144 LBGA208(3) 38 59 81 N13 PCR[28] AF0 AF1 AF2 AF3 — GPIO[28] E0UC[4] — CS1_0 ANX[0] SIUL eMIOS_0 — DSPI_0 ADC I/O I/O — O I J Tristate 39 61 83 M16 PCR[29] AF0 AF1 AF2 AF3 — GPIO[29] E0UC[5] — CS2_0 ANX[1] SIUL eMIOS_0 — DSPI_0 ADC I/O I/O — O I J Tristate 40 63 85 M13 PCR[30] AF0 AF1 AF2 AF3 — GPIO[30] E0UC[6] — CS3_0 ANX[2] SIUL eMIOS_0 — DSPI_0 ADC I/O I/O — O I J Tristate 41 65 87 L16 PCR[31] AF0 AF1 AF2 AF3 — GPIO[31] E0UC[7] — CS4_0 ANX[3] SIUL eMIOS_0 — DSPI_0 ADC I/O I/O — O I J Tristate 42 67 89 L13 PC[0](9) PCR[32] AF0 AF1 AF2 AF3 GPIO[32] — TDI — SIUL — JTAGC — I/O — I — M Input, weak pull-up 59 87 126 A8 PC[1](9) PCR[33] AF0 AF1 AF2 AF3 GPIO[33] — TDO(10) — SIUL — JTAGC — I/O — O — M Tristate 54 82 121 C9 PB[12] PB[13] PB[14] PB[15] DocID14619 Rev 13 configuration Pad type Tristate (8) RESET I/O direction(2) J PB[11] Function I/O I/O — I/O I Alternate SIUL eMIOS_0 — DSPI_0 ADC function(1) GPIO[27] E0UC[3] — CS0_0 ANS[3] PCR PCR[27] AF0 AF1 AF2 AF3 — Port pin Peripheral Pin number 25/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 6. Functional port pin descriptions (continued) 26/116 78 117 A11 PCR[35] AF0 AF1 AF2 AF3 — — — GPIO[35] CS0_1 MA[0] — CAN1RX CAN4RX(11) EIRQ[6] SIUL I/O DSPI_1 I/O ADC O — — FlexCAN_1 I FlexCAN_4 I SIUL I S Tristate 49 77 116 B11 PCR[36] AF0 AF1 AF2 AF3 — — GPIO[36] — — — SIN_1 CAN3RX(11) SIUL — — — DSPI_1 FlexCAN_3 I/O — — — I I M Tristate 62 92 131 B7 PCR[37] AF0 AF1 AF2 AF3 — GPIO[37] SOUT_1 CAN3TX(11) — EIRQ[7] SIUL I/O DSPI1 O FlexCAN_3 O — — SIUL I M Tristate 61 91 130 A7 PCR[38] AF0 AF1 AF2 AF3 GPIO[38] LIN1TX — — SIUL LINFlex_1 — — I/O O — — S Tristate 16 25 36 R2 PCR[39] AF0 AF1 AF2 AF3 — — GPIO[39] — — — LIN1RX WKPU[12](4) SIUL — — — LINFlex_1 WKPU I/O — — — I I S Tristate 17 26 37 P3 DocID14619 Rev 13 configuration 50 RESET Tristate Peripheral M Function SIUL I/O DSPI_1 I/O FlexCAN_4 O — — SIUL I Alternate PCR[34] GPIO[34] SCK_1 CAN4TX(11) — EIRQ[5] function(1) LBGA208(3) PC[7] LQFP144 PC[6] LQFP100 PC[5] LQFP64 PC[4] Pad type PC[3] I/O direction(2) PC[2] AF0 AF1 AF2 AF3 — PCR Port pin Pin number SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) Tristate 63 99 143 A1 PCR[41] AF0 AF1 AF2 AF3 — — GPIO[41] — — — LIN2RX WKPU[13](4) SIUL — — — LINFlex_2 WKPU I/O — — — I I S Tristate 2 2 2 B1 PCR[42] AF0 AF1 AF2 AF3 GPIO[42] CAN1TX CAN4TX(11) MA[1] SIUL I/O FlexCAN_1 O FlexCAN_4 O ADC O M Tristate 13 22 28 M3 PCR[43] AF0 AF1 AF2 AF3 — — — GPIO[43] — — — CAN1RX CAN4RX(11) WKPU[5](4) SIUL — — — FlexCAN_1 FlexCAN_4 WKPU I/O — — — I I I S Tristate — 21 27 M4 PCR[44] AF0 AF1 AF2 AF3 — GPIO[44] E0UC[12] — — SIN_2 SIUL eMIOS_0 — — DSPI_2 I/O I/O — — I M Tristate — 97 141 B4 PCR[45] AF0 AF1 AF2 AF3 GPIO[45] E0UC[13] SOUT_2 — SIUL eMIOS_0 DSPI_2 — I/O I/O O — S Tristate — 98 142 A2 PCR[46] AF0 AF1 AF2 AF3 — GPIO[46] E0UC[14] SCK_2 — EIRQ[8] SIUL eMIOS_0 DSPI_2 — SIUL I/O I/O I/O — I S Tristate — 3 3 C1 DocID14619 Rev 13 configuration S RESET I/O O — — Function SIUL LINFlex_2 — — Alternate PCR[40] GPIO[40] LIN2TX — — function(1) LBGA208(3) PC[14] LQFP144 PC[13] LQFP100 PC[12] LQFP64 PC[11] Pad type PC[10] I/O direction(2) PC[9] Peripheral PC[8] AF0 AF1 AF2 AF3 PCR Port pin Pin number 27/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 6. Functional port pin descriptions (continued) 28/116 Tristate — 4 4 D3 PCR[48] AF0 AF1 AF2 AF3 — GPIO[48] — — — GPI[4] SIUL — — — ADC I — — — I I Tristate — 41 63 P12 PCR[49] AF0 AF1 AF2 AF3 — GPIO[49] — — — GPI[5] SIUL — — — ADC I — — — I I Tristate — 42 64 T12 PCR[50] AF0 AF1 AF2 AF3 — GPIO[50] — — — GPI[6] SIUL — — — ADC I — — — I I Tristate — 43 65 R12 PCR[51] AF0 AF1 AF2 AF3 — GPIO[51] — — — GPI[7] SIUL — — — ADC I — — — I I Tristate — 44 66 P13 PCR[52] AF0 AF1 AF2 AF3 — GPIO[52] — — — GPI[8] SIUL — — — ADC I — — — I I Tristate — 45 67 R13 PCR[53] AF0 AF1 AF2 AF3 — GPIO[53] — — — GPI[9] SIUL — — — ADC I — — — I I Tristate — 46 68 T13 DocID14619 Rev 13 configuration M RESET I/O I/O I/O — Function SIUL eMIOS_0 DSPI_2 — Alternate PCR[47] GPIO[47] E0UC[15] CS0_2 — function(1) LBGA208(3) PD[5] LQFP144 PD[4] LQFP100 PD[3] LQFP64 PD[2] Pad type PD[1] I/O direction(2) PD[0] Peripheral PC[15] AF0 AF1 AF2 AF3 PCR Port pin Pin number SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) 8) Tristate — 47 69 T14 PCR[55] AF0 AF1 AF2 AF3 — GPIO[55] — — — GPI[11] SIUL — — — ADC I — — — I I Tristate — 48 70 R14 PCR[56] AF0 AF1 AF2 AF3 — GPIO[56] — — — GPI[12] SIUL — — — ADC I — — — I I Tristate — 49 71 T15 PCR[57] AF0 AF1 AF2 AF3 — GPIO[57] — — — GPI[13] SIUL — — — ADC I — — — I I Tristate — 56 78 N15 PCR[58] AF0 AF1 AF2 AF3 — GPIO[58] — — — GPI[14] SIUL — — — ADC I — — — I I Tristate — 57 79 N14 PCR[59] AF0 AF1 AF2 AF3 — GPIO[59] — — — GPI[15] SIUL — — — ADC I — — — I I Tristate — 58 80 N16 PCR[60] AF0 AF1 AF2 AF3 — GPIO[60] CS5_0 E0UC[24] — ANS[4] SIUL DSPI_0 eMIOS_0 — ADC I/O O I/O — I J Tristate — 60 82 M15 DocID14619 Rev 13 configuration I RESET I — — — I Function SIUL — — — ADC Alternate PCR[54] GPIO[54] — — — GPI[10] function(1) LBGA208(3) PD[12]( LQFP144 PD[11] LQFP100 PD[10] LQFP64 PD[9] Pad type PD[8] I/O direction(2) PD[7] Peripheral PD[6] AF0 AF1 AF2 AF3 — PCR Port pin Pin number 29/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 6. Functional port pin descriptions (continued) 30/116 Tristate — 62 84 M14 PCR[62] AF0 AF1 AF2 AF3 — GPIO[62] CS1_1 E0UC[26] — ANS[6] SIUL DSPI_1 eMIOS_0 — ADC I/O O I/O — I J Tristate — 64 86 L15 PCR[63] AF0 AF1 AF2 AF3 — GPIO[63] CS2_1 E0UC[27] — ANS[7] SIUL DSPI_1 eMIOS_0 — ADC I/O O I/O — I J Tristate — 66 88 L14 PCR[64] AF0 AF1 AF2 AF3 — — GPIO[64] E0UC[16] — — CAN5RX(11) WKPU[6](4) SIUL eMIOS_0 — — FlexCAN_5 WKPU I/O I/O — — I I S Tristate — 6 10 F1 PCR[65] AF0 AF1 AF2 AF3 GPIO[65] E0UC[17] CAN5TX(11) — SIUL I/O eMIOS_0 I/O FlexCAN_5 O — — M Tristate — 8 12 F4 PCR[66] AF0 AF1 AF2 AF3 — GPIO[66] E0UC[18] — — SIN_1 SIUL eMIOS_0 — — DSPI_1 I/O I/O — — I M Tristate — 89 128 D7 PCR[67] AF0 AF1 AF2 AF3 GPIO[67] E0UC[19] SOUT_1 — SIUL eMIOS_0 DSPI_1 — I/O I/O O — M Tristate — 90 129 C7 DocID14619 Rev 13 configuration J RESET I/O I/O I/O — I Function SIUL DSPI_1 eMIOS_0 — ADC Alternate PCR[61] GPIO[61] CS0_1 E0UC[25] — ANS[5] function(1) LBGA208(3) PE[3] LQFP144 PE[2] LQFP100 PE[1] LQFP64 PE[0] Pad type PD[15] I/O direction(2) PD[14] Peripheral PD[13] AF0 AF1 AF2 AF3 — PCR Port pin Pin number SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) Tristate — 93 132 D6 PCR[69] AF0 AF1 AF2 AF3 GPIO[69] E0UC[21] CS0_1 MA[2] SIUL eMIOS_0 DSPI_1 ADC I/O I/O I/O O M Tristate — 94 133 C6 PCR[70] AF0 AF1 AF2 AF3 GPIO[70] E0UC[22] CS3_0 MA[1] SIUL eMIOS_0 DSPI_0 ADC I/O I/O O O M Tristate — 95 139 B5 PCR[71] AF0 AF1 AF2 AF3 GPIO[71] E0UC[23] CS2_0 MA[0] SIUL eMIOS_0 DSPI_0 ADC I/O I/O O O M Tristate — 96 140 C4 PCR[72] AF0 AF1 AF2 AF3 GPIO[72] CAN2TX(12) E0UC[22] CAN3TX(11) SIUL I/O FlexCAN_2 O eMIOS_0 I/O FlexCAN_3 O M Tristate — 9 13 G2 PCR[73] AF0 AF1 AF2 AF3 — — — GPIO[73] — E0UC[23] — WKPU[7](4) CAN2RX(12) CAN3RX(11) SIUL — eMIOS_0 — WKPU FlexCAN_2 FlexCAN_3 I/O — I/O — I I I S Tristate — 10 14 G1 PCR[74] AF0 AF1 AF2 AF3 — GPIO[74] LIN3TX CS3_1 — EIRQ[10] SIUL LINFlex_3 DSPI_1 — SIUL I/O O O — I S Tristate — 11 15 G3 DocID14619 Rev 13 configuration M RESET I/O I/O I/O — I Function SIUL eMIOS_0 DSPI_1 — SIUL Alternate PCR[68] GPIO[68] E0UC[20] SCK_1 — EIRQ[9] function(1) LBGA208(3) PE[10] LQFP144 PE[9] LQFP100 PE[8] LQFP64 PE[7] Pad type PE[6] I/O direction(2) PE[5] Peripheral PE[4] AF0 AF1 AF2 AF3 — PCR Port pin Pin number 31/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 6. Functional port pin descriptions (continued) 32/116 Tristate — 13 17 H2 PCR[76] AF0 AF1 AF2 AF3 — — GPIO[76] — E1UC[19](13) — SIN_2 EIRQ[11] SIUL — eMIOS_1 — DSPI_2 SIUL I/O — I/O — I I S Tristate — 76 109 C14 PCR[77] AF0 AF1 AF2 AF3 GPIO[77] SOUT2 E1UC[20] — SIUL DSPI_2 eMIOS_1 — I/O O I/O — S Tristate — — 103 D15 PCR[78] AF0 AF1 AF2 AF3 — GPIO[78] SCK_2 E1UC[21] — EIRQ[12] SIUL DSPI_2 eMIOS_1 — SIUL I/O I/O I/O — I S Tristate — — 112 C13 PCR[79] AF0 AF1 AF2 AF3 GPIO[79] CS0_2 E1UC[22] — SIUL DSPI_2 eMIOS_1 — I/O I/O I/O — M Tristate — — 113 A13 PCR[80] AF0 AF1 AF2 AF3 — GPIO[80] E0UC[10] CS3_1 — ANS[8] SIUL eMIOS_0 DSPI_1 — ADC I/O I/O O — I J Tristate — — 55 N10 PCR[81] AF0 AF1 AF2 AF3 — GPIO[81] E0UC[11] CS4_1 — ANS[9] SIUL eMIOS_0 DSPI_1 — I I/O I/O O — I J Tristate — — 56 P10 DocID14619 Rev 13 configuration S RESET I/O — O — I I Function SIUL — DSPI_1 — LINFlex_3 WKPU Alternate PCR[75] GPIO[75] — CS4_1 — LIN3RX WKPU[14](4) function(1) LBGA208(3) PF[1] LQFP144 PF[0] LQFP100 PE[15] LQFP64 PE[14] Pad type PE[13] I/O direction(2) PE[12] Peripheral PE[11] AF0 AF1 AF2 AF3 — — PCR Port pin Pin number SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) Tristate — — 57 T10 PCR[83] AF0 AF1 AF2 AF3 — GPIO[83] E0UC[13] CS1_2 — ANS[11] SIUL eMIOS_0 DSPI_2 — ADC I/O I/O O — I J Tristate — — 58 R10 PCR[84] AF0 AF1 AF2 AF3 — GPIO[84] E0UC[14] CS2_2 — ANS[12] SIUL eMIOS_0 DSPI_2 — ADC I/O I/O O — I J Tristate — — 59 N11 PCR[85] AF0 AF1 AF2 AF3 — GPIO[85] E0UC[22] CS3_2 — ANS[13] SIUL eMIOS_0 DSPI_2 — ADC I/O I/O O — I J Tristate — — 60 P11 PCR[86] AF0 AF1 AF2 AF3 — GPIO[86] E0UC[23] — — ANS[14] SIUL eMIOS_0 — — ADC I/O I/O — — I J Tristate — — 61 T11 PCR[87] AF0 AF1 AF2 AF3 — GPIO[87] — — — ANS[15] SIUL — — — ADC I/O — — — I J Tristate — — 62 R11 PCR[88] AF0 AF1 AF2 AF3 GPIO[88] CAN3TX(14) CS4_0 CAN2TX(15) SIUL I/O FlexCAN_3 O DSPI_0 O FlexCAN_2 O M Tristate — — 34 P1 DocID14619 Rev 13 configuration J RESET I/O I/O I/O — I Function SIUL eMIOS_0 DSPI_2 — ADC Alternate PCR[82] GPIO[82] E0UC[12] CS0_2 — ANS[10] function(1) LBGA208(3) PF[8] LQFP144 PF[7] LQFP100 PF[6] LQFP64 PF[5] Pad type PF[4] I/O direction(2) PF[3] Peripheral PF[2] AF0 AF1 AF2 AF3 — PCR Port pin Pin number 33/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 6. Functional port pin descriptions (continued) PF[10] PF[11] PF[12] PF[13] PF[14] PF[15] 34/116 PCR[92] AF0 AF1 AF2 AF3 S Tristate — — 33 N2 configuration SIUL I/O — — DSPI_0 O — — FlexCAN_2 I FlexCAN_3 I RESET LBGA208(3) GPIO[91] — — — WKPU[15](4) LQFP144 PCR[91] AF0 AF1 AF2 AF3 — LQFP100 GPIO[90] — — — LQFP64 PCR[90] AF0 AF1 AF2 AF3 Pad type GPIO[89] — CS5_0 — CAN2RX(15) CAN3RX(14) Peripheral Function Alternate function(1) PCR[89] AF0 AF1 AF2 AF3 — — I/O direction(2) PF[9] PCR Port pin Pin number SIUL — — — I/O — — — M Tristate — — 38 R3 SIUL — — — WKPU I/O — — — I S Tristate — — 39 R4 GPIO[92] E1UC[25] — — SIUL eMIOS_1 — — I/O I/O — — M Tristate — — 35 R1 PCR[93] AF0 AF1 AF2 AF3 — GPIO[93] E1UC[26] — — WKPU[16](4) SIUL eMIOS_1 — — WKPU I/O I/O — — I S Tristate — — 41 T6 PCR[94] AF0 AF1 AF2 AF3 GPIO[94] CAN4TX(11) E1UC[27] CAN1TX SIUL I/O FlexCAN_4 O eMIOS_1 I/O FlexCAN_4 O M Tristate — — 102 D14 PCR[95] AF0 AF1 AF2 AF3 — — — GPIO[95] — — — CAN1RX CAN4RX(11) EIRQ[13] SIUL — — — FlexCAN_1 FlexCAN_4 SIUL S Tristate — — 101 E15 I/O — — — I I I DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) LQFP64 LQFP100 LQFP144 LBGA208(3) 98 E14 PCR[97] AF0 AF1 AF2 AF3 — — GPIO[97] — E1UC[24] — CAN5RX(11) EIRQ[14] SIUL — eMIOS_1 — FlexCAN_5 SIUL I/O — I/O — I I S Tristate — — 97 E13 PCR[98] AF0 AF1 AF2 AF3 GPIO[98] E1UC[11] — — SIUL eMIOS_1 — — I/O I/O — — M Tristate — — 8 E4 PG[3] PCR[99] AF0 AF1 AF2 AF3 — GPIO[99] E1UC[12] — — WKPU[17](4) SIUL eMIOS_1 — — WKPU I/O I/O — — I S Tristate — — 7 E3 PG[4] AF0 AF1 PCR[100] AF2 AF3 GPIO[100] E1UC[13] — — SIUL eMIOS_1 — — I/O I/O — — M Tristate — — 6 E1 PG[5] AF0 AF1 PCR[101] AF2 AF3 — GPIO[101] E1UC[14] — — WKPU[18](4) SIUL eMIOS_1 — — WKPU I/O I/O — — I S Tristate — — 5 E2 PG[6] AF0 AF1 PCR[102] AF2 AF3 GPIO[102] E1UC[15] — — SIUL eMIOS_1 — — I/O I/O — — M Tristate — — 30 M2 PG[1] PG[2] DocID14619 Rev 13 configuration — RESET Pad type — Peripheral Tristate Function M PG[0] Alternate SIUL I/O FlexCAN_5 O eMIOS_1 I/O — — function(1) GPIO[96] CAN5TX(11) E1UC[23] — PCR PCR[96] AF0 AF1 AF2 AF3 Port pin I/O direction(2) Pin number 35/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 6. Functional port pin descriptions (continued) LQFP64 LQFP100 LQFP144 LBGA208(3) — — 29 M1 PG[8] AF0 AF1 PCR[104] AF2 AF3 — GPIO[104] E1UC[17] — CS0_2 EIRQ[15] SIUL eMIOS_1 — DSPI_2 SIUL I/O I/O — I/O I S Tristate — — 26 L2 PG[9] AF0 AF1 PCR[105] AF2 AF3 GPIO[105] E1UC[18] — SCK_2 SIUL eMIOS_1 — DSPI_2 I/O I/O — I/O S Tristate — — 25 L1 PG[10] AF0 AF1 PCR[106] AF2 AF3 GPIO[106] E0UC[24] — — SIUL eMIOS_0 — — I/O I/O — — S Tristate — — 114 D13 PG[11] AF0 AF1 PCR[107] AF2 AF3 GPIO[107] E0UC[25] — — SIUL eMIOS_0 — — I/O I/O — — M Tristate — — 115 B12 PG[12] AF0 AF1 PCR[108] AF2 AF3 GPIO[108] E0UC[26] — — SIUL eMIOS_0 — — I/O I/O — — M Tristate — — 92 K14 PG[13] AF0 AF1 PCR[109] AF2 AF3 GPIO[109] E0UC[27] — — SIUL eMIOS_0 — — I/O I/O — — M Tristate — — 91 K16 PG[14] AF0 AF1 PCR[110] AF2 AF3 GPIO[110] E1UC[0] — — SIUL eMIOS_1 — — I/O I/O — — S Tristate — — 110 B14 36/116 DocID14619 Rev 13 configuration Pad type Tristate RESET I/O direction(2) M Function I/O I/O — — Alternate SIUL eMIOS_1 — — function(1) GPIO[103] E1UC[16] — — PCR PG[7] AF0 AF1 PCR[103] AF2 AF3 Port pin Peripheral Pin number SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 6. Functional port pin descriptions (continued) LQFP64 LQFP100 LQFP144 LBGA208(3) — — 111 B13 PH[0] AF0 AF1 PCR[112] AF2 AF3 — GPIO[112] E1UC[2] — — SIN1 SIUL eMIOS_1 — — DSPI_1 I/O I/O — — I M Tristate — — 93 F13 PH[1] AF0 AF1 PCR[113] AF2 AF3 GPIO[113] E1UC[3] SOUT1 — SIUL eMIOS_1 DSPI_1 — I/O I/O O — M Tristate — — 94 F14 PH[2] AF0 AF1 PCR[114] AF2 AF3 GPIO[114] E1UC[4] SCK_1 — SIUL eMIOS_1 DSPI_1 — I/O I/O I/O — M Tristate — — 95 F16 PH[3] AF0 AF1 PCR[115] AF2 AF3 GPIO[115] E1UC[5] CS0_1 — SIUL eMIOS_1 DSPI_1 — I/O I/O I/O — M Tristate — — 96 F15 PH[4] AF0 AF1 PCR[116] AF2 AF3 GPIO[116] E1UC[6] — — SIUL eMIOS_1 — — I/O I/O — — M Tristate — — 134 A6 PH[5] AF0 AF1 PCR[117] AF2 AF3 GPIO[117] E1UC[7] — — SIUL eMIOS_1 — — I/O I/O — — S Tristate — — 135 B6 PH[6] AF0 AF1 PCR[118] AF2 AF3 GPIO[118] E1UC[8] — MA[2] SIUL eMIOS_1 — ADC I/O I/O — O M Tristate — — 136 D5 DocID14619 Rev 13 configuration Pad type Tristate RESET I/O direction(2) M Function I/O I/O — — Alternate SIUL eMIOS_1 — — function(1) GPIO[111] E1UC[1] — — PCR PG[15] AF0 AF1 PCR[111] AF2 AF3 Port pin Peripheral Pin number 37/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 6. Functional port pin descriptions (continued) LQFP64 LQFP100 LQFP144 LBGA208(3) Tristate — — 137 C5 PH[8] AF0 AF1 PCR[120] AF2 AF3 GPIO[120] E1UC[10] CS2_2 MA[0] SIUL eMIOS_1 DSPI_2 ADC I/O I/O O O M Tristate — — 138 A5 PH[9](9) PCR[121] PH[10]( 9) PCR[122] Function configuration Pad type M RESET I/O direction(2) I/O I/O O O Alternate SIUL eMIOS_1 DSPI_2 ADC function(1) GPIO[119] E1UC[9] CS3_2 MA[1] PCR PH[7] AF0 AF1 PCR[119] AF2 AF3 Port pin Peripheral Pin number AF0 AF1 AF2 AF3 GPIO[121] — TCK — SIUL — JTAGC — I/O — I — S Input, weak pull-up 60 88 127 B8 AF0 AF1 AF2 AF3 GPIO[122] — TMS — SIUL — JTAGC — I/O — I — S Input, weak pull-up 53 81 120 B9 1. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00  AF0; PCR.PA = 01  AF1; PCR.PA = 10  AF2; PCR.PA = 11  AF3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “—”. 2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside the SIUL module. 3. LBGA208 available only as development package for Nexus2+ 4. All WKPU pins also support external interrupt capability. See wakeup unit chapter for further details. 5. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored. 6. “Not applicable” because these functions are available only while the device is booting. Refer to BAM chapter of the reference manual for details. 7. Value of PCR.IBE bit must be 0 8. Be aware that this pad is used on the SPC560B64L3 and SPC560B64L5 to provide VDD_HV_ADC and VSS_HV_ADC1. Therefore, you should be careful in ensuring compatibility between SPC560B40x/50x and SPC560C40x/50x and SPC560B64. 9. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO. PC[0:1] are available as JTAG pins (TDI and TDO respectively). PH[9:10] are available as JTAG pins (TCK and TMS respectively). If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1-2001. 10. The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in STANDBY mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad is configured as an input. When no debugger is connected the TDO pad is floating causing additional current consumption. To avoid the extra consumption TDO must be connected. An external pull-up resistor in the range of 47–100 k should be added between the TDO pin and VDD_HV. Only in case the TDO pin is used as application pin and a pull-up cannot be used then a pull-down resistor with the same value should be used between TDO pin and GND instead. 38/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions 11. Available only on SPC560Cx versions and SPC560B50B2 devices 12. Not available on SPC560B40L3 and SPC560B40L5 devices 13. Not available in 100 LQFP package 14. Available only on SPC560B50B2 devices 15. Not available on SPC560B44L3 devices 3.7 Nexus 2+ pins In the LBGA208 package, eight additional debug pins are available (see Table 7). Table 7. Nexus 2+ pin descriptions Pin number Debug pin Function I/O direction MCKO Message clock out O F MDO0 Message data out 0 O MDO1 Message data out 1 MDO2 Pad type Function after reset LQFP 100 LQFP 144 LBGA 208(1) — — — T4 M — — — H15 O M — — — H16 Message data out 2 O M — — — H14 MDO3 Message data out 3 O M — — — H13 EVTI Event in I M Pull-up — — K1 EVTO Event out O M — — — L4 MSEO Message start/end out O M — — — G16 1. LBGA208 available only as development package for Nexus2+. 3.8 Electrical characteristics 3.9 Introduction This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid applying any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column. DocID14619 Rev 13 39/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column. Caution: All LQFP64 information is indicative and must be confirmed during silicon validation. 3.10 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 8 are used and the parameters are tagged accordingly in the tables where appropriate. Table 8. Parameter classifications Classification tag Tag description P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. Note: The classification is shown in the column labeled “C” in the parameter tables where appropriate. 3.11 NVUSRO register Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the device configuration, namely electrical parameters such as high voltage supply and oscillator margin, as well as digital functionality (watchdog enable/disable after reset). For a detailed description of the NVUSRO register, please refer to the device reference manual. 3.11.1 NVUSRO[PAD3V5V] field description The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 9 shows how NVUSRO[PAD3V5V] controls the device configuration. Table 9. PAD3V5V field description Value (1) Description 0 High voltage supply is 5.0 V 1 High voltage supply is 3.3 V 1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash. 40/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x 3.11.2 Package pinouts and signal descriptions NVUSRO[OSCILLATOR_MARGIN] field description The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. Table 10 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration. Table 10. OSCILLATOR_MARGIN field description Value (1) Description 0 Low consumption configuration (4 MHz/8 MHz) 1 High margin configuration (4 MHz/16 MHz) 1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash. 3.11.3 NVUSRO[WATCHDOG_EN] field description The watchdog enable/disable configuration after reset is dependent on the WATCHDOG_EN bit value. Table 11 shows how NVUSRO[WATCHDOG_EN] controls the device configuration. Table 11. WATCHDOG_EN field description Value(1) Description 0 Disable after reset 1 Enable after reset 1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash. 3.12 Absolute maximum ratings Table 12. Absolute maximum ratings Value Symbol Parameter VSS SR Digital ground on VSS_HV pins VDD SR Conditions Voltage on VDD_HV pins with respect to ground (VSS) VSS_LV Voltage on VSS_LV (low voltage digital SR supply) pins with respect to ground (VSS) VDD_BV SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) Voltage on VSS_HV_ADC (ADC VSS_ADC SR reference) pin with respect to ground (VSS) VDD_ADC SR Unit Min Max — 0 0 V — 0.3 6.0 V — VSS0.1 VSS+0.1 V — 0.3 6.0 0.3 VDD+0.3 VSS0.1 VSS+0.1 0.3 6.0 VDD 0.3 VDD+0.3 Relative to VDD — — Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) Relative to V DD DocID14619 Rev 13 V V V 41/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 12. Absolute maximum ratings (continued) Value Symbol Parameter Conditions Unit Min Max — Voltage on any GPIO pin with respect to ground (VSS) Relative to VDD 0.3 6.0 — VDD+0.3 VIN SR IINJPAD SR Injected input current on any pin during overload condition — 10 10 IINJSUM SR Absolute sum of all injected input currents during overload condition — 50 50 — 70 — 64 — — 150 mA — 55 150 °C V mA VDD = 5.0 V ± 10%, Sum of all the static I/O current within a PAD3V5V = 0 IAVGSEG SR supply segment V = 3.3 V ± 10%, mA DD PAD3V5V = 1 ICORELV SR Low voltage static current sink through VDD_BV TSTORAGE SR Storage temperature Note: Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values. 3.13 Recommended operating conditions Table 13. Recommended operating conditions (3.3 V) Value Symbol VSS Parameter SR Digital ground on VSS_HV pins Conditions Unit Min Max — 0 0 V VDD(1) SR Voltage on VDD_HV pins with respect to ground (VSS) — 3.0 3.6 V VSS_LV(2) SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) — VSS0.1 VSS+0.1 V VDD_BV(3) Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) — 3.0 3.6 SR Relative to VDD VDD0.1 VDD+0.1 VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) — VSS0.1 VSS+0.1 VDD_ADC(4) Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) — 3.0(5) 3.6 SR Relative to VDD VDD0.1 VDD+0.1 42/116 DocID14619 Rev 13 V V V SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 13. Recommended operating conditions (3.3 V) (continued) Value Symbol Parameter Conditions — Voltage on any GPIO pin with respect to ground (VSS) Relative to VDD Unit Min Max VSS0.1 — — VDD+0.1 VIN SR IINJPAD SR Injected input current on any pin during overload condition — 5 5 IINJSUM SR Absolute sum of all injected input currents during overload condition — 50 50 — 3.0(7) 250 x 103 (0.25 [V/µs]) V mA TVDD SR VDD slope to ensure correct power up(6) V/s 1. 100 nF capacitance needs to be provided between each VDD/VSS pair 2. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 3. 400 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 4. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. 5. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is reset. 6. Guaranteed by device validation. 7. Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH). Table 14. Recommended operating conditions (5.0 V) Value Symbol VSS Parameter SR Digital ground on VSS_HV pins Voltage on VDD_HV pins with respect to ground (VSS) VDD(1) SR VSS_LV(3) SR VDD_BV(4) Voltage on VDD_BV pin (regulator supply) SR with respect to ground (VSS) VSS_ADC SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS Conditions Max 0 0 4.5 5.5 3.0 5.5 — VSS0.1 VSS+0.1 — 4.5 5.5 Voltage drop(2) 3.0 5.5 Relative to VDD VDD0.1 VDD+0.1 — VSS0.1 VSS+0.1 4.5 5.5 3.0 5.5 Relative to VDD VDD0.1 VDD+0.1 — VSS0.1 — Relative to VDD — VDD+0.1 — — (2) Voltage drop — VDD_ADC(5) VIN Voltage on VDD_HV_ADC pin (ADC SR reference) with respect to ground (VSS) SR Voltage on any GPIO pin with respect to ground (VSS) DocID14619 Rev 13 Unit Min (2) Voltage drop V V V V V V V 43/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 14. Recommended operating conditions (5.0 V) (continued) Value Symbol Parameter Conditions Injected input current on any pin during overload condition IINJPAD SR IINJSUM Absolute sum of all injected input currents SR during overload condition Unit — Min Max 5 5 mA TVDD SR VDD slope to ensure correct power up (6) 50 — — 3.0 (7) 50 250 x 103 (0.25 [V/µs]) V/s 1. 100 nF capacitance needs to be provided between each VDD/VSS pair. 2. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 3. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 4. 100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 5. 1 µF (electrolithic/tantalum) + 47 nF (ceramic) capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Another ceramic cap of 10 nF with low inductance package can be added. 6. Guaranteed by device validation. 7. Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH). Note: RAM data retention is guaranteed with VDD_LV not below 1.08 V. 3.14 Thermal characteristics 3.14.1 Package thermal characteristics Table 15. LQFP thermal characteristics(1) Symbol C Conditions(2) Parameter Single-layer board - 1s RJA CC D Thermal resistance, junction-toambient natural convection(3) Single-layer board - 1s CC D Thermal resistance, junction-toboard(4) 64 60 100 64 144 64 64 42 100 51 144 49 64 24 100 36 144 37 64 24 100 34 144 35 Unit °C/W Four-layer board - 2s2p 44/116 Value °C/W Four-layer board - 2s2p RJB Pin count DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 15. LQFP thermal characteristics(1) (continued) Symbol C Conditions(2) Parameter Single-layer board - 1s RJC CC D Thermal resistance, junction-tocase(5) Single-layer board - 1s CC D Junction-to-board thermal characterization parameter, natural convection Single-layer board - 1s CC D 64 11 100 22 144 22 64 11 100 22 144 22 64 TBD 100 33 144 34 64 TBD 100 34 144 35 64 TBD 100 9 144 10 64 TBD 100 9 144 10 Unit °C/W Four-layer board - 2s2p JC Value °C/W Four-layer board - 2s2p JB Pin count Junction-to-case thermal characterization parameter, natural convection °C/W Four-layer board - 2s2p 1. Thermal characteristics are based on simulation. 2. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C 3. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 4. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 5. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 3.14.2 Power considerations The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1: Equation 1TJ = TA + (PD x RJA) Where: TA is the ambient temperature in °C. RJA is the package junction-to-ambient thermal resistance, in °C/W. PD is the sum of PINT and PI/O (PD = PINT + PI/O). PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power. PI/O represents the power dissipation on input and output pins; user determined. DocID14619 Rev 13 45/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: Equation 2 PD = K / (TJ + 273 °C) Therefore, solving equations Equation 1 and Equation 2: Equation 3 K = PD x (TA + 273 °C) + RJA x PD2 Where: K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations Equation 1 and Equation 2 iteratively for any value of TA. 3.15 I/O pad electrical characteristics 3.15.1 I/O pad types The device provides four main I/O pad types depending on the associated alternate functions:  Slow pads—These pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission.  Medium pads—These pads provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission.  Fast pads—These pads provide maximum speed. There are used for improved Nexus debugging capability.  Input only pads—These pads are associated to ADC channels and the external 32 kHz crystal oscillator (SXOSC) providing low input leakage. Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance. 3.15.2 I/O input DC characteristics Table 16 provides input DC electrical characteristics as described in Figure 6. 46/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Figure 6. I/O input DC electrical characteristics definition VIN VDD VIH VHYS VIL PDIx = ‘1’ (GPDI register of SIUL) PDIx = ‘0’ Table 16. I/O input DC electrical characteristics Symbol C Value Conditions(1) Parameter Unit Min Typ Max VIH SR P Input high level CMOS (Schmitt Trigger) — 0.65VDD — VDD+0.4 VIL SR P Input low level CMOS (Schmitt Trigger) — 0.4 — 0.35VDD VHYS CC C Input hysteresis CMOS (Schmitt Trigger) — 0.1VDD — — TA = 40 °C — 2 200 TA = 25 °C — 2 200 TA = 85 °C — 5 300 TA = 105 °C — 12 500 TA = 125 °C — 70 1000 D D ILKG CC D No injection on adjacent pin Digital input leakage D P WFI(2) V nA SR P Wakeup input filtered pulse — — — 40 ns WNFI(2) SR P Wakeup input not filtered pulse — 1000 — — ns 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 2. In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage. DocID14619 Rev 13 47/116 115 Package pinouts and signal descriptions 3.15.3 SPC560B40x/50x, SPC560C40x/50x I/O output DC characteristics The following tables provide DC characteristics for bidirectional pads:  Table 17 provides weak pull figures. Both pull-up and pull-down resistances are supported.  Table 18 provides output driver characteristics for I/O pads when in SLOW configuration.  Table 19 provides output driver characteristics for I/O pads when in MEDIUM configuration.  Table 20 provides output driver characteristics for I/O pads when in FAST configuration. Table 17. I/O pull-up/pull-down DC electrical characteristics Symbol C Parameter C Weak pull-up current C C absolute value P P C Weak pull-down current |IWPD| C C absolute value P Unit Min Typ Max PAD3V5V = 0 10 — 150 VIN = VIL, VDD = 5.0 V ± 10% PAD3V5V = 1(2) 10 — 250 VIN = VIL, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150 PAD3V5V = 0 10 — 150 PAD3V5V = 1 10 — 250 VIN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150 P |IWPU| Value Conditions(1) VIN = VIH, VDD = 5.0 V ± 10% µA µA 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. 2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 18. SLOW configuration output buffer electrical characteristics Symbol C P VOH CC C C 48/116 Parameter Value Conditions(1) Unit Min Typ Max 0.8VDD — — 0.8VDD — — IOH = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD0.8 (recommended) — — IOH = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) IOH = 2 mA, Output high level Push Pull VDD = 5.0 V ± 10%, PAD3V5V = SLOW configuration 1(2) DocID14619 Rev 13 V SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 18. SLOW configuration output buffer electrical characteristics (continued) Symbol C Parameter IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) P VOL CC C IOL = 2 mA, Output low level Push Pull VDD = 5.0 V ± 10%, PAD3V5V = SLOW configuration 1(2) IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) C Value Conditions(1) Unit Min Typ Max — — 0.1VDD — — 0.1VDD — — 0.5 V 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 19. MEDIUM configuration output buffer electrical characteristics Symbol C Parameter Value Conditions(1) Unit Min Typ Max C IOH = 3.8 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD — — P IOH = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) 0.8VDD — — Output high level I = 1 mA, Push Pull OH 0.8VDD MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 1(2) — — VOH CC C V C IOH = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) VDD0.8 — — C IOH = 100 µA, VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD — — C IOL = 3.8 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.2VDD P IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) — — 0.1VDD — — 0.1VDD VOL CC C Output low level I = 1 mA, Push Pull OL MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 1(2) C IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) — — 0.5 C IOL = 100 µA, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD V 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified DocID14619 Rev 13 49/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x 2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 20. FAST configuration output buffer electrical characteristics Symbol C Value Conditions(1) Parameter Unit Min Typ Max 0.8VDD — — I = 7mA, 0.8VDD Push Pull OH VDD = 5.0 V ± 10%, PAD3V5V = 1(2) — — C IOH = 11mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) VDD0.8 — — P IOL = 14mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) — — 0.1VDD — — 0.1VDD — — 0.5 IOH = 14mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) P VOH CC C VOL CC C Output high level FAST configuration Output low level FAST configuration I = 7mA, Push Pull OL VDD = 5.0 V ± 10%, PAD3V5V = 1(2) IOL = 11mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) C V V 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. 3.15.4 Output pin transition times Table 21. Output pin transition times Symbol C Value Conditions(1) Parameter Unit Min Typ Max ttr D CL = 25 pF T CL = 50 pF D Output transition time output CC pin(2) D SLOW configuration 50/116 — — 50 — — 100 CL = 100 pF — — 125 CL = 25 pF — — 50 — — 100 — — 125 VDD = 5.0 V ± 10%, PAD3V5V = 0 ns T CL = 50 pF D CL = 100 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 21. Output pin transition times (continued) Symbol C Value Conditions(1) Parameter Unit Min Typ Max ttr D CL = 25 pF — — 10 T CL = 50 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 CL = 100 pF — — 20 — — 40 CL = 25 pF — — 12 CL = 50 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 CL = 100 pF — — 25 — — 40 — — 4 — — 6 CL = 100 pF — — 12 CL = 25 pF — — 4 — — 7 — — 12 D Output transition time output CC pin(2) D MEDIUM configuration T D ns CL = 25 pF CL = 50 pF ttr Output transition time output CC D pin(2) FAST configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 ns CL = 50 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100 pF 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 2. CL includes device and package capacitances (CPKG < 5 pF). 3.15.5 I/O pad current specification The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 22. Table 22. I/O supply segment Supply segment Package 1 LBGA208(1) 2 3 4 Equivalent to LQFP144 segment pad distribution pin100–pin122 pin 123–pin19 5 6 MCKO MDOn/MSEO — — LQFP144 pin20–pin49 pin51–pin99 LQFP100 pin16–pin35 pin37–pin69 pin70–pin83 pin 84–pin15 — — LQFP64(2) pin8–pin26 pin28–pin55 pin56–pin7 — — — 1. LBGA208 available only as development package for Nexus2+ 2. All LQFP64 information is indicative and must be confirmed during silicon validation. Table 23 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. DocID14619 Rev 13 51/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 23. I/O consumption Symbol ISWTSLW (2) ISWTMED (2 ) ISWTFST (2) C Value Conditions(1) Parameter Unit Min Typ Max VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 20 VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 16 VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 29 VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 17 VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 110 VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 50 — — 2.3 — — 3.2 CL = 100 pF, 2 MHz — — 6.6 CL = 25 pF, 2 MHz — — 1.6 — — 2.3 — — 4.7 — — 6.6 — — 13.4 CL = 100 pF, 13 MHz — — 18.3 CL = 25 pF, 13 MHz — — 5 — — 8.5 — — 11 — — 22 — — 33 CL = 100 pF, 40 MHz — — 56 CL = 25 pF, 40 MHz — — 14 — — 20 — — 35 — — 70 — — 65 Dynamic I/O current for CC D CL = 25 pF SLOW configuration Dynamic I/O current for CC D CL = 25 pF MEDIUM configuration Dynamic I/O current for CC D CL = 25 pF FAST configuration mA mA mA CL = 25 pF, 2 MHz CL = 25 pF, 4 MHz Root mean square I/O IRMSSLW CC D current for SLOW configuration CL = 25 pF, 4 MHz VDD = 5.0 V ± 10%, PAD3V5V = 0 mA VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100 pF, 2 MHz CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz Root mean square I/O IRMSMED CC D current for MEDIUM configuration CL = 25 pF, 40 MHz VDD = 5.0 V ± 10%, PAD3V5V = 0 mA VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100 pF, 13 MHz CL = 25 pF, 40 MHz CL = 25 pF, 64 MHz Root mean square I/O IRMSFST CC D current for FAST configuration CL = 25 pF, 64 MHz VDD = 5.0 V ± 10%, PAD3V5V = 0 mA VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100 pF, 40 MHz Sum of all the static I/O VDD = 5.0 V ± 10%, PAD3V5V = 0 IAVGSEG SR D current within a supply VDD = 3.3 V ± 10%, PAD3V5V = 1 segment 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to125 °C, unless otherwise specified 2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. Table 24 provides the weight of concurrent switching I/Os. 52/116 DocID14619 Rev 13 mA SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Due to the dynamic current limitations, the sum of the weight of concurrent switching I/Os on a single segment must not exceed 100% to ensure device functionality. Table 24. I/O weight(1) LQFP64(2) LQFP144/LQFP100 Supply segment Pad 100 Weight 3.3 V Weight 5 V Weight 3.3 V SRC(3) = SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 0 LQFP LQFP LQFP 144 Weight 5 V 64 PB[3] 10% — 12% — 10% — 12% — PC[9] 10% — 12% — 10% — 12% — — PC[14] 9% — 11% — — — — — — PC[15] 9% 13% 11% 12% — — — — — — PG[5] 9% — 11% — — — — — — — PG[4] 9% 12% 10% 11% — — — — — — PG[3] 9% — 10% — — — — — — — PG[2] 8% 12% 10% 10% — — — — 3 PA[2] 8% — 9% — 8% — 9% — — PE[0] 8% — 9% — — — — — 3 PA[1] 7% — 9% — 7% — 9% — — PE[1] 7% 10% 8% 9% — — — — — PE[8] 7% 9% 8% 8% — — — — — PE[9] 6% — 7% — — — — — — PE[10] 6% — 7% — — — — — 3 PA[0] 5% 8% 6% 7% 5% 8% 6% 7% — PE[11] 5% — 6% — — — — — 3 4 4 4 4 DocID14619 Rev 13 53/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 24. I/O weight(1) (continued) LQFP64(2) LQFP144/LQFP100 Supply segment Pad Weight 3.3 V Weight 5 V Weight 3.3 V SRC(3) = SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 0 LQFP LQFP LQFP 144 Weight 5 V 100 64 — — PG[9] 9% — 10% — — — — — — — PG[8] 9% — 11% — — — — — — PC[11] 9% — 11% — — — — — 1 PC[10] 9% 13% 11% 12% 9% 13% 11% 12% — — PG[7] 10% 14% 11% 12% — — — — — — PG[6] 10% 14% 12% 12% — — — — PB[0] 10% 14% 12% 12% 10% 14% 12% 12% 1 1 PB[1] 10% — 12% — 10% — 12% — 1 1 — — PF[9] 10% — 12% — — — — — — — PF[8] 10% 15% 12% 13% — — — — — — PF[12] 10% 15% 12% 13% — — — — PC[6] 10% — 12% — 10% — 12% — 1 1 PC[7] 10% — 12% — 10% — 12% — — — PF[10] 10% 14% 12% 12% — — — — — — PF[11] 10% — 11% — — — — — 1 1 PA[15] 9% 12% 10% 11% 9% 12% 10% 11% — — PF[13] 8% — 10% — — — — — PA[14] 8% 11% 9% 10% 8% 11% 9% 10% PA[4] 8% — 9% — 8% — 9% — PA[13] 7% 10% 9% 9% 7% 10% 9% 9% PA[12] 7% — 8% — 7% — 8% — 1 54/116 1 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 24. I/O weight(1) (continued) LQFP64(2) LQFP144/LQFP100 Supply segment Pad 100 2 64 2 Weight 3.3 V Weight 5 V Weight 3.3 V SRC(3) = SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 0 LQFP LQFP LQFP 144 Weight 5 V PB[9] 1% — 1% — 1% — 1% — PB[8] 1% — 1% — 1% — 1% — PB[10] 6% — 7% — 6% — 7% — — — PF[0] 6% — 7% — — — — — — — PF[1] 7% — 8% — — — — — — — PF[2] 7% — 8% — — — — — — — PF[3] 7% — 9% — — — — — — — PF[4] 8% — 9% — — — — — — — PF[5] 8% — 10% — — — — — — — PF[6] 8% — 10% — — — — — — — PF[7] 9% — 10% — — — — — — PD[0] 1% — 1% — — — — — — PD[1] 1% — 1% — — — — — — PD[2] 1% — 1% — — — — — — PD[3] 1% — 1% — — — — — — PD[4] 1% — 1% — — — — — — PD[5] 1% — 1% — — — — — — PD[6] 1% — 1% — — — — — — PD[7] 1% — 1% — — — — — — PD[8] 1% — 1% — — — — — PB[4] 1% — 1% — 1% — 1% — PB[5] 1% — 1% — 1% — 2% — PB[6] 1% — 1% — 1% — 2% — PB[7] 1% — 1% — 1% — 2% — — PD[9] 1% — 1% — — — — — — PD[10] 1% — 1% — — — — — — PD[11] 1% — 1% — — — — — 2 PB[11] 11% — 13% — 17% — 21% — — PD[12] 11% — 13% — — — — — 2 PB[12] 11% — 13% — 18% — 21% — — PD[13] 10% — 12% — — — — — 2 2 2 DocID14619 Rev 13 55/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 24. I/O weight(1) (continued) LQFP64(2) LQFP144/LQFP100 Supply segment Pad 100 Weight 3.3 V Weight 5 V Weight 3.3 V SRC(3) = SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 0 LQFP LQFP LQFP 144 Weight 5 V 64 2 PB[13] 10% — 12% — 18% — 21% — — PD[14] 10% — 12% — — — — — 2 PB[14] 10% — 12% — 18% — 21% — — PD[15] 10% — 11% — — — — — PB[15] 9% — 11% — 18% — 21% — PA[3] 9% — 11% — 18% — 21% — 2 2 — — PG[13] 9% 13% 10% 11% — — — — — — PG[12] 9% 12% 10% 11% — — — — — — PH[0] 5% 8% 6% 7% — — — — — — PH[1] 5% 7% 6% 6% — — — — — — PH[2] 5% 6% 5% 6% — — — — — — PH[3] 4% 6% 5% 5% — — — — — — PG[1] 4% — 4% — — — — — — — PG[0] 3% 4% 4% 4% — — — — — — PF[15] 3% — 4% — — — — — — — PF[14] 4% 5% 5% 5% — — — — — — PE[13] 4% — 5% — — — — — PA[7] 5% — 6% — 16% — 19% — PA[8] 5% — 6% — 16% — 19% — PA[9] 5% — 6% — 15% — 18% — PA[10] 6% — 7% — 15% — 18% — PA[11] 6% — 8% — 14% — 17% — — PE[12] 7% — 8% — — — — — — — PG[14] 7% — 8% — — — — — — — PG[15] 7% 10% 8% 9% — — — — — — PE[14] 7% — 8% — — — — — — — PE[15] 7% 9% 8% 8% — — — — — — PG[10] 6% — 8% — — — — — — — PG[11] 6% 9% 7% 8% — — — — PC[3] 6% — 7% — 7% — 9% — 3 2 PC[2] 6% 8% 7% 7% 6% 9% 8% 8% 2 2 3 3 56/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 24. I/O weight(1) (continued) LQFP64(2) LQFP144/LQFP100 Supply segment Pad 3 100 Weight 3.3 V Weight 5 V Weight 3.3 V SRC(3) = SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 0 LQFP LQFP LQFP 144 Weight 5 V 64 PA[5] 5% 7% 6% 6% 6% 8% 7% 7% PA[6] 5% — 6% — 5% — 6% — PH[10] 4% 6% 5% 5% 5% 7% 6% 6% PC[1] 5% — 5% — 5% — 5% — PC[0] 6% 9% 7% 8% 6% 9% 7% 8% PH[9] 7 7 8 8 7 7 8 8 — PE[2] 7% 10% 9% 9% — — — — — PE[3] 8% 11% 9% 9% — — — — PC[5] 8% 11% 9% 10% 8% 11% 9% 10% PC[4] 8% 12% 10% 10% 8% 12% 10% 10% — PE[4] 8% 12% 10% 11% — — — — — PE[5] 9% 12% 10% 11% — — — — — — PH[4] 9% 13% 11% 11% — — — — — — PH[5] 9% — 11% — — — — — — — PH[6] 9% 13% 11% 12% — — — — — — PH[7] 9% 13% 11% 12% — — — — — — PH[8] 10% 14% 11% 12% — — — — — PE[6] 10% 14% 12% 12% — — — — — PE[7] 10% 14% 12% 12% — — — — — PC[12] 10% 14% 12% 13% — — — — — PC[13] 10% — 12% — — — — — PC[8] 10% — 12% — 10% — 12% — PB[2] 10% 15% 12% 13% 10% 15% 12% 13% 3 2 3 4 3 4 4 3 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to125 °C, unless otherwise specified 2. All LQFP64 information is indicative and must be confirmed during silicon validation. 3. SRC: “Slew Rate Control” bit in SIU_PCR 3.16 RESET electrical characteristics The device implements a dedicated bidirectional RESET pin. DocID14619 Rev 13 57/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Figure 7. Start-up reset requirements VDD VDDMIN RESET VIH VIL device reset forced by RESET device start-up phase Figure 8. Noise filtering on reset signal VRESET hw_rst VDD ‘1’ VIH VIL ‘0’ filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter unknown reset state device under hardware reset WFRST WNFRST Table 25. Reset electrical characteristics Symbol C Parameter Value Conditions(1) Unit Min Typ Max VIH SR P Input High Level CMOS (Schmitt Trigger) — 0.65VDD — VDD+0.4 V VIL SR P Input low Level CMOS (Schmitt Trigger) — 0.4 — 0.35VDD V 58/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 25. Reset electrical characteristics (continued) Symbol VHYS C CC C Parameter VOL CC C Output low level C ttr Output transition time CC D output pin(3) Unit Min Typ Max 0.1VDD — — Push Pull, IOL = 2mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) — — 0.1VDD Push Pull, IOL = 1mA, VDD = 5.0 V ± 10%, PAD3V5V = 1(2) — — 0.1VDD Push Pull, IOL = 1mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) — — 0.5 CL = 25pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 10 CL = 50pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 20 CL = 100pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 40 CL = 25pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 12 CL = 50pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 25 CL = 100pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 40 Input hysteresis CMOS (Schmitt Trigger) P Value Conditions(1) — V V ns WFRST SR P RESET input filtered pulse — — — 40 ns WNFRST SR P RESET input not filtered pulse — 1000 — — ns VDD = 3.3 V ± 10%, PAD3V5V = 1 10 — 150 VDD = 5.0 V ± 10%, PAD3V5V = 0 10 — 150 VDD = 5.0 V ± 10%, PAD3V5V = 1(2) 10 — 250 P Weak pull-up current |IWPU| CC D absolute value P µA 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 2. This transient configuration does not occurs when device is used in the VDD = 3.3 V ± 10% range. 3. CL includes device and package capacitance (CPKG < 5 pF). DocID14619 Rev 13 59/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x 3.17 Power management electrical characteristics 3.17.1 Voltage regulator electrical characteristics The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved: 60/116  HV—High voltage external power supply for voltage regulator module. This must be provided externally through VDD_HV power pin.  BV—High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV power pin. Voltage values should be aligned with VDD.  LV—Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated by the internal voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure noise isolation between critical LV modules within the device: – LV_COR—Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding. – LV_CFLA—Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. – LV_DFLA—Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. – LV_PLL—Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding. DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Figure 9. Voltage regulator capacitance connection CREG2 (LV_COR/LV_CFLA) VDD_HV VSS_LV VDD_BV Voltage Regulator I VSS_LVn VDD_BV CREG1 (LV_COR/LV_DFLA) VDD_LVn CDEC1 (Ballast decoupling) VREF VDD_LV VDD_LV VSS_LV VSS_LV DEVICE DEVICE VDD_LV CREG3 (LV_COR/LV_PLL) VSS_HV VDD_HV CDEC2 (supply/IO decoupling) The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH. Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see Section 3.13: Recommended operating conditions). The internal voltage regulator requires a controlled slew rate of both VDD_HV and VDD_BV as described in Figure 10. DocID14619 Rev 13 61/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Figure 10. VDD_HV and VDD_BV maximum slope VDD_HV VDD_HV(MAX) d VDD dt VPORH(MAX) POWER UP FUNCTIONAL RANGE POWER DOWN When STANDBY mode is used, further constraints are applied to the both VDD_HV and VDD_BV in order to guarantee correct regulator function during STANDBY exit. This is described on Figure 11. STANDBY regulator constraints should normally be guaranteed by implementing equivalent of CSTDBY capacitance on application board (capacitance and ESR typical values), but would actually depend on exact characteristics of application external regulator. Figure 11. VDD_HV and VDD_BV supply constraints during STANDBY mode exit VDD_HV VDD_HV VDD_HV(MAX) d VDD  STDBY  dt VDD(STDBY) VDD(STDBY) VDD_HV(MIN) d VDD  STDBY  dt VDD_LV VDD_LV(NOMINAL) 0V 62/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 26. Voltage regulator electrical characteristics Symbol C CREGn SR — Internal voltage regulator external capacitance RREG SR — Stability capacitor equivalent serial Range: resistance 10 kHz to 20 MHz CDEC1 (2) SR — Decoupling capacitance d VDD dt SR — Maximum slope on VDD SR — Maximum instant variation on VDD during standby exit Maximum slope on VDD during d VDD  STDBY  SR — standby exit dt T VMREG CC Main regulator output voltage P SR — Main regulator current provided to VDD_LV domain IMREGINT CC D Main regulator module current consumption VLPREG CC P Low power regulator output voltage ILPREG SR — Low power regulator current provided to VDD_LV domain D ILPREGINT Low power regulator module current consumption CC — VULPREG CC P Before exiting from reset After trimming IMREG Ultra low power regulator output voltage Unit Min Typ Max 200 — 500 nF — — 0.2 W VDD_BV/VSS_LV pair: 100 (3) VDD_BV = 4.5 V to 5.5 V Decoupling capacitance regulator VDD/VSS pair supply SR — VDD(STDBY)| ballast — VDD_BV/VSS_LV pair: VDD_BV = 3 V to 3.6 V CDEC2 Value Conditions(1) Parameter — 470 (4) 400 nF — 10 100 — nF — — 250 mV/µs — — 30 mV — — 15 mV/µs — 1.32 — V 1.16 1.28 — — — 150 IMREG = 200 mA — — 2 IMREG = 0 mA — — 1 After trimming 1.16 1.28 — V — — 15 mA ILPREG = 15 mA; TA = 55 °C — — 600 ILPREG = 0 mA; TA = 55 °C — 5 — 1.16 1.28 — — — After trimming DocID14619 Rev 13 mA mA µA V 63/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 26. Voltage regulator electrical characteristics (continued) Symbol IULPREG SR — IULPREGINT IDD_BV C Parameter Ultra low power regulator current provided to VDD_LV domain — IULPREG = 5 mA; Ultra low power regulator module TA = 55 °C CC D current consumption IULPREG = 0 mA; TA = 55 °C CC D Value Conditions(1) In-rush average current on VDD_BV during power-up(5) — Unit Min Typ Max — — 5 — — 100 mA µA — 2 — — — 300 (6) mA 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 2. This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical value is in the range of 470 nF. 3. This value is acceptable to guarantee operation from 4.5 V to 5.5 V 4. External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in operating range. 5. In-rush average current is seen only for short time (maximum 20 µs) during power-up and on standby exit. It is dependant on the sum of the CREGn capacitances. 6. The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc. The VDD(STDBY)| and dVDD(STDBY)/dt system requirement can be used to define the component used for the VDD supply generation. The following two examples describe how to calculate capacitance size: Example 1 No regulator (worst case) The VDD(STDBY)| parameter can be seen as the VDD voltage drop through the ESR resistance of the regulator stability capacitor when the IDD_BV current required to load VDD_LV domain during the standby exit. It is thus possible to define the maximum equivalent resistance ESRSTDBY(MAX) of the total capacitance on the VDD supply: ESRSTDBY(MAX) = VDD(STDBY)|/IDD_BV = (30 mV)/(300 mA) = 0.1 (d) The dVDD(STDBY)/dt parameter can be seen as the VDD voltage drop at the capacitance pin (excluding ESR drop) while providing the IDD_BV supply required to load VDD_LV domain during the standby exit. It is thus possible to define the minimum equivalent capacitance CSTDBY(MIN) of the total capacitance on the VDD supply: CSTDBY(MIN) = IDD_BV/dVDD(STDBY)/dt = (300 mA)/(15 mV/µs) = 20µF This configuration is a worst case, with the assumption no regulator is available. Example 2 Simplified regulator The regulator should be able to provide significant amount of the current during the standby exit process. For example, in case of an ideal voltage regulator providing 200 mA current, it is possible to recalculate the equivalent ESRSTDBY(MAX) and CSTDBY(MIN) as follows: d. Based on typical time for standby exit sequence of 20 µs, ESR(MIN) can actually be considered at ~50 kHz. 64/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions ESRSTDBY(MAX) = VDD(STDBY)|/(IDD_BV  200 mA) = (30 mV)/(100 mA) = 0.3  CSTDBY(MIN) = (IDD_BV  200 mA)/dVDD(STDBY)/dt = (300 mA  200 mA)/(15 mV/µs) = 6.7 µF In case optimization is required, CSTDBY(MIN) and ESRSTDBY(MAX) should be calculated based on the regulator characteristics as well as the board VDD plane characteristics. 3.17.2 Low voltage detector electrical characteristics The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well as four low voltage detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied: Note:  POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state (refer to RGM Destructive Event Status (RGM_DES) Register flag F_POR in device reference manual)  LVDHV3 monitors VDD to ensure device reset below minimum functional supply (refer to RGM Destructive Event Status (RGM_DES) Register flag F_LVD27 in device reference manual)  LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range (refer to RGM Functional Event Status (RGM_FES) Register flag F_LVD45 in device reference manual)  LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status (RGM_DES) Register flag F_LVD12_PD1 in device reference manual  LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status (RGM_DES) Register flag F_LVD12_PD0 in device reference manual) When enabled, power domain No. 2 is monitored through LVDLVBKP. Figure 12. Low voltage detector vs reset VDD VLVDHVxH VLVDHVxL RESET Note: Figure 12: Low voltage detector vs reset does not apply to LVDHV5 low voltage detector because LVDHV5 is automatically disabled during reset and it must be enabled by software again. Once the device is forced to reset by LVDHV5, the LVDHV5 is disabled and reset is DocID14619 Rev 13 65/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x released as soon as internal reset sequence is completed regardless of LVDHV5H threshold. Table 27. Low voltage detector electrical characteristics Symbol C VPORUP SR P Supply for functional POR module VPORH CC Value Conditions(1) Parameter Unit — TA = 25 °C, after trimming P Power-on reset threshold T — Min Typ Max 1.0 — 5.5 1.5 — 2.6 1.5 — 2.6 VLVDHV3H CC T LVDHV3 low voltage detector high threshold — — 2.95 VLVDHV3L CC P LVDHV3 low voltage detector low threshold 2.6 — 2.9 VLVDHV5H CC T LVDHV5 low voltage detector high threshold — — 4.5 VLVDHV5L CC P LVDHV5 low voltage detector low threshold 3.8 — 4.4 VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold 1.08 — 1.16 VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold 1.08 — 1.16 V — 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 3.18 Power consumption Table 28 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application. Table 28. Power consumption on VDD_BV and VDD_HV Symbol IDDMAX(2) IDDRUN(4) C CC D Parameter RUN mode maximum average current Typ — 115 Max 140(3) mA fCPU = 8 MHz — 7 — T fCPU = 16 MHz — 18 — fCPU = 32 MHz — 29 — fCPU = 48 MHz — 40 100 fCPU = 64 MHz — 51 125 Slow internal RC oscillator TA = 25 °C (128 kHz) running TA = 125 °C — 8 15 — 14 25 RUN mode typical CC T average current(5) P C 66/116 — Unit Min T P IDDHALT Value Conditions(1) CC P HALT mode current(6) DocID14619 Rev 13 mA mA SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 28. Power consumption on VDD_BV and VDD_HV (continued) Symbol IDDSTOP C Parameter Value Conditions(1) Unit Min Typ Max P TA = 25 °C — 180 700(8) D TA = 55 °C — 500 — — 1 6(8) — 2 9(8) µA D Slow internal RC oscillator TA = 85 °C (128 kHz) running TA = 105 °C P TA = 125 °C — 4.5 12(8) P TA = 25 °C — 30 100 TA = 55 °C Slow internal RC oscillator TA = 85 °C (128 kHz) running TA = 105 °C — 75 — — 180 700 — 315 1000 P TA = 125 °C — 560 1700 T TA = 25 °C — 20 60 TA = 55 °C Slow internal RC oscillator TA = 85 °C (128 kHz) running TA = 105 °C — 45 — — 100 350 — 165 500 TA = 125 °C — 280 900 CC D STOP mode current(7) D STANDBY2 mode IDDSTDBY2 CC D current(9) D D STANDBY1 mode IDDSTDBY1 CC D current(10) D D mA µA µA 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 2. IDDMAX is drawn only from the VDD_BV pin. Running consumption does not include I/Os toggling which is highly dependent on the application. The given value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation ongoing on data flash. Notice that this value can be significantly reduced by application: switch off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible. 3. Higher current may be sinked by device during power-up and standby exit. Please refer to in rush current on Table 26. 4. IDDRUN is drawn only from the VDD_BV pin. RUN current measured with typical application with accesses on both flash and RAM. 5. Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPI as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer reset enabled. 6. Data Flash Power Down. Code Flash in Low Power. SIRC (128 kHz) and FIRC (16 MHz) on. 10 MHz XTAL clock. FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex: instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON (16 channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication). RTC/API ON. PIT ON. STM ON. ADC ON but not conversion except 2 analog watchdog. 7. Only for the “P” classification: No clock, FIRC (16 MHz) off, SIRC (128 kHz) on, PLL off, HPvreg off, ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode. 8. When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA. 9. Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum consumption, all possible modules switched off. 10. ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules switched off. DocID14619 Rev 13 67/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x 3.19 Flash memory electrical characteristics 3.19.1 Program/Erase characteristics Table 29 shows the program and erase characteristics. Table 29. Program and erase specifications Value Symbol C Parameter Unit Min Typ(1) Initial max(2) Max(3) Double word (64 bits) program time(4) — 22 50 500 µs 16 KB block preprogram and erase time — 300 500 5000 ms T32Kpperase 32 KB block preprogram and erase time — 400 600 5000 ms T128Kpperase 128 KB block preprogram and erase time — 800 1300 7500 ms — — 30 30 µs Tdwprogram T16Kpperase CC C CC D Erase suspend latency Tesus 1. Typical program and erase times assume nominal supply values and operation at 25 °C. 2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. 3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4. Actual hardware programming times. This does not include software overhead. Table 30. Flash module life Value Symbol P/E C Parameter Conditions 16 KB blocks Number of program/erase cycles 32 KB blocks CC C per block over the operating temperature range (TJ) 128 KB blocks Blocks with 0–1000 P/E cycles Retention CC C Minimum data retention at 85 °C Blocks with average ambient temperature(1) 1001–10000 P/E cycles Blocks with 10001–100000 P/E cycles Unit Min Typ Max 100000 — — 10000 100000 — 1000 100000 — 20 — — 10 — — 5 — — cycles years 1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range. ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability. 68/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 31. Flash read access timing Symbol C Conditions(1) Parameter P fREAD CC C Maximum frequency for Flash reading C Max 2 wait states 64 1 wait state 40 0 wait states 20 Unit MHz 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 3.19.2 Flash power supply DC characteristics Table 32 shows the power supply DC characteristics on external supply. Table 32. Flash memory power supply DC electrical characteristics Symbol IFREAD (2) C Sum of the current consumption on CC D VDD_HV and VDD_BV on read access Sum of the current consumption on IFMOD(2) CC D VDD_HV and VDD_BV on matrix modification (program/erase) IFLPW IFPWD Value Conditions(1) Parameter Sum of the current consumption on CC D VDD_HV and VDD_BV Sum of the current consumption on CC D VDD_HV and VDD_BV Unit Min Typ Max Code flash memory module read fCPU = 64 MHz(3) — 15 33 Data flash memory module read fCPU = 64 MHz(3) — 15 33 Program/Erase ongoing while reading code flash memory registers fCPU = 64 MHz(3) — 15 33 Program/Erase ongoing while reading data flash memory registers fCPU = 64 MHz(3) — 15 33 During code flash memory lowpower mode — — 900 During data flash memory lowpower mode — — 900 During code flash memory power-down mode — — 150 During data flash memory powerdown mode — — 150 mA mA µA µA 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 2. This value is only relative to the actual duration of the read cycle 3. fCPU 64 MHz can be achieved only at up to 105 °C DocID14619 Rev 13 69/116 115 Package pinouts and signal descriptions 3.19.3 SPC560B40x/50x, SPC560C40x/50x Start-up/Switch-off timings Table 33. Start-up time/Switch-off time Symbol C Parameter CC TFLALPEXIT CC TFLAPDEXIT CC TFLALPENTRY CC TFLAPDENTRY CC Unit Min Typ Max Code Flash — — 125 T Data Flash — — 125 T Delay for Flash module to exit low-power T mode Code Flash — — 0.5 Data Flash — — 0.5 T Delay for Flash module to exit power-down T mode Code Flash — — 30 Data Flash — — 30 T Delay for Flash module to enter low-power T mode Code Flash — — 0.5 Data Flash — — 0.5 T Delay for Flash module to enter power- Code Flash — — 1.5 T down mode Data Flash — — 1.5 T TFLARSTEXIT Value Conditions(1) Delay for Flash module to exit reset mode µs 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 3.20 Electromagnetic compatibility (EMC) characteristics Susceptibility tests are performed on a sample basis during product characterization. 3.20.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for his application.   Software recommendations:The software flowchart must include the management of runaway conditions such as: – Corrupted program counter – Unexpected reset – Critical data corruption (control registers...) Prequalification trials:Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note Software Techniques For Improving Microcontroller EMC Performance (AN1015)). 70/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x 3.20.2 Package pinouts and signal descriptions Electromagnetic interference (EMI) The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1 standard, which specifies the general conditions for EMI measurements. Table 34. EMI radiated emission measurement(1)(2) Value Symbol C Parameter Conditions Unit Min Typ Max S — Scan range R — 0.150 — 1000 MHz fCPU S — Operating frequency R — — 64 — MHz VDD_LV S — LV operating voltages R — — 1.28 — V No PLL frequency modulation — — 18 dBµV ±2% PLL frequency modulation — — 14 dBµV — SEMI C T Peak level C VDD = 5 V, TA = 25 °C, LQFP144 package Test conforming to IEC 61967-2, fOSC = 8 MHz/fCPU = 64 MHz 1. EMI testing and I/O port waveforms per IEC 61967-1, -2, -4 2. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local marketing representative. 3.20.3 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 3.20.3.1 Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the application note Electrostatic Discharge Sensitivity Measurement (AN1181). Table 35. ESD absolute maximum ratings(1) (2) Symbol C Ratings Conditions Class Max value VESD(HBM) CC T Electrostatic discharge voltage (Human Body Model) TA = 25 °C conforming to AEC-Q100-002 H1C 2000 VESD(MM) CC T Electrostatic discharge voltage (Machine Model) TA = 25 °C conforming to AEC-Q100-003 M2 200 VESD(CDM) CC T Electrostatic discharge voltage (Charged Device Model) TA = 25 °C conforming to AEC-Q100-011 C3A Unit V 500 750 (corners) 1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. DocID14619 Rev 13 71/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x 2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 3.20.3.2 Static latch-up (LU) Two complementary static tests are required on six parts to assess the latch-up performance:  A supply overvoltage is applied to each power supply pin.  A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with the EIA/JESD 78 IC latch-up standard. Table 36. Latch-up results Symbol LU 3.21 CC C Parameter T Static latch-up class Conditions TA = 125 °C conforming to JESD 78 Class II level A Fast external crystal oscillator (4 to 16 MHz) electrical characteristics The device provides an oscillator/resonator driver. Figure 13 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. Table 37 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations. 72/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Figure 13. Crystal oscillator and resonator connection scheme EXTAL C1 Crystal EXTAL XTAL C2 DEVICE VDD I R EXTAL XTAL Resonator DEVICE XTAL DEVICE Notes: 1. XTAL/EXTAL must not be directly used to drive external circuits 2. A series resistor may be required, according to crystal oscillator supplier recommendations. Table 37. Crystal description Crystal motional capacitance (Cm) fF Crystal motional inductance (Lm) mH Load on xtalin/xtalout C1 = C2 (pF)(1) Shunt capacitance between xtalout and xtalin C0(2) (pF) Nominal frequency (MHz) NDK crystal reference Crystal equivalent series resistance ESR  4 NX8045GB 300 2.68 591.0 21 2.93 8 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 120 3.11 56.5 15 2.93 120 3.90 25.3 10 3.00 12 16 NX5032GA 1. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them. 2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package, etc.). DocID14619 Rev 13 73/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Figure 14. Fast external crystal oscillator (4 to 16 MHz) timing diagram S_MTRANS bit (ME_GS register) ‘1’ ‘0’ VXTAL 1/fFXOSC VFXOSC 90% VFXOSCOP 10% tFXOSCSU valid internal clock Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics Symbol fFXOSC C Parameter Typ Max — 4.0 — 16.0 CC C VDD = 3.3 V ± 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 0 2.2 — 8.2 CC P VDD = 5.0 V ± 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 0 2.0 — 7.4 SR — Fast external crystal oscillator frequency CC C CC T Oscillation amplitude at EXTAL VFXOSCOP CC C Oscillation operating point IFXOSC(2) CC T Fast external crystal oscillator consumption Fast external crystal tFXOSCSU CC T oscillator start-up time 74/116 Unit Min Fast external crystal gmFXOSC oscillator transconductance VDD = 3.3 V ± 10%, CC C PAD3V5V = 1 OSCILLATOR_MARGIN = 1 VFXOSC Value Conditions(1) MHz mA/V 2.7 — 9.7 VDD = 5.0 V ± 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 1 2.5 — 9.2 fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 1.3 — — V fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 1.3 — — — — 0.95 — V — — 2 3 mA fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 — — 6 ms fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 DocID14619 Rev 13 — — 1.8 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued) Symbol C Parameter Value Conditions(1) Unit Min Typ Max VIH SR P Input high level CMOS (Schmitt Trigger) Oscillator bypass mode 0.65VDD — VDD+0.4 V VIL SR P Input low level CMOS (Schmitt Trigger) Oscillator bypass mode 0.4 — 0.35VDD V 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 2. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals) 3.22 Slow external crystal oscillator (32 kHz) electrical characteristics The device provides a low power oscillator/resonator driver. Figure 15. Crystal oscillator and resonator connection scheme OSC32K_EXTAL OSC32K_EXTAL Crystal Resonator C1 OSC32K_XTAL DEVICE OSC32K_XTAL C2 DEVICE Note: OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits. DocID14619 Rev 13 75/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Figure 16. Equivalent circuit of a quartz crystal C0 C1 Crystal Cm C2 Rm Lm C1 C2 Table 39. Crystal motional characteristics(1) Value Symbol Parameter Conditions Unit Min Typ Max Lm Motional inductance — — 11.796 — KH Cm Motional capacitance — — 2 — fF Load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground(2) — 18 — 28 pF AC coupled @ C0 = 2.85 pF(4) — — 65 AC coupled @ C0 = 4.9 pF(4) — — 50 AC coupled @ C0 = 7.0 pF(4) — — 35 AC coupled @ C0 = 9.0 pF(4) — — 30 C1/C2 Rm(3) Motional resistance 1. Crystal used: Epson Toyocom MC306 2. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It includes all the parasitics due to board traces, crystal and package. 3. Maximum ESR (Rm) of the crystal is 50 k 4. C0 includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins 76/116 DocID14619 Rev 13 kW SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Figure 17. Slow external crystal oscillator (32 kHz) timing diagram OSCON bit (OSC_CTL register) 1 0 VOSC32K_XTAL 1/fSXOSC VSXOSC 90% 10% TSXOSCSU valid internal clock Table 40. Slow external crystal oscillator (32 kHz) electrical characteristics Symbol C Value Conditions(1) Parameter Unit Min Typ Max fSXOSC SR — Slow external crystal oscillator frequency — 32 32.768 40 kHz VSXOSC CC T Oscillation amplitude — — 2.1 — V — — 2.5 — µA — — — 8 µA — 2(2) s ISXOSCBIAS CC T Oscillation bias current CC T Slow external crystal oscillator consumption ISXOSC TSXOSCSU CC T Slow external crystal oscillator start-up time — — 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. Values are specified for no neighbor GPIO pin activity. If oscillator is enabled (OSC32K_XTAL and OSC32K_EXTAL pins), neighboring pins should not toggle. 2. Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal. 3.23 FMPLL electrical characteristics The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver. Table 41. FMPLL electrical characteristics Symbol C fPLLIN SR — FMPLL reference clock(2) PLLIN SR — Value Conditions(1) Parameter FMPLL reference clock duty cycle(2) fPLLOUT CC D FMPLL output clock frequency Unit Min Typ Max — 4 — 64 MHz — 40 — 60 % — 16 — 64 MHz DocID14619 Rev 13 77/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Table 41. FMPLL electrical characteristics (continued) Symbol C P fVCO(3) CC Value Conditions(1) Parameter VCO frequency without frequency modulation — Unit Min Typ Max 256 — 512 MHz VCO frequency with frequency C modulation — 245 — 533 fCPU SR — System clock frequency — — — 64 MHz fFREE CC P Free-running frequency — 20 — 150 MHz tLOCK CC P FMPLL lock time Stable oscillator (fPLLIN = 16 MHz) — 40 100 µs fsys maximum –4 — 4 % fPLLIN = 16 MHz (resonator), fPLLCLK @ 64 MHz, 4000 cycles — — 10 ns TA = 25 °C — — 4 mA tSTJIT CC — FMPLL short term jitter(4) tLTJIT CC — FMPLL long term jitter IPLL CC C FMPLL consumption 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. 2. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN. 3. Frequency modulation is considered ±4% 4. Short term jitter is measured on the clock rising edge at cycle n and n+4. 3.24 Fast internal RC oscillator (16 MHz) electrical characteristics The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up of the device. Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics Symbol fFIRC IFIRCRUN (2) C CC P Fast internal RC oscillator high SR — frequency CC T Fast internal RC oscillator high frequency current in running mode Fast internal RC oscillator high IFIRCPWD CC D frequency current in power down mode TA = 25 °C, trimmed — Unit Min Typ Max — 16 — MHz 12 20 TA = 25 °C, trimmed — — 200 µA TA = 125 °C — — 10 µA sysclk = off — 500 — sysclk = 2 MHz — 600 — sysclk = 4 MHz — 700 — sysclk = 8 MHz — 900 — sysclk = 16 MHz — 1250 — Fast internal RC oscillator high IFIRCSTOP CC T frequency and system clock current TA = 25 °C in stop mode 78/116 Value Conditions(1) Parameter DocID14619 Rev 13 µA SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics (continued) Symbol tFIRCSU C CC C Value Conditions(1) Parameter Fast internal RC oscillator start-up time VDD = 5.0 V ± 10% Unit Min Typ Max — 1.1 2.0 µs +1 % FIRCPRE CC T Fast internal RC oscillator precision TA = 25 °C after software trimming of fFIRC 1 — FIRCTRIM CC T Fast internal RC oscillator trimming TA = 25 °C step — 1.6 5 — Fast internal RC oscillator variation in over temperature and supply with FIRCVAR CC P respect to fFIRC at TA = 25 °C in high-frequency configuration — % +5 % 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. 2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 3.25 Slow internal RC oscillator (128 kHz) electrical characteristics The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the RTC module. Table 43. Slow internal RC oscillator (128 kHz) electrical characteristics Symbol fSIRC C CC P Slow internal RC oscillator low SR — frequency TA = 25 °C, trimmed — ISIRC(2) CC C Slow internal RC oscillator low frequency current tSIRCSU CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ± time 10% SIRCPRE SIRCVAR TA = 25 °C, trimmed Slow internal RC oscillator CC C precision after software trimming of TA = 25 °C fSIRC SIRCTRIM CC C Value Conditions(1) Parameter Slow internal RC oscillator trimming step Unit Min Typ Max — 128 — 100 — 150 — — 5 µA — 8 12 µs 2 — +2 kHz % — Slow internal RC oscillator variation in temperature and supply with CC C High frequency configuration respect to fSIRC at TA = 55 °C in high frequency configuration — 2.7 — 10 — +10 % 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. 2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. DocID14619 Rev 13 79/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x 3.26 ADC electrical characteristics 3.26.1 Introduction The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital converter. Figure 18. ADC characteristic and error definitions Offset error (EO) Gain error (EG) 1023 1022 1021 1020 1019 1 LSB ideal = VDD_ADC / 1024 1018 (2) code out 7 (1) 6 5 (1) Example of an actual transfer curve (5) (2) The ideal transfer curve 4 (3) Differential non-linearity error (DNL) (4) (4) Integral non-linearity error (INL) 3 (5) Center of a step of the actual transfer curve (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal) Offset error (EO) 3.26.2 Input impedance and ADC accuracy In the following analysis, the input circuit corresponding to the precise channels is considered. 80/116 DocID14619 Rev 13 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: being CS and Cp2 substantially two switched capacitances, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS+Cp2 equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fc × (CS+Cp2)), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS+Cp2) and the sum of RS + RF, the external circuit must be designed to respect the Equation 4: Equation 4 RS + RF 1 V A  ---------------------  --- LSB R EQ 2 Equation 4 generates a constraint for external network design, in particular on a resistive path. DocID14619 Rev 13 81/116 115 Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x Figure 19. Input equivalent circuit (precise channels) EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source Filter RS Current Limiter RF Sampling RSW1 RAD RL CF VA Channel Selection CP1 CP2 CS RS: Source impedance RF: Filter resistance CF: Filter capacitance RL: Current limiter resistance RSW1: Channel selection switch impedance RAD: Sampling switch impedance CP: Pin capacitance (two contributions, CP1 and CP2) CS: Sampling capacitance Figure 20. Input equivalent circuit (extended channels) EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source RS VA Filter RF Current Limiter RL CF CP1 RS: Source impedance RF: Filter resistance CF: Filter capacitance RL: Current limiter resistance RSW1: Channel selection switch impedance (two contributions, RSW1 and RSW2) RAD: Sampling switch impedance CP: Pin capacitance (two contributions, CP1, CP2 and CP3) CS: Sampling capacitance 82/116 DocID14619 Rev 13 Channel Selection Extended Switch Sampling RSW1 RSW2 RAD CP3 CP2 CS SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit in Figure 19): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close). Figure 21. Transient behavior during sampling phase Voltage transient on CS VCS VA VA2 V