SPC560P34L1, SPC560P34L3
SPC560P40L1, SPC560P40L3
32-bit Power Architecture® based MCU with 320 KB Flash memory
and 20 KB RAM for automotive chassis and safety applications
Datasheet − production data
Features
■
■
Up to 64 MHz, single issue, 32-bit CPU core
complex (e200z0h)
– Compliant with Power Architecture®
embedded category
– Variable Length Encoding (VLE)
Memory organization
– Up to 256 KB on-chip code flash memory
with ECC and erase/program controller
– Additional 64 (4 × 16) KB on-chip data
flash memory with ECC for EEPROM
emulation
– Up to 20 KB on-chip SRAM with ECC
■
Fail-safe protection
– Programmable watchdog timer
– Non-maskable interrupt
– Fault collection unit
■
Nexus Class 1 interface
■
Interrupts and events
– 16-channel eDMA controller
– 16 priority level controller
– Up to 25 external interrupts
– PIT implements four 32-bit timers
– 120 interrupts are routed via INTC
■
General purpose I/Os
– Individually programmable as input, output
or special function
– 37 on LQFP64
– 64 on LQFP100
■
1 general purpose eTimer unit
– 6 timers each with up/down capabilities
– 16-bit resolution, cascadable counters
– Quadrature decode with rotation direction
flag
– Double buffer input capture and output
compare
September 2013
This is information on a product in full production.
LQFP100 (14 x 14 x 1.4 mm)
LQFP64 (10 x 10 x 1.4 mm)
■
Communications interfaces
– 2 LINFlex channels (1× Master/Slave, 1×
Master only)
– Up to 3 DSPI channels with automatic chip
select generation (up to 8/4/4 chip selects)
– Up to 2 FlexCAN interface (2.0B Active)
with 32 message buffers
– 1 safety port based on FlexCAN with 32
message buffers and up to 8 Mbit/s at
64 MHz capability usable as second CAN
when not used as safety port
■
One 10-bit analog-to-digital converter (ADC)
– Up to 16 input channels (16 on LQFP100 /
12 on LQFP64)
– Conversion time < 1 µs including sampling
time at full precision
– Programmable Cross Triggering Unit (CTU)
– 4 analog watchdogs with interrupt
capability
■
On-chip CAN/UART bootstrap loader with Boot
Assist Module (BAM)
■
1 FlexPWM unit: 8 complementary or
independent outputs with ADC synchronization
signals
Table 1.
Device summary
Code flash memory
Package
192 KB
256 KB
LQFP100
SPC560P34L3
SPC560P40L3
LQFP64
SPC560P34L1
SPC560P40L1
Doc ID 16100 Rev 7
1/103
www.st.com
1
Contents
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Contents
1
2/103
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3
Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5
Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.1
High performance e200z0 core processor . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.2
Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.3
Enhanced direct memory access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.4
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.5
Static random access memory (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.6
Interrupt controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.7
System status and configuration module (SSCM) . . . . . . . . . . . . . . . . . 16
1.5.8
System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.9
Frequency-modulated phase-locked loop (FMPLL) . . . . . . . . . . . . . . . . 17
1.5.10
Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.11
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.12
Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.13
System timer module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.14
Software watchdog timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.15
Fault collection unit (FCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.16
System integration unit – Lite (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.17
Boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.18
Error correction status module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.19
Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.20
Controller area network (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.21
Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.22
Serial communication interface module (LINFlex) . . . . . . . . . . . . . . . . . 22
1.5.23
Deserial serial peripheral interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 23
1.5.24
Pulse width modulator (FlexPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5.25
eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.26
Analog-to-digital converter (ADC) module . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.27
Cross triggering unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.5.28
Nexus Development Interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
2
3
Contents
1.5.29
Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.30
IEEE 1149.1 JTAG controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.31
On-chip voltage regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 29
2.1
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.1
Power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.2
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.3
Pin multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2
Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.5
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5.1
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5.2
General notes for specifications at maximum junction temperature . . . 52
3.6
Electromagnetic interference (EMI) characteristics . . . . . . . . . . . . . . . . . 54
3.7
Electrostatic discharge (ESD) characteristics . . . . . . . . . . . . . . . . . . . . . 54
3.8
Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 54
3.8.1
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 54
3.8.2
Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 57
3.9
Power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.10
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.10.1
NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.10.2
DC electrical characteristics (5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.10.3
DC electrical characteristics (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.10.4
Input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . 63
3.10.5
I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.11
Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.12
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.13
16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . 68
3.14
Analog-to-digital converter (ADC) electrical characteristics . . . . . . . . . . . 68
Doc ID 16100 Rev 7
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Contents
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
3.15
3.16
3.14.1
Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.14.2
ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.15.1
Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.15.2
Flash memory power supply DC characteristics . . . . . . . . . . . . . . . . . . 75
3.15.3
Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.16.1
3.17
4
5
Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.17.1
RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.17.2
IEEE 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.17.3
Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.17.4
External interrupt timing (IRQ pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.17.5
DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.2.1
LQFP100 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.2.2
LQFP64 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Appendix A Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4/103
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SPC560P34/SPC560P40 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPC560P40 device configuration differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPC560P34/SPC560P40 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
EMI testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Approved NPN ballast components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . . . . . . . . . . . . . . . 60
Supply current (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . . . . . . . . . . . . . . . 62
Supply current (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I/O supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Main oscillator output electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . 65
Main oscillator output electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . 66
Input clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Flash memory power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 75
Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
DSPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LQFP100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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List of figures
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
6/103
Block diagram (SPC560P40 full-featured configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . 10
64-pin LQFP pinout – Full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . 29
64-pin LQFP pinout – Airbag configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
100-pin LQFP pinout – Full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . 31
100-pin LQFP pinout – Airbag configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power supplies constraints (–0.3 V ≤ VDD_HV_IOx ≤ 6.0 V). . . . . . . . . . . . . . . . . . . . . . . . . 47
Independent ADC supply (–0.3 V ≤ VDD_HV_REG ≤ 6.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power supplies constraints (3.0 V ≤ VDD_HV_IOx ≤ 5.5 V). . . . . . . . . . . . . . . . . . . . . . . . . . 51
Independent ADC supply (3.0 V ≤ VDD_HV_REG ≤ 5.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Voltage regulator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Power-up typical sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Power-down typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Brown-out typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Nexus event trigger and test clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DSPI classic SPI timing – Master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
DSPI classic SPI timing – Master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DSPI classic SPI timing – Slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DSPI classic SPI timing – Slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
DSPI modified transfer format timing – Master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 88
DSPI modified transfer format timing – Master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 89
DSPI modified transfer format timing – Slave, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . 89
DSPI modified transfer format timing – Slave, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . 90
DSPI PCS Strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
LQFP64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
1
Introduction
1.1
Document overview
Introduction
This document provides electrical specifications, pin assignments, and package diagrams
for the SPC560P34/40 series of microcontroller units (MCUs). It also describes the device
features and highlights important electrical and physical characteristics. For functional
characteristics, refer to the device reference manual.
1.2
Description
This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest
achievement in integrated automotive application controllers. It belongs to an expanding
range of automotive-focused products designed to address chassis applications—
specifically, electrical hydraulic power steering (EHPS) and electric power steering (EPS)—
as well as airbag applications.
This family is one of a series of next-generation integrated automotive microcontrollers
based on the Power Architecture technology.
The advanced and cost-efficient host processor core of this automotive controller family
complies with the Power Architecture embedded category. It operates at speeds of up to
64 MHz and offers high performance processing optimized for low power consumption. It
capitalizes on the available development infrastructure of current Power Architecture
devices and is supported with software drivers, operating systems and configuration code to
assist with users implementations.
1.3
Device comparison
Table 2 provides a summary of different members of the SPC560P34/SPC560P40 family
and their features—relative to full-featured version—to enable a comparison among the
family members and an understanding of the range of functionality offered within this family.
Table 2.
SPC560P34/SPC560P40 device comparison
Feature
SPC560P34
Full-featured
SPC560P40
Full-featured
192 KB
256 KB
Code flash memory (with ECC)
Data flash memory / EE option (with ECC)
64 KB
SRAM (with ECC)
12 KB
20 KB
Processor core
32-bit e200z0h
Instruction set
VLE (variable length encoding)
CPU performance
0–64 MHz
FMPLL (frequency-modulated phase-locked loop)
module
INTC (interrupt controller) channels
1
120
PIT (periodic interrupt timer)
1 (with four 32-bit timers)
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Introduction
Table 2.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
SPC560P34/SPC560P40 device comparison (continued)
SPC560P34
Full-featured
Feature
SPC560P40
Full-featured
eDMA (enhanced direct memory access) channels
16
FlexCAN (controller area network)
1(1)
2(1),(2)
Safety port
No
Yes (via second FlexCAN
module)
FCU (fault collection unit)
Yes
CTU (cross triggering unit)
Yes
eTimer
Yes
1 (16-bit, 6 channels)
8
(capture capabity not
supported)
FlexPWM (pulse-width modulation) channels
Analog-to-digital converter (ADC)
8
(capture capability not
supported)
1 (10-bit, 16 channels)
LINFlex
2
(1 × Master/Slave,
1 × Master only)
2
(1 × Master/Slave,
1 × Master only)
2
3
DSPI (deserial serial peripheral interface)
CRC (cyclic redundancy check) unit
Yes
Junction temperature sensor
No
JTAG controller
Yes
Nexus port controller (NPC)
Digital power
Yes (Nexus Class 1)
supply(3)
3.3 V or 5 V single supply with external transistor
Analog power supply
3.3 V or 5 V
Internal RC oscillator
16 MHz
Supply
External crystal oscillator
4–40 MHz
LQFP64
LQFP100
Packages
Temperature
Standard ambient temperature
–40 to 125 °C
1. Each FlexCAN module has 32 message buffers.
2. One FlexCAN module can act as a safety port with a bit rate as high as 8 Mbit/s at 64 MHz.
3. The different supply voltages vary according to the part number ordered.
SPC560P34/SPC560P40 is available in two configurations having different features: Fullfeatured and airbag. Table 3 shows the main differences between the two versions of the
SPC560P40 MCU.
8/103
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SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Table 3.
Introduction
SPC560P40 device configuration differences
Configuration
Feature
Airbag
Full-featured
16 KB
20 KB
1
2
Safety port
No
Yes
(via second FlexCAN module)
FlexPWM (pulse-width modulation) channels
No
8
(capture capability not
supported)
CTU (cross triggering unit)
No
Yes
SRAM (with ECC)
FlexCAN (controller area network)
1.4
Block diagram
Figure 1 shows a top-level block diagram of the SPC560P34/SPC560P40 MCU. Table 2
summarizes the functions of the blocks.
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Introduction
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Figure 1.
Block diagram (SPC560P40 full-featured configuration)
External ballast
e200z0 Core
32-bit
general
purpose
registers
1.2 V regulator
control
XOSC
Integer
execution
unit
16 MHz
RC oscillator
FMPLL_0
(System)
JTAG
Nexus port
controller
Special
purpose
registers
Exception
handler
Instruction
unit
Variable
length
encoded
instructions
Branch
prediction
unit
Load/store
unit
Interrupt
controller
Nexus 1
eDMA
16 channels
Data
32-bit
Instruction
32-bit
Master
Master
Master
Crossbar switch (XBAR, AMBA 2.0 v6 AHB)
ECSM
SIUL
BAM
MC_ME
MC_CGM
MC_RGM
SWT
STM
SRAM
(with ECC)
CRC
Data Flash
(with ECC)
Slave
WKPU
Code Flash
(with ECC)
Slave
PIT
Slave
FCU
Safety port
FlexCAN
2×
LINFlex
3×
DSPI
eTimer
(6 ch)
SSCM
ADC
(10 bit, 16 ch)
CTU
FlexPWM
Peripheral bridge
Legend:
ADC
BAM
CRC
CTU
DSPI
ECSM
eDMA
eTimer
FCU
Flash
FlexCAN
FlexPWM
FMPLL
INTC
JTAG
10/103
Analog-to-digital converter
Boot assist module
Cyclic redundancy check
Cross triggering unit
Deserial serial peripheral interface
Error correction status module
Enhanced direct memory access
Enhanced timer
Fault collection unit
Flash memory
Controller area network
Flexible pulse width modulation
Frequency-modulated phase-locked loop
Interrupt controller
JTAG controller
LINFlex
MC_CGM
MC_ME
MC_PCU
MC_RGM
PIT
SIUL
SRAM
SSCM
STM
SWT
WKPU
XOSC
XBAR
Doc ID 16100 Rev 7
Serial communication interface (LIN support)
Clock generation module
Mode entry module
Power control unit
Reset generation module
Periodic interrupt timer
System Integration unit Lite
Static random-access memory
System status and configuration module
System timer module
Software watchdog timer
Wakeup unit
External oscillator
Crossbar switch
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Table 4.
Introduction
SPC560P34/SPC560P40 series block summary
Block
Function
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter
Boot assist module (BAM)
Block of read-only memory containing VLE code which is executed according to
the boot mode of the device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Controller area network
(FlexCAN)
Supports the standard CAN communications protocol
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the
eMIOS or from the PIT
Crossbar switch (XBAR)
Supports simultaneous connections between two master ports and three slave
ports; supports a 32-bit address bus width and a 32-bit data bus width
Cyclic redundancy check (CRC)
CRC checksum generator
Deserial serial peripheral
interface (DSPI)
Provides a synchronous serial interface for communication with external
devices
Enhanced direct memory access
(eDMA)
Performs complex data transfers with minimal intervention from a host
processor via “n” programmable channels
Enhanced timer (eTimer)
Provides enhanced programmable up/down modulo counting
Error correction status module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
External oscillator (XOSC)
Provides an output clock used as input reference for FMPLL_0 or as reference
clock for specific modules depending on system needs
Fault collection unit (FCU)
Provides functional safety to the device
Flash memory
Provides non-volatile storage for program code, constants and variables
Frequency-modulated phaselocked loop (FMPLL)
Generates high-speed system clocks and supports programmable frequency
modulation
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control
unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Periodic interrupt timer (PIT)
Produces periodic interrupts and triggers
Peripheral bridge (PBRIDGE)
Is the interface between the system bus and on-chip peripherals
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
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Introduction
Table 4.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
SPC560P34/SPC560P40 series block summary (continued)
Block
Function
Pulse width modulator
(FlexPWM)
Contains four PWM submodules, each of which capable of controlling a single
half-bridge power stage and two fault input channels
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the
device
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integration unit lite (SIUL) of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status and configuration
module (SSCM)
Provides system configuration and status data (such as memory size and
status, device mode and security status), device identification data, debug
status port enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AUTOSAR(1) and operating
system tasks
System watchdog timer (SWT)
Provides protection from runaway code
Wakeup unit (WKPU)
Supports up to 18 external sources that can generate interrupts or wakeup
events, of which 1 can cause non-maskable interrupt requests or wakeup
events
1. AUTOSAR: AUTomotive Open System ARchitecture (see www.autosar.org)
12/103
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SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
1.5
Feature details
1.5.1
High performance e200z0 core processor
Introduction
The e200z0 Power Architecture core provides the following features:
1.5.2
●
High performance e200z0 core processor for managing peripherals and interrupts
●
Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU
●
Harvard architecture
●
Variable length encoding (VLE), allowing mixed 16- and 32-bit instructions
–
Results in smaller code size footprint
–
Minimizes impact on performance
●
Branch processing acceleration using lookahead instruction buffer
●
Load/store unit
–
1-cycle load latency
–
Misaligned access support
–
No load-to-use pipeline bubbles
●
Thirty-two 32-bit general purpose registers (GPRs)
●
Separate instruction bus and load/store bus Harvard architecture
●
Hardware vectored interrupt support
●
Reservation instructions for implementing read-modify-write constructs
●
Long cycle time instructions, except for guarded loads, do not increase interrupt
latency
●
Extensive system development support through Nexus debug port
●
Non-maskable interrupt support
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between three
master ports and three slave ports. The crossbar supports a 32-bit address bus width and a
32-bit data bus width.
The crossbar allows for two concurrent transactions to occur from any master port to any
slave port; but one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic will select the higher priority master and grant it ownership of the slave port.
All other masters requesting that slave port will be stalled until the higher priority master
completes its transactions. Requesting masters will be treated with equal priority and will be
granted access a slave port in round-robin fashion, based upon the ID of the last master to
be granted access.
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Introduction
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
The crossbar provides the following features:
●
●
1.5.3
3 master ports:
–
e200z0 core complex instruction port
–
e200z0 core complex Load/Store Data port
–
eDMA
3 slave ports:
–
Flash memory (Code and Data)
–
SRAM
–
Peripheral bridge
●
32-bit internal address, 32-bit internal data paths
●
Fixed Priority Arbitration based on Port Master
●
Temporary dynamic priority elevation of masters
Enhanced direct memory access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels.
The eDMA module provides the following features:
1.5.4
●
16 channels support independent 8-, 16- or 32-bit single value or block transfers
●
Supports variable-sized queues and circular queues
●
Source and destination address registers are independently configured to either postincrement or to remain constant
●
Each transfer is initiated by a peripheral, CPU, or eDMA channel request
●
Each eDMA channel can optionally send an interrupt request to the CPU on completion
of a single value or block transfer
●
DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer
and CTU
●
Programmable DMA channel multiplexer allows assignment of any DMA source to any
available DMA channel with as many as 30 request sources
●
eDMA abort operation through software
Flash memory
The SPC560P34/SPC560P40 provides 320 KB of programmable, non-volatile, flash
memory. The non-volatile memory (NVM) can be used for instruction and/or data storage.
The flash memory module is interfaced to the system bus by a dedicated flash memory
controller. It supports a 32-bit data bus width at the system bus port, and a 128-bit read data
interface to flash memory. The module contains four 128-bit wide prefetch buffers. Prefetch
buffer hits allow no-wait responses. Normal flash memory array accesses are registered
and are forwarded to the system bus on the following cycle, incurring two wait-states.
14/103
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SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Introduction
The flash memory module provides the following features:
●
–
6 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 128 KB) code flash memory
–
4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash memory
–
Full Read-While-Write (RWW) capability between code flash memory and data
flash memory
●
Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch
buffers can be configured to prefetch code or data or both)
●
Typical flash memory access time: no wait-state for buffer hits, 2 wait-states for page
buffer miss at 64 MHz
●
Hardware managed flash memory writes handled by 32-bit RISC Krypton engine
●
Hardware and software configurable read and write access protections on a per-master
basis
●
Configurable access timing allowing use in a wide range of system frequencies
●
Multiple-mapping support and mapping-based block access timing (up to 31 additional
cycles) allowing use for emulation of other memory types
●
Software programmable block program/erase restriction control
●
Erase of selected block(s)
●
Read page sizes
●
1.5.5
As much as 320 KB flash memory
–
Code flash memory: 128 bits (4 words)
–
Data flash memory: 32 bits (1 word)
ECC with single-bit correction, double-bit detection for data integrity
–
Code flash memory: 64-bit ECC
–
Data flash memory: 32-bit ECC
●
Embedded hardware program and erase algorithm
●
Erase suspend and program abort
●
Censorship protection scheme to prevent flash memory content visibility
●
Hardware support for EEPROM emulation
Static random access memory (SRAM)
The SPC560P34/SPC560P40 SRAM module provides up to 20 KB of general-purpose
memory.
The SRAM module provides the following features:
●
Supports read/write accesses mapped to the SRAM from any master
●
Up to 20 KB general purpose SRAM
●
Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of
memory
●
Typical SRAM access time: no wait-state for reads and 32-bit writes; 1 wait-state for 8and 16-bit writes if back-to-back with a read to same memory block
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Introduction
1.5.6
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Interrupt controller (INTC)
The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt
requests, suitable for statically scheduled hard real-time systems. The INTC handles 128
selectable-priority interrupt sources.
For high-priority interrupt requests, the time from the assertion of the interrupt request by the
peripheral to the execution of the interrupt service routine (ISR) by the processor has been
minimized. The INTC provides a unique vector for each interrupt request source for quick
determination of which ISR has to be executed. It also provides a wide number of priorities
so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the
appropriate priorities for each source of interrupt request, the priority of each interrupt
request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol (PCP) for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the same resource can not preempt each other.
The INTC provides the following features:
1.5.7
●
Unique 9-bit vector for each separate interrupt source
●
8 software triggerable interrupt sources
●
16 priority levels with fixed hardware arbitration within priority levels for each interrupt
source
●
Ability to modify the ISR or task priority: modifying the priority can be used to implement
the priority ceiling protocol for accessing shared resources.
●
1 external high priority interrupt (NMI) directly accessing the main core and I/O
processor (IOP) critical interrupt mechanism
System status and configuration module (SSCM)
The system status and configuration module (SSCM) provides central device functionality.
The SSCM includes these features:
●
16/103
System configuration and status
–
Memory sizes/status
–
Device mode and security status
–
Determine boot vector
–
Search code flash for bootable sector
–
DMA status
●
Debug status port enable and selection
●
Bus and peripheral abort enable/disable
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
1.5.8
Introduction
System clocks and clock generation
The following list summarizes the system clock and clock generation on the
SPC560P34/SPC560P40:
1.5.9
●
Lock detect circuitry continuously monitors lock status
●
Loss of clock (LOC) detection for PLL outputs
●
Programmable output clock divider (÷1, ÷2, ÷4, ÷8)
●
FlexPWM module and eTimer module running at the same frequency as the e200z0h
core
●
Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency
trimming by user application
Frequency-modulated phase-locked loop (FMPLL)
The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input
clock. Further, the FMPLL supports programmable frequency modulation of the system
clock. The PLL multiplication factor, output clock divider ratio are all software configurable.
The FMPLL has the following major features:
1.5.10
●
Input clock frequency: 4–40 MHz
●
Maximum output frequency: 64 MHz
●
Voltage controlled oscillator (VCO)—frequency 256–512 MHz
●
Reduced frequency divider (RFD) for reduced frequency operation without forcing the
FMPLL to relock
●
Frequency-modulated PLL
–
Modulation enabled/disabled through software
–
Triangle wave modulation
●
Programmable modulation depth (±0.25% to ±4% deviation from center frequency):
programmable modulation frequency dependent on reference frequency
●
Self-clocked mode (SCM) operation
Main oscillator
The main oscillator provides these features:
1.5.11
●
Input frequency range: 4–40 MHz
●
Crystal input mode or oscillator input mode
●
PLL reference
Internal RC oscillator
This device has an RC ladder phase-shift oscillator. The architecture uses constant current
charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap
reference voltage.
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Introduction
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
The RC oscillator provides these features:
1.5.12
●
Nominal frequency 16 MHz
●
±5% variation over voltage and temperature after process trim
●
Clock output of the RC oscillator serves as system clock source in case loss of lock or
loss of clock is detected by the PLL
●
RC oscillator is used as the default system clock during startup
Periodic interrupt timer (PIT)
The PIT module implements these features:
1.5.13
●
4 general-purpose interrupt timers
●
32-bit counter resolution
●
Clocked by system clock frequency
●
Each channel usable as trigger for a DMA request
System timer module (STM)
The STM implements these features:
1.5.14
●
One 32-bit up counter with 8-bit prescaler
●
Four 32-bit compare channels
●
Independent interrupt source for each channel
●
Counter can be stopped in debug mode
Software watchdog timer (SWT)
The SWT has the following features:
1.5.15
●
32-bit time-out register to set the time-out period
●
Programmable selection of window mode or regular servicing
●
Programmable selection of reset or interrupt on an initial time-out
●
Master access protection
●
Hard and soft configuration lock bits
●
Reset configuration inputs allow timer to be enabled out of reset
Fault collection unit (FCU)
The FCU provides an independent fault reporting mechanism even if the CPU is
malfunctioning.
The FCU module has the following features:
18/103
●
FCU status register reporting the device status
●
Continuous monitoring of critical fault signals
●
User selection of critical signals from different fault sources inside the device
●
Critical fault events trigger 2 external pins (user selected signal protocol) that can be
used externally to reset the device and/or other circuitry (for example, a safety relay)
●
Faults are latched into a register
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
1.5.16
Introduction
System integration unit – Lite (SIUL)
The SPC560P34/SPC560P40 SIUL controls MCU pad configuration, external interrupt,
general purpose I/O (GPIO), and internal peripheral multiplexing.
The pad configuration block controls the static electrical characteristics of I/O pins. The
GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.
The SIUL provides the following features:
1.5.17
●
Centralized general purpose input output (GPIO) control of up to 49 input/output pins
and 16 analog input-only pads (package dependent)
●
All GPIO pins can be independently configured to support pull-up, pull-down, or no pull
●
Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
●
All peripheral pins, except ADC channels, can be alternatively configured as both
general purpose input or output pins
●
ADC channels support alternative configuration as general purpose inputs
●
Direct readback of the pin value is supported on all pins through the SIUL
●
Configurable digital input filter that can be applied to some general purpose input pins
for noise elimination
●
Up to 4 internal functions can be multiplexed onto 1 pin
Boot and censorship
Different booting modes are available in the SPC560P34/SPC560P40: booting from internal
flash memory and booting via a serial link.
The default booting scheme uses the internal flash memory (an internal pull-down resistor is
used to select this mode). Optionally, the user can boot via FlexCAN or LINFlex (using the
boot assist module software).
A censorship scheme is provided to protect the content of the flash memory and offer
increased security for the entire device.
A password mechanism is designed to grant the legitimate user access to the non-volatile
memory.
Boot assist module (BAM)
The BAM is a block of read-only memory that is programmed once and is identical for all
SPC560Pxx devices that are based on the e200z0h core. The BAM program is executed
every time the device is powered on if the alternate boot mode has been selected by the
user.
The BAM provides the following features:
1.5.18
●
Serial bootloading via FlexCAN or LINFlex
●
Ability to accept a password via the used serial communication channel to grant the
legitimate user access to the non-volatile memory
Error correction status module (ECSM)
The ECSM provides a myriad of miscellaneous control functions regarding program-visible
information about the platform configuration and revision levels, a reset status register, a
software watchdog timer, wakeup control for exiting sleep modes, and information on
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Introduction
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
platform memory errors reported by error-correcting codes and/or generic access error
information for certain processor cores.
The Error Correction Status Module supports a number of miscellaneous control functions
for the platform. The ECSM includes these features:
●
Registers for capturing information on platform memory errors if error-correcting codes
(ECC) are implemented
●
For test purposes, optional registers to specify the generation of double-bit memory
errors are enabled on the SPC560P34/SPC560P40.
The sources of the ECC errors are:
1.5.19
●
Flash memory
●
SRAM
Peripheral bridge (PBRIDGE)
The PBRIDGE implements the following features:
1.5.20
●
Duplicated periphery
●
Master access privilege level per peripheral (per master: read access enable; write
access enable)
●
Write buffering for peripherals
●
Checker applied on PBRIDGE output toward periphery
●
Byte endianess swap capability
Controller area network (FlexCAN)
The SPC560P34/SPC560P40 MCU contains one controller area network (FlexCAN)
module. This module is a communication controller implementing the CAN protocol
according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: realtime processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness
and required bandwidth. The FlexCAN module contains 32 message buffers.
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SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Introduction
The FlexCAN module provides the following features:
●
–
Standard data and remote frames
–
Extended data and remote frames
–
Up to 8-bytes data length
–
Programmable bit rate up to 1 Mbit/s
●
32 message buffers of up to 8-bytes data length
●
Each message buffer configurable as Rx or Tx, all supporting standard and extended
messages
●
Programmable loop-back mode supporting self-test operation
●
3 programmable mask registers
●
Programmable transmit-first scheme: lowest ID or lowest buffer number
●
Time stamp based on 16-bit free-running timer
●
Global network time, synchronized by a specific message
●
Maskable interrupts
●
Independent of the transmission medium (an external transceiver is assumed)
●
High immunity to EMI
●
Short latency time due to an arbitration scheme for high-priority messages
●
Transmit features
●
●
1.5.21
Full implementation of the CAN protocol specification, version 2.0B
–
Supports configuration of multiple mailboxes to form message queues of scalable
depth
–
Arbitration scheme according to message ID or message buffer number
–
Internal arbitration to guarantee no inner or outer priority inversion
–
Transmit abort procedure and notification
Receive features
–
Individual programmable filters for each mailbox
–
8 mailboxes configurable as a 6-entry receive FIFO
–
8 programmable acceptance filters for receive FIFO
Programmable clock source
–
System clock
–
Direct oscillator clock to avoid PLL jitter
Safety port (FlexCAN)
The SPC560P34/SPC560P40 MCU has a second CAN controller synthesized to run at high
bit rates to be used as a safety port. The CAN module of the safety port provides the
following features:
●
Identical to the FlexCAN module
●
Bit rate up to 8 Mbit/s at 64 MHz CPU clock using direct connection between CAN
modules (no physical transceiver required)
●
32 message buffers of up to 8-bytes data length
●
Can be used as a second independent CAN module
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Introduction
1.5.22
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Serial communication interface module (LINFlex)
The LINFlex (local interconnect network flexible) on the SPC560P34/SPC560P40 features
the following:
●
Supports LIN Master mode (both instances), LIN Slave mode (only one instance) and
UART mode
●
LIN state machine compliant to LIN1.3, 2.0 and 2.1 specifications
●
Handles LIN frame transmission and reception without CPU intervention
●
LIN features
●
●
22/103
–
Autonomous LIN frame handling
–
Message buffer to store Identifier and up to 8 data bytes
–
Supports message length of up to 64 bytes
–
Detection and flagging of LIN errors (sync field, delimiter, ID parity, bit framing,
checksum, and time-out)
–
Classic or extended checksum calculation
–
Configurable Break duration of up to 36-bit times
–
Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
–
Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection
–
Interrupt-driven operation with 16 interrupt sources
LIN slave mode features:
–
Autonomous LIN header handling
–
Autonomous LIN response handling
–
Optional discarding of irrelevant LIN responses using ID filter
UART mode:
–
Full-duplex operation
–
Standard non return-to-zero (NRZ) mark/space format
–
Data buffers with 4-byte receive, 4-byte transmit
–
Configurable word length (8-bit or 9-bit words)
–
Error detection and flagging
–
Parity, Noise and Framing errors
–
Interrupt-driven operation with four interrupt sources
–
Separate transmitter and receiver CPU interrupt sources
–
16-bit programmable baud-rate modulus counter and 16-bit fractional
–
2 receiver wake-up methods
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
1.5.23
Introduction
Deserial serial peripheral interface (DSPI)
The deserial serial peripheral interface (DSPI) module provides a synchronous serial
interface for communication between the SPC560P34/SPC560P40 MCU and external
devices.
The DSPI modules provide these features:
1.5.24
●
Full duplex, synchronous transfers
●
Master or slave operation
●
Programmable master bit rates
●
Programmable clock polarity and phase
●
End-of-transmission interrupt flag
●
Programmable transfer baud rate
●
Programmable data frames from 4 to 16 bits
●
Up to 8 chip select lines available:
–
8 on DSPI_0
–
4 each on DSPI_1 and DSPI_2
●
8 clock and transfer attributes registers
●
Chip select strobe available as alternate function on one of the chip select pins for
deglitching
●
FIFOs for buffering up to 4 transfers on the transmit and receive side
●
Queueing operation possible through use of the I/O processor or eDMA
●
General purpose I/O functionality on pins when not used for SPI
Pulse width modulator (FlexPWM)
The pulse width modulator module (PWM) contains four PWM submodules each of which is
set up to control a single half-bridge power stage. There are also three fault channels.
This PWM is capable of controlling most motor types: AC induction motors (ACIM),
permanent magnet AC motors (PMAC), both brushless (BLDC) and brush DC motors
(BDC), switched (SRM) and variable reluctance motors (VRM), and stepper motors.
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Introduction
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
The FlexPWM block implements the following features:
24/103
●
16-bit resolution for center, edge-aligned, and asymmetrical PWMs
●
Clock frequency same as that used for e200z0h core
●
PWM outputs can operate as complementary pairs or independent channels
●
Can accept signed numbers for PWM generation
●
Independent control of both edges of each PWM output
●
Synchronization to external hardware or other PWM supported
●
Double buffered PWM registers
–
Integral reload rates from 1 to 16
–
Half cycle reload capability
●
Multiple ADC trigger events can be generated per PWM cycle via hardware
●
Write protection for critical registers
●
Fault inputs can be assigned to control multiple PWM outputs
●
Programmable filters for fault inputs
●
Independently programmable PWM output polarity
●
Independent top and bottom deadtime insertion
●
Each complementary pair can operate with its own PWM frequency and deadtime
values
●
Individual software-control for each PWM output
●
All outputs can be programmed to change simultaneously via a “Force Out” event
●
PWMX pin can optionally output a third PWM signal from each submodule
●
Channels not used for PWM generation can be used for buffered output compare
functions
●
Channels not used for PWM generation can be used for input capture functions
●
Enhanced dual-edge capture functionality
●
eDMA support with automatic reload
●
2 fault inputs
●
Capture capability for PWMA, PWMB, and PWMX channels not supported
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
1.5.25
Introduction
eTimer
The SPC560P34/SPC560P40 includes one eTimer module which provides six 16-bit
general purpose up/down timer/counter units with the following features:
●
Clock frequency same as that used for the e200z0h core
●
Individual channel capability
●
●
1.5.26
–
Input capture trigger
–
Output compare
–
Double buffer (to capture rising edge and falling edge)
–
Separate prescaler for each counter
–
Selectable clock source
–
0–100% pulse measurement
–
Rotation direction flag (quad decoder mode)
Maximum count rate
–
External event counting: max. count rate = peripheral clock/2
–
Internal clock counting: max. count rate = peripheral clock
Counters are:
–
Cascadable
–
Preloadable
●
Programmable count modulo
●
Quadrature decode capabilities
●
Counters can share available input pins
●
Count once or repeatedly
●
Pins available as GPIO when timer functionality not in use
Analog-to-digital converter (ADC) module
The ADC module provides the following features:
Analog part:
●
1 on-chip analog-to-digital converter
–
10-bit AD resolution
–
1 sample and hold unit
–
Conversion time, including sampling time, less than 1 µs (at full precision)
–
Typical sampling time is 150 ns minimum (at full precision)
–
DNL/INL ±1 LSB
–
TUE < 1.5 LSB
–
Single-ended input signal up to 3.3 V/5.0 V
–
3.3 V/5.0 V input reference voltage
–
ADC and its reference can be supplied with a voltage independent from VDDIO
–
ADC supply can be equal or higher than VDDIO
–
ADC supply and ADC reference are not independent from each other (both
internally bonded to same pad)
–
Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
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Introduction
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Digital part:
●
16 input channels
●
4 analog watchdogs comparing ADC results against predefined levels (low, high,
range) before results are stored in the appropriate ADC result location
●
2 modes of operation: Motor Control mode or Regular mode
●
Regular mode features
●
1.5.27
–
Register based interface with the CPU: control register, status register and 1 result
register per channel
–
ADC state machine managing 3 request flows: regular command, hardware
injected command and software injected command
–
Selectable priority between software and hardware injected commands
–
DMA compatible interface
CTU-controlled mode features
–
Triggered mode only
–
4 independent result queues (1×16 entries, 2×8 entries, 1×4 entries)
–
Result alignment circuitry (left justified and right justified)
–
32-bit read mode allows to have channel ID on one of the 16-bit part
–
DMA compatible interfaces
Cross triggering unit (CTU)
The cross triggering unit allows automatic generation of ADC conversion requests on user
selected conditions without CPU load during the PWM period and with minimized CPU load
for dynamic configuration.
It implements the following features:
1.5.28
●
Double buffered trigger generation unit with up to 8 independent triggers generated
from external triggers
●
Trigger generation unit configurable in sequential mode or in triggered mode
●
Each trigger can be appropriately delayed to compensate the delay of external low
pass filter
●
Double buffered global trigger unit allowing eTimer synchronization and/or ADC
command generation
●
Double buffered ADC command list pointers to minimize ADC-trigger unit update
●
Double buffered ADC conversion command list with up to 24 ADC commands
●
Each trigger capable of generating consecutive commands
●
ADC conversion command allows to control ADC channel, single or synchronous
sampling, independent result queue selection
Nexus Development Interface (NDI)
The NDI (Nexus Development Interface) block is compliant with Nexus Class 1 of the IEEEISTO 5001-2003 standard. This development support is supplied for MCUs without requiring
external address and data pins for internal visibility. The NDI block is an integration of
several individual Nexus blocks that are selected to provide the development support
interface for this device. The NDI block interfaces to the host processor and internal busses
to provide development support as per the IEEE-ISTO 5001-2003 Nexus Class 1 standard.
26/103
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Introduction
The development support provided includes access to the MCU’s internal memory map and
access to the processor’s internal registers.
The NDI provides the following features:
1.5.29
●
Configured via the IEEE 1149.1
●
All Nexus port pins operate at VDDIO (no dedicated power supply)
●
Nexus Class 1 supports Static debug
Cyclic redundancy check (CRC)
The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The
CRC module features:
●
Support for CRC-16-CCITT (x25 protocol):
–
●
Support for CRC-32 (Ethernet protocol):
–
●
1.5.30
x16 + x12 + x5 + 1
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
Zero wait states for each write/read operations to the CRC_CFG and CRC_INP
registers at the maximum frequency
IEEE 1149.1 JTAG controller
The JTAG controller (JTAGC) block provides the means to test chip functionality and
connectivity while remaining transparent to system logic when not in test mode. All data
input to and output from the JTAGC block is communicated in serial format. The JTAGC
block is compliant with the IEEE standard.
The JTAG controller provides the following features:
●
IEEE test access port (TAP) interface 4 pins (TDI, TMS, TCK, TDO)
●
Selectable modes of operation include JTAGC/debug or normal system operation.
●
5-bit instruction register that supports the following IEEE 1149.1-2001 defined
instructions:
●
●
●
–
BYPASS
–
IDCODE
–
EXTEST
–
SAMPLE
–
SAMPLE/PRELOAD
5-bit instruction register that supports the additional following public instructions:
–
ACCESS_AUX_TAP_NPC
–
ACCESS_AUX_TAP_ONCE
3 test data registers:
–
Bypass register
–
Boundary scan register (size parameterized to support a variety of boundary scan
chain lengths)
–
Device identification register
TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry
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Introduction
1.5.31
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
On-chip voltage regulator (VREG)
The on-chip voltage regulator module provides the following features:
28/103
●
Uses external NPN (negative-positive-negative) transistor
●
Regulates external 3.3 V/5.0 V down to 1.2 V for the core logic
●
Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-
2
Package pinouts and signal descriptions
2.1
Package pinouts
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
A[15]
A[14]
B[6]
A[13]
A[9]
VSS_LV_COR2
VDD_LV_COR2
C[8]
VSS_HV_IO3
VDD_HV_IO3
A[12]
A[11]
A[10]
B[2]
B[1]
B[0]
The LQFP pinouts are shown in the following figures. For pin signal descriptions, please
refer to Table 7.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LQFP64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A[4]
VPP_TEST
D[14]]
D[12]
D[13
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
C[12]
C[11]
D[7]
E[1]
C[1]
B[7]
C[2]
B[8]
E[2]
B[9]
B[10]
B[11]
B[12]
VDD_HV_ADC0
VSS_HV_ADC0
E[3]/B[13]
BCTRL
VDD_HV_REG
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NMI
A[6]
A[7]
A[8]
A[5]
VDD_HV_IO1
VSS_HV_IO1
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
VSS_LV_COR0
VDD_LV_COR0
Figure 2.
64-pin LQFP pinout – Full featured configuration (top view)
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SPC560P34L1, SPC560P34L3, SPC560P40L1,
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
A[15]
A[14]
B[6]
A[13]
A[9]
VSS_LV_COR2
VDD_LV_COR2
C[8]
VSS_HV_IO3
VDD_HV_IO3
A[12]
A[11]
A[10]
B[2]
B[1]]
B[0]
Package pinouts and signal descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LQFP64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A[4]
VPP_TEST
D[14]
D[12]
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
C[12]
C[11]
D[7]
E[1]
C[1]
B[7]
C[2]
B[8]
E[2]
B[9]
B[10]
B[11]
B[12]
VDD_HV_ADC0
VSS_HV_ADC0
E[3]/B[13]
BCTRL
VDD_HV_REG
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NMI
A[6]
A[7]
A[8]
A[5]
VDD_HV_IO1
VSS_HV_IO1
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
VSS_LV_COR0
VDD_LV_COR0
Figure 3.
30/103
64-pin LQFP pinout – Airbag configuration (top view)
Doc ID 16100 Rev 7
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
A[15]
A[14]
C[6]
D[2]
B[6]
A[13]
A[9]
VSS_LV_COR2
VDD_LV_COR2
C[8]
D[4]
D[3]
VSS_HV_IO3
VDD_HV_IO3
D[0]
C[15]
C[9]
A[12]
A[11]
A[10]
B[3]
B[2]
C[10]
B[1]
B[0]
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LQFP100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A[4]
VPP_TEST
D[14]
C[14]
C[13]
D[12]
N.C.
N.C.
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
A[2]
C[12]
C[11]
D[11]
D[10]
A[1]
A[0]
D[7]
E[1]
C[1]
B[7]
C[2]
B[8]
E[2]
N.C.
N.C.
B[9]
B[10]
B[11]
B[12]
VDD_HV_ADC0
VSS_HV_ADC0
E[7]/D[15]
E[3]/B[13]
E[5]/B[15]
E[4]/B[14]
E[6]/C[0]
N.C.
BCTRL
N.C.
N.C.
VDD_HV_REG
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NMI
A[6]
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
C[3]
N.C.
N.C.
VDD_HV_IO1
VSS_HV_IO1
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[6]
VSS_LV_COR0
VDD_LV_COR0
Figure 4.
100-pin LQFP pinout – Full featured configuration (top view)
Doc ID 16100 Rev 7
31/103
SPC560P34L1, SPC560P34L3, SPC560P40L1,
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
A[15]
A[14]
C[6]
D[2]
B[6]
A[13]
A[9]
VSS_LV_COR2
VDD_LV_COR2
C[8]
D[4]
D[3]
VSS_HV_IO3
VDD_HV_IO3
D[0]
C[15]
C[9]
A[12]
A[11]
A[10]
B[3]
B[2]
C[10]
B[1]
B[0]
Package pinouts and signal descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LQFP100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A[4]
VPP_TEST
D[14]
C[14]
C[13]
D[12]
N.C.
N.C.
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
A[2]
C[12]
C[11]
D[11]
D[10]
A[1]
A[0]
D[7]
E[1]
C[1]
B[7]
C[2]
B[8]
E[2]
N.C.
N.C.
B[9]
B[10]
B[11]
B[12]
VDD_HV_ADC0
VSS_HV_ADC0
E[7]/D[15]
E[3]/B[13]
E[5]/B[15]
E[4]/B[14]
E[6]/C[0]
N.C.
BCTRL
N.C.
N.C.
VDD_HV_REG
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NMI
A[6]
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
C[3]
N.C.
N.C.
VDD_HV_IO1
VSS_HV_IO1
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[6]
VSS_LV_COR0
VDD_LV_COR0
Figure 5.
32/103
100-pin LQFP pinout – Airbag configuration (top view)
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-
2.2
Pin description
The following sections provide signal descriptions and related information about the
functionality and configuration of the SPC560P34/SPC560P40 devices.
2.2.1
Power supply and reference voltage pins
Table 5 lists the power supply and reference voltage for the SPC560P34/SPC560P40
devices.
Table 5.
Supply pins
Supply
Symbol
Pin
Description
64-pin
100-pin
VREG control and power supply pins. Pins available on 64-pin and 100-pin packages
BCTRL
VDD_HV_REG
(3.3 V or 5.0 V)
Voltage regulator external NPN ballast base control pin
31
47
Voltage regulator supply voltage
32
50
ADC_0 reference and supply voltage. Pins available on 64-pin and 100-pin packages
VDD_HV_ADC0(1)
ADC_0 supply and high reference voltage
28
39
VSS_HV_ADC0
ADC_0 ground and low reference voltage
29
40
Power supply pins (3.3 V or 5.0 V). Pins available on 64-pin and 100-pin packages
VDD_HV_IO1
Input/output supply voltage
6
13
VSS_HV_IO1
Input/output ground
7
14
VDD_HV_IO2
Input/output supply voltage and data Flash memory supply voltage
40
63
VSS_HV_IO2
Input/output ground and Flash memory HV ground
39
62
VDD_HV_IO3
Input/output supply voltage and code Flash memory supply voltage
55
87
VSS_HV_IO3
Input/output ground and code Flash memory HV ground
56
88
VDD_HV_OSC
Crystal oscillator amplifier supply voltage
9
16
VSS_HV_OSC
Crystal oscillator amplifier ground
10
17
Power supply pins (1.2 V). Pins available on 64-pin and 100-pin packages
VDD_LV_COR0
1.2 V supply pins for core logic and PLL. Decoupling capacitor must be
connected between these pins and the nearest VSS_LV_COR pin.
16
25
VSS_LV_COR0
1.2 V supply pins for core logic and PLL. Decoupling capacitor must be
connected between these pins and the nearest VDD_LV_COR pin.
15
24
VDD_LV_COR1
1.2 V supply pins for core logic and data Flash. Decoupling capacitor
must be connected between these pins and the nearest VSS_LV_COR
pin.
42
65
VSS_LV_COR1
1.2 V supply pins for core logic and data Flash. Decoupling capacitor
must be connected between these pins and the nearest VDD_LV_COR
pin.
43
66
Doc ID 16100 Rev 7
33/103
Package pinouts and signal descriptions
Table 5.
SPC560P34L1, SPC560P34L3, SPC560P40L1,
Supply pins (continued)
Supply
Symbol
Pin
Description
64-pin
100-pin
VDD_LV_COR2
1.2 V supply pins for core logic and code Flash. Decoupling capacitor
must be connected between these pins and the nearest VSS_LV_COR
pin.
58
92
VSS_LV_COR2
1.2 V supply pins for core logic and code Flash. Decoupling capacitor
must be connected betwee.n these pins and the nearest VDD_LV_COR
pin.
59
93
1. Analog supply/ground and high/low reference lines are internally physically separate, but are shorted via a double-bonding
connection on VDD_HV_ADCx/VSS_HV_ADCx pins.
2.2.2
System pins
Table 6 and Table 7 contain information on pin functions for the SPC560P34/SPC560P40
devices. The pins listed in Table 6 are single-function pins. The pins shown in Table 7 are
multi-function pins, programmable via their respective pad configuration register (PCR)
values.
Table 6.
System pins
Pad speed(1)
Symbol
Description
Pin
Direction
SRC = 0 SRC = 1 64-pin 100-pin
Dedicated pins
NMI
XTAL
EXTAL
Non-maskable Interrupt
Input only
Slow
—
1
1
Analog output of the oscillator amplifier
circuit—needs to be grounded if oscillator is
used in bypass mode
—
—
—
11
18
Analog input of the oscillator amplifier circuit,
when the oscillator is not in bypass mode
Analog input for the clock generator when the
oscillator is in bypass mode
—
—
—
12
19
TDI
JTAG test data input
Input only
Slow
—
35
58
TMS
JTAG state machine control
Input only
Slow
—
36
59
TCK
JTAG clock
Input only
Slow
—
37
60
TDO
JTAG test data output
Output only
Slow
Fast
38
61
—
13
20
—
47
74
Reset pin
RESET
Bidirectional reset with Schmitt trigger
characteristics and noise filter
Bidirectional Medium
Test pin
VPP_TEST
Pin for testing purpose only. To be tied to
ground in normal operating mode.
—
—
1. SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.
34/103
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descrip-
2.2.3
Pin multiplexing
Table 7 defines the pin list and muxing for the SPC560P34/SPC560P40 devices.
Each row of Table 7 shows all the possible ways of configuring each pin, via alternate
functions. The default function assigned to each pin after reset is the ALT0 function.
SPC560P34/SPC560P40 devices provide three main I/O pad types, depending on the
associated functions:
●
Slow pads are the most common, providing a compromise between transition time and
low electromagnetic emission.
●
Medium pads provide fast enough transition for serial communication channels with
controlled current to reduce electromagnetic emission.
●
Fast pads provide maximum speed. They are used for improved NEXUS debugging
capability.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance. For more information, see “Pad AC Specifications” in
the device datasheet.
Table 7.
Port
pin
Pin muxing
PCR
register
Alternate
function(1),(2)
Functions
Peripheral(3)
I/O
direction(4)
Pad speed(5)
Pin
SRC = 0 SRC = 1 64-pin 100-pin
Port A (16-bit)
A[0]
A[1]
A[2]
A[3]
PCR[0]
ALT0
ALT1
ALT2
ALT3
—
GPIO[0]
ETC[0]
SCK
F[0]
EIRQ[0]
SIUL
eTimer_0
DSPI_2
FCU_0
SIUL
I/O
I/O
I/O
O
I
Slow
Medium
—
51
PCR[1]
ALT0
ALT1
ALT2
ALT3
—
GPIO[1]
ETC[1]
SOUT
F[1]
EIRQ[1]
SIUL
eTimer_0
DSPI_2
FCU_0
SIUL
I/O
I/O
O
O
I
Slow
Medium
—
52
PCR[2]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[2]
ETC[2]
—
A[3]
SIN
ABS[0]
EIRQ[2]
SIUL
eTimer_0
—
FlexPWM_0
DSPI_2
MC_RGM
SIUL
I/O
I/O
—
O
I
I
I
Slow
Medium
—
57
PCR[3]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[3]
ETC[3]
CS0
B[3]
ABS[1]
EIRQ[3]
SIUL
eTimer_0
DSPI_2
FlexPWM_0
MC_RGM
SIUL
I/O
I/O
I/O
O
I
I
Slow
Medium
41
64
Doc ID 16100 Rev 7
35/103
Package pinouts and signal descriptions
Table 7.
Port
pin
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
36/103
SPC560P34L1, SPC560P34L3, SPC560P40L1,
Pin muxing (continued)
I/O
direction(4)
Pad speed(5)
Pin
PCR
register
Alternate
function(1),(2)
Functions
PCR[4]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[4]
—
CS1
ETC[4]
FAB
EIRQ[4]
SIUL
—
DSPI_2
eTimer_0
MC_RGM
SIUL
I/O
—
O
I/O
I
I
Slow
Medium
48
75
PCR[5]
ALT0
ALT1
ALT2
ALT3
—
GPIO[5]
CS0
—
CS7
EIRQ[5]
SIUL
DSPI_1
—
DSPI_0
SIUL
I/O
I/O
—
O
I
Slow
Medium
5
8
PCR[6]
ALT0
ALT1
ALT2
ALT3
—
GPIO[6]
SCK
—
—
EIRQ[6]
SIUL
DSPI_1
—
—
SIUL
I/O
I/O
—
—
I
Slow
Medium
2
2
PCR[7]
ALT0
ALT1
ALT2
ALT3
—
GPIO[7]
SOUT
—
—
EIRQ[7]
SIUL
DSPI_1
—
—
SIUL
I/O
O
—
—
I
Slow
Medium
3
4
PCR[8]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[8]
—
—
—
SIN
EIRQ[8]
SIUL
—
—
—
DSPI_1
SIUL
I/O
—
—
—
I
I
Slow
Medium
4
6
PCR[9]
ALT0
ALT1
ALT2
ALT3
—
GPIO[9]
CS1
—
B[3]
FAULT[0]
SIUL
DSPI_2
—
FlexPWM_0
FlexPWM_0
I/O
O
—
O
I
Slow
Medium
60
94
PCR[10]
ALT0
ALT1
ALT2
ALT3
—
GPIO[10]
CS0
B[0]
X[2]
EIRQ[9]
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
I/O
I/O
O
O
I
Slow
Medium
52
81
Peripheral(3)
Doc ID 16100 Rev 7
SRC = 0 SRC = 1 64-pin 100-pin
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descripTable 7.
Port
pin
A[11]
A[12]
A[13]
A[14]
A[15]
Pin muxing (continued)
I/O
direction(4)
Pad speed(5)
Pin
PCR
register
Alternate
function(1),(2)
Functions
PCR[11]
ALT0
ALT1
ALT2
ALT3
—
GPIO[11]
SCK
A[0]
A[2]
EIRQ[10]
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
I/O
I/O
O
O
I
Slow
Medium
53
82
PCR[12]
ALT0
ALT1
ALT2
ALT3
—
GPIO[12]
SOUT
A[2]
B[2]
EIRQ[11]
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
I/O
O
O
O
I
Slow
Medium
54
83
PCR[13]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[13]
—
B[2]
—
SIN
FAULT[0]
EIRQ[12]
SIUL
—
FlexPWM_0
—
DSPI_2
FlexPWM_0
SIUL
I/O
—
O
—
I
I
I
Slow
Medium
61
95
PCR[14]
ALT0
ALT1
ALT2
ALT3
—
GPIO[14]
TXD
—
—
EIRQ[13]
SIUL
Safety Port_0
—
—
SIUL
I/O
O
—
—
I
Slow
Medium
63
99
PCR[15]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[15]
—
—
—
RXD
EIRQ[14]
SIUL
—
—
—
Safety Port_0
SIUL
I/O
—
—
—
I
I
Slow
Medium
64
100
Peripheral(3)
SRC = 0 SRC = 1 64-pin 100-pin
Port B (16-bit)
B[0]
B[1]
PCR[16]
ALT0
ALT1
ALT2
ALT3
—
GPIO[16]
TXD
—
DEBUG[0]
EIRQ[15]
SIUL
FlexCAN_0
—
SSCM
SIUL
I/O
O
—
—
I
Slow
Medium
49
76
PCR[17]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[17]
—
—
DEBUG[1]
RXD
EIRQ[16]
SIUL
—
—
SSCM
FlexCAN_0
SIUL
I/O
—
—
—
I
I
Slow
Medium
50
77
Doc ID 16100 Rev 7
37/103
Package pinouts and signal descriptions
Table 7.
Port
pin
B[2]
B[3]
B[6]
B[7]
B[8]
B[9]
B[10]
38/103
SPC560P34L1, SPC560P34L3, SPC560P40L1,
Pin muxing (continued)
I/O
direction(4)
Pad speed(5)
Pin
PCR
register
Alternate
function(1),(2)
Functions
PCR[18]
ALT0
ALT1
ALT2
ALT3
—
GPIO[18]
TXD
—
DEBUG[2]
EIRQ[17]
SIUL
LIN_0
—
SSCM
SIUL
I/O
O
—
—
I
Slow
Medium
51
79
PCR[19]
ALT0
ALT1
ALT2
ALT3
—
GPIO[19]
—
—
DEBUG[3]
RXD
SIUL
—
—
SSCM
LIN_0
I/O
—
—
—
I
Slow
Medium
—
80
PCR[22]
ALT0
ALT1
ALT2
ALT3
—
GPIO[22]
CLKOUT
CS2
—
EIRQ[18]
SIUL
Control
DSPI_2
—
SIUL
I/O
O
O
—
I
Slow
Medium
62
96
PCR[23]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[23]
—
—
—
AN[0]
RXD
SIUL
—
—
—
ADC_0
LIN_0
Input only
—
—
20
29
PCR[24]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[24]
—
—
—
AN[1]
ETC[5]
SIUL
—
—
—
ADC_0
eTimer_0
Input only
—
—
22
31
PCR[25]
ALT0
ALT1
ALT2
ALT3
—
GPIO[25]
—
—
—
AN[11]
SIUL
—
—
—
ADC_0
Input only
—
—
24
35
PCR[26]
ALT0
ALT1
ALT2
ALT3
—
GPIO[26]
—
—
—
AN[12]
SIUL
—
—
—
ADC_0
Input only
—
—
25
36
Peripheral(3)
Doc ID 16100 Rev 7
SRC = 0 SRC = 1 64-pin 100-pin
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descripTable 7.
Port
pin
B[11]
B[12]
B[13]
B[14]
B[15]
Pin muxing (continued)
I/O
direction(4)
Pad speed(5)
Pin
PCR
register
Alternate
function(1),(2)
Functions
PCR[27]
ALT0
ALT1
ALT2
ALT3
—
GPIO[27]
—
—
—
AN[13]
SIUL
—
—
—
ADC_0
Input only
—
—
26
37
PCR[28]
ALT0
ALT1
ALT2
ALT3
—
GPIO[28]
—
—
—
AN[14]
SIUL
—
—
—
ADC_0
Input only
—
—
27
38
PCR[29]
ALT0
ALT1
ALT2
ALT3
—
—
—
SIUL
GPIO[29]
—
—
—
—
—
—
Input only
ADC_0
AN[6]
emu. AN[0] emu. ADC_1(6)
RXD
LIN_1
—
—
30
42
PCR[30]
ALT0
ALT1
ALT2
ALT3
—
—
—
—
SIUL
GPIO[30]
—
—
—
—
—
—
Input only
ADC_0
AN[7]
emu. AN[1] emu. ADC_1(6)
ETC[4]
eTimer_0
EIRQ[19]
SIUL
—
—
—
44
PCR[31]
ALT0
ALT1
ALT2
ALT3
—
—
—
SIUL
GPIO[31]
—
—
—
—
—
—
Input only
ADC_0
AN[8]
emu. AN[2] emu. ADC_1(6)
EIRQ[20]
SIUL
—
—
—
43
—
—
—
45
Peripheral(3)
SRC = 0 SRC = 1 64-pin 100-pin
Port C (16-bit)
C[0]
PCR[32]
ALT0
ALT1
ALT2
ALT3
—
—
SIUL
GPIO[32]
—
—
—
—
Input only
—
—
ADC_0
AN[9]
emu. AN[3] emu. ADC_1(6)
Doc ID 16100 Rev 7
39/103
Package pinouts and signal descriptions
Table 7.
Port
pin
C[1]
C[2]
C[3]
C[4]
C[5]
C[6]
C[7]
C[8]
40/103
SPC560P34L1, SPC560P34L3, SPC560P40L1,
Pin muxing (continued)
I/O
direction(4)
Pad speed(5)
Pin
PCR
register
Alternate
function(1),(2)
Functions
PCR[33]
ALT0
ALT1
ALT2
ALT3
—
GPIO[33]
—
—
—
AN[2]
SIUL
—
—
—
ADC_0
Input only
—
—
19
28
PCR[34]
ALT0
ALT1
ALT2
ALT3
—
GPIO[34]
—
—
—
AN[3]
SIUL
—
—
—
ADC_0
Input only
—
—
21
30
PCR[35]
ALT0
ALT1
ALT2
ALT3
—
GPIO[35]
CS1
—
TXD
EIRQ[21]
SIUL
DSPI_0
—
LIN_1
SIUL
I/O
O
—
O
I
Slow
Medium
—
10
PCR[36]
ALT0
ALT1
ALT2
ALT3
—
GPIO[36]
CS0
X[1]
DEBUG[4]
EIRQ[22]
SIUL
DSPI_0
FlexPWM_0
SSCM
SIUL
I/O
I/O
O
—
I
Slow
Medium
—
5
PCR[37]
ALT0
ALT1
ALT2
ALT3
—
GPIO[37]
SCK
—
DEBUG[5]
EIRQ[23]
SIUL
DSPI_0
—
SSCM
SIUL
I/O
I/O
—
—
I
Slow
Medium
—
7
PCR[38]
ALT0
ALT1
ALT2
ALT3
—
GPIO[38]
SOUT
B[1]
DEBUG[6]
EIRQ[24]
SIUL
DSPI_0
FlexPWM_0
SSCM
SIUL
I/O
O
O
—
I
Slow
Medium
—
98
PCR[39]
ALT0
ALT1
ALT2
ALT3
—
GPIO[39]
—
A[1]
DEBUG[7]
SIN
SIUL
—
FlexPWM_0
SSCM
DSPI_0
I/O
—
O
—
I
Slow
Medium
—
9
PCR[40]
ALT0
ALT1
ALT2
ALT3
GPIO[40]
CS1
—
CS6
SIUL
DSPI_1
—
DSPI_0
I/O
O
—
O
Slow
Medium
57
91
Peripheral(3)
Doc ID 16100 Rev 7
SRC = 0 SRC = 1 64-pin 100-pin
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descripTable 7.
Port
pin
Pin muxing (continued)
I/O
direction(4)
Pad speed(5)
Pin
PCR
register
Alternate
function(1),(2)
Functions
PCR[41]
ALT0
ALT1
ALT2
ALT3
GPIO[41]
CS3
—
X[3]
SIUL
DSPI_2
—
FlexPWM_0
I/O
O
—
O
Slow
Medium
—
84
C[10] PCR[42]
ALT0
ALT1
ALT2
ALT3
—
GPIO[42]
CS2
—
A[3]
FAULT[1]
SIUL
DSPI_2
—
FlexPWM_0
FlexPWM_0
I/O
O
—
O
I
Slow
Medium
—
78
C[11]
PCR[43]
ALT0
ALT1
ALT2
ALT3
GPIO[43]
ETC[4]
CS2
—
SIUL
eTimer_0
DSPI_2
—
I/O
I/O
O
—
Slow
Medium
33
55
C[12] PCR[44]
ALT0
ALT1
ALT2
ALT3
GPIO[44]
ETC[5]
CS3
—
SIUL
eTimer_0
DSPI_2
—
I/O
I/O
O
—
Slow
Medium
34
56
C[13] PCR[45]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[45]
—
—
—
EXT_IN
EXT_SYNC
SIUL
—
—
—
CTU_0
FlexPWM_0
I/O
—
—
—
I
I
Slow
Medium
—
71
C[14] PCR[46]
ALT0
ALT1
ALT2
ALT3
GPIO[46]
—
EXT_TGR
—
SIUL
—
CTU_0
—
I/O
—
O
—
Slow
Medium
—
72
C[15] PCR[47]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[47]
—
—
A[1]
EXT_IN
EXT_SYNC
SIUL
—
—
FlexPWM_0
CTU_0
FlexPWM_0
I/O
—
—
O
I
I
Slow
Medium
—
85
I/O
—
—
O
Slow
Medium
—
86
C[9]
Peripheral(3)
SRC = 0 SRC = 1 64-pin 100-pin
Port D (16-bit)
D[0]
PCR[48]
ALT0
ALT1
ALT2
ALT3
GPIO[48]
—
—
B[1]
SIUL
—
—
FlexPWM_0
Doc ID 16100 Rev 7
41/103
Package pinouts and signal descriptions
Table 7.
Port
pin
SPC560P34L1, SPC560P34L3, SPC560P40L1,
Pin muxing (continued)
I/O
direction(4)
Pad speed(5)
Pin
PCR
register
Alternate
function(1),(2)
Functions
PCR[49]
ALT0
ALT1
ALT2
ALT3
GPIO[49]
—
—
EXT_TRG
SIUL
—
—
CTU_0
I/O
—
—
O
Slow
Medium
—
3
PCR[50]
ALT0
ALT1
ALT2
ALT3
GPIO[50]
—
—
X[3]
SIUL
—
—
FlexPWM_0
I/O
—
—
O
Slow
Medium
—
97
PCR[51]
ALT0
ALT1
ALT2
ALT3
GPIO[51]
—
—
A[3]
SIUL
—
—
FlexPWM_0
I/O
—
—
O
Slow
Medium
—
89
PCR[52]
ALT0
ALT1
ALT2
ALT3
GPIO[52]
—
—
B[3]
SIUL
—
—
FlexPWM_0
I/O
—
—
O
Slow
Medium
—
90
PCR[53]
ALT0
ALT1
ALT2
ALT3
GPIO[53]
CS3
F[0]
—
SIUL
DSPI_0
FCU_0
—
I/O
O
O
—
Slow
Medium
—
22
PCR[54]
ALT0
ALT1
ALT2
ALT3
—
GPIO[54]
CS2
—
—
FAULT[1]
SIUL
DSPI_0
—
—
FlexPWM_0
I/O
O
—
—
I
Slow
Medium
—
23
PCR[55]
ALT0
ALT1
ALT2
ALT3
GPIO[55]
CS3
F[1]
CS4
SIUL
DSPI_1
FCU_0
DSPI_0
I/O
O
O
O
Slow
Medium
17
26
PCR[56]
ALT0
ALT1
ALT2
ALT3
GPIO[56]
CS2
—
CS5
SIUL
DSPI_1
—
DSPI_0
I/O
O
—
O
Slow
Medium
14
21
PCR[57]
ALT0
ALT1
ALT2
ALT3
GPIO[57]
X[0]
TXD
—
SIUL
FlexPWM_0
LIN_1
—
I/O
O
O
—
Slow
Medium
8
15
D[10] PCR[58]
ALT0
ALT1
ALT2
ALT3
GPIO[58]
A[0]
—
—
SIUL
FlexPWM_0
—
—
I/O
O
—
—
Slow
Medium
—
53
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
42/103
Peripheral(3)
Doc ID 16100 Rev 7
SRC = 0 SRC = 1 64-pin 100-pin
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Package pinouts and signal descripTable 7.
Port
pin
Pin muxing (continued)
I/O
direction(4)
Pad speed(5)
Pin
PCR
register
Alternate
function(1),(2)
Functions
PCR[59]
ALT0
ALT1
ALT2
ALT3
GPIO[59]
B[0]
—
—
SIUL
FlexPWM_0
—
—
I/O
O
—
—
Slow
Medium
—
54
D[12] PCR[60]
ALT0
ALT1
ALT2
ALT3
—
GPIO[60]
X[1]
—
—
RXD
SIUL
FlexPWM_0
—
—
LIN_1
I/O
O
—
—
I
Slow
Medium
45
70
D[13] PCR[61]
ALT0
ALT1
ALT2
ALT3
GPIO[61]
A[1]
—
—
SIUL
FlexPWM_0
—
—
I/O
O
—
—
Slow
Medium
44
67
D[14] PCR[62]
ALT0
ALT1
ALT2
ALT3
GPIO[62]
B[1]
—
—
SIUL
FlexPWM_0
—
—
I/O
O
—
—
Slow
Medium
46
73
D[15] PCR[63]
ALT0
ALT1
ALT2
ALT3
—
—
—
—
—
41
D[11]
Peripheral(3)
SIUL
GPIO[63]
—
—
—
—
Input only
—
—
ADC_0
AN[10]
emu. AN[4] emu. ADC_1(6)
SRC = 0 SRC = 1 64-pin 100-pin
Port E (16-bit)
E[1]
E[2]
E[3]
PCR[65]
ALT0
ALT1
ALT2
ALT3
—
GPIO[65]
—
—
—
AN[4]
SIUL
—
—
—
ADC_0
Input only
—
—
18
27
PCR[66]
ALT0
ALT1
ALT2
ALT3
—
GPIO[66]
—
—
—
AN[5]
SIUL
—
—
—
ADC_0
Input only
—
—
23
32
PCR[67]
ALT0
ALT1
ALT2
ALT3
—
GPIO[67]
—
—
—
AN[6]
SIUL
—
—
—
ADC_0
Input only
—
—
30
42
Doc ID 16100 Rev 7
43/103
Package pinouts and signal descriptions
Table 7.
Port
pin
E[4]
E[5]
E[6]
E[7]
SPC560P34L1, SPC560P34L3, SPC560P40L1,
Pin muxing (continued)
I/O
direction(4)
Pad speed(5)
Pin
PCR
register
Alternate
function(1),(2)
Functions
PCR[68]
ALT0
ALT1
ALT2
ALT3
—
GPIO[68]
—
—
—
AN[7]
SIUL
—
—
—
ADC_0
Input only
—
—
—
44
PCR[69]
ALT0
ALT1
ALT2
ALT3
—
GPIO[69]
—
—
—
AN[8]
SIUL
—
—
—
ADC_0
Input only
—
—
—
43
PCR[70]
ALT0
ALT1
ALT2
ALT3
—
GPIO[70]
—
—
—
AN[9]
SIUL
—
—
—
ADC_0
Input only
—
—
—
45
PCR[71]
ALT0
ALT1
ALT2
ALT3
—
GPIO[71]
—
—
—
AN[10]
SIUL
—
—
—
ADC_0
Input only
—
—
—
41
Peripheral(3)
SRC = 0 SRC = 1 64-pin 100-pin
1. ALT0 is the primary (default) function for each port after reset.
2. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIU module. PCR.PA = 00 → ALT0;
PCR.PA = 01 → ALT1; PCR.PA = 10 → ALT2; PCR.PA = 11 → ALT3. This is intended to select the output functions; to
use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA
bitfields. For this reason, the value corresponding to an input only function is reported as “—”.
3. Module included on the MCU.
4. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMIO.PADSELx bitfields inside the SIUL module.
5. Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.
6. ADC0.AN emulates ADC1.AN. This feature is used to provide software compatibility between SPC560P34/SPC560P40
and SPC560P50. Refer to ADC chapter of reference manual for more details.
44/103
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
3
Electrical characteristics
3.1
Introduction
Electrical characteristics
This section contains device electrical characteristics as well as temperature and power
considerations.
This microcontroller contains input protection against damage due to high static voltages.
However, it is advisable to take precautions to avoid application of any voltage higher than
the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD
or VSS). This can be done by the internal pull-up or pull-down resistors, which are provided
by the device for most general purpose pins.
The following tables provide the device characteristics and its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.
Caution:
All of the following parameter values can vary depending on the application and must be
confirmed during silicon characterization or silicon reliability trial.
3.2
Parameter classification
The electrical parameters are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 8 are used and the parameters are tagged
accordingly in the tables where appropriate.
Table 8.
Parameter classifications
Classification tag
Note:
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from
typical devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.
D
Those parameters are derived mainly from simulations.
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
Doc ID 16100 Rev 7
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Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
3.3
Absolute maximum ratings
Table 9.
Absolute maximum ratings(1)
Value
Symbol
Parameter
Conditions
Min
Max(2)
Unit
S
R
Device ground
—
0
0
V
S
R
3.3 V/5.0 V input/output supply
voltage (supply).
Code flash memory supply with
VDD_HV_IO3 and data flash memory
with VDD_HV_IO2
—
–0.3
6.0
V
VSS_HV_IOx
S
R
3.3 V/5.0 V input/output supply
voltage (ground).
Code flash memory ground with
VSS_HV_IO3 and data flash memory
with VSS_HV_IO2
—
–0.1
0.1
V
6.0
VDD_HV_OSC
—
3.3 V/5.0 V crystal oscillator amplifier
Relative to
supply voltage (supply)
VDD_HV_IOx
–0.3
S
R
–0.3
VDD_HV_IOx + 0.3
VSS_HV_OSC
S
R
3.3 V/5.0 V crystal oscillator amplifier
supply voltage (ground)
–0.1
0.1
–0.3
VDD_HV_REG + 0.3
VSS
VDD_HV_IOx(3)
VDD_HV_ADC0
S
R
3.3 V/5.0 V ADC_0 supply and highreference voltage
—
VDD_HV_REG
< 2.7 V
V
V
V
VDD_HV_REG
> 2.7 V
–0.3
6.0
—
–0.1
0.1
—
–0.3
6.0
–0.3
VDD_HV_IOx + 0.3
VSS_HV_ADC0
S
R
3.3 V/5.0 V ADC_0 ground and lowreference voltage
VDD_HV_REG
S
R
3.3 V/5.0 V voltage-regulator supply
voltage
TVDD
S
R
Slope characteristics on all VDD
during power up(4) with respect to
ground (VSS)
—
3.0(5)
500 x 103
(0.5 [V/µs])
V/s
VDD_LV_CORx
C
C
1.2 V supply pins for core logic
(supply)
—
–0.1
1.5
V
VSS_LV_CORx
S
R
1.2 V supply pins for core logic
(ground)
—
–0.1
0.1
V
—
–0.3
6.0
VIN
S
R
Voltage on any pin with respect to
ground (VSS_HV_IOx)
VDD_HV_IOx + 0.3
V
–0.3
S
R
Input current on any pin during
overload condition
–10
10
mA
IINJPAD
46/103
Relative to
VDD_HV_IOx
Relative to
VDD_HV_IOx
—
Doc ID 16100 Rev 7
V
V
(6)
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Table 9.
Electrical characteristics
Absolute maximum ratings(1) (continued)
Value
Symbol
Parameter
Conditions
Min
Max(2)
Unit
IINJSUM
S
R
Absolute sum of all input currents
during overload condition
—
–50
50
mA
TSTG
S
R
Storage temperature
—
–55
150
°C
TJ
S
R
Junction temperature under bias
—
−40
150
°C
1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.
2. Absolute maximum voltages are currently maximum burn-in voltages.
3. The difference between each couple of voltage supplies must be less than 300 mV, ⏐VDD_HV_IOy – VDD_HV_IOx⏐ < 300 mV.
4. Guaranteed by device validation.
5. Minimum value of TVDD must be guaranteed until VDD_HV_REG reaches 2.6 V (maximum value of VPORH)
6. Only when VDD_HV_IOx < 5.2 V
Figure 6 shows the constraints of the different power supplies.
VDD_HV_xxx
6.0 V
VDD_HV_IOx
–0.3 V
–0.3 V
Figure 6.
6.0 V
Power supplies constraints (–0.3 V ≤ VDD_HV_IOx ≤ 6.0 V)
The SPC560P34/SPC560P40 supply architecture allows the ADC supply to be managed
independently from the standard VDD_HV supply. Figure 7 shows the constraints of the ADC
power supply.
Doc ID 16100 Rev 7
47/103
Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
VDD_HV_ADCx
6.0 V
VDD_HV_REG
–0.3 V
Figure 7.
6.0 V
2.7 V
–0.3 V
Independent ADC supply (–0.3 V ≤ VDD_HV_REG ≤ 6.0 V)
3.4
Recommended operating conditions
Table 10.
Recommended operating conditions (5.0 V)
Value
Symbol
VSS
Parameter
Conditions
SR Device ground
Unit
Min
Max(1)
—
0
0
V
VDD_HV_IOx(2)
SR
5.0 V input/output supply
voltage
—
4.5
5.5
V
VSS_HV_IOx
SR
Input/output ground
voltage
—
0
0
V
—
4.5
5.5
VDD_HV_OSC
5.0 V crystal oscillator
SR
amplifier supply voltage
VDD_HV_IOx – 0.1
VDD_HV_IOx + 0.1
VSS_HV_OSC
5.0 V crystal oscillator
SR amplifier reference
voltage
—
0
0
—
4.5
5.5
VDD_HV_REG
5.0 V voltage regulator
SR
supply voltage
VDD_HV_IOx – 0.1
VDD_HV_IOx + 0.1
48/103
Relative to
VDD_HV_IOx
Relative to
VDD_HV_IOx
Doc ID 16100 Rev 7
V
V
V
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Table 10.
Electrical characteristics
Recommended operating conditions (5.0 V) (continued)
Value
Symbol
Parameter
Max(1)
4.5
5.5
VDD_HV_REG – 0.1
—
—
0
0
V
CC Internal supply voltage
—
—
—
V
Internal reference
voltage
—
0
0
V
—
—
—
V
—
0
0
V
fCPU = 60 MHz
−40
125
°C
fCPU = 64 MHz
−40
105
°C
SR
VSS_HV_ADC0
SR
,(4)
Unit
Min
VDD_HV_ADC0
VDD_LV_REGCOR(3)
Conditions
VSS_LV_REGCOR(3) SR
—
5.0 V ADC_0 supply and
Relative to
high reference voltage
VDD_HV_REG
ADC_0 ground and low
reference voltage
VDD_LV_CORx(3),(4) CC Internal supply voltage
VSS_LV_CORx(3)
SR
Internal reference
voltage
TA
SR
Ambient temperature
under bias
V
1. Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, ADC electrical characteristics and
I/Os DC electrical specification may not be guaranteed.
2. The difference between each couple of voltage supplies must be less than 100 mV, ⏐VDD_HV_IOy –
VDD_HV_IOx⏐ < 100 mV.
3. To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an onchip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to high
voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast
emitter.
4. The low voltage supplies (VDD_LV_xxx) are not all independent.
– VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low
voltage supply to the data flash memory module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
– VDD_LV_REGCOR and VDD_LV_RECORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Table 11.
Recommended operating conditions (3.3 V)
Value
Symbol
VSS
Parameter
Conditions
SR Device ground
Unit
Min
Max(1)
—
0
0
V
VDD_HV_IOx(2)
SR
3.3 V input/output supply
voltage
—
3.0
3.6
V
VSS_HV_IOx
SR
Input/output ground
voltage
—
0
0
V
—
3.0
3.6
VDD_HV_OSC
3.3 V crystal oscillator
SR
amplifier supply voltage
VSS_HV_OSC
3.3 V crystal oscillator
SR amplifier reference
voltage
Relative to
VDD_HV_IOx
—
Doc ID 16100 Rev 7
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
0
0
V
49/103
Electrical characteristics
Table 11.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Recommended operating conditions (3.3 V) (continued)
Value
Symbol
Parameter
Conditions
—
VDD_HV_REG
SR
VDD_HV_ADC0
SR
VSS_HV_ADC0
SR
VDD_LV_REGCOR(3)
,(4)
3.3 V voltage regulator
supply voltage
Relative to
VDD_HV_IOx
Max(1)
3.0
3.6
Unit
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
3.0
5.5
VDD_HV_REG −
0.1
5.5
—
0
0
V
CC Internal supply voltage
—
—
—
V
Internal reference
voltage
—
0
0
V
—
—
—
V
—
0
0
V
fCPU = 60 MHz
−40
125
°C
fCPU = 64 MHz
−40
105
°C
VSS_LV_REGCOR(3) SR
—
3.3 V ADC_0 supply and
Relative to
high reference voltage
VDD_HV_REG
Min
ADC_0 ground and low
reference voltage
VDD_LV_CORx(3),(4) CC Internal supply voltage
VSS_LV_CORx(3)
SR
Internal reference
voltage
TA
SR
Ambient temperature
under bias
V
1. Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and
I/Os DC electrical specification may not be guaranteed.
2. The difference between each couple of voltage supplies must be less than 100 mV, ⏐VDD_HV_IOy –
VDD_HV_IOx⏐ < 100 mV.
3. To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an onchip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to high
voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast
emitter.
4. The low voltage supplies (VDD_LV_xxx) are not all independent.
– VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low
voltage supply to the data flash memory module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
– VDD_LV_REGCOR and VDD_LV_RECORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Figure 8 shows the constraints of the different power supplies.
50/103
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Figure 8.
Electrical characteristics
Power supplies constraints (3.0 V ≤ VDD_HV_IOx ≤ 5.5 V)
VDD_HV_xxx
5.5 V
3.3 V
3.0 V
VDD_HV_IOx
3.0 V
5.5 V
3.3 V
Note: IO AC and DC characteristics are guaranteed only in the range of 3.0–3.6 V when
PAD3V5V is low, and in the range of 4.5–5.5 V when PAD3V5V is high.
The SPC560P34/SPC560P40 supply architecture allows the ADC supply to be managed
independently from the standard VDD_HV supply. Figure 9 shows the constraints of the ADC
power supply.
Figure 9.
Independent ADC supply (3.0 V ≤ VDD_HV_REG ≤ 5.5 V)
VDD_HV_ADCx
5.5 V
3.0 V
VDD_HV_REG
3.0 V
Doc ID 16100 Rev 7
5.5 V
51/103
Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
3.5
Thermal characteristics
3.5.1
Package thermal characteristics
Table 12.
LQFP thermal characteristics
Typical value
Symbol
RθJA
RθJB
Parameter
Thermal resistance junction-to-ambient, natural Single layer board—1s
convection(1)
Four layer board—2s2p
ΨJC
64-pin
63
57
°C/W
51
41
°C/W
Four layer board—2s2p
33
22
°C/W
(top)(3)
Single layer board—1s
15
13
°C/W
Operating conditions
33
22
°C/W
Operating conditions
1
1
°C/W
Junction-to-board, natural convection(4)
Junction-to-case, natural
Unit
100-pin
(2)
Thermal resistance junction-to-board
RθJCtop Thermal resistance junction-to-case
ΨJB
Conditions
convection(5)
1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets JEDEC specification
for this package.
2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package. When Greek letters are not available, the symbols are typed as RthJB or Theta-JB.
3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
4. Thermal characterization parameter indicating the temperature difference between the board and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.
5. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JC.
3.5.2
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
Equation 1: TJ = TA + (RθJA * PD)
where:
TA = ambient temperature for the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The junction-to-ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by a
factor of two. Which value is closer to the application depends on the power dissipated by
other components on the board. The value obtained on a single layer board is appropriate
for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are
well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a
junction-to-case thermal resistance and a case-to-ambient thermal resistance:
52/103
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Electrical characteristics
Equation 2: RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resistance (°C/W)
RθJC = junction-to-case thermal resistance (°C/W)
RθCA = case-to-ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal
environment to change the case-to-ambient thermal resistance, RθCA. For instance, the
user can change the size of the heat sink, the air flow around the device, the interface
material, the mounting arrangement on printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are
not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using Equation 3:
Equation 3: TJ = TT + (ΨJT x PD)
where:
TT = thermocouple temperature on top of the package (°C)
ΨJT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40
gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the package.
A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of
wire extending from the junction. The thermocouple wire is placed flat against the package
case to avoid measurement errors caused by cooling effects of the thermocouple wire.
References:
●
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134U.S.A.
(408) 943-6900
●
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global
Engineering Documents at (800) 854-7179 or (303) 397-7956.
●
JEDEC specifications are available on the WEB at http://www.jedec.org.
●
C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module, Proceedings of SemiTherm, San Diego, 1998,
pp. 47–54.
●
G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled
Applications, Electronic Packaging and Production, pp. 53–58, March 1998.
●
B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling, Proceedings of SemiTherm, San
Diego, 1999, pp. 212–220.
Doc ID 16100 Rev 7
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Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
3.6
Electromagnetic interference (EMI) characteristics
Table 13.
EMI testing specifications
Symbol
Parameter
Conditions
VDD = 5.0 V; TA = 25 °C
VEME
Radiated
emissions
Frequency
Level
(Typ)
150 kHz–150 MHz
11
150–1000 MHz
13
dBµ
V
M
—
8
12
dBµ
V
N
—
150 kHz–150 MHz
9
150–1000 MHz
12
dBµ
V
M
—
7
12
dBµ
V
N
—
Clocks
fOSC = 8 MHz
fCPU = 64 MHz
No PLL frequency
modulation
IEC level
Other device configuration,
f
= 8 MHz
150 kHz–150 MHz
test conditions and EM testing OSC
f
=
64
MHz
CPU
per standard IEC61967-2
150–1000 MHz
±4% PLL frequency
IEC level
modulation
VDD = 3.3 V; TA = 25 °C
fOSC = 8 MHz
fCPU = 64 MHz
No PLL frequency
modulation
IEC level
Other device configuration,
f
= 8 MHz
150 kHz–150 MHz
test conditions and EM testing OSC
f
=
64
MHz
CPU
per standard IEC61967-2
150–1000 MHz
±4% PLL frequency
IEC level
modulation
3.7
Electrostatic discharge (ESD) characteristics
Table 14.
ESD ratings(1),(2)
Symbol
Parameter
Unit
Conditions
Value
Unit
2000
V
VESD(HBM)
S
Electrostatic discharge (Human Body Model)
R
—
VESD(CDM)
S
Electrostatic discharge (Charged Device Model)
R
—
750 (corners)
V
500 (other)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
3.8
Power management electrical characteristics
3.8.1
Voltage regulator electrical characteristics
The internal voltage regulator requires an external NPN ballast, approved ballast list
availbale in Table 15, to be connected as shown in Figure 10. Capacitances should be
placed on the board as near as possible to the associated pins. Care should also be taken
to limit the serial inductance of the VDD_HV_REG, BCTRL and VDD_LV_CORx pins to less than
LReg. (refer to Table 16).
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Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Note:
Electrical characteristics
The voltage regulator output cannot be used to drive external circuits. Output pins are to be
used only for decoupling capacitance.
VDD_LV_COR must be generated using internal regulator and external NPN transistor. It is
not possible to provide VDD_LV_COR through external regulator.
For the SPC560P34/SPC560P40 microcontroller, capacitor(s), with total values not below
CDEC1, should be placed between VDD_LV_CORx/VSS_LV_CORx close to external ballast
transistor emitter. 4 capacitors, with total values not below CDEC2, should be placed close to
microcontroller pins between each VDD_LV_CORx/VSS_LV_CORx supply pairs and the
VDD_LV_REGCOR/VSS_LV_REGCOR pair . Additionally, capacitor(s) with total values not below
CDEC3, should be placed between the VDD_HV_REG/VSS_HV_REG pins close to ballast
collector. Capacitors values have to take into account capacitor accuracy, aging and
variation versus temperature.
All reported information are valid for voltage and temperature ranges described in
recommended operating condition, Table 10 and Table 11.
Figure 10. Voltage regulator configuration
VDD_HV_REG
SPC560P34/SPC560P
CDEC3
BJT(1)
BCTRL
VDD_LV_COR
CDEC2
CDEC1
1. Refer to Table 15.
Table 15.
Approved NPN ballast components
Part
Manufacturer
Approved derivatives(1)
ON Semi
BCP68
NXP
BCP68-25
Infineon
BCP68-25
BCX68
Infineon
BCX68-10; BCX68-16; BCX-25
BC868
NXP
BC868
BCP68
Doc ID 16100 Rev 7
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Electrical characteristics
Table 15.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Approved NPN ballast components
Part
Approved derivatives(1)
Manufacturer
Infineon
BC817-16; BC817-25; BC817SU
NXP
BC817-16; BC817-25
ST
BCP56-16
Infineon
BCP56-10; BCP56-16
ON Semi
BCP56-10
NXP
BCP56-10; BCP56-16
BC817
BCP56
1. For automotive applications please check with the appropriate transistor vendor for automotive grade certification
Table 16.
Voltage regulator electrical characteristics
Value
Symbol
C
Parameter
Conditions
Unit
Min
VDD_LV_REGCOR
CDEC1
C
C
S
R
Output voltage under
P maximum load run supply
current configuration
—
External decoupling/stability
ceramic capacitor
Post-trimming
1.15
—
1.32
V
BJT from Table 15. Three
capacitors (i.e. X7R or X8R
capacitors) with nominal
value of 10 µF
19.5
30
—
µF
BJT BC817, one capacitance
of 22 µF
14.3
22
—
µF
—
—
45
mΩ
Four capacitances (i.e. X7R
or X8R capacitors) with
nominal value of 440 nF
120
0
176
0
—
nF
Three capacitors (i.e. X7R or
X8R capacitors) with nominal
value of 10 µF; CDEC3 has to
be equal or greater than
CDEC1
19.5
30
—
µF
—
—
—
5
nH
RREG
S
R
—
Absolute maximum value
Resulting ESR of either one or
between 100 kHz and
all three CDEC1
10 MHz
CDEC2
S
R
—
External decoupling/stability
ceramic capacitor
CDEC3
S
R
External decoupling/stability
— ceramic capacitor on
VDD_HV_REG
LReg
S
R
—
56/103
Typ Max
Resulting ESL of VDD_HV_REG,
BCTRL and VDD_LV_CORx pins
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
3.8.2
Electrical characteristics
Voltage monitor electrical characteristics
The device implements a power on reset module to ensure correct power-up initialization,
as well as three low voltage detectors to monitor the VDD and the VDD_LV voltage while
device is supplied:
Table 17.
●
POR monitors VDD during the power-up phase to ensure device is maintained in a safe
reset state
●
LVDHV3 monitors VDD to ensure device reset below minimum functional supply
●
LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range
●
LVDLVCOR monitors low voltage digital power domain
Low voltage monitor electrical characteristics
Symbol
C
Parameter
Value
Conditions(1)
Unit
Min
Max
—
1.5
2.7
V
TA = 25 °C
1.0
—
V
VPORH
T
Power-on reset threshold
VPORUP
P
Supply for functional POR module
VREGLVDMOK_H
P
Regulator low voltage detector high threshold
—
—
2.95
V
VREGLVDMOK_L
P
Regulator low voltage detector low threshold
—
2.6
—
V
VFLLVDMOK_H
P
Flash low voltage detector high threshold
—
—
2.95
V
VFLLVDMOK_L
P
Flash low voltage detector low threshold
—
2.6
—
V
VIOLVDMOK_H
P
I/O low voltage detector high threshold
—
—
2.95
V
VIOLVDMOK_L
P
I/O low voltage detector low threshold
—
2.6
—
V
VIOLVDM5OK_H
P
I/O 5 V low voltage detector high threshold
—
—
4.4
V
VIOLVDM5OK_L
P
I/O 5 V low voltage detector low threshold
—
3.8
—
V
VMLVDDOK_H
P
Digital supply low voltage detector high
—
—
1.145
V
VMLVDDOK_L
P
Digital supply low voltage detector low
—
1.08
—
V
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 °C to TA MAX, unless otherwise specified
3.9
Power up/down sequencing
To prevent an overstress event or a malfunction within and outside the device, the
SPC560P34/SPC560P40 implements the following sequence to ensure each module is
started only when all conditions for switching it ON are available:
●
A POWER_ON module working on voltage regulator supply controls the correct startup of the regulator. This is a key module ensuring safe configuration for all voltage
regulator functionality when supply is below 1.5 V. Associated POWER_ON (or POR)
signal is active low.
●
Several low voltage detectors, working on voltage regulator supply monitor the voltage
of the critical modules (voltage regulator, I/Os, flash memory and low voltage domain).
LVDs are gated low when POWER_ON is active.
●
A POWER_OK signal is generated when all critical supplies monitored by the LVD are
available. This signal is active high and released to all modules including I/Os, flash
Doc ID 16100 Rev 7
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Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
memory and 16 MHz RC oscillator needed during power-up phase and reset phase.
When POWER_OK is low the associated modules are set into a safe state.
Figure 11.
Power-up typical sequence
VDD_HV_REG
VPORH
VLVDHV3H
3.3V
VPOR_UP
0V
3.3V
POWER_ON
0V
3.3V
LVDM (HV)
0V
VDD_LV_REGCOR
VMLVDOK_H
1.2V
0V
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
~1us
Internal Reset Generation Module
FSM
P0
P1
1.2V
0V
Figure 12. Power-down typical sequence
VDD_HV_REG
VLVDHV3L
VPORH
3.3V
0V
3.3V
LVDM (HV)
0V
3.3V
POWER_ON
0V
1.2V
0V
VDD_LV_REGCOR
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
Internal Reset Generation Module
FSM
IDLE
58/103
P0
Doc ID 16100 Rev 7
1.2V
0V
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Electrical characteristics
Figure 13. Brown-out typical sequence
VLVDHV3L
VDD_HV_REG
VLVDHV3H
3.3V
0V
3.3V
LVDM (HV)
0V
3.3V
POWER_ON
0V
1.2V
0V
VDD_LV_REGCOR
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
~1us
Internal Reset Generation Module
FSM
IDLE
P0
3.10
DC electrical characteristics
3.10.1
NVUSRO register
P1
1.2V
0V
Portions of the device configuration, such as high voltage supply and watchdog
enable/disable after reset are controlled via bit values in the non-volatile user options
(NVUSRO) register.
For a detailed description of the NVUSRO register, please refer to the device reference
manual.
NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 18 shows
how NVUSRO[PAD3V5V] controls the device configuration.
Table 18.
PAD3V5V field description
Value(1)
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
1. Default manufacturing value before flash initialization is ‘1’ (3.3 V).
Doc ID 16100 Rev 7
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Electrical characteristics
3.10.2
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
DC electrical characteristics (5 V)
Table 19 gives the DC electrical characteristics at 5 V (4.5 V < VDD_HV_IOx < 5.5 V,
NVUSRO[PAD3V5V] = 0).
Table 19.
DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)
Value
Symbol
C
Parameter
Conditions
Max
—
−0.4(1)
—
V
P
—
—
0.35 VDD_HV_IOx
V
P
—
0.65 VDD_HV_IOx
—
V
—
—
VDD_HV_IOx + 0.4
(1)
V
—
0.1 VDD_HV_IOx
—
V
D
VIL
VIH
Unit
Min
Low level input voltage
High level input voltage
D
VHYS
T
Schmitt trigger hysteresis
VOL_S
P
Slow, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_S
P
Slow, high level output voltage
IOH = −3 mA
0.8 VDD_HV_IOx
—
V
VOL_M
P
Medium, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_M
P
Medium, high level output
voltage
IOH = −3 mA
0.8 VDD_HV_IOx
—
V
VOL_F
P
Fast, low level output voltage
IOL = 14 mA
—
0.1 VDD_HV_IOx
V
VOH_F
P
Fast, high level output voltage
IOH = −14 mA
0.8 VDD_HV_IOx
—
V
P
Equivalent pull-up current
VIN = VIL
−130
—
IPU
VIN = VIH
—
−10
—
P
VIN = VIL
10
IPD
VIN = VIH
—
130
IIL
P
Input leakage current
(all bidirectional ports)
TA = −40 to 125 °C
−1
1
µA
IIL
P
Input leakage current
(all ADC input-only ports)
TA = −40 to 125 °C
−0.5
0.5
µA
CIN
D Input capacitance
—
—
10
pF
Equivalent pull-down current
µA
1. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.
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Doc ID 16100 Rev 7
µA
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Table 20.
Electrical characteristics
Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)
Value(1)
Symbol
C
Parameter
T
Conditions
Max
40 MHz
44
55
64 MHz
52
65
40 MHz
38
46
64 MHz
45
54
HALT mode(4)
—
1.5
10
mode(5)
—
1
10
VDD_HV_FL at 5.0 V
—
8
10
Flash during erase
at 5.0 V
V
operation on 1 flash module DD_HV_FL
—
15
19
RUN—Maximum mode(2)
P
P
VDD_LV_CORx externally
forced at 1.3 V
RUN—Typical mode(3)
T
Supply current
IDD_LV_CORx
Unit
Typ
STOP
Flash during read
IDD_FLASH
T
IDD_ADC
T
ADC
VDD_HV_ADC0 at 5.0 V
fADC = 16 MHz
ADC_0
3
4
IDD_OSC
T
Oscillator
VDD_HV_OSC at 5.0 V
8 MHz
2.6
3.2
IDD_HV_REG
D
Internal regulator module
current consumption
VDD_HV_REG at 5.5 V
—
10
mA
1. All values to be confirmed after characterization/data collection.
2. Maximum mode: FlexPWM, ADC, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0 enabled, 125 °C ambient. I/O
supply current excluded.
3. Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0, 105 °C ambient. I/O supply current
excluded.
4. Halt mode configurations: Code fetched from SRAM, code flash memory and data flash memory in low power mode,
OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.
5. STOP “P” mode Device Under Test (DUT) configuration: Code fetched from SRAM, code flash memory and data flash
memory off, OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.
Doc ID 16100 Rev 7
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Electrical characteristics
3.10.3
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
DC electrical characteristics (3.3 V)
Table 21 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V,
NVUSRO[PAD3V5V] = 1); see Figure 14.
DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)(1)
Table 21.
Value
Symbol C
Parameter
Conditions
Unit
Min
Max
—
−0.4(2)
—
V
—
—
0.35 VDD_HV_IOx
V
—
0.65 VDD_HV_IOx
—
V
D
—
—
VDD_HV_IOx + 0.4(2)
V
VHYS
T Schmitt trigger hysteresis
—
0.1 VDD_HV_IOx
—
V
VOL_S
P Slow, low level output voltage
IOL = 1.5 mA
—
0.5
V
VOH_S
P Slow, high level output voltage
IOH = −1.5 mA
VDD_HV_IOx − 0.8
—
V
VOL_M
P Medium, low level output voltage
IOL = 2 mA
—
0.5
V
VOH_M
P Medium, high level output voltage
IOH = −2 mA
VDD_HV_IOx − 0.8
—
V
VOL_F
P Fast, low level output voltage
IOL = 11 mA
—
0.5
V
VOH_F
P Fast, high level output voltage
IOH = −11 mA
VDD_HV_IOx − 0.8
—
V
VIN = VIL
−130
—
VIN = VIH
—
−10
VIN = VIL
10
—
VIN = VIH
—
130
D
VIL
Low level input voltage
P
P
VIH
High level input voltage
IPU
P Equivalent pull-up current
IPD
P Equivalent pull-down current
IIL
P
Input leakage current (all
bidirectional ports)
TA = −40 to 125 °C
—
1
µA
IIL
P
Input leakage current (all ADC
input-only ports)
TA = −40 to 125 °C
—
0.5
µA
CIN
D Input capacitance
—
—
10
pF
µA
1. These specifications are design targets and subject to change per device characterization.
2. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.
62/103
Doc ID 16100 Rev 7
µA
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Table 22.
Electrical characteristics
Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)
Value(1)
Symbol
C
Parameter
Conditions
RUN—Maximum mode(2)
Unit
Typ
Max
40 MHz
44
55
64 MHz
52
65
40 MHz
38
46
T
VDD_LV_CORx externally
forced at 1.3 V
RUN—Typical mode(3)
P
Supply current
IDD_LV_CORx
64 MHz
45
54
HALT
mode(4)
—
1.5
10
STOP
mode(5)
—
1
10
ADC
VDD_HV_ADC0 at 3.3 V
fADC = 16 MHz
ADC_0
3
4
T
Oscillator
VDD_HV_OSC at 3.3 V
8 MHz
2.6
3.2
D
Internal regulator module
current consumption
VDD_HV_REG at 5.5 V
—
10
IDD_ADC
T
IDD_OSC
IDD_HV_REG
mA
1. All values to be confirmed after characterization/data collection.
2. Maximum mode: FlexPWM, ADC, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0 enabled, 125 °C ambient. I/O
supply current excluded.
3. Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0, 105 °C ambient. I/O supply current
excluded.
4. Halt mode configurations: Code fetched from SRAM, code flash memory and data flash memory in low power mode,
OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.
5. STOP “P” mode Device Under Test (DUT) configuration: Code fetched from SRAM, code flash memory and data flash
memory off, OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.
3.10.4
Input DC electrical characteristics definition
Figure 14 shows the DC electrical characteristics behavior as function of time.
Figure 14. Input DC electrical characteristics definition
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
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Electrical characteristics
3.10.5
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD/VSS supply pair as described in Table 23.
Table 23.
I/O supply segment
Supply segment
Package
1
2
3
4
5
LQFP100
pin15–pin26
pin27–pin46
pin51–pin61
pin64–pin86
pin89–pin10
LQFP64
pin8–pin17
pin18–pin30
pin33–pin38
pin41–pin54
pin57–pin5
Table 24.
Symbol
I/O consumption
C
Value
Conditions(1)
Parameter
Unit
Min Typ Max
ISWTSLW(2)
ISWTMED(2)
ISWTFST(2)
Dynamic I/O current
C
D for SLOW
C
configuration
Dynamic I/O current
C
D for MEDIUM
C
configuration
Dynamic I/O current
C
D for FAST
C
configuration
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CL = 25 pF
CL = 25 pF
CL = 25 pF
IRMSSLW
—
—
16
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
29
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
17
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
110
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
50
—
—
2.3
—
—
3.2
—
—
6.6
—
—
1.6
—
—
2.3
—
—
4.7
—
—
6.6
—
—
13.4
—
—
18.3
—
—
5
—
—
8.5
—
—
11
mA
mA
VDD = 5.0 V ± 10%,
PAD3V5V = 0
mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 2 MHz
CL = 25 pF, 13 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
IRMSMED
64/103
CL = 25 pF, 40 MHz
Root medium square
CL = 100 pF, 13 MHz
C
I/O current for
D
C
MEDIUM
CL = 25 pF, 13 MHz
configuration
VDD = 3.3 V ± 10%,
CL = 25 pF, 40 MHz
PAD3V5V = 1
CL = 100 pF, 13 MHz
Doc ID 16100 Rev 7
20
mA
Root medium square C = 100 pF, 2 MHz
L
C
D I/O current for SLOW
C
CL = 25 pF, 2 MHz
configuration
CL = 25 pF, 4 MHz
—
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 25 pF, 2 MHz
CL = 25 pF, 4 MHz
—
mA
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Table 24.
Symbol
Electrical characteristics
I/O consumption (continued)
C
Value
Conditions(1)
Parameter
Unit
Min Typ Max
CL = 25 pF, 40 MHz
—
—
22
—
—
33
—
—
56
—
—
14
—
—
20
CL = 100 pF, 40 MHz
—
—
35
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
70
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
65
CL = 25 pF, 64 MHz
IRMSFST
Root medium square C = 100 pF, 40 MHz
L
C
D I/O current for FAST
C
C
L = 25 pF, 40 MHz
configuration
CL = 25 pF, 64 MHz
IAVGSEG
VDD = 5.0 V ± 10%,
PAD3V5V = 0
Sum of all the static
S
D I/O current within a
R
supply segment
mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
mA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
3.11
Main oscillator electrical characteristics
The SPC560P34/SPC560P40 provides an oscillator/resonator driver.
Table 25.
Main oscillator output electrical characteristics (5.0 V,
NVUSRO[PAD3V5V] = 0)
Value
Symbol
fOSC
C
Parameter
Conditions
SR — Oscillator frequency
Unit
Min
Max
4
40
MHz
6.5
25
mA/V
gm
—
P Transconductance
VOSC
—
T Oscillation amplitude on XTAL pin
1
—
V
tOSCSU
—
T Start-up time(1),(2)
8
—
ms
T
4 MHz
5
30
T
8 MHz
5
26
12 MHz
5
23
T
16 MHz
5
19
T
20 MHz
5
16
T
40 MHz
5
8
T
CL
CC
XTAL load capacitance(3)
pf
1. The start-up time is dependent upon crystal characteristics, board leakage, etc. High ESR and excessive
capacitive loads can cause long start-up time.
2. Value captured when amplitude reaches 90% of XTAL
3. This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals
specified for this oscillator, load capacitors should not exceed these limits.
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Electrical characteristics
Table 26.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Main oscillator output electrical characteristics (3.3 V,
NVUSRO[PAD3V5V] = 1)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
SR — Oscillator frequency
4
40
MHz
gm
—
P Transconductance
4
20
mA/V
VOSC
—
T Oscillation amplitude on XTAL pin
1
—
V
—
(1),(2)
8
—
ms
fOSC
tOSCSU
T Start-up time
T
4 MHz
5
30
T
8 MHz
5
26
12 MHz
5
23
T
16 MHz
5
19
T
20 MHz
5
16
T
40 MHz
5
8
T
CL
CC
XTAL load capacitance(3)
pf
1. The start-up time is dependent upon crystal characteristics, board leakage, etc. High ESR and excessive
capacitive loads can cause long start-up time.
2. Value captured when amplitude reaches 90% of XTAL
3. This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals
specified for this oscillator, load capacitors should not exceed these limits.
Table 27.
Input clock characteristics
Value
Symbol
Parameter
Unit
Typ
Max
fOSC
SR
Oscillator frequency
4
—
40
MHz
fCLK
SR
Frequency in bypass
—
—
64
MHz
trCLK
SR
Rise/fall time in bypass
—
—
1
ns
tDC
SR
Duty cycle
47.5
50
52.5
%
3.12
FMPLL electrical characteristics
Table 28.
FMPLL electrical characteristics
Symbol
Min
C
Value
Conditions(1)
Parameter
Unit
Min
Max
4
40
MHz
fref_crystal
fref_ext
D
PLL reference frequency range(2)
fPLLIN
D
Phase detector input frequency range
(after pre-divider)
—
4
16
MHz
fFMPLLOUT
D
Clock frequency range in normal mode
—
16
64
MHz
66/103
Crystal reference
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Table 28.
Symbol
Electrical characteristics
FMPLL electrical characteristics (continued)
C
fFREE
P
Free-running frequency
tCYC
D
System clock period
fLORL
D
fLORH
D
fSCM
D
Max
20
150
MHz
—
1/
fSYS
ns
Lower limit
1.6
3.7
Upper limit
24
56
20
150
MHz
fSYS maximum
−4
4
% fCLKOUT
fPLLIN = 16 MHz
(resonator), fPLLCLK at
64 MHz, 4000 cycles
—
10
ns
—
MHz
Self-clocked mode frequency(4),(5)
Short-term
jitter(10)
Long-term jitter
(average over 2 ms
interval)
Unit
Min
Measured using clock
division—typically /16
Loss of reference frequency window(3)
CLKOUT period
jitter(6),(7),(8),(9)
Value
Conditions(1)
Parameter
—
CJITTER
T
tlpll
D
PLL lock time(11), (12)
—
—
200
µs
tdc
D
Duty cycle of reference
—
40
60
%
fLCK
D
Frequency LOCK range
—
−6
6
% fSYS
fUL
D
Frequency un-LOCK range
—
−18
18
% fSYS
fCS
D
fDS
D
fMOD
D
±4.0
Center spread
±0.25
Down spread
−0.5
−8.0
—
70
Modulation depth
Modulation frequency(14)
—
(13)
% fSYS
kHz
1. VDD_LV_CORx = 1.2 V ±10%; VSS = 0 V; TA = –40 to 125 °C, unless otherwise specified
2. Considering operation with PLL not bypassed.
3. “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.
4. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR
window.
5. fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced
mode.
6. This value is determined by the crystal manufacturer and board design.
7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDD_LV_COR0 and VSS_LV_COR0 and variation in crystal oscillator frequency increase the
CJITTER percentage for a given interval.
8. Proper PC board layout procedures must be followed to achieve specifications.
9. Values are obtained with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER
and either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
10. Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.
11. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this
PLL, load capacitors should not exceed these limits.
12. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
13. This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).
14. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
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Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
3.13
16 MHz RC oscillator electrical characteristics
Table 29.
16 MHz RC oscillator electrical characteristics
Value
Symbol
fRC
ΔRCMVAR
3.14
C
Parameter
Conditions
P RC oscillator frequency
Unit
Min
Typ
Max
TA = 25 °C
—
16
—
MHz
—
−5
—
5
%
Fast internal RC oscillator variation over
P temperature and supply with respect to fRC at
TA = 25 °C in high-frequency configuration
Analog-to-digital converter (ADC) electrical characteristics
The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital
converter.
Figure 15. ADC characteristics and error definitions
Offset Error (EO)
Gain Error (EG)
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(5)
(2) The ideal transfer curve
4
(3) Differential non-linearity error (DNL)
(4)
(4) Integral non-linearity error (INL)
3
(5) Center of a step of the actual transfer curve
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error (EO)
68/103
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
3.14.1
Electrical characteristics
Input impedance and ADC accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it
sources charge during the sampling phase, when the analog signal source is a highimpedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the source
impedance value of the transducer or circuit supplying the analog signal to be measured.
The filter at the input pins must be designed taking into account the dynamic characteristics
of the input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: CS and CP2 being substantially two switched capacitances, with a
frequency equal to the ADC conversion rate, it can be seen as a resistive path to ground.
For instance, assuming a conversion rate of 1 MHz, with CS+CP2 equal to 3 pF, a resistance
of 330 kΩ is obtained (REQ = 1 / (fc × (CS+CP2)), where fc represents the conversion rate at
the considered channel). To minimize the error induced by the voltage partitioning between
this resistance (sampled voltage on CS+CP2) and the sum of RS + RF, the external circuit
must be designed to respect the Equation 4:
Equation 4
VA
RS + R F
• --------------------- < 1--- LSB
R EQ
2
Equation 4 generates a constraint for external network design, in particular on resistive
path.
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Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Figure 16. Input equivalent circuit
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
Filter
RS
VA
RF
Current Limiter
Channel
Selection
Sampling
RSW
RAD
RL
CF
CP1
CP2
CS
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW: Channel selection switch impedance
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1 and CP2)
CS: Sampling capacitance
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the
equivalent circuit reported in Figure 16): A charge sharing phenomenon is installed when
the sampling phase is started (A/D switch closed).
Figure 17. Transient behavior during sampling phase
Voltage Transient on CS
VCS
VA
VA2
ΔV < 0.5 LSB
1
2
τ1 < (RSW + RAD) CS 2048 • C S
72/103
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
3.14.2
ADC conversion characteristics
Table 30.
ADC conversion characteristics
Symbol
C
Electrical characteristics
Value
Conditions(1)
Parameter
Unit
Min
Typ
Max
ADC clock frequency (depends on
S
ADC configuration)
—
R
(The duty cycle depends on ADC
clock(2) frequency)
—
3(3)
—
60
MHz
fs
S
— Sampling frequency
R
—
—
—
1.53
MHz
— D Sampling time(4)
fADC = 20 MHz, INPSAMP = 3
125
—
—
ns
ts
fADC = 9 MHz, INPSAMP = 255
—
—
28.2
µs
tc
— P Conversion time(5)
fADC = 20 MHz(6), INPCMP = 1
0.65
0
—
—
µs
ADC power-up delay (time needed
S
— for ADC to settle exiting from
R
software power down; PWDN bit = 0)
—
—
—
1.5
µs
fCK
tADC_P
U
CS(7)
— D ADC input sampling capacitance
—
—
—
2.5
pF
CP1
(7)
— D ADC input pin capacitance 1
—
—
—
3
pF
CP2
(7)
— D ADC input pin capacitance 2
—
—
—
1
pF
VDD_HV_ADC0 = 5 V ± 10%
—
—
0.6
kΩ
VDD_HV_ADC0 = 3.3 V ± 10%
—
—
3
kΩ
—
—
2
kΩ
−5
—
5
mA
RSW(7)
— D Internal resistance of analog source
(7)
— D Internal resistance of analog source
RAD
—
IINJ
— T Input current injection
Current injection on one ADC
input, different from the
converted one. Remains
within TUE specification
INL
C
C
P Integral non-linearity
No overload
−1.5
—
1.5
LSB
DNL
C
C
P Differential non-linearity
No overload
−1.0
—
1.0
LSB
EO
C
C
T Offset error
—
—
±1
—
LSB
EG
C
C
T Gain error
—
—
±1
—
LSB
TUE
C
C
P
Total unadjusted error without
current injection
—
−2.5
—
2.5
LSB
TUE
C
C
T
Total unadjusted error with current
injection
—
−3
—
3
LSB
1. VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = −40 °C to TA MAX, unless otherwise specified and analog input voltage from
VSS_HV_ADC0 to VDD_HV_ADC0.
2. AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
3. When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which the precision is lost.
Doc ID 16100 Rev 7
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Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
4. During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within ts. After the end of the
sampling time ts, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock
ts depend on programming.
5. This parameter includes the sampling time ts.
6. 20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.
7. See Figure 16.
3.15
Flash memory electrical characteristics
3.15.1
Program/Erase characteristics
Table 31.
Program and erase specifications
Value
Symbol
C
Parameter
Unit
Min
Typ(1)
Initial
Max(2)
Max(3)
—
30
70
500
µs
—
22
50
500
µs
—
0.73
0.83
17.5
s
—
0.49
1.2
4.1
s
16 KB Block Pre-program and Erase Time for code
flash memory
—
300
500
5000
16 KB Block Pre-program and Erase Time for data
flash memory
—
700
800
5000
T32kpperase P 32 KB Block Pre-program and Erase Time
—
400
600
5000
ms
T128kpperase P 128 KB Block Pre-program and Erase Time
—
800
1300
7500
ms
10
—
—
—
ms
Twprogram
Tdwprogram
P Word Program Time for data flash memory(4)
P Double Word Program Time for code flash
memory(4)
P Bank Program (256 KB)(4)(5)
TBKPRG
P Bank Program (64
T16kpperase P
tESRT
KB)(4)(5)
ms
P Program and erase specifications(6)
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
5. Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will require
more than one pulse, adding a small overhead to total bank programming time (see “Initial Max” column).
6. Time between erase suspend resume and next erase suspend request.
74/103
Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Table 32.
Electrical characteristics
Flash memory module life
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
—
P/E
Number of program/erase cycles per
C block for 16 KB blocks over the
operating temperature range (TJ)
—
100000
P/E
Number of program/erase cycles per
C block for 32 KB blocks over the
operating temperature range (TJ)
—
10000
100000 cycles
P/E
Number of program/erase cycles per
C block for 128 KB blocks over the
operating temperature range (TJ)
—
1000
100000 cycles
Blocks with 0–1000 P/E cycles
20
—
years
Blocks with 10000 P/E cycles
10
—
years
Blocks with 100000 P/E cycles
5
—
years
Minimum data retention at 85 °C
Retention C
average ambient temperature(1)
cycles
1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature
range.
Table 33.
Flash memory read access timing
Symbol
C
Parameter
Conditions(1)
Max value
66
C
Maximum working frequency for code flash memory at given
number of wait states in worst conditions
2 wait states
fmax
0 wait states
18
fmax
C
8 wait states
66
Maximum working frequency for data flash memory at given
number of wait states in worst conditions
Unit
MHz
MHz
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
3.15.2
Flash memory power supply DC characteristics
Table 34 shows the power supply DC characteristics on external supply.
Table 34.
Symbol
Flash memory power supply DC electrical characteristics
C
Value
Conditions(1)
Parameter
IFLPW
C
Sum of the current consumption on VDD_HV_IOx
D
C
and VDD_LV_CORx during low-power mode
IFPWD
C
Sum of the current consumption on VDD_HV_IOx
D
C
and VDD_LV_CORx during power-down mode
Unit
Min
Typ
Max
Code flash memory
—
—
900
Code flash memory
—
—
150
Data flash memory
—
—
150
µA
µA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
Doc ID 16100 Rev 7
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Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
3.15.3
Start-up/Switch-off timings
Table 35.
Start-up time/Switch-off time
Symbol
C
Value
Conditions(1)
Parameter
Unit
Min
C T
Delay for Flash module to exit reset mode
C
T
TFLARSTEXIT
Code flash
memory
—
—
125
Data flash memory
—
—
125
—
—
0.5
C
Code flash
D Delay for Flash module to exit low-power mode
C
memory
TFLALPEXIT
Typ Max
µs
C T Delay for Flash module to exit power-down
C
mode
T
TFLAPDEXIT
C
Delay for Flash module to enter low-power
D
C
mode
TFLALPENTRY
Code flash
memory
—
—
30
Data flash memory
—
—
30
Code flash
memory
—
—
0.5
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
3.16
AC specifications
3.16.1
Pad AC specifications
Table 36.
Output pin transition times
Symbol
C
Value
Conditions(1)
Parameter
Unit
Min Typ Max
CL = 25 pF
D
ttr
ttr
76/103
CC
CC
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
50
—
—
100
T
CL = 50 pF
D Output transition time output pin(2)
D SLOW configuration
CL = 100 pF
—
—
125
CL = 25 pF
—
—
40
T
CL = 50 pF
—
—
50
D
CL = 100 pF
—
—
75
D
CL = 25 pF
—
—
10
T
CL = 50 pF
—
—
20
D Output transition time output pin(2)
D MEDIUM configuration
CL = 100 pF
—
—
40
—
—
12
T
CL = 50 pF
—
—
25
D
CL = 100 pF
—
—
40
CL = 25 pF
Doc ID 16100 Rev 7
ns
VDD = 3.3 V ± 10%,
PAD3V5V = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
ns
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Table 36.
Symbol
Electrical characteristics
Output pin transition times (continued)
C
Value
Conditions(1)
Parameter
Unit
Min Typ Max
CL = 25 pF
CL = 50 pF
ttr
CC D
Output transition time output pin(2)
FAST configuration
CL = 100 pF
CL = 25 pF
CL = 50 pF
CL = 100 pF
tSYM
(3)
CC T
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
—
—
4
—
—
6
—
—
12
—
—
4
—
—
7
—
—
12
—
—
4
—
—
5
ns
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
Symmetric transition time, same drive VDD = 5.0 V ± 10%, PAD3V5V = 0
strength between N and P transistor V = 3.3 V ± 10%, PAD3V5V = 1
DD
ns
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 °C to TA MAX, unless otherwise specified.
2. CL includes device and package capacitances (CPKG < 5 pF).
3. Transition timing of both positive and negative slopes will differ maximum 50%.
Figure 19. Pad output delay
VDD_HV_IOx/2
Pad
Data Input
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
VOH
VOL
Pad
Output
3.17
AC timing characteristics
3.17.1
RESET pin characteristics
The SPC560P34/SPC560P40 implements a dedicated bidirectional RESET pin.
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Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Figure 20. Start-up reset requirements
VDD
VDDMIN
VRESET
VIH
VIL
device reset forced by VRESET
device start-up phase
tPOR
Figure 21. Noise filtering on reset signal
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
WFRST
WNFRST
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device under hardware reset
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Table 37.
Symbol
Electrical characteristics
RESET electrical characteristics
C
Value(2)
(1)
Parameter
Conditions
Unit
Min
Typ
Max
VIH
S
Input high level CMOS
P
R
(Schmitt Trigger)
—
0.65VDD
—
VDD + 0.4
V
VIL
S
Input low level CMOS
P
R
(Schmitt Trigger)
—
−0.4
—
0.35VDD
V
C
Input hysteresis CMOS
C
C
(Schmitt Trigger)
—
0.1VDD
—
—
V
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
Push Pull, IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 1(3)
—
—
0.1VDD
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
CL = 25 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
10
CL = 50 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
20
CL = 100 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
40
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
12
CL = 50 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
25
CL = 100 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
40
VHYS
VOL
ttr
C
P Output low level
C
Output transition time
C
D output pin(4) MEDIUM
C
configuration
V
ns
WFRST
S
RESET input filtered
P
R
pulse
—
—
—
40
ns
WNFRST
S
RESET input not
P
R
filtered pulse
—
500
—
—
ns
Monotonic VDD_HV supply ramp
—
—
1
ms
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
—
150
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
—
150
10
—
250
tPOR
|IWPU|
Maximum delay before
internal reset is
C
D released after all
C
VDD_HV reach nominal
supply
C
Weak pull-up current
P
C
absolute value
VDD = 5.0 V ± 10%, PAD3V5V =
1(5)
µA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
2. All values need to be confirmed during device validation.
3. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of device
reference manual).
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Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
4. CL includes device and package capacitance (CPKG < 5 pF).
5. The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
3.17.2
IEEE 1149.1 interface timing
Table 38.
JTAG pin AC electrical characteristics
Value
No
.
Symbol
C
Parameter
Conditions
Unit
Min
Max
1
tJCYC
CC
D TCK cycle time
—
100
—
ns
2
tJDC
CC
D TCK clock pulse width (measured at VDD_HV_IOx/2)
—
40
60
ns
3
tTCKRISE
CC
D TCK rise and fall times (40%–70%)
—
—
3
ns
4
tTMSS, tTDIS
CC
D TMS, TDI data setup time
—
5
—
ns
5
tTMSH,
tTDIH
CC
D TMS, TDI data hold time
—
25
—
ns
6
tTDOV
CC
D TCK low to TDO data valid
—
—
40
ns
7
tTDOI
CC
D TCK low to TDO data invalid
—
0
—
ns
8
tTDOHZ
CC
D TCK low to TDO high impedance
—
40
—
ns
9
tBSDV
CC
D TCK falling edge to output valid
—
—
50
ns
10
tBSDVZ
CC
D
TCK falling edge to output valid out of high
impedance
—
—
50
ns
11
tBSDHZ
CC
D TCK falling edge to output high impedance
—
—
50
ns
12
tBSDST
CC
D Boundary scan input valid to TCK rising edge
—
50
—
ns
13
tBSDHT
CC
D TCK rising edge to boundary scan input invalid
—
50
—
ns
Figure 22. JTAG test clock input timing
TCK
2
3
2
1
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SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Electrical characteristics
Figure 23. JTAG test access port timing
TCK
4
5
TMS, TDI
6
8
7
TDO
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Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Figure 24. JTAG boundary scan timing
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
3.17.3
Nexus timing
Table 39.
Nexus debug port timing(1)
Value
No.
1
2
3
Symbol
C
Parameter
Unit
Min
Typ
Max
4(2)
—
—
tCYC
tTCYC
CC D TCK cycle time
tNTDIS
CC D TDI data setup time
5
—
—
ns
tNTMSS
CC D TMS data setup time
5
—
—
ns
tNTDIH
CC D TDI data hold time
25
—
—
ns
tNTMSH
CC D TMS data hold time
25
—
—
ns
4
tTDOV
CC D TCK low to TDO data valid
10
—
20
ns
5
tTDOI
CC D TCK low to TDO data invalid
—
—
—
ns
1. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal.
2. Lower frequency is required to be fully compliant to standard.
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Electrical characteristics
Figure 25. Nexus output timing
1
MCKO
2
3
4
MDO
MSEO
EVTO
Output Data Valid
Figure 26. Nexus event trigger and test clock timing
TCK
EVTI
EVTO
5
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Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Figure 27. Nexus TDI, TMS, TDO timing
TCK
6
7
TMS, TDI
9
8
TDO
3.17.4
External interrupt timing (IRQ pin)
Table 40.
External interrupt timing(1)
Value
No.
Symbol
C
Parameter
Conditions
Unit
Min
Max
1
tIPWL
CC
D
IRQ pulse width low
—
4
—
tCYC
2
tIPWH
CC
D
IRQ pulse width high
—
4
—
tCYC
3
tICYC
CC
D
IRQ edge to edge time(2)
—
—
tCYC
4+N
(3)
1. IRQ timing specified at fSYS = 64 MHz and VDD_HV_IOx = 3.0 V to 5.5 V, TA = TL to TH, and CL = 200 pF with SRC = 0b00
2. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
3. N = ISR time to clear the flag
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Electrical characteristics
Figure 28. External interrupt timing
IRQ
1
2
3
3.17.5
DSPI timing
Table 41.
DSPI timing(1)
Value
No.
1
Symbol
C
Conditions
Unit
Min
Max
Master (MTFE = 0)
60
—
Slave (MTFE = 0)
60
—
ns
tSCK
CC
2
tCSC
CC
D
CS to SCK delay
—
16
—
ns
3
tASC
CC
D
After SCK delay
—
26
—
ns
4
tSDC
CC
D
SCK duty cycle
—
0.4 * tSCK
0.6 * tSCK
ns
5
tA
CC
D
Slave access time
SS active to SOUT valid
—
30
ns
6
tDIS
CC
D
Slave SOUT disable time
SS inactive to SOUT high
impedance or invalid
—
16
ns
7
tPCSC CC
D
PCSx to PCSS time
—
13
—
ns
8
tPASC CC
D
PCSS to PCSx time
—
13
—
ns
Master (MTFE = 0)
35
—
Slave
4
—
Master (MTFE = 1, CPHA = 0)
35
—
Master (MTFE = 1, CPHA = 1)
35
—
Master (MTFE = 0)
−5
—
Slave
4
—
Master (MTFE = 1, CPHA = 0)
11
—
Master (MTFE = 1, CPHA = 1)
−5
—
9
10
tSUI
tHI
CC
CC
D
Parameter
D
D
DSPI cycle time
Data setup time for inputs
ns
Data hold time for inputs
ns
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Electrical characteristics
Table 41.
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
DSPI timing(1) (continued)
Value
No.
11
12
Symbol
tSUO
tHO
CC
CC
C
D
D
Parameter
Conditions
Unit
Min
Max
Master (MTFE = 0)
—
12
Slave
—
36
Data valid (after SCK edge) Master (MTFE = 1,
CPHA = 0)
—
12
Master (MTFE = 1,
CPHA = 1)
—
12
Master (MTFE = 0)
−2
—
Slave
6
—
Master (MTFE = 1, CPHA = 0)
6
—
Master (MTFE = 1, CPHA = 1)
−2
—
ns
Data hold time for outputs
1. All timing are provided with 50 pF capacitance on output, 1 ns transition time on input signal
Figure 29. DSPI classic SPI timing – Master, CPHA = 0
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
SIN
First Data
Data
12
SOUT
First Data
Last Data
11
Data
Note: Numbers shown reference Table 41.
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ns
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Last Data
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Electrical characteristics
Figure 30. DSPI classic SPI timing – Master, CPHA = 1
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
First Data
SIN
Last Data
12
SOUT
First Data
11
Data
Last Data
Note: Numbers shown reference Table 41.
Figure 31. DSPI classic SPI timing – Slave, CPHA = 0
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
SOUT
First Data
9
SIN
12
11
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 41.
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Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Figure 32. DSPI classic SPI timing – Slave, CPHA = 1
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
10
First Data
Note: Numbers shown reference Table 41.
Figure 33. DSPI modified transfer format timing – Master, CPHA = 0
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
First Data
10
12
SOUT
First Data
11
Data
Note: Numbers shown reference Table 41.
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Last Data
Data
Doc ID 16100 Rev 7
Last Data
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Electrical characteristics
Figure 34. DSPI modified transfer format timing – Master, CPHA = 1
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
First Data
Last Data
Data
12
First Data
SOUT
11
Last Data
Data
Note: Numbers shown reference Table 41.
Figure 35. DSPI modified transfer format timing – Slave, CPHA = 0
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
SOUT
First Data
Data
First Data
6
Last Data
10
9
SIN
12
11
5
Data
Last Data
Note: Numbers shown reference Table 41.
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Electrical characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Figure 36. DSPI modified transfer format timing – Slave, CPHA = 1
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
First Data
SOUT
9
Last Data
Data
Last Data
10
First Data
SIN
Data
Note: Numbers shown reference Table 41.
Figure 37. DSPI PCS Strobe (PCSS) timing
8
7
PCSS
PCSx
Note: Numbers shown reference Table 41.
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4
Package characteristics
4.1
ECOPACK®
Package characteristics
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Doc ID 16100 Rev 7
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Package characteristics
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
4.2
Package mechanical data
4.2.1
LQFP100 mechanical outline drawing
Figure 38. LQFP100 package mechanical drawing
0.25 mm
0.10 inch
GAGE PLANE
k
D
L
D1
L1
D3
51
75
C
76
50
b
E3 E1 E
100
26
Pin 1
1
identification
25
ccc
C
e
A1
A2
A
SEATING PLANE
C
1L_ME
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Table 42.
Package characteristics
LQFP100 package mechanical data
Dimensions
Symbol
inches(1)
mm
Min
Typ
Max
Min
Typ
Max
A
—
—
1.600
—
—
0.0630
A1
0.050
—
0.150
0.0020
—
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
—
0.200
0.0035
—
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
—
12.000
—
—
0.4724
—
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
—
12.000
—
—
0.4724
—
e
—
0.500
—
—
0.0197
—
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
—
1.000
—
—
0.0394
—
k
0.0°
3.5°
7.0°
0.0°
3.5°
7.0°
ccc(2)
0.08
0.0031
1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.
2. Tolerance
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Package characteristics
4.2.2
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
LQFP64 mechanical outline drawing
Figure 39. LQFP64 package mechanical drawing
D
ccc C
D1
A
A2
D3
33
48
32
49
b
L1
E3 E1 E
L
A1
K
64
17
Pin 1
identification
Table 43.
16
1
c
5W_ME
LQFP64 package mechanical data
Dimensions
Symbol
inches(1)
mm
Min
Typ
Max
Min
Typ
Max
A
—
—
1.6
—
—
0.063
A1
0.05
—
0.15
0.002
—
0.0059
A2
1.35
1.4
1.45
0.0531
0.0551
0.0571
b
0.17
0.22
0.27
0.0067
0.0087
0.0106
c
0.09
—
0.2
0.0035
—
0.0079
D
11.8
12
12.2
0.4646
0.4724
0.4803
D1
9.8
10
10.2
0.3858
0.3937
0.4016
D3
—
7.5
—
—
0.2953
—
E
11.8
12
12.2
0.4646
0.4724
0.4803
E1
9.8
10
10.2
0.3858
0.3937
0.4016
E3
—
7.5
—
—
0.2953
—
e
—
0.5
—
—
0.0197
—
L
0.45
0.6
0.75
0.0177
0.0236
0.0295
L1
—
1
—
—
0.0394
—
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SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Table 43.
Package characteristics
LQFP64 package mechanical data (continued)
Dimensions
Symbol
k
ccc(2)
inches(1)
mm
Min
Typ
Max
Min
Typ
Max
0.0°
3.5°
7.0°
0.0°
3.5°
7.0°
0.08
0.0031
1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.
2. Tolerance
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Ordering information
5
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Ordering information
Figure 40. Commercial product code structure
Example code:
Product identifier Core Family Memory Package Temperature Custom vers. Packing
SPC56
0
P
40
L3
C
EFA
Y
Y = Tray
R = Tape and Reel
X = Tape and Reel 90°
A = 64 MHz, 5 V
B = 64 MHz, 3.3 V
C = 40 MHz, 5 V
D = 40 MHz, 3.3 V
F = Full-featured
A = Airbag
E = Data Flash
0 = No Data Flash
B = –40 to 105 °C
C = –40 to 125 °C
L1 = LQFP64
L3 = LQFP100
34 = 192 KB
40 = 256 KB
P = SPC560Px family
0 = e200z0
SPC56 = Power Architecture in 90 nm
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Appendix A
Ordering information
Abbreviations
Table 44 lists abbreviations used in this document.
Table 44.
Abbreviations
Abbreviation
Meaning
CMOS
Complementary metal–oxide–semiconductor
CPHA
Clock phase
CPOL
Clock polarity
CS
Peripheral chip select
DUT
Device under test
ECC
Error code correction
EVTO
Event out
GPIO
General purpose input / output
MC
Modulus counter
MCKO
Message clock out
MCU
Microcontroller unit
MDO
Message data out
MSEO
Message start/end out
MTFE
Modified timing format enable
NPN
NVUSRO
Negative-positive-negative
Non-volatile user options register
PTF
Post trimming frequency
PWM
Pulse width modulation
RISC
Reduced instruction set computer
SCK
Serial communications clock
SOUT
Serial data out
TBC
To be confirmed
TBD
To be defined
TCK
Test clock input
TDI
Test data input
TDO
Test data output
TMS
Test mode select
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Revision history
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Revision history
Table 45.
Document revision history
Date
Revision
01-Sep-2009
1
Initial release.
2
Editorial updates
Updated the following items in the “SPC560P34/SPC560P40 device comparison”
table:
– The heading
– The “SRAM” row
– The “FlexCAN” row
– The “CTU” row
– The “FlexPWM” row
– The “LINFlex” row
– The “DSPI” row
– The “Nexus” row
Updated the “SPC560P34/SPC560P40 device configuration difference” table:
– Editorial updates
– Added the “CTU” row
– Deleted the “temperature” row
– Swapped the content of Airbag and Full Featured cells
Added the “Wakeup unit” block in the SPC560P34/SPC560P40 block diagram
Updated the “Absolute Maximum Ratings“ table
Updated the “Recommended operating conditions (5.0 V)“ table
Updated the “Recommended operating conditions (3.3 V)“ table
Updated the “Thermal characteristics for 100-pin LQFP“ table:
– ΨJT: changed the typical value
Updated the “EMI testing specifications“ table: replaced all values in “Level (Max)“
column with TBD
Updated the “Electrical characteristics“ section:
– Added the “Introduction” section
– Added the “Parameter classification“ section
– Added the “NVUSRO register“ section
– Added the “Power supplies constraints (–0.3 V ≤ VDD_HV_IOx ≤ 6.0 V)” figure
– Added the “Independent ADC supply (–0.3 V ≤ VDD_HV_REG ≤ 6.0 V)“ figure
– Added the “Power supplies constraints (3.0 V ≤ VDD_HV_IOx ≤ 5.5 V)“ figure
– Added the “Independent ADC supply (3.0 V ≤ VDD_HV_REG ≤ 5.5 V)“ figure
Updated the “Power management electrical characteristics” section
Updated the “Power Up/Down sequencing” section
Updated the “DC electrical characteristics“ section
– Deleted the “NVUSRO register” section
– Updated the “DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)“ section:
– Deleted all rows concerning RESET
– Deleted “IVPP“ row
– Added the max value for CIN
21-May-2010
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Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Table 45.
Date
Revision history
Document revision history (continued)
Revision
Changes
– Updated the “DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 0)“ section:
– Deleted all rows concerning RESET
– Deleted “IVPP“ row
2
–
Added the max value for CIN
21-May-2010
(continued)
Added the “I/O pad current specification“ section
Updated the Order codes table.
Added “Appendix A”
23-Dec-2010
3
“Introduction” section:
– Changed title (was “Overview“)
– Updated contents
“SPC560P34/SPC560P40 device comparison” table:
– Added sentence above table
– Removed “FlexRay” row
– “FlexCAN” row: removed link to footnote 2 for SPC560P34
– Updated “Safety port” row for SPC560P34
– Updated “DSPI” row for SPC560P34
“SPC560P34/SPC560P40 block diagram”: added the following blocks: MC_CGM,
MC_ME, MC_PCU, MC_RGM, CRC, and SSCM
Added “SPC560P34/SPC560P40 series block summary” table
“Pin muxing” section: removed information on “Symmetric pads”
“Electrical characteristics” section:
– Updated “Caution” note
– Demoted “NVUSRO register” section to subsection of “DC electrical characteristics”
section
– “NVUSRO register” section: deleted “NVUSRO[WATCHDOG_EN] field description“
section
Updated “EMI testing specifications” table
“Low voltage monitor electrical characteristics” table: updated VMLVDDOK_H max value
“DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)” table: removed VOL_SYM,
and VOH_SYM rows
“Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)” table:
– IDD_LV_CORE, RUN—Maximum mode, 40/64 MHz: updated typ/max values
– IDD_LV_CORE, RUN—Airbag mode, 40/64 MHz: updated typ/max values
– IDD_LV_CORE, RUN—Maximum mode, “P” parameter classification: removed
– IDD_FLASH: removed rows
– IDD_ADC, Maximum mode: updated typ/max values
– IDD_OSC: updated max value
Updated “DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)” table
“Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)” table:
– IDD_LV_CORE, RUN—Maximum mode, 40/64 MHz: updated typ/max values
– IDD_LV_CORE, RUN—Airbag mode, 40/64 MHz: updated typ/max values
– IDD_FLASH: removed rows
– IDD_ADC, Maximum mode: updated typ/max values
– IDD_OSC: updated max value
Added “I/O consumption” table
Removed “I/O weight” table
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Revision history
Table 45.
Date
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Document revision history (continued)
Revision
Changes
Updated “Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)”
table
Updated “Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)”
table
“Input clock characteristics” table: updated fCLK max value
“PLLMRFM electrical specifications (VDDPLL = 1.08 V to 1.32 V, VSS = VSSPLL = 0 V,
TA = TL to TH)” table:
– Updated supply voltage range for VDDPLL in the table title
– Updated fSCM max value
– Updated CJITTER row
– Updated fMOD max value
Updated “16 MHz RC oscillator electrical characteristics” table
Updated “ADC conversion characteristics” table
“Program and erase specifications” table:
– Twprogram: updated initial max and max values
– TBKPRG, 64 KB: updated initial max and max values
3
23-Dec-2010
(continued) – added information about “erase time” for Data Flash
“Flash module life” table:
– P/E, 32 KB: added typ value
– P/E, 128 KB: added typ value
Replaced “Pad AC specifications (5.0 V, NVUSRO[PAD3V5V] = 0)” and “Pad AC
specifications (3.3 V, INVUSRO[PAD3V5V] = 1)” tables with “Output pin transition
times” table
“JTAG pin AC electrical characteristics” table:
– tTDOV: updated max value
– tTDOHZ: added min value and removed max value
“Nexus debug port timing” table: removed the rows “tMCYC”, “tMDOV”, “tMSEOV”, and
“tEVTOV”
Updated “External interrupt timing (IRQ pin)” table
Updated “FlexCAN timing” table
Updated “DSPI timing” table
Updated “Ordering information” section
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Table 45.
Date
13-May-2011
Revision history
Document revision history (continued)
Revision
4
Changes
Editorial and formatting changes throughout
Cover page features list:
• changed core feature “64 MHz” to “Up to 64 MHz”
• changed Data flash memory “64 (4 × 16) KB” to “Additional 64 (4 × 16) KB”
• changed “1 FlexCAN interface” to “Up to 2 FlexCAN interface”
Updated Device summary
Section “Introduction“: Reorganized contents
SPC560P40 device configuration differences: Editorial changes to indicate that the
table concerns only the SPC560P40 devices); removed “DSPI” row
Block diagram (SPC560P40 full-featured configuration): reorganized blocks above and
below peripheral bridge; made arrow going from peripheral bridge to crossbar switch
bidirectional; removed SPC560P34 part number from title
Added section “Features details”
64-pin and 100-pin LQFP pinout diagrams: replaced instances of HV_AD0 with
HV_ADC0
System pins: updated “XTAL” and “EXTAL” rows
Updated LQFP thermal characteristics
Updated EMI testing specifications
section “Voltage regulator electrical characteristics“: removed BCP56 from named BJTs;
replaced two configuration diagrams and two electrical characteristics tables with
single diagram and single table
Voltage regulator electrical characteristics: updated VDD_LV_REGCOR row
Low voltage monitor electrical characteristics: updated VMLVDDOK_H max value—was
1.15 V; is 1.145 V
Supply current (5.0 V, NVUSRO[PAD3V5V] = 0): changed symbol IDD_LV_CORE to
IDD_LV_CORx; changed parameter classification from T to P for IDD_LV_CORx RUN—
Maximum mode at 64 MHz; added IDD_FLASH characteristics; replaced instances of
“Airbag” mode with “Typical mode”
Supply current (3.3 V, NVUSRO[PAD3V5V] = 1): changed symbol IDD_LV_CORE to
IDD_LV_CORx; replaced instances of “Airbag” mode with “Typical mode”
DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1): corrected parameter
description for VOL_F—was “Fast, high level output voltage”; is “Fast, low level output
voltage”
Added Section 3.10.4, Input DC electrical characteristics definition
Main oscillator output electrical characteristics tables: replaced instances of EXTAL with
XTAL; added load capacitance parameter
FMPLL electrical characteristics: updated conditions and table title; removed fsys row;
updated fFMPLLOUT values; replaced instances of VDDPLL with VDD_LV_COR0; replaced
instances of VSSPLL with VSS_LV_COR0
16 MHz RC oscillator electrical characteristics: removed rows ΔRCMTRIM and
ΔRCMSTEP
ADC characteristics and error definitions: updated symbols
ADC conversion characteristics: updated symbols; added row tADC_PU
Added Section 3.15.2, Flash memory power supply DC characteristics
Added Section 3.15.3, Start-up/Switch-off timings
Removed section “Generic timing diagrams”
Updated Start-up reset requirements diagram
Removed FlexCAN timing characteristics
RESET electrical characteristics: added row for tPOR
In the range of figures “DSPI Classic SPI Timing — Master, CPHA = 0” to “DSPI PCS
Strobe (PCSS) Timing”: added note
Updated Order codes
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Revision history
Table 45.
Date
13-May-2011
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
Document revision history (continued)
Revision
Changes
4
Commercial product code structure: Replaced “Conditioning” with “Packing”
(continued) Table 44: added “DUT”, “NPN”, and “RISC”
5
Updated Table 1: Device summary
Updated Section 1.5.28: Nexus Development Interface (NDI)
Section Table 2.: SPC560P34/SPC560P40 device comparison: changed Nexus L1+
with Nexus Class 1
Table 7: Pin muxing: removed E[0] row
Table 9: Absolute maximum ratings: updated minumum and maximum values for TVDD
parameter
Section 3.10: DC electrical characteristics: Removed oscillator margin.
Removed Section NVUSRO[OSCILLATOR_MARGIN] field description and Table
NVUSRO[OSCILLATOR_MARGIN] field description
Updated Section 3.8.1: Voltage regulator electrical characteristics
Updated Section Figure 10.: Voltage regulator configuration
Table 16: Voltage regulator electrical characteristics: added LReg row, updated condition
for CDEC1, CDEC2 and CDEC3
Removed “Order codes” tables
20-Dec-2012
6
Table 9 (Absolute maximum ratings): updated TVDD parameter, the minimum value to
3.0 V/s, added note on minimum value, and the maximum value to 0.5 V/µs
Table 20 (Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)): added IDD_HV_REG row
Table 22 (Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)): added IDD_HV_REG row
Updated Section 3.14.1, Input impedance and ADC accuracy
Table 30 (ADC conversion characteristics): renamed “RSW1” in “RSW”
Table 31 (Program and erase specifications): added tESRT row
18-Sep-2013
7
Updated Disclaimer.
22-Dec-2011
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Doc ID 16100 Rev 7
SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3
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