SPC560P44L3, SPC560P44L5
SPC560P50L3, SPC560P50L5
32-bit Power Architecture® based MCU with 576 KB Flash memory
and 40 KB SRAM for automotive chassis and safety applications
Datasheet − production data
Features
■
64 MHz, single issue, 32-bit CPU core complex
(e200z0h)
– Compliant with Power Architecture®
embedded category
– Variable Length Encoding (VLE)
■
Memory organization
– Up to 512 KB on-chip code flash memory
with ECC and erase/program controller
– Additional 64 (4 × 16) KB on-chip data flash
memory with ECC for EEPROM emulation
– Up to 40 KB on-chip SRAM with ECC
■
Fail safe protection
– Programmable watchdog timer
– Non-maskable interrupt
– Fault collection unit
■
Nexus L2+ interface
■
Interrupts
– 16-channel eDMA controller
– 16 priority level controller
■
General purpose I/Os individually
programmable as input, output or special
function
■
■
2 general purpose eTimer units
– 6 timers each with up/down count
capabilities
– 16-bit resolution, cascadable counters
– Quadrature decode with rotation direction
flag
– Double buffer input capture and output
compare
Communications interfaces
– 2 LINFlex channels (LIN 2.1)
– 4 DSPI channels with automatic chip select
generation
– 1 FlexCAN interface (2.0B Active) with 32
message objects
September 2013
This is information on a product in full production.
LQFP144 (20 x 20 x 1.4 mm)
LQFP100 (14 x 14 x 1.4 mm)
– 1 safety port based on FlexCAN with 32
message objects and up to 7.5 Mbit/s
capability; usable as second CAN when not
used as safety port
– 1 FlexRay™ module (V2.1) with selectable
dual or single channel support, 32
message objects and up to 10 Mbit/s
(512 KB device only)
■
Two 10-bit analog-to-digital converters (ADC)
– 2 × 11 input channels, + 4 shared channels
– Conversion time < 1 µs including sampling
time at full precision
– Programmable ADC Cross Triggering Unit
(CTU)
– 4 analog watchdogs with interrupt
capability
■
On-chip CAN/UART bootstrap loader with Boot
Assist Module (BAM)
■
1 FlexPWM unit: 8 complementary or
independent outputs with ADC synchronization
signals
Table 1.
Device summary
Part number
Package
448 KB Flash
576 KB Flash
LQFP144 SPC560P44L5
SPC560P50L5
LQFP100 SPC560P44L3
SPC560P50L3
Doc ID 14723 Rev 9
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www.st.com
1
Contents
SPC560P44Lx, SPC560P50Lx
Contents
1
2/112
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3
Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5
Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.1
High performance e200z0 core processor . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.2
Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.3
Enhanced direct memory access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.4
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.5
Static random access memory (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.6
Interrupt controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.7
System status and configuration module (SSCM) . . . . . . . . . . . . . . . . . 16
1.5.8
System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.9
Frequency-modulated phase-locked loop (FMPLL) . . . . . . . . . . . . . . . . 17
1.5.10
Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.11
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.12
Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.13
System timer module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.14
Software watchdog timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.15
Fault collection unit (FCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.16
System integration unit – Lite (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.17
Boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.18
Error correction status module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.19
Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.20
Controller area network (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.21
Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.22
FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.5.23
Serial communication interface module (LINFlex) . . . . . . . . . . . . . . . . . 22
1.5.24
Deserial serial peripheral interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 23
1.5.25
Pulse width modulator (FlexPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5.26
eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.27
Analog-to-digital converter (ADC) module . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.28
Cross triggering unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
2
3
Contents
1.5.29
Nexus development interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.5.30
Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.31
IEEE 1149.1 JTAG controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.32
On-chip voltage regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 29
2.1
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.1
Power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.2
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.3
Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2
Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.4
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.5
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.5.1
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.5.2
General notes for specifications at maximum junction temperature . . . 57
3.6
Electromagnetic interference (EMI) characteristics . . . . . . . . . . . . . . . . . 59
3.7
Electrostatic discharge (ESD) characteristics . . . . . . . . . . . . . . . . . . . . . 59
3.8
Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 59
3.8.1
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 59
3.8.2
Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 63
3.9
Power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.10
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.10.1
NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.10.2
DC electrical characteristics (5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.10.3
DC electrical characteristics (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.10.4
Input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . 69
3.10.5
I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.11
Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.12
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.13
16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . 78
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Contents
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3.14
Analog-to-digital converter (ADC) electrical characteristics . . . . . . . . . . . 78
3.14.1
Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.14.2
ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.15
Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.16
AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.16.1
3.17
4
5
Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.17.1
RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.17.2
IEEE 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.17.3
Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.17.4
External interrupt timing (IRQ pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.17.5
DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2.1
LQFP144 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2.2
LQFP100 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . 103
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Appendix A Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SPC560P44Lx, SPC560P50Lx device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPC560P44Lx, SPC560P50Lx device configuration differences . . . . . . . . . . . . . . . . . . . . . 8
SPC560P44Lx, SPC560P50Lx series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Thermal characteristics for 144-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Thermal characteristics for 100-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
EMI testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Approved NPN ballast components (configuration with resistor on base) . . . . . . . . . . . . . 60
Voltage regulator electrical characteristics (configuration with resistor on base) . . . . . . . . 61
Voltage regulator electrical characteristics (configuration without resistor on base) . . . . . 62
Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . . . . . . . . . . . . . . . 66
Supply current (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . . . . . . . . . . . . . . . 67
Supply current (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Main oscillator output electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) . . . . . . . 75
Main oscillator output electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1) . . . . . . . 76
Input clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
DSPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
LQFP100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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List of figures
SPC560P44Lx, SPC560P50Lx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
6/112
SPC560P44Lx, SPC560P50Lx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
144-pin LQFP pinout – Full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . 29
100-pin LQFP pinout – Airbag configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
100-pin LQFP pinout – Full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . 31
Power supplies constraints (–0.3 V ≤ VDD_HV_IOx ≤ 6.0 V). . . . . . . . . . . . . . . . . . . . . . . . . 52
Independent ADC supply (–0.3 V ≤ VDD_HV_REG ≤ 6.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . 52
Power supplies constraints (3.0 V ≤ VDD_HV_IOx ≤ 5.5 V). . . . . . . . . . . . . . . . . . . . . . . . . . 55
Independent ADC supply (3.0 V ≤ VDD_HV_REG ≤ 5.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Configuration with resistor on base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Configuration without resistor on base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Power-up typical sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Power-down typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Brown-out typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
DSPI classic SPI timing – Master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
DSPI classic SPI timing – Master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
DSPI classic SPI timing – Slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
DSPI classic SPI timing – Slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DSPI modified transfer format timing – Master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 98
DSPI modified transfer format timing – Master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 99
DSPI modified transfer format timing – Slave, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . 99
DSPI modified transfer format timing – Slave, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 100
DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
1
Introduction
1.1
Document overview
Introduction
This document provides electrical specifications, pin assignments, and package diagrams
for the SPC560P44/50 series of microcontroller units (MCUs). It also describes the device
features and highlights important electrical and physical characteristics. For functional
characteristics, refer to the device reference manual.
1.2
Description
This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest
achievement in integrated automotive application controllers. It belongs to an expanding
range of automotive-focused products designed to address chassis applications—
specifically, electrical hydraulic power steering (EHPS) and electric power steering (EPS)—
as well as airbag applications.
This family is one of a series of next-generation integrated automotive microcontrollers
based on the Power Architecture technology.
The advanced and cost-efficient host processor core of this automotive controller family
complies with the Power Architecture embedded category. It operates at speeds of up to
64 MHz and offers high performance processing optimized for low power consumption. It
capitalizes on the available development infrastructure of current Power Architecture
devices and is supported with software drivers, operating systems and configuration code to
assist with users implementations.
1.3
Device comparison
Table 2 provides a summary of different members of the SPC560P44Lx, SPC560P50Lx
family and their features—relative to full-featured version—to enable a comparison among
the family members and an understanding of the range of functionality offered within this
family.
Table 2.
SPC560P44Lx, SPC560P50Lx device comparison
Feature
Code flash memory (with ECC)
SPC560P44
SPC560P50
384 KB
512 KB
Data flash memory / EE option (with ECC)
64 KB
SRAM (with ECC)
36 KB
40 KB
Processor core
32-bit e200z0h
Instruction set
VLE (variable length encoding)
CPU performance
0–64 MHz
FMPLL (frequency-modulated phase-locked loop)
module
INTC (interrupt controller) channels
2
147
PIT (periodic interrupt timer)
1 (includes four 32-bit timers)
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Introduction
Table 2.
SPC560P44Lx, SPC560P50Lx
SPC560P44Lx, SPC560P50Lx device comparison (continued)
Feature
SPC560P44
SPC560P50
eDMA (enhanced direct memory access)
channels
16
FlexRay
Yes(1)
FlexCAN (controller area network)
2(2),(3)
Safety port
Yes (via second FlexCAN module)
FCU (fault collection unit)
Yes
CTU (cross triggering unit)
Yes
eTimer
2 (16-bit, 6 channels)
FlexPWM (pulse-width modulation) channels
8 (capturing on X-channels)
2 (10-bit, 15-channel(4))
ADC (analog-to-digital converter)
LINFlex
2
DSPI (deserial serial peripheral interface)
4
CRC (cyclic redundancy check) unit
Yes
JTAG controller
Yes
Nexus port controller (NPC)
Yes (Level 2+)
Digital power supply(5)
3.3 V or 5 V single supply with external transistor
Analog power supply
3.3 V or 5 V
Internal RC oscillator
16 MHz
Supply
External crystal oscillator
4–40 MHz
LQFP100
LQFP144
Packages
Temperature
Standard ambient temperature
–40 to 125 °C
1. 32 message buffers, selectable single or dual channel support
2. Each FlexCAN module has 32 message buffers.
3. One FlexCAN module can act as a Safety Port with a bit rate as high as 7.5 Mbit/s.
4. Four channels shared between the two ADCs
5. The different supply voltages vary according to the part number ordered.
SPC560P44Lx, SPC560P50Lx is available in two configurations having different features:
full-featured and airbag. Table 3 shows the main differences between the two versions.
Table 3.
SPC560P44Lx, SPC560P50Lx device configuration differences
Feature
Full-featured
Airbag
CTU (cross triggering unit)
Yes
No
FlexPWM
Yes
No
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Table 3.
Introduction
SPC560P44Lx, SPC560P50Lx device configuration differences (continued)
Feature
Full-featured
Airbag
Yes
No
2 (one FMPLL, one for
FlexRay)
1 (only FMPLL)
FlexRay
FMPLL (frequency-modulated phase-locked loop) module
1.4
Block diagram
Figure 1 shows a top-level block diagram of the SPC560P44Lx, SPC560P50Lx MCU.
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Introduction
SPC560P44Lx, SPC560P50Lx
External ballast
e200z0 Core
1.2 V regulator
control
32-bit
general
purpose
registers
XOSC
Integer
execution
unit
16 MHz
RC oscillator
FMPLL_0
(System)
Special
purpose
registers
Exception
handler
Instruction
unit
Variable
length
encoded
instructions
Branch
prediction
unit
Load/store
unit
FMPLL_1
(FlexRay, MotCtrl)
JTAG
Nexus port
controller
Interrupt
controller
Nexus 2+
eDMA
16 channels
Master
FlexRay
Data
32-bit
Instruction
32-bit
Master
Master
Crossbar switch (XBAR, AMBA 2.0 v6 AHB)
ECSM
SIUL
BAM
MC_ME
MC_CGM
MC_RGM
SWT
SRAM
(with ECC)
STM
Data Flash
(with ECC)
CRC
Code Flash
(with ECC)
Slave
WKPU
Slave
PIT
Slave
FCU
Safety port
FlexCAN
2×
LINFlex
4×
DSPI
2×
eTimer (6 ch)
SSCM
Channels
0–10
10-bit
ADC_1
Shared
channels
11–14
10-bit
ADC_0
Channels
0–10
1.2 V Rail VREG
CTU
FlexPWM
Peripheral bridge
Legend:
ADC
BAM
CRC
CTU
DSPI
ECSM
eDMA
eTimer
FCU
Flash
FlexCAN
FlexPWM
FMPLL
INTC
JTAG
Analog-to-digital converter
Boot assist module
Cyclic redundancy check
Cross triggering unit
Deserial serial peripheral interface
Error correction status module
Enhanced direct memory access
Enhanced timer
Fault collection unit
Flash memory
Controller area network
Flexible pulse width modulation
Frequency-modulated phase-locked loop
Interrupt controller
JTAG controller
Figure 1.
10/112
LINFlex
MC_CGM
MC_ME
MC_PCU
MC_RGM
PIT
SIUL
SRAM
SSCM
STM
SWT
WKPU
XOSC
XBAR
Serial communication interface (LIN support)
Clock generation module
Mode entry module
Power control unit
Reset generation module
Periodic interrupt timer
System integration unit Lite
Static random-access memory
System status and configuration module
System timer module
Software watchdog timer
Wakeup unit
External oscillator
Crossbar switch
SPC560P44Lx, SPC560P50Lx block diagram
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Table 4.
Introduction
SPC560P44Lx, SPC560P50Lx series block summary
Block
Function
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter
Boot assist module (BAM)
Block of read-only memory containing VLE code which is executed according to
the boot mode of the device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Controller area network
(FlexCAN)
Supports the standard CAN communications protocol
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the
eMIOS or from the PIT
Crossbar switch (XBAR)
Supports simultaneous connections between two master ports and three slave
ports; supports a 32-bit address bus width and a 32-bit data bus width
Cyclic redundancy check (CRC)
CRC checksum generator
Deserial serial peripheral
interface (DSPI)
Provides a synchronous serial interface for communication with external
devices
Enhanced direct memory access
(eDMA)
Performs complex data transfers with minimal intervention from a host
processor via “n” programmable channels
Enhanced timer (eTimer)
Provides enhanced programmable up/down modulo counting
Error correction status module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
External oscillator (XOSC)
Provides an output clock used as input reference for FMPLL_0 or as reference
clock for specific modules depending on system needs
Fault collection unit (FCU)
Provides functional safety to the device
Flash memory
Provides non-volatile storage for program code, constants and variables
Frequency-modulated phaselocked loop (FMPLL)
Generates high-speed system clocks and supports programmable frequency
modulation
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with minimum load on CPU
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control
unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Periodic interrupt timer (PIT)
Produces periodic interrupts and triggers
Peripheral bridge (PBRIDGE)
Interface between the system bus and on-chip peripherals
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
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Introduction
Table 4.
SPC560P44Lx, SPC560P50Lx
SPC560P44Lx, SPC560P50Lx series block summary (continued)
Block
Function
Pulse width modulator
(FlexPWM)
Contains four PWM submodules, each of which is capable of controlling a
single half-bridge power stage and two fault input channels
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the
device
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integration unit lite (SIUL) of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status and configuration
module (SSCM)
Provides system configuration and status data (such as memory size and
status, device mode and security status), device identification data, debug
status port enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AUTOSAR(1) and operating
system tasks
System watchdog timer (SWT)
Provides protection from runaway code
Wakeup unit (WKPU)
Supports up to 18 external sources that can generate interrupts or wakeup
events, 1 of which can cause non-maskable interrupt requests or wakeup
events
1. AUTOSAR: AUTomotive Open System ARchitecture (see www.autosar.org)
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Introduction
1.5
Feature details
1.5.1
High performance e200z0 core processor
The e200z0 Power Architecture core provides the following features:
1.5.2
●
High performance e200z0 core processor for managing peripherals and interrupts
●
Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU
●
Harvard architecture
●
Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions
–
Results in smaller code size footprint
–
Minimizes impact on performance
●
Branch processing acceleration using lookahead instruction buffer
●
Load/store unit
–
1 cycle load latency
–
Misaligned access support
–
No load-to-use pipeline bubbles
●
Thirty-two 32-bit general purpose registers (GPRs)
●
Separate instruction bus and load/store bus Harvard architecture
●
Hardware vectored interrupt support
●
Reservation instructions for implementing read-modify-write constructs
●
Long cycle time instructions, except for guarded loads, do not increase interrupt
latency
●
Extensive system development support through Nexus debug port
●
Non-maskable interrupt support
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four
master ports and three slave ports. The crossbar supports a 32-bit address bus width and a
32-bit data bus width.
The crossbar allows for two concurrent transactions to occur from any master port to any
slave port; but one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic will select the higher priority master and grant it ownership of the slave port.
All other masters requesting that slave port will be stalled until the higher priority master
completes its transactions. Requesting masters will be treated with equal priority and will be
granted access to a slave port in round-robin fashion, based upon the ID of the last master
to be granted access.
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SPC560P44Lx, SPC560P50Lx
The crossbar provides the following features:
●
●
1.5.3
4 master ports:
–
e200z0 core complex Instruction port
–
e200z0 core complex Load/Store Data port
–
eDMA
–
FlexRay
3 slave ports:
–
Flash memory (code flash and data flash)
–
SRAM
–
Peripheral bridge
●
32-bit internal address, 32-bit internal data paths
●
Fixed Priority Arbitration based on Port Master
●
Temporary dynamic priority elevation of masters
Enhanced direct memory access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels. This implementation is utilized to minimize the
overall block size.
The eDMA module provides the following features:
1.5.4
●
16 channels support independent 8, 16 or 32-bit single value or block transfers
●
Supports variable sized queues and circular queues
●
Source and destination address registers are independently configured to either postincrement or to remain constant
●
Each transfer is initiated by a peripheral, CPU, or eDMA channel request
●
Each eDMA channel can optionally send an interrupt request to the CPU on completion
of a single value or block transfer
●
DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer
and CTU
●
Programmable DMA channel multiplexer for assignment of any DMA source to any
available DMA channel with as many as 30 request sources
●
eDMA abort operation through software
Flash memory
The SPC560P44Lx, SPC560P50Lx provides as much as 576 KB of programmable, nonvolatile, flash memory. The non-volatile memory (NVM) can be used for instruction and/or
data storage. The flash memory module interfaces the system bus to a dedicated flash
memory array controller. It supports a 32-bit data bus width at the system bus port, and a
128-bit read data interface to flash memory. The module contains four 128-bit wide prefetch
buffers. Prefetch buffer hits allow no-wait responses. Normal flash memory array accesses
are registered and are forwarded to the system bus on the following cycle, incurring two
wait-states.
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Introduction
The flash memory module provides the following features:
●
–
8 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 3×128 KB) code flash
–
4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash
–
Full Read While Write (RWW) capability between code and data flash
●
Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch
buffers can be configured to prefetch code or data or both)
●
Typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page
buffer miss at 64 MHz
●
Hardware managed flash memory writes handled by 32-bit RISC Krypton engine
●
Hardware and software configurable read and write access protections on a per-master
basis
●
Configurable access timing allowing use in a wide range of system frequencies
●
Multiple-mapping support and mapping-based block access timing (up to 31 additional
cycles) allowing use for emulation of other memory types.
●
Software programmable block program/erase restriction control
●
Erase of selected block(s)
●
Read page sizes
●
1.5.5
As much as 576 KB flash memory
–
Code flash memory: 128 bits (4 words)
–
Data flash memory: 32 bits (1 word)
ECC with single-bit correction, double-bit detection for data integrity
–
Code flash memory: 64-bit ECC
–
Data flash memory: 64-bit ECC
●
Embedded hardware program and erase algorithm
●
Erase suspend, program suspend and erase-suspended program
●
Censorship protection scheme to prevent flash memory content visibility
●
Hardware support for EEPROM emulation
Static random access memory (SRAM)
The SPC560P44Lx, SPC560P50Lx SRAM module provides up to 40 KB of general-purpose
memory.
The SRAM module provides the following features:
1.5.6
●
Supports read/write accesses mapped to the SRAM from any master
●
Up to 40 KB general purpose SRAM
●
Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of
memory
●
Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait state for 8and 16-bit writes if back to back with a read to same memory block
Interrupt controller (INTC)
The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt
requests, suitable for statically scheduled hard real-time systems. The INTC handles 147
selectable-priority interrupt sources.
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For high priority interrupt requests, the time from the assertion of the interrupt request from
the peripheral to when the processor is executing the interrupt service routine (ISR) has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR has to be executed. It also provides a wide number of
priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol (PCP) for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the same resource can not preempt each other.
The INTC provides the following features:
1.5.7
●
Unique 9-bit vector for each separate interrupt source
●
8 software triggerable interrupt sources
●
16 priority levels with fixed hardware arbitration within priority levels for each interrupt
source
●
Ability to modify the ISR or task priority: modifying the priority can be used to implement
the Priority Ceiling Protocol for accessing shared resources.
●
2 external high priority interrupts directly accessing the main core and I/O processor
(IOP) critical interrupt mechanism
System status and configuration module (SSCM)
The system status and configuration module (SSCM) provides central device functionality.
The SSCM includes these features:
●
1.5.8
System configuration and status
–
Memory sizes/status
–
Device mode and security status
–
Determine boot vector
–
Search code flash for bootable sector
–
DMA status
●
Debug status port enable and selection
●
Bus and peripheral abort enable/disable
System clocks and clock generation
The following list summarizes the system clock and clock generation on the SPC560P44Lx,
SPC560P50Lx:
16/112
●
Lock detect circuitry continuously monitors lock status
●
Loss of clock (LOC) detection for PLL outputs
●
Programmable output clock divider (÷1, ÷2, ÷4, ÷8)
●
FlexPWM module and eTimer module can run on an independent clock source
●
On-chip oscillator with automatic level control
●
Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency
trimming by user application
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1.5.9
Introduction
Frequency-modulated phase-locked loop (FMPLL)
The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input
clock. Further, the FMPLL supports programmable frequency modulation of the system
clock. The PLL multiplication factor, output clock divider ratio are all software configurable.
The PLL has the following major features:
1.5.10
●
Input clock frequency: 4–40 MHz
●
Maximum output frequency: 64 MHz
●
Voltage controlled oscillator (VCO)—frequency 256–512 MHz
●
Reduced frequency divider (RFD) for reduced frequency operation without forcing the
PLL to relock
●
Frequency-modulated PLL
–
Modulation enabled/disabled through software
–
Triangle wave modulation
●
Programmable modulation depth (±0.25% to ±4% deviation from center frequency):
programmable modulation frequency dependent on reference frequency
●
Self-clocked mode (SCM) operation
Main oscillator
The main oscillator provides these features:
1.5.11
●
Input frequency range: 4–40 MHz
●
Crystal input mode or oscillator input mode
●
PLL reference
Internal RC oscillator
This device has an RC ladder phase-shift oscillator. The architecture uses constant current
charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap
reference voltage.
The RC oscillator provides these features:
1.5.12
●
Nominal frequency 16 MHz
●
±5% variation over voltage and temperature after process trim
●
Clock output of the RC oscillator serves as system clock source in case loss of lock or
loss of clock is detected by the PLL
●
RC oscillator is used as the default system clock during startup
Periodic interrupt timer (PIT)
The PIT module implements these features:
●
4 general purpose interrupt timers
●
32-bit counter resolution
●
Clocked by system clock frequency
●
Each channel can be used as trigger for a DMA request
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Introduction
1.5.13
SPC560P44Lx, SPC560P50Lx
System timer module (STM)
The STM module implements these features:
1.5.14
●
One 32-bit up counter with 8-bit prescaler
●
Four 32-bit compare channels
●
Independent interrupt source for each channel
●
Counter can be stopped in debug mode
Software watchdog timer (SWT)
The SWT has the following features:
1.5.15
●
32-bit time-out register to set the time-out period
●
Programmable selection of system or oscillator clock for timer operation
●
Programmable selection of window mode or regular servicing
●
Programmable selection of reset or interrupt on an initial time-out
●
Master access protection
●
Hard and soft configuration lock bits
●
Reset configuration inputs allow timer to be enabled out of reset
Fault collection unit (FCU)
The FCU provides an independent fault reporting mechanism even if the CPU is
malfunctioning.
The FCU module has the following features:
1.5.16
●
FCU status register reporting the device status
●
Continuous monitoring of critical fault signals
●
User selection of critical signals from different fault sources inside the device
●
Critical fault events trigger 2 external pins (user selected signal protocol) that can be
used externally to reset the device and/or other circuitry (for example, safety relay or
FlexRay transceiver)
●
Faults are latched into a register
System integration unit – Lite (SIUL)
The SPC560P44Lx, SPC560P50Lx SIUL controls MCU pad configuration, external
interrupt, general purpose I/O (GPIO), and internal peripheral multiplexing.
The pad configuration block controls the static electrical characteristics of I/O pins. The
GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.
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Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Introduction
The SIU provides the following features:
1.5.17
●
Centralized general purpose input output (GPIO) control of as many as 80 input/output
pins and 26 analog input-only pads (package dependent)
●
All GPIO pins can be independently configured to support pull-up, pull down, or no pull
●
Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
●
All peripheral pins (except ADC channels) can be alternatively configured as both
general purpose input or output pins
●
ADC channels support alternative configuration as general purpose inputs
●
Direct readback of the pin value is supported on all pins through the SIUL
●
Configurable digital input filter that can be applied to some general purpose input pins
for noise elimination: as many as 4 internal functions can be multiplexed onto 1 pin
Boot and censorship
Different booting modes are available in the SPC560P44Lx, SPC560P50Lx: booting from
internal flash memory and booting via a serial link.
The default booting scheme uses the internal flash memory (an internal pull-down is used to
select this mode). Optionally, the user can boot via FlexCAN or LINFlex (using the boot
assist module software).
A censorship scheme is provided to protect the content of the flash memory and offer
increased security for the entire device.
A password mechanism is designed to grant the legitimate user access to the non-volatile
memory.
Boot assist module (BAM)
The BAM is a block of read-only one-time programmed memory and is identical for all
SPC560Pxx devices that are based on the e200z0h core. The BAM program is executed
every time the device is powered on if the alternate boot mode has been selected by the
user.
The BAM provides the following features:
1.5.18
●
Serial bootloading via FlexCAN or LINFlex
●
Ability to accept a password via the used serial communication channel to grant the
legitimate user access to the non-volatile memory
Error correction status module (ECSM)
The ECSM provides a myriad of miscellaneous control functions regarding program-visible
information about the platform configuration and revision levels, a reset status register, a
software watchdog timer, wakeup control for exiting sleep modes, and information on
platform memory errors reported by error-correcting codes and/or generic access error
information for certain processor cores.
The Error Correction Status Module supports a number of miscellaneous control functions
for the platform. The ECSM includes these features:
●
Registers for capturing information on platform memory errors if error-correcting codes
(ECC) are implemented
●
For test purposes, optional registers to specify the generation of double-bit memory
errors are enabled on the SPC560P44Lx, SPC560P50Lx.
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Introduction
SPC560P44Lx, SPC560P50Lx
The sources of the ECC errors are:
1.5.19
●
Flash memory
●
SRAM
Peripheral bridge (PBRIDGE)
The PBRIDGE implements the following features:
1.5.20
●
Duplicated periphery
●
Master access privilege level per peripheral (per master: read access enable; write
access enable)
●
Write buffering for peripherals
●
Checker applied on PBRIDGE output toward periphery
●
Byte endianess swap capability
Controller area network (FlexCAN)
The SPC560P44Lx, SPC560P50Lx MCU contains one controller area network (FlexCAN)
module. This module is a communication controller implementing the CAN protocol
according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: realtime processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness
and required bandwidth. The FlexCAN module contains 32 message buffers.
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Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Introduction
The FlexCAN module provides the following features:
●
–
Standard data and remote frames
–
Extended data and remote frames
–
Up to 8-bytes data length
–
Programmable bit rate up to 1 Mbit/s
●
32 message buffers of up to 8-bytes data length
●
Each message buffer configurable as Rx or Tx, all supporting standard and extended
messages
●
Programmable loop-back mode supporting self-test operation
●
3 programmable mask registers
●
Programmable transmit-first scheme: lowest ID or lowest buffer number
●
Time stamp based on 16-bit free-running timer
●
Global network time, synchronized by a specific message
●
Maskable interrupts
●
Independent of the transmission medium (an external transceiver is assumed)
●
High immunity to EMI
●
Short latency time due to an arbitration scheme for high-priority messages
●
Transmit features
●
●
1.5.21
Full implementation of the CAN protocol specification, version 2.0B
–
Supports configuration of multiple mailboxes to form message queues of scalable
depth
–
Arbitration scheme according to message ID or message buffer number
–
Internal arbitration to guarantee no inner or outer priority inversion
–
Transmit abort procedure and notification
Receive features
–
Individual programmable filters for each mailbox
–
8 mailboxes configurable as a six-entry receive FIFO
–
8 programmable acceptance filters for receive FIFO
Programmable clock source
–
System clock
–
Direct oscillator clock to avoid PLL jitter
Safety port (FlexCAN)
The SPC560P44Lx, SPC560P50Lx MCU has a second CAN controller synthesized to run at
high bit rates to be used as a safety port. The CAN module of the safety port provides the
following features:
●
Identical to the FlexCAN module
●
Bit rate as fast as 7.5 Mbit/s at 60 MHz CPU clock using direct connection between
CAN modules (no physical transceiver required)
●
32 message buffers of up to 8 bytes data length
●
Can be used as a second independent CAN module
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Introduction
1.5.22
SPC560P44Lx, SPC560P50Lx
FlexRay
The FlexRay module provides the following features:
1.5.23
●
Full implementation of FlexRay Protocol Specification 2.1
●
32 configurable message buffers can be handled
●
Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
●
Message buffers configurable as Tx, Rx or RxFIFO
●
Message buffer size configurable
●
Message filtering for all message buffers based on FrameID, cycle count and message
ID
●
Programmable acceptance filters for RxFIFO message buffers
Serial communication interface module (LINFlex)
The LINFlex (local interconnect network flexible) on the SPC560P44Lx, SPC560P50Lx
features the following:
●
Supports LIN Master mode, LIN Slave mode and UART mode
●
LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications
●
Handles LIN frame transmission and reception without CPU intervention
●
LIN features
●
●
22/112
–
Autonomous LIN frame handling
–
Message buffer to store Identifier and as much as 8 data bytes
–
Supports message length as long as 64 bytes
–
Detection and flagging of LIN errors (sync field, delimiter, ID parity, bit framing,
checksum, and time-out)
–
Classic or extended checksum calculation
–
Configurable Break duration as long as 36-bit times
–
Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
–
Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection
–
Interrupt-driven operation with 16 interrupt sources
LIN slave mode features
–
Autonomous LIN header handling
–
Autonomous LIN response handling
UART mode
–
Full-duplex operation
–
Standard non return-to-zero (NRZ) mark/space format
–
Data buffers with 4-byte receive, 4-byte transmit
–
Configurable word length (8-bit or 9-bit words)
–
Error detection and flagging
–
Parity, Noise and Framing errors
–
Interrupt-driven operation with four interrupt sources
–
Separate transmitter and receiver CPU interrupt sources
–
16-bit programmable baud-rate modulus counter and 16-bit fractional
–
2 receiver wake-up methods
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
1.5.24
Introduction
Deserial serial peripheral interface (DSPI)
The deserial serial peripheral interface (DSPI) module provides a synchronous serial
interface for communication between the SPC560P44Lx, SPC560P50Lx MCU and external
devices.
The DSPI modules provide these features:
1.5.25
●
Full duplex, synchronous transfers
●
Master or slave operation
●
Programmable master bit rates
●
Programmable clock polarity and phase
●
End-of-transmission interrupt flag
●
Programmable transfer baud rate
●
Programmable data frames from 4 to 16 bits
●
Up to 20 chip select lines available
–
8 on DSPI_0
–
4 each on DSPI_1, DSPI_2 and DSPI_3
●
8 clock and transfer attributes registers
●
Chip select strobe available as alternate function on one of the chip select pins for
deglitching
●
FIFOs for buffering as many as 5 transfers on the transmit and receive side
●
Queueing operation possible through use of the eDMA
●
General purpose I/O functionality on pins when not used for SPI
Pulse width modulator (FlexPWM)
The pulse width modulator module (PWM) contains four PWM submodules, each capable of
controlling a single half-bridge power stage. There are also four fault channels.
This PWM is capable of controlling most motor types: AC induction motors (ACIM),
permanent magnet AC motors (PMAC), both brushless (BLDC) and brush DC motors
(BDC), switched (SRM) and variable reluctance motors (VRM), and stepper motors.
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Introduction
SPC560P44Lx, SPC560P50Lx
The FlexPWM block implements the following features:
24/112
●
16-bit resolution for center, edge-aligned, and asymmetrical PWMs
●
Maximum operating clock frequency of 120 MHz
●
PWM outputs can operate as complementary pairs or independent channels
●
Can accept signed numbers for PWM generation
●
Independent control of both edges of each PWM output
●
Synchronization to external hardware or other PWM supported
●
Double buffered PWM registers
–
Integral reload rates from 1 to 16
–
Half cycle reload capability
●
Multiple ADC trigger events can be generated per PWM cycle via hardware
●
Write protection for critical registers
●
Fault inputs can be assigned to control multiple PWM outputs
●
Programmable filters for fault inputs
●
Independently programmable PWM output polarity
●
Independent top and bottom deadtime insertion
●
Each complementary pair can operate with its own PWM frequency and deadtime
values
●
Individual software-control for each PWM output
●
All outputs can be programmed to change simultaneously via a “Force Out” event
●
PWMX pin can optionally output a third PWM signal from each submodule
●
Channels not used for PWM generation can be used for buffered output compare
functions
●
Channels not used for PWM generation can be used for input capture functions
●
Enhanced dual-edge capture functionality
●
eDMA support with automatic reload
●
2 fault inputs
●
Capture capability for PWMA, PWMB, and PWMX channels not supported
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
1.5.26
Introduction
eTimer
The SPC560P44Lx, SPC560P50Lx includes two eTimer modules. Each module provides
six 16-bit general purpose up/down timer/counter units with the following features:
●
Maximum operating clock frequency of 120 MHz
●
Individual channel capability
●
●
1.5.27
–
Input capture trigger
–
Output compare
–
Double buffer (to capture rising edge and falling edge)
–
Separate prescaler for each counter
–
Selectable clock source
–
0–100% pulse measurement
–
Rotation direction flag (Quad decoder mode)
Maximum count rate
–
External event counting: max. count rate = peripheral clock/2
–
Internal clock counting: max. count rate = peripheral clock
Counters are:
–
Cascadable
–
Preloadable
●
Programmable count modulo
●
Quadrature decode capabilities
●
Counters can share available input pins
●
Count once or repeatedly
●
Pins available as GPIO when timer functionality not in use
Analog-to-digital converter (ADC) module
The ADC module provides the following features:
Analog part:
●
2 on-chip AD converters
–
10-bit AD resolution
–
1 sample and hold unit per ADC
–
Conversion time, including sampling time, less than 1 µs (at full precision)
–
Typical sampling time is 150 ns min. (at full precision)
–
Differential non-linearity error (DNL) ±1 LSB
–
Integral non-linearity error (INL) ±1.5 LSB
–
TUE
ground (VSS)
2.7 V
VDD_HV_ADC1(
4)
VIN
50/112
—
VDD_HV_REG <
3.3 V / 5.0 V ADC_0 supply and high
2.7 V
SR reference voltage with respect to
VDD_HV_REG >
ground (VSS)
2.7 V
VSS_HV_ADC1 SR
TVDD
ADC_0 ground and low reference
voltage with respect to ground (VSS)
ADC_1 ground and low reference
voltage with respect to ground (VSS)
Slope characteristics on all VDD
SR during power up(5) with respect to
ground (VSS)
Voltage on any pin with respect to
SR ground (VSS_HV_IOx) with respect to
ground (VSS)
V
VDD_HV_IOx + 0.3
—
3.3 V / 5.0 V crystal oscillator
VDD_HV_OSC SR amplifier supply voltage with respect Relative to
to ground (VSS)
VDD_HV_IOx
VSS_HV_ADC0 SR
Unit
Min
0.1
V
6.0
V
VDD_HV_IOx + 0.3
0.1
V
6.0
–0.3
V
VDD_HV_IOx + 0.3
VDD_HV_REG +
0.3
–0.3
V
6.0
–0.1
0.1
V
VDD_HV_REG +
0.3
–0.3
V
6.0
—
–0.1
0.1
V
—
3.0
500 x 103
(0.5 [V/µs])
V/s
—
Relative to
VDD_HV_IOx
Doc ID 14723 Rev 9
6.0
–0.3
V
VDD_HV_IOx + 0.3
SPC560P44Lx, SPC560P50Lx
Table 9.
Electrical characteristics
Absolute maximum ratings(1) (continued)
Value
Symbol
Parameter
Conditions
Min
VINAN0
VINAN1
ADC0 and shared ADC0/1 analog
SR
input voltage(6)
SR ADC1 analog input voltage(7)
VDD_HV_REG > VSS_HV_ADV0 −
2.7 V
0.3
VDD_HV_REG <
2.7 V
VSS_HV_ADV0
VDD_HV_REG > VSS_HV_ADV1 −
2.7 V
0.3
Max(2)
Unit
VDD_HV_ADV0 +
0.3
V
VDD_HV_ADV0
V
VDD_HV_ADV1 +
0.3
V
VDD_HV_REG <
2.7 V
VSS_HV_ADV1
VDD_HV_ADV1
V
IINJPAD
SR
Injected input current on any pin
during overload condition
—
–10
10
mA
IINJSUM
SR
Absolute sum of all injected input
currents during overload condition
—
–50
50
mA
IVDD_LV
SR
Low voltage static current sink
through VDD_LV
—
—
155
mA
SR Storage temperature
—
–55
150
°C
SR Junction temperature under bias
—
–40
150
°C
TSTG
TJ
1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.
2. Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress
have not yet been determined.
3. The difference between each couple of voltage supplies must be less than 300 mV,
|VDD_HV_IOy – VDD_HV_IOx | < 300 mV.
4. The difference between ADC voltage supplies must be less than 100 mV, |VDD_HV_ADC1 – VDD_HV_ADC0| < 100 mV.
5. Guaranteed by device validation
6. Not allowed to refer this voltage to VDD_HV_ADV1, VSS_HV_ADV1
7. Not allowed to refer this voltage to VDD_HV_ADV0, VSS_HV_ADV0
Figure 5 shows the constraints of the different power supplies.
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
VDD_HV_xxx
6.0 V
VDD_HV_IOx
–0.3 V
–0.3 V
Figure 5.
6.0 V
Power supplies constraints (–0.3 V ≤ VDD_HV_IOx ≤ 6.0 V)
The SPC560P44Lx, SPC560P50Lx supply architecture allows of having ADC supply
managed independently from standard VDD_HV supply. Figure 6 shows the constraints of
the ADC power supply.
VDD_HV_ADCx
6.0 V
VDD_HV_REG
–0.3 V
–0.3 V
Figure 6.
52/112
2.7 V
6.0 V
Independent ADC supply (–0.3 V ≤ VDD_HV_REG ≤ 6.0 V)
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Electrical characteristics
3.4
Recommended operating conditions
Table 10.
Recommended operating conditions (5.0 V)
Value
Symbol
VSS
Parameter
Conditions
SR Device ground
VDD_HV_IOx(2)
SR
5.0 V input/output supply
voltage
VSS_HV_IOx
SR Input/output ground voltage
VDD_HV_FL
5.0 V code and data flash
SR
supply voltage
VSS_HV_FL
SR Code and data flash ground
Max(1)
—
0
0
V
—
4.5
5.5
V
—
0
0
V
—
4.5
5.5
Relative to
VDD_HV_IOx
—
—
5.0 V crystal oscillator amplifier
Relative to
supply voltage
VDD_HV_IOx
VDD_HV_OSC
SR
VSS_HV_OSC
SR
5.0 V crystal oscillator amplifier
reference voltage
VDD_HV_REG
SR
—
5.0 V voltage regulator supply
Relative to
voltage
VDD_HV_IOx
VDD_HV_ADC0(3)
VSS_HV_ADC0
VDD_HV_ADC1(3)
VSS_HV_ADC1
VDD_LV_REGCOR(4),
(5)
VDD_LV_CORx
VSS_LV_CORx
TA
(4)
—
—
5.0 V ADC_0 supply and high
SR
Relative to
reference voltage
VDD_HV_REG
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
0
0
4.5
5.5
V
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
0
0
4.5
5.5
V
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
4.5
5.5
VDD_HV_REG – 0.1
—
0
0
4.5
5.5
VDD_HV_REG – 0.1
—
—
0
0
V
—
—
—
V
—
0
0
V
CC Internal supply voltage
—
—
—
V
SR Internal reference voltage
—
0
0
V
fCPU = 64 MHz
–40
105
fCPU = 60 MHz
–40
125
SR
ADC_0 ground and low
reference voltage
—
—
5.0 V ADC_1 supply and high
SR
Relative to
reference voltage
VDD_HV_REG
SR
ADC_1 ground and low
reference voltage
CC Internal supply voltage
VSS_LV_REGCOR(4) SR Internal reference voltage
(4),(5)
Unit
Min
SR
Ambient temperature under
bias
V
V
V
°C
1. Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.
In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.
2. The difference between each couple of voltage supplies must be less than 100 mV, |VDD_HV_IOy – VDD_HV_IOx | < 100 mV.
Doc ID 14723 Rev 9
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
3. The difference between ADC voltage supplies must be less than 100 mV, |VDD_HV_ADC1 − VDD_HV_ADC0| < 100 mV.
4. To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an onchip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to high
voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast
emitter.
5. The low voltage supplies (VDD_LV_xxx) are not all independent.
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low
voltage supply to the data flash module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
VDD_LV_REGCOR and VDD_LV_REGCORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Table 11.
Recommended operating conditions (3.3 V)
Value
Symbol
VSS
Parameter
Conditions
SR Device ground
VDD_HV_IOx(2)
SR
3.3 V input/output supply
voltage
VSS_HV_IOx
SR Input/output ground voltage
VDD_HV_FL
3.3 V code and data flash
SR
supply voltage
VSS_HV_FL
SR Code and data flash ground
Max(1)
—
0
0
V
—
3.0
3.6
V
—
0
0
V
—
3.0
3.6
Relative to
VDD_HV_IOx
—
—
3.3 V crystal oscillator amplifier
Relative to
supply voltage
VDD_HV_IOx
VDD_HV_OSC
SR
VSS_HV_OSC
SR
3.3 V crystal oscillator amplifier
reference voltage
VDD_HV_REG
SR
—
3.3 V voltage regulator supply
Relative to
voltage
VDD_HV_IOx
—
—
VDD_HV_ADC0(3)
VSS_HV_ADC0
VDD_HV_ADC1(3)
VSS_HV_ADC1
VDD_LV_REGCOR(4),
(5)
3.3 V ADC_0 supply and high
SR
reference voltage
SR
ADC_0 ground and low
reference voltage
3.3 V ADC_1 supply and high
SR
reference voltage
SR
ADC_1 ground and low
reference voltage
CC Internal supply voltage
VSS_LV_REGCOR(4) SR Internal reference voltage
VDD_LV_CORx
54/112
(4),(5)
CC Internal supply voltage
Unit
Min
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
0
0
3.0
3.6
V
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
0
0
3.0
3.6
V
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
3.0
5.5
VDD_HV_REG – 0.1
5.5
—
0
0
—
3.0
5.5
VDD_HV_REG – 0.1
5.5
—
0
0
V
—
—
—
V
—
0
0
V
—
—
—
V
Relative to
VDD_HV_REG
Relative to
VDD_HV_REG
Doc ID 14723 Rev 9
V
V
V
SPC560P44Lx, SPC560P50Lx
Table 11.
Electrical characteristics
Recommended operating conditions (3.3 V) (continued)
Value
Symbol
VSS_LV_CORx(4)
TA
Parameter
Conditions
Min
Max(1)
—
0
0
fCPU = 64 MHz
–40
105
fCPU = 60 MHz
–40
125
SR Internal reference voltage
SR
Ambient temperature under
bias
Unit
V
°C
1. Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.
In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.
2. The difference between each couple of voltage supplies must be less than 100 mV, |VDD_HV_IOy – VDD_HV_IOx | < 100 mV.
3. The difference between each couple of voltage supplies must be less than 100 mV, |VDD_HV_ADC1 – VDD_HV_ADC0| < 100
mV. As long as that condition is met, ADC_0 and ADC_1 can be operated at 5 V with the rest of the device operating at 3.3
V.
4. To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an onchip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to high
voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast
emitter.
5. The low voltage supplies (VDD_LV_xxx) are not all independent.
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low
voltage supply to the data flash module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
VDD_LV_REGCOR and VDD_LV_REGCORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Figure 7 shows the constraints of the different power supplies.
VDD_HV_xxx
5.5 V
3.3 V
3.0 V
VDD_HV_IOx
3.0 V
3.3 V
5.5 V
Note: IO AC and DC characteristics are guaranteed only in the range of 3.0–3.6 V when
PAD3V5V is low, and in the range of 4.5–5.5 V when PAD3V5V is high.
Figure 7.
Power supplies constraints (3.0 V ≤ VDD_HV_IOx ≤ 5.5 V)
Doc ID 14723 Rev 9
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
The SPC560P44Lx, SPC560P50Lx supply architecture allows the ADC supply to be
managed independently from the standard VDD_HV supply. Figure 8 shows the constraints
of the ADC power supply.
VDD_HV_ADCx
5.5 V
3.0 V
VDD_HV_REG
3.0 V
Figure 8.
Independent ADC supply (3.0 V ≤ VDD_HV_REG ≤ 5.5 V)
3.5
Thermal characteristics
3.5.1
Package thermal characteristics
Table 12.
5.5 V
Thermal characteristics for 144-pin LQFP
Conditions
Typical
value
Unit
Single layer board—1s
54.2
°C/
W
Four layer board—
2s2p
44.4
°C/
W
Thermal resistance junction-to-board(2)
Four layer board—
2s2p
29.9
°C/
W
Thermal resistance junction-to-case
(top)(3)
Single layer board—1s
9.3
°C/
W
ΨJB
Junction-to-board, natural convection(4)
Operating conditions
30.2
°C/
W
ΨJC
Junction-to-case, natural convection(5)
Operating conditions
0.8
°C/
W
Symbol
RθJA
RθJB
RθJCtop
Parameter
Thermal resistance junction-to-ambient,
natural convection(1)
1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets
JEDEC specification for this package.
56/112
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Electrical characteristics
2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the
interface layer.
4. Thermal characterization parameter indicating the temperature difference between the board and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JB.
5. Thermal characterization parameter indicating the temperature difference between the case and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JC.
Table 13.
Thermal characteristics for 100-pin LQFP
Symbol
Parameter
Conditions
Typical value Unit
Single layer board—1s
47.3
°C/
W
Four layer board—2s2p
35.3
°C/
W
Thermal resistance junction-to-board(2)
Four layer board—2s2p
19.1
°C/
W
Thermal resistance junction-to-case
(top)(3)
Single layer board—1s
9.7
°C/
W
ΨJB
Junction-to-board, natural convection(4)
Operating conditions
19.1
°C/
W
ΨJC
Junction-to-case, natural convection(5)
Operating conditions
0.8
°C/
W
RθJA
RθJB
RθJCtop
Thermal resistance junction-to-ambient,
natural convection(1)
1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets
JEDEC specification for this package.
2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the
interface layer.
4. Thermal characterization parameter indicating the temperature difference between the board and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JB.
5. Thermal characterization parameter indicating the temperature difference between the case and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JC.
3.5.2
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
Equation 1 TJ = TA + (RθJA * PD)
where:
TA
= ambient temperature for the package (°C)
RθJA
= junction to ambient thermal resistance (°C/W)
PD
= power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by a
factor of two. Which value is closer to the application depends on the power dissipated by
other components on the board. The value obtained on a single layer board is appropriate
for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are
well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a
junction to case thermal resistance and a case to ambient thermal resistance:
Equation 2 RθJA = RθJC + RθCA
where:
RθJA
= junction to ambient thermal resistance (°C/W)
RθJC
= junction to case thermal resistance (°C/W)
RθCA
= case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal
environment to change the case to ambient thermal resistance, RθCA. For instance, the user
can change the size of the heat sink, the air flow around the device, the interface material,
the mounting arrangement on printed circuit board, or change the thermal dissipation on the
printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are
not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using Equation 3:
Equation 3 TJ = TT + (ΨJT x PD)
where:
TT
= thermocouple temperature on top of the package (°C)
ΨJT
= thermal characterization parameter (°C/W)
PD
= power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40
gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the package.
A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of
wire extending from the junction. The thermocouple wire is placed flat against the package
case to avoid measurement errors caused by cooling effects of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
U.S.A.
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global
Engineering Documents at 800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
58/112
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Electrical characteristics
1.
C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module, Proceedings of SemiTherm, San Diego, 1998,
pp. 47–54.
2.
G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled
Applications, Electronic Packaging and Production, pp. 53–58, March 1998.
3.
B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling, Proceedings of SemiTherm, San
Diego, 1999, pp. 212–220.
3.6
Electromagnetic interference (EMI) characteristics
Table 14.
EMI testing specifications
Symbol
Parameter
Conditions
Clocks
fOSC 8 MHz
Device configuration, test
fCPU 64 MHz
conditions and EM testing per
No PLL frequency
standard IEC61967-2
modulation
VEME
Level
Frequency
Unit
(Max)
150 kHz–150 MHz
16
150–1000 MHz
15
IEC Level
M
dBµV
—
Radiated emissions
150 kHz–150 MHz
fOSC 8 MHz
Supply voltage = 5 V DC
f
64 MHz
150–1000 MHz
Ambient temperature = 25 °C CPU
1% PLL frequency
Worst-case orientation
IEC Level
modulation
3.7
Electrostatic discharge (ESD) characteristics
Table 15.
ESD ratings(1),(2)
Symbol
Parameter
15
dBµV
14
M
—
Conditions
Value
Unit
2000
V
VESD(HBM)
S
Electrostatic discharge (Human Body Model)
R
—
VESD(CDM)
S
Electrostatic discharge (Charged Device Model)
R
—
750 (corners)
V
500 (other)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
3.8
Power management electrical characteristics
3.8.1
Voltage regulator electrical characteristics
The internal voltage regulator requires an external NPN ballast to be connected as shown in
Figure 9. Table 16 contains all approved NPN ballast components. Capacitances should be
placed on the board as near as possible to the associated pins. Care should also be taken
to limit the serial inductance of the VDD_HV_REG, BCTRL and VDD_LV_CORx pins to less than
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
LReg, see Table 17.
Note:
The voltage regulator output cannot be used to drive external circuits. Output pins are used
only for decoupling capacitances.
VDD_LV_COR must be generated using internal regulator and external NPN transistor. It is
not possible to provide VDD_LV_COR through external regulator.
For the SPC560P44Lx, SPC560P50Lx microcontroller, capacitors, with total values not
below CDEC1, should be placed between VDD_LV_CORx/VSS_LV_CORx close to external
ballast transistor emitter. 4 capacitors, with total values not below CDEC2, should be placed
close to microcontroller pins between each VDD_LV_CORx/VSS_LV_CORx supply pairs and the
VDD_LV_REGCOR/VSS_LV_REGCOR pair . Additionally, capacitors with total values not below
CDEC3, should be placed between the VDD_HV_REG/VSS_HV_REG pins close to ballast
collector. Capacitors values have to take into account capacitor accuracy, aging and
variation versus temperature.
All reported information are valid for voltage and temperature ranges described in
recommended operating condition, Table 10 and Table 11.
VDD_HV_REG
CDEC3
SPC560P44Lx,
BJT(1)
BCTRL
RB
VDD_LV_COR
CDEC2
CDEC1
1. Refer to Table 16.
Figure 9.
Configuration with resistor on base
Table 16.
Approved NPN ballast components (configuration with resistor on base)
Manufacturer
Approved derivatives(1)
ON Semi
BCP68
NXP
BCP68-25
Infineon
BCP68-25
BCX68
Infineon
BCX68-10;BCX68-16;BCX68-25
BC868
NXP
BC868
Part
BCP68
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Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Table 16.
Electrical characteristics
Approved NPN ballast components (configuration with resistor on base)
Part
Manufacturer
Approved derivatives(1)
Infineon
BC817-16;BC817-25;BC817SU;
NXP
BC817-16;BC817-25
ST
BCP56-16
Infineon
BCP56-10;BCP56-16
ON Semi
BCP56-10
NXP
BCP56-10;BCP56-16
BC817
BCP56
1. For automotive applications please check with the appropriate transistor vendor for automotive grade
certification
Table 17.
Voltage regulator electrical characteristics (configuration with resistor on base)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Output voltage under
VDD_LV_REGCOR CC P maximum load run supply
current configuration
RB
CDEC1
RREG
SR —
SR —
1.15
—
1.32
V
18
—
22
kΩ
BJT from Table 16. 3
capacitances (i.e. X7R or
X8R capacitors) with nominal
value of 10 µF
19.5
30
—
µF
BJT BC817, one capacitance
of 22 µF
14.3
22
Resulting ESR of all three
capacitors of CDEC1
BJT from Table 16. 3x10 µF.
Absolute maximum value
between 100 kHz and
10 MHz
—
—
50
mΩ
Resulting ESR of the unique
capacitor CDEC1
BJT BC817, 1x 22 µF.
Absolute maximum value
between 100 kHz and
10 MHz
10
—
40
mΩ
External decoupling/stability
ceramic capacitor
4 capacitances (i.e. X7R or
X8R capacitors) with nominal 1200 1760
value of 440 nF
—
nF
3 capacitances (i.e. X7R or
X8R capacitors) with nominal
value of 10 µF; CDEC3 has to
be equal or greater than
CDEC1
External resistance on bipolar
junction transistor (BJT) base
External decoupling/stability
ceramic capacitor
—
µF
SR —
CDEC2
SR —
CDEC3
External decoupling/stability
SR — ceramic capacitor on
VDD_HV_REG
LReg
Post-trimming
Typ Max
SR —
Resulting ESL of VDD_HV_REG,
—
BCTRL and VDD_LV_CORx pins
Doc ID 14723 Rev 9
19.5
30
—
µF
—
—
15
nH
61/112
Electrical characteristics
SPC560P44Lx, SPC560P50Lx
VDD_HV_REG
CDEC3
SPC560P44Lx,
BCP56,
BCP68,
BCX68,
BC817
BCTRL
VDD_LV_COR
CDEC2
CDEC1
Figure 10. Configuration without resistor on base
Table 18.
Voltage regulator electrical characteristics (configuration without resistor on base)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Output voltage under
VDD_LV_REGCOR CC P maximum load run supply
current configuration
Typ Max
Post-trimming
1.15
—
1.32
V
CDEC1
SR —
External decoupling/stability
ceramic capacitor
4 capacitances
40
56
—
µF
RREG
SR —
Resulting ESR of all four
CDEC1
Absolute maximum value
between 100 kHz and
10 MHz
—
—
45
mΩ
CDEC2
SR —
External decoupling/stability
ceramic capacitor
4 capacitances of 100 nF
each
400
—
—
nF
CDEC3
External decoupling/stability
SR — ceramic capacitor on
VDD_HV_REG
40
—
—
µF
—
—
15
nH
LReg
62/112
SR —
Resulting ESL of VDD_HV_REG,
—
BCTRL and VDD_LV_CORx pins
Doc ID 14723 Rev 9
—
SPC560P44Lx, SPC560P50Lx
3.8.2
Electrical characteristics
Voltage monitor electrical characteristics
The device implements a Power-on Reset module to ensure correct power-up initialization,
as well as three low voltage detectors to monitor the VDD and the VDD_LV voltage while
device is supplied:
Table 19.
●
POR monitors VDD during the power-up phase to ensure device is maintained in a safe
reset state
●
LVDHV3 monitors VDD to ensure device reset below minimum functional supply
●
LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10 % range
●
LVDLVCOR monitors low voltage digital power domain
Low voltage monitor electrical characteristics
Symbol
C
Parameter
Value
Conditions
Unit
(1)
Min
Max
—
1.5
2.7
V
TA = 25 °C
1.0
—
V
VPORH
T
Power-on reset threshold
VPORUP
P
Supply for functional POR module
VREGLVDMOK_H
P
Regulator low voltage detector high threshold
—
—
2.95
V
VREGLVDMOK_L
P
Regulator low voltage detector low threshold
—
2.6
—
V
VFLLVDMOK_H
P
Flash low voltage detector high threshold
—
—
2.95
V
VFLLVDMOK_L
P
Flash low voltage detector low threshold
—
2.6
—
V
VIOLVDMOK_H
P
I/O low voltage detector high threshold
—
—
2.95
V
VIOLVDMOK_L
P
I/O low voltage detector low threshold
—
2.6
—
V
VIOLVDM5OK_H
P
I/O 5V low voltage detector high threshold
—
—
4.4
V
VIOLVDM5OK_L
P
I/O 5V low voltage detector low threshold
—
3.8
—
V
VMLVDDOK_H
P
Digital supply low voltage detector high
—
—
1.145
V
VMLVDDOK_L
P
Digital supply low voltage detector low
—
1.08
—
V
1. VDD = 3.3V ± 10% / 5.0V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
3.9
Power up/down sequencing
To prevent an overstress event or a malfunction within and outside the device, the
SPC560P44Lx, SPC560P50Lx implements the following sequence to ensure each module
is started only when all conditions for switching it ON are available:
●
A POWER_ON module working on voltage regulator supply controls the correct startup of the regulator. This is a key module ensuring safe configuration for all voltage
regulator functionality when supply is below 1.5V. Associated POWER_ON (or POR)
signal is active low.
●
Several low voltage detectors, working on voltage regulator supply monitor the voltage
of the critical modules (voltage regulator, I/Os, flash memory and low voltage domain).
LVDs are gated low when POWER_ON is active.
●
A POWER_OK signal is generated when all critical supplies monitored by the LVD are
available. This signal is active high and released to all modules including I/Os, flash
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
memory and RC16 oscillator needed during power-up phase and reset phase. When
POWER_OK is low the associated module are set into a safe state.
VDD_HV_REG
VPORH
VLVDHV3H
3.3V
VPOR_UP
0V
3.3V
POWER_ON
0V
3.3V
LVDM (HV)
0V
VDD_LV_REGCOR
VMLVDOK_H
1.2V
0V
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
~1us
Internal Reset Generation Module
FSM
Figure 11.
P0
P1
1.2V
0V
Power-up typical sequence
VDD_HV_REG
VLVDHV3L
VPORH
3.3V
0V
3.3V
LVDM (HV)
0V
3.3V
POWER_ON
0V
1.2V
0V
VDD_LV_REGCOR
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
Internal Reset Generation Module
FSM
IDLE
P0
Figure 12. Power-down typical sequence
64/112
Doc ID 14723 Rev 9
1.2V
0V
SPC560P44Lx, SPC560P50Lx
Electrical characteristics
VLVDHV3L
VLVDHV3H
3.3V
VDD_HV_REG
0V
3.3V
LVDM (HV)
0V
3.3V
POWER_ON
0V
1.2V
0V
VDD_LV_REGCOR
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
~1us
Internal Reset Generation Module
FSM
IDLE
P0
P1
1.2V
0V
Figure 13. Brown-out typical sequence
3.10
DC electrical characteristics
3.10.1
NVUSRO register
Portions of the device configuration, such as high voltage supply, and watchdog
enable/disable after reset are controlled via bit values in the non-volatile user options
(NVUSRO) register.
For a detailed description of the NVUSRO register, please refer to the device reference
manual.
NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 20 shows
how NVUSRO[PAD3V5V] controls the device configuration.
Table 20.
PAD3V5V field description
Value(1)
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
1. Default manufacturing value before flash initialization is ‘1’ (3.3 V).
Doc ID 14723 Rev 9
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Electrical characteristics
3.10.2
SPC560P44Lx, SPC560P50Lx
DC electrical characteristics (5 V)
Table 21 gives the DC electrical characteristics at 5 V (4.5 V < VDD_HV_IOx < 5.5 V,
NVUSRO[PAD3V5V] = 0); see Figure 14.
Table 21.
DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)
Value
Symbol C
Parameter
Conditions
Unit
Min
Max
—
–0.1(1)
—
V
—
—
0.35 VDD_HV_IOx
V
—
0.65 VDD_HV_IOx
—
V
D
—
—
VDD_HV_IOx + 0.1(1)
V
VHYS
T Schmitt trigger hysteresis
—
0.1 VDD_HV_IOx
—
V
VOL_S
P Slow, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_S
P Slow, high level output voltage
IOH = –3 mA
0.8 VDD_HV_IOx
—
V
VOL_M
P Medium, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_M
P Medium, high level output voltage
IOH = –3 mA
0.8 VDD_HV_IOx
—
V
VOL_F
P Fast, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_F
P Fast, high level output voltage
IOH = –3 mA
0.8 VDD_HV_IOx
—
V
VOL_SYM P Symmetric, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_SYM P Symmetric, high level output voltage
IOH = –3 mA
0.8 VDD_HV_IOx
—
V
VIN = VIL
–130
—
VIN = VIH
—
–10
VIN = VIL
10
—
VIN = VIH
—
130
TA = –40 to 125 °C
–1
1
µA
–0.5
0.5
µA
—
10
pF
VIN = VIL
–130
—
VIN = VIH
—
–10
D
VIL
Low level input voltage
P
P
VIH
High level input voltage
IPU
P Equivalent pull-up current
IPD
P Equivalent pull-down current
IIL
P
Input leakage current (all
bidirectional ports)
IIL
P
Input leakage current (all ADC inputTA = –40 to 125 °C
only ports)
CIN
D Input capacitance
IPU
D RESET, equivalent pull-up current
—
µA
µA
µA
1. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.
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Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Table 22.
Electrical characteristics
Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)
Value
Symbol
C
Parameter
Conditions
RUN—Maximum mode(1)
VDD_LV_CORx
externally forced at 1.3 V
T
RUN—Typical mode(2)
P
IDD_FLASH
T
Supply current
IDD_LV_CORx
Max
40 MHz
62
77
64 MHz
71
88
40 MHz
45
56
64 MHz
52
65
RUN—Maximum mode(3)
VDD_LV_CORx
externally forced at 1.3 V
64 MHz
60
75
HALT mode(4)
VDD_LV_CORx
externally forced at 1.3 V
—
1.5
10
STOP mode(5)
VDD_LV_CORx
externally forced at 1.3 V
—
1
10
Flash during read
VDD_HV_FL at 5.0 V
—
10
12
Flash during erase operation on 1
VDD_HV_FL at 5.0 V
flash module
—
15
19
ADC_1
3.5
5
ADC_0
3
4
ADC_1
0.8
1
ADC—Maximum mode(1)
IDD_ADC
Unit
Typ
T
ADC—Typical mode(2)
VDD_HV_ADC0 at 5.0 V
VDD_HV_ADC1 at 5.0 V
fADC = 16 MHz
ADC_0
IDD_OSC
T
Oscillator
VDD_OSC at 5.0 V
8 MHz
mA
0.005 0.006
2.6
3.2
1. Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled. I/O supply
current excluded.
2. Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only. I/O supply current excluded.
3. Code fetched from RAM, PLL_0: 64 MHz system clock (x4 multiplier with 16 MHz XTAL), PLL_1 is ON at
PHI_div2 = 120 MHz and PHI_div3 = 80 MHz, auxiliary clock sources set that all peripherals receive maximum frequency,
all peripherals enabled.
4. Halt mode configurations: code fetched from RAM, code and data flash memories in low power mode, OSC/PLL_0/PLL_1
are OFF, core clock frozen, all peripherals are disabled.
5. STOP “P” mode Device Under Test (DUT) configuration: code fetched from RAM, code and data flash memories OFF,
OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.
3.10.3
DC electrical characteristics (3.3 V)
Table 23 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V,
NVUSRO[PAD3V5V] = 1); see Figure 14.
DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)(1)
Table 23.
Value
Symbol C
Parameter
D
VIL
Conditions
Unit
Min
Max
—
–0.1(2)
—
V
—
—
0.35 VDD_HV_IOx
V
Low level input voltage
P
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)(1) (continued)
Table 23.
Value
Symbol C
Parameter
Conditions
P
VIH
—
High level input voltage
Unit
Min
Max
0.65 VDD_HV_IOx
—
V
(2)
D
—
—
VDD_HV_IOx + 0.1
VHYS
T Schmitt trigger hysteresis
—
0.1 VDD_HV_IOx
—
V
VOL_S
P Slow, low level output voltage
IOL = 1.5 mA
—
0.5
V
VOH_S
P Slow, high level output voltage
IOH = –1.5 mA
VDD_HV_IOx – 0.8
—
V
VOL_M
P Medium, low level output voltage
IOL = 2 mA
—
0.5
V
VOH_M
P Medium, high level output voltage
IOH = –2 mA
VDD_HV_IOx – 0.8
—
V
VOL_F
P Fast, low level output voltage
IOL = 1.5 mA
—
0.5
V
VOH_F
P Fast, high level output voltage
IOH = –1.5 mA
VDD_HV_IOx – 0.8
—
V
VOL_SYM P Symmetric, low level output voltage
IOL = 1.5 mA
—
0.5
V
VOH_SYM P Symmetric, high level output voltage
IOH = –1.5 mA
VDD_HV_IOx – 0.8
—
V
VIN = VIL
–130
—
VIN = VIH
—
–10
VIN = VIL
10
—
VIN = VIH
—
130
V
IPU
P Equivalent pull-up current
IPD
P Equivalent pull-down current
IIL
P
Input leakage current (all
bidirectional ports)
TA = –40 to 125 °C
—
1
µA
IIL
P
Input leakage current (all ADC inputTA = –40 to 125 °C
only ports)
—
0.5
µA
CIN
D Input capacitance
—
10
pF
—
D RESET, equivalent pull-up current
VIN = VIL
–130
IPU
VIN = VIH
—
–10
—
µA
µA
µA
1. These specifications are design targets and subject to change per device characterization.
2. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.
68/112
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Table 24.
Electrical characteristics
Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)
Value
Symbol
C
Parameter
Conditions
RUN—Maximum mode(1)
VDD_LV_CORx
externally forced at 1.3 V
T
RUN—Typical mode(2)
P
IDD_FLASH
T
Supply current
IDD_LV_CORx
Max
40 MHz
62
77
64 MHz
71
89
40 MHz
45
56
64 MHz
53
66
RUN—Maximum mode(3)
VDD_LV_CORx
externally forced at 1.3 V
64 MHz
60
75
HALT mode(4)
VDD_LV_CORx
externally forced at 1.3 V
—
1.5
10
STOP mode(5)
VDD_LV_CORx
externally forced at 1.3 V
—
1
10
Flash during read on single mode
VDD_HV_FL at 3.3 V
—
8
10
Flash during erase operation on
single mode
VDD_HV_FL at 3.3 V
—
10
12
ADC_1
2.5
4
ADC_0
2
4
ADC_1
0.8
1
ADC—Maximum mode(1)
IDD_ADC
Unit
Typ
T
ADC—Typical mode(2)
VDD_HV_ADC0 at 3.3 V
VDD_HV_ADC1 at 3.3 V
fADC = 16 MHz
mA
ADC_0 0.005 0.006
IDD_OSC
T
Oscillator
VDD_OSC at 3.3 V
8 MHz
2.4
3
1. Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled. I/O supply
current excluded.
2. Typical mode: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only. I/O supply current excluded.
3. Code fetched from RAM, PLL_0: 64 MHz system clock (x4 multiplier with 16 MHz XTAL), PLL_1 is ON at
PHI_div2 = 120 MHz and PHI_div3 = 80 MHz, auxiliary clock sources set that all peripherals receive maximum frequency,
all peripherals enabled.
4. Halt mode configurations: code fetched from RAM, code and data flash memories in low power mode, OSC/PLL_0/PLL_1
are OFF, core clock frozen, all peripherals are disabled.
5. STOP “P” mode Device Under Test (DUT) configuration: code fetched from RAM, code and data flash memories OFF,
OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.
3.10.4
Input DC electrical characteristics definition
Figure 14 shows the DC electrical characteristics behavior as function of time.
Doc ID 14723 Rev 9
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Figure 14. Input DC electrical characteristics definition
3.10.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD/VSS supply pair as described in Table 25.
Table 25.
I/O supply segment
Supply segment
Package
1
2
3
4
5
6
7
LQFP144 pin8 – pin20 pin23 – pin38 pin39 – pin55 pin58 – pin68 pin73 – pin89 pin92 – pin125 pin128 – pin5
LQFP100 pin15 – pin26 pin27 – pin38 pin41 – pin46 pin51 – pin61 pin64 – pin86 pin89 – pin10
—
Table 26 provides the weight of concurrent switching I/Os.
In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on
a single segment should remain below 100%.
Table 26.
I/O weight
LQFP144
LQFP100
Pad
70/112
Weight 5V
Weight 3.3V
Weight 5V
Weight 3.3V
NMI
1%
1%
1%
1%
PAD[6]
6%
5%
14%
13%
PAD[49]
5%
4%
14%
12%
PAD[84]
14%
10%
—
—
PAD[85]
9%
7%
—
—
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Table 26.
Electrical characteristics
I/O weight (continued)
LQFP144
LQFP100
Pad
Weight 5V
Weight 3.3V
Weight 5V
Weight 3.3V
PAD[86]
9%
6%
—
—
MODO[0]
12%
8%
—
—
PAD[7]
4%
4%
11%
10%
PAD[36]
5%
4%
11%
9%
PAD[8]
5%
4%
10%
9%
PAD[37]
5%
4%
10%
9%
PAD[5]
5%
4%
9%
8%
PAD[39]
5%
4%
9%
8%
PAD[35]
5%
4%
8%
7%
PAD[87]
12%
9%
—
—
PAD[88]
9%
6%
—
—
PAD[89]
10%
7%
—
—
PAD[90]
15%
11%
—
—
PAD[91]
6%
5%
—
—
PAD[57]
8%
7%
8%
7%
PAD[56]
13%
11%
13%
11%
PAD[53]
14%
12%
14%
12%
PAD[54]
15%
13%
15%
13%
PAD[55]
25%
22%
25%
22%
PAD[96]
27%
24%
—
—
PAD[65]
1%
1%
1%
1%
PAD[67]
1%
1%
—
—
PAD[33]
1%
1%
1%
1%
PAD[68]
1%
1%
—
—
PAD[23]
1%
1%
1%
1%
PAD[69]
1%
1%
—
—
PAD[34]
1%
1%
1%
1%
PAD[70]
1%
1%
—
—
PAD[24]
1%
1%
1%
1%
PAD[71]
1%
1%
—
—
PAD[66]
1%
1%
1%
1%
PAD[25]
1%
1%
1%
1%
PAD[26]
1%
1%
1%
1%
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Electrical characteristics
Table 26.
SPC560P44Lx, SPC560P50Lx
I/O weight (continued)
LQFP144
LQFP100
Pad
72/112
Weight 5V
Weight 3.3V
Weight 5V
Weight 3.3V
PAD[27]
1%
1%
1%
1%
PAD[28]
1%
1%
1%
1%
PAD[63]
1%
1%
1%
1%
PAD[72]
1%
1%
—
—
PAD[29]
1%
1%
1%
1%
PAD[73]
1%
1%
—
—
PAD[31]
1%
1%
1%
1%
PAD[74]
1%
1%
—
—
PAD[30]
1%
1%
1%
1%
PAD[75]
1%
1%
—
—
PAD[32]
1%
1%
1%
1%
PAD[76]
1%
1%
—
—
PAD[64]
1%
1%
1%
1%
PAD[0]
23%
20%
23%
20%
PAD[1]
21%
18%
21%
18%
PAD[107]
20%
17%
—
—
PAD[58]
19%
16%
19%
16%
PAD[106]
18%
16%
—
—
PAD[59]
17%
15%
17%
15%
PAD[105]
16%
14%
—
—
PAD[43]
15%
13%
15%
13%
PAD[104]
14%
13%
—
—
PAD[44]
13%
12%
13%
12%
PAD[103]
12%
11%
—
—
PAD[2]
11%
10%
11%
10%
PAD[101]
11%
9%
—
—
PAD[21]
10%
8%
10%
8%
TMS
1%
1%
1%
1%
TCK
1%
1%
1%
1%
PAD[20]
16%
11%
16%
11%
PAD[3]
4%
3%
4%
3%
PAD[61]
9%
8%
9%
8%
PAD[102]
11%
10%
—
—
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Table 26.
Electrical characteristics
I/O weight (continued)
LQFP144
LQFP100
Pad
Weight 5V
Weight 3.3V
Weight 5V
Weight 3.3V
PAD[60]
11%
10%
11%
10%
PAD[100]
12%
10%
—
—
PAD[45]
12%
10%
12%
10%
PAD[98]
12%
11%
—
—
PAD[46]
12%
11%
12%
11%
PAD[99]
13%
11%
—
—
PAD[62]
13%
11%
13%
11%
PAD[92]
13%
12%
—
—
VPP_TEST
1%
1%
1%
1%
PAD[4]
14%
12%
14%
12%
PAD[16]
13%
12%
13%
12%
PAD[17]
13%
11%
13%
11%
PAD[42]
13%
11%
13%
11%
PAD[93]
12%
11%
—
—
PAD[95]
12%
11%
—
—
PAD[18]
12%
10%
12%
10%
PAD[94]
11%
10%
—
—
PAD[19]
11%
10%
11%
10%
PAD[77]
10%
9%
—
—
PAD[10]
10%
9%
10%
9%
PAD[78]
9%
8%
—
—
PAD[11]
9%
8%
9%
8%
PAD[79]
8%
7%
—
—
PAD[12]
7%
7%
7%
7%
PAD[41]
7%
6%
7%
6%
PAD[47]
5%
4%
5%
4%
PAD[48]
4%
4%
4%
4%
PAD[51]
4%
4%
4%
4%
PAD[52]
5%
4%
5%
4%
PAD[40]
5%
5%
6%
5%
PAD[80]
9%
8%
—
—
PAD[9]
10%
9%
11%
10%
PAD[81]
10%
9%
—
—
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Electrical characteristics
Table 26.
SPC560P44Lx, SPC560P50Lx
I/O weight (continued)
LQFP144
LQFP100
Pad
Table 27.
Symbol
ISWTSLW
(2)
ISWTMED(2)
ISWTFST(2)
Weight 5V
Weight 3.3V
Weight 5V
Weight 3.3V
PAD[13]
10%
9%
12%
11%
PAD[82]
10%
9%
—
—
PAD[22]
10%
9%
13%
12%
PAD[83]
10%
9%
—
—
PAD[50]
10%
9%
14%
12%
PAD[97]
10%
9%
—
—
PAD[38]
10%
9%
14%
13%
PAD[14]
9%
8%
14%
13%
PAD[15]
9%
8%
15%
13%
I/O consumption
C
Dynamic I/O current
CC D for SLOW
configuration
Dynamic I/O current
CC D for MEDIUM
configuration
Dynamic I/O current
CC D for FAST
configuration
CL = 25 pF
CL = 25 pF
CL = 25 pF
CL = 25 pF, 4 MHz
Typ
Max
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
20
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
16
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
29
mA
mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
17
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
110
mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
Root medium square C = 100 pF, 2 MHz
L
CC D I/O current for SLOW
C
L = 25 pF, 2 MHz
configuration
CL = 25 pF, 4 MHz
—
—
50
—
—
2.3
—
—
3.2
—
—
6.6
—
—
1.6
—
—
2.3
—
—
4.7
mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 2 MHz
74/112
Unit
Min
CL = 25 pF, 2 MHz
IRMSSLW
Value
Conditions(1)
Parameter
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Table 27.
Symbol
Electrical characteristics
I/O consumption (continued)
C
Value
Conditions(1)
Parameter
Unit
Min
Typ
Max
—
—
6.6
—
—
13.4
—
—
18.3
—
—
5
—
—
8.5
—
—
11
—
—
22
—
—
33
—
—
56
—
—
14
—
—
20
CL = 100 pF, 40 MHz
—
—
35
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
70
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
65
CL = 25 pF, 13 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
IRMSMED
CL = 25 pF, 40 MHz
Root medium square
CL = 100 pF, 13 MHz
I/O current for
CC D
MEDIUM
CL = 25 pF, 13 MHz
configuration
VDD = 3.3 V ± 10%,
CL = 25 pF, 40 MHz
PAD3V5V = 1
CL = 100 pF, 13 MHz
CL = 25 pF, 40 MHz
CL = 25 pF, 64 MHz
IRMSFST
Root medium square C = 100 pF, 40 MHz
L
CC D I/O current for FAST
CL = 25 pF, 40 MHz
configuration
CL = 25 pF, 64 MHz
IAVGSEG
VDD = 5.0 V ± 10%,
PAD3V5V = 0
Sum of all the static
SR D I/O current within a
supply segment
mA
mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
mA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
3.11
Main oscillator electrical characteristics
The SPC560P44Lx, SPC560P50Lx provides an oscillator/resonator driver.
Table 28.
Main oscillator output electrical characteristics (5.0 V,
NVUSRO[PAD3V5V] = 0)
Value
Symbol
C
Parameter
Unit
Min
Max
4
40
MHz
fOSC
SR
—
Oscillator
frequency
gm
—
P
Transconduc
tance
6.5
25
mA/V
VOSC
—
T
Oscillation
amplitude on
XTAL pin
1
—
V
tOSCSU
—
T
Start-up
time(1),(2)
8
—
ms
1. The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive
capacitive loads can cause long start-up time.
2. Value captured when amplitude reaches 90% of XTAL
Doc ID 14723 Rev 9
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Electrical characteristics
Table 29.
SPC560P44Lx, SPC560P50Lx
Main oscillator output electrical characteristics (3.3 V,
NVUSRO[PAD3V5V] = 1)
Value
Symbol
C
Parameter
Unit
Min
Max
fOSC
SR
— Oscillator frequency
4
40
MHz
gm
—
P Transconductance
4
20
mA/V
VOSC
—
T
1
—
V
8
—
ms
tOSCSU
—
T
Oscillation amplitude on XTAL pin
Start-up time
(1),(2)
1. The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive
capacitive loads can cause long start-up time.
2. Value captured when amplitude reaches 90% of XTAL
Table 30.
Input clock characteristics
Value
Symbol
Parameter
Unit
Typ
Max
fOSC
SR Oscillator frequency
4
—
40
MHz
fCLK
SR Frequency in bypass
—
—
64
MHz
trCLK
SR Rise/fall time in bypass
—
—
1
ns
47.5
50
52.5
%
tDC
SR Duty cycle
3.12
FMPLL electrical characteristics
Table 31.
FMPLL electrical characteristics
Symbol
Min
C
Value
Conditions(1)
Parameter
Unit
Min
Max
4
40
MHz
fref_crystal
fref_ext
D
PLL reference frequency range(2)
fPLLIN
D
Phase detector input frequency range
(after pre-divider)
—
4
16
MHz
fFMPLLOUT
D
Clock frequency range in normal mode
—
16
120
MHz
fFREE
P
Free-running frequency
Measured using clock
division — typically /16
20
150
MHz
tCYC
D
System clock period
—
—
1 / fSYS
ns
fLORL
fLORH
Loss of reference frequency window(3)
Lower limit
1.6
3.7
D
Upper limit
24
56
fSCM
D
20
150
76/112
Crystal reference
MHz
Self-clocked mode frequency(4),(5)
Doc ID 14723 Rev 9
—
MHz
SPC560P44Lx, SPC560P50Lx
Table 31.
Symbol
Electrical characteristics
FMPLL electrical characteristics (continued)
C
Short-term jitter(10)
CLKOUT period
jitter(6),(7),(8),(9)
Value
Conditions(1)
Parameter
fSYS maximum
= 16 MHz
f
Long-term jitter (avg. PLLIN
(resonator), fPLLCLK at
over 2 ms interval)
64 MHz, 4000 cycles
Unit
Min
Max
−4
4
% fCLKOUT
—
10
ns
CJITTER
T
tlpll
D
PLL lock time (11), (12)
—
—
200
µs
tdc
D
Duty cycle of reference
—
40
60
%
fLCK
D
Frequency LOCK range
—
−6
6
% fSYS
fUL
D
Frequency un-LOCK range
—
-18
18
% fSYS
fCS
fDS
Center spread
±0.25
±4.0(13)
D
Modulation depth
Down spread
−0.5
−8.0
fMOD
D
—
70
Modulation frequency(14)
—
% fSYS
kHz
1. VDD_LV_CORx = 1.2 V ±10%; VSS = 0 V; TA = –40 to 125 °C, unless otherwise specified
2. Considering operation with PLL not bypassed
3. “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self-clocked mode.
4. Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR
window.
5. fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced
mode.
6. This value is determined by the crystal manufacturer and board design.
7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER
percentage for a given interval.
8. Proper PC board layout procedures must be followed to achieve specifications.
9. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either
fCS or fDS (depending on whether center spread or down spread modulation is enabled).
10. Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.
11. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this
PLL, load capacitors should not exceed these limits.
12. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
13. This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).
14. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
Doc ID 14723 Rev 9
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
3.13
16 MHz RC oscillator electrical characteristics
Table 32.
16 MHz RC oscillator electrical characteristics
Value
Symbol
fRC
C
Parameter
P RC oscillator frequency
ΔRCMVAR
Fast internal RC oscillator variation over temperature
and
P
supply with respect to fRC at TA = 25 °C in highfrequency configuration
ΔRCMTRIM
T
ΔRCMSTEP
T Fast internal RC oscillator trimming step
Post Trim Accuracy: The variation of the PTF(1) from
the 16 MHz
Conditions
Unit
Min
Typ
Max
TA = 25 °C
—
16
—
MHz
—
–5
—
5
%
TA = 25 °C
–1
—
1
%
TA = 25 °C
—
1.6
—
%
1. PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and
temperature
3.14
Analog-to-digital converter (ADC) electrical characteristics
The device provides a 10-bit successive approximation register (SAR) analog-to-digital
converter.
78/112
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Electrical characteristics
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(5)
(2) The ideal transfer curve
4
(3) Differential non-linearity error (DNL)
(4)
(4) Integral non-linearity error (INL)
3
(5) Center of a step of the actual transfer curve
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error OSE
Figure 15. ADC characteristics and error definitions
3.14.1
Input impedance and ADC accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it
sources charge during the sampling phase, when the analog signal source is a highimpedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the source
impedance value of the transducer or circuit supplying the analog signal to be measured.
Doc ID 14723 Rev 9
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
The filter at the input pins must be designed taking into account the dynamic characteristics
of the input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: CS and CP2 being substantially two switched capacitances, with a
frequency equal to the ADC conversion rate, it can be seen as a resistive path to ground.
For instance, assuming a conversion rate of 1 MHz, with CS+CP2 equal to 3 pF, a resistance
of 330 kΩ is obtained (REQ = 1 / (fc × (CS+CP2)), where fc represents the conversion rate at
the considered channel). To minimize the error induced by the voltage partitioning between
this resistance (sampled voltage on CS+CP2) and the sum of RS + RF, the external circuit
must be designed to respect the Equation 4:
Equation 4
RS + R F
1
V A • --------------------- < --- LSB
R EQ
2
Equation 4 generates a constraint for external network design, in particular on resistive
path.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
VA
Filter
RF
Current Limiter
RL
CF
CP1
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1 and CP2)
CS: Sampling capacitance
Figure 16. Input equivalent circuit
80/112
Doc ID 14723 Rev 9
Channel
Selection
Sampling
RSW1
RAD
CP2
CS
SPC560P44Lx, SPC560P50Lx
Electrical characteristics
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the
equivalent circuit reported in Figure 16): A charge sharing phenomenon is installed when
the sampling phase is started (A/D switch closed).
Voltage Transient on CS
VCS
VA
VA2
ΔV < 0.5 LSB
1
2
τ1 < (RSW + RAD) CS 2048 • C S
3.14.2
ADC conversion characteristics
Table 33.
ADC conversion characteristics
Symbol
C
Parameter
Typ
Max
—
VSS_HV_ADV0
− 0.3
—
VDD_HV_ADV0
+ 0.3
V
—
VSS_HV_ADV1
− 0.3
—
VDD_HV_ADV1
+ 0.3
V
ADC clock frequency
(depends on ADC
SR — configuration)
(The duty cycle depends on
AD_clk(5) frequency)
—
3(6)
—
60
MHz
SR — Sampling frequency
—
—
—
1.53
MHz
fADC = 20 MHz,
INPSAMP = 3
125
—
—
ns
fADC = 9 MHz,
INPSAMP = 255
—
—
28.2
µs
fADC = 20 MHz(9),
INPCMP = 1
0.650
—
—
µs
ADC0 and shared ADC0/1
analog input voltage(2), (3)
VINAN1 SR
(4)
fs
tADC_S
tADC_C
Unit
Min
VINAN0 SR
fCK
Value
Conditions(1)
ADC1 analog input voltage(2),
— D Sample time(7)
— P Conversion time(8)
Doc ID 14723 Rev 9
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Electrical characteristics
Table 33.
SPC560P44Lx, SPC560P50Lx
ADC conversion characteristics (continued)
Symbol
C
Parameter
ADC power-up delay (time
needed for ADC to settle
tADC_PU SR —
exiting from software power
down; PWDN bit = 0)
ADC input sampling
capacitance
Value
Conditions(1)
Unit
Min
Typ
Max
—
—
—
1.5
µs
—
—
—
2.5
pF
CS(10)
— D
CP1(10)
— D ADC input pin capacitance 1
—
—
—
3
pF
CP2(10)
— D ADC input pin capacitance 2
—
—
—
1
pF
—
—
0.6
kΩ
—
—
3
kΩ
—
—
—
2
kΩ
–5
—
5
mA
VDD_HV_ADC =
5
V ± 10%
Internal
resistance
of
analog
RSW1(10) — D
source
VDD_HV_ADC =
3.3 V ± 10%
RAD(10) — D
Internal resistance of analog
source
IINJ
— T Input current injection
Current injection
on one ADC input,
different from the
converted one.
Remains within
TUE spec.
INL
CC P Integral non-linearity
No overload
–1.5
—
1.5
LSB
DNL
CC P Differential non-linearity
No overload
–1.0
—
1.0
LSB
OSE
GE
CC T Offset error
—
—
±1
—
LSB
CC T Gain error
—
—
±1
—
LSB
TUE
CC P
Total unadjusted error without
current injection
—
–2.5
—
2.5
LSB
TUE
CC T
Total unadjusted error with
current injection
—
–3
—
3
LSB
1. VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 °C to TA MAX, unless otherwise specified and analog input voltage from
VSS_HV_ADCx to VDD_HV_ADCx.
2. VAINx may exceed VSS_HV_AD and VDD_HV_AD limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
3. Not allowed to refer this voltage to VDD_HV_ADV1, VSS_HV_ADV1
4. Not allowed to refer this voltage to VDD_HV_ADV0, VSS_HV_ADV0
5. AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
6. When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost.
7. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the
sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample
clock tADC_S depend on programming.
8. This parameter includes the sample time tADC_S.
9. 20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.
10. See Figure 16.
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Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Electrical characteristics
3.15
Flash memory electrical characteristics
Table 34.
Program and erase specifications
Value
Symbol
C
Tdwprogram
TBKPRG
Parameter
Min
Typical(1)
Initial
max(2)
Max(3)
Unit
P
Double Word (64 bits) Program Time(4)
—
22
50
500
µs
P
Bank Program (512 KB)(4)(5)
—
1.45
1.65
33
s
—
0.18
0.21
4.10
s
KB)(4)(5)
P
Bank Program (64
T16kpperase
P
16 KB Block Pre-program and Erase Time
—
300
500
5000
ms
T32kpperase
P
32 KB Block Pre-program and Erase Time
—
400
600
5000
ms
T128kpperase
P
128 KB Block Pre-program and Erase
Time
—
800
1300
7500
ms
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
5. Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will require
more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).
Table 35.
Flash memory module life
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
P/E
Number of program/erase cycles per block
C for 16 KB blocks over the operating
temperature range (TJ)
—
100000
—
cycles
P/E
Number of program/erase cycles per block
C for 32 KB blocks over the operating
temperature range (TJ)
—
10000
100000
cycles
P/E
Number of program/erase cycles per block
C for 128 KB blocks over the operating
temperature range (TJ)
—
1000
100000
cycles
Blocks with 0–1000 P/E
cycles
20
—
years
Blocks with 10000 P/E
cycles
10
—
years
Blocks with 100000 P/E
cycles
5
—
years
Retention C
Minimum data retention at 85 °C average
ambient temperature(1)
1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature
range.
Doc ID 14723 Rev 9
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Electrical characteristics
Table 36.
SPC560P44Lx, SPC560P50Lx
Flash memory read access timing
Symbol
C
fmax
C
Parameter
Maximum working frequency at given number of
wait states in worst conditions
Conditions(1)
Max value
2 wait states
66
0 wait states
18
Unit
MHz
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
3.16
AC specifications
3.16.1
Pad AC specifications
Table 37.
Output pin transition times
Symbol
C
Value
Conditions(1)
Parameter
Unit
Min Typ Max
CL = 25 pF
D
ttr
ttr
CC
CC
—
50
—
—
100
CL = 50 pF
D Output transition time output pin(2)
D SLOW configuration
CL = 100 pF
—
—
125
CL = 25 pF
—
—
40
T
CL = 50 pF
—
—
50
D
CL = 100 pF
—
—
75
D
CL = 25 pF
—
—
10
T
CL = 50 pF
—
—
20
D Output transition time output pin(2)
D MEDIUM configuration
CL = 100 pF
—
—
40
—
—
12
T
CL = 50 pF
—
—
25
D
CL = 100 pF
—
—
40
—
—
4
—
—
6
—
—
12
—
—
4
—
—
7
—
—
12
—
—
4
—
—
5
CL = 25 pF
CL = 50 pF
CC D
Output transition time output pin(2)
FAST configuration
CL = 100 pF
CL = 25 pF
CL = 50 pF
CL = 100 pF
tSYM(3) CC T
ns
VDD = 3.3 V ± 10%,
PAD3V5V = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
ns
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
ns
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
Symmetric transition time, same drive VDD = 5.0 V ± 10%, PAD3V5V = 0
strength between N and P transistor V = 3.3 V ± 10%, PAD3V5V = 1
DD
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
2. CL includes device and package capacitances (CPKG < 5 pF).
3. Transition timing of both positive and negative slopes will differ maximum 50%
86/112
—
T
CL = 25 pF
ttr
VDD = 5.0 V ± 10%,
PAD3V5V = 0
Doc ID 14723 Rev 9
ns
SPC560P44Lx, SPC560P50Lx
Electrical characteristics
VDD_HV_IOx/2
Pad
Data Input
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
VOH
VOL
Pad
Output
Figure 19. Pad output delay
3.17
AC timing characteristics
3.17.1
RESET pin characteristics
The SPC560P44Lx, SPC560P50Lx implements a dedicated bidirectional RESET pin.
VDD
VDDMIN
VRESET
VIH
VIL
device reset forced by VRESET
device start-up phase
TPOR
Figure 20. Start-up reset requirements
Doc ID 14723 Rev 9
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
Figure 21. Noise filtering on reset signal
Table 38.
Symbol
RESET electrical characteristics
C
Parameter
Value
Conditions(1)
Unit
Min
Typ
Max
VIH
SR P
Input High Level CMOS
(Schmitt Trigger)
—
0.65VDD
—
VDD+0.4
V
VIL
SR P
Input low Level CMOS
(Schmitt Trigger)
—
–0.4
—
0.35VDD
V
VHYS
CC C
Input hysteresis CMOS
(Schmitt Trigger)
—
0.1VDD
—
—
V
Push Pull, IOL = 2mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
Push Pull, IOL = 1mA,
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
—
—
0.1VDD
Push Pull, IOL = 1mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
VOL
88/112
CC P Output low level
Doc ID 14723 Rev 9
V
SPC560P44Lx, SPC560P50Lx
Table 38.
Symbol
Electrical characteristics
RESET electrical characteristics (continued)
C
Value
Conditions(1)
Parameter
Unit
Min
Typ
Max
CL = 25pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
10
CL = 50pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
20
—
—
40
CL = 100pF,
Output transition time V = 5.0 V ± 10%, PAD3V5V = 0
DD
CC D output pin(3)
MEDIUM configuration CL = 25pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
ttr
ns
—
—
12
CL = 50pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
25
CL = 100pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
40
WFRST SR P
RESET input filtered
pulse
—
—
—
40
ns
WNFRST SR P
RESET input not
filtered pulse
—
500
—
—
ns
—
—
1
ms
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
—
150
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
—
150
10
—
250
Maximum delay before
internal reset is
Monotonic VDD_HV supply ramp
CC D released after all
VDD_HV reach nominal
supply
tPOR
Weak pull-up current
|IWPU| CC P
absolute value
VDD = 5.0 V ± 10%, PAD3V5V =
1(4)
µA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
2. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of device
reference manual).
3. CL includes device and package capacitance (CPKG < 5 pF).
4. The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
3.17.2
IEEE 1149.1 interface timing
Table 39.
JTAG pin AC electrical characteristics
Value
No.
Symbol
C
Parameter
Conditions
Unit
Min Max
1
tJCYC
CC
D TCK cycle time
—
100
—
ns
2
tJDC
CC
D TCK clock pulse width (measured at VDD_HV_IOx/2)
—
40
60
ns
3
tTCKRISE
CC
D TCK rise and fall times (40% – 70%)
—
—
3
ns
4
tTMSS, tTDIS
CC
D TMS, TDI data setup time
—
5
—
ns
Doc ID 14723 Rev 9
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Electrical characteristics
Table 39.
SPC560P44Lx, SPC560P50Lx
JTAG pin AC electrical characteristics (continued)
Value
No.
Symbol
C
Parameter
Conditions
Unit
Min Max
5
tTMSH, tTDIH
CC
D TMS, TDI data hold time
—
25
—
ns
6
tTDOV
CC
D TCK low to TDO data valid
—
—
40
ns
7
tTDOI
CC
D TCK low to TDO data invalid
—
0
—
ns
8
tTDOHZ
CC
D TCK low to TDO high impedance
—
40
—
ns
11
tBSDV
CC
D TCK falling edge to output valid
—
—
50
ns
12
tBSDVZ
CC
D
TCK falling edge to output valid out of high
impedance
—
—
50
ns
13
tBSDHZ
CC
D TCK falling edge to output high impedance
—
—
50
ns
14
tBSDST
CC
D Boundary scan input valid to TCK rising edge
—
50
—
ns
15
tBSDHT
CC
D TCK rising edge to boundary scan input invalid
—
50
—
ns
TCK
2
3
2
1
Figure 22.
90/112
3
JTAG test clock input timing
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Electrical characteristics
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 23. JTAG test access port timing
Doc ID 14723 Rev 9
91/112
Electrical characteristics
SPC560P44Lx, SPC560P50Lx
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 24. JTAG boundary scan timing
3.17.3
Nexus timing
Table 40.
Nexus debug port timing(1)
Value
No.
Symbol
C
Parameter
Unit
1
tMCYC
CC
D
MCKO cycle time
2
tMDOV
CC
D
MCKO low to MDO data valid(2)
3
tMSEOV
CC
D
Typ
Max
32
—
—
ns
—
—
6
ns
MCKO low to MSEO data
valid(2)
—
—
6
ns
valid(2)
—
—
6
ns
64(3)
—
—
ns
4
tEVTOV
CC
D
MCKO low to EVTO data
5
tTCYC
CC
D
TCK cycle time
92/112
Min
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Table 40.
Electrical characteristics
Nexus debug port timing(1) (continued)
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
tNTDIS
CC
D
TDI data setup time
6
—
—
ns
tNTMSS
CC
D
TMS data setup time
6
—
—
ns
tNTDIH
CC
D
TDI data hold time
10
—
—
ns
tNTMSH
CC
D
TMS data hold time
10
—
—
ns
8
tTDOV
CC
D
TCK low to TDO data valid
—
—
35
ns
9
tTDOI
CC
D
TCK low to TDO data invalid
6
—
—
ns
6
7
1. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal.
2. MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
3. Lower frequency is required to be fully compliant to standard.
1
MCKO
2
3
4
MDO
MSEO
EVTO
Output Data Valid
Figure 25. Nexus output timing
TCK
EVTI
EVTO
5
Figure 26. Nexus event trigger and test clock timings
Doc ID 14723 Rev 9
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
TCK
6
7
TMS, TDI
9
8
TDO
Figure 27. Nexus TDI, TMS, TDO timing
3.17.4
External interrupt timing (IRQ pin)
Table 41.
External interrupt timing(1)
Value
No.
Symbol
C
Parameter
Conditions
Unit
Min
Max
—
tCYC
—
tCYC
—
tCYC
1
tIPWL
CC
D IRQ pulse width low
—
4
2
tIPWH
CC
D IRQ pulse width high
—
4
3
tICYC
CC
D IRQ edge to edge
time(2)
—
4+N
(3)
1. IRQ timing specified at fSYS = 64 MHz and VDD_HV_IOx = 3.0 V to 5.5 V, TA = TL to TH, and CL = 200 pF with
SRC = 0b00.
2. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
3. N = ISR time to clear the flag
94/112
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Electrical characteristics
IRQ
1
2
3
Figure 28. External interrupt timing
3.17.5
DSPI timing
Table 42.
DSPI timing(1)
Value
No.
1
Symbol
C
Parameter
Conditions
Unit
Min
Max
Master (MTFE = 0)
60
—
Slave (MTFE = 0)
60
—
tSCK
CC D DSPI cycle time
ns
2
tCSC
CC D CS to SCK delay
—
16
—
ns
3
tASC
CC D After SCK delay
—
26
—
ns
4
tSDC
CC D SCK duty cycle
—
5
tA
6
tDIS
0.4 * tSCK 0.6 * tSCK
ns
CC D Slave access time
SS active to SOUT valid
—
30
ns
CC D Slave SOUT disable time
SS inactive to SOUT high
impedance or invalid
—
16
ns
7
tPCSC CC D PCSx to PCSS time
—
13
—
ns
8
tPASC CC D PCSS to PCSx time
—
13
—
ns
Master (MTFE = 0)
35
—
Slave
4
—
Master (MTFE = 1, CPHA = 0)
35
—
Master (MTFE = 1, CPHA = 1)
35
—
Master (MTFE = 0)
–5
—
Slave
4
—
Master (MTFE = 1, CPHA = 0)
11
—
Master (MTFE = 1, CPHA = 1)
–5
—
9
10
tSUI
tHI
CC D Data setup time for inputs
ns
CC D Data hold time for inputs
ns
Doc ID 14723 Rev 9
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Electrical characteristics
Table 42.
SPC560P44Lx, SPC560P50Lx
DSPI timing(1) (continued)
Value
No.
11
12
Symbol
tSUO
tHO
C
Parameter
Conditions
Unit
Min
Max
Master (MTFE = 0)
—
12
Slave
—
36
Master (MTFE = 1, CPHA = 0)
—
12
Master (MTFE = 1, CPHA = 1)
—
12
Master (MTFE = 0)
–2
—
Slave
6
—
Master (MTFE = 1, CPHA = 0)
6
—
Master (MTFE = 1, CPHA = 1)
–2
—
CC D Data valid (after SCK edge)
ns
CC D Data hold time for outputs
ns
1. All timing is provided with 50 pF capacitance on output, 1 ns transition time on input signal.
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
SIN
First Data
Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Note: Numbers shown reference Table 42.
Figure 29. DSPI classic SPI timing – Master, CPHA = 0
96/112
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SPC560P44Lx, SPC560P50Lx
Electrical characteristics
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
First Data
SIN
Last Data
12
SOUT
First Data
11
Data
Last Data
Note: Numbers shown reference Table 42.
Figure 30. DSPI classic SPI timing – Master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
SOUT
First Data
9
SIN
12
11
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 42.
Figure 31. DSPI classic SPI timing – Slave, CPHA = 0
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
10
First Data
Note: Numbers shown reference Table 42.
Figure 32. DSPI classic SPI timing – Slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
First Data
10
12
SOUT
First Data
Last Data
Data
11
Data
Last Data
Note: Numbers shown reference Table 42.
Figure 33. DSPI modified transfer format timing – Master, CPHA = 0
98/112
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Electrical characteristics
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
First Data
Last Data
Data
12
First Data
SOUT
11
Last Data
Data
Note: Numbers shown reference Table 42.
Figure 34. DSPI modified transfer format timing – Master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
SOUT
First Data
Data
First Data
6
Last Data
10
9
SIN
12
11
5
Data
Last Data
Note: Numbers shown reference Table 42.
Figure 35. DSPI modified transfer format timing – Slave, CPHA = 0
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Electrical characteristics
SPC560P44Lx, SPC560P50Lx
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
First Data
SOUT
9
Last Data
Data
Last Data
10
First Data
SIN
Data
Note: Numbers shown reference Table 42.
Figure 36. DSPI modified transfer format timing – Slave, CPHA = 1
8
7
PCSS
PCSx
Note: Numbers shown reference Table 42.
Figure 37. DSPI PCS strobe (PCSS) timing
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Package characteristics
4
Package characteristics
4.1
ECOPACK®
IIn order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.2
Package mechanical data
4.2.1
LQFP144 mechanical outline drawing
L
Seating plane
C
A
A2 A1
c
b
0.25 mm
gage plane
ccc
C
k
D
D1
A1
D3
L1
108
73
72
109
E3 E1
144
Pin 1
identification
L
E
37
1
36
e
ME_1A
Figure 38. LQFP144 package mechanical drawing
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Package characteristics
Table 43.
SPC560P44Lx, SPC560P50Lx
LQFP144 mechanical data
Dimensions
Symbol
inches(1)
mm
Min
Typ
Max
Min
Typ
Max
A
—
—
1.600
—
—
0.0630
A1
0.050
—
0.150
0.0020
—
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
—
0.200
0.0035
—
0.0079
D
21.800
22.000
22.200
0.8583
0.8661
0.8740
D1
19.800
20.000
20.200
0.7795
0.7874
0.7953
D3
—
17.500
—
—
0.6890
—
E
21.800
22.000
22.200
0.8583
0.8661
0.8740
E1
19.800
20.000
20.200
0.7795
0.7874
0.7953
E3
—
17.500
—
—
0.6890
—
e
—
0.500
—
—
0.0197
—
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
—
1.000
—
—
0.0394
—
k
0.0°
3.5°
7.0°
3.5°
0.0°
7.0°
ccc(2)
0.080
0.0031
1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.
2. Tolerance
102/112
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4.2.2
Package characteristics
LQFP100 mechanical outline drawing
0.25 mm
0.10 inch
GAGE PLANE
k
D
L
D1
L1
D3
51
75
C
76
50
b
E3 E1 E
100
Pin 1
identification
26
1
25
ccc
C
e
A1
A2
A
SEATING PLANE
C
1L_ME
Figure 39. LQFP100 package mechanical drawing
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Package characteristics
Table 44.
SPC560P44Lx, SPC560P50Lx
LQFP100 package mechanical data
Dimensions
Symbol
inches(1)
mm
Min
Typ
Max
Min
Typ
Max
A
—
—
1.600
—
—
0.0630
A1
0.050
—
0.150
0.0020
—
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
—
0.200
0.0035
—
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
—
12.000
—
—
0.4724
—
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
—
12.000
—
—
0.4724
—
e
—
0.500
—
—
0.0197
—
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
—
1.000
—
—
0.0394
—
k
0.0°
3.5°
7.0°
0.0°
3.5°
7.0°
ccc(2)
0.08
0.0031
1. Values in inches are converted from millimeters (mm) and rounded to four decimal digits.
2. Tolerance
104/112
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5
Ordering information
Ordering information
Example code:
Product identifier Core Family Memory
SPC56
0
P
50
Package Temperature Custom vers. Conditioning
L5
C
EFA
Y
Y = Tray
R = Tape and Reel
X = Tape and Reel 90°
A = 64 MHz, 5 V
B = 64 MHz, 3.3 V
C = 40 MHz, 5 V
D = 40 MHz, 3.3 V
F = Full featured
A = Airbag
E = Data flash memory
B = –40 to 105 °C
C = –40 to 125 °C
L3 = LQFP100
L5 = LQFP144
50 = 512 KB
44 = 384 KB
P = SPC560Px family
0 = e200z0
SPC56 = Power Architecture in 90 nm
Figure 40. Commercial product code structure(a)
a. Not all configurations are available on the market. Please contact your ST sales representative to get the list of
orderable commercial part number.
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Abbreviations
SPC560P44Lx, SPC560P50Lx
Appendix A
Abbreviations
Table 45 lists abbreviations used in this document.
Table 45.
Abbreviations
Abbreviation
CMOS
Complementary metal–oxide–semiconductor
CPHA
Clock phase
CPOL
Clock polarity
CS
Peripheral chip select
DUT
Device under test
ECC
Error code correction
EVTO
Event out
GPIO
General purpose input/output
MC
Modulus counter
MCKO
Message clock out
MCU
Microcontroller unit
MDO
Message data out
MSEO
Message start/end out
MTFE
Modified timing format enable
NPN
NVUSRO
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Meaning
Negative-positive-negative
Non-volatile user options register
PTF
Post trimming frequency
PWM
Pulse width modulation
RBW
Resolution bandwidth
SCK
Serial communications clock
SOUT
Serial data out
TCK
Test clock input
TDI
Test data input
TDO
Test data output
TMS
Test mode select
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6
Revision history
Revision history
Table 46 summarizes revisions to this document.
Table 46.
Revision history
Date
Revision
28-Aug-2008
1
Changes
Initial release
Table 7:
TDO and TDI pins (Port pins B[4:5] are single function pins.
Table 12, Table 13:
Thermal characteristics added.
Table 11, Table 12:
EMI testing specifications split into separate tables for Normal mode and Airbag mode;
data to be added in a later revision.
25-Nov-2008
2
Table 16, Table 17, Table 19, Table 20:
Supply current specifications split into separate tables for Normal mode and Airbag
mode; data to be added in a later revision.
Table 23:
●
Values for IOL and IOH (in Conditions column) changed.
●
Max values for VOH_S, VOH_M, VOH_F and VOH_SYM deleted.
●
VILR max value changed.
●
IPUR min and max values changed.
Table 27:
Sensitivity value changed.
Table 30:
Most values in table changed.
05-Mar-2009
3
●
Description of system requirements, controller characteristics and how controller
characteristics are guaranteed updated.
●
Electrical parameters updated.
●
EMI characteristics are now in one table; values have been updated.
●
ESD characteristics are now in one table.
●
Electrical parameters are identified as either system requirements or controller
characteristics. Method used to guarantee each controller characteristic is noted in
table.
●
AC Timings: 1149.1 (JTAG) Timing, Nexus Timing, External Interrupt Timing, and
DSPI Timing sections deleted
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Revision history
Table 46.
Date
07-Jul-2009
108/112
SPC560P44Lx, SPC560P50Lx
Revision history (continued)
Revision
Changes
4
Through all document:
– Replaced all “RESET_B” occurrences with “RESET” through all document.
– AC Timings: 1149.1 (JTAG) Timing, Nexus Timing, External Interrupt Timing, and DSPI
Timing sections inserted again.
– Electrical parameters updated.
Section , Features:
– Specified LIN 2.1 in communications interfaces feature.
Table 2
– Added row for Data Flash.
Table 4
– Added a footnote regarding the decoupling capacitors.
Table 6
– Removed the “other function“ column.
– Rearranged the contents.
Table 14
– Updated definition of Condition column.
Table 19
– merged in an unique Table the power consumption data related to "Maximum mode"
and "Airbag mode".
Table 21
– merged in an unique Table the power consumption data related to "Maximum mode"
and "Airbag mode".
Table 29
– Updated the parameter definition of ΔRCMVAR.
– Removed the condition definition of ΔRCMVAR.
Table 29
– Added tADC_C and TUE rows.
Table 30
– Added tADC_C and TUE rows.
– Removed Rsw2.
Table 33
– Added.
Table 29
– Updated and added footnotes.
Section 3.16.1 RESET Pin Characteristics
– Replaces whole section.
Table 38
– Renamed the “Flash (KB)“ heading column in “Code Flash / Data Flash (EE) (KB)“
– Replaced the value of RAM from 32 to 36KB in the last four rows.
Doc ID 14723 Rev 9
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Table 46.
Date
27-Oct-2009
06-Apr-2010
07-Apr-2011
Revision history
Revision history (continued)
Revision
Changes
5
- Added “Full Feature“ and “Airbag“ customization.
- Removed B[4] and B[5] rows from “Pin muxing” table and inserted them on “System pins”
table.
- Updated package pinout.
- Rewrote entirely section “Power Up/dpwn Sequencing“ section.
- Renamend “VDD_LV_PLL“ and “VSS_LV_PLL“ supply pins with respectively “VDD_LV_COR3“
and “VSS_LV_COR3”.
- Added explicative figures on “Electrical characteristics” section.
- Updated “Thermal characteristics“ for 100-pin.
- Proposed two different configuration of “voltage regulator. - Inserted Power Up/Down
sequence.
- Added explicative figures on “DC Electrical characteristics”.
- Added “I/O pad current specification” section.
- Renamed the “Airbag mode” with “Typical mode“and updated the values on “supply
current” tables.
- Added more order code.
6
Inserted label of Y-axis in the “Independent ADC supply“ figure.
“Recommended Operating Conditions” tables:
Moved the TJ row to “Absolute Maximum Ratings“ table.
Rewrite note 1 and 3
Inverted Min a Typ value of CDEC2 on ”Voltage Regulator Electrical Characteristics” table.
Removed an useless duplicate of “Voltage Regulator Electrical Characteristics“ table.
Inserted the name of CS into “Input Equivalent Circuit“ figure.
Removed leakage Ivpp from datasheet.
Updated “Supply Current” tables.
Added note on “Output pin transition times“ table.
Updated ”Temperature Sensor Electrical Characteristics” table.
Updated “16 MHz RC Oscillator Electrical Characteristics” table.
Removed the note about the condition from “Flash read access timing“ table.
Removed the notes that assert the values need to be confirmed before validation.
7
Formatting and editorial changes throughout
Removed all content referencing Junction Temperature Sensor
Cover page Features:
– CPU core—specified 64 MHz frequency
– updated memory features
– eTimer units: changed “up/down capabilities” to “up/down count capabilities”
– ADC—changed “2 × 13 input channels” to “2 × 11 input channels, + 4 shared channels”
– replaced “On-chip CAN/UART/FlexRay bootstrap loader” with “On-chip CAN/UART
bootstrap loader”
Section 1: Introduction: changed title (was: Overview); reorganized contents
SPC560P44Lx, SPC560P50Lx device comparison:
– ADC feature: changed “16 channels” to “15-channel”; added footnote to to indicate that
four channels are shared between the two ADCs
– removed SPC560P40 column
– changed “dual channel” to “selectable single or dual channel support” in FlexRay
footnote
– updated “eTimer” feature
– updated footnote relative to “Digital power supply” feature
Doc ID 14723 Rev 9
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Revision history
Table 46.
Date
07-Apr-2011
110/112
SPC560P44Lx, SPC560P50Lx
Revision history (continued)
Revision
Changes
7
(cont’d)
SPC560P44Lx, SPC560P50Lx device configuration differences: Removed “temperature”
row (temperature information is provided in Order codes)
Updated SPC560P44Lx, SPC560P50Lx block diagram
Added SPC560P44Lx, SPC560P50Lx series block summary
Added Section 1.5 Feature details
Section 2.1, Package pinouts: removed alternate functions from pinout diagrams
Supply pins: updated descriptions of power supply pins (1.2 V)
System pins: updated table
Pin muxing: added rows “B[4]” and “B[5]
Section 3.3, Absolute maximum ratings: added voltage specifications to titles of Figure 5
and Figure 6; in Table 9, changed row “VSS_HV / Digital Ground” to “VSS / Device
Ground”; updated symbols
Section 3.4, Recommended operating conditions: added voltage specifications to titles of
Figure 7 and Figure 8
Recommended operating conditions (5.0 V), and Recommended operating conditions
(3.3 V): changed row “VSS_HV / Digital Ground” to “VSS / Device Ground”; updated
symbols
Updated Section 3.5.1, Package thermal characteristics
Updated Section 3.6, Electromagnetic interference (EMI) characteristics
Section 3.8.1, Voltage regulator electrical characteristics: amended titles of Table 16 and
Table 19
Voltage regulator electrical characteristics (configuration without resistor on base) and
Voltage regulator electrical characteristics (configuration with resistor on base):
updated symbol and values for VDD_LV_REGCOR
Low voltage monitor electrical characteristics: Updated VMLVDDOK_H max value—was
1.15 V; is 1.145 V
Section 3.10, DC electrical characteristics: reorganized contents
Updated Section 3.10.1, NVUSRO register (includes adding
Section NVUSRO[OSCILLATOR_MARGIN] field description)
Supply current (5.0 V, NVUSRO[PAD3V5V] = 0): updated symbols
Corrected parameter descriptions in DC electrical characteristics (3.3 V,
NVUSRO[PAD3V5V] = 1):
– VOL_F—was “Fast, high level output voltage”; is “Fast, low level output voltage”
– VOL_SYM—was “Symmetric, high level output voltage”; is “Symmetric, low level output
voltage”
Supply current (3.3 V, NVUSRO[PAD3V5V] = 1): updated symbols
Main oscillator output electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0): replaced
instances of EXTAL with XTAL
Main oscillator output electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1): replaced
instances of EXTAL with XTAL
FMPLL electrical characteristics: replaced “PLLMRFM” with “FMPLL” in table title;
updated conditions; removed fsys row; updated fFMPLLOUT min value
ADC conversion characteristics: updated symbols; added row tADC_PU
Flash memory read access timing: added footnote to “Conditions” column
Section 3.16.1, Pad AC specifications: added Pad output delay diagram
In the range of figures “DSPI Classic SPI Timing — Master, CPHA = 0” to “DSPI PCS
Strobe (PCSS) Timing”: added note
Updated Order codes
Updated “Commercial product code structure” figure
Table 45: Added abbreviations “DUT”, “NPN”, and “RBW”
Doc ID 14723 Rev 9
SPC560P44Lx, SPC560P50Lx
Table 46.
Date
Revision history
Revision history (continued)
Revision
18-Jul-2012
8
18-Sep-2013
9
Changes
Updated Table 1 (Device summary)
Section 1.5.4, Flash memory: Changed “Data flash memory: 32-bit ECC” to “Data flash
memory: 64-bit ECC”
Figure 40 (Commercial product code structure), replaced "C = 60 MHz, 5 V" and "D = 60
MHz, 3.3 V" with respectively "C = 40 MHz, 5 V" and "D = 40 MHz, 3.3 V"
Table 9 (Absolute maximum ratings), updated TVDD parameter, the minimum value to
3.0 V/s and the maximum value to 0.5 V/µs
Table 7 (Pin muxing), changed the description in the column "I/O direction" from "I/O" to
"O" for the following port pins:
A[10] with function B[0]
A[11] with function A[0]
A[11] with function A[2]
A[12] with function A[2]
A[12] with function B[2]
A[13] with function B[2]
C[7] with function A[1]
C[10] with function A[3]
C[15] with function A[1]
D[0] with function B[1]
D[10] with function A[0]
D[11] with function B[0]
D[13] with function A[1]
D[14] with function B[1]
Updated Section 3.8.1, Voltage regulator electrical characteristics
Added Table 27 (I/O consumption)
Section 3.10, DC electrical characteristics:
deleted references to “oscillator margin”
deleted subsection “NVUSRO[OSCILLATOR_MARGIN] field description”
Table 21 (DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)), added IPU row
for RESET pin
Table 23 (DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)), added IPU row
for RESET pin
Table 33 (ADC conversion characteristics), added VINAN entry
Removed “Order codes” table
Figure 40 (Commercial product code structure):
added a footnote
updated “E = Data flash memory”
Updated Disclaimer
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SPC560P44Lx, SPC560P50Lx
Please Read Carefully:
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