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SPC564A80L7CFBR

SPC564A80L7CFBR

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    LQFP176

  • 描述:

    IC MCU 32BIT 4MB FLASH 176LQFP

  • 数据手册
  • 价格&库存
SPC564A80L7CFBR 数据手册
SPC564A74B4, SPC564A74L7, SPC564A80B4, SPC564A80L7 32-bit MCU family built on the embedded Power Architecture® Features ■ ■ ■ ■ 150 MHz e200z4 Power Architecture® core – Variable length instruction encoding (VLE) – Superscalar architecture with 2 execution units – Up to 2 integer or floating point instructions per cycle – Up to 4 multiply and accumulate operations per cycle LBGA208 PBGA324 LQFP176 – 3  FlexCAN with 64 messages each – 1  FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC Memory organization – 4 MB on-chip flash memory with ECC and Read While Write (RWW) – 192 KB on-chip RAM with standby functionality (32 KB) and ECC – 8 KB instruction cache (with line locking), configurable as 2- or 4-way – 14 + 3 KB eTPU code and data RAM – 5  4 crossbar switch (XBAR) – 24-entry MMU – External Bus Interface (EBI) with slave and master port Fail Safe Protection – 16-entry Memory Protection Unit (MPU) – CRC unit with 3 sub-modules – Junction temperature sensor Interrupts – Configurable interrupt controller (with NMI) – 64-channel DMA ■ Serial channels – 3  eSCI – 3  DSPI (2 of which support downstream Micro Second Channel [MSC]) Table 1. Device summary ■ 1  eMIOS ■ 1  eTPU2 (second generation eTPU) ■ 2 enhanced queued analog-to-digital converters (eQADCs) ■ On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM) ■ Nexus: Class 3+ for core; Class 1 for the eTPU ■ JTAG (5-pin) ■ Development Trigger Semaphore (DTS) ■ Clock generation – On-chip 4–40 MHz main oscillator – On-chip FMPLL (frequency-modulated phase-locked loop) ■ Up to 120 general purpose I/O lines ■ Power reduction mode: slow, stop and standby modes ■ Flexible supply scheme – 5 V single supply with external ballast – Multiple external supply: 5 V, 3.3 V and 1.2 V ■ Designed for LQFP176, LBGA208, PBGA324 and Known Good Die (KGD) Part number Memory Flash size Package LQFP176 Package: LBGA208 Package: PBGA324 KGD 4MB SPC564A80L7 - SPC564A80B4 - 3MB SPC564A74L7 - SPC564A74B4 - September 2013 Doc ID 15399 Rev 9 1/157 www.st.com 1 Contents SPC564A74L7, SPC564A80B4, SPC564A80L7 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Document Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 SPC564A80 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.6 2/157 1.5.1 e200z4 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.2 Crossbar Switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.3 eDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.5 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.6 FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.7 SIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.8 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.9 BAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.10 eMIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.11 eTPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.12 Reaction module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.13 eQADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.14 DSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.15 eSCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.5.16 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.5.17 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.18 System timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.19 Software watchdog timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.20 Cyclic redundancy check (CRC) module . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.21 Error correction status module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.22 External bus interface (EBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.23 Calibration EBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.24 Power management controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.25 Nexus port controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.26 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.27 Development Trigger Semaphore (DTS) . . . . . . . . . . . . . . . . . . . . . . . . 29 SPC564A80 series architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 2 3 Contents 1.6.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.6.2 Block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Pinout and signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.1 LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2 LBGA208 ballmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3 PBGA324 ballmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4 Signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.5 Signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.3.1 General notes for specifications at maximum junction temperature . . . 85 3.4 EMI (electromagnetic interference) characteristics . . . . . . . . . . . . . . . . . 88 3.5 Electrostatic discharge (ESD) characteristics . . . . . . . . . . . . . . . . . . . . . 88 3.6 Power management control (PMC) and power on reset (POR) electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.6.1 Regulator Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.6.2 Recommended power transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.7 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.8 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.9 I/O pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.9.1 I/O pad VRC33 current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.9.2 LVDS pad specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.10 Oscillator and PLLMRFM electrical characteristics . . . . . . . . . . . . . . . . 104 3.11 Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . 106 3.12 eQADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.13 Configuring SRAM wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.14 Platform flash controller electrical characteristics . . . . . . . . . . . . . . . . . 109 3.15 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 3.16.1 3.17 Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Doc ID 15399 Rev 9 3/157 Contents SPC564A74L7, SPC564A80B4, SPC564A80L7 3.17.1 Reset and configuration pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3.17.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.17.4 External Bus Interface (EBI) and calibration bus interface timing . . . . 122 3.17.5 External interrupt timing (IRQ pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 3.17.6 eTPU timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 3.17.7 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 3.17.8 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 3.17.9 eQADC SSI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.17.10 FlexCAN system clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.1 ECOPACK‚ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.2.1 LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.2.2 BGA208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 4.2.3 PBGA324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 4/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPC564A80, SPC563M64 and SPC564A70 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SPC564A80 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SPC564A80 signal properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Power/ground segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Thermal characteristics for 176-pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Thermal characteristics for 208-pin LBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Thermal characteristics for 324-pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 EMI Testing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 PMC Operating Conditions and External Regulators Supply Voltage . . . . . . . . . . . . . . . . 89 PMC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SPC564A80 External network specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Recommended operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Power sequence pin states (fast pads). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Power sequence pin states (medium, slow, and multi-voltage pads) . . . . . . . . . . . . . . . . . 94 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I/O pad average IDDE specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 I/O pad VRC33 average IDDE specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 VRC33 pad average DC current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 DSPI LVDS pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 PLLMRFM electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 eQADC conversion specifications (operating) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 eQADC single ended conversion specifications (operating). . . . . . . . . . . . . . . . . . . . . . . 107 eQADC differential ended conversion specifications (operating) . . . . . . . . . . . . . . . . . . . 107 Cutoff frequency for additional SRAM wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 APC, RWSC, WWSC settings vs. frequency of operation, . . . . . . . . . . . . . . . . . . . . . . . . 109 Flash program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Pad AC specifications (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Pad AC specifications (VDDE = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Reset and Configuration Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Nexus debug port operating frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 External Bus Interface maximum operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Calibration bus interface maximum operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . 122 External bus interface (EBI) and calibration bus operation timing . . . . . . . . . . . . . . . . . 122 External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 eTPU timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 DSPI channel frequency support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 DSPI timing, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Doc ID 15399 Rev 9 5/157 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. 6/157 SPC564A74L7, SPC564A80B4, SPC564A80L7 eQADC SSI timing characteristics (pads at 3.3 V or at 5.0 V) . . . . . . . . . . . . . . . . . . . . . 135 FlexCAN engine system clock divider threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 FlexCAN engine system clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 LQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 PBGA324 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. SPC564A80 series block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 176-pin LQFP pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 208-pin LBGA package ballmap (viewed from above) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 324-pin PBGA package ballmap (northwest, viewed from above) . . . . . . . . . . . . . . . . . . . 37 324-pin PBGA package ballmap (southwest, viewed from above) . . . . . . . . . . . . . . . . . . . 38 324-pin PBGA package ballmap (northeast, viewed from above) . . . . . . . . . . . . . . . . . . . 39 324-pin PBGA package ballmap (southeast, viewed from above) . . . . . . . . . . . . . . . . . . . 40 Core voltage regulator controller external components preferred configuration . . . . . . . . . 93 Pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Reset and Configuration Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 JTAG JCOMP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 CLKOUT timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Synchronous output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Synchronous input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ALE signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 DSPI classic SPI timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 DSPI classic SPI timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 DSPI classic SPI timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 DSPI classic SPI timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 DSPI modified transfer format timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . 132 DSPI modified transfer format timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . 132 DSPI modified transfer format timing — slave, CPHA =0. . . . . . . . . . . . . . . . . . . . . . . . . 133 DSPI modified transfer format timing — slave, CPHA =1. . . . . . . . . . . . . . . . . . . . . . . . . 134 DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 eQADC SSI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 LQFP176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 PBGA324 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Doc ID 15399 Rev 9 7/157 Introduction SPC564A74L7, SPC564A80B4, SPC564A80L7 1 Introduction 1.1 Document Overview This document provides electrical specifications, pin assignments, and package diagrams for the SPC564A80 series of microcontroller units (MCUs). For functional characteristics, refer to the SPC564A80 Microcontroller Reference Manual. 1.2 Description The microcontroller’s e200z4 host processor core is built on Power Architecture technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP). The SPC564A80 has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by 192 KB on-chip SRAM and 4 MB of internal flash memory. The SPC564A80 includes an external bus interface, and also a calibration bus that is only accessible when using the calibration tools. This document describes the features of the SPC564A80 and highlights important electrical and physical characteristics of the device. 8/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 1.3 Introduction Device comparison Table 2 summarizes the SPC564A80 and compares it to the SPC563M64. Table 2. SPC564A80, SPC563M64 and SPC564A70 comparison Feature SPC564A80 SPC563M64 Process Core 90 nm e200z4 e200z3 SIMD Yes VLE Yes Cache SPC564A70 8 KB instruction Non-Maskable Interrupt (NMI) e200z4 No 8 KB instruction NMI & Critical Interrupt MMU 24 entry 16 entry 24 entry MPU 16 entry No 16 entry 54 34 44 0–150 MHz 0–80 MHz 0–150 MHz Crossbar switch Core performance Windowing software watchdog Core Nexus Yes Class 3+ Class 2+ Class 3+ SRAM 192 KB 94 KB 128 KB Flash 4 MB 1.5 MB 2 MB 4  256-bit 4  128-bit External bus 16-bit (incl 32-bit muxed) None Calibration bus 16-bit (incl 32-bit muxed) 16-bit 16-bit (incl 32-bit muxed) 64 ch. 32 ch. 64 ch. Flash fetch accelerator DMA DMA Nexus Serial None 3 eSCI_A Yes (MSC Uplink) eSCI_B Yes (MSC Uplink) eSCI_C CAN 3 Yes No Yes 3 2 3 CAN_A SPI 2 64 buf CAN_B 64 buf No 64 buf CAN_C 64 buf 32 buf 64 buf 3 2 3 Doc ID 15399 Rev 9 9/157 Introduction Table 2. SPC564A74L7, SPC564A80B4, SPC564A80L7 SPC564A80, SPC563M64 and SPC564A70 comparison (continued) Feature SPC564A80 SPC563M64 Micro Second Channel (MSC) bus downlink Yes DSPI_A No DSPI_B Yes (with LVDS) DSPI_C Yes (with LVDS) DSPI_D FlexRay Yes No Yes Yes No Yes 5 PIT channels 4 STM channels 1 Software Watchdog System timers eMIOS 24 ch. 16 ch. eTPU 14 KB Data memory 3 KB (1) 486 ch. 307 ch. 486 ch.(1) 40 ch. 34 ch. 40 ch. ADC ADC_A Yes ADC_B Yes Temp sensor Yes Variable gain amp. Yes Decimation filter 2 1 Sensor diagnostics Yes No FMPLL Yes (2) 5 V, 3.3 V 5 V, 3.3 V(3) 5 V, 3.3 V(2) Stop Mode Slow Mode Low-power modes LQFP176(4) LBGA208(4) PBGA Known Good Die (KGD) 496-pin CSP(5) 1. 199 interrupt vectors are reserved. 2. 5 V single supply only for LQFP176. 3. 5 V single supply only for LQFP144 and LQFP100. 4. Pinout compatible with STMicroelectronics’ SPC563M64 devices. 5. For ST calibration tool only. 10/157 Yes Yes VRC Packages 2 Yes CRC Supplies 24 ch. 32 ch. eTPU2 Code memory Interrupt controller SPC564A70 Doc ID 15399 Rev 9 LQFP100 LQFP144 LQFP176 LBGA208 496-pin CSP(5) LQFP176(4) LBGA208(4) PBGAKnown Good Die (KGD) 496-pin CSP(5) SPC564A74L7, SPC564A80B4, SPC564A80L7 1.4 Introduction SPC564A80 feature list ● ● ● ● ● 150 MHz e200z4 Power Architecture core – Variable length instruction encoding (VLE) – Superscalar architecture with 2 execution units – Up to 2 integer or floating point instructions per cycle – Up to 4 multiply and accumulate operations per cycle Memory organization – 4 MB on-chip flash memory with ECC and Read While Write (RWW) – 192 KB on-chip SRAM with standby functionality (32 KB) and ECC – 8 KB instruction cache (with line locking), configurable as 2- or 4-way – 14 + 3 KB eTPU code and data RAM – 5  4 crossbar switch (XBAR) – 24-entry MMU – External Bus Interface (EBI) with slave and master port Fail Safe Protection – 16-entry Memory Protection Unit (MPU) – CRC unit with 3 sub-modules – Junction temperature sensor Interrupts – Configurable interrupt controller (with NMI) – 64-channel DMA Serial channels – 3  eSCI – 3  DSPI (2 of which support downstream Micro Second Channel [MSC]) – 3  FlexCAN with 64 messages each – 1  FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC ● 1  eMIOS: 24 unified channels ● 1  eTPU2 (second generation eTPU) ● – 32 standard channels – 1  reaction module (6 channels with three outputs per channel) 2 enhanced queued analog-to-digital converters (eQADCs) – Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external multiplexers – 6 command queues – Trigger and DMA support – 688 ns minimum conversion time ● On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM) ● Nexus ● – Class 3+ for the e200z4 core – Class 1 for the eTPU JTAG (5-pin) Doc ID 15399 Rev 9 11/157 Introduction ● ● ● Development Trigger Semaphore (DTS) – Register of semaphores (32-bits) and an identification register – Used as part of a triggered data acquisition protocol – EVTO pin is used to communicate to the external tool Clock generation – On-chip 4–40 MHz main oscillator – On-chip FMPLL (frequency-modulated phase-locked loop) Up to 120 general purpose I/O lines – Individually programmable as input, output or special function – Programmable threshold (hysteresis) ● Power reduction mode: slow, stop and stand-by modes ● Flexible supply scheme ● 12/157 SPC564A74L7, SPC564A80B4, SPC564A80L7 – 5 V single supply with external ballast – Multiple external supply: 5 V, 3.3 V and 1.2 V Packages – LQFP176 – LBGA208 – PBGA324 – Known Good Die (KGD) – 496-pin CSP (calibration tool only) Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 1.5 Feature details 1.5.1 e200z4 core Introduction SPC564A80 devices have a high performance e200z448n3 core processor: 1.5.2 ● Dual issue, 32-bit Power Architecture embedded category CPU ● Variable Length Encoding Enhancements ● 8 KB instruction cache: 2- or 4- way set associative instruction cache ● Thirty-two 64-bit general purpose registers (GPRs) ● Memory management unit (MMU) with 24-entry fully-associative translation look-aside buffer (TLB) ● Harvard Architecture: Separate instruction bus and load/store bus ● Vectored interrupt support ● Non-maskable interrupt input ● Critical Interrupt input ● New ‘Wait for Interrupt’ instruction, to be used with new low power modes ● Reservation instructions for implementing read-modify-write accesses ● Signal processing extension (SPE) APU ● Single Precision Floating point (scalar and vector) ● Nexus Class 3+ debug ● Process ID manipulation for the MMU using an external tool Crossbar Switch (XBAR) The XBAR multiport crossbar switch supports simultaneous connections between five master ports and four slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. The crossbar allows three concurrent transactions to occur from the master ports to any slave port but each master must access a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following features: ● 5 master ports – CPU instruction bus – CPU data bus – eDMA – FlexRay – External Bus Interface Doc ID 15399 Rev 9 13/157 Introduction ● ● 1.5.3 SPC564A74L7, SPC564A80B4, SPC564A80L7 4 slave ports – Flash – Calibration and EBI bus – SRAM – Peripheral bridge 32-bit internal address, 64-bit internal data paths eDMA The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 64 programmable channels, with minimal intervention from the host processor. The hardware micro-architecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The eDMA module provides the following features: 1.5.4 ● All data movement via dual-address transfers: read from source, write to destination ● Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes ● Transfer control descriptor organized to support two-deep, nested transfer operations ● An inner data transfer loop defined by a “minor” byte transfer count ● An outer data transfer loop defined by a “major” iteration count ● Channel activation via one of three methods: – Explicit software initiation – Initiation via a channel-to-channel linking mechanism for continuous transfers – Peripheral-paced hardware requests (one per channel) ● Support for fixed-priority and round-robin channel arbitration ● Channel completion reported via optional interrupt requests ● One interrupt per channel, optionally asserted at completion of major iteration count ● Error termination interrupts optionally enabled ● Support for scatter/gather DMA processing ● Ability to suspend channel transfers by a higher priority channel Interrupt controller The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By 14/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Introduction providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource cannot preempt each other. The INTC provides the following features: ● 9-bit vector addresses ● Unique vector for each interrupt request source ● Hardware connection to processor or read from register ● Each interrupt source can assigned a specific priority by software ● Preemptive prioritized interrupt requests to processor ● ISR at a higher priority preempts executing ISRs or tasks at lower priorities ● Automatic pushing or popping of preempted priority to or from a LIFO ● Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources ● Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic. 1.5.5 Memory protection unit (MPU) The Memory Protection Unit (MPU) provides hardware access control for all memory references generated in a device. Using preprogrammed region descriptors, which define memory spaces and their associated access rights, the MPU concurrently monitors all system bus transactions and evaluates the appropriateness of each transfer. Memory references with sufficient access control rights are allowed to complete; references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. The MPU has these major features: ● ● Support for 16 memory region descriptors, each 128 bits in size – Specification of start and end addresses provide granularity for region sizes from 32 bytes to 4 GB – MPU is invalid at reset, thus no access restrictions are enforced – Two types of access control definitions: processor core bus master supports the traditional {read, write, execute} permissions with independent definitions for supervisor and user mode accesses; the remaining non-core bus masters (eDMA, FlexRay, and EBI1) support {read, write} attributes – Automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a coherent image of the descriptor – Alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter the access rights of a descriptor only(a) – For overlapping region descriptors, priority is given to permission granting over access denying as this approach provides more flexibility to system software Support for two XBAR slave port connections (SRAM and PBRIDGE) – For each connected XBAR slave port (SRAM and PBRIDGE), MPU hardware monitors every port access using the pre-programmed memory region descriptors Doc ID 15399 Rev 9 15/157 Introduction 1.5.6 SPC564A74L7, SPC564A80B4, SPC564A80L7 – An access protection error is detected if a memory reference does not hit in any memory region or the reference is flagged as illegal in all memory regions where it does hit. In the event of an access error, the XBAR reference is terminated with an error response and the MPU inhibits the bus cycle being sent to the targeted slave device – 64-bit error registers, one for each XBAR slave port, capture the last faulting address, attributes, and detail information FMPLL The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz crystal oscillator or external clock generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all software configurable. The PLL has the following major features: 1.5.7 ● Input clock frequency from 4 MHz to 40 MHz ● Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock ● Three modes of operation – Bypass mode with PLL off – Bypass mode with PLL running (default mode out of reset) – PLL normal mode ● Each of the three modes may be run with a crystal oscillator or an external clock reference ● Programmable frequency modulation – Modulation enabled/disabled through software – Triangle wave modulation up to 100 kHz modulation frequency – Programmable modulation depth (0% to 2% modulation depth) – Programmable modulation frequency dependent on reference frequency ● Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors lock status to report loss of lock conditions ● Clock Quality Module – Detects the quality of the crystal clock and causes interrupt request or system reset if error is detected – Detects the quality of the PLL output clock; if error detected, causes system reset or switches system clock to crystal clock and causes interrupt request ● Programmable interrupt request or system reset on loss of lock ● Self-clocked mode (SCM) operation SIU The SPC564A80 SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The a. EBI not available on all packages and is not available, as a master, for customer. 16/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Introduction GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring of internal and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z4 CPU core is via the crossbar switch. The SIU provides the following features: ● ● ● ● ● 1.5.8 System configuration – MCU reset configuration via external pins – Pad configuration control for each pad – Pad configuration control for virtual I/O via DSPI serialization System reset monitoring and generation – Power-on reset support – Reset status register provides last reset source to software – Glitch detection on reset input – Software controlled reset assertion External interrupt – Rising or falling edge event detection – Programmable digital filter for glitch rejection – Critical Interrupt request – Non-Maskable Interrupt request GPIO – Centralized control of I/O and bus pins – Virtual GPIO via DSPI serialization (requires external deserialization device) – Dedicated input and output registers for setting each GPIO and Virtual GPIO pin Internal multiplexing – Allows serial and parallel chaining of DSPIs – Allows flexible selection of eQADC trigger inputs – Allows selection of interrupt requests between external pins and DSPI Flash memory The SPC564A80 provides up to 4 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used to store instructions or data, or both. The flash module includes a Fetch Accelerator that optimizes the performance of the flash array to match the CPU architecture. The flash module interfaces the system bus to a dedicated flash memory array controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and 128- and 256-bit read data interfaces to flash memory. The module contains a prefetch controller which prefetches sequential lines of data from the flash array into the buffers. Prefetch buffer hits allow no-wait responses. The flash memory provides the following features: ● Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword reads are supported. Only aligned word and doubleword writes are supported. ● Fetch Accelerator – Architected to optimize the performance of the flash – Configurable read buffering and line prefetch support Doc ID 15399 Rev 9 17/157 Introduction 1.5.9 SPC564A74L7, SPC564A80B4, SPC564A80L7 – Four-entry 256-bit wide line read buffer – Prefetch controller ● Hardware and software configurable read and write access protections on a per-master basis ● Interface to the flash array controller pipelined with a depth of one, allowing overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs ● Configurable access timing usable in a wide range of system frequencies ● Multiple-mapping support and mapping-based block access timing (0-31 additional cycles) usable for emulation of other memory types ● Software programmable block program/erase restriction control ● Erase of selected block(s) ● Read page size of 128 bits (four words) ● ECC with single-bit correction, double-bit detection ● Program page size of 128 bits (four words) to accelerate programming ● ECC single-bit error corrections are visible to software ● Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC ● Embedded hardware program and erase algorithm ● Erase suspend, program suspend and erase-suspended program ● Shadow information stored in non-volatile shadow block ● Independent program/erase of the shadow block BAM The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by ST and is identical for all SPC564A80 MCUs. The BAM program is executed every time the MCU is powered-on or reset in normal mode. The BAM supports different modes of booting. They are: ● Booting from internal flash memory ● Serial boot loading (A program is downloaded into RAM via eSCI or the FlexCAN and then executed) ● Booting from external memory on external bus The BAM also reads the reset configuration half word (RCHW) from internal flash memory and configures the SPC564A80 hardware accordingly. The BAM provides the following features: 18/157 ● Sets up MMU to cover all resources and mapping of all physical addresses to logical addresses with minimum address translation ● Sets up MMU to allow user boot code to execute as either Power Architecture embedded category (default) or as VLE code ● Location and detection of user boot code ● Automatic switch to serial boot mode if internal flash is blank or invalid ● Supports user programmable 64-bit password protection for serial boot mode ● Supports serial bootloading via FlexCAN bus and eSCI using standard protocol ● Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing ● Supports serial bootloading of either Power Architecture code (default) or VLE code Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 1.5.10 ● Supports booting from calibration bus interface ● Supports censorship protection for internal flash memory ● Provides an option to enable the core watchdog timer ● Provides an option to disable the system watchdog timer Introduction eMIOS The eMIOS timer module provides the capability to generate or measure events in hardware. The eMIOS module features include: ● Twenty-four 24-bit wide channels ● 3 channels’ internal timebases can be shared between channels ● 1 Timebase from eTPU2 can be imported and used by the channels ● Global enable feature for all eMIOS and eTPU timebases ● Dedicated pin for each channel (not available on all package types) Each channel (0–23) supports the following functions: 1.5.11 ● General-purpose input/output (GPIO) ● Single-action input capture (SAIC) ● Single-action output compare (SAOC) ● Output pulse-width modulation buffered (OPWMB) ● Input period measurement (IPM) ● Input pulse-width measurement (IPWM) ● Double-action output compare (DAOC) ● Modulus counter buffered (MCB) ● Output pulse width and frequency modulation buffered (OPWFMB) eTPU2 The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, the eTPU2 processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler and documentation allows customers to develop their own functions on the eTPU2. SPC564A80 devices feature the second generation of the eTPU, called eTPU2. Enhancements of the eTPU2 over the standard eTPU include: ● The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input [TCRCLK]) now have an option to run at full system clock speed or system clock / 2. ● Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode. ● A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode. Doc ID 15399 Rev 9 19/157 Introduction SPC564A74L7, SPC564A80B4, SPC564A80L7 ● Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can also be requested simultaneously at the same instruction. ● Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point. ● Channel digital filters can be bypassed. The eTPU2 includes these distinctive features: ● ● ● ● 20/157 32 channels; each channel associated with one input and one output signal – Enhanced input digital filters on the input pins for improved noise immunity – Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned to more than one channel at a given time, so each signal can have any functionality. – Each channel has an event mechanism which supports single and double action functionality in various combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and equal-only comparators. – Input and output signal states visible from the host 2 independent 24-bit time bases for channel synchronization: – First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by output of second time base prescaler – Second time base counter can work as a continuous angle counter, enabling angle based applications to match angle instead of time – Both time bases can be exported to the eMIOS timer module – Both time bases visible from the host Event-triggered microengine: – Fixed-length instruction execution in two-system-clock microcycle – 14 KB of code memory (SCM) – 3 KB of parameter (data) RAM (SPRAM) – Parallel execution of data memory, ALU, channel control and flow control subinstructions in selected combinations – 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign extension and conditional execution – Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands. Resource sharing features support channel use of common channel registers, memory and microengine time: – Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined, host-configured priority – Automatic channel context switch when a “task switch” occurs, that is, one function thread ends and another begins to service a request from other channel: channelspecific registers, flags and parameter base address are automatically loaded for the next serviced channel Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 ● 1.5.12 Introduction – SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or inter-channel – Hardware implementation of four semaphores support coherent parameter sharing between both eTPU engines – Dual-parameter coherency hardware support allows atomic access to two parameters by host Test and development support features: – Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware breakpoints and watchpoints on several conditions – Software breakpoints – SCM continuous signature-check built-in self test (MISC - multiple input signature calculator), runs concurrently with eTPU2 normal operation Reaction module The reaction module provides the ability to modulate output signals to manage closed loop control without CPU assistance. It works in conjunction with the eQADC and eTPU2 to increase system performance by removing the CPU from the current control loop. The reaction module has the following features: ● Six reaction channels ● Each channel output is a bus of three signals, providing ability to control 3 inputs. ● Each channel can implement a peak and hold waveform, making it possible to implement up to six independent peak and hold control channels Target applications include solenoid control for direct injection systems and valve control in automatic transmissions 1.5.13 eQADC The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions for a wide range of applications. The eQADC provides a parallel interface to two on-chip analog to digital converters (ADC), and a single master to single slave serial interface to an off-chip external device. Both on-chip ADCs have access to all the analog channels. The eQADC prioritizes and transfers commands from six command conversion command ‘queues’ to the on-chip ADCs or to the external device. The block can also receive data from the on-chip ADCs or from an off-chip external device into the six result queues, in parallel, independently of the command queues. The six command queues are prioritized with Queue_0 having the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running conversion on either ADC and start a Queue_0 conversion. This means that Queue_0 will always have a deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs were performing when the trigger occurred. The eQADC supports software and external hardware triggers from other blocks to initiate transfers of commands from the queues to the on-chip ADCs or to the external device. It also monitors the fullness of command queues and result queues, and accordingly generates DMA or interrupt requests to control data movement between the queues and the system memory, which is external to the eQADC. The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used in a system for detecting engine knock. These features Doc ID 15399 Rev 9 21/157 Introduction SPC564A74L7, SPC564A80B4, SPC564A80L7 include differential inputs; integrated variable gain amplifiers for increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics. The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results at a high rate, passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate results to the result FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band noise; while providing a reduced sample rate output to minimize the amount DSP processing bandwidth required to fully process the digitized waveform. The eQADC provides the following features: ● Dual on-chip ADCs – 2  12-bit ADC resolution – Programmable resolution for increased conversion speed (12-bit, 10-bit, 8-bit) 12-bit conversion time: 938 ns (1 M sample/sec) 10-bit conversion time: 813 ns (1.2 M sample/second) 8-bit conversion time: 688 ns (1.4 M sample/second) Up to 10-bit accuracy at 500 KSample/s and 8-bit accuracy at 1 MSample/s – Differential conversions – Single-ended signal range from 0 to 5 V – Variable gain amplifiers on differential inputs (1, 2, 4) – Sample times of 2 (default), 8, 64 or 128 ADC clock cycles – Provides time stamp information when requested – Allows time stamp information relative to eTPU clock sources, such as an angle clock – Parallel interface to eQADC CFIFOs and RFIFOs – Supports both right-justified unsigned and signed formats for conversion results ● 40 single-ended input channels, expandable to 56 channels with external multiplexers (supports four external 8-to-1 muxes) ● 8 channels can be used as 4 pairs of differential analog input channels ● Differential channels include variable gain amplifier for improved dynamic range ● Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics (200 k100 k5 k ● Additional internal channels for monitoring voltages (such as core voltage, I/O voltage, LVI voltages, etc.) inside the device ● An internal bandgap reference to allow absolute voltage measurements ● Silicon die temperature sensor ● 22/157 – – Provides temperature of silicon as an analog value – Read using an internal ADC analog channel – May be read with either ADC 2 Decimation Filters – Programmable decimation factor (1 to 16) – Selectable IIR or FIR filter – Up to 4th order IIR or 8th order FIR – Programmable coefficients Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 ● ● ● 1.5.14 Introduction – Saturated or non-saturated modes – Programmable Rounding (Convergent; Two’s Complement; Truncated) – Prefill mode to precondition the filter before the sample window opens – Supports Multiple Cascading Decimation Filters to implement more complex filter designs – Optional Absolute Integrators on the output of Decimation Filters Full duplex synchronous serial interface to an external device – Free-running clock for use by an external device – Supports a 26-bit message length Priority based queues – Supports six queues with fixed priority. When commands of distinct queues are bound for the same ADC, the higher priority queue is always served first – Queue_0 can bypass all prioritization, buffering and abort current conversions to start a Queue_0 conversion a deterministic time after the queue trigger – Supports software and hardware trigger modes to arm a particular queue – Generates interrupt when command coherency is not achieved External hardware triggers – Supports rising edge, falling edge, high level and low level triggers – Supports configurable digital filter DSPI The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the SPC564A80 MCU and external devices. The DSPI supports pin count reduction through serialization and deserialization of eTPU and eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like protocol. This SPI-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion, etc. Each bit in the frame may be configured to serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI can be configured to serialize data to an external device that implements the Microsecond Bus protocol. There are three identical DSPI blocks on the SPC564A80 MCU. The DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) to improve high speed operation. DSPI module features include: ● Selectable LVDS pads working at 40 MHZ for SOUT and SCK pins for DSPI_B and DSPI_C ● 3 sources of serialized data: eTPU_A, eMIOS output channels and memory-mapped register in the DSPI ● 4 destinations for deserialized data: eTPU_A and eMIOS input channels, SIU external Interrupt input request, memory-mapped register in the DSPI ● 32-bit DSI and TSB modes require 32 PCR registers, 32 GPO and GPI registers in the SIU to select either GPIO, eTPU or eMIOS bits for serialization ● The DSPI Module can generate and check parity in a serial frame Doc ID 15399 Rev 9 23/157 Introduction 1.5.15 SPC564A74L7, SPC564A80B4, SPC564A80L7 eSCI Three enhanced serial communications interface (eSCI) modules provide asynchronous serial communications with peripheral devices and other MCUs, and include support to interface to Local Interconnect Network (LIN) slave devices. Each eSCI block provides the following features: ● Full-duplex operation ● Standard mark/space non-return-to-zero (NRZ) format ● 13-bit baud rate selection ● Programmable 8-bit or 9-bit, data format ● Programmable 12-bit or 13-bit data format for Timed Serial Bus (TSB) configuration to support the Microsecond bus standard ● Automatic parity generation ● LIN support – Autonomous transmission of entire frames – Configurable to support all revisions of the LIN standard – Automatic parity bit generation – Double stop bit after bit error – 10- or 13-bit break support ● Separately enabled transmitter and receiver ● Programmable transmitter output parity ● 2 receiver wake-up methods: – Idle line wake-up – Address mark wake-up ● Interrupt-driven operation with flags ● Receiver framing error detection ● Hardware parity checking ● 1/16 bit-time noise detection ● DMA support for both transmit and receive data – 1.5.16 Global error bit stored with receive data in system RAM to allow post processing of errors FlexCAN The SPC564A80 MCU includes three controller area network (FlexCAN) blocks. The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. Each FlexCAN module contains 64 message buffers. 24/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Introduction The FlexCAN modules provide the following features: ● Full Implementation of the CAN protocol specification, Version 2.0B – Standard data and remote frames – Extended data and remote frames – Zero to eight bytes data length – Programmable bit rate up to 1 Mbit/s ● Content-related addressing ● 64 message buffers of zero to eight bytes data length ● Individual Rx Mask Register per message buffer ● Each message buffer configurable as Rx or Tx, all supporting standard and extended messages ● Includes 1088 bytes of embedded memory for message buffer storage ● Includes 256-byte memory for storing individual Rx mask registers ● Full featured Rx FIFO with storage capacity for six frames and internal pointer handling ● Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16 standard or 32 partial (8 bits) IDs, with individual masking capability ● Selectable backwards compatibility with previous FlexCAN versions ● Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock ● Listen only mode capability ● Programmable loop-back mode supporting self-test operation ● 3 programmable Mask Registers ● Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority ● Time Stamp based on 16-bit free-running timer ● Global network time, synchronized by a specific message ● Maskable interrupts ● Warning interrupts when the Rx and Tx Error Counters reach 96 ● Independent of the transmission medium (an external transceiver is assumed) ● Multi-master concept ● High immunity to EMI ● Short latency time due to an arbitration scheme for high-priority messages ● Low power mode, with programmable wake-up on bus activity Doc ID 15399 Rev 9 25/157 Introduction 1.5.17 SPC564A74L7, SPC564A80B4, SPC564A80L7 FlexRay The SPC564A80 includes one dual-channel FlexRay module that implements the FlexRay Communications System Protocol Specification, Version 2.1 Rev A. Features include: ● Single channel support ● FlexRay bus data rates of 10 Mbit/s, 8 Mbit/s, 5 Mbit/s, and 2.5 Mbit/s supported ● 128 message buffers, each configurable as: ● ● 1.5.18 – Receive message buffer – Single buffered transmit message buffer – Double buffered transmit message buffer (combines two single buffered message buffer) 2 independent receive FIFOs – 1 receive FIFO per channel – Up to 255 entries for each FIFO ECC support System timers The system timers include two distinct types of system timer: ● Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT) ● Operating system task monitors using the System Timer Module (STM) Periodic interrupt timer (PIT) The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has no external input or output pins and is intended to provide system ‘tick’ signals to the operating system, as well as periodic triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock and one is clocked by the crystal clock. This one channel is also referred to as Real-Time Interrupt (RTI) and is used to wake up the device from low power stop mode. The following features are implemented in the PIT: ● 5 independent timer channels ● Each channel includes 32-bit wide down counter with automatic reload ● 4 channels clocked from system clock ● 1 channel clocked from crystal clock (wake-up timer) ● Wake-up timer remains active when System STOP mode is entered; used to restart system clock after predefined time-out period ● Each channel optionally able to generate an interrupt request or a trigger event (to trigger eQADC queues) when timer reaches zero System timer module (STM) The System Timer Module (STM) is designed to implement the software task monitor as defined by AUTOSAR(b). It consists of a single 32-bit counter, clocked by the system clock, b. AUTOSAR: AUTomotive Open System ARchitecture (see www.autosar.org) 26/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Introduction and four independent timer comparators. These comparators produce a CPU interrupt when the timer exceeds the programmed value. The following features are implemented in the STM: 1.5.19 ● One 32-bit up counter with 8-bit prescaler ● Four 32-bit compare channels ● Independent interrupt source for each channel ● Counter can be stopped in debug mode Software watchdog timer (SWT) The Software Watchdog Timer (SWT) is a second watchdog module to complement the standard Power Architecture watchdog integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can provide a system reset or interrupt request when the correct software key is not written within the required time window. The following features are implemented: 1.5.20 ● 32-bit modulus counter ● Clocked by system clock or crystal clock ● Optional programmable watchdog window mode ● Can optionally cause system reset or interrupt request on timeout ● Reset by writing a software key to memory mapped register ● Enabled out of reset ● Configuration is protected by a software key or a write-once register Cyclic redundancy check (CRC) module The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC features: ● Support for CRC-16-CCITT (x25 protocol): – ● Support for CRC-32 (Ethernet protocol): – ● 1.5.21 X16 + X12 + X5 + 1 X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency Error correction status module (ECSM) The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes, and information on platform memory errors reported by error-correcting codes and/or generic access error information for certain processor cores. Doc ID 15399 Rev 9 27/157 Introduction SPC564A74L7, SPC564A80B4, SPC564A80L7 The Error Correction Status Module supports a number of miscellaneous control functions for the platform. The ECSM includes these features: ● Registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented ● For test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the SPC564A80. The sources of the ECC errors are: 1.5.22 ● Flash ● SRAM ● Peripheral RAM (FlexRay, CAN, eTPU2 Parameter RAM) External bus interface (EBI) The SPC564A80 device features an external bus interface that is available in PBGA324 and calibration packages. The EBI supports operation at frequencies of system clock /1, /2 and /4, with a maximum frequency support of 80 MHz. Customers running the device at 120 MHz or 132 MHz will use the /2 divider, giving an EBI frequency of 60 MHz or 66 MHz. Customers running the device at 80 MHz will be able to use the /1 divider to have the EBI run at the full 80 MHz frequency. Features include: 1.5.23 ● 1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V) ● Memory controller with support for various memory types ● 16-bit data bus, up to 22-bit address bus ● Pin muxing included to support 32-bit muxed bus ● Selectable drive strength ● Configurable bus speed modes ● Bus monitor ● Configurable wait states Calibration EBI The Calibration EBI controls data transfer across the crossbar switch to/from memories or peripherals attached to the calibration tool connector in the calibration address space. The Calibration EBI is only available in the calibration tool. Features include: 28/157 ● 1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V) ● Memory controller supports various memory types ● 16-bit data bus, up to 22-bit address bus ● Pin muxing supports 32-bit muxed bus ● Selectable drive strength ● Configurable bus speed modes ● Bus monitor ● Configurable wait states Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 1.5.24 Introduction Power management controller (PMC) The power management controller contains circuitry to generate the internal 3.3 V supply and to control the regulation of 1.2 V supply with an external NPN ballast transistor. It also contains low voltage inhibit (LVI) and power-on reset (POR) circuits for the 1.2 V supply, the 3.3 V supply, the 3.3 V/5 V supply of the closest I/O segment (VDDEH1) and the 5 V supply of the regulators (VDDREG). 1.5.25 Nexus port controller The NPC (Nexus Port Controller) block provides real-time Nexus Class3+ development support capabilities for the SPC564A80 Power Architecture-based MCU in compliance with the IEEE-ISTO 5001-2003 and 2010 standards. MDO port widths of 4 pins and 12 pins are available in all packages. 1.5.26 JTAG The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant with the IEEE 1149.1-2001 standard and supports the following features: ● IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO) ● A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions: – ● ● 1.5.27 BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP A 5-bit instruction register that supports the additional following public instructions: – ACCESS_AUX_TAP_NPC – ACCESS_AUX_TAP_ONCE – ACCESS_AUX_TAP_eTPU – ACCESS_CENSOR 3 test data registers to support JTAG Boundary Scan mode – Bypass register – Boundary scan register – Device identification register ● A TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry ● Censorship Inhibit Register – 64-bit Censorship password register – If the external tool writes a 64-bit password that matches the Serial Boot password stored in the internal flash shadow row, Censorship is disabled until the next system reset. Development Trigger Semaphore (DTS) SPC564A80 devices include a system development feature, the Development Trigger Semaphore (DTS) module, that enables software to signal an external tool by driving a persistent (affected only by reset or an external tool) signal on an external device pin. There Doc ID 15399 Rev 9 29/157 Introduction SPC564A74L7, SPC564A80B4, SPC564A80L7 is a variety of ways this module can be used, including as a component of an external realtime data acquisition system 1.6 SPC564A80 series architecture 1.6.1 Block diagram Figure 1 shows a top-level block diagram of the SPC564A80 series. 30/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Introduction Power ArchitectureTM e200z4 JTAG Nexus Class 3+ SPE Nexus VLE MMU eDMA 64 Channel 8 KB I-cache M4 FlexRay M1 M0 M6 Crossbar Switch MPU S0 S2 4 MB Flash IEEE-ISTO 5001-2003/2010 M7 S1 S7 Analog PLL 192 KB SRAM Voltage Regulator RCOSC Standby Regulator with Switch XOSC ECSM Cal Bus Interface Ext. Bus Interface Interrupt Controller Temp Sens ADC ADC eSCI3 DSPI3 FlexCAN3 PIT SWT SIU STM BAM PMC FMPLL CRC DTS 3 KB Data eTPU2 eMIOS 32 RAM Channel 24 14 KB Code Nexus Channel RAM Class 1 REACM I/O Bridge ADCi DEC x2 AMux VGA LEGEND ADC – Analog to Digital Converter ADCi – ADC interface AMux – Analog Multiplexer BAM – Boot Assist Module CRC – Cyclic Redundancy Check unit DEC – Decimation Filter DTS – Development Trigger Semaphore DSPI – Deserial/Serial Peripheral Interface EBI – External Bus Interface ECSM – Error Correction Status Module eDMA – Enhanced Direct Memory Access eMIOS – Enhanced Modular Input Output System eSCI – Enhanced Serial Communications Interface eTPU2 – Second gen. Enhanced Time Processing Unit FlexCAN– Controller Area Network (FlexCAN) FMPLL – Frequency-Modulated Phase Locked Loop Figure 1. JTAG MMU MPU PMC PIT RCOSC REACM SIU SPE SRAM STM SWT VGA VLE XOSC – IEEE 1149.1 test controller – Memory Management Unit – Memory Protection Unit – Power Management Controller – Periodic Interrupt Timer – low-speed RC oscillator – Reaction module – System Integration Unit – Signal Processing Extension – Static RAM – System Timer Module – Software Watchdog Timer – Variable Gain Amplifier – Variable Length (instruction) Encoding – XTAL Oscillator SPC564A80 series block diagram Doc ID 15399 Rev 9 31/157 Introduction 1.6.2 SPC564A74L7, SPC564A80B4, SPC564A80L7 Block summary Table 3 summarizes the functions of the blocks present on the SPC564A80 series microcontrollers. Table 3. SPC564A80 series block summary Block Function Boot assist module (BAM) Block of read-only memory containing executable code that searches for user-supplied boot code and, if none is found, executes the BAM boot code resident in device ROM. Calibration Bus interface Transfers data across the crossbar switch to/from peripherals attached to the calibration tool connector. Controller area network (FlexCAN) Supports the standard CAN communications protocol. Crossbar switch (XBAR) Internal busmaster. Cyclic redundancy check (CRC) CRC checksum generator. Deserial serial peripheral interface (DSPI) Provides a synchronous serial interface for communication with external devices. e200z4 core Executes programs and interrupt handlers. Enhanced direct memory access (eDMA) Performs complex data movements with minimal intervention from the core. Enhanced modular input-output system (eMIOS) Provides the functionality to generate or measure events. Enhanced queued analog-to-digital converter (eQADC) Provides accurate and fast conversions for a wide range of applications. Enhanced serial communication interface (eSCI) Provides asynchronous serial communication capability with peripheral devices and other microcontroller units. Enhanced time processor unit (eTPU2) Second-generation co-processor processes real-time input events, performs output waveform generation, and accesses shared data without host intervention. Error Correction Status Module (ECSM) The Error Correction Status Module supports a number of miscellaneous control functions for the platform, and includes registers for capturing information on platform memory errors if errorcorrecting codes (ECC) are implemented External bus interface (EBI) Enables expansion of internal bus to enable connection of external memory or peripherals. Flash memory Provides storage for program code, constants, and variables. FlexRay Provides high-speed distributed control for advanced automotive applications. Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests. JTAG controller Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. Memory protection unit (MPU) Provides hardware access control for all memory references generated. Nexus port controller (NPC) Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2003 standard. 32/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 3. Introduction SPC564A80 series block summary (continued) Block Function Reaction Module (REACM) Works in conjunction with the eQADC and eTPU2 to increase system performance by removing the CPU from the current control loop. System Integration Unit (SIU) Controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. Static random-access memory (SRAM) Provides storage for program code, constants, and variables. System timers Includes periodic interrupt timer with real-time interrupt; output compare timer and system watchdog timer. Temperature sensor Provides the temperature of the device as an analog value. Doc ID 15399 Rev 9 33/157 Pinout and signal description 2 SPC564A74L7, SPC564A80B4, SPC564A80L7 Pinout and signal description This section contains the pinouts for all production packages for the SPC564A80 family of devices. Caution: 34/157 Any pins labeled “NC” are to be left unconnected. Any connection to an external circuit or voltage may cause unpredictable device behavior or damage. Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 LQFP176 pinout 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VDD AN[37] AN[36] AN[21] AN[0] (DAN0+) AN[1] (DAN0-) AN[2] (DAN1+) AN[3] (DAN1-) AN[4] (DAN2+) AN[5] (DAN2-) AN[6] (DAN3+) AN[7] (DAN3-) REFBYPC VRH VRL AN[22] AN[23] AN[24] AN[25] AN[27] AN[28] AN[30] AN[31] AN[32] AN[33] AN[34] AN[35] VDD AN[12] / MA[0] / ETPUA19_O /SDS AN[13] / MA[1] / ETPUA21_O / SDO AN[14] / MA[2] / ETPUA27_O / SDI AN[15] / FCK / ETPUA29_O GPIO[207] ETRIG1 GPIO[206] ETRIG0 DSPI_D_SIN / GPIO[99] DSPI_D_SCK / GPIO[98] VSS MDO9 / ETPUA25_O / GPIO[80] VDDEH7B MDO8 / ETPUA21_O / GPIO[79] MDO7 / ETPUA19_O / GPIO[78] MDO6 / ETPUA13_O / GPIO[77] MDO10 / ETPUA27_O / GPIO[81] VSS 2.1 Pinout and signal description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176-Pin LQFP signal details: pin 21: ETPUA31 / DSPI_C_PCS[4] / ETPUA13_O / GPIO[145] pin 22: ETPUA30 / DSPI_C_PCS[3] / ETPUA11_O / GPIO[144] pin 23: ETPUA29 / DSPI_C_PCS[2] / RCH5_C / GPIO[143] pin 24: ETPUA28 / DSPI_C_PCS[1] / RCH5_B / GPIO[142] pin 25: ETPUA27 / IRQ[15] / DSPI_C_SOUT_LVDS+ / SOUTB / GPIO[141] pin 26: ETPUA26 / IRQ[14] / DSPI_C_SOUT_LVDS- / GPIO[140] pin 27: ETPUA25 / IRQ[13] / DSPI_C_SCK_LVDS+ / GPIO[139] pin 28: ETPUA24 / IRQ[12] / DSPI_C_SCK_LVDS- / GPIO[138] pin 30: ETPUA23 / IRQ[11] / ETPUA21_O / FR_A_TX_EN / GPIO[137] pin 32: ETPUA22 / IRQ[10] / ETPUA17_O / GPIO[136] pin 34: ETPUA21 / IRQ[9] / RCH0_C / FR_A_RX / GPIO[135] pin 35: ETPUA20 / IRQ[8] / RCH0_B / FR_A_TX / GPIO[134] pin 36: ETPUA19 / DSPI_D_PCS[4] / RCH5_A / GPIO[133] pin 37: ETPUA18 / DSPI_D_PCS[3] / RCH4_A / GPIO[132] pin 38: ETPUA17 / DSPI_D_PCS[2] / RCH3_A / GPIO[131] pin 39: ETPUA16 / DSPI_D_PCS[1] / RCH2_A / GPIO[130] pin 40: ETPUA15 / DSPI_B_PCS[5] / RCH1_A / GPIO[129] pin 42: ETPUA14 / DSPI_B_PCS[4] / ETPUA9_O / RCH0_A / GPIO[128] 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 VDD TMS TDI MDO5 / ETPUA4_O / GPIO[76] TCK VSS MDO4 / ETPUA2_O / GPIO[75] VDDEH7A MDO11 / ETPUA29_O / GPIO[82] TDO GPIO[219] JCOMP EVTO NC MSEO[0] MSEO[1] EVTI VSS DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108] DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104] DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103] DSPI_B_PCS[0] / DSPI_D_PCS[2] / GPIO[105] VDDEH6B DSPI_B_PCS[1] / DSPI_D_PCS[0] / GPIO[106] VSS DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107] DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102] DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109] DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110] VDD RSTOUT CAN_C_TX / DSPI_D_PCS3 / GPIO[87] SCI_A_TX / EMIOS13 / GPIO[89] SCI_A_RX / EMIOS15 / GPIO[90] CAN_C_RX / DSPI_D_PCS4 / GPIO[88] RESET VSS VDDEH6A VSS XTAL EXTAL / EXTCLK VDDPLL VSS CAN_B_RX / DSPI_C_PCS[4] / SCI_C_RX / GPIO[86] VDD ETPUA13 / DSPI_B_PCS[3] / GPIO[127] ETPUA12 / DSPI_B_PCS[1] / RCH4_C / GPIO[126] ETPUA11 / ETPUA23_O / RCH4_B / GPIO[125] ETPUA10 / ETPUA22_O / RCH1_C /GPIO[124] ETPUA9 / ETPUA21_O / RCH1_B / GPIO[123] ETPUA8 / ETPUA20_O / DSPI_B_SOUT_LVDS+ / GPIO[122] ETPUA7 / ETPUA19_O / DSPI_B_SOUT_LVDS- / ETPUA6_O / GPIO[121] ETPUA6 / ETPUA18_O / DSPI_B_SCK_LVDS+ / FR_B_RX / GPIO[120] ETPUA5 / ETPUA17_O / DSPI_B_SCK_LVDS- / FR_B_TX_EN/ GPIO[119] VDDEH4A ETPUA4 / ETPUA16_O / FR_B_TX / GPIO[118] VSS ETPUA3 / ETPUA15_O / GPIO[117] ETPUA2 / ETPUA14_O / GPIO[116] ETPUA1 / ETPUA13_O / GPIO[115] ETPUA0 / ETPUA12_O / ETPUA19_O / GPIO[114] VDD EMIOS0 / ETPUA0 / ETPUA25_O / GPIO[179] EMIOS1 / ETPUA1_O / GPIO[180] EMIOS2 / ETPUA2_O / RCH2_B / GPIO[181] EMIOS3 / ETPUA3_O /GPIO[182] EMIOS4 / ETPUA4_O / RCH2_C / GPIO[183] EMIOS6 / ETPUA6_O / GPIO[185] EMIOS7 / ETPUA7_O / GPIO[186] EMIOS8 / ETPUA8_O / SCI_B_TX / GPIO[187] EMIOS9 / ETPUA9_O / SCI_B_RX / GPIO[188] VSS EMIOS10 / DSPI_D_PCS3 / RCH3_B / GPIO[189] VDDEH4B EMIOS11 / DSPI_D_PCS4 / RCH3_C / GPIO[190] EMIOS12 / DSPI_C_SOUT / ETPUA27_O / GPIO[191] EMIOS13 / DSPI_D_SOUT / GPIO[192] EMIOS14 / IRQ[0] / ETPUA29_O / GPIO[193] EMIOS15 / IRQ[1] / GPIO[194] EMIOS23 / GPIO[202] CAN_A_TX / SCI_A_TX / GPIO[83] CAN_A_RX / SCI_A_RX / GPIO[84] PLLREF / IRQ[4]/ETRIG[2] / GPIO[208] SCI_B_RX / DSPI_D_PCS5 / GPIO[92] BOOTCFG1 / IRQ[3] / ETRIG[3] / GPIO[212] WKPCFG / NMI / DSPI_B_SOUT / GPIO[213] SCI_B_TX / DSPI_D_PCS1 / GPIO[91] CAN_B_TX / DSPI_C_PCS3 / SCI_C_TX / GPIO[85] 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 AN[18] AN[17] AN[16] AN[11] / ANZ AN[9] / ANX VDDA VSSA AN[39] AN[8] / ANW VDDREG VRCCTL VSTBY VRC33 MCKO VSS NC MDO[0] MDO[1] MDO[2] MDO[3] (see signal details, pin 21) (see signal details, pin 22) (see signal details, pin 23) (see signal details, pin 24) (see signal details, pin 25) (see signal details, pin 26) (see signal details, pin 27) (see signal details, pin 28) VSS (see signal details, pin 30) VDDEH1A (see signal details, pin 32) VDD (see signal details, pin 34) (see signal details, pin 35) (see signal details, pin 36) (see signal details, pin 37) (see signal details, pin 38) (see signal details, pin 39) (see signal details, pin 40) VDDEH1B (see signal details, pin 42) VSS NIC Note: Pin 96 (VSS) should be tied low. Figure 2. 176-pin LQFP pinout (top view) Doc ID 15399 Rev 9 35/157 LBGA208 ballmap Figure 3. 208-pin LBGA package ballmap (viewed from above) Doc ID 15399 Rev 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A VSS AN9 AN11 VDDA1 VSSA1 AN1 AN5 VRH VRL AN27 VSSA0 AN12-SDS MDO2 MDO0 VRC33 VSS A B VDD VSS AN8 AN21 AN0 AN4 REFBYPC AN22 AN25 AN28 VDDA0 AN13-SDO MDO3 MDO1 VSS VDD B C VSTBY VDD VSS AN17 AN34 AN16 AN3 AN7 AN23 AN32 AN33 AN14-SDI AN15-FCK VSS MSEO0 TCK C D VRC33 AN39 VDD VSS AN18 AN2 AN6 AN24 AN30 AN31 AN35 VDDEH7 VSS TMS EVTO NC D E ETPUA30 ETPUA31 AN37 VDD NC TDI EVTI MSEO1 E F ETPUA28 ETPUA29 ETPUA26 AN36 VDDEH6AB TDO MCKO JCOMP F G ETPUA24 ETPUA27 ETPUA25 ETPUA21 VSS VSS VSS VSS DSPI_B_ SOUT DSPI_B_ PCS3 DSPI_B_ SIN DSPI_B_ PCS0 G H ETPUA23 ETPUA22 ETPUA17 ETPUA18 VSS VSS VSS VSS GPIO99 DSPI_B_ PCS4 DSPI_B_ PCS2 DSPI_B_ PCS1 H J ETPUA20 ETPUA19 ETPUA14 ETPUA13 VSS VSS VSS VSS DSPI_B_ PCS5 SCI_A_TX GPIO98 DSPI_B_ SCK J K ETPUA16 ETPUA15 ETPUA7 VDDEH1AB VSS VSS VSS VSS CAN_C_TX SCI_A_R X RSTOUT VDDREG K L ETPUA12 ETPUA11 ETPUA6 TCRCLKA SCI_B_TX CAN_C_ RX WKPCFG RESET L M ETPUA10 ETPUA9 ETPUA1 ETPUA5 SCI_B_RX PLLREF BOOTCFG1 VSS M ETPUA8 ETPUA4 ETPUA0 VSS VDD VRC33 EMIOS2 EMIOS10 VDDEH4AB EMIOS12 P ETPUA3 ETPUA2 VSS VDD GPIO207 NC EMIOS6 EMIOS8 MDO11_ ETPUA29_ O MDO4_ ETPUA2_O MDO8_ ETPUA21_ O CAN_A_TX VDD VSS NC XTAL P R NC VSS VDD GPIO206 EMIOS4 EMIOS3 EMIOS9 EMIOS11 EMIOS14 MDO10_ ETPUA27_ O EMIOS23 CAN_A_RX CAN_B_RX VDD VSS VDDPLL R T VSS VDD NC EMIOS0 EMIOS1 GPIO219 MDO9_ ETPUA25_ O EMIOS13 EMIOS15 MDO5_ ETPUA4_O MDO6_ ETPUA13_ O CAN_B_TX VDDE5 ENGCLK VDD VSS T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 36/157 1. This pin (N13) should be tied low. VRC33 VSS(1) VRCCTL NC EXTAL N Pinout and signal description N MDO7_ ETPUA19_ O SPC564A74L7, SPC564A80B4, SPC564A80L7 2.2 PBGA324 ballmap 2 3 4 5 6 7 8 9 10 11 A VSS VDD VSTBY AN37 AN11 VDDA0 VSSA0 AN1 AN5 VRH VRL B VRC33 VSS VDD AN36 AN39 AN19 AN16 AN0 AN4 REFBYPC AN23 C ETPUA30 ETPUA31 VSS VDD AN38 AN17 AN20 AN21 AN3 AN7 AN22 D ETPUA28 ETPUA29 ETPUA26 VSS VDD AN8 ANW AN9 AN10 ANY AN18 AN2 AN6 E ETPUA24 ETPUA27 ETPUA25 ETPUA21 F ETPUA23 ETPUA22 ETPUA17 ETPUA18 G ETPUA20 ETPUA19 ETPUA14 ETPUA13 H ETPUA16 ETPUA15 ETPUA10 VDDEH1AB J ETPUA12 ETPUA11 ETPUA6 ETPUA9 VSS VSS VSS K ETPUA8 ETPUA7 ETPUA2 ETPUA5 VSS VSS VSS L ETPUA4 ETPUA3 ETPUA0 ETPUA1 VSS VSS VSS Figure 4. 324-pin PBGA package ballmap (northwest, viewed from above) SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 1 Pinout and signal description 37/157 2.3 BDIP TCRCLKA CS1 CS0 VDDE2 VDDE2 VSS N CS3 CS2 WE1 WE0 VSS VSS VDDE2 P ADDR16 ADDR17 RD_WR VRC33 VSS VSS VDDE2 R ADDR18 ADDR19 VDDE-EH TA T ADDR20 ADDR21 ADDR12 TS U ADDR22 ADDR23 ADDR13 ADDR14 V ADDR24 ADDR25 ADDR15 ADDR31 W ADDR26 VDDE-EH ADDR30 VSS VDD VDDE2 VRC33 VDDE2 DATA11 DATA12 DATA14 Y ADDR28 ADDR27 VSS VDD VDDE2 DATA8 DATA9 DATA10 GPIO207 DATA13 DATA15 AA ADDR29 VSS VDD VDDE2 DATA1 VDDE2 GPIO206 DATA5 DATA7 VDDE2 EMIOS3 AB VSS VDD VDDE2 DATA0 DATA2 DATA3 DATA4 DATA6 OE EMIOS0 EMIOS1 1 2 3 4 5 6 7 8 9 10 11 Figure 5. SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 M 324-pin PBGA package ballmap (southwest, viewed from above) Pinout and signal description 38/157 14 15 16 17 18 19 20 21 22 AN27 AN28 AN35 VSSA1 AN12_ SDS MDO11_ ETPUA29_O MDO10_ ETPUA27_O MDO8_ ETPUA21_O VDD VRC33 VSS A AN26 AN31 AN32 VSSA1 AN13_ SDO MDO9_ ETPUA25_O MDO7_ ETPUA19_O MDO4_ ETPUA2_O MDO0 VSS NIC(1),(2) B AN25 AN30 AN33 VDDA1 AN14_ SDI MDO5_ ETPUA4_O MDO2 MDO1 VSS NIC(1),(2) VDD C AN24 AN29 AN34 VDDEH7 AN15_ FCK MDO6_ ETPUA13_O MDO3 VSS NIC(1),(2) TCK TDI D NIC(1),(2) TMS TDO NIC(1) E NIC(1),(2) JCOMP EVTI EVTO F RDY MCKO MSEO0 MSEO1 G VDDEH6AB GPIO203 GPIO204 DSPI_B_ SIN H VSS VSS NIC(1),(2) DSPI_B_ SOUT DSPI_B_ PCS3 DSPI_B_ PCS0 DSPI_B_ PCS1 J VSS VSS VSS GPIO99 DSPI_B_ PCS4 DSPI_B_ SCK DSPI_B_ PCS2 K VSS VSS VSS DSPI_B_ PCS5 DSPI_A_ SOUT DSPI_A_ SIN DSPI_A_ SCK L 1. Pins marked “NIC” have no internal connection. 2. Balls B22, C21, D20, E19, F19 and J14 are shorted together inside the package. Figure 6. 324-pin PBGA package ballmap (northeast, viewed from above) SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 13 Pinout and signal description 39/157 12 VSS VSS DSPI_A_ PCS1 DSPI_A_ PCS0 GPIO98 VDDREG M VSS VSS VSS DSPI_A_ PCS4 SCI_A_TX DSPI_A_ PCS5 NIC(1) N VSS VSS VSS CAN_C_TX SCI_A_RX RSTOUT RSTCFG P WKPCFG CAN_C_RX SCI_B_TX RESET R SCI_B_RX BOOTCFG1 VSS(2) VSS T VDDEH6AB PLLCFG1 BOOTCFG0 EXTAL U VDD VRCCTL PLLREF XTAL V Doc ID 15399 Rev 9 EMIOS2 EMIOS8 VDDEH4AB EMIOS12 EMIOS21 VDDE5 SCI_C_TX VSS VDD NIC(1) VDDPLL W EMIOS6 EMIOS10 EMIOS15 EMIOS17 EMIOS22 CAN_A_TX VDDE5 SCI_C_RX VSS VDD VRC33 Y EMIOS5 EMIOS9 EMIOS13 EMIOS16 EMIOS19 EMIOS23 CAN_A_RX VDDE5 CLKOUT VSS VDD AA EMIOS4 EMIOS7 EMIOS11 EMIOS14 EMIOS18 EMIOS20 CAN_B_TX CAN_B_RX VDDE5 ENGCLK VSS AB 12 13 14 15 16 17 18 19 20 21 22 SPC564A74L7, SPC564A80B4, SPC564A80L7 VSS 1. Pins marked “NIC” have no internal connection. 2. This pin (T21) should be tied low. Figure 7. 324-pin PBGA package ballmap (southeast, viewed from above) Pinout and signal description 40/157 Signal summary Table 4. SPC564A80 signal properties Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) I/O Type (3) Package pin # (5) Voltage / Pad Type(6) During Reset After Reset 176 208 324 GPIO (8) eMIOS channel P 01 GPIO[203] GPIO G 00 EMIOS15(8) eMIOS channel P 01 GPIO[204] GPIO G 00 GPIO[206] ETRIG0 GPIO / eQADC Trigger Input G 00 GPIO[207] ETRIG1 GPIO / eQADC Trigger Input G 00 GPIO[219] GPIO G — EMIOS14 203 O VDDEH7 I/O Slow VDDEH7 Slow 206 I/O(9) VDDEH7 207 I/O(9) VDDEH7 I/O MultiV(12) 219 (11) Slow(10) Slow VDDEH7 — / Up — — H20 — / Up —/ Up — — H21 — / Up — / Up 143 R4 AA7 — / Up — / Up 144 P5 Y9 — / Up — / Up 122 T6 97 L16 R22 RSTOUT / Down 102 K15 P21 PLLREF / Up 83 M14 V21 — Reset / Configuration RESET External Reset Input P — — I RSTOUT External Reset Output P 01 230 O PLLREF FMPLL Mode Selection P 001 IRQ[4] External Interrupt Request A1 010 ETRIG2 eQADC Trigger Input A2 100 GPIO G 000 I/O — GPIO[208] (13) — — — IRQ[5] External interrupt request A1 010 DSPI_D_SOUT DSPI D data output A2 100 GPIO[209] GPIO G 000 RSTCFG RSTCFG P 01 GPIO[210] GPIO G 00 PLLCFG1 VDDEH6 Slow VDDEH6 Slow RESET / Up RSTOUT / Down RESET / Up I 208 209 I VDDEH6 I Slow I VDDEH6 O Medium — / Up — / Up — / Up — — U20 — — — P22 I/O 210 I VDDEH6 I/O Slow — / Down SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 O I/O 204 — / Up Pinout and signal description 41/157 2.4 SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type Doc ID 15399 Rev 9 BOOTCFG[0] Boot Config. Input P 01 IRQ[2] External Interrupt Request A1 10 GPIO[211] GPIO G 00 I/O BOOTCFG[1] Boot Config. Input P 001 I IRQ[3] External Interrupt Request A1 010 ETRIG3 eQADC Trigger Input A2 100 GPIO[212] GPIO G 000 I/O WKPCFG Weak Pull Config. Input P 001 I NMI Non-Maskable Interrupt A1 010 DSPI_B_SOUT DSPI D data output A2 100 GPIO[213] GPIO G 000 I 211 212 213 I Package pin # (5) Voltage / Pad Type(6) VDDEH6 Slow I VDDEH6 I Slow I VDDEH6 O Medium During Reset — / Down After Reset BOOTCFG[0] / Down 176 208 — — 324 U21 BOOTCFG[1] / Down 85 M15 T20 — / Up WKPCFG / Up 86 L15 R19 — / Up — / Up — — M4 — / Up — / Up — — M3 — / Up — / Up — — N2 — / Up — / Up — — N1 I/O External Bus Interface CS[0] External chip selects P 01 ADDR[8] External address bus A1 10 GPIO[0] GPIO G 00 CS[1] External chip selects P 01 ADDR9 External address bus A1 10 GPIO[1] GPIO G 00 O 0 I/O I/O O 1 I/O I/O CS[2] External chip selects P 0001 O ADDR10 External address bus A1 0010 I/O WE[2]/BE[2] Write/byte enable A2 0100 CAL_WE[2]/BE[2] Cal. bus write/byte enable A3 1000 O GPIO[2] GPIO G 0000 I/O 2 O CS[3] External chip selects P 0001 O ADDR11 External address bus A1 0010 I/O WE[3]/BE[3] Write/byte enable A2 0100 CAL_WE[3]/BE[3] Cal bus write/byte enable A3 1000 O GPIO[3] GPIO G 0000 I/O 3 O VDDE2 Fast VDDE2 Fast VDDE2 Fast VDDE2 Fast 42/157 Pinout and signal description — / Down SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type External address bus P 01 GPIO[8] GPIO G 00 ADDR13 External address bus P 001 WE[2] Write/byte enable A2 100 GPIO[9] GPIO G 000 ADDR14 External address bus P 001 WE[3] Write/byte enables A2 100 GPIO[10] GPIO G 000 ADDR15 External address bus P 01 GPIO[11] GPIO G 00 ADDR16 External address bus P 001 FR_A_TX Flexray TX data channel A A1 010 DATA16 External data bus A2 100 GPIO[12] GPIO G 000 I/O ADDR17 External address bus P 001 I/O FR_A_TX_EN FlexRay ch. A TX data enable A1 010 DATA17 External data bus A2 100 GPIO[13] GPIO G 000 I/O ADDR18 External address bus P 001 I/O FR_A_RX Flexray RX data ch. A A1 010 DATA18 External data bus A2 100 GPIO[14] GPIO G 000 I/O ADDR19 External address bus P 001 I/O FR_B_TX Flexray TX data ch. B A1 010 DATA19 External data bus A2 100 GPIO[15] GPIO G 000 I/O ADDR20 External address bus P 001 I/O FR_B_TX_EN Flexray TX data enable for ch. B A1 010 DATA20 External data bus A2 100 GPIO[16] GPIO G 000 8 I/O VDDE3 I/O Fast I/O 9 O I/O I/O 10 O I/O 11 Voltage / Pad Type(6) VDDE3 Fast VDDE3 Fast I/O VDDE3 I/O Fast During Reset After Reset 176 208 324 — / Up — / Up — — T3 — / Up — / Up — — U3 — / Up — / Up — — U4 — / Up — / Up — — V3 — / Up — / Up — — P1 — / Up — / Up — — P2 — / Up — / Up — — R1 — / Up — / Up — — R2 — / Up — / Up — — T1 I/O 12 13 14 15 16 O VDDE-EH I/O Medium O VDDE-EH I/O Medium I VDDE-EH I/O Medium O VDDE-EH I/O Medium O VDDE-EH I/O Medium I/O SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 ADDR12 Package pin # (5) Pinout and signal description 43/157 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) Doc ID 15399 Rev 9 External address bus P 001 FR_B_RX Flexray RX data channel B A1 010 DATA21 External data bus A2 100 GPIO[17] GPIO G 000 ADDR22 External address bus P 001 DATA22 External data bus A2 100 GPIO[18] GPIO G 000 ADDR23 External address bus P 001 DATA23 External data bus A2 100 GPIO[19] GPIO G 000 ADDR24 External address bus P 001 DATA24 External data bus A2 100 GPIO[20] GPIO G 000 ADDR25 External address bus P 001 DATA25 External data bus A2 100 GPIO[21] GPIO G 000 ADDR26 External address bus P 001 DATA26 External data bus A2 100 GPIO[22] GPIO G 000 ADDR27 External address bus P 001 DATA27 External data bus A2 100 GPIO[23] GPIO G 000 ADDR28 External address bus P 001 DATA28 External data bus A2 100 GPIO[24] GPIO G 000 ADDR29 External address bus P 001 DATA29 External data bus A2 100 GPIO[25] GPIO G 000 Type Voltage / Pad Type(6) Package pin # During Reset After Reset 176 208 324 I/O 17 I VDDE-EH I/O Medium — / Up — / Up — — T2 — / Up — / Up — — U1 — / Up — / Up — — U2 — / Up — / Up — — V1 — / Up — / Up — — V2 — / Up — / Up — — W1 — / Up — / Up — — Y2 — / Up — / Up — — Y1 — / Up — / Up — — AA1 I/O I/O 18 I/O I/O I/O 19 I/O I/O I/O 20 I/O I/O I/O 21 I/O I/O I/O 22 I/O I/O I/O 23 I/O I/O I/O 24 I/O I/O I/O 25 I/O I/O VDDE-EH Medium VDDE-EH Medium VDDE-EH Medium VDDE-EH Medium VDDE-EH Medium VDDE-EH Medium VDDE-EH Medium VDDE-EH Medium 44/157 Pinout and signal description ADDR21 I/O (5) SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type External address bus P 001 ADDR6(8) External address bus A1 010 DATA30 External data bus A2 100 GPIO[26] GPIO G 000 I/O ADDR31 External address bus P 001 I/O ADDR7(8) External address bus A1 010 DATA31 External data bus A2 100 GPIO[27] GPIO G 000 DATA0 External data bus P 001 ADDR16 External address bus A1 010 GPIO[28] GPIO G 000 DATA1 External data bus P 001 ADDR17 External address bus A1 010 GPIO[29] GPIO G 000 DATA2 External data bus P 001 ADDR18 External address bus A1 010 GPIO[30] GPIO G 000 DATA3 External data bus P 001 ADDR19 External address bus A1 010 GPIO[31] GPIO G 000 DATA4 External data bus P 001 ADDR20 External address bus A1 010 GPIO[32] GPIO G 000 DATA5 External data bus P 001 ADDR21 External address bus A1 010 GPIO[33] GPIO G 000 DATA6 External data bus P 001 ADDR22 External address bus A1 010 GPIO[34] GPIO G 000 Voltage / Pad Type(6) During Reset After Reset 176 208 324 I/O 26 27 O VDDE-EH I/O Medium O VDDE-EH I/O Medium — / Up — / Up — — W3 — / Up — / Up — — V4 — / Up — / Up — — AB4 — / Up — / Up — — AA5 — / Up — / Up — — AB5 — / Up — / Up — — AB6 — / Up — / Up — — AB7 — / Up — / Up — — AA8 — / Up — / Up — — AB8 I/O I/O 28 I/O I/O I/O 29 I/O I/O I/O 30 I/O I/O I/O 31 I/O I/O I/O 32 I/O I/O I/O 33 I/O I/O I/O 34 I/O I/O VDDE5 Fast VDDE5 Fast VDDE5 Fast VDDE5 Fast VDDE5 Fast VDDE5 Fast VDDE5 Fast SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 ADDR30 Package pin # (5) Pinout and signal description 45/157 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) Doc ID 15399 Rev 9 External data bus P 001 ADDR23 External address bus A1 010 GPIO[35] GPIO G 000 DATA8 External data bus P 001 ADDR24 External address bus A1 010 GPIO[36] GPIO G 000 DATA9 External data bus P 001 ADDR25 External address bus A1 010 GPIO[37] GPIO G 000 DATA10 External data bus P 001 ADDR26 External address bus A1 010 GPIO[38] GPIO G 000 DATA11 External data bus P 001 ADDR27 External address bus A1 010 GPIO[39] GPIO G 000 DATA12 External data bus P 001 ADDR28 External address bus A1 010 GPIO[40] GPIO G 000 DATA13 External data bus P 001 ADDR29 External address bus A1 010 GPIO[41] GPIO G 000 DATA14 External data bus P 001 ADDR30 External address bus A1 010 GPIO[42] GPIO G 000 DATA15 External data bus P 001 ADDR31 External address bus A1 010 GPIO[43] GPIO G 000 RD_WR External read/write P 01 GPIO[62] GPIO G 00 Type I/O 35 I/O I/O I/O 36 I/O I/O I/O 37 I/O I/O I/O 38 I/O I/O I/O 39 I/O I/O I/O 40 I/O I/O I/O 41 I/O I/O I/O 42 I/O I/O I/O 43 I/O I/O 62 Voltage / Pad Type(6) Package pin # VDDE5 Fast VDDE5 Fast VDDE5 Fast VDDE5 Fast VDDE5 Fast VDDE5 Fast VDDE5 Fast VDDE5 Fast VDDE5 Fast I/O VDDE2 I/O Fast During Reset After Reset 176 208 324 — / Up — / Up — — AA9 — / Up — / Up — — Y6 — / Up — / Up — — Y7 — / Up — / Up — — Y8 — / Up — / Up — — W9 — / Up — / Up — — W10 — / Up — / Up — — Y10 — / Up — / Up — — W11 — / Up — / Up — — Y11 — / Up — / Up — — P3 Pinout and signal description 46/157 DATA7 I/O (5) SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) BDIP External burst data in progress P 01 GPIO[63] GPIO G 00 WE[0]/BE[0] External write/byte enable P 01 GPIO[64] GPIO G 00 WE[1]/BE[1] External write/byte enable P 01 GPIO[65] GPIO G 00 OE External output enable P 01 GPIO[68] GPIO G 00 External transfer start P 001 Address latch enable A1 010 GPIO[69] GPIO[69] G 000 TA External transfer acknowledge P 001 TS(8) External transfer start A1 010 GPIO[70] GPIO G 000 64 65 68 Type O VDDE2 I/O Fast O VDDE2 I/O Fast O VDDE2 I/O Fast O VDDE2 I/O Fast I/O 69 O I/O I/O 70 Voltage / Pad Type(6) O I/O Package pin # VDDE2 Fast VDDE2 Fast During Reset After Reset 176 208 324 — / Up — / Up — — M1 — / Up — / Up — — N4 — / Up — / Up — — N3 — / Up — / Up — — AB9 — / Up — / Up — — T4 — / Up — / Up — — R4 —/— — — — —/— — — — —/— — — — —/— — — — —/— — — — Calibration Bus CAL_CS0 Calibration chip select P 01 CAL_CS2 Calibration chip select P 001 CAL_ADDR[10] Calibration address bus A 010 CAL_WE[2]/BE[2] Calibration write/byte enable A2 100 CAL_CS3 Calibration chip select P 001 CAL_ADDR[11] Calibration address bus A 010 CAL_WE[3]/BE[3] Calibration write/byte enable A2 100 CAL_ADDR[12] Calibration address bus P 01 CAL_WE[2]/BE[2] Calibration write/byte enable A 10 CAL_ADDR[13] Calibration address bus P 01 CAL_WE[3]/BE[3] Calibration write/byte enable A 10 336 O 338 I/O O O O 339 I/O O 340 340 VDDE12 Fast VDDE12 Fast VDDE12 Fast I/O VDDE12 O Fast I/O VDDE12 O Fast SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 TS ALE 63 I/O (5) Pinout and signal description 47/157 Table 4. SPC564A80 signal properties (continued) Name Function(1) P A G(2) PCR PA Field Status(7) PCR (4) (3) Doc ID 15399 Rev 9 Calibration address bus P 01 CAL_DATA[31] Calibration data bus A 10 CAL_ADDR[15] Calibration address bus P 01 CAL_ALE Calibration address latch enable A1 10 CAL_ADDR[16] Calibration address bus P 01 CAL_DATA[16] Calibration data bus A 10 CAL_ADDR[17] Calibration address bus P 01 CAL_DATA[17] Calibration data bus A 10 CAL_ADDR[18] Calibration address bus P 01 CAL_DATA[18] Calibration data bus A 10 CAL_ADDR[19] Calibration address bus P 01 CAL_DATA[19] Calibration data bus A 10 CAL_ADDR[20] Calibration address bus P 01 CAL_DATA[20] Calibration data bus A 10 CAL_ADDR[21] Calibration address bus P 01 CAL_DATA[21] Calibration data bus A 10 CAL_ADDR[22] Calibration address bus P 01 CAL_DATA[22] Calibration data bus A 10 CAL_ADDR[23] Calibration address bus P 01 CAL_DATA[23] Calibration data bus A 10 CAL_ADDR[24] Calibration address bus P 01 CAL_DATA[24] Calibration data bus A 10 CAL_ADDR[25] Calibration address bus P 01 CAL_DATA[25] Calibration data bus A 10 CAL_ADDR[26] Calibration address bus P 01 CAL_DATA[26] Calibration data bus A 10 CAL_ADDR[27] Calibration address bus P 01 CAL_DATA[27] Calibration data bus A 10 340 340 345 345 345 345 345 345 345 345 345 345 345 345 Type Voltage / Pad Type(6) Package pin # I/O VDDE12 I/O Fast I/O VDDE12 O Fast I/O VDDE12 I/O Fast I/O VDDE12 I/O Fast I/O VDDE12 I/O Fast I/O VDDE12 I/O Fast I/O VDDE12 I/O Fast I/O VDDE12 I/O Fast I/O VDDE12 I/O Fast I/O VDDE12 I/O Fast I/O VDDE12 I/O Fast I/O VDDE12 I/O Fast I/O VDDE12 I/O Fast I/O VDDE12 I/O Fast During Reset After 176 208 324 —/— — — — —/— — — — —/— — — — —/— — — — —/— — — — —/— — — — —/— — — — —/— — — — —/— — — — —/— — — — —/— — — — —/— — — — —/— — — — —/— — — — Reset Pinout and signal description 48/157 CAL_ADDR[14] I/O (5) SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. SPC564A80 signal properties (continued) Name Function(1) P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type Calibration address bus P 01 CAL_DATA[28] Calibration data bus A 10 CAL_ADDR[29] Calibration address bus P 01 CAL_DATA[29] Calibration data bus A 10 CAL_ADDR[30] Calibration address bus P 01 CAL_DATA[30] Calibration data bus A 10 CAL_DATA[0] Calibration data bus P 01 341 I/O CAL_DATA[1] Calibration data bus P 01 341 I/O CAL_DATA[2] Calibration data bus P 01 341 I/O CAL_DATA[3] Calibration data bus P 01 341 I/O CAL_DATA[4] Calibration data bus P 01 341 I/O CAL_DATA[5] Calibration data bus P 01 341 I/O CAL_DATA[6] Calibration data bus P 01 341 I/O CAL_DATA[7] Calibration data bus P 01 341 I/O CAL_DATA[8] Calibration data bus P 01 341 I/O CAL_DATA[9] Calibration data bus P 01 341 I/O CAL_DATA[10] Calibration data bus P 01 341 I/O 345 345 345 Voltage / Pad Type(6) I/O VDDE12 I/O Fast I/O VDDE12 I/O Fast I/O VDDE12 I/O Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast During Reset After 176 208 324 —/— — — — —/— — — — —/— — — — — / Up — / Up — — — — / Up — / Up — — — — / Up — / Up — — — — / Up — / Up — — — — / Up — / Up — — — — / Up — / Up — — — — / Up — / Up — — — — / Up — / Up — — — — / Up — / Up — — — — / Up — / Up — — — — / Up — / Up — — — Reset SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 CAL_ADDR[28] Package pin # (5) Pinout and signal description 49/157 Table 4. SPC564A80 signal properties (continued) Name Function(1) P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type Doc ID 15399 Rev 9 Calibration data bus P 01 341 I/O CAL_DATA[12] Calibration data bus P 01 341 I/O CAL_DATA[13] Calibration data bus P 01 341 I/O CAL_DATA[14] Calibration data bus P 01 341 I/O CAL_DATA[15] Calibration data bus P 01 341 I/O CAL_RD_WR Calibration read/write enable P 01 342 O CAL_WE[0]/BE[0] Calibration write/byte enable P 01 342 O CAL_WE[1]/BE[1] Calibration write/byte enable P 01 342 O CAL_OE Calibration output enable P 01 342 O CAL_TS Calibration transfer start P 01 CAL_ALE Address Latch Enable A 10 CAL_MDO[4] Calibration Nexus Message Data Out P 01 — O CAL_MDO[5] Calibration Nexus Message Data Out P 01 — O CAL_MDO[6] Calibration Nexus Message Data Out P 01 — O CAL_MDO[7] Calibration Nexus Message Data Out P 01 — O 343 Voltage / Pad Type(6) VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast During Reset — — / Up — / Up — — — — / Up — / Up — — — — / Up — / Up — — — — / Up — / Up — — — —/— — — — —/— — — — —/— — — — —/— — — — —/— — — — — CAL_MDO[4] / — — — — — CAL_MDO[5] / — — — — — CAL_MDO[6] / — — — — — CAL_MDO[7] / — — — — VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast 324 — Fast Fast 208 — VDDE12 VDDE12 176 — / Up Fast O Reset — / Up VDDE12 O After Pinout and signal description 50/157 CAL_DATA[11] Package pin # (5) SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type CAL_MDO[8] Calibration Nexus Message Data Out P 01 — O CAL_MDO[9] Calibration Nexus Message Data Out P 01 — O CAL_MDO[10] Calibration Nexus Message Data Out P 01 — O CAL_MDO[11] Calibration Nexus Message Data Out P 01 — O Package pin # (5) Voltage / Pad Type(6) VDDE12 Fast VDDE12 Fast VDDE12 Fast VDDE12 Fast During Reset After Reset 176 208 324 — CAL_MDO[8] / — — — — — CAL_MDO[9] / — — — — — CAL_MDO[10] / — — — — — CAL_MDO[11] / — — — — — / Up EVTI / Up 116 E15 F21 — EVTO / — 120 D15 F22 — MCKO / — 14 F15 G20 — MDO[0] / — 17 A14 B20 — MDO[1] / — 18 B14 C19 — MDO[2] / — 19 A13 C18 — MDO[3] / — 20 B13 D18 — —/— 126 P10 B19 Pinout and signal description 51/157 Table 4. NEXUS Nexus event in P 01 231 I MultiV(12),(14) EVTO Nexus event out P 01 227 O MultiV(12),(14), VDDEH7 (15) MCKO Nexus message clock out P — MDO0(16) Nexus message data out P MDO1(16) Nexus message data out MDO2(16) 219(11 ) O 01 220 O P 01 221 O Nexus message data out P 01 222 O MDO3(16) Nexus message data out P 01 223 O MDO4(16) Nexus message data out P 01 ETPUA2_O(8) eTPU A channel (output only) A1 10 GPIO[75] GPIO G 00 O 75 O I/O VRC33 Fast VRC33 Fast VRC33 Fast VRC33 Fast VRC33 Fast VDDEH7 MultiV(12),(14) SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 VDDEH7 EVTI SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type Voltage / Pad Type(6) Doc ID 15399 Rev 9 Nexus message data out P 01 ETPUA4_O(8) eTPU A channel (output only) A1 10 GPIO[76] GPIO G 00 MDO6(16) Nexus message data out P 01 ETPUA13_O(8) eTPU A channel (output only) A1 10 GPIO[77] GPIO G 00 MDO7(16) Nexus message data out P 01 ETPUA19_O(8) eTPU A channel (output only) A1 10 GPIO[78] GPIO G 00 MDO8(16) Nexus message data out P 01 ETPUA21_O(8) eTPU A channel (output only) A1 10 GPIO[79] GPIO G 00 MDO9(16) Nexus message data out P 01 ETPUA25_O(8) eTPU A channel (output only) A1 10 GPIO[80] GPIO G 00 MDO10(16) Nexus message data out P 01 ETPUA27_O(8) eTPU A channel (output only) A1 10 GPIO[81] GPIO G 00 MDO11(16) Nexus message data out P 01 ETPUA29_O(8) eTPU A channel (output only) A1 10 GPIO[82] GPIO[82] G 00 MSEO[0](16) Nexus message start/end out P 01 224 O MultiV(12),(14) MSEO[1](16) Nexus message start/end out P 01 225 O MultiV(12),(14) RDY Nexus ready output P 01 226 O MultiV(12),(14) O O I/O VDDEH7 MultiV(12),(14) O 77 O I/O VDDEH7 MultiV(12),(14) O 78 O I/O VDDEH7 MultiV(12),(14) O 79 O I/O VDDEH7 MultiV(12),(14) O 80 O I/O VDDEH7 MultiV(12),(14) O 81 O I/O VDDEH7 MultiV(12),(14) O 82 O I/O VDDEH7 MultiV(12),(14) VDDEH7 VDDEH7 VDDEH7 52/157 JTAG During Reset After Reset 176 208 324 — —/— 129 T10 C17 — —/— 135 T11 D17 — —/— 136 N11 B18 — —/— 137 P11 A19 — —/— 139 T7 B17 — —/— 134 R10 A18 — —/— 124 P9 A17 — MSEO[0] / — 118 C15 G21 — MSEO[1] / — 117 E16 G22 — — — — G19 Pinout and signal description MDO5(16) 76 Package pin # (5) SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type Package pin # (5) Voltage / Pad Type(6) VDDEH7 JTAG test clock input P 01 — I MultiV(12) TDI JTAG test data input P 01 232 I MultiV(12) TDO JTAG test data output P 01 228 O MultiV(12) TMS JTAG test mode select input P 01 — I JCOMP JTAG TAP controller enable P 01 — I MultiV(12) TCK / Down After Reset 176 208 324 TCK / Down 128 C16 D21 TDI / Up TDI / Up 130 E14 D22 TDO / Up TDO / Up 123 F14 E21 MultiV(12) TMS / Up TMS / Up 131 D14 E20 VDDEH7 JCOMP / Down JCOMP / Down 121 F16 F20 — / Up — / Up 81 P12 Y17 — / Up — / Up 82 R12 AA18 — / Up — / Up 88 T12 AB18 — / Up — / Up 89 R13 AB19 — / Up — / Up 101 K13 P19 VDDEH7 VDDEH7 VDDEH7 FlexCAN CAN_A_TX FlexCAN A TX P 01 SCI_A_TX eSCI A TX A1 10 GPIO[83] GPIO G 00 CAN_A_RX FlexCAN A RX P 01 SCI_A_RX eSCI A RX A1 10 GPIO[84] GPIO G 00 I/O CAN_B_TX FlexCAN B TX P 001 O DSPI_C_PCS[3] DSPI C peripheral chip select A1 010 SCI_C_TX eSCI C TX A2 100 GPIO[85] GPIO G 000 CAN_B_RX FlexCAN B RX P 001 I DSPI_C_PCS[4] DSPI C peripheral chip select A1 010 O VDDEH6 SCI_C_RX eSCI C RX A2 100 I Slow GPIO[86] GPIO G 000 CAN_C_TX FlexCAN C TX P 01 DSPI_D_PCS[3] DSPI D peripheral chip select A1 10 GPIO[87] GPIO G 00 O 83 O I/O I 84 85 I VDDEH6 Slow VDDEH6 Slow O VDDEH6 O Slow I/O 86 I/O O 87 O I/O VDDEH6 Medium SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 TCK During Reset Pinout and signal description 53/157 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) CAN_C_RX FlexCAN C RX P 01 DSPI_D_PCS[4] DSPI D peripheral chip select A1 10 GPIO[88] GPIO G 00 I/O Type Voltage / Pad Type(6) I 88 Package pin # (5) VDDEH6 O Slow I/O During Reset After Reset 176 208 324 — / Up 98 L14 R20 — / Up — / Up 100 J14 N20 — / Up — / Up 99 K14 P20 — / Up — / Up 87 L13 R21 — / Up — / Up 84 M13 T19 — / Up — / Up — — W18 — / Up — / Up — — Y19 — / Up — / Up — — L22 — / Up — / Up — — L21 eSCI Doc ID 15399 Rev 9 SCI_A_TX eSCI A TX P 01 EMIOS13(8) eMIOS channel A1 10 GPIO[89] GPIO G 00 SCI_A_RX eSCI A RX P 01 EMIOS15(8) eMIOS channel A1 10 GPIO[90] GPIO G 00 SCI_B_TX eSCI B TX P 01 DSPI_D_PCS[1] DSPI D peripheral chip select A1 10 GPIO[91] GPIO G 00 SCI_B_RX eSCI B RX P 01 DSPI_D_PCS[5] DSPI D peripheral chip select A1 10 GPIO[92] GPIO G 00 SCI_C_TX eSCI C TX P 01 GPIO[244] GPIO G 00 SCI_C_RX eSCI C RX P 01 GPIO[245] GPIO G 00 O 89 VDDEH6 O Medium I/O I 90 VDDEH6 O Medium I/O O 91 VDDEH6 O Medium I/O I 92 VDDEH6 O Medium I/O 244 245 O VDDEH6 I/O Medium I VDDEH6 I/O Medium DSPI (17) — — — DSPI_C_PCS[1] DSPI C peripheral chip select A1 10 GPIO[93] GPIO G 00 DSPI_A_SIN(17) — — — DSPI_C_PCS[2] DSPI C peripheral chip select A1 10 GPIO[94] GPIO G 00 DSPI_A_SCK — 93 O I/O — 94 O 54/157 I/O VDDEH7 Medium VDDEH7 Medium Pinout and signal description — / Up SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) — — — DSPI_C_PCS[5] DSPI C peripheral chip select A1 10 GPIO[95] GPIO G 00 DSPI_A_PCS[0](17) — — — DSPI_D_PCS[2] DSPI D peripheral chip select A1 10 GPIO[96] GPIO G 00 DSPI_A_PCS[1](17) — — — DSPI_B_PCS[2] DSPI B peripheral chip select A1 10 GPIO[97] GPIO G 00 CS[2] — — — DSPI_D_SCK SPI clock pin for DSPI module A1 10 GPIO[98] GPIO G 00 CS[3] — — — DSPI_D_SIN DSPI D data input A1 10 GPIO[99] GPIO G 00 DSPI_A_PCS[4](17) — — — DSPI_D_SOUT DSPI D data output A1 10 GPIO[100] GPIO G 00 DSPI_A_PCS[5](17) — — — DSPI_B_PCS[3] DSPI B peripheral chip select A1 10 GPIO[101] GPIO G 00 DSPI_B_SCK SPI clock pin for DSPI module P 01 DSPI_C_PCS[1] DSPI C peripheral chip select A1 10 GPIO[102] GPIO G 00 DSPI_B_SIN DSPI B data input P 01 DSPI_C_PCS[2] DSPI C peripheral chip select A1 10 GPIO[103] GPIO G 00 Type — 95 O I/O — 96 O I/O — 97 O I/O — 98 I/O I/O — 99 I I/O 100 101 Medium VDDEH7 Medium VDDEH7 Medium VDDEH7 Medium VDDEH7 Medium O VDDEH7 Medium O VDDEH7 I/O Medium O I/O I 103 VDDEH7 I/O I/O 102 Voltage / Pad Type(6) O I/O Package pin # VDDEH6 Medium VDDEH6 Medium During Reset After Reset 176 208 324 — / Up — / Up — — L20 — / Up — / Up — — M20 — / Up — / Up — — M19 — / Up — / Up 141 J15 M21 — / Up — / Up 142 H13 K19 — / Up — / Up — — N19 — / Up — / Up — — N21 — / Up — / Up 106 J16 K21 — / Up — / Up 112 G15 H22 SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 DSPI_A_SOUT(17) I/O (5) Pinout and signal description 55/157 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) Doc ID 15399 Rev 9 DSPI B data output P 01 DSPI_C_PCS[5] DSPI C peripheral chip select A1 10 GPIO[104] GPIO G 00 DSPI_B_PCS[0] DSPI B peripheral chip select P 01 DSPI_D_PCS[2] DSPI D peripheral chip select A1 10 GPIO[105] GPIO G 00 DSPI_B_PCS[1] DSPI B peripheral chip select P 01 DSPI_D_PCS[0] DSPI D peripheral chip select A1 10 GPIO[106] GPIO G 00 DSPI_B_PCS[2] DSPI B peripheral chip select P 01 DSPI_C_SOUT DSPI C data output A1 10 GPIO[107] GPIO G 00 DSPI_B_PCS[3] DSPI B peripheral chip select P 01 DSPI_C_SIN DSPI C data input A1 10 GPIO[108] GPIO G 00 DSPI_B_PCS[4] DSPI B peripheral chip select P 01 DSPI_C_SCK SPI clock pin for DSPI module A1 10 GPIO[109] GPIO G 00 DSPI_B_PCS[5] DSPI B peripheral chip select P 01 DSPI_C_PCS[0] DSPI C peripheral chip select A1 10 GPIO[110] GPIO G 00 Type O 104 O I/O I/O 105 O I/O O 106 I/O I/O O 107 O I/O O 108 I I/O O 109 I/O I/O O 110 I/O I/O Voltage / Pad Type(6) Package pin # VDDEH6 Medium VDDEH6 Medium VDDEH6 Medium VDDEH6 Medium VDDEH6 Medium VDDEH6 Medium VDDEH6 Medium During Reset After Reset 176 208 324 — / Up — / Up 113 G13 J19 — / Up — / Up 111 G16 J21 — / Up — / Up 109 H16 J22 — / Up — / Up 107 H15 K22 — / Up — / Up 114 G14 J20 — / Up — / Up 105 H14 K20 — / Up — / Up 104 J13 L19 I/— AN[0] / — 172 B5 B8 I/— AN[1] / — 171 A6 A8 I/— AN[2] / — 170 D6 D10 eQADC (18) Single Ended Analog Input DAN0+ Positive Terminal Diff. Input AN1(18) Single Ended Analog Input DAN0- Negative Terminal Diff. Input AN2(18) Single Ended Analog Input DAN1+ Positive Terminal Diff. Input AN0 56/157 P — — P — — P — — I VDDA I Analog I VDDA I Analog I VDDA I Analog Pinout and signal description DSPI_B_SOUT I/O (5) SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. SPC564A80 signal properties (continued) Name Function(1) Single Ended Analog Input DAN1- Negative Terminal Diff. Input AN4(18) Single Ended Analog Input DAN2+ Positive Terminal Diff. Input AN5(18) Single Ended Analog Input DAN2- Negative Terminal Diff. Input AN6(18) Single Ended Analog Input DAN3+ Positive Terminal Diff. Input AN7(18) Single Ended Analog Input DAN3- Negative Terminal Diff. Input AN8 Single-ended Analog Input ANW Multiplexed Analog Input AN9 Single-ended Analog Input ANX External Multiplexed Analog Input AN10 Single-ended Analog Input ANY Multiplexed Analog Input AN11 Single-ended Analog Input ANZ Multiplexed Analog Input AN12 - SDS MA0 PCR PA Field Status(7) PCR (4) (3) I/O Type Voltage / Pad Type(6) I VDDA I Analog P — — P — — P — — P — — P — — P 01 — P 01 — P 01 — I P 01 — I Single-ended Analog Input P 001 I MUX Address 0 A1 010 O VDDEH7(19) eTPU A channel (output only) A2 100 O Medium SDS eQADC Serial Data Select G 000 AN13 - SDO Single-ended Analog Input P 001 I MA1 MUX Address 1 A1 010 O VDDEH7(19) eTPU A channel (output only) A2 100 O Medium eQADC Serial Data Out G 000 ETPUA19_O ETPUA21_O SDO (8) (8) 215 I VDDA I Analog I VDDA I Analog I VDDA I Analog I VDDA I Analog I Package pin # (5) VDDA Analog I VDDA I Analog VDDA Analog VDDA Analog During Reset After Reset 176 208 324 I/— AN[3] / — 169 C7 C9 I/— AN[4] / — 168 B6 B9 I/— AN[5] / — 167 A7 A9 I/— AN[6] / — 166 D7 D11 I/— AN[7] / — 165 C8 C10 I/— AN[8] / — 9 B3 D6 I/— AN[9] / — 5 A2 D7 I/— AN[10] / — I/— AN[11] / — 4 A3 A5 I/— AN[12] / — 148 A12 A16 I/— AN[13] / — 147 B12 B16 — — D8 I/O 216 O SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 AN3(18) P A G(2) Pinout and signal description 57/157 Table 4. SPC564A80 signal properties (continued) Name Function(1) P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type Voltage / Pad Type(6) Single-ended Analog Input P 001 I MA2 MUX Address 2 A1 010 O VDDEH7(19) eTPU A channel (output only) A2 100 O Medium SDI eQADC Serial Data In G 000 AN15 - FCK Single-ended Analog Input P 001 FCK eQADC Free Running Clock A1 010 ETPUA29_O(8) eTPU A channel (output only) A2 100 AN16 Single-ended Analog Input P — — I AN17 Single-ended Analog Input P — — I AN18 Single-ended Analog Input P — — I AN19 Single-ended Analog Input P — — I AN20 Single-ended Analog Input P — — I AN21 Single-ended Analog Input P — — I AN22 Single-ended Analog Input P — — I AN23 Single-ended Analog Input P — — I AN24 Single-ended Analog Input P — — I AN25 Single-ended Analog Input P — — I ETPUA27_O 217 During Reset After Reset 176 208 324 Doc ID 15399 Rev 9 I/— AN[14] / — 146 C12 C16 I/— AN[15] / — 145 C13 D16 I/— AN[16] / — 3 C6 B7 I/— AN[17] / — 2 C4 C6 I/— AN[18] / — 1 D5 D9 I/— AN[19] / — — — B6 I/— AN[20] / — — — C7 I/— AN[21] / — 173 B4 C8 I/— AN[22] / — 161 B8 C11 I/— AN[23] / — 160 C9 B11 I/— AN[24] / — 159 D8 D12 I/— AN[25] / — 158 B9 C12 I I 218 O O VDDEH7(19) Medium VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog 58/157 Pinout and signal description AN14 - SDI (8) Package pin # (5) SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. Name SPC564A80 signal properties (continued) Function(1) P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type Single-ended Analog Input P — — I AN27 Single-ended Analog Input P — — I AN28 Single-ended Analog Input P — — I AN29 Single-ended Analog Input P — — I AN30 Single-ended Analog Input P — — I AN31 Single-ended Analog Input P — — I AN32 Single-ended Analog Input P — — I AN33 Single-ended Analog Input P — — I AN34 Single-ended Analog Input P — — I AN35 Single-ended Analog Input P — — I AN36 Single-ended Analog Input P — — I AN37 Single-ended Analog Input P — — I AN38 Single-ended Analog Input P — — I AN39 Single-ended Analog Input P — — I Voltage / Pad Type(6) VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog VDDA Analog During Reset After Reset 176 208 — 324 I/— AN[26] / — — I/— AN[27] / — 157 A10 A12 I/— AN[28] / — 156 B10 A13 I/— AN[29] / — — I/— AN[30] / — 155 D9 C13 I/— AN[31] / — 154 D10 B13 I/— AN[32] / — 153 C10 B14 I/— AN[33] / — 152 C11 C14 I/— AN[34] / — 151 C5 D14 I/— AN[35] / — 150 D11 A14 I/— AN[36] / — 174 F4 B4 I/— AN[37] / — 175 E3 A4 I/— AN[38] / — — — C5 I/— AN[39] / — 8 D2 B5 — B12 D13 SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 AN26 Package pin # (5) Pinout and signal description 59/157 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type VRH Voltage Reference High P — — I VRL Voltage Reference Low P — — I P — — I REFBYBC Reference Bypass Capacitor Input Package pin # (5) Voltage / Pad Type(6) VDDA — VDDA — VDDA Analog During Reset After Reset 176 208 324 I/— VRH 163 A8 A10 I/— VRL 162 A9 A11 I/— REFBYPC 164 B7 B10 — / Up — / Up — L4 M2 61 N3 L3 60 M3 L4 59 P2 K3 58 P1 L2 56 N2 L1 eTPU2 Doc ID 15399 Rev 9 TCRCLKA eTPU A TCR clock P 01 IRQ[7] External interrupt request A1 10 GPIO[113] GPIO G 00 I/O ETPUA0 eTPU A channel P 001 I/O ETPUA12_O(8) eTPU A channel (output only) A1 010 ETPUA19_O(8) eTPU A channel (output only) A2 100 GPIO[114] GPIO G 000 ETPUA1 eTPU A channel P 01 ETPUA13_O(8) eTPU A channel (output only) A1 10 GPIO[115] GPIO G 00 ETPUA2 eTPU A channel P 01 ETPUA14_O(8) eTPU A channel (output only) A1 10 GPIO[116] GPIO G 00 ETPUA3 eTPU A channel P 01 ETPUA15_O(8) eTPU A channel (output only) A1 10 GPIO[117] GPIO G 00 I/O ETPUA4 eTPU A channel P 0001 I/O ETPUA16_O(8) eTPU A channel (output only) A1 0010 FR_B_TX Flexray TX data channel B A3 1000 GPIO[118] GPIO G 0000 I 113 114 I VDDEH4 Slow O VDDEH4 —/ —/ O Slow WKPCFG WKPCFG SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. I/O I/O 115 O I/O I/O O I/O I/O 117 118 O —/ —/ Slow WKPCFG WKPCFG VDDEH4 —/ —/ Slow WKPCFG WKPCFG — / WKPCFG GPIO / WKPCFG VDDEH4 Slow O VDDEH4 —/ —/ O Slow WKPCFG WKPCFG I/O 60/157 Pinout and signal description 116 VDDEH4 SPC564A80 signal properties (continued) Function(1) Name ETPUA5 ETPUA17_O(8) DSPI_B_SCK_LVD SFR_B_TX_EN GPIO[119] ETPUA6 ETPUA18_O(8) DSPI_B_SCK_LVD S+ GPIO[120] ETPUA7 ETPUA19_O(8) DSPI_B_SOUT_LV DSETPUA6_O(8) GPIO[121] ETPUA8 ETPUA20_O(8) DSPI_B_SOUT_LV DS+ GPIO[122] PCR PA Field Status(7) PCR (4) (3) eTPU A channel P 0001 eTPU A channel (output only) A1 0010 LVDS negative DSPI clock A2 0100 Flexray TX data enable for ch. B A3 GPIO I/O Type Package pin # (5) Voltage / Pad Type(6) During Reset After Reset 176 208 324 I/O O VDDEH4 O Slow + 1000 O LVDS G 0000 I/O eTPU A channel P 0001 I/O eTPU A channel (output only) A1 0010 LVDS positive DSPI clock A2 0100 Flexray RX data channel B A3 GPIO 119 O VDDEH4 O Medium + 1000 I LVDS G 0000 I/O eTPU A channel P 0001 I/O eTPU A channel (output only) A1 0010 LVDS negative DSPI data out A2 0100 eTPU A channel (output only) A3 GPIO 120 O VDDEH4 O Slow + 1000 O LVDS G 0000 I/O eTPU A channel P 001 I/O eTPU A channel (output only) A1 010 LVDS positive DSPI data out A2 100 GPIO G 000 I/O I/O 121 122 O O ETPUA9 eTPU A channel P 001 ETPUA21_O(8) eTPU A channel (output only) A1 010 RCH1_B Reaction channel 1B A2 100 GPIO[123] GPIO G 000 I/O ETPUA10 eTPU A channel P 001 I/O ETPUA22_O(8) eTPU A channel (output only) A1 010 RCH1_C Reaction channel 1C A2 100 GPIO[124] GPIO G 000 123 124 VDDEH4 Slow + LVDS —/ —/ WKPCFG WKPCFG —/ —/ WKPCFG WKPCFG —/ —/ WKPCFG WKPCFG —/ —/ WKPCFG WKPCFG O VDDEH4 —/ —/ O Slow WKPCFG WKPCFG O VDDEH1 —/ —/ O Slow WKPCFG WKPCFG I/O 54 M4 K4 53 L3 J3 52 K3 K2 51 N1 K1 50 M2 J4 49 M1 H3 SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 FR_B_RX P A G(2) Pinout and signal description 61/157 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type Doc ID 15399 Rev 9 eTPU A channel P 001 ETPUA23_O(8) eTPU A channel (output only) A1 010 RCH4_B Reaction channel 4B A2 100 GPIO[125] GPIO G 000 I/O ETPUA12 eTPU A channel P 001 I/O DSPI_B_PCS[1] DSPI B peripheral chip select A1 010 RCH4_C Reaction channel 4C A2 100 GPIO[126] GPIO G 000 ETPUA13 eTPU A channel P 01 DSPI_B_PCS[3] DSPI B peripheral chip select A1 10 GPIO[127] GPIO G 00 I/O ETPUA14 eTPU A channel P 0001 I/O DSPI_B_PCS[4] DSPI B peripheral chip select A1 0010 ETPUA9_O(8) eTPU A channel (output only) A2 0100 RCH0_A Reaction channel 0A A3 1000 O GPIO[128] GPIO G 0000 I/O ETPUA15 eTPU A channel P 001 I/O DSPI_B_PCS[5] DSPI B peripheral chip select A1 010 RCH1_A Reaction channel 1A A2 100 GPIO[129] GPIO G 000 I/O ETPUA16 eTPU A channel P 001 I/O DSPI_D_PCS[1] DSPI D peripheral chip select A1 010 RCH2_A Reaction channel 2A A2 100 GPIO[130] GPIO G 000 I/O ETPUA17 eTPU A channel P 001 I/O DSPI_D_PCS[2] DSPI D peripheral chip select A1 010 RCH3_A Reaction channel 3A A2 100 GPIO[131] GPIO G 000 Voltage / Pad Type(6) During Reset After Reset 176 208 324 I/O 125 126 O VDDEH1 —/ —/ O Slow WKPCFG WKPCFG O VDDEH1 —/ —/ O Medium WKPCFG WKPCFG 48 L2 J2 47 L1 J1 46 J4 G4 42 J3 G3 40 K2 H2 39 K1 H1 38 H3 F3 I/O I/O 127 O O 128 129 130 131 O VDDEH1 —/ —/ Medium WKPCFG WKPCFG VDDEH1 —/ —/ Medium WKPCFG WKPCFG O VDDEH1 —/ —/ O Medium WKPCFG WKPCFG O VDDEH1 —/ —/ O Slow WKPCFG WKPCFG O VDDEH1 —/ —/ O Slow WKPCFG WKPCFG I/O 62/157 Pinout and signal description ETPUA11 Package pin # (5) SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type eTPU A channel P 001 DSPI_D_PCS[3] DSPI D peripheral chip select A1 010 RCH4_A Reaction channel 4A A2 100 GPIO[132] GPIO G 000 I/O ETPUA19 eTPU A channel P 001 I/O DSPI_D_PCS[4] DSPI D peripheral chip select A1 010 RCH5_A Reaction channel 5A A2 100 GPIO[133] GPIO G 000 I/O ETPUA20 eTPU A channel P 0001 I/O IRQ[8] External interrupt request A1 0010 RCH0_B Reaction channel 0B A2 0100 FR_A_TX Flexray TX data channel A A3 1000 O GPIO[134] GPIO G 0000 I/O ETPUA21 eTPU A channel P 0001 I/O IRQ[9] External interrupt request A1 0010 RCH0_C Reaction channel 0C A2 0100 FR_A_RX Flexray RX channel A A3 1000 I GPIO[135] GPIO G 0000 I/O ETPUA22 eTPU A channel P 001 I/O IRQ[10] External interrupt request A1 010 ETPUA17_O(8) eTPU A channel (output only) A2 100 GPIO[136] GPIO G 000 I/O ETPUA23 eTPU A channel P 0001 I/O IRQ[11] External interrupt request A1 0010 ETPUA21_O(8) eTPU A channel (output only) A2 0100 FR_A_TX_EN Flexray ch. A TX enable A3 1000 O GPIO[137] GPIO G 0000 I/O Voltage / Pad Type(6) During Reset After Reset 176 208 324 I/O 132 133 O VDDEH1 —/ —/ O Slow WKPCFG WKPCFG O VDDEH1 —/ —/ O Slow WKPCFG WKPCFG I 134 O I 135 136 O —/ —/ Slow WKPCFG WKPCFG VDDEH1 —/ —/ Slow WKPCFG WKPCFG I VDDEH1 —/ —/ O Slow WKPCFG WKPCFG I 137 VDDEH1 O VDDEH1 —/ —/ Slow WKPCFG WKPCFG 37 H4 F4 36 J2 G2 35 J1 G1 34 G4 E4 32 H2 F2 30 H1 F1 SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 ETPUA18 Package pin # (5) Pinout and signal description 63/157 Table 4. SPC564A80 signal properties (continued) Function(1) Name ETPUA24 IRQ[12] DSPI_C_SCK_LVD SGPIO[138] ETPUA25 IRQ[13] DSPI_C_SCK_LVD S+ GPIO[139] Doc ID 15399 Rev 9 ETPUA26 IRQ[14] DSPI_C_SOUT_LV DSGPIO[140] ETPUA27 IRQ[15] DSPI_C_SOUT_LV DS+ DSPI_B_SOUT GPIO[141] P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type eTPU A channel P 001 External interrupt request A1 010 LVDS negative DSPI clock A2 100 GPIO G 000 I/O eTPU A channel P 001 I/O External interrupt request A1 010 LVDS positive DSPI clock A2 100 GPIO G 000 I/O eTPU A channel P 001 I/O External interrupt request A1 010 LVDS negative DSPI data out A2 100 GPIO G 000 I/O eTPU A channel P 0001 I/O External interrupt request A1 0010 LVDS positive DSPI data out A2 0100 DSPI data out A3 GPIO I/O 138 139 140 I O I O I O Voltage / Pad Type(6) VDDEH1 Slow + LVDS VDDEH1 Medium + LVDS VDDEH1 Slow + LVDS VDDEH1 Slow + 1000 O LVDS G 0000 I/O I/O ETPUA28 eTPU A channel P 001 DSPI_C_PCS[1] DSPI C peripheral chip select A1 010 RCH5_B Reaction channel 5B A2 100 GPIO[142] GPIO G 000 I/O ETPUA29 eTPU A channel P 001 I/O DSPI_C_PCS[2] DSPI C peripheral chip select A1 010 RCH5_C Reaction channel 5C A2 100 GPIO[143] GPIO G 000 142 143 During Reset After Reset —/ —/ WKPCFG WKPCFG —/ —/ WKPCFG WKPCFG —/ —/ WKPCFG WKPCFG —/ —/ WKPCFG WKPCFG O VDDEH1 —/ —/ O Medium WKPCFG WKPCFG O VDDEH1 —/ —/ O Medium WKPCFG WKPCFG I/O 176 208 324 28 G1 E1 27 G3 E3 26 F3 D3 25 G2 E2 24 F1 D1 23 F2 D2 64/157 Pinout and signal description I O 141 Package pin # (5) SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type ETPUA30 eTPU A channel P 001 DSPI_C_PCS[3] DSPI C peripheral chip select A1 010 ETPUA11_O(8) eTPU A channel (output only) A2 100 GPIO[144] GPIO G 000 I/O ETPUA31 eTPU A channel P 001 I/O DSPI_C_PCS[4] DSPI C peripheral chip select A1 010 ETPUA13_O(8) eTPU A channel (output only) A2 100 GPIO[145] GPIO G 000 Package pin # (5) Voltage / Pad Type(6) During Reset After Reset 176 208 324 I/O 144 145 O VDDEH1 —/ —/ O Medium WKPCFG WKPCFG 22 E1 C1 21 E2 C2 O VDDEH1 —/ —/ O Medium WKPCFG WKPCFG — / Up — / Up 63 T4 AB10 — / Up — / Up 64 T5 AB11 — / Up — / Up 65 N7 W12 66 R6 AA11 67 R5 AB12 Pinout and signal description 65/157 Table 4. I/O eMIOS eMIOS channel P 001 ETPUA0_O(8) eTPU A channel (output only) A1 010 ETPUA25_O(8) eTPU A channel (output only) A2 100 GPIO[179] GPIO G 000 EMIOS1 eMIOS channel P 01 ETPUA1_O(8) eTPU A channel (output only) A1 10 GPIO[180] GPIO G 00 I/O EMIOS2 eMIOS channel P 001 I/O ETPUA2_O(8) eTPU A channel (output only) A1 010 RCH2_B Reaction channel 2B A2 100 GPIO[181] GPIO G 000 EMIOS3 eMIOS channel P 01 ETPUA3_O(8) eTPU A channel (output only) A1 10 GPIO[182] GPIO G 00 I/O EMIOS4 eMIOS channel P 001 I/O ETPUA4_O(8) eTPU A channel (output only) A1 010 RCH2_C Reaction channel 2C A2 100 GPIO[183] GPIO G 000 I/O 179 O VDDEH4 O Slow I/O I/O 180 181 O VDDEH4 Slow O VDDEH4 O Slow I/O I/O 182 183 O VDDEH4 —/ —/ Slow WKPCFG WKPCFG O VDDEH4 —/ —/ O Slow WKPCFG WKPCFG I/O SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 EMIOS0 SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type Doc ID 15399 Rev 9 eMIOS channel P 01 ETPUA5_O(8) eTPU A channel (output only) A1 10 GPIO[184] GPIO G 00 EMIOS6 eMIOS channel P 01 ETPUA6_O(8) eTPU A channel (output only) A1 10 GPIO[185] GPIO G 00 EMIOS7 eMIOS channel P 01 ETPUA7_O(8) eTPU A channel (output only) A1 10 GPIO[186] GPIO G 00 I/O EMIOS8 eMIOS channel P 001 I/O ETPUA8_O(8) eTPU A channel (output only) A1 010 SCI_B_TX eSCI B TX A2 100 GPIO[187] GPIO G 000 I/O EMIOS9 eMIOS channel P 001 I/O ETPUA9_O(8) eTPU A channel (output only) A1 010 SCI_B_RX eSCI B RX A2 100 GPIO[188] GPIO G 000 I/O EMIOS10 eMIOS channel P 001 I/O DSPI_D_PCS[3] DSPI D peripheral chip select A1 010 RCH3_B Reaction channel 3B A2 100 GPIO[189] GPIO G 000 I/O EMIOS11 eMIOS channel P 001 I/O DSPI_D_PCS[4] DSPI D peripheral chip select A1 010 RCH3_C Reaction channel 3C A2 100 GPIO[190] GPIO G 000 I/O EMIOS12 eMIOS channel P 001 I/O DSPI_C_SOUT DSPI C data output A1 010 ETPUA27_O(8) eTPU A channel (output only) A2 100 GPIO[191] GPIO G 000 I/O 184 O I/O I/O 185 O I/O I/O 186 187 188 189 190 191 O Voltage / Pad Type(6) During Reset After Reset 208 — — 324 VDDEH4 —/ —/ Slow WKPCFG WKPCFG — / Down — / Down 68 — / Down — / Down 69 — / Up — / Up 70 P8 W13 — / Up — / Up 71 R7 AA13 73 N8 Y13 75 R8 AB14 76 N10 W15 VDDEH4 Slow VDDEH4 Slow O VDDEH4 O Slow O VDDEH4 I Slow O VDDEH4 —/ —/ O Medium WKPCFG WKPCFG O VDDEH4 —/ —/ O Medium WKPCFG WKPCFG O VDDEH4 —/ —/ O Medium WKPCFG WKPCFG I/O 176 P7 AA12 Y12 — AB13 Pinout and signal description 66/157 EMIOS5 Package pin # (5) SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type eMIOS channel P 01 DSPI_D_SOUT DSPI D data output A1 10 GPIO[192] GPIO G 00 I/O EMIOS14 eMIOS channel P 001 I/O IRQ[0] External interrupt request A1 010 ETPUA29_O(8) eTPU A channel (output only) A2 100 GPIO[193] GPIO G 000 EMIOS15 eMIOS channel P 01 IRQ[1] External interrupt request A1 10 GPIO[194] GPIO G 00 EMIOS16 eMIOS channel P 01 GPIO[195] GPIO G 00 EMIOS17 eMIOS channel P 01 GPIO[196] GPIO G 00 EMIOS18 eMIOS channel P 01 GPIO[197] GPIO G 00 EMIOS19 eMIOS channel P 01 GPIO[198] GPIO G 00 EMIOS20 eMIOS channel P 01 GPIO[199] GPIO G 00 EMIOS21 eMIOS channel P 01 GPIO[200] GPIO G 00 EMIOS22 eMIOS channel P 01 GPIO[201] GPIO G 00 EMIOS23 eMIOS channel P 01 GPIO[202] GPIO G 00 I/O 192 193 O Voltage / Pad Type(6) During Reset After Reset VDDEH4 —/ —/ Medium WKPCFG WKPCFG — / Down I VDDEH4 O Slow 176 208 324 77 T8 AA14 — / Down 78 R9 AB15 — / Down — / Down 79 T9 Y14 — / Up — / Up — — AA15 — / Up — / Up — — Y15 — / Up — / Up — — AB16 — — AA16 — — AB17 — — W16 — — Y16 I/O I/O 194 I I/O 195 196 197 198 199 200 201 202 VDDEH4 Slow I/O VDDEH4 I/O Slow I/O VDDEH4 I/O Slow I/O VDDEH4 I/O Slow I/O VDDEH4 —/ —/ I/O Slow WKPCFG WKPCFG I/O VDDEH4 —/ —/ I/O Slow WKPCFG WKPCFG I/O VDDEH4 —/ —/ I/O Slow WKPCFG WKPCFG I/O VDDEH4 I/O Slow — / Down — / Down I/O VDDEH4 I/O Slow — / Down — / Down Clock Synthesizer 80 R11 AA17 SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 EMIOS13 Package pin # (5) Pinout and signal description 67/157 Table 4. SPC564A80 signal properties (continued) Function(1) Name P A G(2) PCR PA Field Status(7) PCR (4) (3) XTAL Crystal oscillator output P 01 EXTAL Crystal oscillator input P 01 EXTCLK External clock input A 10 CLKOUT System clock output P ENGCLK Engineering clock output P I/O Type — O — I 01 229 O 01 214 O Package pin # (5) Voltage / Pad Type(6) VDDEH6 Analog VDDEH6 Analog VDDE5 Fast VDDE5 Fast During Reset After Reset 176 208 324 — — 93 P16 V22 — — 92 N16 U22 — CLKOUT — — ENGCLK — — AA20 T14 AB21 Power / Ground Doc ID 15399 Rev 9 Voltage Regulator Supply — — I 5V I/— VDDREG 10 K16 M22 VRCCTL Voltage Regulator Control Output — — O — O/— VRCCTL 11 N14 V20 Internal regulator output — — O 3.3 V I/O / — VRC33 13 Input for external 3.3 V supply — — A15, D1, A21, B1, N6, N12 P4, W7, Y22 eQADC high reference voltage — — I 5V I/— VDDA 6 — — — — I — I/— VSSA 7 — — — — I 5V I/— VDDA0 — B11 A6 — — I — I/— VSSA0 — A11 A7 — — I 5V I/— VDDA1 — A4 C15 — — I — I/— VSSA1 — A5 A15, B15 VRC33(20) VDDA VSSA eQADC ground/low reference voltage 3.3 V VDDA0(21) eQADC high reference voltage VSSA0(22) eQADC ground/low reference VDDA1(21) eQADC high reference voltage VSSA1(22) eQADC ground/low reference VDDPLL FMPLL Supply Voltage — — I 1.2 I/— VDDPLL 91 R16 W22 VSTBY Power Supply for Standby RAM — — I 0.9 V - 6 V I/— VSTBY 12 C1 A3 voltage voltage 68/157 Pinout and signal description VDDREG SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. SPC564A80 signal properties (continued) Function(1) Name VDD VDDE12 decoupling External supply input for calibration bus interfaces External supply input for EBI interfaces PCR PA Field Status(7) PCR (4) (3) I/O Type Package pin # (5) Voltage / Pad Type(6) During Reset After Reset 176 208 324 B1, B16, C2, D3, E4, N5, P4, P13, R3, R14, T2, T15 A2, A20, B3, C4, C22, D5, V19, W5, W20, Y4, Y21, AA3, AA22, AB2 — — — M9, M10, N11, P11, W6, W8, Y5, AA4, AA6, AA10, AB3 — — I 1.2 V I/— VDD 33, 45, 62, 103, 132, 149, 176 — — I 1.8 V - 3.3 V I/— VDDE12 — — — I 1.8 V - 3.3 V I/— (24) VDDE2 — External supply input for — T13 W17, Y18, AA19, AB20 VDDE5 ENGCLK, CLKOUT and EBI signals DATA[0:15] — — I 1.8 V - 3.3 V I/— VDDE5 VDDE-EH External supply for EBI interfaces — — I 3.0 V - 5 V I/— VDDE-EH — — VDDEH1A(25) I/O Supply Input — — I 3.3 V - 5.0 V I/— VDDEH1A(25) 31 — — VDDEH1B(25) I/O Supply Input — — I 3.3 V - 5.0 V I/— VDDEH1B(25) 41 — — VDDEH1AB(25) I/O Supply Input — — I 3.3 V - 5.0 V I/— VDDEH1AB(25) — VDDEH4(26) I/O Supply Input — — I 3.3 V - 5.0 V I/— VDDEH4(26) — — — VDDEH4A(26) I/O Supply Input — — I 3.3 V - 5.0 V I/— VDDEH4A(26) 55 — — VDDEH4B(26) I/O Supply Input — — I 3.3 V - 5.0 V I/— VDDEH4B(26) 74 — — K4 R3, W2 H4 SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 VDDE2(23) Core supply for input or P A G(2) Pinout and signal description 69/157 Table 4. SPC564A80 signal properties (continued) Name Function(1) Doc ID 15399 Rev 9 VDDEH4AB(26) I/O Supply Input VDDEH6(27) I/O Supply Input VDDEH6A(27) I/O Supply Input VDDEH6B(27) I/O Supply Input VDDEH6AB(27) I/O Supply Input VDDEH7 VDDEH7A I/O Supply Input I/O Supply Input P A G(2) PCR PA Field Status(7) PCR (4) (3) I/O Type Package pin # (5) Voltage / Pad Type(6) During Reset After Reset 176 208 324 — — I 3.3 V - 5.0 V I/— VDDEH4AB(26) — — I 3.3 V - 5.0 V I/— VDDEH6(27) — — I 3.3 V - 5.0 V I/— VDDEH6A(27) — — I 3.3 V - 5.0 V I/— VDDEH6B(27) — — I 3.3 V - 5.0 V I/— VDDEH6AB(27) — F13 H19, U19 — — I 3.3 V - 5.0 V I/— VDDEH7 — D12 D15 — — I 3.3 V - 5.0 V I/— VDDEH7A — — N9 W14 — — 95 — — 110 — — 125 — SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 4. — Pinout and signal description 70/157 SPC564A80 signal properties (continued) Function(1) Name VDDEH7B Ground — — PCR PA Field Status(7) PCR (4) (3) — — I/O Type I Package pin # (5) Voltage / Pad Type(6) 3.3 V - 5.0 V I — During Reset I/— I/— After Reset VDDEH7B VSS 176 138 15, 29, 43, 57, 72, 90, 94, 96, 108, 115, 127, 133, 140 208 324 — — A1, A16, A1, A22, B2, B2, B15, B21, C3, C20, C3, C14, D4, D19, J9, D4, D13, J10, J11, J12, G7, G8, J13, K9, K10, K11, K12, G9, K13, K14, L9, G10, L10, L11, L12, H7, H8, H9, H10, L13, L14, M11, M12, J7, J8, M13, M14, N9, J9, J10, N10, N12, K7, N13, N14, P9, K8, K9, P10, P12, K10, P13, P14, M16, T21, T22, N4, N13, W4,W19, Y3, P3, P14, Y20, AA2, R2, R15, AA21, AB1, T1, T16 AB22 1. For each pin in the table, each line in the Function column is a separate function of the pin. For all I/O pins the selection of primary pin function or secondary function or GPIO is done in the SIU except where explicitly noted. See the Signal details table for a description of each signal. 2. The P/A/G column indicates the position a signal occupies in the muxing order for a pin—Primary, Alternate 1, Alternate 2, Alternate 3, or GPIO. Signals are selected by setting the PA field value in the appropriate PCR register in the SIU module. The PA field values are as follows: P - 0b0001, A1 - 0b0010, A2 - 0b0100, A3 - 0b1000, or G 0b0000. Depending on the register, the PA field size can vary in length. For PA fields having fewer than four bits, remove the appropriate number of leading zeroes from these values. 3. The Pad Configuration Register (PCR) PA field is used by software to select pin function. 4. Values in the PCR No. column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR number. For example, PCR[190] refers to the SIU register named SIU_PCR190. 5. The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3 V to 5.0 V range (10%/+5%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/- 10%). 6. See Table 5 for details on pad types. SPC564A74L7, SPC564A80B4, SPC564A80L7 Doc ID 15399 Rev 9 VSS I/O Supply Input P A G(2) Pinout and signal description 71/157 Table 4. 8. Output only. 9. When used as ETRIG, this pin must be configured as an input. For GPIO it can be configured either as an input or output. 10. Maximum frequency is 50 kHz. 11. The SIU_PCR219 register is unusual in that it controls pads for two separate device pins: GPIO[219] and MCKO. See the SPC564A80 Microcontroller Reference Manual (SIU chapter) for details. 12. Multivoltage pads are automatically configured in low swing mode when a JTAG or Nexus function is selected, otherwise they are high swing. 13. On LQFP176 and LBGA208 packages, this pin is tied low internally. 14. Nexus multivoltage pads default to 5 V operation until the Nexus module is enabled. 15. EVTO should be clamped to 3.3 V to prevent possible damage to external tools that only support 3.3 V. 16. Do not connect pin directly to a power supply or ground. 17. This signal name is used to support legacy naming. Doc ID 15399 Rev 9 18. During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the system clock propagates through the device. 19. For pins AN12-AN15, if the analog features are used the VDDEH7 input pins should be tied to VDDA because that segment must meet the VDDA specification to support analog input function. SPC564A74L7, SPC564A80B4, SPC564A80L7 7. The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. Terminology is O - output, I - input, Up weak pull up enabled, Down - weak pull down enabled, Low - output driven low, High - output driven high. A dash for the function in this column denotes that both the input and output buffer are turned off. The signal name to the left or right of the slash indicates the pin is enabled. 20. Do not use VRC33 to drive external circuits. 21. VDDA0 and VDDA1 are shorted together internally in BGA packages. In the QFP package the two pads are double bonded on one pin called VDDA. 22. VSSA0 and VSSA1 are shorted together internally in BGA packages. In the QFP package the two pads are double bonded on one pin called VSSA. 23. VDDE2 and VDDE3 are shorted together in all production packages. 24. VDDE2 and VDDE3 are shorted together in all production packages. 25. VDDEH1A, VDDEH1B, and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document. 27. VDDEH6, VDDEH6A, VDDEH6B, and VDDEH6AB are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document. 72/157 Pinout and signal description 26. VDDEH4, VDDEH4A, VDDEH4B, and VDDEH4AB are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document. SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 5. Pinout and signal description Pad types Pad Type Name I/O Voltage Range Slow pad_ssr_hv 3.0V - 5.5 V Medium pad_msr_hv 3.0 V - 5.5 V Fast pad_fc 3.0 V - 3.6 V MultiV(1),(2) pad_multv_hv 3.0 V - 5.5 V (high swing mode) 3.0 V - 3.6 V (low swing mode) Analog pad_ae_hv 0.0 - 5.5 V LVDS pad_lo_lv — 1. Multivoltage pads are automatically configured in low swing mode when a JTAG or Nexus function is selected, otherwise they are high swing. 2. VDDEH7 supply cannot be below 4.5 V when in low-swing mode. 2.5 Signal details Table 6. Signal details Signal Module or Function Description CLKOUT Clock Generation SPC564A80 clock output for the external/calibration bus interface ENGCLK Clock Generation Clock for external ASIC devices EXTAL Clock Generation Input pin for an external crystal oscillator or an external clock source based on the value driven on the PLLREF pin at reset. PLLREF is used to select whether the oscillator operates in xtal mode or external reference mode from reset. PLLREF=0 selects external reference mode. On the 324BGA package, PLLREF is bonded to the ball used for PLLCFG[0] for compatibility with previous devices . PLLREF Clock Generation Reset/Configuration For the 176-pin QFP and 208-ball BGA packages: 0: External reference clock is selected. 1: XTAL oscillator mode is selected For the 324 ball BGA package: If RSTCFG is 0: 0: External reference clock is selected. 1: XTAL oscillator mode is selected. If RSTCFG is 1, XTAL oscillator mode is selected. XTAL Clock Generation Crystal oscillator input DSPI_B_SCK_LVDSDSPI_B_SCK_LVDS+ DSPI LVDS pair used for DSPI_B TSB mode transmission DSPI_B_SOUT_LVDSDSPI_B_SOUT_LVDS+ DSPI LVDS pair used for DSPI_B TSB mode transmission Doc ID 15399 Rev 9 73/157 Pinout and signal description Table 6. SPC564A74L7, SPC564A80B4, SPC564A80L7 Signal details (continued) Signal Module or Function Description DSPI_C_SCK_LVDSDSPI_C_SCK_LVDS+ DSPI LVDS pair used for DSPI_C TSB mode transmission DSPI_C_SOUT_LVDSDSPI_C_SOUT_LVDS+ DSPI LVDS pair used for DSPI_C TSB mode transmission PCS_B[0] PCS_C[0] PCS_D[0] DSPI_B - DSPI_D Peripheral chip select when device is in master mode—slave select when used in slave mode PCS_B[1:5] PCS_C[1:5] PCS_D[1:5] DSPI_B - DSPI_D Peripheral chip select when device is in master mode—not used in slave mode SCK_B SCK_C SCK_D DSPI_B - DSPI_D DSPI clock—output when device is in master mode; input when in slave mode SIN_B SIN_C SIN_D DSPI_B - DSPI_D DSPI data in SOUT_B SOUT_C SOUT_D DSPI_B - DSPI_D DSPI data out The ADDR[10:31] signals specify the physical address of the bus transaction. ADDR[10:31] EBI The 26 address lines correspond to bits 3-31 of the EBI’s 32-bit internal address bus. ADDR[15:31] can be used as Address and Data signals when configured appropriately for a multiplexed external bus. This allows 32-bit data operations, or 16-bit data operations without using DATA[0:15] signals. ALE EBI The Address Latch Enable (ALE) signal is used to demultiplex the address from the data bus. It is asserted while the least significant 16 bits of the address are present in the multiplexed address/data bus. BDIP EBI BDIP is asserted to indicate that the master is requesting another data beat following the current one. CS[0:3] EBI CSx is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the Primary external bus. DATA[0:31] EBI The DATA[0:31] signals contain the data to be transferred for the current transaction. EBI OE is used to indicate when an external memory is permitted to drive back read data. External memories must have their data output buffers off when OE is negated. OE is only asserted for chip-select accesses. OE 74/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 6. Pinout and signal description Signal details (continued) Signal Module or Function Description EBI RD_WR indicates whether the current transaction is a read access or a write access. TA EBI TA is asserted to indicate that the slave has received the data (and completed the access) for a write cycle, or returned data for a read cycle. If the transaction is a burst read, TA is asserted for each one of the transaction beats. For write transactions, TA is only asserted once at access completion, even if more than one write data beat is transferred. TS EBI The Transfer Start signal (TS) is asserted by the SPC564A80 to indicate the start of a transfer. WE[2:3] EBI Write enables are used to enable program operations to a particular memory. WE[2:3] are only asserted for write accesses WE[0:3]/BE[0:3] EBI Write enables are used to enable program operations to a particular memory. These signals can also be used as byte enables for read and write operation by setting the WEBS bit in the appropriate EBI Base Register (EBI_BRn). WE[0:3] are only asserted for write accesses. BE[0:3] are asserted for both read and write accesses eMIOS[0:23] eMIOS eMIOS I/O channels AN[0:39] eQADC Single-ended analog inputs for analog-to-digital converter FCK eQADC eQADC free running clock for eQADC SSI. MA[0:2] eQADC These three control bits are output to enable the selection for an external Analog Mux for expansion channels. REFBYPC eQADC Bypass capacitor input SDI eQADC Serial data in SDO eQADC Serial data out SDS eQADC Serial data select VRH eQADC Voltage reference high input VRL eQADC Voltage reference low input SCI_A_RX SCI_B_RX SCI_C_RX eSCI_A - eSCI_C eSCI receive SCI_A_TX SCI_B_TX SCI_C_TX eSCI_A - eSCI_C eSCI transmit ETPU_A[0:31] eTPU eTPU I/O channel RD_WR Doc ID 15399 Rev 9 75/157 Pinout and signal description Table 6. SPC564A74L7, SPC564A80B4, SPC564A80L7 Signal details (continued) Signal Module or Function Description RCH0_[A:C] RCH1_[A:C] RCH2_[A:C] RCH3_[A:C] RCH4_[A:C] RCH5_[A:C] eTPU2 Reaction Module eTPU2 reaction channels. Used to control external actuators, e.g., solenoid control for direct injection systems and valve control in automatic transmissions TCRCLKA eTPU2 Input clock for TCR time base CAN_A_TX CAN_B_TX CAN_C_TX FlexCan_A FlexCAN_C FlexCAN transmit CAN_A_RX CAN_B_RX CAN_C_RX FlexCAN_A FlexCAN_C FlexCAN receive FR_A_RX FR_B_RX FlexRay FlexRay receive (Channels A, B) FR_A_TX_EN FR_B_TX_EN FlexRay FlexRay transmit enable (Channels A, B) FR_A_TX FR_B_TX FlexRay Flexray transmit (Channels A, B) JCOMP JTAG Enables the JTAG TAP controller. TCK JTAG Clock input for the on-chip test logic. TDI JTAG Serial test instruction and data input for the on-chip test logic. TDO JTAG Serial test data output for the on-chip test logic. TMS JTAG Controls test mode operations for the on-chip test logic. EVTI is an input that is read on the negation of RESET to enable or disable the Nexus Debug port. After reset, the EVTI pin is used to initiate program synchronization messages or generate a breakpoint. EVTI Nexus EVTO Nexus Output that provides timing to a development tool for a single watchpoint or breakpoint occurrence. MCKO Nexus MCKO is a free running clock output to the development tools which is used for timing of the MDO and MSEO signals. (1) Nexus Trace message output to development tools. This pin also indicates the status of the crystal oscillator clock following a power-on reset, when MDO[0] is driven high until the crystal oscillator clock achieves stability and is then negated. MSEO[0:1](1) Nexus Output pin—Indicates the start or end of the variable length message on the MDO pins RDY Nexus Nexus Ready Output (RDY) is an output that indicates to the development tools the data is ready to be read from or written to the Nexus read/write access registers. MDO[0:11] 76/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 6. Pinout and signal description Signal details (continued) Signal Module or Function Description Two BOOTCFG signals are implemented in SPC564A80 MCUs. The BAM program uses the BOOTCFG0 bit to determine where to read the reset configuration word, and whether to initiate a FlexCAN or eSCI boot. The BOOTCFG1 pin is sampled during the assertion of the RSTOUT signal, and the value is used to update the RSR and the BAM boot mode BOOTCFG[0:1] See the SPC564A80 Microcontroller Reference Manual for more information. SIU - Configuration The following values are for BOOTCFG[0:1}: 00:Boot from internal flash memory 01:FlexCAN/eSCI boot 10:Boot from external memory using EBI 11:Reserved Note: For the 176-pin QFP and 208-ball BGA packages BOOTCFG[0] is always 0 since the EBI interface is not available. The WKPCFG pin is applied at the assertion of the internal reset signal (assertion of RSTOUT), and is sampled 4 clock cycles before the negation of the RSTOUT pin. WKPCFG The value is used to configure whether the eTPU and eMIOS pins are connected to internal weak pull up or weak pull down devices after reset. The value latched on the WKPCFG pin at reset is stored in the Reset Status Register (RSR), and is updated for all reset sources except the Debug Port Reset and Software External Reset. SIU - Configuration 0:Weak pulldown applied to eTPU and eMIOS pins at reset 1:Weak pullup applied to eTPU and eMIOS pins at reset. ETRIG[2:3] SIU - eQADC Triggers External signal eTRIGx triggers eQADC CFIFOx GPIO[206] ETRIG0 (Input) SIU - eQADC Triggers External signal eTRIGx triggers eQADC CFIFOx GPIO[207] ETRIG1 (Input) SIU - eQADC Triggers External signal eTRIGx triggers eQADC CFIFOx Doc ID 15399 Rev 9 77/157 Pinout and signal description Table 6. SPC564A74L7, SPC564A80B4, SPC564A80L7 Signal details (continued) Signal Module or Function Description The IRQ[0:15] pins connect to the SIU IRQ inputs. IMUX Select Register 1 is used to select the IRQ[0:15] pins as inputs to the IRQs. IRQ[0:5] IRQ[7:15] SIU - External Interrupts NMI SIU - External Interrupts GPIO[0:3] GPIO[8:43] GPIO[62:65] GPIO[68:70] GPIO[75:145] GPIO[179:204] GPIO[208:213] GPIO[219] GPIO[244:245] See the SPC564A80 Microcontroller Reference Manual for more information. Non-Maskable Interrupt Configurable general purpose I/O pins. Each GPIO input and output is separately controlled by an 8-bit input (GPDI) or output (GPDO) register. Additionally, each GPIO pins is configured using a dedicated SIU_PCR register. SIU - GPIO The GPIO pins are generally multiplexed with other I/O pin functions. See The SPC564A80 Microcontroller Reference Manual for more information. – The RESET pin is an active low input. The RESET pin is asserted by an external device during a power-on or external reset. The internal reset signal asserts only if the RESET pin asserts for 10 clock cycles. Assertion of the RESET pin while the device is in reset causes the reset cycle to start over. RESET SIU - Reset The RESET pin has a glitch detector which detects spikes greater than two clock cycles in duration that fall below the switch point of the input buffer logic of the VDDEH input pins. The switch point lies between the maximum VIL and minimum VIH specifications for the VDDEH input pins. Used to enable or disable the PLLREF and the BOOTCFG[0:1] configuration signals. RSTCFG SIU - Reset 0:Get configuration information from BOOTCFG[0:1] and PLLREF 1:Use default configuration of booting from internal flash with crystal clock source For the 176-pin QFP and 208-ball BGA packages RSTCFG is always 0, so PLLREF and BOOTCFG signals are used. RSTOUT SIU - Reset The RSTOUT pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven to the low state by the MCU for all internal and external reset sources. There is a delay between initiation of the reset and the assertion of the RSTOUT pin. 1. Do not connect pin directly to a power supply or ground. 78/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 7. Pinout and signal description Power/ground segmentation Power Segment Voltage VDDE2 1.8 V - 3.3 V CS0, CS1, CS2, CS3,RD_WR, BDIP, WE0, WE1, OE, TS, TA VDDE3 1.8 V - 3.3 V ADDR12, ADDR13, ADDR14, ADDR15 VDDE5 1.8 V - 3.3 V DATA0, DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7, DATA8, DATA9, DATA10, DATA11, DATA12, DATA13, DATA14, DATA15, CLKOUT, ENGCLK VDDE12 1.8 V - 3.3 V CAL_CS0, CAL_CS2, CAL_CS3 CAL_ADDR12, CAL_ADDR13, CAL_ADDR14, CAL_ADDR15, CAL_ADDR16, CAL_ADDR17, CAL_ADDR18, CAL_ADDR19, CAL_ADDR20, CAL_ADDR21, CAL_ADDR22, CAL_ADDR23, CAL_ADDR24, CAL_ADDR25, CAL_ADDR26, CAL_ADDR27, CAL_ADDR28, CAL_ADDR29, CAL_ADDR30, CAL_DATA0, CAL_DATA1, CAL_DATA2, CAL_DATA3, CAL_DATA4, CAL_DATA5, CAL_DATA6, CAL_DATA7, CAL_DATA8, CAL_DATA9, CAL_DATA10, CAL_DATA11, CAL_DATA12, CAL_DATA13, CAL_DATA14, CAL_DATA15, CAL_RD_WR, CAL_WE0, CAL_WE1, CAL_OE, CAL_TS VDDE-EH 3.0 V - 5 V ADDR16, ADDR17, ADDR18, ADDR19, ADDR20, ADDR21, ADDR22, ADDR23, ADDR24, ADDR25, ADDR26, ADDR27, ADDR28, ADDR29, ADDR30, ADDR31 3.3 V - 5.0 V ETPUA10, ETPUA11, ETPUA12, ETPUA13, ETPUA14, ETPUA15, ETPUA16, ETPUA17, ETPUA18, ETPUA19, ETPUA20, ETPUA21, ETPUA22, ETPUA23, ETPUA24, ETPUA25, ETPUA26, ETPUA27, ETPUA28, ETPUA29, ETPUA30, ETPUA31 3.3 V - 5.0 V EMIOS0, EMIOS1, EMIOS2, EMIOS3, EMIOS4, EMIOS5, EMIOS6, EMIOS7, EMIOS8, EMIOS9, EMIOS10, EMIOS11, EMIOS12, EMIOS13, EMIOS14, EMIOS15, EMIOS16, EMIOS17, EMIOS18, EMIOS19, EMIOS20, EMIOS21, EMIOS22, EMIOS23, TCRCLKA, ETPUA0, ETPUA1, ETPUA2, ETPUA3, ETPUA4, ETPUA5, ETPUA6, ETPUA7, ETPUA8, ETPUA9, ETPUA0 3.3 V - 5.0 V RESET, RSTOUT, PLLREF, PLLCFG1, RSTCFG, BOOTCFG0, BOOTCFG1, WKPCFG, CAN_A_TX, CAN_A_RX, CAN_B_TX, CAN_B_RX, CAN_C_TX, CAN_C_RX, SCI_A_TX, SCI_A_RX, SCI_B_TX, SCI_C_RX, DSPI_B_SCK, DSPI_B_SIN, DSPI_B_SOUT, DSPI_B_PCS[0], DSPI_B_PCS[1], DSPI_B_PCS[2], DSPI_B_PCS[3], DSPI_B_PCS[4], DSPI_B_PCS[5], SCI_B_RX, SCI_C_TX, EXTAL, XTAL 3.3 V - 5.0 V EMIOS14, EMIOS 15, GPIO98, GPIO99, GPIO203, GPIO204, GPIO206, GPIO207, GPIO219, EVTI, EVTO, MDO4, MDO5, MDO6, MDO7, MDO8, MDO9, MDO10, MDO11, MSEO0, MSEO1, RDY, TCK, TDI, TDO, TMS, JCOMP, DSPI_A_SCK, DSPI_A_SIN, DSPI_A_SOUT, DSPI_A_PCS[0], DSPI_A_PCS[1], DSPI_A_PCS[4], DSPI_A_PCS[5], AN12-SDS, AN13-SDO, AN14SDI, AN15-FCK VDDEH1 VDDEH4 VDDEH6 VDDEH7 VDDA 5V VRC33(1) 3.3 V I/O Pins Powered by Segment AN0, AN1, AN2, AN3, AN4, AN5, AN6, AN7, AN8, AN9, AN10, AN11, AN16, AN17, AN18, AN19, AN20, AN21, AN22, AN23, AN24, AN25, AN26, AN27, AN28, AN29, AN30, AN31, AN32, AN33, AN34, AN35, AN36, AN37, AN38, AN39, VRH, VRL, REFBYBC MCKO, MDO0, MDO1, MDO2, MDO3 Doc ID 15399 Rev 9 79/157 Pinout and signal description Table 7. SPC564A74L7, SPC564A80B4, SPC564A80L7 Power/ground segmentation (continued) Power Segment Voltage I/O Pins Powered by Segment Other Power Segments VDDREG 5V — VRCCTL — — VDDPLL 1.2 V — 0.95–1.2 V (unregulated mode) — 2.0–5.5 V (regulated mode) — — — VSTBY VSS 1. Do not use VRC33 to drive external circuits. 80/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 3 Electrical characteristics Electrical characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the SPC564A80 series of MCUs. The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column. 3.1 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 8 are used and the parameters are tagged accordingly in the tables where appropriate. Table 8. Parameter classifications Classification tag Note: Tag description P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. The classification is shown in the column labeled “C” in the parameter tables where appropriate. Doc ID 15399 Rev 9 81/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 3.2 Maximum ratings Table 9. Absolute maximum ratings(1) Value Symbol Parameter Conditions Unit min max VDD SR 1.2 V core supply voltage(2) –0.3 1.32 V VFLASH SR Flash core voltage(3),(4) –0.3 3.6 V (5) VSTBY SR SRAM standby voltage –0.3 6 V VDDPLL SR Clock synthesizer voltage –0.3 1.32 V VRC33 SR Voltage regulator control input voltage(4) –0.3 3.6 V VDDA SR Analog supply voltage(5) –0.3 5.5 V VDDE SR I/O supply voltage(4),(6) –0.3 3.6 V VDDEH SR I/O supply voltage(5) –0.3 5.5 V VDDEH powered I/O pads –1.0(8) VDDEH + 0.3 V(9) VDDE powered I/O pads –1.0(10) VDDE + 0.3 V(10) VDDA powered I/O pads –1.0 5.5 VIN SR DC input voltage(7) Reference to VSSA V VDDREG SR Voltage regulator supply voltage –0.3 5.5 V VRH SR Analog reference high voltage Reference to VRL –0.3 5.5 V VSS – VSSA SR VSS differential voltage –0.1 0.1 V VRH – VRL SR VREF differential voltage –0.3 5.5 V VRL – VSSA SR VRL to VSSA differential voltage –0.3 0.3 V VSSPLL – VSS SR VSSPLL to VSS differential voltage –0.1 0.1 V IMAXD SR Maximum DC digital input current(11) Per pin, applies to all digital pins –3 3 mA IMAXA SR Maximum DC analog input current(12) Per pin, applies to all analog pins — 5 mA 82/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 9. Electrical characteristics Absolute maximum ratings(1) (continued) Value Symbol Parameter Conditions Unit min max TJ SR Maximum operating temperature range - die junction temperature –40.0 150.0 o C TSTG SR Storage temperature range –55.0 150.0 o C TSDR SR Maximum solder temperature(13) — 260.0 oC MSL SR Moisture sensitivity level(14) — 3 1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2. Allowed 2 V for 10 hours cumulative time, remaining time at 1.2 V +10%. 3. The VFLASH supply is connected to VRC33 in the package substrate. This specification applies to calibration package devices only. 4. Allowed 5.3 V for 10 hours cumulative time, remaining time at 3.3 V +10%. 5. Allowed 5.9 V for 10 hours cumulative time, remaining time at 5 V +10%. 6. All functional non-supply I/O pins are clamped to VSS and VDDE, or VDDEH. 7. AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration). 8. Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met. 9. Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDEH supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage specifications. 10. Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications. 11. Total injection current for all pins (including both digital and analog) must not exceed 25 mA. 12. Total injection current for all analog input pins must not exceed 15 mA. 13. Solder profile per IPC/JEDEC J-STD-020D. 14. Moisture sensitivity per JEDEC test method A112. 3.3 Thermal characteristics Table 10. Thermal characteristics for 176-pin QFP(1) Symbol C Parameter Conditions Value Unit Single layer board - 1s 38 °C/W CC D Junction-to-Ambient, Natural Convection(2) RJA CC (2) D Junction-to-Ambient, Natural Convection Four layer board - 2s2p 31 °C/W RJMA CC D Junction-to-Moving-Air, Ambient(2) 200 ft./min., single layer board - 1s 30 °C/W RJMA CC D Junction-to-Moving-Air, Ambient(2) at 200 ft./min., four layer board - 2s2p 25 °C/W RJB CC D Junction-to-Board(3) 20 °C/W RJA Doc ID 15399 Rev 9 83/157 Electrical characteristics Table 10. SPC564A74L7, SPC564A80B4, SPC564A80L7 Thermal characteristics for 176-pin QFP(1) (continued) Symbol C Parameter RJCtop CC D Junction-to-Case(4) JT CC D Conditions Junction-to-Package Top, Natural Convection(5) Value Unit 5 °C/W 2 °C/W 1. Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Table 11. Thermal characteristics for 208-pin LBGA(1) Symbol C Parameter Conditions Value Unit RJA CC D Junction-to-Ambient, Natural Convection(2),(3) One layer board - 1s 39 °C/W RJA CC D Junction-to-Ambient, Natural Convection(2),(4) Four layer board - 2s2p 24 °C/W RJMA CC D Junction-to-Moving-Air, Ambient(2),(4) at 200 ft./min., one layer board 31 °C/W RJMA CC D Junction-to-Moving-Air, Ambient(2),(4) at 200 ft./min., four layer board 2s2p 20 °C/W RJB CC D Junction-to-board(5) Four layer board - 2s2p RJC CC D Junction-to-case(6) JT CC D Junction-to-package top natural convection(7) 13 °C/W 6 °C/W 2 °C/W 1. Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. 4. Per JEDEC JESD51-6 with the board horizontal. 5. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 6. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. 7. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 84/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 12. Electrical characteristics Thermal characteristics for 324-pin PBGA(1) Symbol C Parameter Conditions Value Unit Single layer board - 1s 31 °C/W CC D Junction-to-Ambient, Natural Convection(2) RJA CC (2) D Junction-to-Ambient, Natural Convection Four layer board - 2s2p 23 °C/W RJMA CC D Junction-to-Moving-Air, Ambient(2) at 200 ft./min., single layer board 23 °C/W RJMA CC D Junction-to-Moving-Air, Ambient(2) at 200 ft./min., four layer board 2s2p 17 °C/W RJB CC D Junction-to-Board(3) 11 °C/W 7 °C/W 2 °C/W RJA (4) RJCtop CC D Junction-to-Case JT CC D Junction-to-Package Top, Natural Convection(5) 1. Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 3.3.1 General notes for specifications at maximum junction temperature An estimation of the chip junction temperature, TJ, can be obtained from the equation: Equation 1 TJ = TA + (RJA * PD) where: TA = ambient temperature for the package (oC) RJA = junction-to-ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the: ● Construction of the application board (number of planes) ● Effective size of the board which cools the component ● Quality of the thermal and electrical connections to the planes ● Power dissipated by adjacent components Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. Doc ID 15399 Rev 9 85/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has: ● One oz. (35 micron nominal thickness) internal planes ● Components are well separated ● Overall power dissipation on the board is less than 0.02 W/cm2 The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: Equation 2 TJ = TB + (RJB * PD) where: TB = board temperature for the package perimeter (oC) RJB = junction-to-board thermal resistance (oC/W) per JESD51-8S PD = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: Equation 3 RJA = RJC + RCA where: RJA = junction-to-ambient thermal resistance (oC/W) RJC = junction-to-case thermal resistance (oC/W) RCA = case to ambient thermal resistance (oC/W) RJC is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit 86/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: Equation 4 TJ = TT + (JT x PD) where: TT = thermocouple temperature on top of the package (oC) JT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International 3081 Zanker Road San Jose, CA 95134 USA (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. ● C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. ● G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications”, Electronic Packaging and Production, pp. 53-58, March 1998. ● B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220. Doc ID 15399 Rev 9 87/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 3.4 EMI (electromagnetic interference) characteristics Table 13. EMI Testing Specifications(1) Symbol Parameter Conditions VDDREG = 5.25 V; TA = 25 °C Radiated emissions, electric field VRE_TEM Frequency Range Level (Max) 150 kHz – 50 MHz 20 50 – 150 MHz 20 150 – 500 MHz 26 500 – 1000 MHz 26 IEC Level K — SAE Level 3 — 150 kHz– 50 MHz 13 50 – 150 MHz 13 150 – 500 MHz 11 500 – 1000 MHz 13 IEC Level L — SAE Level 2 — Conditions Value Unit — 2000 V — 1500  — 100 pF Clocks 16 MHz crystal 40 MHz bus No PLL frequency modulation 150 kHz – 30 MHz RBW 9 kHz, Step Size 5 kHz 30 MHz – 1 GHz RBW 120 kHz, Step Size 80 kHz 16 MHz crystal 40 MHz bus ± 2% PLL frequency modulation Unit dBV dBV 1. EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03 and IEC 61967-2. 3.5 Electrostatic discharge (ESD) characteristics Table 14. ESD ratings(1),(2) Symbol Parameter — SR R1 SR ESD for Human Body Model (HBM) HBM circuit description C SR — SR — — SR SR ESD for field induced charge Model (FDCM) All pins 500 Corner pins 750 V Positive pulses (HBM) 1 — Negative pulses (HBM) 1 — 1 — Number of pulses per pin Number of pulses — 1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2. Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature.” 88/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics 3.6 Power management control (PMC) and power on reset (POR) electrical specifications Table 15. PMC Operating Conditions and External Regulators Supply Voltage ID Name Parameter Min Typ Max Unit °C 1 Jtemp SR — Junction temperature –40 27 150 2 Vddreg SR — PMC 5 V supply voltage VDDREG 4.75 5 5.25 V SR Core supply voltage 1.2 V VDD when external regulator is used without disabling the internal — regulator (PMC unit turned on, LVI monitor active)(1) 1.26(2) 1.3 1.32 V 1.14 1.2 1.32 V 445 — — mA 3 Vdd 3a — SR Core supply voltage 1.2 V VDD when external regulator is used with a disabled internal — regulator (PMC unit turned-off, LVI monitor disabled) 4 Ivdd SR — SR Regulated 3.3 V supply voltage when external regulator is used without disabling the internal — regulator (PMC unit turned-on, internal 3.3V regulator enabled, LVI monitor active)(3) 3.3 3.45 3.6 V 3 3.3 3.6 V 80 — — mA 5 Vdd33 Voltage regulator core supply maximum required DC output current 5a — SR Regulated 3.3 V supply voltage when external regulator is used with a disabled internal — regulator (PMC unit turned-off, LVI monitor disabled) 6 — SR — Voltage regulator 3.3 V supply maximum required DC output current 1. An internal regulator controller can be used to regulate core supply. 2. The minimum supply required for the part to exit reset and enter in normal run mode is 1.28 V. 3. An internal regulator can be used to regulate 3.3 V supply. Table 16. ID PMC Electrical Characteristics Name Parameter Min Typ Max Unit — 1.219 — V VBG - 7% VBG Vbg + 6% V 1 VBG CC C Nominal bandgap voltage reference 1a — CC P Untrimmed bandgap reference voltage 1b — CC P Trimmed bandgap reference VBG -10mV voltage (5 V, 27 °C) VBG VBG + 10mV V 1c — CC C Bandgap reference temperature variation — 100 — ppm/°C 1d — CC C Bandgap reference supply voltage variation — 3000 — ppm/V Doc ID 15399 Rev 9 Notes 89/157 Electrical characteristics Table 16. ID SPC564A74L7, SPC564A80B4, SPC564A80L7 PMC Electrical Characteristics (continued) Name Parameter Min Typ Max Unit Notes Vdd Nominal VDD core supply CC C internal regulator target DC output voltage(1) — 1.28 — V — Nominal VDD core supply internal regulator target DC CC P output voltage variation at power-on reset Vdd - 6% Vdd Vdd + 10% V 2b — Nominal VDD core supply internal regulator target DC CC P output voltage variation after power-on reset Vdd 10%(2) Vdd Vdd + 3% V 2c — CC C Trimming step Vdd — 20 — mV 2d Ivrcctl Voltage regulator controller CC C for core supply maximum DC output current 20 — — mA 3 Lvi1p2 CC C Nominal LVI for rising core supply(3) — 1.160 — V 3a — Variation of LVI for rising CC C core supply at power-on reset 1.120 1.200 1.280 V See note (4) 3b — Variation of LVI for rising CC C core supply after power-on Lvi1p2 - 3% reset Lvi1p2 Lvi1p2 + 3% V See note (4) 3c — CC C — 20 — mV 3d Lvi1p2_h — 40 — mV 4 Por1.2V_r CC C POR 1.2 V rising — 0.709 — V 2 2a 4a 4b — Trimming step LVI core supply CC C LVI core supply hysteresis CC C POR 1.2 V rising variation Por1.2V_f CC C POR 1.2 V falling Por1.2V_r Por1.2V_r + Por1.2V_r 35% 35% — 0.638 — CC C POR 1.2 V falling variation 5 Vdd33 Nominal 3.3 V supply CC C internal regulator DC output voltage — 3.39 — Nominal 3.3 V supply internal regulator DC output CC P voltage variation at poweron reset Vdd33 8.5% Vdd33 — Nominal 3.3 V supply internal regulator DC output CC P voltage variation power-on reset Vdd33 7.5% Vdd33 5b 90/157 — V Por1.2V_f Por1.2V_f + Por1.2V_f 35% 35% 4c 5a V Doc ID 15399 Rev 9 — V V See note (5) Vdd3 + 7% V Vdd33 + 7% V With internal load up to Idd3p3 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 16. ID 5c 5d 5e Electrical characteristics PMC Electrical Characteristics (continued) Name — Idd3p3 Parameter Voltage regulator 3.3 V CC D output impedance at maximum DC load Voltage regulator 3.3 V maximum DC output current CC P (internal regulator enabled)(6) Vdd33 ILim CC C Voltage regulator 3.3 V DC current limit Min Typ Max Unit — — 2  80(7) — — mA — 130 — mA Notes — 3.090 — V The Lvi3p3 specs are also valid for the Vddeh LVI Lvi3p3 - 6% Lvi3p3 Lvi3p3 + 6% V See note (8) — Variation of LVI for rising CC C 3.3 V supply after power-on Lvi3p3 - 3% reset Lvi3p3 Lvi3p3 + 3% V See note (8) 6c — CC C Trimming step LVI 3.3 V — 20 — mV 6d Lvi3p3_h CC C LVI 3.3 V hysteresis — 60 — mV Lvi3p3 6a — Variation of LVI for rising CC C 3.3 V supply at power-on reset 6b 7 7a 7b CC C Nominal LVI for rising 3.3 V supply 6 Por3.3V_r CC C — CC C Por3.3V_f CC C Nominal POR for rising 3.3 V supply Variation of POR for rising 3.3 V supply Nominal POR for falling 3.3 V supply 7c — CC C Variation of POR for falling 3.3 V supply 8 Lvi5p0 CC C Nominal LVI for rising 5 V VDDREG supply 8a — 8b — 2.07 — Por3.3V_rPor3.3V_r + Por3.3V_r 35% 35% — 1.95 — Por3.3V_f Por3.3V_f + Por3.3V_f 35% 35% — V V V V 4.290 — V Variation of LVI for rising 5 V CC C VDDREG supply at power-on Lvi5p0 - 6% reset Lvi5p0 Lvi5p0 + 6% V — Variation of LVI for rising 5 V CC C VDDREG supply power-on Lvi5p0 - 3% reset Lvi5p0 Lvi5p0 + 3% V 8c — CC C Trimming step LVI 5 V — 20 — mV 8d Lvi5p0_h CC C LVI 5 V hysteresis — 60 — mV Doc ID 15399 Rev 9 The 3.3V POR specs are also valid for the VDDEH POR 91/157 Electrical characteristics Table 16. ID SPC564A74L7, SPC564A80B4, SPC564A80L7 PMC Electrical Characteristics (continued) Name Parameter Min Typ Max Unit 9 Por5V_r CC C Nominal POR for rising 5 V VDDREG supply — 2.67 — V 9a — CC C Variation of POR for rising 5 V VDDREG supply Por5V_r - 35% Por5V_r Por5V_r + 50% V 9b Por5V_f CC C Nominal POR for falling 5 V VDDREG supply — 2.47 — V 9c — CC C Variation of POR for falling 5 V VDDREG supply Por5V_f - 35% Por5V_f Por5V_f + 50% V Notes 1. Using external ballast transistor. 2. Min range is extended to 10% since Lvi1p2 is reprogrammed from 1.2 V to 1.16 V after power-on reset. 3. LVI for falling supply is calculated as LVI rising – LVI hysteresis. 4. Lvi1p2 tracks DC target variation of internal Vdd regulator. Minimum and maximum Lvi1p2 correspond to minimum and maximum Vdd DC target respectively. 5. Minimum loading (1.0 (1.5 preferred) W 1.0 A DC current gain (Beta) Absolute minimum power dissipation ICMaxDC Value Minimum peak collector current Collector-to-emitter saturation voltage 600(1) 200 – Base-to-emitter voltage 0.4 – 1.0 mV V 1. Adjust resistor at bipolar transistor collector for 3.3 V/5.0 V to avoid VCE < VCESAT. 3.7 Power up/down sequencing There is no power sequencing required among power sources during power up and power down, in order to operate within specification. Although there are no power up/down sequencing requirements to prevent issues such as latch-up or excessive current spikes the state of the I/O pins during power up/down varies according to Table 19 for all pins with fast pads, and Table 20 for all pins with medium, slow, and multi-voltage pads. Table 19. VDDE VRC33 VDD Pad State LOW X X LOW VDDE LOW X HIGH VDDE VRC33 LOW HIGH IMPEDANCE VDDE VRC33 VDD FUNCTIONAL Table 20. 94/157 Power sequence pin states (fast pads) Power sequence pin states (medium, slow, and multi-voltage pads) VDDEH VDD Pad State LOW X LOW VDDEH LOW HIGH IMPEDANCE VDDEH VDD FUNCTIONAL Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics 3.8 DC electrical specifications Table 21. DC electrical specifications Value Symbol C Parameter Conditions Unit min typ max VDD SR — Core supply voltage — 1.14 1.32 V VDDE SR — I/O supply voltage — 1.62 3.6 V VDDEH SR — I/O supply voltage — 3.0 5.25 V VDDE-EH SR — I/O supply voltage — 3.0 5.25 V — 3.0 — 3.6 V 3.3 V regulated voltage(1) VRC33 SR — VDDA SR — Analog supply voltage — 4.75(2) — 5.25 V VINDC SR — Analog input voltage — VSSA-0.3 — VDDA+0.3 V SR — VSS differential voltage — –100 — 100 mV — VSSA — VSSA+0.1 V — –100 — 100 mV — VDDA-0.1 — VDDA V SR — VREF differential voltage — 4.75 — 5.25 V Flash operating voltage(3) — 1.14 — 1.32 V — 3.0 — 3.6 V 0.95 — 1.2 VSS – VSSA VRL VRL – VSSA VRH VRH – VRL VDDF VFLASH(4) SR — Analog reference low voltage SR — VRL differential voltage SR — SR — Analog reference high voltage SR — Flash read voltage SRAM standby voltage Unregulated mode VSTBY SR — V Keep-out Range: 1.2V– Regulated 2V mode 2.0 — 5.5 VDDREG SR — Voltage regulator supply voltage — 4.75 — 5.25 V VDDPLL SR — Clock synthesizer operating voltage — 1.14 — 1.32 V VSSPLL – VSS SR — VSSPLL to VSS differential voltage — –100 — 100 mV VSS-0.3 — 0.35*VDDEH C VIL_S Slow/medium I/O pad input low voltage CC P Hysteresis enabled V Hysteresis disabled Doc ID 15399 Rev 9 VSS-0.3 — 0.40*VDDEH 95/157 Electrical characteristics Table 21. SPC564A74L7, SPC564A80B4, SPC564A80L7 DC electrical specifications (continued) Value Symbol C Parameter Conditions C VIL_F Fast pad I/O input low voltage CC P C VIL_LS CC P C VIL_HS CC Multi-voltage I/O pad input low voltage in Low-swingmode(5),(6),(7),(8) Multi-voltage pad I/O input low voltage in high-swing-mode — 0.35*VDDE V Hysteresis disabled VSS-0.3 — 0.40*VDDE Hysteresis enabled VSS-0.3 — 0.8 Hysteresis disabled VSS-0.3 — 1.1 Hysteresis enabled VSS-0.3 — 0.35 VDDEH VSS-0.3 — 0.4 VDDEH Hysteresis enabled 0.65 VDDEH — VDDEH+0.3 P Hysteresis disabled 0.55 VDDEH — VDDEH+0.3 C Hysteresis enabled 0.65 VDDE — VDDE+0.3 Slow/medium pad I/O input high voltage(9) CC Fast I/O input high voltage CC C CC P C VIH_HS VSS-0.3 V CC P V V P VIH_LS max V C VIH_F Hysteresis enabled typ Hysteresis disabled P VIH_S Unit min Multi-voltage pad I/O input high voltage in low-swingmode(5),(6),(7),(8) Hysteresis disabled 0.58 VDDE — VDDE+0.3 Hysteresis enabled 2.5 — VDDEH+0.3 V Multi-voltage I/O input high voltage in highswing-mode Hysteresis disabled 2.2 — VDDEH+0.3 Hysteresis enabled 0.65 VDDEH — VDDEH+0.3 V Hysteresis disabled 0.55 VDDEH — VDDEH+0.3 VOL_S CC P Slow/medium pad I/O output low voltage(9) — — 0.2*VDDEH V VOL_F CC P Fast I/O output low voltage(9) — — 0.2*VDDE V CC P Multi-voltage pad I/O output low voltage in low-swing mode(5),(6),(7),(8),(9) — — 0.6 V VOL_LS 96/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 21. Electrical characteristics DC electrical specifications (continued) Value Symbol C Parameter Conditions Unit min typ max VOL_HS CC P Multi-voltage pad I/O output low voltage in high-swing mode(9) — — 0.2*VDDEH V VOH_S CC P Slow/medium pad I/O output high voltage(9) 0.8 VDDEH — — V VOH_F CC P Fast pad I/O output high voltage(9) 0.8 VDDE — — V VOH_LS CC P Multi-voltage pad I/O output high voltage in low-swing mode(5),(6),(7),(8) 2.1 3.1 3.7 V VOH_HS CC P Multi-voltage pad I/O output high voltage in high-swing mode(9) 0.8 VDDEH — — V VHYS_S CC C Slow/medium/multivoltage I/O input hysteresis — 0.1 * VDDEH — — V VHYS_F CC C Fast I/O input hysteresis — 0.1 * VDDE — — V VHYS_LS CC C Low-Swing-Mode Multihysteresis Voltage I/O Input enabled Hysteresis 0.25 — — v — 380 mA VDD at 1.32 V at 80 MHz P IDD+IDDPLL IDDSTBY IDDSTBY27 IOH_LS = 0.5 mA CC P Operating current 1.2 V VDD at 1.32V at 120 MHz supplies — 400 mA P VDD at 1.32V at 150 MHz — 445 mA T Operating current 0.95VSTBY at 55 oC 1.2 V — 35 100 A T Operating current 2– 5.5 V — 45 110 A CC VSTBY at 55 oC P Operating current 0.95VSTBY 27 oC 1.2 V 25 90 A P Operating current 25.5 V 35 100 A CC VSTBY 27 oC Doc ID 15399 Rev 9 97/157 Electrical characteristics Table 21. SPC564A74L7, SPC564A80B4, SPC564A80L7 DC electrical specifications (continued) Value Symbol IDDSTBY150 IDDSLOW IDDSTOP IDD33 C Parameter 790 2000 A P Operating current 2– 5.5 V VSTBY at 150 oC — 760 2000 A VDD low-power mode operating current at 1.32 V Slow mode(10) — 191 Stop mode(11) — 190 — 60 CC P CC P CC C Operating current 3.3 V VRC33(1),(12) supplies CC P VDDA Analog Operating current 5.0 V reference supplies supply current (transient) 98/157 — 30.0 — — 1.0 70(13) — — D VDDEH1 — — D VDDEH4 — — VDDEH6 — — VDDEH7 — — D VDDE7 — — D VDDEH9 — — D VDDE12 — — 15 — 95 35 — 200 1.62 V – 1.98 V 36 — 120 2.25 V – 2.75 V 34 — 139 3.0 V – 3.6 V 42 — 158 VDDE= 3.0–3.6 V(5), C Multi-voltage pad weak MultiV pad, high swing pullup current mode only 10 — 75 P 25 — 200 D CC D CC P CC D CC — VDDREG D IACT_MV_PU mA C Operating current VDDE(14) supplies Slow/medium I/O weak 3.0 V – 3.6 V pull up/down current(15) 4.75 V – 5.5 V D IACT_F max — C IACT_S typ Operating current 0.95VSTBY 150 oC 1.2 V IDDREG IDDH1 IDDH4 IDDH6 IDDH7 IDD7 IDDH9 IDD12 Unit min P P IDDA IREF Conditions Fast I/O weak pull up/down current(15) 4.75 V – 5.25 V Doc ID 15399 Rev 9 See note (14) mA mA mA A A A SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 21. Electrical characteristics DC electrical specifications (continued) Value Symbol IACT_MV_PD C CC Parameter Conditions C Multivoltage pad weak pulldown current P Unit min typ max VDDE= 3.0–3.6 V(5), MultiV pad, high swing mode only 10 — 60 4.75 V – 5.25 V 25 — 200 A IINACT_D CC P I/O input leakage current(16) — –2.5 — 2.5 A IIC SR T DC injection current (per pin) — –1.0 — 1.0 mA Analog input current, channel off, AN[0:7](17) — –250 — 250 P IINACT_A SR nA Analog input current, P channel off, all other analog pins(17) D D CL CC D — –150 DSC(PCR[8:9]) = 0b00 — 10 — 20 — 30 DSC(PCR[8:9]) = 0b11 — 50 DSC(PCR[8:9]) Load capacitance (fast = 0b01 I/O)(18) DSC(PCR[8:9]) = 0b10 D — 150 pF CIN CC D Input capacitance (digital pins) — — 7 pF CIN_A CC D Input capacitance (analog pins) — — 10 pF CIN_M CC D Input capacitance (digital and analog pins(19)) — — 12 pF RPUPD200K SR P Weak Pull-Up/Down Resistance(20), 200 k Option — 130 — 280 k RPUPD100K SR P Weak Pull-Up/Down Resistance(20), 100 k Option — 65 — 140 k Doc ID 15399 Rev 9 99/157 Electrical characteristics Table 21. SPC564A74L7, SPC564A80B4, SPC564A80L7 DC electrical specifications (continued) Value Symbol RPUPD5K RPUPDMTCH TA (TL to TH) — C SR C CC Parameter Conditions Weak Pull-Up/Down Resistance(20), 5 k Option Pull-up/Down C Resistance matching ratios (100K/200K) typ max 5 V ± 5% supply 1.4 — 7.5 k Pull-up and pull-down resistances both enabled and settings are equal. –2.5 — 2.5 % — –40.0 125.0 C — — 25 V/ms Operating temperature SR — range - ambient (packaged) SR — Unit min Slew rate on power supply pins 1. These specifications apply when VRC33 is supplied externally, after disabling the internal regulator (VDDREG = 0). 2. ADC is functional with 4 V  VDDA  4.75 V but with derated accuracy. This means the ADC will continue to function at full speed with no undesirable behavior, but the accuracy will be degraded. 3. The VDDF supply is connected to VDD in the package substrate. This specification applies to calibration package devices only. 4. VFLASH is only available in the calibration package. 5. Power supply for multi-voltage pads cannot be below 4.5 V when in low-swing mode. 6. The slew rate (SRC) setting must be 0b11 when in low-swing mode. 7. While in low-swing mode there are no restrictions in transitioning to high-swing mode. 8. Pin in low-swing mode can accept a 5 V input. 9. All VOL/VOH values 100% tested with ± 2 mA load except where noted. 10. Bypass mode, system clock at 1 MHz (using system clock divider), PLL shut down, CPU running simple executive code, 4 x ADC conversion every 10 ms, 2 x PWM channels 1 kHz, all other modules stopped. 11. Bypass mode, system clock at 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules stopped. 12. This current will be consumed for external regulation and internal regulation, when 3.3V regulator is switched off by shadow flash 13. If 1.2V and 3.3V internal regulators are on,then iddreg=70mA If supply is external that is 3.3V internal regulator is off, then iddreg=15mA 14. Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. See Table 22 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 15. Absolute value of current, measured at VIL and VIH. 16. Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to fast, slow, and medium pads. 17. Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to analog pads. 18. Applies to CLKOUT, external bus pins, and Nexus pins. 19. Applies to the FCK, SDI, SDO, and SDS pins. 20. This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics. 100/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 3.9 Electrical characteristics I/O pad current specifications The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 22 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 22. Table 22. Pad Type Slow Medium Fast MultiV (High Swing Mode) MultiV (Low Swing Mode) I/O pad average IDDE specifications(1) C Period (ns) Load(2) (pF) VDDE (V) Drive/Slew Rate Select IDDE Avg (mA)(3) IDDE RMS (mA) CC D 37 50 5.5 11 9 — CC D 130 50 5.5 01 2.5 — CC D 650 50 5.5 00 0.5 — CC D 840 200 5.5 00 1.5 — CC D 24 50 5.5 11 14 — CC D 62 50 5.5 01 5.3 — CC D 317 50 5.5 00 1.1 — CC D 425 200 5.5 00 3 — CC D 10 50 3.6 11 22.7 68.3 CC D 10 30 3.6 10 12.1 41.1 CC D 10 20 3.6 01 8.3 27.7 CC D 10 10 3.6 00 4.44 14.3 CC D 10 50 1.98 11 12.5 31 CC D 10 30 1.98 10 7.3 18.6 CC D 10 20 1.98 01 5.42 12.6 CC D 10 10 1.98 00 2.84 6.4 CC D 20 50 5.5 11 9 — CC D 30 50 5.5 01 6.1 — CC D 117 50 5.5 00 2.3 — CC D 212 200 5.5 00 5.8 — CC D 30 30 5.5 11 3.4 — Symbol IDRV_SSR_HV IDRV_MSR_HV IDRV_FC IDRV_MULTV_HV IDRV_MULTV_HV 1. Numbers from simulations at best case process, 150 °C. 2. All loads are lumped. 3. Average current is for pad configured as output only. Doc ID 15399 Rev 9 101/157 Electrical characteristics 3.9.1 SPC564A74L7, SPC564A80B4, SPC564A80L7 I/O pad VRC33 current specifications The power consumption of the VRC33 supply is dependent on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VRC33 currents for all I/O segments. The output pin VRC33 current can be calculated from Table 23 based on the voltage, frequency, and load on all fast pad pins. The input pin VRC33 current can be calculated from Table 23 based on the voltage, frequency, and load on all medium-speed pads. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 23. Table 23. I/O pad VRC33 average IDDE specifications(1) Pad Type Symbol Slow IDRV_SSR_HV Medium MultiV(3) (High Swing Mode) MultiV(4) (Low Swing Mode) IDRV_MSR_HV IDRV_MULTV_HV IDRV_MULTV_HV C Period (ns) Load (2) Drive Select IDD33 Avg (µA) IDD33 RMS (µA) (pF) CC D 100 50 11 0.8 235.7 CC D 200 50 01 0.04 87.4 CC D 800 50 00 0.06 47.4 CC D 800 200 00 0.009 47 CC D 40 50 11 2.75 258 CC D 100 50 01 0.11 76.5 CC D 500 50 00 0.02 56.2 CC D 500 200 00 0.01 56.2 CC D 20 50 11 33.4 35.4 CC D 30 50 01 33.4 34.8 CC D 117 50 00 33.4 33.8 CC D 212 200 00 33.4 33.7 CC D 30 30 11 33.4 34.9 1. These are typical values that are estimated from simulation and not tested. Currents apply to output pins only. 2. All loads are lumped. 3. Average current is for pad configured as output only. 4. In low swing mode, multi-voltage pads must operate in highest slew rate setting. 102/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 24. Pad Type Fast Electrical characteristics VRC33 pad average DC current(1) Symbol IDRV_FC C Load Period (ns) (2) (pF) VRC33 (V) VDDE (V) Drive Select IDD33 Avg (µA) IDD33 RMS (µA) CC D 10 50 3.6 3.6 11 2.35 6.12 CC D 10 30 3.6 3.6 10 1.75 4.3 CC D 10 20 3.6 3.6 01 1.41 3.43 CC D 10 10 3.6 3.6 00 1.06 2.9 CC D 10 50 3.6 1.98 11 1.75 4.56 CC D 10 30 3.6 1.98 10 1.32 3.44 CC D 10 20 3.6 1.98 01 1.14 2.95 CC D 10 10 3.6 1.98 00 0.95 2.62 1. These are typical values that are estimated from simulation and not tested. Currents apply to output pins only. 2. All loads are lumped. 3.9.2 LVDS pad specifications LVDS pads are implemented to support the MSC (Microsecond Channel) protocol which is an enhanced feature of the DSPI module. The LVDS pads are compliant with LVDS specifications and support data rates up to 50 MHz. Table 25. # DSPI LVDS pad specification Characteristic Symbol C Condition Min. Value Typ. Value Max. Value Unit Data Rate 4 Data Frequency fLVDSCLK CC D — 50 MHz Driver Specs 5 Differential output voltage VOD CC P SRC=0b00 or 0b11 150 400 CC P SRC=0b01 90 320 CC P SRC=0b10 160 480 6 Common mode voltage (LVDS), VOS VOD CC P 7 Rise/Fall time TR/TF CC D 8 Propagation delay (Low to High) TPLH CC D 9 Propagation delay (High to Low) TPHL CC D 1.06 — — Doc ID 15399 Rev 9 1.2 1.39 mV V 2 ns 4 ns 4 ns 103/157 Electrical characteristics Table 25. # SPC564A74L7, SPC564A80B4, SPC564A80L7 DSPI LVDS pad specification (continued) Characteristic Symbol C Condition 10 Delay (H/L), sync Mode tPDSYNC CC D 11 Delay, Z to Normal (High/Low) TDZ CC D — 12 Diff Skew Itphla-tplhbI or Itplhb-tphlaI TSKEW CC D — Min. Value Typ. Value Max. Value Unit 4 ns 500 ns 0.5 ns 105  150 C Termination 13 Trans. Line (differential Zo) CC D 14 Temperature CC D — 95 100 –40 3.10 Oscillator and PLLMRFM electrical characteristics Table 26. PLLMRFM electrical specifications (VDDPLL = 1.08 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH) Value Symbol C Parameter Conditions Crystal reference D fref_crystal fref_ext CC fpll_in CC P fvco CC fsys CC PLL reference frequency range(1) 80 Phase detector input frequency range (after pre-divider) — 4 16 MHz P VCO frequency range — 256 512 MHz C On-chip PLL frequency(2) — 16 150 MHz Crystal reference 4 40 (2) CC fSCM CC 104/157 MHz System frequency in bypass mode P fLORL fLORH 40 4 CC CC 4 MHz C tCYC max External reference T fsys Unit min External reference 0 80 — — 1 / fsys D System clock period D Lower limit 1.6 3.7 D Loss of reference frequency window(3) Upper limit 24 56 P Self-clocked mode frequency (4),(5) — 1.2 72.25 ns MHz Doc ID 15399 Rev 9 MHz SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 26. Electrical characteristics PLLMRFM electrical specifications (VDDPLL = 1.08 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH) (continued) Value Symbol C Parameter T CJITTER tcst T CC T Crystal start-up time (10), (11) Long-term jitter (avg. over 2 ms interval) T VIHEXT CC EXTAL input high voltage T max –5 5 % fCLKOUT –6 6 ns — 10 ms Crystal Mode(12) Vxtal + 0.4 — External Reference(12), VRC33 /2 + 0.4 VRC33 — Vxtal 0.4 0 VRC33 /2 0.4 4 MHz 5 30 8 MHz 5 26 12 MHz 5 23 16 MHz 5 19 20 MHz 5 16 40 MHz 5 8 fSYS maximum — (13) Crystal Mode(12) T VILEXT CC EXTAL input low voltage T Unit min Peak-to-peak (clock edge to clock edge) CLKOUT period jitter(6),(7),(8),(9) CC Conditions External Reference(12), (13) — CC T XTAL load capacitance(10) V V pF tlpll CC P PLL lock time (10), (14) — — 200 s tdc CC T Duty cycle of reference — 40 60 % fLCK CC T Frequency LOCK range — –6 6 % fsys fUL CC T Frequency un-LOCK range — –18 18 % fsys fCS fDS Center spread ±0.25 ±4.0 CC Down Spread –0.5 –8.0 fMOD CC — 100 D Modulation Depth D D Modulation frequency(15) — % fsys kHz 1. Considering operation with PLL not bypassed. 2. All internal registers retain data at 0 Hz. 3. “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode. 4. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR window. Doc ID 15399 Rev 9 105/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 5. fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced mode. 6. This value is determined by the crystal manufacturer and board design. 7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER percentage for a given interval. 8. Proper PC board layout procedures must be followed to achieve specifications. 9. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled). 10. This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals specified for this PLL, load capacitors should not exceed these limits. 11. Proper PC board layout procedures must be followed to achieve specifications. 12. This parameter is guaranteed by design rather than 100% tested. 13. VIHEXT cannot exceed VRC33 in external reference mode. 14. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 15. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz. 3.11 Temperature sensor electrical characteristics Table 27. Temperature sensor electrical characteristics Value Symbol C Parameter Conditions Unit Temperature monitoring range — CC C — CC C Sensitivity — CC P Accuracy TJ = –40 to 150 °C 3.12 eQADC electrical characteristics Table 28. eQADC conversion specifications (operating) min typical max –40 — 150 °C — 6.3 — mV/°C –10 — 10 °C Value Symbol C Unit Parameter fADCLK SR — ADC clock (ADCLK) frequency CC CC D Conversion cycles time(1) TSR CC C Stop mode recovery fADCLK SR — ADC clock (ADCLK) frequency min max 2 16 MHz 2+13 128+14 ADCLK cycles — 10 s 2 16 mV 1. Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms. 106/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 29. Electrical characteristics eQADC single ended conversion specifications (operating) Value Symbol C Parameter Unit min max OFFNC CC C Offset error without calibration 0 160 Counts OFFWC CC C Offset error with calibration –4 4 Counts GAINNC CC C Full scale gain error without calibration –160 0 Counts GAINWC CC C Full scale gain error with calibration –4 4 Counts –3 3 mA –4 4 Counts (6) Counts 8 Counts IINJ EINJ CC CC T T Disruptive input injection current (1), (2), (3), (4) (5),(6) Incremental error due to injection current TUE8 CC C Total unadjusted error (TUE) at 8 MHz –4 TUE16 CC C Total unadjusted error at 16 MHz –8 4 1. Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater then VRH and 0x0 for values less then VRL. Other channels are not affected by non-disruptive conditions. 2. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 3. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values. 4. Condition applies to two adjacent pins at injection limits. 5. Performance expected with production silicon. 6. All channels have same 10 k < Rs < 100 k; Channel under test has Rs=10 k; IINJ=IINJMAX,IINJMIN Table 30. eQADC differential ended conversion specifications (operating) Value Symbol C Parameter Unit min CC – CC C CC max Variable gain amplifier accuracy (gain=1)(2) 8 MHz ADC –4 4 Counts(3) C 16 MHz ADC –8 8 Counts CC C 8 MHz ADC –3(4) 3(4) Counts CC C 16 MHz ADC –3(4) 3(4) Counts INL GAINVGA1 (1) DNL Doc ID 15399 Rev 9 107/157 Electrical characteristics Table 30. SPC564A74L7, SPC564A80B4, SPC564A80L7 eQADC differential ended conversion specifications (operating) (continued) Value Symbol C Parameter Unit min CC – CC D max Variable gain amplifier accuracy (gain=2)(2) 8 MHz ADC –5 5 Counts INL GAINVGA2 CC D 16 MHz ADC –8 8 Counts CC D 8 MHz ADC –3 3 Counts 16 MHz ADC –3 3 Counts (1) DNL CC D CC – CC D CC Variable gain amplifier accuracy (gain=4)(2) 8 MHz ADC –7 7 Counts D 16 MHz ADC –8 8 Counts CC D 8 MHz ADC –4 4 Counts CC D 16 MHz ADC –4 4 Counts CC C PREGAIN set to 1X setting — (VRH - VRL)/2 V — (VRH - VRL)/4 V — (VRH - VRL)/8 V (VRH + VRL)/2 5% (VRH + VRL)/2 + 5% V INL GAINVGA4 (1) DNL DIFFmax DIFFmax2 CC C DIFFmax4 CC C DIFFcmv CC C Maximum differential voltage PREGAIN (DANx+ - DANx-) set to 2X or (DANx- setting DANx+)(5) PREGAIN set to 4X setting Differential input Common mode voltage (DANx- + DANx+)/2(5) — 1. Applies only to differential channels. 2. Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of 1, 2, or 4. Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as indicated. 3. At VRH – VRL = 5.12 V, one LSB = 1.25 mV. 4. Guaranteed 10-bit mono tonicity. 5. Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode voltage of the differential signal violates the Differential Input common mode voltage specification. 108/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 3.13 Electrical characteristics Configuring SRAM wait states Use the SWSC field in the ECSM_MUDCR register to specify an additional wait state for the device SRAM. By default, no wait state is added. Table 31. Cutoff frequency for additional SRAM wait state (1) SWSC Value 98 0 153 1 1. Max frequencies including 2% PLL FM. Please see the device reference manual for details. 3.14 Platform flash controller electrical characteristics Table 32. APC, RWSC, WWSC settings vs. frequency of operation(1),(2) Max. Flash Operating Frequency (MHz)(3) APC(4) RWSC(4) WWSC 20 MHz 0b000 0b000 0b11 61 MHz 0b001 0b001 0b11 90 MHz 0b010 0b010 0b11 123 MHz 0b011 0b011 0b11 153 MHz 0b100 0b100 0b11 1. APC, RWSC and WWSC are fields in the flash memory BIUCR register used to specify wait states for address pipelining and read/write accesses. Illegal combinations exist—all entries must be taken from the same row. 2. TBD: To Be Defined. 3. Max frequencies including 2% PLL FM. 4. APC must be equal to RWSC. 3.15 Flash memory electrical characteristics Table 33. Flash program and erase specifications(1) # Symbol C Parameter Min. Typical Initial Max(3) Value Value Max(2) Unit 1 Tdwprogram C C P Double Word (64 bits) Program Time — 45 — 500 s 2 Tpprogram C C P Page Program Time — 55 160(4) 500 s 3 T16kpperase C C P 16 KB Block Pre-program and Erase Time — 300 1000 5000 ms Doc ID 15399 Rev 9 109/157 Electrical characteristics Flash program and erase specifications(1) (continued) Table 33. # SPC564A74L7, SPC564A80B4, SPC564A80L7 Symbol C Parameter Min. Typical Initial Max(3) Value Value Max(2) Unit 5 T64kpperase C C P 64 KB Block Pre-program and Erase Time — 800 1800 5000 ms 6 T128kpperase C C P 128 KB Block Pre-program and Erase Time — 1500 3000 7500 ms 7 T256kpperase C C P 256 KB Block Pre-program and Erase Time — 3000 5300 15000 ms 8 Tpsrt Program suspend request rate(5) 100 — — — s 9 Tesrt SR — SR — Erase suspend request rate (6) 10 ms 1. Typical program and erase times assume nominal supply values and operation at 25 oC. All times are subject to change pending device characterization. 2. Initial factory condition: < 100 program/erase cycles, 25 oC, typical supply voltage, 80 MHz minimum system frequency. 3. The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized but not guaranteed. 4. Page size is 128 bits (4 words). 5. Time between program suspend resume and the next program suspend request. 6. Time between erase suspend resume and the next erase suspend request. Table 34. Flash module life Value Symbol P/E P/E Data Retention C CC CC CC Parameter Conditions Unit min typ C Number of program/erase cycles per block for 16 KB, 48 KB, and 64 Kbyte blocks over the operating temperature range (TJ) — 100,000 — P/E cycles C Number of program/erase cycles per block for 128 Kbyte and 256 Kbyte blocks over the operating temperature range (TJ) — 1,000 100,000 P/E cycles Blocks with 0 – 1,000 P/E cycles 20 — years Blocks with 1,001 – 10,000 P/E cycles 10 — years Blocks with 10,001 – 100,000 P/E cycles 5 — years C Minimum data retention at 85 C average ambient temperature(1) 1. Ambient temperature averaged over duration of application, not to exceed product operating temperature range. 110/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 3.16 AC specifications 3.16.1 Pad AC specifications Table 35. Pad AC specifications (5.0 V)(1) Output Delay (ns)(2),(3) Name C CC D Low-to-High / Highto-Low Drive Load SRC/DSC (pF) Max Min Max 4.6/3.7 12/12 2.2/2.2 7/7 MSB,LSB 50 11(8) 10(9) N/A CC D 12/13 28/34 5.6/6 15/15 50 01 CC D 69/71 152/165 34/35 74/74 50 00 CC D 7.3/5.7 19/18 4.4/4.3 14/14 50 11(8) 10(9) N/A Slow(7),(10) MultiV (Low Swing Mode) Rise/Fall Edge (ns)(3),(4) Min Medium(5),(6),(7) MultiV(11) (High Swing Mode) Electrical characteristics CC D 26/27 61/69 13/13 34/34 50 01 CC D 137/142 320/330 72/74 164/164 50 00 CC D 4.1/3.6 10.3/8.9 3.28/2.98 8/8 50 11(8) 10(9) N/A CC D 8.38/6.11 16/12.9 5.48/4.81 11/11 50 01 CC D 61.7/10.4 92.2/24.3 42.0/12.2 63/63 50 00 CC D 2.31/2.34 7.62/6.33 1.26/1.67 6.5/4.4 30 11(8) ±1.5/1.5 0.5 N/A 5000/5000 50 N/A Fast(12) N/A pad_i_hv(13) CC D 0.5/0.5 1.9/1.9 pull_hv CC D NA 6000 0.3/0.3 1. These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V, TA = TL to TH 2. This parameter is supplied for reference and is not guaranteed by design and not tested. 3. Delay and rise/fall are measured to 20% or 80% of the respective signal. 4. This parameter is guaranteed by characterization before qualification rather than 100% tested. 5. In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output pads 6. Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown. 7. Output delay is shown in Figure 9: Pad output delay. Add a maximum of one system clock to the output delay for delay with respect to system clock. 8. Can be used on the tester. 9. This drive select value is not supported. If selected, it will be approximately equal to 11. 10. Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown. 11. Selectable high/low swing IO pad with selectable slew in high swing mode only. 12. Fast pads are 3.3 V pads. 13. Stand alone input buffer. Also has weak pull-up/pull-down. Doc ID 15399 Rev 9 111/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 Pad AC specifications (VDDE = 3.3 V)(1) Table 36. Output Delay (ns)(2),(3) Pad Type C Low-to-High / Highto-Low Rise/Fall Edge (ns)(3),(4) Drive Load (pF) Min Max Min Max MSB,LSB CC D 5.8/4.4 18/17 2.7/2.1 10/10 50 CC D 16/13 46/49 11.2/8.6 34/34 200 11(8) 10(9) N/A Medium(5),(6),(7) SRC/DSC CC D 14/16 37/45 6.5/6.7 19/19 50 CC D 27/27 69/82 15/13 43/43 200 CC D 83/86 200/210 38/38 86/86 50 CC D 113/109 270/285 53/46 120/120 200 CC D 9.2/6.9 27/28 5.5/4.1 20/20 50 CC D 30/23 81/87 21/16 63/63 200 01 00 11 10(9) N/A Slow(7),(10) CC D 31/31 80/90 15.4/15.4 42/42 50 CC D 58/52 144/155 32/26 82/85 200 CC D 162/168 415/415 80/82 190/190 50 CC D 216/205 533/540 106/95 250/250 200 CC D 3.7/3.1 10/10 30 CC D 46/49 37/37 200 01 00 MultiV(7),(11) (High Swing Mode) 11(8) 10(9) N/A CC D 32 15/15 50 CC D 72 46/46 200 CC D 210 100/100 50 CC D 295 134/134 200 01 00 MultiV (Low Swing Mode) Not a valid operational mode CC D 2.5/2.5 1.2/1.2 10 00 CC D 2.5/2.5 1.2/1.2 20 01 CC D 2.5/2.5 1.2/1.2 30 10 CC D 2.5/2.5 1.2/1.2 50 11(8) pad_i_hv(12) CC D 0.5/0.5 3/3 ±1.5/1.5 0.5 N/A pull_hv CC D NA 6000 5000/5000 50 N/A Fast 0.4/0.4 1. These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at VDD = 1.14 V to 1.32 V, VDDE = 3 V to 3.6 V, VDDEH = 3 V to 3.6 V, TA = TL to TH. 2. This parameter is supplied for reference and is not guaranteed by design and not tested. 3. Delay and rise/fall are measured to 20% or 80% of the respective signal. 112/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics 4. This parameter is guaranteed by characterization before qualification rather than 100% tested. 5. In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output pads 6. Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown. 7. Output delay is shown in Figure 9. Add a maximum of one system clock to the output delay for delay with respect to system clock. 8. Can be used on the tester. 9. This drive select value is not supported. If selected, it will be approximately equal to 11. 10. Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown. 11. Selectable high/low swing IO pad with selectable slew in high swing mode only. 12. Stand alone input buffer. Also has weak pull-up/pull-down. VDDE/2 Pad Data Input Rising Edge Output Delay Falling Edge Output Delay VOH Pad Output Figure 9. VOL Pad output delay Doc ID 15399 Rev 9 113/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 3.17 AC timing 3.17.1 Reset and configuration pin timing Table 37. Reset and Configuration Pin Timing(1) # Characteristic Symbol Min Max Unit 1 RESET Pulse Width(2) tRPW 10 — tcyc 2 RESET Glitch Detect Pulse Width tGPW 2 — tcyc 3 PLLREF, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid tRCSU 10 — tcyc 4 PLLREF, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid tRCH 0 — tcyc 1. Reset timing specified at: VDDEH = 3.0 V to 5.25 V, VDD = 1.14 V to 1.32 V, TA = TL to TH. 2. RESET pulse width is measured from 50% of the falling edge to 50% of the rising edge. 2 RESET 1 RSTOUT 3 BOOTCFG WKPCFG 4 Figure 10. Reset and Configuration Pin Timing 114/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 3.17.2 IEEE 1149.1 interface timing Table 38. JTAG pin AC electrical characteristics(1) # Symbol C Characteristic Electrical characteristics Min. Max. Value Value Unit 1 tJCYC CC D TCK Cycle Time 100 — ns 2 tJDC CC D TCK Clock Pulse Width 40 60 ns 3 tTCKRISE CC D TCK Rise and Fall Times (40% 70%) — 3 ns 4 tTMSS, tTDIS CC D TMS, TDI Data Setup Time 5 — ns 5 tTMSH, tTDIH CC D TMS, TDI Data Hold Time 25 — ns 6 tTDOV CC D TCK Low to TDO Data Valid — 22(2) ns 7 tTDOI CC D TCK Low to TDO Data Invalid 0 — ns 8 tTDOHZ CC D TCK Low to TDO High Impedance — 22 ns 9 tJCMPPW CC D JCOMP Assertion Time 100 — ns 10 tJCMPS CC D JCOMP Setup Time to TCK Low 40 — ns 11 tBSDV CC D TCK Falling Edge to Output Valid — 50 ns 12 tBSDVZ CC D TCK Falling Edge to Output Valid out of High Impedance — 50 ns 13 tBSDHZ CC D TCK Falling Edge to Output High Impedance — 50 ns 14 tBSDST CC D Boundary Scan Input Valid to TCK Rising Edge 25(3) — ns 15 tBSDHT CC D TCK Rising Edge to Boundary Scan Input Invalid 25(3) — ns 1. JTAG timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V with multi-voltage pads programmed to LowSwing mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b11. These specifications apply to JTAG boundary scan only. See Table 39 for functional specifications. 2. Pad delay is 8–10 ns. Remainder includes TCK pad delay, clock tree delay logic delay and TDO output pad delay. 3. For 20 MHz TCK. Note: The Nexus/JTAG Read/Write Access Control/Status Register (RWCS) write (to begin a read access) or the write to the Read/Write Access Data Register (RWD) (to begin a write access) does not actually begin its action until 1 JTAG clock (TCK) after leaving the JTAG Update-DR state. This prevents the access from being performed and therefore will not signal its completion via the READY (RDY) output unless the JTAG controller receives an additional TCK. In addition, EVTI is not latched into the device unless there are clock transitions on TCK. The tool/debugger must provide at least one TCK clock for the EVTI signal to be recognized by the MCU. When using the RDY signal to indicate the end of a Nexus read/write access, ensure that TCK continues to run for at least 1 TCK after leaving the Update-DR state. This can be just a TCK with TMS low while in the Run-Test/Idle state or by continuing with the Doc ID 15399 Rev 9 115/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 next Nexus/JTAG command. Expect the affect of EVTI and RDY to be delayed by edges of TCK. Note: RDY is not available in all packages of all devices. TCK 2 3 2 1 3 Figure 11. JTAG test clock input timing TCK 4 5 TMS, TDI 6 8 7 TDO Figure 12. JTAG test access port timing 116/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics TCK 10 JCOMP 9 Figure 13. JTAG JCOMP timing Doc ID 15399 Rev 9 117/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 TCK 11 13 Output Signals 12 Output Signals 14 15 Input Signals Figure 14. JTAG boundary scan timing 3.17.3 Nexus timing Table 39. Nexus debug port timing(1) # 1 Symbol tMCYC CC C D Characteristic Min. Value Max. Value MCKO Cycle Time 1a tMCYC CC D Absolute Minimum MCKO Cycle Time 2 tMDC CC D MCKO Duty Cycle 3 tMDOV CC D MCKO Low to MDO Data Valid(5) 4 tMSEOV CC D Unit 2(2),(3) 8 tCYC 25(4) — ns 40 60 % - 0.1 0.35 tMCYC MCKO Low to MSEO Data Valid(5) - 0.1 0.35 tMCYC Valid(5) - 0.1 0.35 tMCYC 6 tEVTOV CC D MCKO Low to EVTO Data 7 tEVTIPW CC D EVTI Pulse Width 4.0 — tTCYC 8 tEVTOPW CC D EVTO Pulse Width 1 — tMCYC 118/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Nexus debug port timing(1) (continued) Table 39. # 9 Electrical characteristics Symbol tTCYC CC C D Characteristic Min. Value Max. Value Unit TCK Cycle Time 4(6),(7) — tCYC 100(8) — ns 9a tTCYC CC D Absolute Minimum TCK Cycle Time 10 tTDC CC D TCK Duty Cycle 40 60 % 11 tNTDIS CC D TDI Data Setup Time 5 — ns 12 tNTDIH CC D TDI Data Hold Time 25 — ns 13 tNTMSS CC D TMS Data Setup Time 5 — ns 14 tNTMSH CC D TMS Data Hold Time 25 — ns 15 — CC D TDO propagation delay from falling edge of TCK — 19.5 ns 16 — CC D TDO hold time with respect to TCK falling edge (minimum TDO propagation delay) 5.25 — ns 1. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V with multi-voltage pads programmed to Low-Swing mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10. 2. Achieving the absolute minimum MCKO cycle time may require setting the MCKO divider to more than its minimum setting (NPC_PCR[MCKO_DIV] depending on the actual system frequency being used. 3. This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute minimum MCKO period specification. 4. This may require setting the MCO divider to more than its minimum setting (NPC_PCR[MCKO_DIV]) depending on the actual system frequency being used. 5. MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 6. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. 7. This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute minimum TCK period specification. 8. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. 1 2 MCKO 3 4 6 MDO MSEO EVTO Output Data Valid Figure 15. Nexus output timing Doc ID 15399 Rev 9 119/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 TCK EVTI EVTO 9 7 7 8 8 Figure 16. Nexus event trigger and test clock timings TCK 11 13 12 14 TMS, TDI 15 16 TDO Figure 17. Nexus TDI, TMS, TDO timing 120/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 40. Electrical characteristics N Nexus debug port operating frequency Nexus Pin Usage Package Nexus Width Nexus Routing MDO[0:3] LQFP176 BGA208 BGA324 MDO[4:11] CAL_MDO[4:11] GPIO GPIO 40 MHz(3) GPIO 40 MHz(5),(6) GPIO 40 MHz(3) GPIO 40 MHz(5),(6) Cal Nexus Data Out [4:11] 40 MHz(3) Reduced port Nexus Data Out Route to MDO(2) mode(1) [0:3] Full port mode(4) Route to MDO(2) Nexus Data Out Nexus Data Out [0:3] [4:11] Reduced port Nexus Data Out Route to MDO(2) mode(1) [0:3] CSP496 Route to MDO(2) Full port mode(4) Route to CAL_MDO(7) Max. Operating Frequency GPIO Nexus Data Out Nexus Data Out [0:3] [4:11] Cal Nexus Data Out [0:3] GPIO 1. NPC_PCR[FPM] = 0 2. NPC_PCR[NEXCFG] = 0 3. The Nexus AUX port runs up to 40 MHz. Set NPC_PCR[MCKO_DIV] to divide-by-two if the system frequency is greater than 40 MHz. 4. NPC_PCR[FPM] = 1 5. Set the NPC_PCR[MCKO_DIV] to divide by two if the system frequency is between 40 MHz and 80 MHz inclusive. Set the NPC_PCR[MCKO_DIV] to divide by four if the system frequency is greater than 80 MHz. 6. Pad restrictions limit the Maximum Operation Frequency in these configurations 7. NPC_PCR[NEXCFG] = 1 Doc ID 15399 Rev 9 121/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 3.17.4 External Bus Interface (EBI) and calibration bus interface timing Table 41. External Bus Interface maximum operating frequency Port Width Multiplexed Mode ADDR[12:15] Pin Usage ADDR[16:31] Pin Usage DATA[0:15] Pin Usage Max. Operating Frequency 16-bit Yes ADDR[12:15] GPIO ADDR[16:31] DATA[0:15] 66 MHz(1) 16-bit No ADDR[12:15] ADDR[16:31] DATA[0:15] 33 MHz(2),(3) 32-bit Yes ADDR[12:15] ADDR[16:31] DATA[16:31] DATA[0:15] 33 MHz(2),(3) 1. Set SIU_ECCR[EBDF] to divide by two or divide by four if the system frequency is greater than 66 MHz. 2. System Frequency must be 132 MHz and SIU_ECCR[EBDF] set to divide by four. 3. Pad restrictions limit the maximum operating frequency. Table 42. Calibration bus interface maximum operating frequency Port Width Multiplexed Mode CAL_ADDR[12:15] Pin Usage CAL_ADDR[16:30] Pin Usage CAL_DATA[0:15] Pin Usage Max. Operating Frequency 16-bit Yes GPIO GPIO CAL_ADDR[12:30] CAL_DATA[0:15] 66 MHz(1) 16-bit No CAL_ADDR[12:15] CAL_ADDR[16:30] CAL_DATA[0:15] 66 MHz(1) 32-bit Yes CAL_WE[2:3] CAL_DATA[31] CAL_ADDR[16:30] CAL_DATA[16:30] CAL_ADDR[0:15] CAL_DATA[0:15] 66 MHz(1) 1. Set SIU_ECCR[EBDF] to divide by two or divide by four if the system frequency is greater than 66 MHz Table 43. External bus interface (EBI) and calibration bus operation timing (1) 66 MHz (ext. bus)(2) # Symbol C Characteristic Unit Min Max 1 TC CC P CLKOUT Period 15.2 — ns 2 tCDC CC D CLKOUT duty cycle 45% 55% TC ns 3 tCRT CC D CLKOUT rise time — (3) 4 tCFT CC D CLKOUT fall time — (3) ns 1.3 — ns CLKOUT Posedge to Output Signal Invalid or High Z(Hold Time) 5 tCOH 122/157 CC – – D – – – – – ADDR[8:31] CS[0:3] DATA[0:31] OE RD_WR TS WE[0:3]/BE[0:3] Doc ID 15399 Rev 9 Notes Signals are measured at 50% VDDE. SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics External bus interface (EBI) and calibration bus operation timing (1) (continued) Table 43. 66 MHz (ext. bus)(2) # Symbol C Characteristic Unit Min Max — 9 ns 6.0 — ns 1.0 — ns 6.5 — ns 1.5(5) — ns Notes CLKOUT Posedge to Output Signal Valid (Output Delay) 6 tCOV 7 tCIS CC CC ADDR[8:31] CS[0:3] D DATA[0:31] OE RD_WR TS WE[0:3]/BE[0:3] D Input Signal Valid to CLKOUT Posedge (Setup Time) DATA[0:31] CLKOUT Posedge to Input Signal Invalid (Hold Time) 8 tCIH CC D 9 tAPW CC D ALE Pulse Width(4) DATA[0:31] 10 tAAI CC D ALE Negated to Address Invalid4 1. External Bus and Calibration bus timing specified at fSYS = 150 MHz and 100 MHz, VDD = 1.14 V to 1.32 V, VDDE = 3 V to 3.6 V (unless stated otherwise), TA = TL to TH, and CL = 30 pF with DSC = 0b10. 2. The external bus is limited to half the speed of the internal bus. The maximum external bus frequency is 66 MHz for 16-bit muxed mode and 33 MHz for non-muxed mode. For The EBI division factor should be set accordingly based on the internal frequency being used. 3. Refer to Fast Pad timing in Table 35 and Table 36 (different values for 1.8 V vs. 3.3 V). 4. Measured at 50% of ALE. 5. When CAL_TS pad is used for CAL_ALE function the hold time is 1 ns instead of 1.5 ns. Voh_f VDDE/2 CLKOUT Vol_f 2 3 2 4 1 Figure 18. CLKOUT timing Doc ID 15399 Rev 9 123/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 VDDE/2 CLKOUT 6 5 VDDE/2 5 OUTPUT BUS VDDE/2 6 5 5 OUTPUT SIGNAL VDDE/2 6 OUTPUT SIGNAL VDDE/2 Figure 19. Synchronous output timing 124/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 CLKOUT Electrical characteristics VDDE/2 7 8 INPUT BUS VDDE/2 7 8 INPUT SIGNAL VDDE/2 Figure 20. Synchronous input timing System Clock CLKOUT ALE TS A/D DATA ADDR 9 10 Figure 21. ALE signal timing Doc ID 15399 Rev 9 125/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 3.17.5 External interrupt timing (IRQ pin) Table 44. External interrupt timing(1) # Characteristic 1 IRQ Pulse Width Low 2 IRQ Pulse Width High 3 IRQ Edge to Edge Time (2) Symbol Min Max Unit tIPWL 3 — tcyc tIPWH 3 — tcyc tICYC 6 — tcyc 1. IRQ timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH. 2. Applies when IRQ pins are configured for rising edge or falling edge events, but not both. IRQ 2 1 3 Figure 22. External Interrupt Timing 3.17.6 eTPU timing Table 45. eTPU timing(1) # Characteristic Symbol Min Max Unit 1 eTPU Input Channel Pulse Width tICPW 4 — tcyc 2 eTPU Output Channel Pulse Width tOCPW 2(2) — tcyc 1. eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 200 pF with SRC = 0b00. 2. This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR). 126/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 3.17.7 eMIOS timing Table 46. eMIOS timing(1) # Symbol C Electrical characteristics Characteristic Min. Value Max. Value Unit 1 tMIPW CC D eMIOS Input Pulse Width 4 — tCYC 2 tMOPW CC D eMIOS Output Pulse Width 1 — tCYC 1. eMIOS timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V, TA = TL to TH, and CL = 50 pF with SRC = 0b00. 3.17.8 DSPI timing DSPI channel frequency support for the SPC564A80 MCU is shown in Table 47. Timing specifications are in Table 48. Table 47. DSPI channel frequency support System Clock (MHz) DSPI Use Mode Max. Usable Frequency (MHz) LVDS 37.5 Use sysclock /4 divide ratio. Non-LVDS 18.75 Use sysclock /8 divide ratio. LVDS 40 Use sysclock /3 divide ratio. Gives 33/66 duty cycle. Use DSPI configuration DBR=0b1 (double baud rate), BR=0b0000 (scaler value 2) and PBR=0b01 (prescaler value 3). Non-LVDS 20 Use sysclock /6 divide ratio. LVDS 40 Use sysclock /2 divide ratio. Non-LVDS 20 Use sysclock /4 divide ratio. Notes 150 120 80 Table 48. # 1 DSPI timing(1),(2) Symbol tSCK CC C Characteristic D SCK Cycle Time(3),(4),(5) Condition Delay(6) Min. Max. Unit 24.4 ns 2.9 ms — 22(7) — ns 21(9) — ns (½tSC)–2 (½tSC)+2 ns 2 tCSC CC D PCS to SCK 3 tASC CC D After SCK Delay(8) 4 tSDC CC D SCK Duty Cycle 5 tA CC D Slave Access Time (SS active to SOUT driven) — 25 ns 6 tDIS CC D Slave SOUT Disable Time (SS inactive to SOUT High-Z or invalid) — 25 ns 7 tPCSC CC D PCSx to PCSS time 4(10) — ns 8 tPASC CC D PCSS to PCSx time 5(11) — ns Doc ID 15399 Rev 9 127/157 Electrical characteristics Table 48. # SPC564A74L7, SPC564A80B4, SPC564A80L7 DSPI timing(1),(2) (continued) Symbol C Characteristic Condition Min. Max. VDDEH=4.5–5.5 V 20 — VDDEH=3–3.6 V 23.5 — Unit Data Setup Time for Inputs D Master (MTFE = 0) D 9 tSUI CC D Slave 2 — D Master (MTFE = 1, CPHA = 0)(12) 8 — VDDEH=4.5–5.5 V 20 — VDDEH=3–3.6 V 23.5 — ns D Master (MTFE = 1, CPHA = 1) D Data Hold Time for Inputs 10 tHI CC D Master (MTFE = 0) -4 — D Slave 7 — D Master (MTFE = 1, CPHA = 0)(12) 21 — D Master (MTFE = 1, CPHA = 1) -4 — VDDEH=4.5–5.5 V — 5 VDDEH=3–3.6 V — 6.3 VDDEH=4.5–5.5 V — 25 VDDEH=3–3.6 V — 27 — 21 VDDEH=4.5–5.5 V — 5 VDDEH=3–3.6 V — 6.3 VDDEH=4.5–5.5 V –5 — VDDEH=3 –3.6 V –7.5 — 5.5 — 3 — VDDEH=4.5–5.5 V –5 — VDDEH=3–3.6 V –7.5 — ns Data Valid (after SCK edge) D Master (MTFE = 0) D D 11 tSUO Slave CC D D Master (MTFE = 1, CPHA = 0) D Master (MTFE = 1, CPHA = 1) D ns Data Hold Time for Outputs D Master (MTFE = 0) D 12 tHO CC D Slave D Master (MTFE = 1, CPHA = 0) ns D Master (MTFE = 1, CPHA = 1) D 1. All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on medium-speed pads. DSPI signals using slow pads have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3 to 3.6 V and VDDEH = 4.5 to 5.5 V, TA = TL to TH, and CL = 50 pF with SRC = 0b11. 2. Data is verified at fSYS = 102 MHz and 153 MHz (100 MHz and 150 MHz + 2% frequency modulation). 128/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics 3. The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated based on two SPC564A80 devices communicating over a DSPI link. 4. The actual minimum SCK cycle time is limited by pad performance. 5. For DSPI channels using LVDS output operation, up to 40 MHz SCK cycle time is supported. For non-LVDS output, maximum SCK frequency is 20 MHz. Appropriate clock division must be applied. 6. The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. 7. Timing met when pcssck = 3(01), and cssck =2 (0000). 8. The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. 9. Timing met when ASC = 2 (0000), and PASC = 3 (01). 10. Timing met when pcssck = 3. 11. Timing met when ASC = 3. 12. This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10. 2 3 PCSx 1 4 SCK Output (CPOL=0) 4 SCK Output (CPOL=1) 10 9 SIN First Data Data Last Data 12 SOUT First Data 11 Data Last Data Note: Refer to Table 48 for the numbers. Figure 23. DSPI classic SPI timing — master, CPHA = 0 Doc ID 15399 Rev 9 129/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 PCSx SCK Output (CPOL=0) 10 SCK Output (CPOL=1) 9 Data First Data SIN Last Data 12 SOUT 11 Data First Data Last Data Note: Refer to Table 48 for the numbers. Figure 24. DSPI classic SPI timing — master, CPHA = 1 3 2 SS 1 4 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN 12 Data Last Data Data Last Data 10 First Data Note: Refer to Table 48 for the numbers. 130/157 11 Doc ID 15399 Rev 9 6 SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics Figure 25. DSPI classic SPI timing — slave, CPHA = 0 SS SCK Input (CPOL=0) SCK Input (CPOL=1) 11 5 6 12 SOUT First Data 9 SIN Data Last Data Data Last Data 10 First Data Note: Refer to Table 48 for the numbers. Figure 26. DSPI classic SPI timing — slave, CPHA = 1 3 PCSx 4 1 2 SCK Output (CPOL=0) 4 SCK Output (CPOL=1) 9 SIN First Data 10 12 SOUT First Data Last Data Data 11 Data Last Data Note: Refer to Table 48 for the numbers. Doc ID 15399 Rev 9 131/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 Figure 27. DSPI modified transfer format timing — master, CPHA = 0 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) 10 9 SIN First Data Data 12 SOUT First Data Data Last Data 11 Last Data Note: Refer to Table 48 for the numbers. Figure 28. DSPI modified transfer format timing — master, CPHA = 1 132/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics 3 2 SS 1 SCK Input (CPOL=0) 4 4 SCK Input (CPOL=1) SOUT First Data Data First Data 6 Last Data 10 9 SIN 12 11 5 Data Last Data Note: Refer to Table 48 for the numbers. Figure 29. DSPI modified transfer format timing — slave, CPHA =0 Doc ID 15399 Rev 9 133/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 SS SCK Input (CPOL=0) SCK Input (CPOL=1) 11 5 12 First Data SOUT 9 Last Data Data Last Data 10 First Data SIN Data 6 Note: Refer to Table 48 for the numbers. Figure 30. DSPI modified transfer format timing — slave, CPHA =1 8 7 PCSS PCSx Note: Refer to Table 48 for the numbers. Figure 31. DSPI PCS strobe (PCSS) timing 134/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics 3.17.9 eQADC SSI timing Table 49. eQADC SSI timing characteristics (pads at 3.3 V or at 5.0 V)(1) CLOAD = 25 pF on all outputs. Pad drive strength set to maximum. # Symbol C Rating Min 1 fFCK CC D FCK Frequency (2), (3) 1 tFCK CC D FCK Period (tFCK = 1/ fFCK) Typ Max Unit 1/17 12 fSYS_CLK 2 17 tSYS_CLK 2 tFCKHT CC D Clock (FCK) High Time tSYS_CLK  6.5 9* tSYS_CLK  6.5 ns 3 tFCKLT CC D Clock (FCK) Low Time tSYS_CLK  6.5 8* tSYS_CLK  6.5 ns 4 tSDS_LL CC D SDS Lead/Lag Time -7.5 7.5 ns 5 tSDO_LL CC D SDO Lead/Lag Time -7.5 7.5 ns 6 tDVFE CC D Data Valid from FCK Falling Edge (tFCKLT+tSDO_LL) 1 ns 7 tEQ_SU CC D eQADC Data Setup Time (Inputs) 22 ns 8 tEQ_HO CC D eQADC Data Hold Time (Inputs) 1 ns 1. SS timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V, TA = TL to TH, and CL = 50 pF with SRC = 0b00. 2. Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays. 3. FCK duty is not 50% when it is generated through the division of the system clock by an odd number. 1 2 3 FCK 4 4 SDS 5 SDO 25th 6 1st (MSB) 5 2nd 26th External Device Data Sample at FCK Falling Edge 8 7 SDI 1st (MSB) 2nd 25th 26th eQADC Data Sample at FCK Rising Edge Figure 32. eQADC SSI timing Doc ID 15399 Rev 9 135/157 Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 3.17.10 FlexCAN system clock source Table 50. FlexCAN engine system clock divider threshold # Symbol Characteristic 1 FCAN_TH FlexCAN engine system clock threshold Table 51. Unit 100 MHz FlexCAN engine system clock divider System Frequency Required SIU_SYSDIV[CAN_SRC] Value FCAN_TH 1(2),(3) 1. Divides system clock source for FlexCAN engine by 1. 2. System clock is only selected for FlexCAN when CAN_CR[CLK_SRC] = 1. 3. Divides system clock source for FlexCAN engine by 2. 136/157 Value Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 4 Packages 4.1 ECOPACK Packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 15399 Rev 9 137/157 Packages SPC564A74L7, SPC564A80B4, SPC564A80L7 4.2 Package mechanical data 4.2.1 LQFP176 138/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Packages Figure 33. LQFP176 package mechanical drawing Doc ID 15399 Rev 9 139/157 Packages SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 52. LQFP176 package mechanical data MILLIMETERS(1) DATABOOK INCHES REF. TYP MIN MAX TYP MIN A MAX MIN 1.600 MAX 0.063 A1 0.050 0.150 0.002 A2 1.350 1.450 0.053 0.057 b 0.170 0.270 0.007 0.011 C 0.090 0.200 0.004 0.008 D 23.900 24.100 0.941 0.949 E 23.900 24.100 0.941 0.949 e 0.500 0.020 HD 25.900 26.100 1.020 1.028 HE 25.900 26.100 1.020 1.028 0.450 0.750 0.018 0.030 L (2) L1 1.000 0.039 ZD 1.250 0.049 ZE 1.250 0.049 ccc 0.080 0o ANGLE 7o 1. Controlling Dimension: MILLIMETER 2. L dimension is measured at gauge plane at 0.25 above the seating plane. 140/157 TYP Doc ID 15399 Rev 9 0.003 0 7o SPC564A74L7, SPC564A80B4, SPC564A80L7 BGA208 ddd C Seating plane A A A1 A4 A3 D B A2 D D1 e A F E E1 F T R P N M L K J H G F E D C B A e 4.2.2 Packages 1 3 2 5 4 7 6 9 8 A1 corner index area (See note 1) 11 13 15 10 12 14 16 b (208 balls) eee M C A B fff M C Bottom view 1. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. Table 53. LBGA208 mechanical data inches(1) mm Symbol Min Typ A(2) A1 Max Min Typ 1.70 0.30 0.0669 0.0118 A2 1.085 0.0427 A3 0.30 0.0118 A4 b(3) 0.80 0.50 Max 0.60 0.70 Doc ID 15399 Rev 9 0.0315 0.0197 0.0236 0.0276 141/157 Packages SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 53. LBGA208 mechanical data (continued) inches(1) mm Symbol D Min Typ Max Min Typ Max 16.80 17.00 17.20 0.6614 0.6693 0.6772 D1 E 15.00 16.80 17.00 0.5906 17.20 0.6614 0.6693 E1 15.00 0.5906 e 1.00 0.0394 F 1.00 0.0394 ddd eee (4) fff(5) 0.6772 0.20 0.0079 0.25 0.0098 0.10 0.0039 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. LBGA stands for Low profile Ball Grid Array. —Low profile: The total profile height (Dim A) is measured from the seating plane to the top of the component —The maximum total package height is calculated by the following methodology: A2 Typ+A1 Typ + (A12+A32+A42 tolerance values) — Low profile: 1.20mm < A < 1.70mm 3. The typical ball diameter before mounting is 0.60mm. 4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. 5. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones. 4.2.3 142/157 PBGA324 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Packages Figure 34. PBGA324 package mechanical drawing Doc ID 15399 Rev 9 143/157 Packages SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 54. PBGA324 package mechanical data mm inches Symbol MIN. A(1),(2),(3) A1 TYP. MAX. 1.720 0.270 A2 MIN. TYP. MAX. 1.620 1.720 1.820 0.350 0.400 0.450 1.320 1.320 b 0.550 0.6000 0.650 0.550 0.600 0.650 D 22.80 23.00 23.200 22.900 23.000 23.100 D1 E 21.00 22.800 E1 23.000 21.000 23.200 22.900 21.000 23.000 23.100 21.000 e 0.950 1.000 1.050 0.950 1.000 1.050 f 0.875 1.000 1.125 0.875 1.000 1.125 ddd 0.200 0.200 1. Max mounted height is 1.77mm.Based on 0.35mm ball pad diameter. Solder paste is 0.15mm thickness and 0.35mm diameter. 2. PBGA stands for Plastic Ball Grid Array. 3. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1corner. Exact shape of each corner is optional. 144/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 5 Ordering information Ordering information Table 55 shows the orderable part numbers for the SPC564A80 series. Table 55. Order codes Flash/SRAM Package Speed (MHz) SPC564A74L7CFA 3 MB/160 KB 176LQFP 150 SPC564A74B2CFA 3 MB/160 KB 208LBGA 150 SPC564A74B4CFA 3 MB/160 KB 324PBGA 150 SPC564A80L7CFC 4 MB/192 KB LQFP176 80 SPC564A80B2CFC 4 MB/192 KB LBGA208 80 SPC564A80B4CFC 4 MB/192 KB PBGA324 80 SPC564A80L7CFB 4 MB/192 KB LQFP176 120 SPC564A80B2CFB 4 MB/192 KB LBGA208 120 SPC564A80B4CFB 4 MB/192 KB PBGA324 120 SPC564A80L7CFA 4 MB/192 KB LQFP176 150 SPC564A80B2CFA 4 MB/192 KB LBGA208 150 SPC564A80B4CFA 4 MB/192 KB PBGA324 150 SPC564A80H1EFA 4 MB/192 KB KGD 150 Order code Doc ID 15399 Rev 9 145/157 Ordering information SPC564A74L7, SPC564A80B4, SPC564A80L7 Figure 35. Product code structure Example code: SPC56 4 A 80 L5 C F Product identifier Core Family Memory Package Temperature Custom vers. A Y Max Freq. Conditioning Y = Tray R = Tape and Reel A = 150 MHz B = 120 MHz C = 80 MHz F = Optional Flexray controller B = –40 to 105 °C C = –40 to 125 °C B2 = LBGA208 B4 = PBGA324 L7 = LQFP176 H1 = Known Good Die 80 = 4 MB 74 = 3 MB A = SPC564A80 family 4 = e200z4 SPC56 = Power Architecture in 90 nm 146/157 Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 6 Document revision history Table 56. Revision history Document revision history Date Revision 23-Feb-2009 1 Initial release 2 Maximum device speed is 145 MHz (was 150 MHz) 16-entry Memory Protection Unit (MPU). Was incorrectly listed as 8-entry. 288-ball BGA package deleted Feature details section added Changes to signal summary table: – Added ANY function to AN[10] – Added ANW function to AN[8] Changes to 208 ball BGA ballmap: – A12 is AN12-SDS (was AN12) – A15 is VRC33 (was VDD33) – B12 is AN13-SDO (was AN13) – C12 is AN14SDI (was AN14) – C13 is AN15-FCK (was AN15) – D1 is VRC33 (was VDD33) – F13 is VDDEH6AB (was VDDEH6) – H13 is GPIO99 (was PCSA3) – J15 is GPIO98 (was PCSA2) – K4 is now VDDEH1AB (was VDDEH1) – N6 is now VRC33 (was VDD33) – N9 is VDDEH4AB (was VDDEH4) – N12 is now VRC33 (was VDD33) – P6 is now NC – T13 is VDDE5 (was NC) Changes to 324 ball BGA ballmap: – A6 is VDDA (was VDDA1) – A7 is VSSA (was VSSA1) – A15 is VSSA (was VSSA0) – A16 is AN12_SDS (was AN12) – A17 is MDO11_ETPUA29O (was MDO11) – A18 is MDO10_ETPUA27O (was MDO10) – A19 is MDO8_ETPUA21O (was MDO8) – A21 is VRC33 (was VDD33) – B1 is VRC33 (was VDD33) – B15 is VSSA (was VSSA0) – B16 is AN13_SDO (was AN13) – B17 is MDO9_ETPUA25O (was MDO9) – B18 is MDO7_ETPUA19O (was MDO7) – B19 is MDO4_ETPUA2O (was MDO4) – B22 is NIC (was VDDE7) 09-Dec-2009 Changes Doc ID 15399 Rev 9 147/157 Document revision history Table 56. Revision history (continued) Date 09-Dec-2009 148/157 SPC564A74L7, SPC564A80B4, SPC564A80L7 Revision 2 Changes – C4 is VDD (was VDDEH1A) – C15 is VDDA (was VDDA0) – C16 is AN14_SDI (was AN14) – C17 is MDO5_ETPUA4O (was MDO5) – C21 is NIC1 (was VDDE7) – D15 is VDDEH7 (was VDDEH9) – D16 is AN15_FCK (was AN15) – D17 is MDO6_ETPUA13O (was MDO6) – D20 is NIC (was VDDE7) – E19 is NIC (was VDDE7) – E22 is NIC (was NC) – F19 is NIC (was VDDE7) – H4 is VDDEH1AB (was VDDEH1A) – H19 is VDDEH6AB (was VDDEH10) – J14 is NIC (was VDDE7) – K19 is GPIO99 (was PCSA3) – M9 is VDDE2 (was VDD2) – M21 is GPIO98 (was PCSA2) – M22 is VDDREG (was NC) – N22 is NIC (was NC) – P2 is ADDR17 (was ADD17) – P4 is VRC33 (was VDD33) – R3 is VDDE-EH (was VDDE2) – T21 is VSS (was VRCVSS) – T22 is VSS (was VSSPLL) – U19 is VDDEH6AB (was VDDEH6A) – W2 is VDDE-EH (was VDDE2) – W7 is VRC33 (was VDD33) – W14 is VDDEH4AB (was VDDEH4B) – W21 is NIC (was VRC33) – Y22 is VRC33 (was VDD33) – AB22 is VSS (was VSSPLL) Recommended operating characteristics for power transistor updated Pad current specifications updated LVDS pad specifications updated. SRC does not apply to common mode voltage. Temperature sensor electrical characteristics added eQADC electrical characteristics updated with VGA gain specs Pad AC specifications updated Definition for RDY signal added to signal details VSTBY maximum is 5.5 V (was listed incorrectly as 6.0 V) IMAXA maximum is 5 mA (was TBD) Analog differential input functions added to AN0–AN7 in signal summary Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 56. Document revision history Revision history (continued) Date 02-Apr-2010 Revision Changes 3 Internal release. Changes to Signal Properties table (changes apply to Revision 2 and later devices: EBI changes: – WE_BE[2] (A2) and CAL_WE_BE[2] (A3) signals added to CS[2] (PCR 2) – WE_BE[3] (A2) and CAL_WE_BE[3] (A3) signals added to CS[3] (PCR 3) Calibration bus changes: – CAL_WE[2]/BE[2] (A2) signal added to CAL_CS[2] (PCR 338) – CAL_WE[3]/BE[3] (A2) signal added to CAL_CS[3] (PCR 339) – CAL_ALE (A1) added to CAL_ADDR[15] (PCR 340) eQADC changes: – AN[8] and AN[38] pins swapped. AN[8] Is now on pins 9 (176-pin), B3 (208-ball) and D6 (324-ball). AN[8] was on C5 (324-ball) on previous devices. AN[38] Is now on C5 (324-ball). AN[38] was on pins 9 (176-pin), B3 (208-ball) and D6 (324-ball) on previous devices. – ANZ function added to AN11 pin Reaction channels added to eTPU2: – RCH0_A (A3) added to ETPU_A[14] (PCR 128) – RCH0_B (A2) added to ETPU_A[20] (PCR 134) – RCH0_C (A2) added to ETPU_A[21] (PCR 135) – RCH1_A (A2) added to ETPU_A[15] (PCR 129) – RCH1_B (A2) added to ETPU_A[9] (PCR 123) – RCH1_C (A2) added to ETPU_A[10] (PCR 124) – RCH2_A (A2) added to ETPU_A[16] (PCR 130) – RCH3_A (A2) added to ETPU_A[17] (PCR 131 – RCH4_A (A2) added to ETPU_A[18] (PCR 132)) – RCH4_B (A2) added to ETPU_A[11] (PCR 125) – RCH4_C (A2) added to ETPU_A[12] (PCR 126) – RCH5_A (A2) added to ETPU_A[19] (PCR 133) – RCH5_B (A2) added to ETPU_A[28] (PCR 142) – RCH5_C (A2) added to ETPU_A[29] (PCR 143) Reaction channels added to eMIOS: – RCH2_B (A2) added to EMIOS[2] (PCR 181) – RCH2_C (A2) added to EMIOS[4] (PCR 183) – RCH3_B (A2) added to EMIOS[10] (PCR 189) – RCH3_C (A2) added to EMIOS[11] (PCR 190) Pad changes: – ETPUA16 (PCR 130) has Medium (was Slow) pad – ETPUA17 (PCR 131) has Medium (was Slow) pad – ETPUA18 (PCR 132) has Medium (was Slow) pad – ETPUA19 (PCR 133) has Medium (was Slow) pad – ETPUA25 (PCR 139) has Slow+LVDS (was Medium+LVDS) pads Doc ID 15399 Rev 9 149/157 Document revision history Table 56. Revision history (continued) Date 02-Apr-2010 (cont) 150/157 SPC564A74L7, SPC564A80B4, SPC564A80L7 Revision Changes 3 (cont) Signal Details table updated: – Added eTPU2 reaction channels – Changed IRQ[0:15] to two ranges, excluding IRQ6, which does not exist on this device – Changed TCR_A to TCRCLKA (TCR_A is the pin name, not the signal name) – Changed WE_BE[0:1] to WE_BE[0:3] (2 new signals added to Rev. 2). Also changed notation from “WE_BE[n]” to “WE[n]/BE[n]” to be consistent. Changes to Power/ground segmentation table: – ADDR[20:21] removed from VDDE2 segment; they are in VDDE-EH – CAL_CS1 removed from VDDE12 segment (there is no CAL_CS1 on this device) – CAL_EVTO and CAL_MCKO removed from VDDE12 segment. Those pins do not exist – VDDE-VDDEH renamed to VDDE-EH – EMIOS24 removed from VDDEH segment. That pin does not exist. – ETPUA[0:9] added to VDDEH4 segment – Renamed TCR_A in VDDEH4 segment to TCRCLKA. – EXTAL and XTAL added to VDDEH6 segment – AN15-FCK added to VDDEH7 segment – GPIO98, GPIO99, GPIO206, GPIO207 and GPIO219 added to VDDEH7 segment. – MSEO1 added to VDDEH7 segment – Power segment VDDEH1A renamed to VDDEH1 Changes to 176-pin package pinout: – Changed pin 9 from AN38 to AN8. – Added note that pin 96 (VSS) should be tied low. Changes to 208-ball package ballmap: – Changed ball B3 from AN38 to AN8. – Added note that ball N13 (VSS) should be tied low. 324-ball package ballmap updated for Rev. 2 silicon – Renamed VDDA (A6) to VDDA0 – Renamed VSSA (A7) to VSSA0 – AN8 was on ball C5; it is now on D6 – AN38 was on ball D6; it is now on C5 – Renamed VSSA (A15) to VSSA1 – Renamed VDDA (C15) to VDDA1 – Rename VSSA (B15) to VSSA1 BGA288 package is no longer offered Changes to features list: – Correction: there are 6 reaction channels (was noted as 5) – Development Trigger Semaphore (DTS) added to features list and feature details – FlexRay module now has 128 message buffers (was 64) and ECC support Added note after JTAG pin AC electrical characteristics table detailing JTAG EVTI and RDY signal clocking with TCK. This affects debuggers. Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 56. Document revision history Revision history (continued) Date 02-Apr-2010 (cont) 01-Oct-2010 Revision Changes 3 (cont) Added information to AC timings section: – New section added: Reset and configuration pin timing – New section added: External interrupt timing (IRQ pin) – New section added: eTPU timing – Added Nexus debug port operating frequency table to Nexus timings section – Added external bus interface maximum operating frequency table and calibration bus interface maximum operation frequency table – Added FlexCAN system clock source section Changes to Power management control (PMC) and power on reset (POR) electrical specifications: – Max value for parameter 2 (vddreg) is 5.25 V (was 5.5 V) Updated “Core voltage regulator controller external components preferred configuration” diagram. Changes to DC electrical specifications table: – Slew rate on power supply pins (system requirement) changed to 25 V/ms (was 50 V/ms) Throughout the document the maximum frequency is now 150 MHz (was 145 MHz) Changes to DC electrical specifications: – Parameter classifications added – VDDREG max value changed to 5.25 V (was 5.5 V) – VOH_LS min value changed to 2.0 V (was 2.7 V) with a load current of 0.5 mA – VOL_LS max value changed to 0.6 V (was 0.2*VDDEH) with load current of 2 mA – VINDC min value changed to VSSA-0.3 (was VSSA-1.0) – VINDC max value changed to VDDA+0.3 (was VDDA+1.0) Added new section: Configuring SRAM wait states – VRCCTL external circuit updated. 4 Updates to Nexus timings: – tMDOV max value changed to 0.35 (was 0.2) – tMSEOV max value changed to 0.35 (was 0.2) – tEVTOV max value changed to 0.35 (was 0.2) Updates to DC electrical specifications: – VSTBY min value changed to 0.95 V (was 0.9 V) – VSTBY has two ranges—for regulated mode and unregulated mode Correction to PLLMRFM electrical specifications: – VDDPLL range is from 1.08 V to 3.6 V (was 3.0 V to 3.6 V. Updates to pad AC specifications: – Specs with drive load = 200 pF deleted. DSC (drive strength control) values range from 10 – 50 pF. – I/O pad average IDDE specifications updated (fast pad specs only) – I/O pad VRC33 average IDDE specifications (fast pad specs only) Updates to Reset and configuration pin timings: – Footnote added: RESET pulse width is measured from 50% of the falling edge to 50% of the rising edge. – Timings are specified at VDD = 1.14 V to 1.32 V (was 1.08 V to 1.32 V). Doc ID 15399 Rev 9 151/157 Document revision history Table 56. Revision history (continued) Date 01-Oct-2010 (cont) 10-Feb-2011 152/157 SPC564A74L7, SPC564A80B4, SPC564A80L7 Revision Changes 4 (cont) Updates to EBI timings: – Note added to tAAI: When CAL_TS is used as CAL_ALE the hold time is 1 ns instead of 1.5 ns. – Correction: maximum calibration bus interface operating frequency is 66 MHz for all port configurations. – VDDE range in footnote 1 corrected to read, “External Bus and Calibration bus timing specified at fSYS = 150 MHz and 100 MHz, VDD = 1.14 V to 1.32 V, VDDE = 3 V to 3.6 V (unless stated otherwise)” (VDDE range was 1.62 V to 3.6 V) Correction to IEEE 1149.1 timings: – SRC value in footnote 1 corrected to read, “JTAG timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V with multi-voltage pads programmed to LowSwing mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b11.” (SRC value was 0b00) Correction to External interrupt timing (IRQ pin) timings: – Timings are specified at VDD = 1.14 V to 1.32 V (was 1.08 V to 1.32 V). Update to DSPI timings: – Some of the timing parameters can vary depending on the value of VDDE. For these parameters, ranges are now defined for two ranges of VDDE. Change in signal name notation for DSPI, CAN and SCI signals: – DSPI: PCS_x[n] is now DSPI_x_PCS[n] SOUT_x is now DSPI_x_SOUT SIN_x is now DSPI_x_SIN SCK_x is now DSPI_x_SCK – CAN: CNTXx is now CAN_x_TX CNRXx is now CAN_x_RX – SCI: RXDx is now SCI_x_RX TXDx is now SCI_x_TX Updates to DC electrical specifications: – Slew rate on power supply pins specification changed to 25 V/ms (was 50 V/ms) VOH_LS min spec changed to 2.0 V at 0.5 mA (was 2.7 V at 0.5 mA) Updated I/O pad current specifications Updated I/O pad VRC33 current specifications Corrections to Nexus timing: – Maximum Nexus debug port operating frequency is 40 MHz in all configurations – To route Nexus to MDO, clear NPC_PCR[NEXCFG] (formerly this was documented as NPC_PCR[CAL] – To route Nexus to CAL_MDO, set NPC_PCR[NEXCFG]=1 (formerly this was documented as NPC_PCR[CAL] 5 – – – – Minor editorial updates. Re-organized the first few subsections of the “Overview” section. Added ECSM to the block diagram. Added information on the REACM, SIU, and ECS modules to the “Block summary” section. Doc ID 15399 Rev 9 SPC564A74L7, SPC564A80B4, SPC564A80L7 Table 56. Document revision history Revision history (continued) Date Revision Changes – – – – – – – – – – – – – – – – 10-Feb-2011 (cont) 5 (cont) – – – – – – – – – – – – – Added DATA[0:15] to VDDE5 in the “signal properties” table. Updated VSTBY parameters in the “Power/ground segmentation” table. Updated the parameter symbols and classifications throughout the document. Updated footnote instances in the “Absolute maximum ratings“ table. Removed IMAXA footnote in the “Absolute Maximum Ratings” table. Updated the format of the “EMI (electromagnetic interference) characteristics” table. Removed the footnote on VDDREG in the “Power management control (PMC) and power on reset (POR) electrical specifications“ table. Updated values for Vbg, Idd3p3, Por3.3V_r, Por3.3V_f, Por5V_r, and Por5V_f in the “PMC electrical characteristics” table. Updated “Bandgap reference supply voltage variation” in the “PMC Electrical Characteristics” table. Removed the “VRC electrical specifications” table as it contained redundant information. Updated VCESAT and VBEin the “Recommended power transistors” operating characteristics” table. Updated VIH_LS in the “DC electrical specifications” table. Updated the VOH_LS min value in the “DC electrical specifications” table. Updated IDDSTBY and IDDSTBY150 in the “DC electrical specifications” table. Updated the IDDA/IREF/IDDREG max value in the “DC electrical specifications” table. Updated IACT_F, IACT_MV_PU, IACT_MV_PD, RPUPD5K, RPUPDMTCH, and footnotes in the “DC electrical specifications” table. Updated Medium pad type IDD33 values in the “I/O pad VRC33 average IDDE specifications” table. Updated values for VOD in the “DSPI LVDS pad specification“ table. Removed the footnotes from the “DSPI LVDS pad specifications“ table. Removed the redundant “XTAL Load Capacitance” parameter instance from the “PLLMRFM electrical specifications” table. Updated footnotes in the “PLLMRFM electrical specifications” table. Updated values for OFFNC and GAINNC in the “eQADC conversion specifications (operating)“ table. Added DIFFmax, DIFFmax2, DIFFmax4, and DIFFcmv parameters to the “eQADC conversion specifications (operating)” table. Added the maximum operating frequency values in the “Cutoff frequency for additional SRAM wait state” table. Updated multiple entries in the “APC, RWSC, WWSC settings vs. frequency of operation” table. Removed footnote in the “APC, RWSC, WWSC settings vs. frequency of operation” table. Updated the Typical values for Tdwprogram,, Tpprogram, and T16kpperase, and updated the Initial Max values for T128kpperase and T256kpperase in the “Flash program and erase specifications” table. Changed the voltage in the “Pad AC specifications” table title from 4.5 V to 5.0 V. Added the maximum LH/HL output delay values for pad type MultiV in the “Pad AC specifications (VDDE = 3.3 V)“ table. Doc ID 15399 Rev 9 153/157 Document revision history Table 56. Revision history (continued) Date 03-Feb-2012 154/157 SPC564A74L7, SPC564A80B4, SPC564A80L7 Revision Changes 6 – Minor editorial changes. – In Section 1.4: SPC564A80 feature list, moved “24 unified channels” after “1 x eMIOS”. – In Table 4 updated the following rows: DSPI_D_SCK /GPIO [98] -Changed “-” to CS[2] DSPI_D_SIN /GPIO[99] -Changed “-” to CS[3]. – In Table 12 Column “Value” added conditional text. – In Table 21 made the following changes: -For the value “VOL_S” parameter changed from “Slow/ medium/multi-voltage pad I/O output low voltage” to “Slow/medium pad I/O output low voltage”. -Added a new row for “IDDSTBY27”. -For row “IDDSTBY(operating current 0.95 -1.2V)” added max value “100” and changed typ value from “125” to “35”. -For row “IDDSTBY (operating current 2 - 5.5V)” added max value “110” and changed typ value from “135” to “45”. -For symbol “IDDSTBY 150(operating current 0.95 -1.2V)” added max value “2000”, changed typ value from “1050” to “790”,C cell changed from “T” to “P” and for symbol “IDDSTBY (operating current 2 - 5.5V)” added max value “2000”, changed typ value from “1050” to “760”, C cell changed from “T” to “P”. -Removed note 9 and note 10 (Characterization based capability) from symbol “VOL_HS”. – Splitted Table 28: eQADC conversion specifications (operating) into Table 29: eQADC single ended conversion specifications (operating) and Table 30: eQADC differential ended conversion specifications (operating) – In Table 30: eQADC differential ended conversion specifications (operating) made the following changes: -Added the note of DIFFcmv on all of the DIFF specs. -Min value changed from (VRH-VRL)/2-5% to (VRH+VRL)/2-5 % and max value changed from (VRH-VRL)/2+5% to (VRH+VRL)/2+5%for DIFFcmv. – In Table 31: Cutoff frequency for additional SRAM wait state made the following changes: -Added note “Max frequencies including 2% PLL FM”. -Max operating frequency changed from “96” to “98” and “150” to “153”. – In Section 3.13: Configuring SRAM wait states, changed text from “SPC564A80 4M Microcontroller Reference Manual “ to “device reference manual”. – In Table 32: APC, RWSC, WWSC settings vs. frequency of operation, - Added note for “Max Flash Operating Frequency(MHz). - Changed values from 30, 60,120, 150 to 20,61,123, 153 respectively in Max Flash Operating Frequency (MHz). – In Table 33: Flash program and erase specifications, added two parameter “Tpsrt” and “Tesrt”. – In Table 41: External Bus Interface maximum operating frequency, replacedthe
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