SPC56EL70L3, SPC56EL70L5,
SPC564L70L3, SPC564L70L5
32-bit Power Architecture®microcontroller for automotive
SIL3/ASILD chassis and safety applications
Datasheet - production data
LQFP144 (20 x 20 x 1.4 mm)
LQFP100 (14 x 14x 1.4 mm)
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Replicated junction temperature sensor
Non Maskable Interrupt (NMI)
16-region Memory Protection Unit (MPU)
Clock Monitoring Units (CMU)
Power Management Unit (PMU)
Cyclic Redundancy Check (CRC) unit
Decoupled Parallel mode for high performance
use of replicated cores
Features
Nexus Class 3+ interface
High-performance e200z4d dual core
– 32-bit Power Architecture® technology
CPU
– Core frequency as high as 120 MHz
– Dual issue five-stage pipeline core
– Variable Length Encoding (VLE)
– Memory Management Unit (MMU)
– 4 KB instruction cache with error detection
code
– Signal Processing Engine (SPE)
Interrupts
– Replicated 16-priority controller
– Replicated 16-channel eDMA controller
Memory available
– 2 MB flash memory with ECC
– 192 KB on-chip SRAM with ECC
– Built-in RWW capabilities for EEPROM
emulation
SIL3/ASILD innovative safety concept: Lock
step mode and Fail-safe protection
– Sphere of Replication (SoR) for key
components (such as CPU core, eDMA,
crossbar switch)
– Fault Collection and Control Unit (FCCU)
– Redundancy Control and Checker Unit
(RCCU) on outputs of the SoR connected
to FCCU
– Boot-time Built-In Self-Test for Memory
(MBIST) and Logic (LBIST) triggered by
hardware
– Boot-time Built-In Self-Test for ADC and
flash memory triggered by software
– Replicated safety enhanced watchdog
July 2015
This is information on a product in full production.
GPIOs individually programmable as input,
output or special function
Three 6-channel general-purpose eTimer units
2 FlexPWM units: Four 16-bit channels per
module
Communications interfaces
– 2 LINFlexD channels
– 3 DSPI channels with automatic chip select
generation
– 3 FlexCAN interfaces (2.0B Active) with 32
message objects
– FlexRay module (V2.1 Rev. A) with 2
channels, 64 message buffers and data
rates up to 10 Mbit/s
Two 12-bit Analog-to-digital Converters (ADC)
– 16 input channels
– Programmable Cross Triggering Unit (CTU)
to synchronize ADCs conversion with timer
and PWM
Sine wave generator (D/A with low pass filter)
On-chip CAN/UART/FlexRay Bootstrap loader
Single 3.0 V to 3.6 V voltage supply
Ambient temperature range –40 °C to 125 °C
Junction temperature range –40 °C to 150 °C
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Contents
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Contents
1
2/128
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3
Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.5
Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.1
High-performance e200z4d core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.2
Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.3
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.4
Enhanced direct memory access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.5
On-chip flash memory with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.6
On-chip SRAM with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.7
Platform flash memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.8
Platform static RAM controller (SRAMC) . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.9
Memory subsystem access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.10
Error correction status module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.11
Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.12
Interrupt controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.13
System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.14
Frequency-Modulated Phase-Locked Loop (FMPLL) . . . . . . . . . . . . . . 18
1.5.15
Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.16
Internal reference clock (RC) oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.17
Clock, reset, power, mode and test control modules (MC_CGM,
MC_RGM, MC_PCU, and MC_ME) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.18
Periodic interrupt timer module (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.19
System timer module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.20
Software watchdog timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.21
Fault collection and control unit (FCCU) . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.22
System Integration Unit Lite (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.23
Non-maskable interrupt (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.24
Boot assist module (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.25
System status and configuration module (SSCM) . . . . . . . . . . . . . . . . . 21
1.5.26
FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.27
FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Contents
1.5.28
Serial communication interface module (LINFlexD) . . . . . . . . . . . . . . . 24
1.5.29
Deserial serial peripheral interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 25
1.5.30
FlexPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.31
eTimer module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.32
Sine wave generator (SWG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.33
Analog-to-Digital converter module (ADC) . . . . . . . . . . . . . . . . . . . . . . 28
1.5.34
Cross triggering unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.35
Cyclic redundancy checker (CRC) unit . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.5.36
Redundancy control and checker unit (RCCU) . . . . . . . . . . . . . . . . . . . 29
1.5.37
Junction temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.38
Nexus port controller (NPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.39
IEEE 1149.1 JTAG controller (JTAGC) . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.40
Voltage regulator / power management unit (PMU) . . . . . . . . . . . . . . . . 31
1.5.41
Built-In self-test (BIST) capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 33
2.1
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.3
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.4
Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.4
Decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.5
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.5.1
General notes for specifications at maximum junction temperature . . . 79
3.6
Electromagnetic Interference (EMI) characteristics . . . . . . . . . . . . . . . . . 81
3.7
Electrostatic discharge (ESD) characteristics . . . . . . . . . . . . . . . . . . . . . 82
3.8
Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.9
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 83
3.10
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.11
Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . 90
3.12
Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
3.13
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.14
16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . 93
3.15
ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.15.1
3.16
Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.17
SWG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.18
AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.18.1
3.19
3.20
4
Input Impedance and ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.19.1
Reset sequence duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.19.2
Reset sequence description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.19.3
Reset sequence trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.19.4
Reset sequence — start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.19.5
External watchdog window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.20.1
RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.20.2
WKUP/NMI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.20.3
IEEE 1149.1 JTAG interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.20.4
Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
3.20.5
External interrupt timing (IRQ pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.20.6
DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
SPC56XL70/SPC56X64 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Platform memory access time summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LQFP100 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
LQFP144 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Thermal characteristics for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Thermal characteristics for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
EMI configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
EMI emission testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ESD ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Recommended operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Voltage regulator electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Current consumption characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Flash memory program and erase electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 99
Flash memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SPC56XL70 SWG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Pad AC specifications (3.3 V, IPP_HVE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
RESET sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Reset sequence trigger — Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
WKUP/NMI glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
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List of figures
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
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SPC56EL70 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPC56XL70 LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SPC56XL70 LQFP144 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
BCP68 board schematic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Input Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Transient Behavior during Sampling Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Destructive Reset Sequence, BIST enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Destructive Reset Sequence, BIST disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
External Reset Sequence Long, BIST enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Functional Reset Sequence Long. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Functional Reset Sequence Short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Reset sequence start for destructive resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Reset sequence start via RESET assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Reset sequence - External watchdog trigger window position . . . . . . . . . . . . . . . . . . . . . 108
Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Nexus DDR Mode output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
DSPI classic SPI timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
DSPI classic SPI timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
DSPI classic SPI timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
DSPI classic SPI timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
DSPI modified transfer format timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . 118
DSPI modified transfer format timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . 119
DSPI modified transfer format timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 119
DSPI modified transfer format timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 120
DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
1
Introduction
1.1
Document overview
Introduction
This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the devices.
This document provides electrical specifications, pin assignments, and package diagrams
for the SPC56EL70x/SPC564L70x series of microcontroller units (MCUs). For functional
characteristics, see the SPC56XL70 Microcontroller Reference Manual. For use of the
SPC56XL70 in a fail-safe system according to safety standard ISO26262, see the Safety
Application Guide for SPCEL70.
1.2
Description
The SPC56EL70x/SPC564L70x series microcontrollers are system-on-chip devices that are
built on Power Architecture technology and contain enhancements that improve the
architecture’s fit in embedded applications, include additional instruction support for digital
signal processing (DSP) and integrate technologies such as an enhanced time processor
unit, enhanced queued analog-to-digital converter, Controller Area Network, and an
enhanced modular input-output system.
The SPC56EL70x/SPC564L70x family of 32-bit microcontrollers is the latest achievement in
integrated automotive application controllers. It belongs to an expanding range of
automotive-focused products designed to address electrical hydraulic power steering
(EHPS), electric power steering (EPS) and airbag applications. The advanced and costefficient host processor core of the SPC56XL70 automotive controller family complies with
the Power Architecture embedded category. It operates at speeds as high as 120 MHz and
offers high-performance processing optimized for low power consumption. It capitalizes on
the available development infrastructure of current Power Architecture devices and is
supported with software drivers, operating systems and configuration code to assist with
users’ implementations.
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1.3
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Device comparison
Table 1. SPC56XL70/SPC56X64 device summary
Feature
SPC56EL64
SPC56EL70
SPC564L64
SPC564L70
Type
2 × e200z4
(in lock-step or
decoupled
operation)
2 × e200z4
(in lock-step or
decoupled
operation)
1 × e200z4
1 × e200z4
Architecture
Harvard
Execution
speed
0–120 MHz (+2% FM)
DMIPS intrinsic
performance
>240 MIPS
SIMD
(DSP + FPU)
CPU
Yes
MMU
16 entry
Instruction set
PPC
Yes
Instruction set
VLE
Yes
Instruction
cache
4 KB, EDC
MPU-16
regions
Yes, replicated module
Semaphore unit
(SEMA4)
Yes
Core bus
Buses
Crossbar
Memory
8/128
AHB, 32-bit address, 64-bit data
Internal
periphery bus
Master × slave
ports
32-bit address, 32-bit data
Lock Step Mode: 4 × 3
Decoupled Parallel Mode: 6 × 3
4x3
Code/data flash
1.5 MB, ECC,
RWW
2 MB, ECC, RWW
1.5 MB, ECC, RWW
2 MB, ECC, RWW
Static RAM
(SRAM)
160 KB, ECC
192 KB, ECC
160 KB, ECC
192 KB, ECC
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Introduction
Table 1. SPC56XL70/SPC56X64 device summary (continued)
Feature
Interrupt
Controller
(INTC)
SPC56EL70
SPC564L64
1 × 4 channels
System Timer
Module (STM)
1 × 4 channels, replicated module
eDMA
Yes, replicated module
16 channels, replicated module
FlexRay
1 × 64 message buffers, dual channel
FlexCAN
3 × 32 message buffers
LINFlexD
(UART and LIN
with DMA
support)
2
Clock out
Yes
Fault Collection
and Control
Unit (FCCU)
Yes
Cross
Triggering Unit
(CTU)
Yes
eTimer
SPC564L70
16 interrupt levels, replicated module
Periodic
Interrupt Timer
(PIT)
Software
Watchdog
Timer (SWT)
Modules
SPC56EL64
3 × 6 channels(1)
FlexPWM
2 Module 4 × (2 + 1) channels(2)
Analog-toDigital
Converter
(ADC)
2 × 12-bit ADC, 16 channels per ADC
(3 internal, 4 shared and 9 external)
Sine Wave
Generator
(SWG)
32 point
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Table 1. SPC56XL70/SPC56X64 device summary (continued)
Feature
Modules
(cont.)
SPC56EL70
SPC564L64
Deserial Serial
Peripheral
Interface (DSPI)
3 × DSPI as many as 8 chip selects
Cyclic
Redundancy
Checker (CRC)
unit
Yes
Junction
temperature
sensor
(TSENS)
Yes, replicated module
Digital I/Os
16
Device power
supply
Supply
SPC56EL64
Analog
reference
voltage
3.3 V with integrated bypassable ballast transistor
External ballast transistor not needed for bare die
3.0 V – 3.6 V and 4.5 V – 5.5 V
Frequencymodulated
phase-locked
loop (FMPLL)
Clocking
2
Internal RC
oscillator
External crystal
oscillator
SPC564L70
16 MHz
4 – 40 MHz
Debug
Nexus
Level 3+
Package
s
LQFP
100 pins
144 pins
Temperature
range (junction)
–40 to 150 °C
Ambient
Temperat temperature
ure
range using
external ballast
transistor
(LQFP)
–40 to 125 °C
1. The third eTimer is not connected to any pins on the package. Its usage is confined internally to the device.
2. The second FlexPWM is not connected to any pins on the package. Its usage is confined internally to the device.
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1.4
Introduction
Block diagram
Figure 1 shows a top-level block diagram of the SPC56EL70x/SPC564L70x device.
Figure 1. SPC56EL70 block diagram
PMU
JTAG
Nexus
e200z4
SWT
ECSM
STM
INTC
SPE
VLE
VLE
ECSM
STM
INTC
MMU
FlexRay
I-CACHE
eDMA
SWT
SPE
MMU
SEMA4
e200z4
SEMA4
I-CACHE
eDMA
RC
Crossbar Switch
Crossbar Switch
Memory Protection Unit
Memory Protection Unit
ECC logic for SRAM
ECC logic for SRAM
PBRIDGE
RC
TSENS
PBRIDGE
RC
Flash memory
ECC bits + logic
TSENS
SRAM
ECC bits
ADC
BAM
CMU
CRC
CTU
DSPI
ECC
ECSM
eDMA
FCCU
FlexCAN
FMPLL
INTC
IRCOSC
JTAG
– Analog-to-Digital Converter
– Boot Assist Module
– Clock Monitoring Unit
– Cyclic Redundancy Check unit
– Cross Triggering Unit
– Serial Peripherals Interface
– Error Correction Code
– Error Correction Status Module
– Enhanced Direct Memory Access controller
– Fault Collection and Control Unit
– Controller Area Network controller
– Frequency Modulated Phase Locked Loop
– Interrupt Controller
– Internal RC Oscillator
– Joint Test Action Group interface
LINFlexD
MC
PBRIDGE
PIT
PMU
RC
RTC
SEMA4
SIUL
SSCM
STM
SWG
SWT
TSENS
XOSC
DocID023953 Rev 5
PIT
FCCU
SWG
CRC
DSPI
DSPI
DSPI
LINFlexD
LINFlexD
FlexCAN
FlexCAN
FlexCAN
eTimer
eTimer
eTimer
FlexPWM
FlexPWM
CMU
CTU
CMU
CMU
IRCOSC
ADC
ADC
Secondary FMPLL
SIUL
FMPLL
SSCM
XOSC
WakeUp
BAM
MC
RC
– LIN controller with DMA support
– Mode Entry, Clock, Reset, & Power
– Peripheral bridge
– Periodic Interrupt Timer
– Power Management Unit
– Redundancy Checker
– Real Time Clock
– Semaphore Unit
– System Integration Unit Lite
– System Status and Configuration Module
– System Timer Module
– Sine Wave Generator
– Software Watchdog Timer
– Temperature Sensor
– Crystal Oscillator
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SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
1.5
Feature details
1.5.1
High-performance e200z4d core
The e200z4d Power Architecture® core provides the following features:
2 independent execution units, both supporting fixed-point and floating-point operations
Dual issue 32-bit Power Architecture technology compliant
–
5-stage pipeline (IF, DEC, EX1, EX2, WB)
–
In-order execution and instruction retirement
Full support for Power Architecture instruction set and Variable Length Encoding (VLE)
–
Mix of classic 32-bit and 16-bit instruction allowed
–
Optimization of code size possible
Thirty-two 64-bit general purpose registers (GPRs)
Harvard bus (32-bit address, 64-bit data)
–
I-Bus interface capable of one outstanding transaction plus one piped with no waiton-data return
–
D-Bus interface capable of two transactions outstanding to fill AHB pipe
I-cache and I-cache controller
–
No data cache
16-entry MMU
8-entry branch table buffer
Branch look-ahead instruction buffer to accelerate branching
Dedicated branch address calculator
3 cycles worst case for missed branch
Load/store unit
–
Fully pipelined
–
Single-cycle load latency
–
Big- and little-endian modes supported
–
Misaligned access support
–
Single stall cycle on load to use
Single-cycle throughput (2-cycle latency) integer 32 × 32 multiplication
4 – 14 cycles integer 32 × 32 division (average division on various benchmark of nine
cycles)
Single precision floating-point unit
–
1 cycle throughput (2-cycle latency) floating-point 32 × 32 multiplication
–
Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 ×
32 division
–
Special square root and min/max function implemented
Signal processing support: APU-SPE 1.1
–
12/128
4 KB, 256-bit cache line (programmable for 2- or 4-way)
Support for vectorized mode: as many as two floating-point instructions per clock
Vectored interrupt support
Reservation instruction to support read-modify-write constructs
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1.5.2
Introduction
Extensive system development and tracing support via Nexus debug port
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four
master ports and three slave ports. The crossbar supports a 32-bit address bus width and a
64-bit data bus width.
The crossbar allows four concurrent transactions to occur from any master port to any slave
port, although one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic selects the higher priority master and grants it ownership of the slave port.
All other masters requesting that slave port are stalled until the higher priority master
completes its transactions.
The crossbar provides the following features:
4 masters and 3 slaves supported per each replicated crossbar
–
Masters allocation for each crossbar: e200z4d core with two independent bus
interface units (BIU) for I and D access (2 masters), one eDMA, one FlexRay
–
Slaves allocation for each crossbar: a redundant flash-memory controller with 2
slave ports to guarantee maximum flexibility to handle Instruction and Data array,
one redundant SRAM controller with 1 slave port each and 1 redundant peripheral
bus bridge
32-bit address bus and 64-bit data bus
Programmable arbitration priority
–
Requesting masters can be treated with equal priority and are granted access to a
slave port in round-robin method, based upon the ID of the last master to be
granted access or a priority order can be assigned by software at application run
time
Temporary dynamic priority elevation of masters
The XBAR is replicated for each processing channel.
1.5.3
Memory protection unit (MPU)
The Memory Protection Unit splits the physical memory into 16 different regions. Each
master (eDMA, FlexRay, CPU) can be assigned different access rights to each region.
16-region MPU with concurrent checks against each master access
32-byte granularity for protected address region
The memory protection unit is replicated for each processing channel.
1.5.4
Enhanced direct memory access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels. This implementation is used to minimize the
overall block size.
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The eDMA module provides the following features:
16 channels supporting 8-, 16-, and 32-bit value single or block transfers
Support variable sized queues and circular buffered queue
Source and destination address registers independently configured to post-increment
or stay constant
Support major and minor loop offset
Support minor and major loop done signals
DMA task initiated either by hardware requestor or by software
Each DMA task can optionally generate an interrupt at completion and retirement of the
task
Signal to indicate closure of last minor loop
Transfer control descriptors mapped inside the SRAM
The eDMA controller is replicated for each processing channel.
1.5.5
On-chip flash memory with ECC
This device includes programmable, non-volatile flash memory. The non-volatile memory
(NVM) can be used for instruction storage or data storage, or both. The flash memory
module interfaces with the system bus through a dedicated flash memory array controller. It
supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to
flash memory. The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow
no-wait responses. Buffer misses incur a 3 wait state response at 120 MHz.
The flash memory module provides the following features:
1.5.6
2 MB of flash memory in unique multi-partitioned hard macro
Sectorization:
–
Partition 1 (low address): 16 KB + 16 KB + 16 KB + 16 KB
–
Partition 2 (low address): 16 KB + 16 KB + 16 KB + 16 KB
–
Partition 3 (low address): 64 KB + 64 KB
–
Partition 4 (mid address): 128 KB + 128 KB
–
Partition 5 (high address): 256 KB + 256 KB
–
Partition 6 (high address): 256 KB + 256 KB
–
Partition 7 (high address): 256 KB + 256 KB
EEPROM emulation (in software) within same module but on different partition
16 KB test sector and 16 KB shadow sector for test, censorship device and user option
bits
Wait states:
–
Access time less or equal to 3 WS at 120 MHz + 4% FM (4-1-2-1 access)
–
Access time less or equal to 2 WS at 80 MHz + 4% FM
Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits)
Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations
1-bit error correction, 2-bit error detection
On-chip SRAM with ECC
The SPC56XL70 SRAM provides a general-purpose single port memory.
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Introduction
ECC handling is done on a 32-bit boundary for data and it is extended to the address to
have the highest possible diagnostic coverage including the array internal address decoder.
The SRAM module provides the following features:
System SRAM: 192 KB
ECC on 32-bit word (syndrome of 7 bits)
–
1.5.7
ECC covers SRAM bus address
1-bit error correction, 2-bit error detection
Wait states:
–
1 wait state at 120 MHz
–
0 wait states at 80 MHz
Platform flash memory controller
The following list summarizes the key features of the flash memory controller:
Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned
reads within the 32-bit container are supported. Only aligned word writes are
supported.
Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each
bank.
Code flash (bank0) interface provides configurable read buffering and page prefetch
support.
–
Four page-read buffers (each 128 bits wide) and a prefetch controller support
speculative reading and optimized flash access.
Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The
buffers implement a least-recently-used replacement algorithm to maximize
performance.
Data flash (bank1) interface includes a 128-bit register to temporarily hold a single flash
page. This logic supports single-cycle read responses (0 AHB data-phase wait states)
for accesses that hit in the holding register.
–
No prefetch support is provided for this bank.
Programmable response for read-while-write sequences including support for stallwhile-write, optional stall notification interrupt, optional flash operation abort and
optional abort notification interrupt.
Separate and independent configurable access timing (on a per bank basis) to support
use across a wide range of platforms and frequencies.
Support of address-based read access timing for emulation of other memory types.
Support for reporting of single- and multi-bit error events.
Typical operating configuration loaded into programming model by system reset.
The platform flash controller is replicated for each processor.
1.5.8
Platform static RAM controller (SRAMC)
The SRAMC module is the platform SRAM array controller, with integrated error detection
and correction.
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SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
The main features of the SRAMC provide connectivity for the following interfaces:
XBAR Slave Port (64-bit data path)
ECSM (ECC Error Reporting, error injection and configuration)
SRAM array
The following functions are implemented:
ECC encoding (32-bit boundary for data and complete address bus)
ECC decoding (32-bit boundary and entire address)
Address translation from the AHB protocol on the XBAR to the SRAM array
The platform SRAM controller is replicated for each processor.
1.5.9
Memory subsystem access time
Every memory access the CPU performs requires at least one system clock cycle for the
data phase of the access. Slower memories or peripherals may require additional data
phase wait states. Additional data phase wait states may also occur if the slave being
accessed is not parked on the requesting master in the crossbar.
Table 2 shows the number of additional data phase wait states required for a range of
memory accesses.
Table 2. Platform memory access time summary
AHB transfer
Data phase
wait states
Description
e200z4d instruction fetch
0
Flash memory prefetch buffer hit (page hit)
e200z4d instruction fetch
3
Flash memory prefetch buffer miss
(based on 4-cycle random flash array access time)
e200z4d data read
0–1
SRAM read
e200z4d data write
0
SRAM 32-bit write
e200z4d data write
0
SRAM 64-bit write (executed as 2 x 32-bit writes)
e200z4d data write
0–2
SRAM 8-,16-bit write
(Read-modify-Write for ECC)
e200z4d flash memory read
0
Flash memory prefetch buffer hit (page hit)
e200z4d flash memory read
3
Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle
of program flash memory controller arbitration)
1.5.10
Error correction status module (ECSM)
The ECSM on this device manages the ECC configuration and reporting for the platform
memories (flash memory and SRAM). It does not implement the actual ECC calculation. A
detected error (double error for flash memory or SRAM) is also reported to the FCCU. The
following errors and indications are reported into the ECSM dedicated registers:
16/128
ECC error status and configuration for flash memory and SRAM
ECC error reporting for flash memory
ECC error reporting for SRAM
ECC error injection for SRAM
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1.5.11
Introduction
Peripheral bridge (PBRIDGE)
The PBRIDGE implements the following features:
1.5.12
Duplicated periphery
Master access right per peripheral (per master: read access enable; write access
enable)
Checker applied on PBRIDGE output toward periphery
Byte endianess swap capability
Interrupt controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for
statically scheduled hard real-time systems.
For high-priority interrupt requests, the time from the assertion of the interrupt request from
the peripheral to when the processor is executing the interrupt service routine (ISR) has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR needs to be executed. It also provides an ample number
of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.
The INTC supports the priority ceiling protocol for coherent accesses. By providing a
modifiable priority mask, the priority can be raised temporarily so that all tasks which share
the resource can not preempt each other.
The INTC provides the following features:
Duplicated periphery
Unique 9-bit vector per interrupt source
16 priority levels with fixed hardware arbitration within priority levels for each interrupt
source
Priority elevation for shared resource
The INTC is replicated for each processor.
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Introduction
1.5.13
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
System clocks and clock generation
The following list summarizes the system clock and clock generation on this device:
Lock status continuously monitored by lock detect circuitry
Loss-of-clock (LOC) detection for reference and feedback clocks
On-chip loop filter (for improved electromagnetic interference performance and fewer
external components required)
Programmable output clock divider of system clock (1, 2, 4, 8)
FlexPWM module and as many as three eTimer modules running on an auxiliary clock
independent from system clock (with max frequency 120 MHz)
On-chip crystal oscillator with automatic level control
Dedicated internal 16 MHz internal RC oscillator for rapid start-up
–
1.5.14
Supports automated frequency trimming by hardware during device startup and by
user application
Auxiliary clock domain for motor control periphery (FlexPWM, eTimer, CTU, ADC, and
SWG)
Frequency-Modulated Phase-Locked Loop (FMPLL)
Each device has two FMPLLs.
Each FMPLL allows the user to generate high speed system clocks starting from a minimum
reference of 4 MHz input clock. Further, the FMPLL supports programmable frequency
modulation of the system clock. The FMPLL multiplication factor, output clock divider ratio
are all software configurable. The FMPLLs have the following major features:
18/128
Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator)
Voltage controlled oscillator (VCO) range: 256–512 MHz
Frequency modulation via software control to reduce and control emission peaks
–
Modulation depth ±2% if centered or 0% to –4% if downshifted via software control
register
–
Modulation frequency: triangular modulation with 25 KHz nominal rate
Option to switch modulation on and off via software interface
Reduced frequency divider (RFD) for reduced frequency operation without re-lock
3 modes of operation
–
Bypass mode
–
Normal FMPLL mode with crystal reference (default)
–
Normal FMPLL mode with external reference
Lock monitor circuitry with lock status
Loss-of-lock detection for reference and feedback clocks
Self-clocked mode (SCM) operation
On-chip loop filter
Auxiliary FMPLL
–
Used for FlexRay due to precise symbol rate requirement by the protocol
–
Used for motor control periphery and connected IP (A/D digital interface CTU) to
allow independent frequencies of operation for PWM and timers and jitter-free
control
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SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
1.5.15
Introduction
–
Option to enable/disable modulation to avoid protocol violation on jitter and/or
potential unadjusted error in electric motor control loop
–
Allows to run motor control periphery at different (precisely lower, equal or higher
as required) frequency than the system to ensure higher resolution
Main oscillator
The main oscillator provides these features:
1.5.16
Input frequency range 4–40 MHz
Crystal input mode
External reference clock (3.3 V) input mode
FMPLL reference
Internal reference clock (RC) oscillator
The architecture uses constant current charging of a capacitor. The voltage at the capacitor
is compared to the stable bandgap reference voltage. The RC oscillator is the device safe
clock.
The RC oscillator provides these features:
1.5.17
Nominal frequency 16 MHz
±5% variation over voltage and temperature after process trim
Clock output of the RC oscillator serves as system clock source in case loss of lock or
loss of clock is detected by the FMPLL
RC oscillator is used as the default system clock during startup and can be used as
back-up input source of FMPLL(s) in case XOSC fails
Clock, reset, power, mode and test control modules (MC_CGM,
MC_RGM, MC_PCU, and MC_ME)
These modules provide the following:
1.5.18
Clock gating and clock distribution control
Halt, stop mode control
Flexible configurable system and auxiliary clock dividers
Various execution modes
–
HALT and STOP mode as reduced activity low power mode
–
Reset, Idle, Test, Safe
–
Various RUN modes with software selectable powered modules
–
No stand-by mode implemented (no internal switchable power domains)
Periodic interrupt timer module (PIT)
The PIT module implements the following features:
4 general purpose interrupt timers
32-bit counter resolution
Can be used for software tick or DMA trigger operation
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Introduction
1.5.19
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
System timer module (STM)
The STM implements the following features:
Up-counter with 4 output compare registers
OS task protection and hardware tick implementation per AUTOSAR(a) requirement
The STM is replicated for each processor.
1.5.20
Software watchdog timer (SWT)
This module implements the following features:
Fault tolerant output
Safe internal RC oscillator as reference clock
Windowed watchdog
Program flow control monitor with 16-bit pseudorandom key generation
Allows a high level of safety (SIL3 monitor)
The SWT module is replicated for each processor.
1.5.21
Fault collection and control unit (FCCU)
The FCCU module has the following features:
1.5.22
Redundant collection of hardware checker results
Redundant collection of error information and latch of faults from critical modules on
the device
Collection of self-test results
Configurable and graded fault control
–
Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset,
or Safe mode entered)
–
External reaction (failure is reported to the external/surrounding system via
configurable output pins)
System Integration Unit Lite (SIUL)
The SIUL controls MCU reset configuration, pad configuration, external interrupt, general
purpose I/O (GPIO), internal peripheral multiplexing, and system reset operation. The reset
configuration block contains the external pin boot configuration logic. The pad configuration
block controls the static electrical characteristics of I/O pins. The GPIO block provides
uniform and discrete input/output control of the I/O pins of the MCU.
a. Automotive Open System Architecture
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Introduction
The SIU provides the following features:
1.5.23
Centralized pad control on a per-pin basis
–
Pin function selection
–
Configurable weak pull-up/down
–
Configurable slew rate control (slow/medium/fast)
–
Hysteresis on GPIO pins
–
Configurable automatic safe mode pad control
Input filtering for external interrupts
Non-maskable interrupt (NMI)
The non-maskable interrupt with de-glitching filter supports high-priority core exceptions.
1.5.24
Boot assist module (BAM)
The BAM is a block of read-only memory with hard-coded content. The BAM program is
executed only if serial booting mode is selected via boot configuration pins.
The BAM provides the following features:
1.5.25
Enables booting via serial mode (FlexCAN or LINFlex-UART)
Supports programmable 64-bit password protection for serial boot mode
Supports serial bootloading of either Power Architecture code (default) or VLE code
Automatic switch to serial boot mode if internal flash memory is blank or invalid
System status and configuration module (SSCM)
The SSCM on this device features the following:
1.5.26
System configuration and status
Debug port status and debug port enable
Multiple boot code starting locations out of reset through implementation of search for
valid Reset Configuration Half Word
Sets up the MMU to allow user boot code to execute as either Power Architecture code
(default) or as VLE code out of flash memory
Triggering of device self-tests during reset phase of device boot
FlexCAN
The FlexCAN module is a communication controller implementing the CAN protocol
according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: realtime processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness
and required bandwidth.
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SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
The FlexCAN module provides the following features:
–
Standard data and remote frames
–
Extended data and remote frames
–
0 to 8 bytes data length
–
Programmable bit rate as fast as 1Mbit/s
32 message buffers of 0 to 8 bytes data length
Each message buffer configurable as receive or transmit buffer, all supporting standard
and extended messages
Programmable loop-back mode supporting self-test operation
3 programmable mask registers
Programmable transmit-first scheme: lowest ID or lowest buffer number
Time stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Independent of the transmission medium (an external transceiver is assumed)
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Transmit features
22/128
Full implementation of the CAN protocol specification, version 2.0B
–
Supports configuration of multiple mailboxes to form message queues of scalable
depth
–
Arbitration scheme according to message ID or message buffer number
–
Internal arbitration to guarantee no inner or outer priority inversion
–
Transmit abort procedure and notification
Receive features
–
Individual programmable filters for each mailbox
–
8 mailboxes configurable as a 6-entry receive FIFO
–
8 programmable acceptance filters for receive FIFO
Programmable clock source
–
System clock
–
Direct oscillator clock to avoid FMPLL jitter
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1.5.27
Introduction
FlexRay
The FlexRay module provides the following features:
Full implementation of FlexRay Protocol Specification 2.1 Rev. A
64 configurable message buffers can be handled
Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
Message buffers configurable as transmit or receive
Message buffer size configurable
Message filtering for all message buffers based on Frame ID, cycle count, and
message ID
Programmable acceptance filters for receive FIFO
Message buffer header, status, and payload data stored in system memory (SRAM)
Internal FlexRay memories have error detection and correction
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1.5.28
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Serial communication interface module (LINFlexD)
The LINFlexD module (LINFlex with DMA support) on this device features the following:
Supports LIN Master mode, LIN Slave mode and UART mode
LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications
Manages LIN frame transmission and reception without CPU intervention
LIN features
24/128
–
Autonomous LIN frame handling
–
Message buffer to store as many as 8 data bytes
–
Supports messages as long as 64 bytes
–
Detection and flagging of LIN errors (Sync field, delimiter, ID parity, bit framing,
checksum and Time-out errors)
–
Classic or extended checksum calculation
–
Configurable break duration of up to 50-bit times
–
Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
–
Diagnostic features (Loop back, LIN bus stuck dominant detection)
–
Interrupt driven operation with 16 interrupt sources
LIN slave mode features
–
Autonomous LIN header handling
–
Autonomous LIN response handling
UART mode
–
Full-duplex operation
–
Standard non return-to-zero (NRZ) mark/space format
–
Data buffers with 4-byte receive, 4-byte transmit
–
Configurable word length (8-bit, 9-bit, or 16-bit words)
–
Configurable parity scheme: none, odd, even, always 0
–
Speed as fast as 2 Mbit/s
–
Error detection and flagging (Parity, Noise and Framing errors)
–
Interrupt driven operation with four interrupt sources
–
Separate transmitter and receiver CPU interrupt sources
–
16-bit programmable baud-rate modulus counter and 16-bit fractional
–
2 receiver wake-up methods
Support for DMA enabled transfers
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1.5.29
Introduction
Deserial serial peripheral interface (DSPI)
The DSPI modules provide a synchronous serial interface for communication between the
SPC56XL70 and external devices.
A DSPI module provides these features:
1.5.30
Full duplex, synchronous transfers
Master or slave operation
Programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Programmable transfer baud rate
Programmable data frames from 4 to 16 bits
As many as 8 chip select lines available, depending on package and pin multiplexing
4 clock and transfer attributes registers
Chip select strobe available as alternate function on one of the chip select pins for deglitching
FIFOs for buffering as many as 5 transfers on the transmit and receive side
Queueing operation possible through use of the eDMA
General purpose I/O functionality on pins when not used for SPI
FlexPWM
The pulse width modulator module (FlexPWM) contains four PWM channels, each of which
is configured to control a single half-bridge power stage. One module is present in LQFP144
package. Additionally, four fault input channels are provided per FlexPWM module.
This PWM is capable of controlling most motor types, including:
AC induction motors (ACIM)
Permanent Magnet AC motors (PMAC)
Brushless (BLDC) and brush DC motors (BDC)
Switched (SRM) and variable reluctance motors (VRM)
Stepper motors
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Introduction
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
A FlexPWM module implements the following features:
16 bits of resolution for center, edge aligned, and asymmetrical PWMs
Maximum operating frequency as high as 120 MHz
–
Fine granularity control for enhanced resolution of the PWM period
PWM outputs can operate as complementary pairs or independent channels
Ability to accept signed numbers for PWM generation
Independent control of both edges of each PWM output
Synchronization to external hardware or other PWM supported
Double buffered PWM registers
–
Integral reload rates from 1 to 16
–
Half cycle reload capability
Multiple ADC trigger events can be generated per PWM cycle via hardware
Fault inputs can be assigned to control multiple PWM outputs
Programmable filters for fault inputs
Independently programmable PWM output polarity
Independent top and bottom deadtime insertion
Each complementary pair can operate with its own PWM frequency and deadtime
values
Individual software control for each PWM output
All outputs can be forced to a value simultaneously
PWMX pin can optionally output a third signal from each channel
Channels not used for PWM generation can be used for buffered output compare
functions
Channels not used for PWM generation can be used for input capture functions
Enhanced dual edge capture functionality
Option to supply the source for each complementary PWM signal pair from any of the
following:
26/128
Clock source not modulated and independent from system clock (generated via
secondary FMPLL)
–
External digital pin
–
Internal timer channel
–
External ADC input, taking into account values set in ADC high- and low-limit
registers
DMA support
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1.5.31
Introduction
eTimer module
The SPC56XL70 provides two eTimer modules on the LQFP144 package. Six 16-bit
general purpose up/down timer/counters per module are implemented with the following
features:
Maximum clock frequency of 120 MHz
Individual channel capability
1.5.32
–
Input capture trigger
–
Output compare
–
Double buffer (to capture rising edge and falling edge)
–
Separate prescaler for each counter
–
Selectable clock source
–
0–100% pulse measurement
–
Rotation direction flag (Quad decoder mode)
Maximum count rate
–
Equals peripheral clock divided by 2 for external event counting
–
Equals peripheral clock for internal clock counting
Cascadeable counters
Programmable count modulo
Quadrature decode capabilities
Counters can share available input pins
Count once or repeatedly
Preloadable counters
Pins available as GPIO when timer functionality not in use
DMA support
Sine wave generator (SWG)
A digital-to-analog converter is available to generate a sine wave based on 32 stored values
for external devices (ex: resolver).
Frequency range from 1 KHz to 50 KHz
Sine wave amplitude from 0.47 V to 2.26 V
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1.5.33
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Analog-to-Digital converter module (ADC)
The ADC module features include:
Analog part:
2 on-chip ADCs
–
12-bit resolution SAR architecture
–
Same digital interface as in the SPC560P family
–
A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16
channels)
–
One channel dedicated to each T-sensor to enable temperature reading during
application
–
Separated reference for each ADC
–
Shared analog supply voltage for both ADCs
–
One sample and hold unit per ADC
–
Adjustable sampling and conversion time
Digital part:
4 analog watchdogs comparing ADC results against predefined levels (low, high,
range) before results are stored in the appropriate ADC result location
2 modes of operation: CPU Mode or CTU Mode
CPU mode features
1.5.34
–
Register based interface with the CPU: one result register per channel
–
ADC state machine managing three request flows: regular command, hardware
injected command, software injected command
–
Selectable priority between software and hardware injected commands
–
4 analog watchdogs comparing ADC results against predefined levels (low, high,
range)
–
DMA compatible interface
CTU mode features
–
Triggered mode only
–
4 independent result queues (116 entries, 28 entries, 14 entries)
–
Result alignment circuitry (left justified; right justified)
–
32-bit read mode allows to have channel ID on one of the 16-bit parts
–
DMA compatible interfaces
Built-in self-test features triggered by software
Cross triggering unit (CTU)
The ADC cross triggering unit allows automatic generation of ADC conversion requests on
user selected conditions without CPU load during the PWM period and with minimized CPU
load for dynamic configuration.
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Introduction
The CTU implements the following features:
1.5.35
Cross triggering between ADC, FlexPWM, eTimer, and external pins
Double buffered trigger generation unit with as many as 8 independent triggers
generated from external triggers
Maximum operating frequency less than or equal to 120 MHz
Trigger generation unit configurable in sequential mode or in triggered mode
Trigger delay unit to compensate the delay of external low pass filter
Double buffered global trigger unit allowing eTimer synchronization and/or ADC
command generation
Double buffered ADC command list pointers to minimize ADC-trigger unit update
Double buffered ADC conversion command list with as many as 24 ADC commands
Each trigger capable of generating consecutive commands
ADC conversion command allows control of ADC channel from each ADC, single or
synchronous sampling, independent result queue selection
DMA support with safety features
Cyclic redundancy checker (CRC) unit
The CRC module is a configurable multiple data flow unit to compute CRC signatures on
data written to its input register.
The CRC unit has the following features:
1.5.36
3 sets of registers to allow 3 concurrent contexts with possibly different CRC
computations, each with a selectable polynomial and seed
Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores
result in internal register.
The following standard CRC polynomials are implemented:
–
x8 + x4 + x3 + x2 + 1 [8-bit CRC]
–
x16 + x12 + x5 + 1 [16-bit CRC-CCITT]
–
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
[32-bit CRC-ethernet(32)]
Key engine to be coupled with communication periphery where CRC application is
added to allow implementation of safe communication protocol
Offloads core from cycle-consuming CRC and helps checking configuration signature
for safe start-up or periodic procedures
CRC unit connected as peripheral bus on internal peripheral bus
DMA support
Redundancy control and checker unit (RCCU)
The RCCU checks all outputs of the sphere of replication (addresses, data, control signals).
It has the following features:
Duplicated module to guarantee highest possible diagnostic coverage (check of
checker)
Multiple times replicated IPs are used as checkers on the SoR outputs
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1.5.37
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Junction temperature sensor
The junction temperature sensor provides a value via an ADC channel that can be used by
software to calculate the device junction temperature.
The key parameters of the junction temperature sensor include:
1.5.38
Nominal temperature range from –40 to 150 °C
Software temperature alarm via analog ADC comparator possible
Nexus port controller (NPC)
The NPC module provides real-time development support capabilities for this device in
compliance with the IEEE-ISTO 5001-2008 standard. This development support is supplied
for MCUs without requiring external address and data pins for internal visibility.
The NPC block interfaces to the host processor and internal buses to provide development
support as per the IEEE-ISTO 5001-2008 Class 3+, including selected features from Class
4 standard.
The development support provided includes program trace, data trace, watchpoint trace,
ownership trace, run-time access to the MCUs internal memory map and access to the
Power Architecture internal registers during halt. The Nexus interface also supports a JTAG
only mode using only the JTAG pins. The following features are implemented:
Full and reduced port modes
MCKO (message clock out) pin
4 or 12 MDO (message data out) pins(b)
2 MSEO (message start/end out) pins
EVTO (event out) pin
–
Auxiliary input port
EVTI (event in) pin
5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)
–
Supports JTAG mode
Host processor (e200) development support features
–
Data trace via data write messaging (DWM) and data read messaging (DRM).
This allows the development tool to trace reads or writes, or both, to selected
internal memory resources.
–
Ownership trace via ownership trace messaging (OTM). OTM facilitates
ownership trace by providing visibility of which process ID or operating system
task is activated. An ownership trace message is transmitted when a new
process/task is activated, allowing development tools to trace ownership flow.
–
Program trace via branch trace messaging (BTM). Branch trace messaging
displays program flow discontinuities (direct branches, indirect branches,
exceptions, etc.), allowing the development tool to interpolate what transpires
between the discontinuities. Thus, static code may be traced.
–
Watchpoint messaging (WPM) via the auxiliary port
b. 4 MDO pins on LQFP144 package
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1.5.39
–
Watchpoint trigger enable of program and/or data trace messaging
–
Data tracing of instruction fetches via private opcodes
Introduction
IEEE 1149.1 JTAG controller (JTAGC)
The JTAGC block provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode. All data input to and output
from the JTAGC block is communicated in serial format. The JTAGC block is compliant with
the IEEE standard.
The JTAG controller provides the following features:
1.5.40
IEEE Test Access Port (TAP) interface with 5 pins:
–
TDI
–
TMS
–
TCK
–
TDO
–
JCOMP
Selectable modes of operation include JTAGC/debug or normal system operation
5-bit instruction register that supports the following IEEE 1149.1-2001 defined
instructions:
–
BYPASS
–
IDCODE
–
EXTEST
–
SAMPLE
–
SAMPLE/PRELOAD
3 test data registers: a bypass register, a boundary scan register, and a device
identification register. The size of the boundary scan register is parameterized to
support a variety of boundary scan chain lengths.
TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry
Voltage regulator / power management unit (PMU)
The on-chip voltage regulator module provides the following features:
Single external rail required
Single high supply required: nominal 3.3 V both for packaged and Known Good Die
option
–
Packaged option requires external ballast transistor due to reduced dissipation
capacity at high temperature but can use embedded transistor if power dissipation
is maintained within package dissipation capacity (lower frequency of operation)
–
Known Good Die option uses embedded ballast transistor as dissipation capacity
is increased to reduce system cost
All I/Os are at same voltage as external supply (3.3 V nominal)
Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages
(reset, configuration, normal operation) and, to maximize safety coverage, one LVD
can be tested while the other operates (on-line self-testing feature)
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1.5.41
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Built-In self-test (BIST) capability
This device includes the following protection against latent faults:
32/128
Boot-time Memory Built-In Self-Test (MBIST)
Boot-time scan-based Logic Built-In Self-Test (LBIST)
Run-time ADC Built-In Self-Test (BIST)
Run-time Built-In Self Test of LVDs
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Package pinouts and signal descrip-
2
Package pinouts and signal descriptions
2.1
Package pinouts
Figure 2 shows the SPC56XL70 in the LQFP100 package.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
A[15]
A[14]
C[6]
FCCU_F[1]
B[6]
A[13]
A[9]
VSS_LV_COR
VDD_LV_COR
VDD_HV_REG_2
D[4]
D[3]
VSS_HV_IO
VDD_HV_IO
D[0]
C[15]
JCOMP
A[12]
A[11]
A[10]
B[3]
B[2]
C[10]
B[1]
B[0]
Figure 2. SPC56XL70 LQFP100 package
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2
71
74
70
73
69
72
68
71
67
70
66
69
65
68
64
67
63
66
62
65
61
64
60
63
59
62
58
61
57
60
56
59
55
58
54
57
53
56
52
55
51
54
3
4
LQFP100 package
LQFP100
package
5
6
7
3
0
2
9
2
8
A[4]
VPP_TEST
D[14]
C[14]
C[13]
D[12]
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_REG_1
VSS_LV_COR
VDD_LV_COR
A[3]
VDD_HV_IO
VSS_HV_IO
B[4]
TCK
TMS
B[5]
A[2]
C[12]
C[11]
D[11]
D[10]
A[1]
A[0]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
2
7
8
2
6
775
74
573
72
D[7]
FCCU_F[0]
VDD_LV_COR
VSS_LV_COR
B[7]
B[8]
E[2]
VDD_HV_ADR0
VSS_HV_ADR0
B[9]
B[10]
B[11]
B[12]
VDD_HV_ADR1
VSS_HV_ADR1
VDD_HV_ADV
VSS_HV_ADV
B[13]
B[14]
C[0]
E[0]
BCTRL
VDD_LV_COR
VSS_LV_COR
VDD_HV_PMU
NMI
A[6]
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
VDD_HV_REG_0
VSS_LV_COR
VDD_LV_COR
VDD_HV_IO
VSS_HV_IO
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[6]
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
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Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Figure 3 shows the SPC56XL70 in the LQFP144 package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144 package
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
A[4]
VPP_TEST
F[12]
D[14]
G[3]
C[14]
G[2]
C[13]
G[4]
D[12]
G[6]
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_REG_1
VSS_LV_COR
VDD_LV_COR
A[3]
VDD_HV_IO
VSS_HV_IO
B[4]
TCK
TMS
B[5]
G[5]
A[2]
G[7]
C[12]
G[8]
C[11]
G[9]
D[11]
G[10]
D[10]
G[11]
A[1]
A[0]
D[7]
FCCU_F[0]
VDD_LV_COR
VSS_LV_COR
C[1]
E[4]
B[7]
E[5]
C[2]
E[6]
B[8]
E[7]
E[2]
VDD_HV_ADR0
VSS_HV_ADR0
B[9]
B[10]
B[11]
B[12]
VDD_HV_ADR1
VSS_HV_ADR1
VDD_HV_ADV
VSS_HV_ADV
B[13]
E[9]
B[15]
E[10]
B[14]
E[11]
C[0]
E[12]
E[0]
BCTRL
VDD_LV_COR
VSS_LV_COR
VDD_HV_PMU
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NMI
A[6]
D[1]
F[4]
F[5]
VDD_HV_IO
VSS_HV_IO
F[6]
MDO0
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
VDD_HV_REG_0
VSS_LV_COR
VDD_LV_COR
F[7]
F[8]
VDD_HV_IO
VSS_HV_IO
F[9]
F[10]
F[11]
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[6]
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
A[15]
A[14]
C[6]
FCCU_F[1]
D[2]
F[3]
B[6]
VSS_LV_COR
A[13]
VDD_LV_COR
A[9]
F[0]
VSS_LV_COR
VDD_LV_COR
VDD_HV_REG_2
D[4]
D[3]
VSS_HV_IO
VDD_HV_IO
D[0]
C[15]
JCOMP
A[12]
E[15]
A[11]
E[14]
A[10]
E[13]
B[3]
F[14]
B[2]
F[15]
F[13]
C[10]
B[1]
B[0]
Figure 3. SPC56XL70 LQFP144 pinout (top view)
Table 3 and Table 4 provides the pin function summaries for the 100-pin and 144-pin
packages respectively, listing all the signals multiplexed to each pin
Table 3. LQFP100 pin function summary
Pin #
Port/function
1
NMI
2
3
34/128
A[6]
D[1]
Peripheral
Output function
Input function
—
SIUL
GPIO[6]
GPIO[6]
DSPI_1
SCK
SCK
SIUL
—
EIRQ[6]
SIUL
GPIO[49]
GPIO[49]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
FlexRay
—
CA_RX
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 3. LQFP100 pin function summary (continued)
Pin #
4
5
6
7
8
9
Port/function
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
Peripheral
Output function
Input function
SIUL
GPIO[7]
GPIO[7]
DSPI_1
SOUT
—
SIUL
—
EIRQ[7]
FlexCan_2
—
RXD
SIUL
GPIO[36]
GPIO[36]
DSPI_0
CS0
CS0
FlexPWM_0
X[1]
X[1]
SSCM
DEBUG[4]
—
SIUL
—
EIRQ[22]
SIUL
GPIO[8]
GPIO[8]
DSPI_1
—
SIN
SIUL
—
EIRQ[8]
FlexCan_2
TXD
—
SIUL
GPIO[37]
GPIO[37]
DSPI_0
SCK
SCK
SSCM
DEBUG[5]
—
FlexPWM_0
—
FAULT[3]
SIUL
—
EIRQ[23]
SIUL
GPIO[5]
GPIO[5]
DSPI_1
CS0
CS0
eTimer_1
ETC[5]
ETC[5]
DSPI_0
CS7
—
SIUL
—
EIRQ[5]
SIUL
GPIO[39]
GPIO[39]
FlexPWM_0
A[1]
A[1]
SSCM
DEBUG[7]
—
DSPI_0
—
SIN
10
VDD_HV_REG_0
—
11
VSS_LV_COR
—
12
VDD_LV_COR
—
13
VDD_HV_IO
—
14
VSS_HV_IO
—
15
D[9]
SIUL
GPIO[57]
GPIO[57]
FlexPWM_0
X[0]
X[0]
LINFlexD_1
TXD
—
DocID023953 Rev 5
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127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 3. LQFP100 pin function summary (continued)
Pin #
Port/function
16
VDD_HV_OSC
—
17
VSS_HV_OSC
—
18
XTALIN
—
19
XTALOUT
—
20
RESET
—
21
22
23
D[8]
D[5]
D[6]
Peripheral
Output function
SIUL
GPIO[56]
GPIO[56]
DSPI_1
CS2
—
eTimer_1
ETC[4]
ETC[4]
DSPI_0
CS5
—
FlexPWM_0
—
FAULT[3]
SIUL
GPIO[53]
GPIO[53]
DSPI_0
CS3
—
FlexPWM_0
—
FAULT[2]
SIUL
GPIO[54]
GPIO[54]
DSPI_0
CS2
—
FlexPWM_0
X[3]
X[3]
FlexPWM_0
—
FAULT[1]
24
VSS_LV_PLL0_PLL1
—
25
VDD_LV_PLL0_PLL1
—
26
D[7]
SIUL
GPIO[55]
GPIO[55]
DSPI_1
CS3
—
DSPI_0
CS4
—
SWG
Analog output
—
FCCU
F[0]
F[0]
27
FCCU_F[0]
28
VDD_LV_COR
—
29
VSS_LV_COR
—
30
31
B[7]
B[8]
32
E[2]
33
VDD_HV_ADR0
36/128
Input function
SIUL
—
GPIO[23]
LINFlexD_0
—
RXD
ADC_0
—
AN[0]
SIUL
—
GPIO[24]
eTimer_0
—
ETC[5]
ADC_0
—
AN[1]
SIUL
—
GPIO[66]
ADC_0
—
AN[5]
—
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 3. LQFP100 pin function summary (continued)
Pin #
Port/function
34
VSS_HV_ADR0
Peripheral
Output function
—
SIUL
35
B[9]
ADC_0
ADC_1
SIUL
36
B[10]
ADC_0
ADC_1
SIUL
37
B[11]
ADC_0
ADC_1
SIUL
38
B[12]
ADC_0
ADC_1
—
GPIO[25]
—
AN[11]
—
GPIO[26]
—
AN[12]
—
GPIO[27]
—
AN[13]
—
GPIO[28]
—
AN[14]
39
VDD_HV_ADR1
—
40
VSS_HV_ADR1
—
41
VDD_HV_ADV
—
42
VSS_HV_ADV
—
43
44
B[13]
B[14]
Input function
SIUL
—
GPIO[29]
LINFlexD_1
—
RXD
ADC_1
—
AN[0]
SIUL
—
GPIO[30]
eTimer_0
—
ETC[4]
SIUL
—
EIRQ[19]
ADC_1
—
AN[1]
SIUL
—
GPIO[32]
ADC_1
—
AN[3]
SIUL
—
GPIO[64]
ADC_1
—
AN[5]
45
C[0]
46
E[0]
47
BCTRL
—
48
VDD_LV_COR
—
49
VSS_LV_COR
—
50
VDD_HV_PMU
—
DocID023953 Rev 5
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127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 3. LQFP100 pin function summary (continued)
Pin #
51
52
53
54
55
56
57
Port/function
A[0]
A[1]
D[10]
D[11]
C[11]
C[12]
A[2]
Peripheral
Output function
Input function
SIUL
GPIO[0]
GPIO[0]
eTimer_0
ETC[0]
ETC[0]
DSPI_2
SCK
SCK
SIUL
—
EIRQ[0]
SIUL
GPIO[1]
GPIO[1]
eTimer_0
ETC[1]
ETC[1]
DSPI_2
SOUT
—
SIUL
—
EIRQ[1]
SIUL
GPIO[58]
GPIO[58]
FlexPWM_0
A[0]
A[0]
eTimer_0
—
ETC[0]
SIUL
GPIO[59]
GPIO[59]
FlexPWM_0
B[0]
B[0]
eTimer_0
—
ETC[1]
SIUL
GPIO[43]
GPIO[43]
eTimer_0
ETC[4]
ETC[4]
DSPI_2
CS2
—
SIUL
GPIO[44]
GPIO[44]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
GPIO[2]
GPIO[2]
eTimer_0
ETC[2]
ETC[2]
FlexPWM_0
A[3]
A[3]
DSPI_2
—
SIN
MC_RGM
—
ABS[0]
SIUL
—
EIRQ[2]
SIUL
GPIO[21]
GPIO[21]
JTAGC
—
TDI
58
B[5]
59
TMS
—
60
TCK
—
61
B[4]
62
VSS_HV_IO
—
63
VDD_HV_IO
—
38/128
SIUL
GPIO[20]
GPIO[20]
JTAGC
TDO
—
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 3. LQFP100 pin function summary (continued)
Pin #
64
Port/function
A[3]
Peripheral
Output function
Input function
SIUL
GPIO[3]
GPIO[3]
eTimer_0
ETC[3]
ETC[3]
DSPI_2
CS0
CS0
FlexPWM_0
B[3]
B[3]
MC_RGM
—
ABS[2]
SIUL
—
EIRQ[3]
65
VDD_LV_COR
—
66
VSS_LV_COR
—
67
VDD_HV_REG_1
—
68
VSS_HV_FLA
—
69
VDD_HV_FLA
—
70
71
72
73
74
75
D[12]
C[13]
C[14]
D[14]
VPP_TEST
A[4]
SIUL
GPIO[60]
GPIO[60]
FlexPWM_0
X[1]
X[1]
LINFlexD_1
—
RXD
SIUL
GPIO[45]
GPIO[45]
eTimer_1
ETC[1]
ETC[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[46]
GPIO[46]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
SIUL
GPIO[62]
GPIO[62]
FlexPWM_0
B[1]
B[1]
eTimer_0
—
ETC[3]
(1)
—
SIUL
GPIO[4]
GPIO[4]
eTimer_1
ETC[0]
ETC[0]
DSPI_2
CS1
—
eTimer_0
ETC[4]
ETC[4]
MC_RGM
—
FAB
SIUL
—
EIRQ[4]
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Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 3. LQFP100 pin function summary (continued)
Pin #
76
77
78
79
80
81
82
40/128
Port/function
B[0]
B[1]
C[10]
B[2]
B[3]
A[10]
A[11]
Peripheral
Output function
Input function
SIUL
GPIO[16]
GPIO[16]
FlexCAN_0
TXD
—
eTimer_1
ETC[2]
ETC[2]
SSCM
DEBUG[0]
—
SIUL
—
EIRQ[15]
SIUL
GPIO[17]
GPIO[17]
eTimer_1
ETC[3]
ETC[3]
SSCM
DEBUG[1]
—
FlexCAN_0
—
RXD
FlexCAN_1
—
RXD
SIUL
—
EIRQ[16]
SIUL
GPIO[42]
GPIO[42]
DSPI_2
CS2
—
FlexPWM_0
A[3]
A[3]
FlexPWM_0
—
FAULT[1]
SIUL
GPIO[18]
GPIO[18]
LINFlexD_0
TXD
—
SSCM
DEBUG[2]
DEBUG[2]
SIUL
—
EIRQ[17]
SIUL
GPIO[19]
GPIO[19]
SSCM
DEBUG[3]
DEBUG[3]
LINFlexD_0
—
RXD
SIUL
GPIO[10]
GPIO[10]
DSPI_2
CS0
CS0
FlexPWM_0
B[0]
B[0]
FlexPWM_0
X[2]
X[2]
SIUL
—
EIRQ[9]
SIUL
GPIO[11]
GPIO[11]
DSPI_2
SCK
SCK
FlexPWM_0
A[0]
A[0]
FlexPWM_0
A[2]
A[2]
SIUL
—
EIRQ[10]
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 3. LQFP100 pin function summary (continued)
Pin #
83
84
85
86
Port/function
A[12]
JCOMP
C[15]
D[0]
Peripheral
Output function
Input function
SIUL
GPIO[12]
GPIO[12]
DSPI_2
SOUT
—
FlexPWM_0
A[2]
A[2]
FlexPWM_0
B[2]
B[2]
SIUL
—
EIRQ[11]
—
—
JCOMP
SIUL
GPIO[47]
GPIO[47]
FlexRay
CA_TR_EN
—
eTimer_1
ETC[0]
ETC[0]
FlexPWM_0
A[1]
A[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[48]
GPIO[48]
FlexRay
CA_TX
—
eTimer_1
ETC[1]
ETC[1]
FlexPWM_0
B[1]
B[1]
87
VDD_HV_IO
—
88
VSS_HV_IO
—
89
90
D[3]
D[4]
SIUL
GPIO[51]
GPIO[51]
FlexRay
CB_TX
—
eTimer_1
ETC[4]
ETC[4]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[52]
GPIO[52]
FlexRay
CB_TR_EN
—
eTimer_1
ETC[5]
ETC[5]
FlexPWM_0
B[3]
B[3]
91
VDD_HV_REG_2
—
92
VDD_LV_COR
—
93
VSS_LV_COR
—
94
A[9]
SIUL
GPIO[9]
GPIO[9]
DSPI_2
CS1
—
FlexPWM_0
B[3]
B[3]
FlexPWM_0
—
FAULT[0]
DocID023953 Rev 5
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Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 3. LQFP100 pin function summary (continued)
Pin #
95
96
97
98
99
100
Port/function
A[13]
B[6]
FCCU_F[1]
C[6]
A[14]
A[15]
Peripheral
Output function
Input function
SIUL
GPIO[13]
GPIO[13]
FlexPWM_0
B[2]
B[2]
DSPI_2
—
SIN
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[12]
SIUL
GPIO[22]
GPIO[22]
MC_CGM
clk_out
—
DSPI_2
CS2
—
SIUL
—
EIRQ[18]
FCCU
F[1]
F[1]
SIUL
GPIO[38]
GPIO[38]
DSPI_0
SOUT
—
FlexPWM_0
B[1]
B[1]
SSCM
DEBUG[6]
—
SIUL
—
EIRQ[24]
SIUL
GPIO[14]
GPIO[14]
FlexCAN_1
TXD
—
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[13]
SIUL
GPIO[15]
GPIO[15]
eTimer_1
ETC[5]
ETC[5]
FlexCAN_1
—
RXD
FlexCAN_0
—
RXD
SIUL
—
EIRQ[14]
1. VPP_TEST should always be tied to ground (VSS) for normal operations.
Table 4. LQFP144 pin function summary
Pin #
Port/function
1
NMI
2
42/128
A[6]
Peripheral
Output function
Input function
—
SIUL
GPIO[6]
GPIO[6]
DSPI_1
SCK
SCK
SIUL
—
EIRQ[6]
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 4. LQFP144 pin function summary (continued)
Pin #
3
Port/function
D[1]
Peripheral
Output function
Input function
SIUL
GPIO[49]
GPIO[49]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
FlexRay
—
CA_RX
SIUL
GPIO[84]
GPIO[84]
NPC
MDO[3]
—
SIUL
GPIO[85]
GPIO[85]
NPC
MDO[2]
—
4
F[4]
5
F[5]
6
VDD_HV_IO
—
7
VSS_HV_IO
—
8
F[6]
9
MDO0
10
11
12
13
A[7]
C[4]
A[8]
C[5]
SIUL
GPIO[86]
GPIO[86]
NPC
MDO[1]
—
—
SIUL
GPIO[7]
GPIO[7]
DSPI_1
SOUT
—
SIUL
—
EIRQ[7]
FlexCAN_2
—
RXD
SIUL
GPIO[36]
GPIO[36]
DSPI_0
CS0
CS0
FlexPWM_0
X[1]
X[1]
SSCM
DEBUG[4]
—
SIUL
—
EIRQ[22]
SIUL
GPIO[8]
GPIO[8]
DSPI_1
—
SIN
SIUL
—
EIRQ[8]
FlexCAN_2
TXD
—
SIUL
GPIO[37]
GPIO[37]
DSPI_0
SCK
SCK
SSCM
DEBUG[5]
—
FlexPWM_0
—
FAULT[3]
SIUL
—
EIRQ[23]
DocID023953 Rev 5
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127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 4. LQFP144 pin function summary (continued)
Pin #
14
15
Port/function
A[5]
C[7]
Peripheral
Output function
Input function
SIUL
GPIO[5]
GPIO[5]
DSPI_1
CS0
CS0
eTimer_1
ETC[5]
ETC[5]
DSPI_0
CS7
—
SIUL
—
EIRQ[5]
SIUL
GPIO[39]
GPIO[39]
FlexPWM_0
A[1]
A[1]
SSCM
DEBUG[7]
—
DSPI_0
—
SIN
16
VDD_HV_REG_0
—
17
VSS_LV_COR
—
18
VDD_LV_COR
—
19
F[7]
20
F[8]
21
VDD_HV_IO
—
22
VSS_HV_IO
—
23
F[9]
24
F[10]
25
F[11]
26
D[9]
SIUL
GPIO[87]
GPIO[87]
NPC
MCKO
—
SIUL
GPIO[88]
GPIO[88]
NPC
MSEO[1]
—
SIUL
GPIO[89]
GPIO[89]
NPC
MSEO[0]
—
SIUL
GPIO[90]
GPIO[90]
NPC
EVTO
—
SIUL
GPIO[91]
GPIO[91]
NPC
EVTI
—
SIUL
GPIO[57]
GPIO[57]
FlexPWM_0
X[0]
X[0]
LINFlexD_1
TXD
—
27
VDD_HV_OSC
—
28
VSS_HV_OSC
—
29
XTALIN
—
30
XTALOUT
—
31
RESET
—
44/128
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 4. LQFP144 pin function summary (continued)
Pin #
32
33
34
Port/function
D[8]
D[5]
D[6]
Peripheral
Output function
Input function
SIUL
GPIO[56]
GPIO[56]
DSPI_1
CS2
—
eTimer_1
ETC[4]
ETC[4]
DSPI_0
CS5
—
FlexPWM_0
—
FAULT[3]
SIUL
GPIO[53]
GPIO[53]
DSPI_0
CS3
—
FlexPWM_0
—
FAULT[2]
SIUL
GPIO[54]
GPIO[54]
DSPI_0
CS2
—
FlexPWM_0
X[3]
X[3]
FlexPWM_0
—
FAULT[1]
35
VSS_LV_PLL0_PLL1
—
36
VDD_LV_PLL0_PLL1
—
37
D[7]
SIUL
GPIO[55]
GPIO[55]
DSPI_1
CS3
—
DSPI_0
CS4
—
SWG
analog output
—
FCCU
F[0]
F[0]
38
FCCU_F[0]
39
VDD_LV_COR
—
40
VSS_LV_COR
—
41
C[1]
42
E[4]
43
B[7]
44
E[5]
45
C[2]
46
E[6]
SIUL
—
GPIO[33]
ADC_0
—
AN[2]
SIUL
—
GPIO[68]
ADC_0
—
AN[7]
SIUL
—
GPIO[23]
LINFlexD_0
—
RXD
ADC_0
—
AN[0]
SIUL
—
GPIO[69]
ADC_0
—
AN[8]
SIUL
—
GPIO[34]
ADC_0
—
AN[3]
SIUL
—
GPIO[70]
ADC_0
—
AN[4]
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127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 4. LQFP144 pin function summary (continued)
Pin #
47
Port/function
B[8]
Peripheral
Output function
Input function
SIUL
—
GPIO[24]
eTimer_0
—
ETC[5]
ADC_0
—
AN[1]
SIUL
—
GPIO[71]
ADC_0
—
AN[6]
SIUL
—
GPIO[66]
ADC_0
—
AN[5]
48
E[7]
49
E[2]
50
VDD_HV_ADR0
—
51
VSS_HV_ADR0
—
52
B[9]
53
54
B[10]
B[11]
SIUL
—
GPIO[25]
ADC_0
ADC_1
—
AN[11]
SIUL
—
GPIO[26]
ADC_0
ADC_1
—
AN[12]
SIUL
—
GPIO[27]
ADC_0
ADC_1
—
AN[13]
SIUL
—
GPIO[28]
ADC_0
ADC_1
—
AN[14]
55
B[12]
56
VDD_HV_ADR1
—
57
VSS_HV_ADR1
—
58
VDD_HV_ADV
—
59
VSS_HV_ADV
—
60
61
62
63
46/128
B[13]
E[9]
B[15]
E[10]
SIUL
—
GPIO[29]
LINFlexD_1
—
RXD
ADC_1
—
AN[0]
SIUL
—
GPIO[73]
ADC_1
—
AN[7]
SIUL
—
GPIO[31]
SIUL
—
EIRQ[20]
ADC_1
—
AN[2]
SIUL
—
GPIO[74]
ADC_1
—
AN[8]
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 4. LQFP144 pin function summary (continued)
Pin #
64
Port/function
B[14]
Peripheral
Output function
Input function
SIUL
—
GPIO[30]
eTimer_0
—
ETC[4]
SIUL
—
EIRQ[19]
ADC_1
—
AN[1]
SIUL
—
GPIO[75]
ADC_1
—
AN[4]
SIUL
—
GPIO[32]
ADC_1
—
AN[3]
SIUL
—
GPIO[76]
ADC_1
—
AN[6]
SIUL
—
GPIO[64]
ADC_1
—
AN[5]
65
E[11]
66
C[0]
67
E[12]
68
E[0]
69
BCTRL
—
70
VDD_LV_COR
—
71
VSS_LV_COR
—
72
VDD_HV_PMU
—
73
74
75
76
77
A[0]
A[1]
G[11]
D[10]
G[10]
SIUL
GPIO[0]
GPIO[0]
eTimer_0
ETC[0]
ETC[0]
DSPI_2
SCK
SCK
SIUL
—
EIRQ[0]
SIUL
GPIO[1]
GPIO[1]
eTimer_0
ETC[1]
ETC[1]
DSPI_2
SOUT
—
SIUL
—
EIRQ[1]
SIUL
GPIO[107]
GPIO[107]
FlexRay
DBG3
—
FlexPWM_0
—
FAULT[3]
SIUL
GPIO[58]
GPIO[58]
FlexPWM_0
A[0]
A[0]
eTimer_0
—
ETC[0]
SIUL
GPIO[106]
GPIO[106]
FlexRay
DBG2
—
DSPI_2
CS3
—
FlexPWM_0
—
FAULT[2]
DocID023953 Rev 5
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127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 4. LQFP144 pin function summary (continued)
Pin #
78
79
80
81
82
83
84
85
Port/function
D[11]
G[9]
C[11]
G[8]
C[12]
G[7]
A[2]
G[5]
Peripheral
Output function
Input function
SIUL
GPIO[59]
GPIO[59]
FlexPWM_0
B[0]
B[0]
eTimer_0
—
ETC[1]
SIUL
GPIO[105]
GPIO[105]
FlexRay
DBG1
—
DSPI_1
CS1
—
FlexPWM_0
—
FAULT[1]
SIUL
—
EIRQ[29]
SIUL
GPIO[43]
GPIO[43]
eTimer_0
ETC[4]
ETC[4]
DSPI_2
CS2
—
SIUL
GPIO[104]
GPIO[104]
FlexRay
DBG0
—
DSPI_0
CS1
—
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[21]
SIUL
GPIO[44]
GPIO[44]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
GPIO[103]
GPIO[103]
FlexPWM_0
B[3]
B[3]
SIUL
GPIO[2]
GPIO[2]
eTimer_0
ETC[2]
ETC[2]
FlexPWM_0
A[3]
A[3]
DSPI_2
—
SIN
MC_RGM
—
ABS[0]
SIUL
—
EIRQ[2]
SIUL
GPIO[101]
GPIO[101]
FlexPWM_0
X[3]
X[3]
DSPI_2
CS3
—
SIUL
GPIO[21]
GPIO[21]
JTAGC
—
TDI
86
B[5]
87
TMS
—
88
TCK
—
48/128
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 4. LQFP144 pin function summary (continued)
Pin #
Port/function
89
B[4]
90
VSS_HV_IO
—
91
VDD_HV_IO
—
92
A[3]
Peripheral
Output function
Input function
SIUL
GPIO[20]
GPIO[20]
JTAGC
TDO
—
SIUL
GPIO[3]
GPIO[3]
eTimer_0
ETC[3]
ETC[3]
DSPI_2
CS0
CS0
FlexPWM_0
B[3]
B[3]
MC_RGM
—
ABS[2]
SIUL
—
EIRQ[3]
93
VDD_LV_COR
—
94
VSS_LV_COR
—
95
VDD_HV_REG_1
—
96
VSS_HV_FLA
—
97
VDD_HV_FLA
—
98
G[6]
99
100
101
102
103
D[12]
G[4]
C[13]
G[2]
C[14]
SIUL
GPIO[102]
GPIO[102]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[60]
GPIO[60]
FlexPWM_0
X[1]
X[1]
LINFlexD_1
—
RXD
SIUL
GPIO[100]
GPIO[100]
FlexPWM_0
B[2]
B[2]
eTimer_0
—
ETC[5]
SIUL
GPIO[45]
GPIO[45]
eTimer_1
ETC[1]
ETC[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[98]
GPIO[98]
FlexPWM_0
X[2]
X[2]
DSPI_1
CS1
—
SIUL
GPIO[46]
GPIO[46]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
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127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 4. LQFP144 pin function summary (continued)
Pin #
104
105
106
107
108
109
110
111
112
50/128
Port/function
G[3]
D[14]
F[12]
Peripheral
Output function
Input function
SIUL
GPIO[99]
GPIO[99]
FlexPWM_0
A[2]
A[2]
eTimer_0
—
ETC[4]
SIUL
GPIO[62]
GPIO[62]
FlexPWM_0
B[1]
B[1]
eTimer_0
—
ETC[3]
SIUL
GPIO[92]
GPIO[92]
eTimer_1
ETC[3]
ETC[3]
SIUL
—
EIRQ[30]
VPP_TEST(1)
A[4]
B[0]
B[1]
C[10]
F[13]
—
SIUL
GPIO[4]
GPIO[4]
eTimer_1
ETC[0]
ETC[0]
DSPI_2
CS1
—
eTimer_0
ETC[4]
ETC[4]
MC_RGM
—
FAB
SIUL
—
EIRQ[4]
SIUL
GPIO[16]
GPIO[16]
FlexCAN_0
TXD
—
eTimer_1
ETC[2]
ETC[2]
SSCM
DEBUG[0]
—
SIUL
—
EIRQ[15]
SIUL
GPIO[17]
GPIO[17]
eTimer_1
ETC[3]
ETC[3]
SSCM
DEBUG[1]
—
FlexCAN_0
—
RXD
FlexCAN_1
—
RXD
SIUL
—
EIRQ[16]
SIUL
GPIO[42]
GPIO[42]
DSPI_2
CS2
—
FlexPWM_0
A[3]
A[3]
FlexPWM_0
—
FAULT[1]
SIUL
GPIO[93]
GPIO[93]
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[31]
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 4. LQFP144 pin function summary (continued)
Pin #
113
114
115
116
117
118
119
120
121
Port/function
F[15]
B[2]
F[14]
B[3]
E[13]
A[10]
E[14]
A[11]
E[15]
Peripheral
Output function
Input function
SIUL
GPIO[95]
GPIO[95]
LINFlexD_1
—
RXD
FlexCAN_2
TXD
—
SIUL
GPIO[18]
GPIO[18]
LINFlexD_0
TXD
—
SSCM
DEBUG[2]
—
SIUL
—
EIRQ[17]
SIUL
GPIO[94]
GPIO[94]
LINFlexD_1
TXD
—
FlexCAN_2
—
RXD
SIUL
GPIO[19]
GPIO[19]
SSCM
DEBUG[3]
—
LINFlexD_0
—
RXD
SIUL
GPIO[77]
GPIO[77]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
—
EIRQ[25]
SIUL
GPIO[10]
GPIO[10]
DSPI_2
CS0
CS0
FlexPWM_0
B[0]
B[0]
FlexPWM_0
X[2]
X[2]
SIUL
—
EIRQ[9]
SIUL
GPIO[78]
GPIO[78]
eTimer_1
ETC[5]
ETC[5]
SIUL
—
EIRQ[26]
SIUL
GPIO[11]
GPIO[11]
DSPI_2
SCK
SCK
FlexPWM_0
A[0]
A[0]
FlexPWM_0
A[2]
A[2]
SIUL
—
EIRQ[10]
SIUL
GPIO[79]
GPIO[79]
DSPI_0
CS1
—
SIUL
—
EIRQ[27]
DocID023953 Rev 5
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127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 4. LQFP144 pin function summary (continued)
Pin #
122
123
124
125
Port/function
A[12]
JCOMP
C[15]
D[0]
Peripheral
Output function
Input function
SIUL
GPIO[12]
GPIO[12]
DSPI_2
SOUT
—
FlexPWM_0
A[2]
A[2]
FlexPWM_0
B[2]
B[2]
SIUL
—
EIRQ[11]
—
—
JCOMP
SIUL
GPIO[47]
GPIO[47]
FlexRay
CA_TR_EN
—
eTimer_1
ETC[0]
ETC[0]
FlexPWM_0
A[1]
A[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[48]
GPIO[48]
FlexRay
CA_TX
—
eTimer_1
ETC[1]
ETC[1]
FlexPWM_0
B[1]
B[1]
126
VDD_HV_IO
—
127
VSS_HV_IO
—
128
129
D[3]
D[4]
SIUL
GPIO[51]
GPIO[51]
FlexRay
CB_TX
—
eTimer_1
ETC[4]
ETC[4]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[52]
GPIO[52]
FlexRay
CB_TR_EN
—
eTimer_1
ETC[5]
ETC[5]
FlexPWM_0
B[3]
B[3]
130
VDD_HV_REG_2
—
131
VDD_LV_COR
—
132
VSS_LV_COR
—
133
52/128
F[0]
SIUL
GPIO[80]
GPIO[80]
FlexPWM_0
A[1]
A[1]
eTimer_0
—
ETC[2]
SIUL
—
EIRQ[28]
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 4. LQFP144 pin function summary (continued)
Pin #
134
135
136
137
138
139
140
141
142
143
Port/function
A[9]
Peripheral
Output function
Input function
SIUL
GPIO[9]
GPIO[9]
DSPI_2
CS1
—
FlexPWM_0
B[3]
B[3]
FlexPWM_0
—
FAULT[0]
—
VDD_LV_COR
A[13]
SIUL
GPIO[13]
GPIO[13]
FlexPWM_0
B[2]
B[2]
DSPI_2
—
SIN
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[12]
—
VSS_LV_COR
B[6]
F[3]
D[2]
FCCU_F[1]
C[6]
A[14]
SIUL
GPIO[22]
GPIO[22]
MC_CGM
clk_out
—
DSPI_2
CS2
—
SIUL
—
EIRQ[18]
SIUL
GPIO[83]
GPIO[83]
DSPI_0
CS6
—
SIUL
GPIO[50]
GPIO[50]
eTimer_1
ETC[3]
ETC[3]
FlexPWM_0
X[3]
X[3]
FlexRay
—
CB_RX
FCCU
F[1]
F[1]
SIUL
GPIO[38]
GPIO[38]
DSPI_0
SOUT
—
FlexPWM_0
B[1]
B[1]
SSCM
DEBUG[6]
—
SIUL
—
EIRQ[24]
SIUL
GPIO[14]
GPIO[14]
FlexCAN_1
TXD
—
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[13]
DocID023953 Rev 5
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127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 4. LQFP144 pin function summary (continued)
Pin #
Port/function
144
A[15]
Peripheral
Output function
Input function
SIUL
GPIO[15]
GPIO[15]
eTimer_1
ETC[5]
ETC[5]
FlexCAN_1
—
RXD
FlexCAN_0
—
RXD
SIUL
—
EIRQ[14]
1. VPP_TEST should always be tied to ground (VSS) for normal operations.
2.2
Supply pins
Table 5. Supply pins
Supply
Pin #
100
Pkg
144
Pkg
Voltage regulator external NPN ballast base control pin
47
69
VDD_LV_COR
Core logic supply
48
70
VSS_LV_COR
Core regulator ground
49
71
VDD_HV_PMU
Voltage regulator supply
50
72
Symbol
Description
VREG control and power supply pins
BCTRL
ADC_0/ADC_1 reference voltage and ADC supply
VDD_HV_ADR0
ADC_0 high reference voltage
33
50
VSS_HV_ADR0
ADC_0 low reference voltage
34
51
VDD_HV_ADR1
ADC_1 high reference voltage
39
56
VSS_HV_ADR1
ADC_1 low reference voltage
40
57
VDD_HV_ADV
ADC voltage supply for ADC_0 and ADC_1
41
58
VSS_HV_ADV
ADC ground for ADC_0 and ADC_1
42
59
Power supply pins (3.3 V)
VDD_HV_IO
3.3 V Input/Output supply voltage
—
6
VSS_HV_IO
3.3 V Input/Output ground
—
7
VDD_HV_REG_0
10
16
VDD_HV_IO
3.3 V Input/Output supply voltage
13
21
VSS_HV_IO
3.3 V Input/Output ground
14
22
VDD_HV_OSC
Crystal oscillator amplifier supply voltage
16
27
VSS_HV_OSC
Crystal oscillator amplifier ground
17
28
VSS_HV_IO
3.3 V Input/Output ground
62
90
VDD_HV_IO
3.3 V Input/Output supply voltage
63
91
VDD_HV_REG_0
54/128
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 5. Supply pins (continued)
Supply
Pin #
100
Pkg
144
Pkg
VDD_HV_REG_1
67
95
VSS_HV_FLA
VSS_HV_FLA
68
96
VDD_HV_FLA
VDD_HV_FLA
69
97
VDD_HV_IO
VDD_HV_IO
87
126
VSS_HV_IO
VSS_HV_IO
88
127
VDD_HV_REG_2
91
130
Symbol
VDD_HV_REG_1
VDD_HV_REG_2
Description
Power supply pins (1.2 V)
VSS_LV_COR
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
11
17
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
12
18
VSS 1V2
VSS_LV_PLL0_PLL1 /
1.2 V Decoupling pins for on-chip FMPLL modules. Decoupling capacitor must
be connected between this pin and VDD_LV_PLL.
24
35
VDD 1V2
VDD_LV_PLL0_PLL1
Decoupling pins for on-chip FMPLL modules. Decoupling capacitor must be
connected between this pin and VSS_LV_PLL.
25
36
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
28
39
VSS_LV_COR
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
29
40
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic and Regulator feedback. Decoupling capacitor
must be connected between this pins and VSS_LV_REGCOR.
—
70
VSS_LV_COR
VSS_LV_REGCOR0
Decoupling pins for core logic and Regulator feedback. Decoupling capacitor
must be connected between this pins and VDD_LV_REGCOR.
—
71
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
65
93
VSS_LV_COR
VSS_LV_COR
/ 1.2 V Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
66
94
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
92
131
VDD 1V2
DocID023953 Rev 5
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127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 5. Supply pins (continued)
Supply
Symbol
Pin #
Description
100
Pkg
144
Pkg
VSS 1V2
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
93
132
VDD 1V2
VDD_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
—
135
VSS 1V2
VSS_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
—
137
2.3
System pins
Table 6. System pins
Pin #
Symbol
Description
Direction
100
pkg
144
pkg
Output only
—
9
Non Maskable Interrupt
Input only
1
1
Input for oscillator amplifier circuit and internal clock generator
Input only
18
29
Input/Output(4)
19
30
Dedicated pins
MDO0(1)
NMI
(2)
XTAL
EXTAL(3)
Nexus Message Data Output — line
Oscillator amplifier output
(2)
JTAG state machine control
Input only
59
87
(2)
JTAG clock
Input only
60
88
JTAG compliance select
Input only
84
123
Bidirectional
20
31
74
107
TMS
TCK
JCOMP(5)
Reset pin
RESET
Bidirectional reset with Schmitt-Trigger characteristics and noise
filter. This pin has medium drive strength. Output drive is open drain
and must be terminated by an external resistor of value 1KOhm.(6)
Test pin
VPP TEST
Pin for testing purpose only. To be tied to ground in normal operating
mode.
1. This pad is configured for Fast (F) pad speed.
2. This pad contains a weak pull-up.
3. EXTAL is an "Output" in "crystal" mode, and is an "Input" in "ext clock" mode.
4. In XOSC Bypass Mode, the analog portion of crystal oscillator (amplifier) is disabled. An external clock can be applied at
EXTAL as an input. In XOSC Normal Mode, EXTAL is an output
5. This pad contains a weak pull-down.
56/128
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
6. RESET output shall be considered valid only after the 3.3V supply reaches its stable value.
None of system pins (except RESET) provides an open drain output.
2.4
Pin muxing
Table 7 defines the pin list and muxing for this device.
Each entry of Table 7 shows all the possible configurations for each pin, via the alternate
functions. The default function assigned to each pin after reset is indicated by ALT0.
Note:
Pins labeled “NC” are to be left unconnected. Any connection to an external circuit or
voltage may cause unpredictable device behavior or damage.
Pins labeled “Reserved” are to be tied to ground. Not doing so may cause unpredictable
device behavior.
Table 7. Pin muxing
Port
name
PCR
Peripheral
Alternate
output
function
Input
Output
mux sel functions
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Port A
A[0]
A[1]
A[2]
SIUL
GPIO[0]
ALT0
GPIO[0]
—
eTimer_0
ETC[0]
ALT1
ETC[0]
PSMI[35];
PADSEL=0
PCR[0]
PCR[1]
PCR[2]
DSPI_2
SCK
ALT2
SCK
PSMI[1];
PADSEL=0
SIUL
—
—
EIRQ[0]
—
SIUL
GPIO[1]
ALT0
GPIO[1]
—
eTimer_0
ETC[1]
ALT1
ETC[1]
PSMI[36];
PADSEL=0
DSPI_2
SOUT
ALT2
—
—
SIUL
—
—
EIRQ[1]
—
SIUL
GPIO[2]
ALT0
GPIO[2]
—
eTimer_0
ETC[2]
ALT1
ETC[2]
PSMI[37];
PADSEL=0
FlexPWM_0
A[3]
ALT3
A[3]
PSMI[23];
PADSEL=0
DSPI_2
—
—
SIN
PSMI[2];
PADSEL=0
MC_RGM
—
—
ABS[0]
—
SIUL
—
—
EIRQ[2]
—
DocID023953 Rev 5
Pull
down
M
S
51
73
Pull
down
M
S
52
74
Pull
down
M
S
57
84
57/128
127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 7. Pin muxing (continued)
Port
name
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
58/128
PCR
PCR[3]
PCR[4]
PCR[5]
PCR[6]
PCR[7]
PCR[8]
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Peripheral
Alternate
output
function
SIUL
GPIO[3]
ALT0
GPIO[3]
—
eTimer_0
ETC[3]
ALT1
ETC[3]
PSMI[38];
PADSEL=0
DSPI_2
CS0
ALT2
CS0
PSMI[3];
PADSEL=0
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[27];
PADSEL=0
MC_RGM
—
—
ABS[2]
—
SIUL
—
—
EIRQ[3]
—
SIUL
GPIO[4]
ALT0
GPIO[4]
—
eTimer_1
ETC[0]
ALT1
ETC[0]
PSMI[9];
PADSEL=0
DSPI_2
CS1
ALT2
—
—
eTimer_0
ETC[4]
ALT3
ETC[4]
PSMI[7];
PADSEL=0
MC_RGM
—
—
FAB
—
SIUL
—
—
EIRQ[4]
—
SIUL
GPIO[5]
ALT0
GPIO[5]
—
DSPI_1
CS0
ALT1
CS0
—
eTimer_1
ETC[5]
ALT2
ETC[5]
PSMI[14];
PADSEL=0
DSPI_0
CS7
ALT3
—
—
SIUL
—
—
EIRQ[5]
—
SIUL
GPIO[6]
ALT0
GPIO[6]
—
DSPI_1
SCK
ALT1
SCK
—
SIUL
—
—
EIRQ[6]
—
SIUL
GPIO[7]
ALT0
GPIO[7]
—
DSPI_1
SOUT
ALT1
—
—
SIUL
—
—
EIRQ[7]
—
FlexCAN_2
RXD
ALT2
—
—
SIUL
GPIO[8]
ALT0
GPIO[8]
—
DSPI_1
—
—
SIN
—
SIUL
—
—
EIRQ[8]
—
FlexCAN_2
TXD
ALT2
—
—
Input
Output
mux sel functions
DocID023953 Rev 5
Pull
down
M
S
64
92
Pull
down
M
S
75
108
Pull
down
M
S
8
14
Pull
down
M
S
2
2
Pull
down
M
S
4
10
Pull
down
M
S
6
12
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 7. Pin muxing (continued)
Port
name
A[9]
A[10]
A[11]
A[12]
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Peripheral
Alternate
output
function
SIUL
GPIO[9]
ALT0
GPIO[9]
—
DSPI_2
CS1
ALT1
—
—
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[27];
PADSEL=1
FlexPWM_0
—
—
FAULT[0]
PSMI[16];
PADSEL=0
SIUL
GPIO[10]
ALT0
GPIO[10]
—
DSPI_2
CS0
ALT1
CS0
PSMI[3];
PADSEL=1
PCR[10] FlexPWM_0
B[0]
ALT2
B[0]
PSMI[24];
PADSEL=0
FlexPWM_0
X[2]
ALT3
X[2]
PSMI[29];
PADSEL=0
SIUL
—
—
EIRQ[9]
—
SIUL
GPIO[11]
ALT0
GPIO[11]
—
DSPI_2
SCK
ALT1
SCK
PSMI[1];
PADSEL=1
FlexPWM_0
A[0]
ALT2
A[0]
PSMI[20];
PADSEL=0
FlexPWM_0
A[2]
ALT3
A[2]
PSMI[22];
PADSEL=0
SIUL
—
—
EIRQ[10]
—
SIUL
GPIO[12]
ALT0
GPIO[12]
—
DSPI_2
SOUT
ALT1
—
—
FlexPWM_0
A[2]
ALT2
A[2]
PSMI[22];
PADSEL=1
FlexPWM_0
B[2]
ALT3
B[2]
PSMI[26];
PADSEL=0
SIUL
—
—
EIRQ[11]
—
PCR
PCR[9]
PCR[11]
PCR[12]
Input
Output
mux sel functions
DocID023953 Rev 5
Pull
down
M
S
94
134
Pull
down
M
S
81
118
Pull
down
M
S
82
120
Pull
down
M
S
83
122
59/128
127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 7. Pin muxing (continued)
Port
name
A[13]
A[14]
A[15]
PCR
PCR[13]
PCR[14]
PCR[15]
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Peripheral
Alternate
output
function
SIUL
GPIO[13]
ALT0
GPIO[13]
—
FlexPWM_0
B[2]
ALT2
B[2]
PSMI[26];
PADSEL=1
DSPI_2
—
—
SIN
PSMI[2];
PADSEL=1
FlexPWM_0
—
—
FAULT[0]
PSMI[16];
PADSEL=1
SIUL
—
—
EIRQ[12]
—
SIUL
GPIO[14]
ALT0
GPIO[14]
—
FlexCAN_1
TXD
ALT1
—
—
Input
Output
mux sel functions
eTimer_1
ETC[4]
ALT2
ETC[4]
PSMI[13];
PADSEL=0
SIUL
—
—
EIRQ[13]
—
SIUL
GPIO[15]
ALT0
GPIO[15]
—
eTimer_1
ETC[5]
ALT2
ETC[5]
PSMI[14];
PADSEL=1
FlexCAN_1
—
—
RXD
PSMI[34];
PADSEL=0
FlexCAN_0
—
—
RXD
PSMI[33];
PADSEL=0
SIUL
—
—
EIRQ[14]
—
Pull
down
M
S
95
136
Pull
down
M
S
99
143
Pull
down
M
S
100 144
Pull
down
M
S
76
Port B
B[0]
60/128
PCR[16]
SIUL
GPIO[16]
ALT0
GPIO[16]
—
FlexCAN_0
TXD
ALT1
—
—
eTimer_1
ETC[2]
ALT2
ETC[2]
PSMI[11];
PADSEL=0
SSCM
DEBUG[0]
ALT3
—
—
SIUL
—
—
EIRQ[15]
—
DocID023953 Rev 5
109
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 7. Pin muxing (continued)
Port
name
B[1]
B[2]
B[3]
PCR
PCR[17]
PCR[18]
PCR[19]
B[4](2)
PCR[20]
B[5]
PCR[21]
B[6]
B[7]
B[8]
PCR[22]
PCR[23]
PCR[24]
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Peripheral
Alternate
output
function
SIUL
GPIO[17]
ALT0
GPIO[17]
—
eTimer_1
ETC[3]
ALT2
ETC[3]
PSMI[12];
PADSEL=0
SSCM
DEBUG[1]
ALT3
—
—
FlexCAN_0
—
—
RXD
PSMI[33];
PADSEL=1
FlexCAN_1
—
—
RXD
PSMI[34];
PADSEL=1
SIUL
—
—
EIRQ[16]
—
SIUL
GPIO[18]
ALT0
GPIO[18]
—
LINFlex_0
TXD
ALT1
—
—
SSCM
DEBUG[2]
ALT3
—
—
SIUL
—
—
EIRQ[17]
—
SIUL
GPIO[19]
ALT0
GPIO[19]
—
SSCM
DEBUG[3]
ALT3
—
—
Input
Output
mux sel functions
LINFlex_0
—
—
RXD
PSMI[31];
PADSEL=0
SIUL
GPIO[20]
ALT0
GPIO[20]
—
JTAGC
TDO
ALT1
—
—
SIUL
GPIO[21]
ALT0
GPIO[21]
—
JTAGC
—
—
TDI
—
SIUL
GPIO[22]
ALT0
GPIO[22]
—
MC_CGM
clk_out
ALT1
—
—
DSPI_2
CS2
ALT2
—
—
SIUL
—
EIRQ[18]
—
SIUL
—
ALT0
GPI[23]
—
LINFlex_0
—
—
RXD
PSMI[31];
PADSEL=1
ADC_0
—
—
AN[0](3)
—
SIUL
—
ALT0
GPI[24]
—
eTimer_0
—
—
ETC[5]
PSMI[8];
PADSEL=2
ADC_0
—
—
AN[1](3)
—
DocID023953 Rev 5
Pull
down
M
S
77
110
Pull
down
M
S
79
114
Pull
down
M
S
80
116
Pull
down
F
S
61
89
Pull up
M
S
58
86
Pull
down
F
S
96
138
—
—
—
30
43
—
—
—
31
47
61/128
127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 7. Pin muxing (continued)
Port
name
PCR
B[9]
PCR[25]
B[10]
B[11]
B[12]
B[13]
B[14]
B[15]
PCR[26]
PCR[27]
PCR[28]
PCR[29]
PCR[30]
PCR[31]
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Peripheral
Alternate
output
function
SIUL
—
ALT0
GPI[25]
—
ADC_0
ADC_1
—
—
AN[11](3)
—
SIUL
—
ALT0
GPI[26]
—
ADC_0
ADC_1
—
—
AN[12](3)
—
SIUL
—
ALT0
GPI[27]
—
ADC_0
ADC_1
—
—
AN[13](3)
—
SIUL
—
ALT0
GPI[28]
—
ADC_0
ADC_1
—
—
AN[14](3)
—
SIUL
—
ALT0
GPI[29]
—
LINFlex_1
—
—
RXD
PSMI[32];
PADSEL=0
ADC_1
—
—
AN[0](3)
—
SIUL
—
ALT0
GPI[30]
—
eTimer_0
—
—
ETC[4]
PSMI[7];
PADSEL=2
SIUL
—
—
EIRQ[19]
—
ADC_1
—
—
AN[1](3)
—
SIUL
—
ALT0
GPI[31]
—
SIUL
—
—
EIRQ[20]
—
ADC_1
—
Input
Output
mux sel functions
(3)
—
ALT0
GPI[32]
—
—
—
AN[2]
—
—
—
35
52
—
—
—
36
53
—
—
—
37
54
—
—
—
38
55
—
—
—
43
60
—
—
—
44
64
—
—
—
—
62
—
—
—
45
66
—
—
—
—
41
—
—
—
—
45
Port C
C[0]
PCR[32]
C[1]
PCR[33]
C[2]
PCR[34]
62/128
SIUL
—
ADC_1
—
—
AN[3](3)
SIUL
—
ALT0
GPI[33]
—
ADC_0
—
—
AN[2](3)
—
SIUL
—
ALT0
GPI[34]
—
—
AN[3](3)
—
ADC_0
—
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 7. Pin muxing (continued)
Port
name
C[4]
C[5]
C[6]
C[7]
C[10]
C[11]
PCR
Peripheral
SIUL
GPIO[36]
ALT0
GPIO[36]
—
DSPI_0
CS0
ALT1
CS0
—
X[1]
ALT2
X[1]
PSMI[28];
PADSEL=0
SSCM
DEBUG[4]
ALT3
—
—
SIUL
—
—
EIRQ[22]
—
SIUL
GPIO[37]
ALT0
GPIO[37]
—
DSPI_0
SCK
ALT1
SCK
—
SSCM
DEBUG[5]
ALT3
—
—
PCR[36] FlexPWM_0
PCR[37]
FlexPWM_0
—
—
FAULT[3]
SIUL
—
—
EIRQ[23]
—
SIUL
GPIO[38]
ALT0
GPIO[38]
—
DSPI_0
SOUT
ALT1
—
—
B[1]
ALT2
B[1]
PSMI[25];
PADSEL=0
SSCM
DEBUG[6]
ALT3
—
—
SIUL
—
—
EIRQ[24]
—
SIUL
GPIO[39]
ALT0
GPIO[39]
—
FlexPWM_0
A[1]
ALT2
A[1]
PSMI[21];
PADSEL=0
SSCM
DEBUG[7]
ALT3
—
—
DSPI_0
—
—
SIN
—
SIUL
GPIO[42]
ALT0
GPIO[42]
—
DSPI_2
CS2
ALT1
—
—
A[3]
ALT3
A[3]
PSMI[23];
PADSEL=1
FlexPWM_0
—
—
FAULT[1]
PSMI[17];
PADSEL=0
SIUL
GPIO[43]
ALT0
GPIO[43]
—
eTimer_0
ETC[4]
ALT1
ETC[4]
PSMI[7];
PADSEL=1
DSPI_2
CS2
ALT2
—
—
PCR[42] FlexPWM_0
PCR[43]
Input
Output
mux sel functions
PSMI[19];
PADSEL=0
PCR[38] FlexPWM_0
PCR[39]
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Alternate
output
function
DocID023953 Rev 5
Pull
down
M
S
5
11
Pull
down
M
S
7
13
Pull
down
M
S
98
142
Pull
down
M
S
9
15
Pull
down
M
S
78
111
Pull
down
M
S
55
80
63/128
127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 7. Pin muxing (continued)
Port
name
C[12]
C[13]
C[14]
C[15]
PCR
PCR[44]
PCR[45]
PCR[46]
PCR[47]
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Peripheral
Alternate
output
function
SIUL
GPIO[44]
ALT0
GPIO[44]
—
eTimer_0
ETC[5]
ALT1
ETC[5]
PSMI[8];
PADSEL=0
DSPI_2
CS3
ALT2
—
—
SIUL
GPIO[45]
ALT0
GPIO[45]
—
eTimer_1
ETC[1]
ALT1
ETC[1]
PSMI[10];
PADSEL=0
EXT_IN
PSMI[0];
PADSEL=0
Input
Output
mux sel functions
CTU_0
—
—
FlexPWM_0
—
—
SIUL
GPIO[46]
ALT0
GPIO[46]
—
eTimer_1
ETC[2]
ALT1
ETC[2]
PSMI[11];
PADSEL=1
CTU_0
EXT_TGR
ALT2
—
—
SIUL
GPIO[47]
ALT0
GPIO[47]
—
FlexRay
CA_TR_E
N
ALT1
—
—
eTimer_1
ETC[0]
ALT2
ETC[0]
PSMI[9];
PADSEL=1
FlexPWM_0
A[1]
ALT3
A[1]
PSMI[21];
PADSEL=1
CTU_0
—
—
EXT_IN
PSMI[0];
PADSEL=1
FlexPWM_0
—
—
Pull
down
M
S
56
82
Pull
down
M
S
71
101
Pull
down
M
S
72
103
Pull
down
SYM
S
85
124
Pull
down
SYM
S
86
125
EXT_SYN PSMI[15];
C
PADSEL=0
EXT_SYN PSMI[15];
C
PADSEL=1
Port D
D[0]
64/128
PCR[48]
SIUL
GPIO[48]
ALT0
GPIO[48]
—
FlexRay
CA_TX
ALT1
—
—
eTimer_1
ETC[1]
ALT2
ETC[1]
PSMI[10];
PADSEL=1
FlexPWM_0
B[1]
ALT3
B[1]
PSMI[25];
PADSEL=1
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 7. Pin muxing (continued)
Port
name
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
PCR
PCR[49]
Peripheral
SIUL
GPIO[49]
ALT0
GPIO[49]
—
eTimer_1
ETC[2]
ALT2
ETC[2]
PSMI[11];
PADSEL=2
CTU_0
EXT_TGR
ALT3
—
—
FlexRay
—
—
CA_RX
—
SIUL
GPIO[50]
ALT0
GPIO[50]
—
eTimer_1
ETC[3]
ALT2
ETC[3]
PSMI[12];
PADSEL=1
Input
Output
mux sel functions
PCR[50]
PCR[51]
PCR[52]
PCR[53]
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Alternate
output
function
FlexPWM_0
X[3]
ALT3
X[3]
PSMI[30];
PADSEL=0
FlexRay
—
—
CB_RX
—
SIUL
GPIO[51]
ALT0
GPIO[51]
—
FlexRay
CB_TX
ALT1
—
—
eTimer_1
ETC[4]
ALT2
ETC[4]
PSMI[13];
PADSEL=1
FlexPWM_0
A[3]
ALT3
A[3]
PSMI[23];
PADSEL=2
SIUL
GPIO[52]
ALT0
GPIO[52]
—
FlexRay
CB_TR_E
N
ALT1
—
—
eTimer_1
ETC[5]
ALT2
ETC[5]
PSMI[14];
PADSEL=2
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[27];
PADSEL=2
SIUL
GPIO[53]
ALT0
GPIO[53]
—
DSPI_0
CS3
ALT1
—
—
FlexPWM_0
—
—
FAULT[2]
PSMI[18];
PADSEL=0
SIUL
GPIO[54]
ALT0
GPIO[54]
—
DSPI_0
CS2
ALT1
—
—
X[3]
ALT3
X[3]
PSMI[30];
PADSEL=1
—
—
FAULT[1]
PSMI[17];
PADSEL=1
PCR[54] FlexPWM_0
FlexPWM_0
DocID023953 Rev 5
Pull
down
M
S
3
3
Pull
down
M
S
—
140
Pull
down
SYM
S
89
128
Pull
down
SYM
S
90
129
Pull
down
M
S
22
33
Pull
down
M
S
23
34
65/128
127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 7. Pin muxing (continued)
Port
name
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[14]
66/128
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Peripheral
Alternate
output
function
SIUL
GPIO[55]
ALT0
GPIO[55]
—
DSPI_1
CS3
ALT1
—
—
DSPI_0
CS4
ALT3
—
—
SWG
analog
output
—
—
—
SIUL
GPIO[56]
ALT0
GPIO[56]
—
DSPI_1
CS2
ALT1
—
—
eTimer_1
ETC[4]
ALT2
ETC[4]
PSMI[13];
PADSEL=2
DSPI_0
CS5
ALT3
—
—
FlexPWM_0
—
—
FAULT[3]
PSMI[19];
PADSEL=1
SIUL
GPIO[57]
ALT0
GPIO[57]
—
PCR[57] FlexPWM_0
X[0]
ALT1
X[0]
—
LINFlexD_1
TXD
ALT2
—
—
SIUL
GPIO[58]
ALT0
GPIO[58]
—
FlexPWM_0
A[0]
ALT1
A[0]
PSMI[20];
PADSEL=1
eTimer_0
—
—
ETC[0]
PSMI[35];
PADSEL=1
SIUL
GPIO[59]
ALT0
GPIO[59]
—
FlexPWM_0
B[0]
ALT1
B[0]
PSMI[24];
PADSEL=1
eTimer_0
—
—
ETC[1]
PSMI[36];
PADSEL=1
SIUL
GPIO[60]
ALT0
GPIO[60]
FlexPWM_0
X[1]
ALT1
X[1]
PSMI[28];
PADSEL=1
LINFlexD_1
—
—
RXD
PSMI[32];
PADSEL=1
SIUL
GPIO[62]
ALT0
GPIO[62]
—
FlexPWM_0
B[1]
ALT1
B[1]
PSMI[25];
PADSEL=2
eTimer_0
—
—
ETC[3]
PSMI[38];
PADSEL=1
PCR
PCR[55]
PCR[56]
PCR[58]
PCR[59]
PCR[60]
PCR[62]
Input
Output
mux sel functions
DocID023953 Rev 5
Pull
down
M
S
26
37
Pull
down
M
S
21
32
Pull
down
M
S
15
26
Pull
down
M
S
53
76
Pull
down
M
S
54
78
Pull
down
M
S
70
99
Pull
down
M
S
73
105
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
Input
Output
mux sel functions
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Port E
E[0]
PCR[64]
E[2]
PCR[66]
E[4]
PCR[68]
E[5]
PCR[69]
E[6]
PCR[70]
E[7]
PCR[71]
E[9]
PCR[73]
E[10]
PCR[74]
E[11]
PCR[75]
E[12]
PCR[76]
E[13]
E[14]
E[15]
PCR[77]
PCR[78]
PCR[79]
SIUL
—
ALT0
GPI[64]
—
(3)
AN[5]
—
ADC_1
—
—
SIUL
—
ALT0
GPI[66]
—
ADC_0
—
—
AN[5](3)
—
SIUL
—
ALT0
GPI[68]
—
—
ADC_0
—
—
AN[7](3)
SIUL
—
ALT0
GPI[69]
—
ADC_0
—
—
AN[8](3)
—
SIUL
—
ALT0
GPI[70]
—
—
ADC_0
—
—
AN[4](3)
SIUL
—
ALT0
GPI[71]
—
ADC_0
—
—
AN[6](3)
—
SIUL
—
ALT0
GPI[73]
—
—
ADC_1
—
—
AN[7](3)
SIUL
—
ALT0
GPI[74]
—
ADC_1
—
—
AN[8](3)
—
SIUL
—
ALT0
GPI[75]
—
—
ADC_1
—
—
AN[4](3)
SIUL
—
ALT0
GPI[76]
—
ADC_1
—
—
AN[6](3)
—
SIUL
GPIO[77]
ALT0
GPIO[77]
—
eTimer_0
ETC[5]
ALT1
ETC[5]
PSMI[8];
PADSEL=1
DSPI_2
CS3
ALT2
—
—
SIUL
—
—
EIRQ[25]
—
SIUL
GPIO[78]
ALT0
GPIO[78]
—
eTimer_1
ETC[5]
ALT1
ETC[5]
PSMI[14];
PADSEL=3
SIUL
—
—
EIRQ[26]
—
SIUL
GPIO[79]
ALT0
GPIO[79]
—
DSPI_0
CS1
ALT1
—
—
SIUL
—
—
EIRQ[27]
—
DocID023953 Rev 5
—
—
—
46
68
—
—
—
32
49
—
—
—
—
42
—
—
—
—
44
—
—
—
—
46
—
—
—
—
48
—
—
—
—
61
—
—
—
—
63
—
—
—
—
65
—
—
—
—
67
Pull
down
M
S
—
117
Pull
down
M
S
—
119
Pull
down
M
S
—
121
67/128
127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
Input
Output
mux sel functions
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Port F
F[0]
PCR[83]
F[4]
PCR[84]
F[5]
PCR[85]
F[6]
PCR[86]
F[7]
PCR[87]
F[8]
PCR[88]
F[9]
PCR[89]
F[10]
PCR[90]
F[11]
PCR[91]
F[13]
68/128
GPIO[80]
ALT0
GPIO[80]
—
FlexPWM_0
A[1]
ALT1
A[1]
PSMI[21];
PADSEL=2
PCR[80]
F[3]
F[12]
SIUL
PCR[92]
PCR[93]
eTimer_0
—
—
ETC[2]
PSMI[37];
PADSEL=1
SIUL
—
—
EIRQ[28]
—
SIUL
GPIO[83]
ALT0
GPIO[83]
—
DSPI_0
CS6
ALT1
—
—
SIUL
GPIO[84]
ALT0
GPIO[84]
—
NPC
MDO[3]
ALT2
—
—
SIUL
GPIO[85]
ALT0
GPIO[85]
—
NPC
MDO[2]
ALT2
—
—
SIUL
GPIO[86]
ALT0
GPIO[86]
—
NPC
MDO[1]
ALT2
—
—
SIUL
GPIO[87]
ALT0
GPIO[87]
—
NPC
MCKO
ALT2
—
—
SIUL
GPIO[88]
ALT0
GPIO[88]
—
NPC
MSEO[1]
ALT2
—
—
SIUL
GPIO[89]
ALT0
GPIO[89]
—
NPC
MSEO[0]
ALT2
—
—
SIUL
GPIO[90]
ALT0
GPIO[90]
—
NPC
EVTO
ALT2
—
—
SIUL
GPIO[91]
ALT0
GPIO[91]
—
NPC
EVTI
ALT2
—
—
SIUL
GPIO[92]
ALT0
GPIO[92]
—
eTimer_1
ETC[3]
ALT1
ETC[3]
PSMI[12];
PADSEL=2
SIUL
—
—
EIRQ[30]
—
SIUL
GPIO[93]
ALT0
GPIO[93]
—
eTimer_1
ETC[4]
ALT1
ETC[4]
PSMI[13];
PADSEL=3
SIUL
—
—
EIRQ[31]
—
DocID023953 Rev 5
Pull
down
M
S
—
133
Pull
down
M
S
—
139
Pull
down
F
S
—
4
Pull
down
F
S
—
5
Pull
down
F
S
—
8
Pull
down
F
S
—
19
Pull
down
F
S
—
20
Pull
down
F
S
—
23
Pull
down
F
S
—
24
Pull
down
M
S
—
25
Pull
down
M
S
—
106
Pull
down
M
S
—
112
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 7. Pin muxing (continued)
Port
name
F[14]
F[15]
PCR
PCR[94]
PCR[95]
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Peripheral
Alternate
output
function
SIUL
GPIO[94]
ALT0
GPIO[94]
—
LINFlexD_1
TXD
ALT1
—
—
FlexCAN_2
RXD
ALT2
—
—
SIUL
GPIO[95]
ALT0
GPIO[95]
—
LINFlexD_1
—
—
RXD
PSMI[32];
PADSEL=2
FlexCAN_2
TXD
ALT2
—
—
Input
Output
mux sel functions
Pull
down
M
S
—
115
Pull
down
M
S
—
113
FCCU
FCCU
_
F[0]
—
FCCU
F[0]
ALT0
F[0]
—
—
S
S
27
38
FCCU
_
F[1]
—
FCCU
F[1]
ALT0
F[1]
—
—
S
S
97
141
Pull
down
M
S
—
102
Pull
down
M
S
—
104
Pull
down
M
S
—
100
Pull
down
M
S
—
85
Pull
down
M
S
—
98
Port G
SIUL
G[2]
G[3]
G[4]
G[5]
G[6]
GPIO[98]
ALT0
GPIO[98]
—
X[2]
ALT1
X[2]
PSMI[29];
PADSEL=1
DSPI_1
CS1
ALT2
—
—
SIUL
GPIO[99]
ALT0
GPIO[99]
—
FlexPWM_0
A[2]
ALT1
A[2]
PSMI[22];
PADSEL=2
eTimer_0
—
—
ETC[4]
PSMI[7];
PADSEL=3
SIUL
GPIO[100]
ALT0
GPIO[100]
—
FlexPWM_0
B[2]
ALT1
B[2]
PSMI[26];
PADSEL=2
eTimer_0
—
—
ETC[5]
PSMI[8];
PADSEL=3
SIUL
GPIO[101]
ALT0
GPIO[101]
—
X[3]
ALT1
X[3]
PSMI[30];
PADSEL=2
DSPI_2
CS3
ALT2
—
—
SIUL
GPIO[102]
ALT0
GPIO[102]
—
A[3]
PSMI[23];
PADSEL=3
PCR[98] FlexPWM_0
PCR[99]
PCR[100]
PCR[101] FlexPWM_0
PCR[102]
FlexPWM_0
A[3]
ALT1
DocID023953 Rev 5
69/128
127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 7. Pin muxing (continued)
Port
name
PCR
G[7]
PCR[103]
G[8]
G[9]
PCR[104]
PCR[105]
G[10] PCR[106]
G[11] PCR[107]
G[12] PCR[108]
G[13] PCR[109]
G[14] PCR[110]
G[15] PCR[111]
70/128
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Peripheral
Alternate
output
function
SIUL
GPIO[103]
ALT0
GPIO[103]
FlexPWM_0
B[3]
ALT1
B[3]
PSMI[27];
PADSEL=3
SIUL
GPIO[104]
ALT0
GPIO[104]
—
FlexRay
DBG0
ALT1
—
—
DSPI_0
CS1
ALT2
—
—
Input
Output
mux sel functions
FlexPWM_0
—
—
FAULT[0]
PSMI[16];
PADSEL=2
SIUL
—
—
EIRQ[21]
—
SIUL
GPIO[105]
ALT0
GPIO[105]
—
FlexRay
DBG1
ALT1
—
—
DSPI_1
CS1
ALT2
—
—
FlexPWM_0
—
—
FAULT[1]
PSMI[17];
PADSEL=2
SIUL
—
—
EIRQ[29]
—
SIUL
GPIO[106]
ALT0
GPIO[106]
—
FlexRay
DBG2
ALT1
—
—
DSPI_2
CS3
ALT2
—
—
FlexPWM_0
—
—
FAULT[2]
PSMI[18];
PADSEL=1
SIUL
GPIO[107]
ALT0
GPIO[107]
—
FlexRay
DBG3
ALT1
—
—
FlexPWM_0
—
—
FAULT[3]
PSMI[19];
PADSEL=2
SIUL
GPIO[108]
ALT0
GPIO[108]
—
NPC
MDO[11]
ALT2
—
—
SIUL
GPIO[109]
ALT0
GPIO[109]
—
NPC
MDO[10]
ALT2
—
—
SIUL
GPIO[110]
ALT0
GPIO[110]
—
NPC
MDO[9]
ALT2
—
—
SIUL
GPIO[111]
ALT0
GPIO[111]
—
NPC
MDO[8]
ALT2
—
—
DocID023953 Rev 5
Pull
down
M
S
—
83
Pull
down
M
S
—
81
Pull
down
M
S
—
79
Pull
down
M
S
—
77
Pull
down
M
S
—
75
Pull
down
F
S
—
—
Pull
down
F
S
—
—
Pull
down
F
S
—
—
Pull
down
F
S
—
—
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
Input
Output
mux sel functions
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Port H
H[0]
PCR[112]
H[1]
PCR[113]
H[2]
PCR[114]
H[3]
PCR[115]
H[4]
H[5]
H[6]
H[7]
H[8]
H[9]
PCR[116]
SIUL
GPIO[112]
ALT0
GPIO[112]
—
NPC
MDO[7]
ALT2
—
—
SIUL
GPIO[113]
ALT0
GPIO[113]
—
NPC
MDO[6]
ALT2
—
—
SIUL
GPIO[114]
ALT0
GPIO[114]
—
NPC
MDO[5]
ALT2
—
—
SIUL
GPIO[115]
ALT0
GPIO[115]
—
NPC
MDO[4]
ALT2
—
—
SIUL
GPIO[116]
ALT0
GPIO[116]
—
FlexPWM_1
X[0]
ALT1
X[0]
—
eTimer_2
ETC[0]
ALT2
ETC[0]
PSMI[39];
PADSEL=0
SIUL
GPIO[117]
ALT0
GPIO[117]
—
A[0]
ALT1
A[0]
—
DSPI_0
CS4
ALT3
—
—
SIUL
GPIO[118]
ALT0
GPIO[118]
—
B[0]
ALT1
B[0]
—
DSPI_0
CS5
ALT3
—
—
SIUL
GPIO[119]
ALT0
GPIO[119]
—
FlexPWM_1
X[1]
ALT1
X[1]
—
PCR[117] FlexPWM_1
PCR[118] FlexPWM_1
PCR[119]
eTimer_2
ETC[1]
ALT2
ETC[1]
PSMI[40];
PADSEL=0
SIUL
GPIO[120]
ALT0
GPIO[120]
—
A[1]
ALT1
A[1]
—
DSPI_0
CS6
ALT3
—
—
SIUL
GPIO[121]
ALT0
GPIO[121]
—
B[1]
ALT1
B[1]
—
DSPI_0
CS7
ALT3
—
—
SIUL
GPIO[122]
ALT0
GPIO[122]
—
X[2]
ALT1
X[2]
—
ETC[2]
ALT2
ETC[2]
—
PCR[120] FlexPWM_1
PCR[121] FlexPWM_1
H[10] PCR[122] FlexPWM_1
eTimer_2
DocID023953 Rev 5
Pull
down
F
S
—
—
Pull
down
F
S
—
—
Pull
down
F
S
—
—
Pull
down
F
S
—
—
Pull
down
M
S
—
—
Pull
down
M
S
—
—
Pull
down
M
S
—
—
Pull
down
M
S
—
—
Pull
down
M
S
—
—
Pull
down
M
S
—
—
Pull
down
M
S
—
—
71/128
127
Package pinouts and signal descriptions
SPC56EL70L3, SPC56EL70L5,PC564L70L3,
Table 7. Pin muxing (continued)
Port
name
PCR
H[11] PCR[123]
H[12] PCR[124]
H[13] PCR[125]
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Peripheral
Alternate
output
function
SIUL
GPIO[123]
ALT0
GPIO[123]
—
FlexPWM_1
A[2]
ALT1
A[2]
—
SIUL
GPIO[124]
ALT0
GPIO[124]
—
FlexPWM_1
B[2]
ALT1
B[2]
—
SIUL
GPIO[125]
ALT0
GPIO[125]
—
FlexPWM_1
X[3]
ALT1
X[3]
—
Input
Output
mux sel functions
eTimer_2
ETC[3]
ALT2
ETC[3]
PSMI[42];
PADSEL=0
SIUL
GPIO[126]
ALT0
GPIO[126]
—
A[3]
ALT1
A[3]
—
eTimer_2
ETC[4]
ALT2
ETC[4]
—
SIUL
GPIO[127]
ALT0
GPIO[127]
—
B[3]
ALT1
B[3]
—
ETC[5]
ALT2
ETC[5]
—
H[14] PCR[126] FlexPWM_1
H[15] PCR[127] FlexPWM_1
eTimer_2
Pull
down
M
S
—
—
Pull
down
M
S
—
—
Pull
down
M
S
—
—
Pull
down
M
S
—
—
Pull
down
M
S
—
—
Pull
down
M
S
—
—
Pull
down
M
S
—
—
Pull
down
M
S
—
—
Port I
I[0]
I[1]
I[2]
72/128
PCR[128]
PCR[129]
PCR[130]
SIUL
GPIO[128]
ALT0
GPIO[128]
—
eTimer_2
ETC[0]
ALT1
ETC[0]
PSMI[39];
PADSEL=1
DSPI_0
CS4
ALT2
—
—
FlexPWM_1
—
—
FAULT[0]
—
SIUL
GPIO[129]
ALT0
GPIO[129]
—
eTimer_2
ETC[1]
ALT1
ETC[1]
PSMI[40];
PADSEL=1
DSPI_0
CS5
ALT2
—
—
FlexPWM_1
—
—
FAULT[1]
—
SIUL
GPIO[130]
ALT0
GPIO[130]
—
eTimer_2
ETC[2]
ALT1
ETC[2]
PSMI[41];
PADSEL=1
DSPI_0
CS6
ALT2
—
—
FlexPWM_1
—
—
FAULT[2]
—
DocID023953 Rev 5
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Package pinouts and signal descrip-
Table 7. Pin muxing (continued)
Port
name
I[3]
RDY
PCR
PCR[131]
PCR[132]
Pad
Weak
Pin #
pull
speed(1)
Input mux
config
select
during SRC SRC 100 144
reset
=1
= 0 pkg pkg
Peripheral
Alternate
output
function
SIUL
GPIO[131]
ALT0
GPIO[131]
—
eTimer_2
ETC[3]
ALT1
ETC[3]
PSMI[42];
PADSEL=1
DSPI_0
CS7
ALT2
—
—
CTU_0
EXT_TGR
ALT3
—
—
FlexPWM_1
—
—
FAULT[3]
—
SIUL
GPIO[132]
ALT0
GPIO[132]
—
NPC
RDY
ALT2
—
—
Input
Output
mux sel functions
Pull
down
M
S
—
—
Pull
down
F
S
—
—
1. Programmable via the SRC (Slew Rate Control) bit in the respective Pad Configuration Register; S = Slow, M = Medium,
F = Fast, SYM = Symmetric (for FlexRay).
2. The default function of this pin out of reset is ALT1 (TDO).
3. Analog.
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SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
3
Electrical characteristics
3.1
Introduction
This section contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for this device.
This device is designed to operate at 120 MHz. The electrical specifications are preliminary
and are from previous designs, design simulations, or initial evaluation. These specifications
may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications
have been completed.
The “Symbol” column of the electrical parameter and timings tables contains an additional
column containing “SR”, “CC”, “P”, “C”, “T”, or “D”.
3.2
“SR” identifies system requirements—conditions that must be provided to ensure
normal device operation. An example is the input voltage of a voltage regulator.
“CC” identifies controller characteristics—indicating the characteristics and timing of
the signals that the chip provides.
“P”, “C”, “T”, or “D” apply only to controller characteristics—specifications that define
normal device operation. They specify how each characteristic is guaranteed.
–
P: parameter is guaranteed by production testing of each individual device.
–
C: parameter is guaranteed by design characterization. Measurements are taken
from a statistically relevant sample size across process variations.
–
T: parameter is guaranteed by design characterization on a small sample size
from typical devices under typical conditions unless otherwise noted. All values
are shown in the typical (“typ”) column are within this category.
–
D: parameters are derived mainly from simulations.
Absolute maximum ratings
Table 8. Absolute maximum ratings(1)
Symbol
Parameter
Conditions
Min
Max
Unit
V
VDD_HV_REG
SR 3.3 V voltage regulator supply voltage
—
–0.3
4.5(2), (3)
VDD_HV_IOx
SR 3.3 V input/output supply voltage
—
–0.3
4.5(2), (3)
V
VSS_HV_IOx
SR Input/output ground voltage
—
–0.1
0.1
V
V
VDD_HV_FLA
SR 3.3 V flash supply voltage
—
–0.3
4.5(2), (3)
VSS_HV_FLA
SR Flash memory ground
—
–0.1
0.1
V
VDD_HV_OSC
SR 3.3 V crystal oscillator amplifier supply
voltage
—
–0.3
4.5(2), (3)
V
VSS_HV_OSC
SR 3.3 V crystal oscillator amplifier reference
voltage
—
–0.1
0.1
V
—
–0.3
6.4(2)
V
VDD_HV_ADR0(2), (3) SR 3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high reference voltage
VDD_HV_ADR1
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Electrical characteristics
Table 8. Absolute maximum ratings(1) (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
VSS_HV_ADR0
VSS_HV_ADR1
SR ADC_0 ground and low reference voltage
ADC_1 ground and low reference voltage
—
–0.1
0.1
V
VDD_HV_ADV
SR 3.3 V ADC supply voltage
—
–0.3
4.5(3), (4)
V
VSS_HV_ADV
SR 3.3 V ADC supply ground
—
–0.1
0.1
V
TVDD
SR Supply ramp rate
SR Voltage on any pin with respect to ground
(VSS_HV_IOx)or Vss_HV_ADRx
VIN
-6
—
3.0 × 10
(3.0 V/sec)
0.5 V/µs
V/µs
Valid only for
ADC pins
–0.3
6.0(4)
V
Relative to
VDD
–0.3
VDD + 0.3(4),
(5)
IINJPAD
SR Injected input current on any pin during
overload condition
—
–10
10
mA
IINJSUM
SR Absolute sum of all injected input currents
during overload condition
—
–50
50
mA
SR Storage temperature
—
–55
150
°C
TSTG
1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability or cause permanent damage to the device.
2. Any voltage between operating condition and absolute max rating can be sustained for maximum cumulative time of 10
hours.
3. Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
4. Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the
maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications.
5. VDD has to be considered equal to VDD_HV_ADRx in case of ADC pins, whilst it is VDD_HV_IOx for any other pin.
3.3
Recommended operating conditions
Table 9. Recommended operating conditions (3.3 V)
Symbol
Parameter
Conditions
Min(1)
Max
Unit
VDD_HV_REG
SR
3.3 V voltage regulator supply voltage
—
3.0
3.63
V
VSS_HV_REG
SR
3.3 V voltage regulator reference voltage
—
0
0
V
VDD_HV_IOx
SR
3.3 V input/output supply voltage
—
3.0
3.63
V
VSS_HV_IOx
SR
Input/output ground voltage
—
0
0
V
VDD_HV_FLA
SR
3.3 V flash supply voltage
—
3.0
3.63
V
VSS_HV_FLA
SR
Flash memory ground
—
0
0
V
VDD_HV_OSC
SR
3.3 V crystal oscillator amplifier supply
voltage
—
3.0
3.63
V
VSS_HV_OSC
SR
3.3 V crystal oscillator amplifier reference
voltage
—
0
0
V
VDD_HV_ADR0(2),(3)
VDD_HV_ADR1
SR
3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high reference voltage
—
4.5 to 5.5 or
3.0 to 3.63
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Electrical characteristics
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Table 9. Recommended operating conditions (3.3 V) (continued)
Symbol
Parameter
Conditions
Min(1)
Max
Unit
VDD_HV_ADV
SR
3.3 V ADC supply voltage
—
3.0
3.63
V
VSS_HV_AD0
VSS_HV_AD1
SR
ADC_0 ground and low reference voltage
ADC_1 ground and low reference voltage
—
0
0
V
VSS_HV_ADV
SR
3.3 V ADC supply ground
—
0
0
V
(4)
SR
Internal supply voltage
—
—
—
V
VSS_LV_REGCOR(5)
VDD_LV_REGCOR
SR
Internal reference voltage
—
0
0
V
(2)
SR
Internal supply voltage
—
—
—
V
(3)
VDD_LV_CORx
SR
Internal reference voltage
—
0
0
V
VDD_LV_PLL(2)
SR
Internal supply voltage
—
—
—
V
VSS_LV_PLL(3)
SR
Internal reference voltage
—
0
0
V
TA
SR
Ambient temperature under bias
–40
125
°C
TJ
SR
Junction temperature under bias
–40
150
°C
VSS_LV_CORx
fCPU
120 MHz
—
1. Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and
I/Os DC electrical specification may not be guaranteed.
2. VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated at different voltages, and need to be supplied by the same voltage
source.
3. VDD_HV_ADRx must always be applied and should be stable before LBIST starts. If this supply is not above its absolute
minimum level, LBIST operations can fail.
4. Can be connected to emitter of external NPN. Low voltage supplies are not under user control. They are produced by an
on-chip voltage regulator.
5. For the device to function properly, the low voltage grounds (VSS_LV_xxx) must be shorted to high voltage grounds
(VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter, if one is used.
3.4
Decoupling capacitors
The internal voltage regulator requires an external NPN ballast and some additional
decoupling capacitors. These capacitors shall be placed on the board as close as possible
to the associated pin.
Table 10. Decoupling capacitors
Symbol
Parameter
Value
Conditions(1)
Unit
Min
CCOL
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
Max ESR = 100 mΩ.
CLV1
SR
External decoupling /
stability capacitor
Sum of CLV1 placed close to
VDD/VSS_LV_CORy pairs(2).
CLV2
SR
External decoupling /
stability capacitor
Sum of CLV2 placed close to
VDD/VSS_LV_CORy pairs shall be
between 300 nF and 900 nF.
CPMU1
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
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Typ
Max
20
12µF
µF
40µF
µF
100(2)
nF
10
µF
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Electrical characteristics
Table 10. Decoupling capacitors (continued)
Symbol
Parameter
Value
Conditions(1)
Unit
Min
Typ
Max
CPMU2
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
100
nF
CREG
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
20
µF
CIO1
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
100
nF
CIO2
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
470
pF
CFLA1
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
100
nF
CFLA2
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
10
nF
COSC1
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
100
nF
COSC2
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
10
nF
CPLL1
SR
External decoupling /
stability capacitor
CADR1
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
Ceramic capacitor.
10
nF
CADR2
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
Ceramic capacitor.
47
nF
CADR3
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
Electrolytic or tantalum capacitor.
1
µF
CADV1
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
Ceramic capacitor.
10
nF
CADV2
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
Ceramic capacitor.
47
nF
CADV3
SR
External decoupling /
stability capacitor
Accuracy -50%/+35%.
Electrolytic or tantalum capacitor.
1
µF
22
100
nF
1. Capacitors shall be placed as close as possible to the respective pads.
2. Total ESR considering all decoupling capacitor close to the VDD/VSS_LV_CORy pairs shall be between 1 mΩ and 100 mΩ.
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Electrical characteristics
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Figure 4. Decoupling capacitors
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;7$/
&&26&
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
3.5
Electrical characteristics
Thermal characteristics
Table 11. Thermal characteristics for LQFP100 package(1)
Symbol
RJA
RJMA
RJB
RJC
JT
Parameter
Conditions
D Thermal resistance, junction-to-ambient natural Single layer board – 1s
convection(2)
Four layer board – 2s2p
Value
Unit
46
°C/W
34
D Thermal resistance, junction-to-ambient forced Single layer board – 1s
convection at 200 ft/min
Four layer board – 2s2p
28
D Thermal resistance junction-to-board(3)
—
19
°C/W
—
8
°C/W
—
2
°C/W
D Thermal resistance junction-to-case
(4)
D Junction-to-package-top natural convection
(5)
36
°C/W
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
Table 12. Thermal characteristics for LQFP144 package(1)
Symbol
Parameter
Conditions
Value
RJA
D
Thermal resistance, junction-to-ambient natural Single layer board – 1s
convection(2)
Four layer board – 2s2p
RJMA
D
Thermal resistance, junction-to-ambient forced Single layer board – 1s
convection at 200 ft/min
Four layer board – 2s2p
30
RJB
D
Thermal resistance junction-to-board(3)
—
24
°C/W
—
8
°C/W
—
2
°C/W
RJC
JT
D
D
Thermal resistance junction-to-case
Junction-to-package-top natural
(4)
convection(5)
42
Unit
34
35
°C/W
°C/W
1. Thermal characteristics are targets based on simulation that are subject to change per device characterization.
2. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
3.5.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
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Electrical characteristics
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Equation 1 TJ = TA + (RJA × PD)
where:
TA= ambient temperature for the package (oC)
RJA= junction to ambient thermal resistance (oC/W)
PD= power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by a
factor of two. Which value is closer to the application depends on the power dissipated by
other components on the board. The value obtained on a single layer board is appropriate
for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are
well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a
junction to case thermal resistance and a case to ambient thermal resistance:
Equation 2
RJA = RJC + RCA
where:
RJA = junction to ambient thermal resistance (°C/W)
RJC= junction to case thermal resistance (°C/W)
RCA= case to ambient thermal resistance (°C/W)
RJC is device related and cannot be influenced by the user. The user controls the thermal
environment to change the case to ambient thermal resistance, RCA. For instance, the user
can change the size of the heat sink, the air flow around the device, the interface material,
the mounting arrangement on printed circuit board, or change the thermal dissipation on the
printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are
not used, the Thermal Characterization Parameter (JT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using Equation 3:
Equation 3 TJ = TT + (JT × PD)
where:
TT= thermocouple temperature on top of the package (°C)
JT= thermal characterization parameter (°C/W)
PD= power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40
gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the package.
A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of
wire extending from the junction. The thermocouple wire is placed flat against the package
case to avoid measurement errors caused by cooling effects of the thermocouple wire.
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3.5.1.1
Electrical characteristics
References
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134 USA
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering
Documents at 800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB in JEDEC site.
3.6
1.
C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998,
pp. 47–54.
2.
G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled
Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.
3.
B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San
Diego, 1999, pp. 212–220.
Electromagnetic Interference (EMI) characteristics
The characteristics in Table 14 were measured using:
Device configuration, test conditions, and EM testing per standard IEC61967-2
Supply voltage of 3.3 V DC
Ambient temperature of 25 C
The configuration information referenced in Table 14 is explained in Table 13.
Table 13. EMI configuration summary
Configuration name
Description
Configuration A
–
–
–
–
–
High emission = all pads have max slew rate, LVDS pads running at 40 MHz
Oscillator frequency = 40 MHz
System bus frequency = 120 MHz
No PLL frequency modulation
IEC level K ( 30 dBV)
Configuration B
–
–
–
–
–
Reference emission = pads use min, mid and max slew rates, LVDS pads disabled
Oscillator frequency = 40 MHz
System bus frequency = 120 MHz
2% PLL frequency modulation
IEC level K( 30 dBV)
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Electrical characteristics
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Table 14. EMI emission testing specifications
Symbol
VEME
Parameter
CC Radiated emissions
Conditions
Min
Typ
Max
Unit
Configuration A; frequency range
150 kHz–50 MHz
—
10
—
dBV
Configuration A; frequency range 50–
150 MHz
—
18
—
Configuration A; frequency range 150–
500 MHz
—
30
—
Configuration A; frequency range 500–
1000 MHz
—
18
—
Configuration B; frequency range 50–
150 MHz
—
10
—
Configuration B; frequency range 50–
150 MHz
—
18
—
Configuration B; frequency range 150–
500 MHz
—
30
—
Configuration B; frequency range 500–
1000 MHz
—
18
—
EME testing was performed and documented according to these standards: [IEC 61967-2 &
-4]
EMS testing was performed and documented according to these standards: [IEC 62132-2 &
-4]
3.7
Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This test
conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the
application note Electrostatic Discharge Sensitivity Measurement (AN1181).
Table 15. ESD ratings(1)(2)
No.
Symbol
Parameter
Conditions
Class Max value(3) Unit
1
VESD(HBM)
SR
Electrostatic discharge
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100002
H1C
2000
V
2
VESD(MM)
SR
Electrostatic discharge
(Machine Model)
TA = 25 °C
conforming to AEC-Q100003
M2
200
V
3
VESD(CDM)
SR
Electrostatic discharge
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100011
C3A
500
750
(corners)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
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Electrical characteristics
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
3. Data based on characterization results, not tested in production.
3.8
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 16. Latch-up results
No.
1
Symbol
LU
3.9
SR
Parameter
Static latch-up class
Conditions
Class
TA = 125 °C conforming to JESD 78
II level A
Voltage regulator electrical characteristics
The voltage regulator is composed of the following blocks:
High power regulator HPREG1 (internal ballast to support core current)
High power regulator HPREG2 (external NPN to support core current)
Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (VDDIO)
Low voltage detector (LVD_MAIN_2) for 3.3 V supply (VDDREG)
Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (VDDFLASH)
Low voltage detector (LVD_DIG_MAIN) for 1.2 V digital core supply (HPVDD)
Low voltage detector (LVD_DIG_BKUP) for the self-test of LVD_DIG_MAIN
High voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPVDD)
High voltage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN.
Power on Reset (POR)
HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when
external NPN transistor is present on board to supply core current. The SPC56XL70 always
powers up using HPREG1 if an external NPN transistor is present. Then the SPC56XL70
makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is
fully operational, the controller part of HPREG1 is switched off. The following bipolar
transistors are supported:
BCP68 from ON Semiconductor
BCX68 from Infineon
Table 17. Recommended operating characteristics
Symbol
hFE( )
PD
Parameter
DC current gain (Beta)
Maximum power dissipation @
TA=25°C(1)
DocID023953 Rev 5
Value
Unit
85 - 375
—
1.5
W
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Electrical characteristics
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
Table 17. Recommended operating characteristics (continued)
Symbol
Parameter
Value
Unit
1.0
A
ICMaxDC
Maximum peak collector current
VCESAT
Collector-to-emitter saturation
voltage(Max)
600(2)
mV
VBE
Base-to-emitter voltage (Max)
1.0
V
1. Derating factor 12mW/degC.
2. Adjust resistor at bipolar transistor collector for 3.3V to avoid VCE
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