SPC582B60E1CD00X

SPC582Bx SPC58 2B Line - 32 bit Power Architecture automotive MCU Single core 80Mhz, 1MByte Flash, ASIL-B Datasheet - production data – Cyclic redundancy check (CRC) unit – End-to-end Error Correction Code (e2eECC) logic eTQFP64 (10 x 10 x 1.0 mm) eTQFP100 (14 x 14 x 1.0 mm) QFN48 (7 x 7 x 0.9 mm) Features • AEC-Q100 qualified • High performance e200z2 single core – 32-bit Power Architecture technology CPU – Core frequency as high as 80 MHz – Variable Length Encoding (VLE) – Floating Point, End-to-End Error Correction • 1088 KB (1024 KB code flash + 64 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation • 96 KB on-chip general-purpose SRAM • Multi-channel direct memory access controller (eDMA) with 16 channels • 1 interrupt controller (INTC) • Comprehensive new generation ASIL-B safety concept – ASIL-B of ISO 26262 – FCCU for collection and reaction to failure notifications – Memory Error Management Unit (MEMU) for collection and reporting of error events in memories December 2020 This is information on a product in full production. • Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC • Body cross triggering unit (BCTU) – Triggers ADC conversions from any eMIOS channel – Triggers ADC conversions from up to 2 dedicated PIT_RTIs – 1 event configuration register dedicated to each timer event allows to define the corresponding ADC channel – Synchronization with ADC to avoid collision • 1 enhanced 12-bit SAR analog-to-digital converters – Up to 27 channels – enhanced diagnosis feature • Communication interfaces – 6 LINFlexD modules – 4 deserial serial peripheral interface (DSPI) modules – 7 MCAN interfaces with advanced shared memory scheme and ISO CAN FD support • Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell • Nexus Class 3 debug and trace interface • Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART. • Enhanced modular IO subsystem (eMIOS): up to 32 timed I/O channels with 16-bit counter resolution • Advanced and flexible supply scheme – On-chip voltage regulator for 1.2 V core logic supply. • Junction temperature range -40 °C to 150 °C DS11597 Rev 4 1/115 www.st.com Table 1. Device summary Part number Package 2/115 1 MB 768 kB 512 kB eTQFP64 SPC582B60E1 SPC582B54E1 SPC582B50E1 eTQFP100 SPC582B60E3 SPC582B54E3 SPC582B50E3 QFN48 SPC582B60Q3 SPC582B54Q3 SPC582B50Q3 DS11597 Rev 4 SPC582Bx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Feature overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 12 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.1 Power domains and power up/down sequencing . . . . . . . . . . . . . . . . . 17 4.4 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 Electromagnetic compatibility characteristics . . . . . . . . . . . . . . . . . . . . . . 20 4.6 Temperature profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.7 Device consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.8 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8.1 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8.2 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.8.3 I/O pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.9 Reset pad (PORST) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 35 4.10 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.11 4.12 4.10.1 PLL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.10.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.11.1 Crystal oscillator 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.11.2 RC oscillator 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.11.3 Low power RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 ADC system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.12.1 ADC input description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.12.2 SAR ADC 12 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 46 DS11597 Rev 4 3/115 4 Contents SPC582Bx 4.13 5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.13.1 Power management integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.13.2 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.13.3 Voltage monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.14 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.15 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.15.1 Debug and calibration interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.15.2 DSPI timing with CMOS pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.15.3 CAN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.15.4 UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.15.5 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.1 eTQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.1.1 5.2 eTQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.2.1 5.3 Package mechanical drawings and data information . . . . . . . . . . . . . . 95 QFN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.4.1 5.5 Package mechanical drawings and data information . . . . . . . . . . . . . . 90 eTQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.3.1 5.4 Package mechanical drawings and data information . . . . . . . . . . . . . . 85 Package mechanical drawings and data information . . . . . . . . . . . . . . 98 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.5.1 eTQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.5.2 eTQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.5.3 QFN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.5.4 General notes for specifications at maximum junction temperature . . 101 6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4/115 DS11597 Rev 4 SPC582Bx 1 Introduction Introduction This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet. DS11597 Rev 4 5/115 11 Description 2 SPC582Bx Description The SPC582Bx microcontroller is the entry member of a new family of devices superseding the SPC560Bx family. SPC582Bx is built on the legacy of the SPC5x products, while introducing new features to answer the future requirements like the ASIL-B classification, high number of ISO CAN-FD channels, and provide significant power and performance improvement (MIPS per mW). 2.1 Device feature summary Table 2 lists a summary of major features for the SPC582Bx device. The feature column represents a combination of module names and capabilities of certain modules. A detailed description of the functionality provided by each on-chip module is given later in this document. Table 2. SPC582Bx device feature summary Feature Description SPC58 family 40 nm Number of Cores 1 Single Precision Floating Point Yes SIMD No VLE Yes MPU Yes CRC Channels 2x4 Software Watchdog Timer (SWT) 1 Core Nexus Class 3+ 4 x SCU Event Processor 6/115 4 x PMC Run control Module Yes System SRAM 96 KB (including 64 KB of standby RAM) Flash 1088 KB (1024 code flash + 64 KB data flash) Flash fetch accelerator 2 x 4 x 256-bit DMA channels 16 DMA Nexus Class 3 LINFlexD 6 MCAN (ISO CAN-FD) 7 DSPI 4 I2C 1 DS11597 Rev 4 SPC582Bx Description Table 2. SPC582Bx device feature summary (continued) Feature Description 8 PIT channels 4 AUTOSAR® (STM) System Timers RTC/API eMIOS 32 channels BCTU 32 channels Interrupt controller 1 x 151 sources ADC (SAR) One 12-bit, up to 27 channels Self Test Controller Yes PLL Dual PLL with FM Integrated linear voltage regulator Yes External Power Supplies 5 V, 3.3 V STOP Mode Low Power Modes HALT Mode Standby Mode 2.2 Block diagram The figures below show the top-level block diagrams. DS11597 Rev 4 7/115 11 Description SPC582Bx Figure 1. Block diagram JTAGM JTAGC DCI SPU NPC INTC VLE 16 Ch eDMA Nexus3p EFPU2 Core Memory Protection Unit (CMPU) 32 ADD 32 DATA Instruction 32 ADD 32 DATA E2E ECC Nexus Data Trace Load / Store 32 ADD 32 DATA Delayed Lock-step with Redundancy Checkers DMA CHMUX SWT IAC e200 z215n3 – 80 MHz single issue Main Core BIU with E2E ECC Decorated Storage Access Instruction 32 ADD 32 DATA 32 ADD 32 DATA M2 AHB_M4 AHB_M6 Load / Store 32 ADD 32 DATA AHB_M5 M0 M1 Cross Bar Switch (XBAR) AMBA 2.0 v6 AHB – 32 bit 8/115 System Memory Protection Unit S0 S2 S5 S4 32 ADD 32 DATA 32 ADD 32 DATA 32 ADD 32 DATA Periph. Bridge AIPS_2 E2E ECC Periph. Bridge AIPS_1 E2E ECC PRAMC_2 with E2E ECC 32 ADD 32 DATA 32 ADD 32 DATA 32 ADD 32 DATA Peripheral Cluster 2 Peripheral Cluster 1 SRAM Array 2 96 KB DS11597 Rev 4 32 ADD 32 DATA S1 32 ADD 32 DATA PFLASHC Set-Associative MiniCache with E2E ECC 128 Page Line FLASH 1 MB EEPROM 4x16 KB Non Volatile Memory Multiple RWW partitions SPC582Bx Description Figure 2. Periphery allocation BCTU_0 PBRIDGE_2 eMIOS_0 XBAR_1 SMPU_1 SAR_ADC_12bit_B0 XBIC_1 I2C_0 PCM_0 DSPI_0, 2 PFLASH_1 LINFLEX_0, 2, 10 CAN_SUB_0_MESSAGE_RAM INTC_1 CAN_SUB_0_M_CAN_0..3 SWT_2 CCCU STM_2 DTS eDMA_1 JDC PRAM_2 STCU TDM_0 JTAGM MEMU IMA DMAMUX_0 PIT_0 RTC/API WKPU MC_PCU PMC_DIG MC_RGM PBRIDGE_2 – Peripheral Cluster 2 CRC_0 RCOSC_DIG RC1024K_DIG DSPI_1, 3 OSC_DIG LINFlex_1, 7, 15 PLL_DIG CAN_SUB_1_MESSAGE_RAM CAN_SUB_1_M_CAN_1..3 MC_CGM FCCU MC_ME CRC_1 SIUL2 CMU_1_CORE_XBAR FLASH_0 CMU_2_HPBM PASS CMU_3_PBRIDGE SSCM CMU_6_SARADC CMU_11_FBRIDGE PBRIDGE_1 – Peripheral Cluster 1 CMU_0_PLL0_XOSC_IRCOSC PBRIDGE_1 CMU_12_EMIOS CMU_14_PFBRIDGE Note: In this diagram, ON-platform modules are shown in orange color and OFF-platform modules are shown in blue color. DS11597 Rev 4 9/115 11 Description 2.3 SPC582Bx Feature overview On-chip modules within SPC582Bx include the following features: • • One main CPU, single issue, 32-bit CPU core complexes (e200z2). – Power Architecture embedded specification compliance – Instruction set enhancement allowing variable length encoding (VLE), encoding a mix of 16-bit and 32-bit instructions, for code size footprint reduction – Single-precision floating point operations 1088 KB (1024 KB code flash + 64 KB data flash) on-chip Flash memory – • 96 KB on-chip general-purpose SRAM • Multi channel direct memory access controllers – 16 eDMA channels • One interrupt controller (INTC) • Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell • Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC • System integration unit lite (SIUL) • Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART. • Hardware support for safety ASIL-B level related applications • Enhanced modular IO subsystem (eMIOS): up to 32 timed I/O channels with 16-bit counter resolution – • • 10/115 Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation Buffered updates – Support for shifted PWM outputs to minimize occurrence of concurrent edges – Supports configurable trigger outputs for ADC conversion for synchronization to channel output waveforms – Shared or independent time bases – DMA transfer support available Body cross triggering unit (BCTU) – Triggers ADC conversions from any eMIOS channel – Triggers ADC conversions from up to 2 dedicated PIT_RTIs – One event configuration register dedicated to each timer event allows to define the corresponding ADC channel – Synchronization with ADC to avoid collision One 12-bit SAR analog-to-digital converter – up to 27 channels – enhanced diagnosis features • Four deserial serial peripheral interface (DSPI) modules • Six LIN and UART communication interface (LINFlexD) modules – LINFlexD_0 is a Master/Slave – All others are Masters DS11597 Rev 4 SPC582Bx Description • Seven modular controller area network (MCAN) modules, all supporting flexible data rate (ISO CAN-FD) • Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard • Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1 and IEEE 1149.7), 2-pin JTAG interface • On-chip voltage regulator controller manages the supply voltage down to 1.2 V for core logic • Self-test capability DS11597 Rev 4 11/115 11 Package pinouts and signal descriptions 3 SPC582Bx Package pinouts and signal descriptions Refer to the SPC582Bx IO_ Definition document. It includes the following sections: 12/115 1. Package pinouts 2. Pin descriptions a) Power supply and reference voltage pins b) System pins c) Generic pins DS11597 Rev 4 SPC582Bx Electrical characteristics 4 Electrical characteristics 4.1 Introduction The present document contains the target Electrical Specification for the 40 nm family 32-bit MCU SPC582Bx products. In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” (Controller Characteristics) is included in the “Symbol” column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” (System Requirement) is included in the “Symbol” column. The electrical parameters shown in this document are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 3 are used and the parameters are tagged accordingly in the tables where appropriate. Table 3. Parameter classifications Classification tag Tag description P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design validation on a small sample size from typical devices. D Those parameters are derived mainly from simulations. DS11597 Rev 4 13/115 13 Electrical characteristics 4.2 SPC582Bx Absolute maximum ratings Table 4 describes the maximum ratings for the device. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Stress beyond the listed maxima, even momentarily, may affect device reliability or cause permanent damage to the device. Table 4. Absolute maximum ratings Value Symbol C Parameter Conditions Unit Min Typ Max VDD_LV SR D Core voltage operating life range(1) — –0.3 — 1.4 V VDD_HV_IO_MAIN VDD_HV_OSC VDD_HV_FLA SR D I/O supply voltage(2) — –0.3 — 6.0 V VSS_HV_ADV SR D ADC ground voltage Reference to digital ground –0.3 — 0.3 V VDD_HV_ADV SR D ADC Supply voltage(2) Reference to VSS_HV_ADV –0.3 — 6.0 V VSS_HV_ADR_S SR D SAR ADC ground reference — –0.3 — 0.3 V VDD_HV_ADR_S SR D SAR ADC voltage reference(2) Reference to VSS_HV_ADR_S –0.3 — 6.0 V VSS-VSS_HV_ADR_S SR D VSS_HV_ADR_S differential voltage — –0.3 — 0.3 V VSS-VSS_HV_ADV SR D VSS_HV_ADV differential voltage — –0.3 — 0.3 V — –0.3 — 6.0 Relative to Vss –0.3 — — Relative to VDD_HV_IO and VDD_HV_ADV — — 0.3 VIN TTRIN IINJ 14/115 SR SR SR D I/O input voltage range(2)(3) (4) V D Digital Input pad transition time(5) — — — 1 ms T Maximum DC injection current for each analog/digital PAD(6) — –5 — 5 mA DS11597 Rev 4 SPC582Bx Electrical characteristics Table 4. Absolute maximum ratings (continued) Value Symbol TSTG TPAS C SR SR Parameter Conditions Unit Min Typ Max T Maximum nonoperating Storage temperature range — –55 — 125 °C C Maximum nonoperating temperature during passive lifetime — –55 — 150(7) °C — — 20 years TSTORAGE SR — Maximum No supply; storage storage time, temperature in assembled part range –40 °C to programmed in 60 °C ECU TSDR SR T Maximum solder temperature Pbfree packaged(8) — — — 260 °C MSL SR T Moisture sensitivity level(9) — — — 3 — Maximum cumulated XRAY dose Typical range for X-rays source during inspection:80 ÷ 130 KV; 20 ÷ 50 μA — — 1 grey TXRAY dose SR T 1. VDD_LV: allowed 1.335 V - 1.400 V for 60 seconds cumulative time at the given temperature profile. Remaining time allowed 1.260 V - 1.335 V for 10 hours cumulative time at the given temperature profile. Remaining time as defined in Section 4.3: Operating conditions. 2. VDD_HV: allowed 5.5 V – 6.0 V for 60 seconds cumulative time at the given temperature profile, for 10 hours cumulative time with the device in reset at the given temperature profile. Remaining time as defined in Section 4.3: Operating conditions. 3. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3 V can be used for nominal calculations. 4. Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameter IINJ). 5. This limitation applies to pads with digital input buffer enabled. If the digital input buffer is disabled, there are no maximum limits to the transition time. 6. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in Section 4.8.3: I/O pad current specifications. 7. 175°C are allowed for limited time. Mission profile with passive lifetime temperature >150°C have to be evaluated by ST to confirm that are granted by product qualification. 8. Solder profile per IPC/JEDEC J-STD-020D. 9. Moisture sensitivity per JDEC test method A112. DS11597 Rev 4 15/115 15 Electrical characteristics 4.3 SPC582Bx Operating conditions Table 5 describes the operating conditions for the device, and for which all the specifications in the data sheet are valid, except where explicitly noted. The device operating conditions must not be exceeded or the functionality of the device is not guaranteed. Table 5. Operating conditions Value(1) Symbol C Parameter Conditions Unit Min Typ Max FSYS SR P Operating system clock frequency(4) — — — 80 MHz TJ SR C Operating Junction temperature — –40 — 150 °C TA SR P Operating Ambient temperature — –40 — 125 °C VDD_LV SR P Core supply voltage(2) — 1.14 1.20 1.26(3) (4) V SR P IO supply voltage — 3.0 — 5.5 V VDD_HV_ADV SR P ADC supply voltage — 3.0 — 5.5 V VSS_HV_ADVVSS SR D ADC ground differential voltage — –25 — 25 mV VDD_HV_ADR_S SR P SAR ADC reference voltage — 3.0 — 5.5 V D SAR ADC reference differential voltage — — — 25 mV — VDD_HV_IO_MAIN VDD_HV_FLA VDD_HV_OSC VDD_HV_ADR_SVDD_HV_ADV SR VSS_HV_ADR_S SR P SAR ADC ground reference voltage VSS_HV_ADR_SVSS_HV_ADV SR D VSS_HV_ADR_S differential voltage — –25 — 25 mV VRAMP_HV SR D Slew rate on HV power supply — — — 100 V/ms 16/115 DS11597 Rev 4 V VSS_HV_ADV SPC582Bx Electrical characteristics Table 5. Operating conditions (continued) Value(1) Symbol VIN IINJ1 C SR SR P T Parameter I/O input voltage range Injection current (per pin) without performance degradation(5) Conditions Unit Min Typ Max — 0 — 5.5 V Digital pins and analog pins –3.0 — 3.0 mA Digital pins and analog pins –10 — 10 mA (6) (7) IINJ2 SR D Dynamic Injection current (per pin) with performance degradation(7) (8) 1. The ranges in this table are design targets and actual data may vary in the given range. 2. Core voltage as measured on device pin to guarantee published silicon performance. 3. Core voltage can exceed 1.26 V with the limitations provided in Section 4.2: Absolute maximum ratings, provided that HVD134_C monitor reset is disabled. 4. 1.260 V - 1.290 V range allowed periodically for supply with sinusoidal shape and average supply value below or equal to 1.236 V at the given temperature profile. 5. Full device lifetime. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See Section 4.2: Absolute maximum ratings for maximum input current for reliability requirements. 6. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pins is above the supply rail, current will be injected through the clamp diode to the supply rails. For external RC network calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature. 7. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in Section 4.8.3: I/O pad current specifications. 8. Positive and negative Dynamic current injection pulses are allowed up to this limit. I/O and ADC specifications are not granted. See the dedicated chapters for the different specification limits. See the Absolute Maximum Ratings table for maximum input current for reliability requirements. Refer to the following pulses definitions: Pulse1 (ISO 7637-2:2011), Pulse 2a(ISO 7637-2:2011 5.6.2), Pulse 3a (ISO 7637-2:2011 5.6.3), Pulse 3b (ISO 7637-2:2011 5.6.3). 4.3.1 Power domains and power up/down sequencing The following table shows the constraints and relationships for the different power domains. Supply1 (on rows) can exceed Supply2 (on columns), only if the cell at the given row and column is reporting ‘ok’. This limitation is valid during power-up and power-down phases, as well as during normal device operation. DS11597 Rev 4 17/115 18 Electrical characteristics SPC582Bx Table 6. Device supply relation during power-up/power-down sequence Supply2 VDD_HV_IO_MAIN VDD_LV VDD_HV_FLA VDD_HV_ADV VDD_HV_ADR ok ok Supply1 VDD_HV_OSC VDD_HV_IO_MAIN VDD_HV_FLA VDD_HV_OSC(1) ok VDD_HV_ADV ok not allowed VDD_HV_ADR ok not allowed ok not allowed 1. The application shall grant that these supplies are always at the same voltage level. During power-up, all functional terminals are maintained in a known state as described in the device pinout Microsoft Excel file attached to the IO_Definition document. 18/115 DS11597 Rev 4 SPC582Bx 4.4 Electrical characteristics Electrostatic discharge (ESD) The following table describes the ESD ratings of the device: • All ESD testing are in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits, • Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification requirements, which include the complete DC parametric and functional testing at room temperature and hot temperature, maximum DC parametric variation within 10% of maximum specification”. Table 7. ESD ratings Parameter ESD for Human Body Model (HBM)(1) ESD for field induced Charged Device Model (CDM)(2) C Conditions Value Unit T All pins 2000 V T All pins 500 V T Corner Pins 750 V 1. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing. 2. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level. DS11597 Rev 4 19/115 19 Electrical characteristics 4.5 SPC582Bx Electromagnetic compatibility characteristics EMC measurements at IC-level IEC standards are available from STMicroelectronics on request. 20/115 DS11597 Rev 4 SPC582Bx 4.6 Electrical characteristics Temperature profile The device is qualified in accordance to AEC-Q100 Grade1 requirements, such as HTOL 1,000 h and HTDR 1,000 hrs, TJ = 150 °C. DS11597 Rev 4 21/115 21 Electrical characteristics 4.7 SPC582Bx Device consumption Table 8. Device consumption Value(1) Symbol IDD_LKG(2),(3) C CC Parameter Conditions Typ Max C TJ = 40 °C — — 2 D TJ = 25 °C — 0.65 1 D Leakage current on the VDD_LV supply D TJ = 55 °C — — 2.5 TJ = 95 °C — — 6 D TJ = 120 °C — — 14 P TJ = 150 °C — — 35 — — — 50 mA mA IDD_LV(3) CC P Dynamic current on the VDD_LV supply, very high consumption profile(4) IDD_HV CC P Total current on the VDD_HV supply(4) fMAX — — 37 mA IDD_LV_GW CC T Dynamic current on the VDD_LV supply, gateway profile(5) — — — 48 mA IDD_HV_GW CC T Dynamic current on the VDD_HV supply, gateway profile(5) — — — 17 mA T Dynamic current on the VDD_LV supply +Total current on the VDD_HV supply — — 26 37 mA T Dynamic current on the VDD_LV supply +Total current on the VDD_HV supply — — 6.5 9 mA TJ = 25 °C — 40 90 TJ = 40 °C — — 135 TJ = 55 °C — — 210 TJ = 120 °C — — 1.2 P TJ = 150 °C — — 2.5 D TJ = 25 °C — 55 125 TJ = 40 °C — — 190 TJ = 55 °C — — 290 TJ = 120 °C — — 1.6 TJ = 150 °C — — 3.5 IDDHALT(6) IDDSTOP(7) CC CC D C IDDSTBY8 CC D D C IDDSTBY64 CC D D Total standby mode current on VDD_LV and VDD_HV supply, 8 KB RAM(8) Total standby mode current on VDD_LV and VDD_HV supply, 64 KB RAM(8) P 1. The ranges in this table are design targets and actual data may vary in the given range. 22/115 Unit Min DS11597 Rev 4 µA mA µA mA SPC582Bx Electrical characteristics 2. The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered, and they are computed in the dynamic IDD_LV and IDD_HV parameters. 3. IDD_LKG (leakage current) and IDD_LV (dynamic current) are reported as separate parameters, to give an indication of the consumption contributors. The tests used in validation, characterization and production are verifying that the total consumption (leakage+dynamic) is lower or equal to the sum of the maximum values provided (IDD_LKG + IDD_LV). The two parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions and the software profile used. 4. Use case: 1 x e200Z2 @80 MHz, all IPs clock enabled, Flash access with prefetch disabled, Flash consumption includes parallel read and program/erase, 1xSARADC in continuous conversion, DMA continuously triggered by ADC conversion, 4 DSPI / 3 CAN / 2 LINFlex transmitting, RTC and STM running, 1xEMIOS running (12 channels in OPWMT mode), FIRC, SIRC, FXOSC, PLL0-1 running. The switching activity estimated for dynamic consumption does not include I/O toggling, which is highly dependent on the application. Details of the software configuration are separately. The total device consumption is IDD_LV + IDD_HV + IDD_LKG for the selected temperature. 5. Gateway use case: One core running at 80 MHz, DMA, PLL, FLASH read only 25%, 7xCAN, 1xSARADC. 6. Flash in Low Power. Sysclk at 80 MHz, PLL0_PHI at 80 MHz, XTAL at 8 MHz, FIRC 16 MHz ON, RCOSC1M off. FlexCAN: instances: 0, 1, 2, 3, 4, 5, 6 ON (configured but no reception or transmission), ADC ON (continuously converting). All others IPs clock-gated. 7. Sysclk = RC16 MHz, RC16 MHz ON, RC1 MHz ON, PLL OFF. All possible peripherals off and clock gated. Flash in power down mode. 8. STANDBY mode: device configured for minimum consumption, RC16 MHz off, RC1 MHz on. DS11597 Rev 4 23/115 23 Electrical characteristics 4.8 SPC582Bx I/O pad specification The following table describes the different pad type configurations. Table 9. I/O pad specification descriptions Pad type Description Weak configuration Provides a good compromise between transition time and low electromagnetic emission. Medium configuration Strong configuration Very strong configuration Input only pads Standby pads Note: Provides transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. Provides fast transition speed; used for fast interface. Provides maximum speed and controlled symmetric behavior for rise and fall transition. Used for fast interface requiring fine control of rising/falling edge jitter. These low input leakage pads are associated with the ADC channels. Some pads are active during Standby. Low Power Pads input buffer can only be configured in TTL mode. When the pads are in Standby mode, the Pad-Keeper feature is activated: if the pad status is high, the weak pull-up resistor is automatically enabled; if the pad status is low, the weak pull-down resistor is automatically enabled. Each I/O pin on the device supports specific drive configurations. See the signal description table in the device reference manual for the available drive configurations for each I/O pin. PMC_DIG_VSIO register has to be configured to select the voltage level (3.3 V or 5.0 V) for each IO segment. Logic level is configurable in running mode while it is TTL not-configurable in STANDBY for LP (low power) pads, so if a LP pad is used to wakeup from STANDBY, it should be configured as TTL also in running mode in order to prevent device wrong behavior in STANDBY. 4.8.1 I/O input DC characteristics The following table provides input DC electrical characteristics, as described in Figure 3. 24/115 DS11597 Rev 4 SPC582Bx Electrical characteristics Figure 3. I/O input electrical characteristics VIN VDD VIH VHYS VIL VINTERNAL (SIUL register) Table 10. I/O input electrical characteristics Value Symbol C Parameter Conditions Unit Min Typ Max TTL Vihttl SR P Input high level TTL — 2 — VDD_HV_IO + 0.3 V Vilttl SR P Input low level TTL — –0.3 — 0.8 V Vhysttl CC C Input hysteresis TTL — 0.3 — — V CMOS Vihcmos SR P Input high level CMOS — 0.65 * VDD — VDD_HV_IO + 0.3 V Vilcmos SR P Input low level CMOS — –0.3 — 0.35 * VDD V Vhyscmos CC C Input hysteresis CMOS — 0.10 * VDD — — V COMMON ILKG CC P Pad input leakage INPUT-ONLY pads TJ = 150 °C — — 200 nA ILKG CC P Pad input leakage STRONG pads TJ = 150 °C — — 1,000 nA ILKG CC P Pad input leakage VERY STRONG pads, TJ = 150 °C — — 1,000 nA DS11597 Rev 4 25/115 34 Electrical characteristics SPC582Bx Table 10. I/O input electrical characteristics (continued) Value Symbol C Parameter Conditions Unit Min Typ Max CP1 CC D Pad capacitance — — — 10 pF Vdrift CC D Input Vil/Vih temperature drift In a 1 ms period, with a temperature variation 3 V –4 4 –6 6 TJ < 150 °C, VDD_HV_ADV > 3 V, Total unadjusted error VDD_HV_ADR_S > 3 V in 12-bit TJ < 150 °C, configuration(7) > 3 V, V µA mA LSB –6 6 D High frequency mode, TJ < 150 °C, VDD_HV_ADV > 3 V, VDD_HV_ADR_S > 3 V –12 12 D Mode 1, TJ < 150 °C, VDD_HV_ADV > 3 V VDD_HV_ADR_S > 3 V –1.5 1.5 –2.0 2.0 DD_HV_ADV µA (12b) 3 V > VDD_HV_ADR_S > 2 V D TUE10 CC C C 48/115 Mode 1, TJ < 150 °C, VDD_HV_ADV > 3 V, Total unadjusted error 3 V > V DD_HV_ADR_S > 2 V in 10-bit Mode 2, TJ < 150 °C, configuration(7) VDD_HV_ADV > 3 V VDD_HV_ADR_S > 3 V Mode 3, TJ < 150 °C, VDD_HV_ADV > 3 V VDD_HV_ADR_S > 3 V DS11597 Rev 4 LSB (10b) –3.0 3.0 –4.0 4.0 SPC582Bx Electrical characteristics Table 25. SARn ADC electrical specification (continued) Value Symbol ΔTUE12 C CC D Parameter Differential nonlinearity CC T Unit Min Max VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [0:25 mV] –1 1 VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [25:50 mV] –2 2 VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [50:75 mV] –4 4 VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [75:100 mV] –6 6 –2.5 2.5 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [25:50 mV] –4 4 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [50:75 mV] –7 7 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [75:100 mV] –12 12 Standard frequency mode, VDD_HV_ADV > 4 V VDD_HV_ADR_S > 4 V –1 2 High frequency mode, VDD_HV_ADV > 4 V VDD_HV_ADR_S > 4 V –1 TUE degradation due V DD_HV_ADV < VIN < to VDD_HV_ADR offset V DD_HV_ADR with respect to VDD_HV_ADR − VDD_HV_ADV VDD_HV_ADV ∈ [0:25 mV] P DNL(8) Conditions LSB (12b) LSB (12b) 2 1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within the sampling window. Refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration. 2. Mode1: 6 sampling cycles + 10 conversion cycles at 13.33 MHz. 3. Mode2: 5 sampling cycles + 10 conversion cycles at 13.33 MHz. 4. Mode3: 6 sampling cycles + 10 conversion cycles at 16 MHz. 5. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven by the transfer of charge between internal capacitances during the conversion. 6. Current parameter values are for a single ADC. DS11597 Rev 4 49/115 50 Electrical characteristics SPC582Bx 7. TUE is granted with injection current within the range defined in Table 24, for parameters classified as T and D. 8. DNL is granted with injection current within the range defined in Table 24, for parameters classified as T and D. 50/115 DS11597 Rev 4 SPC582Bx 4.13 Electrical characteristics Power management The power management module monitors the different power supplies as well as it generates the required internal supplies. The device can operate in the following configurations: Table 26. Power management regulators Device External regulator Internal SMPS regulator SPC582Bx — — Internal linear regulator external ballast Internal linear regulator internal ballast Auxiliary regulator Clamp regulator Internal standby regulator(1) — X — — X 1. Standby regulator is automatically activated when the device enters standby mode. 4.13.1 Power management integration Use the integration schemes provided below to ensure the proper device function, according to the selected regulator configuration. The internal regulators are supplied by VDD_HV_IO_MAIN supply and are used to generate VDD_LV supply. Place capacitances on the board as near as possible to the associated pins and limit the serial inductance of the board to less than 5 nH. It is recommended to use the internal regulators only to supply the device itself. DS11597 Rev 4 51/115 57 Electrical characteristics SPC582Bx Figure 9. Internal regulator with internal ballast mode 52/115 DS11597 Rev 4 SPC582Bx Electrical characteristics Figure 10. Standby regulator with internal ballast mode &)/$ &( 966 9''B+9B,2 9''B+9B)/$ &%9 9''B+9B,2 &+9Q 6WDQGE\ 5HJ 9''B/9 966 &/9Q 966 966B+9B$'9 9''B+9B$'9 &$'& Table 27. External components integration Symbol C Value Conditions(1) Parameter Unit Min Typ Max — — 1 — µF Total resistance including board track 5 — 50 mΩ Each VDD_LV/VSS pair — 100 — nF Common Components CE SR D Internal voltage regulator stability external capacitance(2) (3) RE SR D Stability capacitor equivalent serial resistance CLVn SR Internal voltage regulator D decoupling external capacitance RLVn SR D Stability capacitor equivalent serial resistance — — — 50 mΩ CBV SR Bulk capacitance for HV supply D (2) on one VDD_HV_IO_MAIN/ VSS pair — 4.7 — µF CHVn SR D Decoupling capacitance for ballast and IOs (2) on all VDD_HV_IO/VSS and VDD_HV_ADR/VSS pairs — 100 — nF (2) (4) (5) DS11597 Rev 4 53/115 57 Electrical characteristics SPC582Bx Table 27. External components integration (continued) Symbol C Value Conditions(1) Parameter CFLA SR D Decoupling capacitance for Flash supply (2) (6) CADC SR D ADC supply external capacitance(2) (6) Unit Min Typ Max — — 10 — nF VDD_HV_ADV/VSS_HV_ADV pair — 0.5 — µF 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TJ = –40 / 150 °C, unless otherwise specified. 2. Recommended X7R or X5R ceramic –50% / +35% variation across process, temperature, voltage and after aging. 3. CE capacitance is required both in internal and external regulator mode. 4. For noise filtering, add a high frequency bypass capacitance of 10 nF. 5. For applications it is recommended to implement at least 5 CLV capacitances. 6. Recommended X7R capacitors. For noise filtering, add a high frequency bypass capacitance of 100 nF. 54/115 DS11597 Rev 4 SPC582Bx 4.13.2 Electrical characteristics Voltage regulators Table 28. Linear regulator specifications Value Symbol C Parameter Conditions CC P Main regulator output voltage VMREG CC P Unit Min Typ Max Power-up, before trimming, no load 1.13 1.21 1.29 After trimming, maximum load 1.09 1.19 1.26 — — 85 mA Power-up condition — — 40 mA 20 µs observation window -50 — 50 mA IMREG = max — — 1.1 IMREG = 0 mA — — 1.1 V Main regulator current provided to VDD_LV domain The maximum current required by T the device (IDD_LV) may exceed the maximum current which can be provided by the internal linear regulator. In this case, the internal regulator mode cannot be used. IDDMREG CC IDDCLAMP Main regulator rush current sinked from VDD_HV_IO_MAIN CC D domain during VDD_LV domain loading ΔIDDMREG CC T IMREGINT CC D Main regulator current D consumption Main regulator output current variation — mA Table 29. Standby regulator specifications Value Symbol VSBY IDDSBY 4.13.3 C Parameter Conditions CC P Standby regulator output voltage CC T After trimming, maximum load Standby regulator current provided to VDD_LV domain — Unit Min Typ Max 0.92 0.98 1.19 V — 0.984 5 mA Voltage monitors The monitors and their associated levels for the device are given in Table 30. Figure 11 illustrates the workings of voltage monitoring threshold. DS11597 Rev 4 55/115 57 Electrical characteristics SPC582Bx Figure 11. Voltage monitor threshold definition VDD_xxx VHVD VLVD TVMFILTER TVMFILTER HVD TRIGGER (INTERNAL) TVMFILTER TVMFILTER LVD TRIGGER (INTERNAL) Table 30. Voltage monitor electrical characteristics Symbol C Supply/Parameter(1) Value(2) Conditions Unit Min Typ Max 1.80 2.02 2.40 V PowerOn Reset HV VPOR200_C CC P VDD_HV_IO_MAIN — Minimum Voltage Detectors HV VMVD270_C CC P VDD_HV_IO_MAIN — 2.71 2.76 2.80 V VMVD270_F CC P VDD_HV_FLA — 2.71 2.76 2.80 V CC P VDD_HV_IO_MAIN (in Standby) — 2.68 2.76 2.84 V VMVD270_SBY Low Voltage Detectors HV VLVD290_C CC P VDD_HV_IO_MAIN — 2.89 2.94 2.99 V VLVD290_F CC P VDD_HV_FLA — 2.89 2.94 2.99 V VLVD290_AS CC P VDD_HV_ADV (ADCSAR pad) — 2.89 2.94 2.99 V VLVD400_AS CC P VDD_HV_ADV (ADCSAR pad) — 4.15 4.23 4.31 V VLVD400_IM CC P VDD_HV_IO_MAIN — 4.15 4.23 4.31 V 56/115 DS11597 Rev 4 SPC582Bx Electrical characteristics Table 30. Voltage monitor electrical characteristics (continued) Symbol C Supply/Parameter(1) Value(2) Conditions Unit Min Typ Max Minimum Voltage Detectors LV VMVD082_C CC P VDD_LV — 0.85 0.88 0.91 V VMVD094_C CC P VDD_LV — 0.98 1.00 1.02 V VMVD094_FA CC P VDD_LV (Flash) — 1.00 1.02 1.04 V VMVD094_FB CC P VDD_LV (Flash) — 1.00 1.02 1.04 V Low Voltage Detectors LV VLVD100_C CC P VDD_LV — 1.06 1.08 1.11 V VLVD100_SB CC P VDD_LV (In Standby) — 0.91 0.93 0.95 V VLVD100_F CC P VDD_LV (Flash) — 1.08 1.10 1.12 V 1.28 1.31 1.33 V — 1.34 1.37 1.39 V — 5 — 25 μs High Voltage Detectors LV VHVD134_C CC P VDD_LV — Upper Voltage Detectors LV VUVD140_C CC P VDD_LV Common TVMFILTER CC D Voltage monitor filter(3) 1. Even if LVD/HVD monitor reaction is configurable, the application ensures that the device remains in the operative condition range, and the internal LVDx monitors are disabled by the application. Then an external voltage monitor with minimum threshold of VDD_LV(min) = 1.08 V measured at the device pad, has to be implemented. For HVDx, if the application disables them, then they need to grant that VDD_LV and VDD_HV voltage levels stay withing the limitations provided in Section 4.2: Absolute maximum ratings. 2. The values reported are Trimmed values, where applicable. 3. See Figure 11. Transitions shorter than minimum are filtered. Transitions longer than maximum are not filtered, and will be delayed by TVMFILTER time. Transitions between minimum and maximum can be filtered or not filtered, according to temperature, process and voltage variations. DS11597 Rev 4 57/115 57 Electrical characteristics 4.14 SPC582Bx Flash The following table shows the Wait State configuration. Table 31. Wait State configuration RWSC CORE FREQUENCY (MHZ) 2 f < 80 1 f < 54 0 f < 27 The following table shows the Program/Erase Characteristics. Table 32. Flash memory program and erase specifications Value Characteristics(1)(2) Symbol Lifetime Initial max Typ(3) C (6) All temp C 25 °C (7) Typical end of life(4) max(5) Unit C < 1 K < 250 K cycles cycles tdwprogram Double Word (64 bits) program time [Packaged part] 51 C 156 — — 168 500 C µs tpprogram Page (256 bits) program time 86 C 288 — — 288 1000 C µs tpprogrameep Page (256 bits) program time Data Flash - EEPROM (partition 1) [Packaged part] 100 C 316 — — 331 1000 C µs Quad Page (1024 bits) program time 264 C 1248 1440 P 1020 2000 C µs tqprogrameep Quad Page (1024 bits) program time Data Flash EEPROM (partition 1) [Packaged part] 294 C 1368 1584 P 1173 2000 C µs t16kpperase 16 KB block pre-program and erase time 230 C 500 550 P 265 1000 — C ms t32kpperase 32 KB block pre-program and erase time 320 C 584 670 P 370 1200 — C ms t64kpperase 64 KB block pre-program and erase time 500 C 800 850 P 575 1600 — C ms t128kpperase 128 KB block pre-program and erase time 850 C 1520 1870 P 930 4000 — C ms — — C — — P — — — C ms t16kprogram 16 KB block program time 40 C 54 60 P 48 1000 — C ms t32kprogram 32 KB block program time 80 C 108 120 P 90 1200 — C ms t64kprogram 64 KB block program time 162 C 210 240 P 180 1600 — C ms tqprogram — 58/115 DS11597 Rev 4 SPC582Bx Electrical characteristics Table 32. Flash memory program and erase specifications (continued) Value Symbol Characteristics Typ(3) C (6) All temp C 25 °C t128kprogram (7) Typical end of life(4) max(5) Unit C < 1 K < 250 K cycles cycles 324 C 420 516 P 360 2000 — C ms — C — — P — — — C ms 47 C 62 70 P 77 1750 C ms Erase 16 KB Data Flash EEPROM (partition 1) [Packaged part] 250 C 584 864 P 475 3600 C ms tprr Program rate(8) 2.59 C 3.36 4.12 C 2.88 — C s/M B terr Erase rate(8) 6.8 C 12.1 14.9 C 7.44 — C s/M B tprfm Program rate Factory Mode(8) 1.76 C 2.25 2.75 C — — C s/M B terfm Erase rate Factory Mode(8) 5.0 C 8.2 9.8 C — — C s/M B Full flash programming time(9) 2.59 C 3.37 4.12 P 2.89 — — C s 5.16 C 13.8 16.4 P 7.81 — — C s — 128 KB block program time Lifetime Initial max (1)(2) — Program 16 KB Data Flash t16kprogrameep EEPROM (partition 1) [Packaged part] t16keraseeep tffprogram time(9) tfferase Full flash erasing tESRT Erase suspend request rate(10) 200 T — — — — — — µs tPSRT Program suspend request rate(10) 30 T — — — — — — µs tAMRT Array Integrity Check - Margin Read suspend request rate 15 T — — — — — — µs tPSUS Program suspend latency(11) — — — — — — 12 T µs tESUS Erase suspend latency(11) — — — — — — 22 T µs tAIC0S Array Integrity Check (1.0 MB, sequential)(12) 60 T — — — — — — — ms Array Integrity Check (128 KB, sequential)(12) 2.5 T — — — — — — — ms tAIC0P Array Integrity Check (1.0 MB, proprietary)(12) 7.2 T — — — — — — — tMR0S Margin Read (1.0 MB, sequential)(12) 300 T — — — — — — — ms tMR256KS Margin Read (128 KB, sequential)(12) 12.5 T — — — — — — — ms tAIC256KS DS11597 Rev 4 s 59/115 60 Electrical characteristics SPC582Bx 1. Characteristics are valid both for Data Flash and Code Flash, unless specified in the characteristics column. 2. Actual hardware operation times; this does not include software overhead. 3. Typical program and erase times assume nominal supply values and operation at 25 °C. 4. Typical End of Life program and erase times represent the median performance and assume nominal supply values. Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but not tested. 5. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified number of program/erase cycles. These maximum values are characterized but not tested or guaranteed. 6. Initial factory condition: < 100 program/erase cycles, 25 °C typical junction temperature and nominal (± 5%) supply voltages. 7. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for less than or equal to 100 program or erase cycles, –40 °C < TJ < 150 °C junction temperature and nominal (± 5%) supply voltages. 8. Rate computed based on 128 KB sectors. 9. Only code sectors, not including EEPROM. 10. Time between suspend resume and next suspend. Value stated actually represents Min value specification. 11. Timings guaranteed by design. 12. AIC is done using system clock, thus all timing is dependent on system frequency and number of wait states. Timing in the table is calculated at max frequency. All the Flash operations require the presence of the system clock for internal synchronization. About 50 synchronization cycles are needed: this means that the timings of the previous table can be longer if a low frequency system clock is used. Table 33. Flash memory Life Specification Symbol Value Characteristics(1) (2) Unit Min C Typ C NCER16K 16 KB CODE Flash endurance 10 — 100 — Kcycles NCER32K 32 KB CODE Flash endurance 10 — 100 — Kcycles NCER64K 64 KB CODE Flash endurance 10 — 100 — Kcycles 1 — 100 — Kcycles 1 — 100 — Kcycles 10 — 100 — Kcycles 16 KB DATA EEPROM Flash endurance 250 — — — Kcycles tDR1k Minimum data retention Blocks with 0 - 1,000 P/E cycles 25 — — — Years tDR10k Minimum data retention Blocks with 1,001 - 10,000 P/E cycles 20 — — — Years tDR100k Minimum data retention Blocks with 10,001 - 100,000 P/E cycles 15 — — — Years tDR250k Minimum data retention Blocks with 100,001 250,000 P/E cycles 10 — — — Years NCER128K 128 KB CODE Flash endurance NCER256K NDER16K 128 KB CODE Flash endurance 128 KB CODE Flash endurance(3) 1. Program and erase cycles supported across specified temperature specifications. 2. It is recommended that the application enables the core cache memory. 3. 10K cycles on 4-128 KB blocks is not intended for production. Reduced reliability and degraded erase time are possible. 60/115 DS11597 Rev 4 SPC582Bx 4.15 Electrical characteristics AC Specifications All AC timing specifications are valid up to 150 °C, except where explicitly noted. 4.15.1 Debug and calibration interface timing 4.15.1.1 JTAG interface timing Table 34. JTAG pin AC electrical characteristics Value(1),(2) # Symbol C Characteristic Unit Min Max 1 tJCYC CC D TCK cycle time 100 — ns 2 tJDC CC T TCK clock pulse width 40 60 % 3 tTCKRISE CC D TCK rise and fall times (40%–70%) — 3 ns 4 tTMSS, tTDIS CC D TMS, TDI data setup time 5 — ns 5 tTMSH, tTDIH CC D TMS, TDI data hold time 5 — ns ns 6 tTDOV CC D TCK low to TDO data valid — 15(3) 7 tTDOI CC D TCK low to TDO data invalid 0 — ns 8 tTDOHZ CC D TCK low to TDO high impedance — 15 ns 9 tJCMPPW CC D JCOMP assertion time 100 — ns 10 tJCMPS CC D JCOMP setup time to TCK low 40 — ns ns 11 tBSDV CC D TCK falling edge to output valid — 600(4) 12 tBSDVZ CC D TCK falling edge to output valid out of high impedance — 600 ns 13 tBSDHZ CC D TCK falling edge to output high impedance — 600 ns 14 tBSDST CC D Boundary scan input valid to TCK rising edge 15 — ns 15 tBSDHT CC D TCK rising edge to boundary scan input invalid 15 — ns 1. These specifications apply to JTAG boundary scan only. See Table 35 for functional specifications. 2. JTAG timing specified at VDD_HV_IO_JTAG = 4.0 to 5.5 V and max. loading per pad type as specified in the I/O section of the datasheet. 3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay. 4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay. DS11597 Rev 4 61/115 80 Electrical characteristics SPC582Bx Figure 12. JTAG test clock input timing TCK 2 3 2 1 3 Figure 13. JTAG test access port timing TCK 4 TMS, TDI 6 8 7 TDO 62/115 DS11597 Rev 4 SPC582Bx Electrical characteristics Figure 14. JTAG JCOMP timing TCK 10 JCOMP 9 Figure 15. JTAG boundary scan timing TCK 11 13 Output Signals 12 Output Signals 14 15 Input Signals DS11597 Rev 4 63/115 80 Electrical characteristics 4.15.1.2 SPC582Bx Nexus interface timing Table 35. Nexus debug port timing Value(1) # Symbol C Characteristic 7 tEVTIPW 8 tEVTOPW CC D EVTO pulse width tTCYC Max 4 — tCYC(2) 40 CC D EVTI pulse width — ns (3),(4) — tCYC(2) Absolute minimum TCK cycle time(5) (TDO sampled on posedge CC D of TCK) 40(6) — Absolute minimum TCK cycle time(7) (TDO sampled on negedge of TCK) (6) TCK cycle time 9 Unit Min 2 ns 20 — 11 tNTDIS CC D TDI data setup time 5 — ns 12 tNTDIH CC D TDI data hold time 5 — ns 13 tNTMSS CC D TMS data setup time 5 — ns 14 tNTMSH CC D TMS data hold time 5 — ns 15 — CC D TDO propagation delay from falling edge of TCK(8) — 16 ns 16 — CC D 2.25 — ns TDO hold time with respect to TCK falling edge (minimum TDO propagation delay) 1. Nexus timing specified at VDD_HV_IO_JTAG = 3.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O section of the data sheet. 2. tCYC is system clock period. 3. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number greater than or equal to that specified here. 4. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute minimum TCK period specification. 5. This value is TDO propagation time 36 ns + 4 ns setup time to sampling edge. 6. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. 7. This value is TDO propagation time 16 ns + 4 ns setup time to sampling edge. 8. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay. 64/115 DS11597 Rev 4 SPC582Bx Electrical characteristics Figure 16. Nexus output timing 1 2 MCKO 3 4 6 MDO MSEO EVTO Output Data Valid Figure 17. Nexus event trigger and test clock timings TCK EVTI EVTO 9 TCK EVTI EVTO 9 DS11597 Rev 4 7 7 8 8 65/115 80 Electrical characteristics SPC582Bx Figure 18. Nexus TDI, TMS, TDO timing TCK 11 13 12 14 TMS, TDI 15 16 TDO 4.15.1.3 External interrupt timing (IRQ pin) Table 36. External interrupt timing Characteristic Symbol Min Max Unit IRQ Pulse Width Low tIPWL 3 — tcyc IRQ Pulse Width High tIPWH 3 — tcyc tICYC 6 — tcyc IRQ Edge to Edge Time(1) 1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both. 66/115 DS11597 Rev 4 SPC582Bx Electrical characteristics Figure 19. External interrupt timing IRQ 2 1 3 Figure 20. External interrupt timing D_CLKOUT 4 IRQ 2 1 3 4.15.2 DSPI timing with CMOS pads DSPI channel frequency support is shown in Table 37. Timing specifications are shown in the tables below. DS11597 Rev 4 67/115 80 Electrical characteristics SPC582Bx Table 37. DSPI channel frequency support Max usable frequency (MHz)(2),(3) DSPI use mode(1) CMOS (Master mode) Full duplex – Classic timing (Table 38) DSPI_0, DSPI_1, DSPI_2, DSPI_3, 10 Full duplex – Modified timing (Table 39) DSPI_0, DSPI_1, DSPI_2, DSPI_3, 10 Output only mode (SCK/SOUT/PCS) (Table 38 and DSPI_0, DSPI_1, Table 39) DSPI_2, DSPI_3, 10 DSPI_0, DSPI_1, DSPI_2, DSPI_3, 10 Output only mode TSB mode (SCK/SOUT/PCS) CMOS (Slave mode Full duplex) (Table 40) — 10 1. Each DSPI module can be configured to use different pins for the interface. Refer to the device pinout Microsoft Excel file attached to the IO_Definition document for the available combinations. It is not possible to reach the maximum performance with every possible combination of pins. 2. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads. 3. Maximum usable frequency does not take into account external device propagation delay. 4.15.2.1 DSPI master mode full duplex timing with CMOS pads 4.15.2.1.1 DSPI CMOS master mode – classic timing Note: In the following table, all output timing is worst case and includes the mismatching of rise and fall times of the output pads. Table 38. DSPI CMOS master classic timing (full duplex and output only) MTFE = 0, CPHA = 0 or 1 Value(1) Condition # Symbol C Characteristic Unit Pad drive(2) Load (CL) Min Max SCK drive strength 1 tSCK CC D SCK cycle time Very strong 25 pF 59.0 — Strong 50 pF 80.0 — Medium 50 pF 200.0 — ns SCK and PCS drive strength 2 tCSC 68/115 PCS to SCK CC D delay Very strong 25 pF (N(3) × tSYS(4)) – 16 — Strong 50 pF (N(3) × tSYS(4)) – 16 — Medium 50 pF (N(3) × tSYS(4)) – 16 — PCS medium and SCK strong PCS = 50 pF SCK = 50 pF (N(3) × tSYS(4)) – 29 — DS11597 Rev 4 ns SPC582Bx Electrical characteristics Table 38. DSPI CMOS master classic timing (full duplex and output only) MTFE = 0, CPHA = 0 or 1 (continued) Value(1) Condition # Symbol C Characteristic Unit Pad drive(2) Load (CL) Min Max SCK and PCS drive strength 3 tASC Very strong PCS = 0 pF SCK = 50 pF (M(5) × tSYS(4)) – 35 — Strong PCS = 0 pF SCK = 50 pF (M(5) × tSYS(4)) – 35 — Medium PCS = 0 pF SCK = 50 pF (M(5) × tSYS(4)) – 35 — PCS medium and SCK strong PCS = 0 pF SCK = 50 pF (M(5) × tSYS(4)) – 35 — CC D After SCK delay ns SCK drive strength 4 tSDC CC D SCK duty cycle(6) Very strong Strong Medium 0 pF 1/ 0 pF 1/ 0 pF 1/ 2tSCK 2tSCK 2tSCK –2 1/ 2tSCK +2 –2 1/ 2tSCK +2 –5 1/ 2tSCK +5 ns PCS strobe timing 5 tPCSC CC D PCSx to PCSS time(7) PCS and PCSS drive strength 6 tPASC CC D PCSS to PCSx time(7) PCS and PCSS drive strength Strong 25 pF Strong 16.0 — ns 16.0 — ns 25 pF 25.0 — 50 pF 31.0 — 50 pF 52.0 — 25 pF SIN setup time SCK drive strength 7 tSUI CC D SIN setup time to Very strong SCK(8) Strong Medium ns SIN hold time SCK drive strength 8 tHI CC D SIN hold time from SCK(8) Very strong 0 pF –1.0 — Strong 0 pF –1.0 — Medium 0 pF –1.0 — 25 pF — 7.0 50 pF — 8.0 50 pF — 16.0 ns SOUT data valid time (after SCK edge) SOUT and SCK drive strength 9 tSUO CC D SOUT data valid Very strong time from SCK(9) Strong Medium DS11597 Rev 4 ns 69/115 80 Electrical characteristics SPC582Bx Table 38. DSPI CMOS master classic timing (full duplex and output only) MTFE = 0, CPHA = 0 or 1 (continued) Value(1) Condition # Symbol C Characteristic Pad drive(2) Unit Load (CL) Min Max 25 pF –7.7 — 50 pF –11.0 — 50 pF –15.0 — SOUT data hold time (after SCK edge) SOUT and SCK drive strength 10 tHO CC D SOUT data hold Very strong time after SCK(9) Strong Medium ns 1. All timing values for output signals in this table are measured to 50% of the output voltage. 2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation. 3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 4. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). 5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 6. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 7. PCSx and PCSS using same pad configuration. 8. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL voltage thresholds. 9. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. 70/115 DS11597 Rev 4 SPC582Bx Electrical characteristics Figure 21. DSPI CMOS master mode — classic timing, CPHA = 0 tCSC tASC PCSx tSCK tSDC SCK Output (CPOL = 0) SCK Output (CPOL = 1) tSDC tSUI tHI First Data SIN Data Last Data tSUO SOUT tHO Data First Data Last Data Figure 22. DSPI CMOS master mode — classic timing, CPHA = 1 3&6[ 6&.2XWSXW &32/  6&.2XWSXW &3 2/ = 1)  (CPOL W68, 6,1 W+, )LUVW'DWD 'DWD W682 6287 )LUVW'DWD DS11597 Rev 4 'DWD /DVW'DWD W+2 /DVW'DWD 71/115 80 Electrical characteristics SPC582Bx Figure 23. DSPI PCS strobe (PCSS) timing (master mode) tPCSC tPASC PCSS PCSx 4.15.2.1.2 DSPI CMOS master mode — modified timing Note: In the following table, all output timing is worst case and includes the mismatching of rise and fall times of the output pads. Table 39. DSPI CMOS master modified timing (full duplex and output only) MTFE = 1, CPHA = 0 or 1 Value(1) Condition # Symbol C Characteristic Pad drive(2) Unit Load (CL) Min Max SCK drive strength 1 tSCK CC D SCK cycle time Very strong 25 pF 33.0 — Strong 50 pF 80.0 — Medium 50 pF 200.0 — ns SCK and PCS drive strength 2 tCSC CC D PCS to SCK delay Very strong 25 pF (N(3) × tSYS(4)) – 16 — Strong 50 pF (N(3) × tSYS(4)) – 16 — Medium 50 pF PCS PCS = 50 pF medium and SCK = 50 pF SCK strong (3) (4) × tSYS ) – 16 — (N(3) × tSYS(4)) – 29 — (N ns SCK and PCS drive strength 3 tASC 72/115 CC D After SCK delay Very strong PCS = 0 pF SCK = 50 pF (M(5) × tSYS(4)) – 35 — Strong PCS = 0 pF SCK = 50 pF (M(5) × tSYS(4)) – 35 — Medium PCS = 0 pF SCK = 50 pF (M(5) × tSYS(4)) – 35 — PCS PCS = 0 pF medium and SCK = 50 pF SCK strong (M(5) × tSYS(4)) – 35 — DS11597 Rev 4 ns SPC582Bx Electrical characteristics Table 39. DSPI CMOS master modified timing (full duplex and output only) MTFE = 1, CPHA = 0 or 1 (continued) Value(1) Condition # Symbol C Characteristic Pad drive(2) Unit Load (CL) Min Max SCK drive strength 4 tSDC CC D SCK duty cycle(6) Very strong Strong Medium 0 pF 1 1 /2tSCK + 2 0 pF 1 1 /2tSCK + 2 0 pF 1 1 /2tSCK + 5 /2tSCK – 2 /2tSCK – 2 /2tSCK – 5 ns PCS strobe timing 5 6 tPCSC CC D PCSx to PCSS time(7) PCSS to PCSx tPASC CC D time(7) PCS and PCSS drive strength Strong 25 pF 16.0 — ns 16.0 — ns PCS and PCSS drive strength Strong 25 pF SIN setup time SCK drive strength SIN setup time to Very strong SCK Strong CPHA = 0(8) 7 tSUI Medium CC D 25 pF 50 pF 50 pF 25 – (P(9) × tSYS(4)) — × tSYS(4)) — × tSYS(4)) — (9) 31 – (P 52 – (P(9) ns SCK drive strength SIN setup time to Very strong SCK Strong CPHA = 1(8) Medium 25 pF 25.0 — 50 pF 31.0 — 50 pF 52.0 — ns SIN hold time SCK drive strength SIN hold time from SCK CPHA = 0(8) 8 tHI CC D Very strong 0 pF –1 + (P(9) × tSYS(3)) — tSYS(3)) — (9) × Strong 0 pF –1 + (P Medium 0 pF –1 + (P(9) × tSYS(3)) — ns SCK drive strength SIN hold time from SCK CPHA = 1(8) Very strong 0 pF –1.0 — Strong 0 pF –1.0 — Medium 0 pF –1.0 — DS11597 Rev 4 ns 73/115 80 Electrical characteristics SPC582Bx Table 39. DSPI CMOS master modified timing (full duplex and output only) MTFE = 1, CPHA = 0 or 1 (continued) Value(1) Condition # Symbol C Characteristic Pad drive(2) Unit Load (CL) Min Max SOUT data valid time (after SCK edge) SOUT data valid time from SCK CPHA = 0, (10) 9 tSUO SOUT and SCK drive strength Very strong 25 pF — 7.0 + tSYS(4) Strong 50 pF — 8.0 + tSYS(4) — tSYS(4) Medium CC D SOUT data valid time from SCK CPHA = 1(10) 50 pF 16.0 + ns SOUT and SCK drive strength Very strong 25 pF — 7.0 Strong 50 pF — 8.0 Medium 50 pF — 16.0 25 pF –7.7 + tSYS(4) — 50 pF –11.0 + tSYS(4) — –15.0 + tSYS(4) — ns SOUT data hold time (after SCK edge) SOUT data hold time after SCK CPHA = 0(10) 10 tHO SOUT and SCK drive strength Very strong Strong Medium CC D SOUT data hold time after SCK CPHA = 1(10) 50 pF ns SOUT and SCK drive strength Very strong 25 pF –7.7 — Strong 50 pF –11.0 — Medium 50 pF –15.0 — ns 1. All timing values for output signals in this table are measured to 50% of the output voltage. 2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation. 3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 4. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). 5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 6. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 7. PCSx and PCSS using same pad configuration. 8. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL voltage thresholds. 9. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_ MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1. 74/115 DS11597 Rev 4 SPC582Bx Electrical characteristics 10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. Figure 24. DSPI CMOS master mode — modified timing, CPHA = 0 tCSC tASC PCSx tSCK tSDC SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN tSDC tSUI tHI First Data Data Last Data tSUO SOUT tHO Data First Data Last Data Figure 25. DSPI CMOS master mode — modified timing, CPHA = 1 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) tSUI SIN tHI tHI Data First Data tSUO SOUT First Data DS11597 Rev 4 Data Last Data tHO Last Data 75/115 80 Electrical characteristics SPC582Bx Figure 26. DSPI PCS strobe (PCSS) timing (master mode) tPCSC tPASC PCSS PCSx 4.15.2.2 Slave mode timing Table 40. DSPI CMOS slave timing — full duplex — normal and modified transfer formats (MTFE = 0/1) Condition # 1 Symbol tSCK CC C D Characteristic SCK Cycle Time(1) Pad Drive Load Min Max Unit — — 62 — ns Delay(1) — — 16 — ns 2 tCSC SR D SS to SCK 3 tASC SR D SCK to SS Delay(1) — — 16 — ns 4 tSDC CC D SCK Duty Cycle(1) — — 30 — ns Very strong 25 pF — 50 ns Strong 50 pF — 50 ns Medium 50 pF — 60 ns Slave SOUT Disable Time(1) Very strong 25 pF — 5 ns (SS inactive to SOUT HighZ or invalid) Strong 50 pF — 5 ns Medium 50 pF — 10 ns 5 6 tA tDIS CC CC D D (1) (2) (3) Slave Access Time (SS active to SOUT driven) (2) (3) 9 tSUI CC D Data Setup Time for Inputs(1) — — 10 — ns 10 tHI CC D Data Hold Time for Inputs(1) — — 10 — ns Very strong 25 pF — 30 ns Strong 50 pF — 30 ns Medium 50 pF — 50 ns Very strong 25 pF 2.5 — ns Strong 50 pF 2.5 — ns Medium 50 pF 2.5 — ns 11 12 tSUO tHO CC CC D D SOUT Valid Time(1) (2) (3) (after SCK edge) (1) (2) (3) SOUT Hold Time (after SCK edge) 1. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL voltage thresholds. 2. All timing values for output signals in this table, are measured to 50% of the output voltage. 3. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. 76/115 DS11597 Rev 4 SPC582Bx Electrical characteristics Figure 27. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 0 tASC tCSC SS tSCK SCK Input (CPOL = 0) tSDC tSDC SCK Input (CPOL = 1) tSUO tA First Data SOUT Data tDIS Last Data tSUI tHI Data First Data SIN tHO Last Data Figure 28. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 1 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) tSUO tA SOUT tHO First Data tSUI SIN 4.15.3 Data Last Data Data Last Data tDIS tHI First Data CAN timing The following table describes the CAN timing. DS11597 Rev 4 77/115 80 Electrical characteristics SPC582Bx Table 41. CAN timing Value Symbol tP(RX:TX) tPLP(RX:TX) 4.15.4 C CC D CC D CC D CC D CC D CC D CC D CC D Parameter Condition CAN controller propagation delay time standard pads CAN controller propagation delay time low power pads Unit Min Typ Max Medium type pads 25pF load — — 70 Medium type pads 50pF load — — 80 STRONG, VERY STRONG type pads 25pF load — — 60 STRONG, VERY STRONG type pads 50pF load — — 65 Medium type pads 25pF load — — 90 Medium type pads 50pF load — — 100 STRONG, VERY STRONG type pads 25pF load — — 80 STRONG, VERY STRONG type pads 50pF load — — 85 ns ns UART timing UART channel frequency support is shown in the following table. Table 42. UART frequency support LINFlexD clock frequency LIN_CLK (MHz) Oversampling rate 16 8 80 6 5 4 16 8 100 6 5 4 4.15.5 Voting scheme Max usable frequency (Mbaud) 3:1 majority voting Limited voting on one sample with configurable sampling point 3:1 majority voting Limited voting on one sample with configurable sampling point 5 10 13.33 16 20 6.25 12.5 16.67 20 25 I2C timing The I2C AC timing specifications are provided in the following tables. Note: 78/115 In the following table, I2C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower than 1 ns (10% – 90%). DS11597 Rev 4 SPC582Bx Electrical characteristics Table 43. I2C input timing specifications – SCL and SDA Value No. Symbol C Parameter Unit Min Max 1 — CC D Start condition hold time 2 — PER_CLK Cycle(1) 2 — CC D Clock low time 8 — PER_CLK Cycle 3 — CC D Bus free time between Start and Stop condition 4.7 — µs 4 — CC D Data hold time 0.0 — ns 5 — CC D Clock high time 4 — PER_CLK Cycle 6 — CC D Data setup time 0.0 — ns 7 — CC D Start condition setup time (for repeated start condition only) 2 — PER_CLK Cycle 8 — CC D Stop condition setup time 2 — PER_CLK Cycle 2 1. PER_CLK is the SoC peripheral clock, which drives the I C BIU and module clock inputs. See the Clocking chapter in the device reference manual for more detail. Note: In the following table: • All output timing is worst case and includes the mismatching of rise and fall times of the output pads. • Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value. • Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation. • Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD register. Table 44. I2C output timing specifications — SCL and SDA Value No. Symbol C Parameter Unit Min Max 1 — CC D Start condition hold time 6 — PER_CLK Cycle(1) 2 — CC D Clock low time 10 — PER_CLK Cycle 3 — CC D Bus free time between Start and Stop condition 4.7 — µs 4 — CC D Data hold time 7 — PER_CLK Cycle 5 — CC D Clock high time 10 — PER_CLK Cycle 6 — CC D Data setup time 2 — PER_CLK Cycle 7 — CC D Start condition setup time (for repeated start condition only) 20 — PER_CLK Cycle 8 — CC D Stop condition setup time 10 — PER_CLK Cycle DS11597 Rev 4 79/115 80 Electrical characteristics SPC582Bx 1. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the device reference manual for more detail. Figure 29. I2C input/output timing 2 5 SCL 1 4 7 SDA 80/115 8 6 DS11597 Rev 4 3 SPC582Bx 5 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. The following table lists the case numbers for SPC582Bx. Table 45. Package case numbers Package type Device type eTQFP64 Production eTQFP100 Production eTQFP144(1) Emulation QFN48 Production 1. eTQFP144 package is for emulation purpose only and not suitable for production. This package is not AEC-Q100 qualified. 5.1 eTQFP64 package information Refer to Section 5.1.1: Package mechanical drawings and data information for full description of below figures and table notes. DS11597 Rev 4 81/115 99 Package information SPC582Bx Figure 30. eTQFP64 package outline life.augmented 82/115 DS11597 Rev 4 SPC582Bx Package information Figure 31. eTQFP64 section A-A ș ș ș ș Figure 32. eTQFP64 section B-B DS11597 Rev 4 83/115 99 Package information SPC582Bx Table 46. eTQFP64 package mechanical data Dimensions(7),(17) Symbol Min. Typ. Max. Ө 0° 3.5° 7° Ө1 0° — — Ө2 10° 12° 14° Ө3 10° 12° 14° (15) — — 1.20 (12) A1 0.05 — 0.15 A2(15) 0.95 1.00 1.05 0.17 0.22 0.27 A (8),(9),(11) b (11) 0.17 0.20 0.23 c(11) 0.09 — 0.20 c1(11) 0.09 — 0.16 b1 D(4) D1 12 BSC (2),(5) D2 (13) D3(14) 10 BSC — — 4.65 2.90 — — e 0.50 BSC (4) 12 BSC E E1(2),(5) E2(13) — — 4.65 (14) 2.90 — — L 0.45 0.60 0.75 E3 L1 1 REF N(16) 64 R1 0.08 — — R2 0.08 — 0.20 S 0.20 — — aaa(1),(18) 0.20 (1),(18) 0.20 (1),(18) ccc 0.08 ddd(1),(18) 0.08 bbb 84/115 10 BSC DS11597 Rev 4 SPC582Bx 5.1.1 Package information Package mechanical drawings and data information The following notes are related to Figure 30, Figure 31, Figure 32 and Table 46: 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Datums A-B and D to be determined at datum plane H. 4. To be determined at seating datum plane C. 5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. 7. All dimensions are in millimeter except where explicitly noted. 8. No intrusion allowed inwards the leads. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 10. Exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from exposed pad itself. Type of exposed pad on SPC582Bx is as Figure 33. End user should verify D2 and E2 dimensions according to the specific device application. 14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove. 15. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface. 16. “N” is the max number of terminal positions for the specified body size. 17. Critical dimensions: a) Stand-Off b) Overall Width c) Lead Coplanarity 18. For symbols, recommended values and tolerances, see Table 47. 19. Notch may be present in this area (MAX 1.5mm square) if center top gate molding technology is applied. Resin gate residual not protruding out of package top surface. DS11597 Rev 4 85/115 99 Package information SPC582Bx Figure 33. eTQFP64 leadframe pad design Note: number, Table 47. eTQFP64 symbol definitions 5.2 Symbol Definition Notes aaa The tolerance that controls the position of the terminal pattern with respect to Datum A and B. The center of the tolerance zone for each terminal is defined by basic dimension e as related to Datum A and B. For flange-molded packages, this tolerance also applies for basic dimensions D1 and E1. For packages tooled with intentional terminal tip protrusions, aaa does not apply to those protrusions. bbb The bilateral profile tolerance that controls the position of the plastic body sides. The centers of the profile zones are defined by the basic dimensions D and E. ccc The unilateral tolerance located above the This tolerance is commonly know as the seating plane where in the bottom surface of “coplanarity” of the package terminals. all terminals must be located. ddd The tolerance that controls the position of the terminals to each other. The centers of the profile zones are defined by basic dimension e. — This tolerance is normally compounded with tolerance zone defined by “b”. eTQFP100 package information Refer to Section 5.2.1: Package mechanical drawings and data information for full description of below figures and table notes. 86/115 DS11597 Rev 4 SPC582Bx Package information Figure 34. eTQFP100 package outline OLIHDXJPHQWHG DS11597 Rev 4 87/115 99 Package information SPC582Bx Figure 35. eTQFP100 section A-A ș ș ș ș Figure 36. eTQFP100 section B-B 88/115 DS11597 Rev 4 SPC582Bx Package information Table 48. eTQFP100 package mechanical data Dimensions(7),(17) Symbol Min. Typ. Max. θ 0ο 3.5ο 7ο θ1 0ο — — θ2 10ο 12ο 14ο θ3 10ο 12ο 14ο A(15) — — 1.20 (12) A1 0.05 — 0.15 A2(15) 0.95 1.00 1.05 0.17 0.22 0.27 (8),(9),(11) b (11) 0.17 0.20 0.23 c(11) 0.09 — 0.20 c1(11) 0.09 — 0.16 b1 D(4) 16.00 BSC (2),(5) 14.00 BSC D1 D2 (13) D3(14) — — 5.35 3.60 — — e 0.50 BSC (4) 16.00 BSC E E1(2),(5) E2(13) 14.00 BSC — — 5.35 (14) 3.60 — — L 0.45 0.60 0.75 E3 L1 1.00 REF N(16) 100 R1 0.08 — — R2 0.08 — 0.20 S 0.20 — — aaa(1),(18) 0.20 (1),(18) 0.20 (1),(18) ccc 0.08 ddd(1),(18) 0.08 bbb DS11597 Rev 4 89/115 99 Package information 5.2.1 SPC582Bx Package mechanical drawings and data information The following notes are related to Figure 34, Figure 35, Figure 36 and Table 48: 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Datums A-B and D to be determined at datum plane H. 4. To be determined at seating datum plane C. 5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. 7. All dimensions are in millimeter except where explicitly noted. 8. No intrusion allowed inwards the leads. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 10. Exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from exposed pad itself. Type of exposed pad on SPC582Bx is as Figure 37. End user should verify D2 and E2 dimensions according to the specific device application. 14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove. 15. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface. 16. “N” is the max number of terminal positions for the specified body size. 17. Critical dimensions: a) Stand-Off b) Overall Width c) Lead Coplanarity 18. For symbols, recommended values and tolerances, see Table 49. 90/115 DS11597 Rev 4 SPC582Bx Package information Figure 37. eTQFP100 leadframe pad design Note: number, dimensions and positions of grooves are for reference only. Table 49. eTQFP100 symbol definitions Symbol Definition Notes aaa The tolerance that controls the position of the terminal pattern with respect to Datum A and B. The center of the tolerance zone for each terminal is defined by basic dimension e as related to Datum A and B. For flange-molded packages, this tolerance also applies for basic dimensions D1 and E1. For packages tooled with intentional terminal tip protrusions, aaa does not apply to those protrusions. bbb The bilateral profile tolerance that controls the position of the plastic body sides. The centers of the profile zones are defined by the basic dimensions D and E. — ccc The unilateral tolerance located above the seating plane where in the bottom surface of all terminals must be located. This tolerance is commonly know as the “coplanarity” of the package terminals. ddd The tolerance that controls the position of the terminals to each other. The centers of the profile zones are defined by basic dimension e. This tolerance is normally compounded with tolerance zone defined by “b”. 5.3 eTQFP144 package information Refer to Section 5.3.1: Package mechanical drawings and data information for full description of below figures and table notes. DS11597 Rev 4 91/115 99 Package information SPC582Bx Figure 38. eTQFP144 package outline OLIHDXJPHQWHG 92/115 DS11597 Rev 4 SPC582Bx Package information Figure 39. eTQFP144 section A-A ș ș ș ș Figure 40. eTQFP144 section B-B DS11597 Rev 4 93/115 99 Package information SPC582Bx Table 50. eTQFP144 package mechanical data Dimensions(7),(17) Symbol Min. Typ. Max. θ 0.0° 3.5° 7.0° θ1 0.0° — — θ2 10.0° 12.0° 14.0° θ3 10.0° 12.0° 14.0° (15) — — 1.20 (12) A1 0.05 — 0.15 A2(15) 0.95 1.00 1.05 0.17 0.22 0.27 A (8),(9),(11) b (11) 0.17 0.20 0.23 c(11) 0.09 — 0.20 c1(11) 0.09 — 0.16 D(4) b1 — 22.00 BSC — (2),(5) — 20.00 BSC — (13) — — 6.77 5.10 — — — 22.00 BSC — D1 D2 D3(14) (4) E (2),(5) — 20.00 BSC — E2(13) — — 6.77 E3(14) 5.10 — — E1 e 0.50 BSC L 0.45 0.60 0.75 L1 — 1.00 REF — N(16) R1 0.08 — — R2 0.08 — 0.20 S 0.20 — — aaa(1),(18) 0.20 (1),(18) 0.20 (1),(18) ccc 0.08 ddd(1),(18) 0.08 bbb 94/115 144 DS11597 Rev 4 SPC582Bx 5.3.1 Package information Package mechanical drawings and data information The following notes are related to Figure 38, Figure 39, Figure 40 and Table 50: 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Datums A-B and D to be determined at datum plane H. 4. To be determined at seating datum plane C. 5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. 7. All dimensions are in millimeter except where explicitly noted. 8. No intrusion allowed inwards the leads. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 10. Exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from exposed pad itself. Type of exposed pad on SPC582Bx is as Figure 41. End user should verify D2 and E2 dimensions according to the specific device application. 14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove. 15. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface. 16. “N” is the max number of terminal positions for the specified body size. 17. Critical dimensions: a) Stand-Off b) Overall Width c) Lead Coplanarity 18. For symbols, recommended values and tolerances, see Table 51. DS11597 Rev 4 95/115 99 Package information SPC582Bx Figure 41. eTQFP144 leadframe pad design Note: number, dimensions and positions of grooves are for reference only. Table 51. eTQFP144 symbol definitions Symbol Definition Notes aaa The tolerance that controls the position of the terminal pattern with respect to Datum A and B. The center of the tolerance zone for each terminal is defined by basic dimension e as related to Datum A and B. For flange-molded packages, this tolerance also applies for basic dimensions D1 and E1. For packages tooled with intentional terminal tip protrusions, aaa does not apply to those protrusions. bbb The bilateral profile tolerance that controls the position of the plastic body sides. The centers of the profile zones are defined by the basic dimensions D and E. — ccc The unilateral tolerance located above the seating plane where in the bottom surface of all terminals must be located. This tolerance is commonly know as the “coplanarity” of the package terminals. ddd The tolerance that controls the position of the terminals to each other. The centers of the profile zones are defined by basic dimension e. This tolerance is normally compounded with tolerance zone defined by “b”. 5.4 QFN48 package information Refer to Section 5.4.1: Package mechanical drawings and data information for full description of below figures and table notes. 96/115 DS11597 Rev 4 SPC582Bx Package information Figure 42. QFN48 package outline DS11597 Rev 4 97/115 99 Package information SPC582Bx Table 52. QFN48 package mechanical data Dimensions Symbol A(4) (11) A1 Min. Typ. Max. 0.80 0.90 1.00 0.00 0.02 0.05 A2 0.2 REF (11) 0.10 — — (4),(9) 0.20 0.25 0.30 (4) — 7.00 — D2 4.70 4.80 4.90 e(4) — 0.5 — (4) — 7.00 — E2 4.70 4.80 4.90 L(4) 0.45 0.50 0.55 L1(4) 0.35 — — A3 b D E N (4) k 48 0.25 aaa(1),(4) 0.15 (1),(4) 0.10 (1),(4) 0.08 ddd(1),(4) 0.05 eee(1),(4) 0.10 bbb ccc 5.4.1 — Package mechanical drawings and data information The following notes are related to Figure 42 and Table 52: 98/115 DS11597 Rev 4 — SPC582Bx Package information 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. The Top package body size may be smaller than the bottom package size by much as 0.15 mm. 3. Datum A-B and D to be determined at datum plane H. 4. To be determined at setting datum plane C. 5. Detail of pin 1 identifier are optional but must be located within the zone indicated. 6. All Dimensions are in millimeters. 7. No intrusion allowed inwards the leads. 8. Exact shape of each corner is optional. 9. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 10. A1 is defined as the distance from the seating plane to the lowest point on the package body. 11. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface. 12. “N” is the max number of terminal positions for the specified body size. 13. For Tolerance of Form and Position see Table. 14. Critical dimensions: a) A b) A1 c) A3 d) D&E e) b&L f) D2 & E2 15. For Symbols, recommended values and tolerances see table below: (ACCORDING TO PACKAGE OR JEDEC SPEC IF REGISTERED) Table 53. QFN48 symbol definitions Symbol Definition Notes aaa The tolerance that controls the position of the terminal pattern with respect to Datum A and B. The center of the tolerance zone for each terminal is defined by basic dimension e as related to Datum A and B. For flange-molded packages, this tolerance also applies for basic dimensions D1 and E1. For packages tooled with intentional terminal tip protrusions, aaa does not apply to those protrusions. bbb The bilateral profile tolerance that controls the position of the plastic body sides. The centers of the profile zones are defined by the basic dimensions D and E. — ccc The unilateral tolerance located above the seating plane where in the bottom surface of all terminals must be located. This tolerance is commonly known as the “coplanarity” of the package terminals. ddd The tolerance that controls the position of the terminals to each other. The centers of the profile zones are defined by basic dimension e. This tolerance is normally compounded with tolerance zone defined by “b”. DS11597 Rev 4 99/115 99 Package information 5.5 SPC582Bx Package thermal characteristics The following tables describe the thermal characteristics of the device. The parameters in this chapter have been evaluated by considering the device consumption configuration reported in the Section 4.7: Device consumption. 5.5.1 eTQFP64 Table 54. Thermal characteristics for 64 exposed pad eTQFP package Symbol RθJA C CC D Junction-to-Ambient, Natural Convection(2) RθJB CC D RθJCtop CC D RθJCbottom ΨJT CC CC Parameter(1) D D Junction-to-board (3) Junction-to-case top(4) Junction-to-case bottom(5) Junction-to-package top(6) Conditions Value Unit Four layer board (2s2p) 43.9 °C/W — 23.8 °C/W — 28.9 °C/W — 12.8 °C/W Natural convection 11.5 °C/W 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation without any interface resistance. 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 5.5.2 eTQFP100 Table 55. Thermal characteristics for 100 exposed pad eTQFP package Symbol C Parameter(1) RθJA CC D Junction-to-Ambient, Natural Convection RθJB CC D RθJCtop RθJCbottom ΨJT CC CC CC D D D (2) Junction-to-board(3) Junction-to-case top (4) (5) Junction-to-case bottom Junction-to-package top(6) Conditions Value Unit Four layer board (2s2p) 43.3 °C/W — 26.1 °C/W — 27 °C/W — 12.6 °C/W Natural convection 11.4 °C/W 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation without any interface resistance. 100/115 DS11597 Rev 4 SPC582Bx Package information 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 5.5.3 QFN48 Table 56. Thermal characteristics for QFN48 package Symbol Parameter(1) C RθJA CC D Junction-to-Ambient, Natural Convection RθJB CC D RθJCtop RθJCbottom ΨJT CC CC CC D D D (3) Conditions Value(2) Unit Four layer board (2s2p) 43.9 °C/W — 28.8 °C/W — 28.9 °C/W — 22.5 °C/W Natural convection 11.5 °C/W Junction-to-board(4) Junction-to-case top (5) Junction-to-case bottom Junction-to-package (6) top(7) 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. These values are preliminary, therefore they are subject to change. 3. Per JEDEC JESD51 with the board (JESD51-7) horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the top case surface in ideal contact and measured by cold plate as per JEDEC best practice guidelines (JESD51-12). 6. Thermal resistance between the die and the bottom case surface in ideal contact and measured by cold plate as per JEDEC best practice guidelines (JESD51-12). 7. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 5.5.4 General notes for specifications at maximum junction temperature An estimation of the chip junction temperature, TJ, can be obtained from the equation: Equation 1 TJ = TA + (RθJA * PD) where: TA = ambient temperature for the package (°C) RθJA = junction-to-ambient thermal resistance (°C/W) PD = power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The differences between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the: • Construction of the application board (number of planes) • Effective size of the board which cools the component • Quality of the thermal and electrical connections to the planes • Power dissipated by adjacent components DS11597 Rev 4 101/115 103 Package information SPC582Bx Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leaves the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has: • One oz. (35 micron nominal thickness) internal planes • Components are well separated • Overall power dissipation on the board is less than 0.02 W/cm2 The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: Equation 2 TJ = TB + (RθJB * PD) where: TB = board temperature for the package perimeter (°C) RθJB = junction-to-board thermal resistance (°C/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, the junction temperature is predictable if the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: Equation 3 RθJA = RθJC + RθCA where: RθJA = junction-to-ambient thermal resistance (°C/W) RθJC = junction-to-case thermal resistance (°C/W) RθCA = case to ambient thermal resistance (°C/W) RθJC is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RθCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required. 102/115 DS11597 Rev 4 SPC582Bx Package information A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. More accurate compact Flotherm models can be generated upon request. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (ΨJT) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: Equation 4 TJ = TT + (ΨJT x PD) where: TT = thermocouple temperature on top of the package (°C) ΨJT = thermal characterization parameter (°C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. When board temperature is perfectly defined below the device, it is possible to use the thermal characterization parameter (ΨJPB) to determine the junction temperature by measuring the temperature at the bottom center of the package case (exposed pad) using the following equation: Equation 5 TJ = TB + (ΨJPB x PD) where: TT = thermocouple temperature on bottom of the package (°C) ΨJT = thermal characterization parameter (°C/W) PD = power dissipation in the package (W) DS11597 Rev 4 103/115 103 Ordering information 6 SPC582Bx Ordering information Figure 43. Ordering information scheme Example code: SPC58 2 B 60 E3 M H X 1 Product identifier Core Product Memory Package Frequency Custom Reserved Silicon version revision X Packing Y = Tray X = Tape and Reel (pin 1 top right) 0 = 1st version 1 = 2nd version 0 = 3x standard CAN D = 3x ISO CAN FD G = 7x standard CAN H = 7x ISO CAN FD A = 48 MHz at 105 oC B = 64 MHz at 105 oC C = 80 MHz at 105 oC K = 48 MHz at 125 oC L = 64 MHz at 125 oC M = 80 MHz at 125 oC E3 = eTQFP100 E1 = eTQFP64 Q3 = QFN48 60 = 1 MB 54 = 768 KB 50 = 512 KB B = SPC582Bx family 2 = Single computing e200z2 core SPC58 = Power Architecture in 40 nm Note: eTQFP144 package (SPC582B60E5-ENG) is available for emulation purpose only (with NEXUS port I/O). Note: For the number of CAN Interfaces available by package, refer to the IO_Definition file. Note: Please contact your ST sales office to ask for the availability of a particular commercial product. Features (for instance, flash, RAM or peripherals) not included in the commercial product cannot be used. ST cannot be called to take any liability for features used outside the commercial product. 104/115 DS11597 Rev 4 SPC582Bx Ordering information Table 57. Code Flash options SPC582B60 (1M) SPC582B54 (768K) SPC582B50 (512K) Partition Start address End address 16 16 16 0 0x00FC0000 0x00FC3FFF 16 16 16 0 0x00FC4000 0x00FC7FFF 16 16 16 0 0x00FC8000 0x00FCBFFF 16 16 16 0 0x00FCC000 0x00FCFFFF 32 32 32 0 0x00FD0000 0x00FD7FFF 32 32 32 0 0x00FD8000 0x00FDFFFF 64 64 64 0 0x00FE0000 0x00FEFFFF 64 64 64 0 0x00FF0000 0x00FFFFFF 128 128 128 0 0x01000000 0x0101FFFF 128 128 128 0 0x01020000 0x0103FFFF 128 128 NA 0 0x01040000 0x0105FFFF 128 128 NA 0 0x01060000 0x0107FFFF 128 NA NA 0 0x01080000 0x0109FFFF 128 NA NA 0 0x010A0000 0x010BFFFF Type Start address End address Table 58. RAM options SPC582B60 SPC582B54 SPC582B50 96(1) 80(1) 64(1) 8 8 8 PRAMC_2 (STBY) 0x400A8000 0x400A9FFF 24 24 24 PRAMC_2 (STBY) 0x400AA000 0x400AFFFF 32 32 32 PRAMC_2 (STBY) 0x400B0000 0x400B7FFF 16 16 NA PRAMC_2 0x400B8000 0x400BBFFF 16 NA NA PRAMC_2 0x400BC000 0x400BFFFF 1. Total KRAM (SRAM). DS11597 Rev 4 105/115 105 Revision history 7 SPC582Bx Revision history Table 59. Document revision history Date Revision 07-April-2016 1 Changes Initial version. The following are the changes in this version of the Datasheet. 29-Jun-2017 106/115 2 – Removed QFN32 package from the document. – Replaced RPNs SPC582B60E1, SPC582B60E3, and SPC582B60Q2 with “SPC582B60x, SPC582B54x, and SPC582B50x” Table 1: Device summary: – Updated the table. Section 3.1: Introduction: – Removed text “The IPs and...for the details”. – Removed the two notes. Table 3: Parameter classifications: – Updated the description of classification tag “T”. Table 4: Absolute maximum ratings: – For parameter “IINJ”, text “DC” removed from description. – Added text “Exposure to absolute ... reliability” – Added text “even momentarily” – Updated values in conditions column. – Added parameter TTRIN. – For parameter “TSTG”, maximum value updated from “175” to “125” – Added new parameter “TPAS” – For parameter “IINJ”, description updated from “maximum...PAD” to “maximum DC...pad” Table 5: Operating Conditions: – Footnote “1.260 V - 1.290 V range .. temperature profile” updated to Text “... average supply value below or equal to 1.236 V ...” – For parameter “IINJ1” description, text “DC” removed. – For parameter “VDD_LV”, changed the classification from “D” to “P” – Removed note “Core voltage as ....” – Added parameter IINJ2. – Removed parameter “VRAMP_LV”. – Updated the table footnote “Positive and negative Dynamic current....” Table 6: Device supply relation during power-up/power-down sequence: – “VDD_HV_PMC” updated to “VDD_HV_OSC”. – Parameter “VDD_LV” removed Section 3.4: Electromagnetic emission characteristics: – Updated this section. DS11597 Rev 4 SPC582Bx Revision history Table 59. Document revision history (continued) Date 29-Jun-2017 Revision Changes 2 (cont’) Table 8: Device consumption: – Updated the table and its values. Section 3.8.2: I/O output DC characteristics: – “WEAK” to “WEAK/SLOW” – “STRONG” to “STRONG/FAST” – “VERY STRONG” to “VERY STRONG / VERY FAST” – Added note “10%/90% is the....” Table 14: I/O input electrical characteristics: – Parameter “ILKG” (Medium Pads (P), TJ=150°C/360 mA) removed. Table 11: I/O pull-up/pull-down electrical characteristics: – Added note “When the device enters into standby mode... an ADC function.” Table 12: WEAK/SLOW I/O output characteristics: – Added “10%-90% in description of parameter “tTR_W”. – For parameter “Fmax_W”, updated condition “25 pF load” to “CL=25pF” – For parameter “tTR_S”, changed min value (25 pF load) from “4” to “3” – Changed min value (50 pF load) from “6” to “5” – For parameter “|tSKEW_W|”, changed max value from “30” to “25”. Table 13: MEDIUM I/O output characteristics: – Added “10%-90% in description of parameter “tTR_M”. – For parameter “|tSKEW_W|”, changed max value from “30” to “25”. Table 14: STRONG/FAST I/O output characteristics: – Added “10%-90% in description of parameter “tTR_S”. – Parameter “IDCMAX_S” updated: – Condition added “VDD=5V+10% – Condition added “VDD=3.3V+10%, Max value updated to 5.5mA – For parameter “|tSKEW_W|”, changed max value from “30” to “25”. Table 16: I/O consumption: – Updated all the max values of parameters IDYN_W and IDYN_M Section 3.8.3: I/O pad current specifications: – Replaced all occurences of “50 pF load” with “CL=50pF”. – Removed note “The external ballast....” Table 19: PLL0 electrical characteristics: – For parameter “IPLL0”, classification changed from “C” to “T”. – Footnote “Jitter values...measurement” added for parameters: – |ΔPLL0PHI0SPJ| – |ΔPLL0PHI1SPJ| – ΔPLL0LTJ Table 20: PLL1 electrical characteristics: – For parameter “IPLL1”, classification changed from “C” to “T”. – Footnote “Jitter values...measurement” added for parameter “|ΔPLL1PHI0SPJ|” – Removed figure “Test circuit” DS11597 Rev 4 107/115 114 Revision history SPC582Bx Table 59. Document revision history (continued) Date 29-Jun-2017 108/115 Revision Changes 2 (cont’) Table 21: External 40 MHz oscillator electrical specifications: – Footnote “Ixatl is the oscillator...Test circuit is shown in Figure 8” modified to “Ixatl is the oscillator...startup of the oscillator”. – Minimum value of parameter “VIHEXT” updated from “VREF+0.6” to “VREF+0.75” – Maximum value of parameter “VILEXT” updated from “VREF-0.6” to “VREF0.75” – Parameter “gm”, value “D” updated to “P” for “fXTAL < 8 MHz”, and “D” for others. – Footnote “This parameter is...100% tested” updated to “Applies to an...to crystal mode”. Also added to parameter “VI – For parameters “VIHEXT” and “VILEXT”, Condition “–” updated to “VREF = 0.29 * VDD_HV_OSC” – Classification for parameters “CS_EXTAL” and “CS_EXTAL” changed from “T” to “D”. – Updated classification, conditions, min and max values for parameter “gm”. – Min and Max value of parameters CS_EXTAL and CS_XTAL updated to “3” (min) and “7” (max). Renamed the section “RC oscillator 1024 kHz” to Section 3.11.3: Low power RC oscillator Table 22: Internal RC oscillator electrical specifications: – For parameter “IFIRC”, replaced max value of 300 with 600. – Added footnote to the description. – For parameter IFIRC, changed the max value to 600 and added footnote. – Min, Typ and Max value of ”δfvar_SW” updated from “-1”, “-”, “1” to “-0.5”, “+0.3” and “0.5” respectively. Table 23: 1024 kHz internal RC oscillator electrical characteristics: – For parameter “δfvar_V”, minimum and maximum value updated from “-0.05” and “+0.05” to “-5” and “+5”. – For parameter “δfvar_T”, and “δfvar_V “ changed the cassification to “P”. Table 24: ADC pin specification: – For ILKG, changed condition “C” to “—”. – For parameter CP2, updated the max value to “1”. Table 25: SARn ADC electrical specification: – Classification for parameter “IADCREFH” changed from “C” to “T”. – For parameter fADCK (High frequency mode), changed min value from “7.5” to “> 13.33”. – Deleted footnote “Values are subject to change (possibly improved to ±2 LSB) after characterization” Table 28: Linear regulator specifications: – Updated the min and typ values of parameter VMREG (After trimming, maximum load). DS11597 Rev 4 SPC582Bx Revision history Table 59. Document revision history (continued) Date 29-Jun-2017 Revision Changes 2 (cont’) Table 29: Standby regulator specifications: – Updated the min and max values for parameter VSBY. – For parameter IDDSBY, added “0.984” to typ column. Table 30: Voltage monitor electrical characteristics: – Updated the Typ value of parameter VPOR200_C – Updated the min, typ, and max values of parameter VLVD100_SB,. – Updated the min and max values for parameter VMVD270_SBY. – Removed “PowerOn Reset LV” Updated Section 3.14: Flash Updated Figure 8: Input equivalent circuit (Fast SARn and SARB channels) Updated Figure 22: DSPI CMOS master mode — classic timing, CPHA = 1 Table 35: Nexus debug port timing: – Classification of parameters “tEVTIPW” and “tEVTOPW” changed from “P” to “D”. Table 38: DSPI CMOS master classic timing (full duplex and output only) — MTFE = 0, CPHA = 0 or 1: – Changed the Min value of tSCK (very strong) from 33 to 59. Added Section 3.15.3: CAN timing Table 46: eTQFP64 package mechanical data: – Updated the values. Table 47: eTQFP100 package mechanical data: – Updated the values. Table 48: eTQFP144 package mechanical data: – Updated the values. Table 37: DSPI channel frequency support: – Added column to show slower and faster frequencies.. Table 49: Thermal characteristics for 64 exposed pad eTQFP package: – Removed parameter RθJMA. Table 50: Thermal characteristics for 100 exposed pad eTQFP package: – Removed parameter RθJMA. – Updated the values of all the parameters. Table 51: Thermal characteristics for 144 exposed pad eTQFP package: – Removed parameter RθJMA. DS11597 Rev 4 109/115 114 Revision history SPC582Bx Table 59. Document revision history (continued) Date Revision Changes The following are the changes in this version of the Datasheet. 04-Jun-2018 110/115 3 Replaced reference to IO_definition excel file by “the device pin out IO definition excel file”, throughout the document. Minor formatting changes throughout the document. Section 2: Package pinouts and signal descriptions: Changed introduction sentence since the pinout excel file will no longer be attached to the Datasheet. Table 6: Device supply relation during power-up/power-down sequence: Added a note “The application.....” to parameter VDD_HV_OSC Table 8: Device consumption: – “IDD_LKG”: added footnote “IDD_LKG and IDD_LV are reported as...” – “IDD_LV”: added Footnote “IDD_LKG and IDD_LV are reported as...” – Updated table footnote 4. – Updated all the typical and maximum values for IDD_LKG, IDDSTBY8, and IDDSTBY64 parameters. Table 9: I/O pad specification descriptions: Removed latest sentence at Standby pads description. Table 14: STRONG/FAST I/O output characteristics: Updated values for tTR_S for condition CL = 25 pF and CL = 50 pF Table 15: VERY STRONG/VERY FAST I/O output characteristics: – “tTR20-80” replaced by “tTR20-8_V” – “tTRTTL” replaced by “tTRTTL_V” – “ΣtTR20-80” replaced by “ΣtTR20-80_V” Table 19: PLL0 electrical characteristics: – Added “fINFIN” – Symbol “fINFIN” : changed “C” by “—” in column “C” – |ΔPLL0PHI0SPJ|: changed “T” by “D” and added pk-pk to Conditions value – |ΔPLL0PHI1SPJ|: added pk-pk to Conditions value – The maximum value of fPLL0PHI0 is changed from “400” to “FSYS” with a footnote. Table 20: PLL1 electrical characteristics: Added “fINFIN”. Table 21: External 40 MHz oscillator electrical specifications: – Changed “i.e.” by “that is” in note “Amplitude on the EXTAL... – Changed table footnote 3 by: This value is determined by the crystal manufacturer and board design, and it can potentially be higher than the maximum provided. – Table footnote 1 updated: “DCF clients XOSC_LF_EN and XOSC_EN_40MHZ” changed by “XOSC_FREQ_SEL” DS11597 Rev 4 SPC582Bx Revision history Table 59. Document revision history (continued) Date 04-Jun-2018 Revision Changes 3 (cont’d) Table 24: ADC pin specification: – Updated Max value for CS – For parameter CP2, updated the max value from “1” to “2”. – Changed Max value = 1 by 2 for Cp2 SARB channels Table 25: SARn ADC electrical specification: – Added symbols tADCINIT and tADCBIASINIT – Column “C” splitted and added “D” for IADV_S Figure 11: Voltage monitor threshold definition: Right blue line adjusted on the top figure. Section 3.13.1: Power management integration: Added sentence “It is recommended...device itself”. Table 28: Linear regulator specifications: Updated values for symbol “ΔIDDMREG”, Min: 50 changed to -50. Section 3.14: Flash: Updated the section. Table 41: CAN timing: Added columns for “CC” and “D”. Section 4.4: Package thermal characteristics: Removed table “Thermal characteristics for 144 exposed pad eTQFP package” Figure 33: Ordering information scheme: For Packing, replaced “R” with “X” and removed description related to “R”. Updated the description of “X”. Added Table 52: RAM options and Table 51: Code Flash options. The following are the changes in this version of the Datasheet. Minor formatting changes throughout the document. Updated Title of the document Updated the sub-title of the document Added picture and dimension for QFN48 Updated Table 1: Device summary 01-Dec-2020 4 Updated Chapter 1: Introduction: Removed “Document overview” section title. Updated section 1.2 Description to Chapter 2: Description Chapter 4: Electrical characteristics Section 4.2: Absolute maximum ratings Table 4: Absolute maximum ratings: – Added cross reference to footnote 2. to all VDD_HV* and VIN – Removed Symbol VDD_HV_IO_FLEX for Parameter “I/O supply voltage” DS11597 Rev 4 111/115 114 Revision history SPC582Bx Table 59. Document revision history (continued) Date Revision Changes Section 4.3: Operating conditions Table 5: Operating conditions: – VDD_HV_ADR_S: removed line for C condition.: – TJ: changed value in column C from “P” to “C”. – Removed Symbol VDD_HV_IO_FLEX for Parameter “I/O supply voltage” Section 4.5: Electromagnetic compatibility characteristics Updated section title from Electromagnetic emission characteristics to Electromagnetic compatibility characteristics. Updated Section 4.6: Temperature profile Section 4.7: Device consumption Table 8: Device consumption: move table footnote 1. from table title to “Value”. Section 4.9: Reset pad (PORST) electrical characteristics Figure 5: Startup Reset requirements: deleted VDDMIN 01-Dec-2020 4 (Cont’d) Section 4.10: PLLs Section 4.10.1: PLL0 Table 19: PLL0 electrical characteristics: changed condition from T to D for |ΔPLL0PHI1SPJ|, ΔPLL0LTJ and IPLL0. Section 4.10.2: PLL1 Table 20: PLL1 electrical characteristics: changed condition from T to D for IPLL1 Section 4.11: Oscillators Section 4.11.2: RC oscillator 16 MHz Table 22: Internal RC oscillator electrical specifications: – updated Max value for IFIRC. – Updated 2. Section 4.12: ADC system Figure 8: Input equivalent circuit (Fast SARn and SARB channels): added parameter “CEXT: external capacitance” and component to scheme. Table 24: ADC pin specification: added row for symbol “CEXT / SR” Updated Section 4.12.1: ADC input description Updated Section 4.12.2: SAR ADC 12 bit electrical specification Section 4.13: Power management Section 4.13.1: Power management integration Table 27: External components integration: – Updated Conditions for CBV. – Updated notes content and numbering 112/115 DS11597 Rev 4 SPC582Bx Revision history Table 59. Document revision history (continued) Date Revision Changes – Updated Min value for RE – Updated Typ value for CLVN – Added note 2 for CFLA – Added note 6 for CADC Section 4.13.3: Voltage monitors Table 30: Voltage monitor electrical characteristics: added footnote “Even if LVD/HVD...” Section 4.14: Flash Updated Table 31: Wait State configuration Updated Table 32: Flash memory program and erase specifications Updated Table 33: Flash memory Life Specification Section 4.15: AC Specifications Updated Figure 22: DSPI CMOS master mode — classic timing, CPHA = 1 Chapter 5: Package information Added introduction sentence in each Package section. Added sub-section “Package mechanical drawings and data information” and introduction sentence to the notes list. Table 45: Package case numbers: removed package reference column. 01-Dec-2020 4 (Cont’d) Figure 30: eTQFP64 package outline: updated. Figure 31: eTQFP64 section A-A: added this figure. Figure 32: eTQFP64 section B-B: added this figure. Table 46: eTQFP64 package mechanical data: updated table, notes content and numbering. Moved notes to new section Section 5.1.1: Package mechanical drawings and data information Figure 33: eTQFP64 leadframe pad design: added this figure. Table 47: eTQFP64 symbol definitions: added this table. Figure 34: eTQFP100 package outline: updated. Figure 35: eTQFP100 section A-A: added this figure. Figure 36: eTQFP100 section B-B: added this figure. Table 48: eTQFP100 package mechanical data: updated table, notes content and numbering. Moved notes to new section Section 5.2.1: Package mechanical drawings and data information Table 49: eTQFP100 symbol definitions: added this table. Figure 37: eTQFP100 leadframe pad design: added this figure. Figure 38: eTQFP144 package outline: updated figure. Table 50: eTQFP144 package mechanical data: updated table, notes content and numbering. DS11597 Rev 4 113/115 114 Revision history SPC582Bx Table 59. Document revision history (continued) Date Revision Changes Moved notes to new section Section 5.3.1: Package mechanical drawings and data information Added Section 5.4: QFN48 package information 01-Dec-2020 4 (Cont’d) Section 5.5: Package thermal characteristics Added Section 5.5.3: QFN48 Chapter 6: Ordering information Figure 43: Ordering information scheme: – Added figure footnote – For Package: added information for QFN48 114/115 DS11597 Rev 4 SPC582Bx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS11597 Rev 4 115/115 115