SPC58EEx, SPC58NEx
32-bit Power Architecture® microcontroller for automotive ASIL-D
applications
Datasheet - production data
• Junction temperature range -40 °C to 165 °C
FPBGA292 (17 x 17 x 1.8 mm)
eLQFP176 (24 x 24 x 1.4 mm)
Known Good Die
Features
• AEC-Q100 qualified
• 32-bit Power Architecture VLE compliant CPU
cores:
– Three main CPUs, dual issue, 32-bit CPU
core complexes (e200z4), two of them
having one checker core in lock-step
– Floating Point, End-to-End Error Correction
• 6576 KB (6288 KB code flash + 288 KB data
flash) on-chip flash memory:
– supports read during program and erase
operations, and multiple blocks allowing
EEPROM emulation
– Supports read while read between the two
code Flash partitions.
• 608 KB on-chip general-purpose SRAM (in
addition to 160 KB core local data RAM)
• 96-channel direct memory access controller
(eDMA)
• Comprehensive new generation ASIL-D safety
concept:
– ASIL-D of ISO 26262
– FCCU for collection and reaction to failure
notifications
– Memory Error Management Unit (MEMU)
for collection and reporting of error events
in memories
– Cyclic redundancy check (CRC) unit
• Dual-channel FlexRay controller
• Hardware Security Module (HSM)
October 2017
This is information on a product in full production.
• GTM 343 - Generic Timer Module:
– Intelligent complex timer module
– 144 channels (40 input and 104 output)
– 5 programmable fine grain multi-threaded
cores
– 24-bit wide channels
• Enhanced analog-to-digital converter system
with:
– 1 supervisor 12-bit SAR analog converter
– 4 separate fast 12-bit SAR analog
converters
– 3 separate 10-bit SAR analog converters,
one with STDBY mode support
– 6 separate 16-bit Sigma-Delta analog
converters
• Communication interfaces:
– 18 LINFlexD modules
– 10 deserial serial peripheral interface
(DSPI) modules
– 8 MCAN interfaces with advanced shared
memory scheme and ISO CAN-FD support,
one supporting time-triggered controller
area network (TTCAN)
• Two Ethernet controller 10/100 Mbps,
compliant IEEE 802.3-2008
• Flexible Power Supply options:
– External Regulators (1.2 V core, 3.3 V–5 V
IO)
– Single internal SMPS regulator
(eLQFP176)
– Single internal Linear Regulator with
external ballast (FPBGA292)
• Nexus development interface (NDI) per IEEEISTO 5001-2003 standard, with some support
for 2010 standard
• Boot assist Flash (BAF) supports factory
programming using a serial bootload through
the asynchronous CAN or LIN/UART
DocID029333 Rev 3
1/153
www.st.com
SPC58EEx, SPC58NEx
Table 1. Device summary
Part number
4 MB
Package
2/153
6 MB
Dual core
Triple core
Dual core
Triple core
eLQFP176
SPC58EE80E7
SPC58NE80E7
SPC58EE84E7
SPC58NE84E7
FPBGA292
SPC58EE80C3
SPC58NE80C3
SPC58EE84C3
SPC58NE84C3
KGD
—
—
—
SPC58NE84H0
DocID029333 Rev 3
SPC58EEx, SPC58NEx
Table of contents
Table of contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1
Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3
Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package pinouts, pad characteristics, and signal descriptions . . . . . 17
2.1
3
Pad dimensions/ KGD coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.1
Power domains and power up/down sequencing . . . . . . . . . . . . . . . . . 24
3.4
Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5
Electromagnetic emission characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6
Temperature profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7
Device consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.8
I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.8.1
I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.8.2
I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.8.3
I/O pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.9
Reset pad (PORST, ESR0) electrical characteristics . . . . . . . . . . . . . . . . 44
3.10
PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.11
3.10.1
PLL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.10.2
PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.11.1
Crystal oscillator 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.11.2
Crystal Oscillator 32 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.11.3
RC oscillator 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.11.4
Low power RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DocID029333 Rev 3
3/153
5
Table of contents
3.12
4
5
4/153
SPC58EEx, SPC58NEx
ADC system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.12.1
ADC input description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.12.2
SAR ADC 12 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.12.3
SAR ADC 10 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.12.4
S/D ADC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.13
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.14
LFAST pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.14.1
LFAST interface timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.14.2
LFAST and MSC/DSPI LVDS interface electrical characteristics . . . . . 73
3.14.3
LFAST PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.15
Aurora LVDS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.16
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.16.1
Power management integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.16.2
Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.16.3
Voltage monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.17
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.18
AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.18.1
Debug and calibration interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.18.2
DSPI timing with CMOS and LVDS pads . . . . . . . . . . . . . . . . . . . . . . . 104
3.18.3
Ethernet timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
3.18.4
FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.18.5
PSI5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
3.18.6
CAN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
3.18.7
UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
3.18.8
I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.1
eLQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4.2
FPBGA292 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.3
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
4.3.1
LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
4.3.2
BGA292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
4.3.3
General notes for specifications at maximum junction temperature . . 139
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
DocID029333 Rev 3
SPC58EEx, SPC58NEx
6
Table of contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
DocID029333 Rev 3
5/153
5
List of tables
SPC58EEx, SPC58NEx
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
6/153
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SPC58xEx feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PRAM wait states configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Device supply relation during power-up/power-down sequence. . . . . . . . . . . . . . . . . . . . . 25
ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Device consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
I/O pad specification descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I/O input electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
I/O pull-up/pull-down electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
WEAK/SLOW I/O output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
MEDIUM I/O output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STRONG/FAST I/O output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
VERY STRONG/VERY FAST I/O output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reset PAD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Reset Pad state during power-up and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PLL0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
PLL1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
External 40 MHz oscillator electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
32 kHz External Slow Oscillator electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Internal RC oscillator electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1024 kHz internal RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ADC pin specification, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SARn ADC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
ADC-Comparator electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SDn ADC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
LVDS pad startup and receiver electrical characteristics,. . . . . . . . . . . . . . . . . . . . . . . . . . 73
LFAST transmitter electrical characteristics,, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
MSC/DSPI LVDS transmitter electrical characteristics ,, . . . . . . . . . . . . . . . . . . . . . . . . . . 76
MSC LVDS transmitter electrical characteristics for LFAST pads. ,, . . . . . . . . . . . . . . . . . 76
LFAST PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Aurora LVDS electrical characteristics, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Power management regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
External components integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Linear regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Auxiliary regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Clamp regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Standby regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SMPS Regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Wait State configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Flash memory program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Flash memory Life Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
JTAG pin AC electrical characteristics, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
DocID029333 Rev 3
SPC58EEx, SPC58NEx
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
List of tables
Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Aurora LVDS interface timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Aurora debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
DSPI channel frequency support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
DSPI CMOS master classic timing (full duplex and output only) — MTFE = 0,
CPHA = 0 or 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
DSPI CMOS master modified timing (full duplex and output only) — MTFE = 1,
CPHA = 0 or 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
DSPI LVDS master timing — full duplex — modified transfer format (MTFE = 1), CPHA = 0
or 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1,
CPOL = 0 or 1, continuous SCK clock,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1,
CPOL = 0 or 1, continuous SCK clock, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
DSPI CMOS slave timing — full duplex — normal and modified transfer formats
(MTFE = 0/1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
MII receive signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
MII transmit signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
MII async inputs signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
MII serial management channel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
RMII serial management channel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
RMII receive signal timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
RMII transmit signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
TxEN output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
TxD output characteristics, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
RxD input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
PSI5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
CAN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
UART frequency support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
I2C input timing specifications — SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
I2C output timing specifications — SCL and SDA,,, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Package case numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
eLQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
FPBGA292 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Thermal characteristics for 176 exposed pad LQFP package . . . . . . . . . . . . . . . . . . . . . 138
Thermal characteristics for 292-pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Code Flash options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
RAM options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
DocID029333 Rev 3
7/153
7
List of figures
SPC58EEx, SPC58NEx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
8/153
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Periphery allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I/O input electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
I/O output DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Startup Reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PLLs integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Input equivalent circuit (Fast SARn and SARB channels) . . . . . . . . . . . . . . . . . . . . . . . . . 54
LFAST and MSC/DSPI LVDS timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Power-down exit time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Rise/fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
LVDS pad external load diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
External regulator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Internal regulator with external ballast mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SMPS Regulator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Standby regulator with external ballast mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Voltage monitor threshold definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
JTAG JCOMP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Aurora timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
DSPI CMOS master mode — classic timing, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . 108
DSPI CMOS master mode — classic timing, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . 108
DSPI PCS strobe (PCSS) timing (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
DSPI CMOS master mode — modified timing, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . 112
DSPI CMOS master mode — modified timing, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 112
DSPI PCS strobe (PCSS) timing (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
DSPI LVDS master mode — modified timing, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 115
DSPI LVDS master mode — modified timing, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 115
DSPI LVDS and CMOS master timing–output only— MTFE = 1, CHPA = 1 . . . . . . . . . . 118
DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 0. . . . . . . . . 119
DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 1. . . . . . . . . 120
MII receive signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
MII transmit signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
MII async inputs timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
MII serial management channel timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
MII serial management channel timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
RMII receive signal timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
RMII transmit signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
TxEN signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
TxEN signal propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
TxD signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
DocID029333 Rev 3
SPC58EEx, SPC58NEx
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
List of figures
TxD Signal propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
I2C input/output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
eLQFP176 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
FPBGA292 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Commercial product scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
DocID029333 Rev 3
9/153
9
Introduction
SPC58EEx, SPC58NEx
1
Introduction
1.1
Document overview
This document provides electrical specifications, pin assignments, and package diagrams
for the SPC5x series of microcontroller units (MCUs). For functional characteristics, see the
SPC5x microcontroller reference manual.
1.2
Description
The SPC58xEx microcontroller is the first in a new family of devices superseding the SPC5x
family. SPC58xEx builds on the legacy of the SPC5x family, while introducing new features
coupled with higher throughput to provide substantial reduction of cost per feature and
significant power and performance improvement (MIPS per mW).
1.3
Device feature summary
Table 2. SPC58xEx feature summary
Feature
Description
SPC58 family
40 nm
Computing Shell 0
Number of Cores
up to 2
Number of checker cores
up to
16 KB Instruction
Local RAM
64 KB Data
Single Precision Floating Point
Yes
SIMD (LSP)
No
VLE
Yes
8 KB Instruction
Cache
4 KB Data
Computing Shell 1
Number of Cores
1
Number of checker cores
up to 1
16 KB Instruction
Local RAM
10/153
32 KB Data
Single Precision Floating Point
Yes
SIMD (LSP)
Yes
VLE
Yes
Cache
8 KB Instruction
DocID029333 Rev 3
SPC58EEx, SPC58NEx
Introduction
Table 2. SPC58xEx feature summary
Feature
Description
Other
MPU
Yes
Security (HSM Module)
up to 1
Semaphores
Yes
CRC Channels
2x4
Software Watchdog Timer (SWT)
4
Core Nexus Class
3+
4 x SCU
Event Processor
4 x PMC
Run control Module
Yes
System SRAM
608 KB (including 256 KB of standby RAM(1))
User Flash memory
up to 6144 KB code / 256 KB data
Flash fetch accelerator
2 x 2 x4 x 256-bit
Security Flash memory
up to 144 KB code / 32 KB data
Flash Overlay RAM
2 x 16 KB
Calibration Interface
64-bit IPS Slave
DMA channels
96
DMA Nexus Class
3
LINFlexD
18
M_CAN supporting CAN-FD
according to ISO 11898-1 2015
(instances supporting also TTCAN)
8 (1)
DSPI
10
Microsecond channel downlink
2
SENT bus
15
I2C
1
PSI5 bus
2
FlexRay
1 x Dual channel
Ethernet
2
SIPI / LFAST Interprocessor bus
High Speed
8 PIT channels
System Timers
4 AUTOSAR® (STM)
RTC/API
GTM Timer
40 Input Channels, 104 Output Channels
GTM RAM
61 KB
DocID029333 Rev 3
11/153
16
Introduction
SPC58EEx, SPC58NEx
Table 2. SPC58xEx feature summary
Feature
Description
Interrupt controller
> 710 sources
ADC (SAR)
8
ADC (SD)
6
Temp. sensor
Yes
Self Test Controller
Yes
PLL
Dual PLL with FM
Integrated linear voltage regulator
Yes(1)
Integrated switch mode voltage
regulator (SMPS)
Yes(2)
External Power Supplies
3.3 V - 5 V, 1.2 V
Stop Mode
Halt Mode
Low Power Modes
Smart Standby with output controller, analog and digital
inputs(1)
Standby Mode(1)
1. Except eLQFP176.
2. Except LFBGA292.
1.4
Block diagram
Figure 1 and Figure 2 show the top-level block diagrams.
12/153
DocID029333 Rev 3
SPC58EEx, SPC58NEx
Introduction
Figure 1. Block diagram
1H[XV'DWD
7UDFH
1H[XV'DWD
7UDFH
1H[XV'DWD
7UDFH
$''
'$7$
$''
'$7$
$''
'$7$
.%
ZD\
'0(0
&RQWURO
'&DFKH
&RQWURO
.%
'0(0
.%
ZD\
8QLILHG
%DFNGRRU
,QWHUIDFH
:LWK
(((&&
&RUH0HPRU\3URWHFWLRQ8QLW
&038
&K
H'0$B
$''
'$7$
(((&&
3$08
0+]
(((&&
3$08
0+]
1H[XV'DWD
7UDFH
1H[XV'DWD
7UDFH
%,8ZLWK(((&&
'HFRUDWHG6WRUDJH$FFHVV
,QVWUXFWLRQ
$''
'$7$
/RDG6WRUH
$''
'$7$
$+%B0
$+%B0
$+%B0
$+%B0
$+%B0
$+%B0
$+%B0$+%B0
)DVW&URVV%DU6ZLWFK ;%$5B $0%$Y$+%±ELW±0+]$+%B0
6\VWHP0HPRU\3URWHFWLRQ8QLW 6038B
$+%B6
$+%B6
$+%B6
$+%B6
$+%B6
$+%B6
$''
'$7$
$''
'$7$
$''
'$7$
$''
'$7$
$''
'$7$
3HULSK%ULGJH 3HULSK%ULGJH
35$0&B
35$0&B
$,36B
$,36B
ZLWK(((&& ZLWK(((&&
(((&&
(((&&
0+]
0+]
0+]
0+]
$''
'$7$
$''
'$7$
$''
'$7$
$''
'$7$
3HULSKHUDO
&OXVWHU
0+]
3HULSKHUDO
&OXVWHU
0+]
65$0
$UUD\
.%
65$0
$UUD\
.%
67'%<
$''
'$7$
$''
'$7$
$+%B0
$+%B0
$+%B0
638
1H[XV$XURUD5RXWHU
6:7B,$&
6:7B,$&
H]Q±0+]
GXDOLVVXH
1H[XVS
0DLQ&RUHB
H]Q±0+]
GXDOLVVXH
1H[XVS
0DLQ&RUHB
9/(
()38
,0(0
&RQWURO
,&DFKH
&RQWURO
.%
,0(0
.%
ZD\
'0(0
&RQWURO
'&DFKH
&RQWURO
.%
'0(0
.%
ZD\
8QLILHG
%DFNGRRU
,QWHUIDFH
:LWK
(((&&
&RUH0HPRU\3URWHFWLRQ8QLW
&038
%,8ZLWK(((&&
'HFRUDWHG6WRUDJH$FFHVV
9/(
()38
,0(0
&RQWURO
,&DFKH
&RQWURO
.%
,0(0
.%
ZD\
'0(0
&RQWURO
'&DFKH
&RQWURO
.%
'0(0
.%
ZD\
8QLILHG
%DFNGRRU
,QWHUIDFH
:LWK
(((&&
&RUH0HPRU\3URWHFWLRQ8QLW
&038
%,8ZLWK(((&&
'HFRUDWHG6WRUDJH$FFHVV
,QVWUXFWLRQ
$''
'$7$
/RDG6WRUH
$''
'$7$
,QVWUXFWLRQ
$''
'$7$
/RDG6WRUH
$''
'$7$
$+%B0
$+%B0
$+%B0
$+%B0
)DVW&URVV%DU6ZLWFK ;%$5B $0%$Y$+%±ELW±0+]
6\VWHP0HPRU\3URWHFWLRQ8QLW 6038B
$+%B6
$+%B6
$+%B6
$''
'$7$
3)/$6+&B0+]
6HW$VVRFLDWLYH
3UHIHWFK%XIIHUV
ZLWK(((&&
$+%B6
$''
'$7$
3DJH/LQH
)/$6+0%
)/$6+0%
1RQ9RODWLOH0HPRU\
0XOWLSOH5::SDUWLWLRQV
DocID029333 Rev 3
$+%B6
$+%B6
$+%B6
$+%B6
$+%B6
$+%B6
$''
'$7$
$''
'$7$
$''
'$7$
$''
'$7$
35$0&B
ZLWK((
(&&
0+]
35$0&B
ZLWK((
(&&
0+]
3HULSK%ULGJH
$,36B
(((&&
0+]
$''
'$7$
$''
'$7$
$''
'$7$
65$0
$UUD\
.%
65$0
$UUD\
.%
3HULSKHUDO
&OXVWHU
0+]
3)/$6+&B0+]
6HW$VVRFLDWLYH
3UHIHWFK%XIIHUV
ZLWK(((&&
((3520
[[.%
%XGG\ 1$5 2YHUOD\ $08
'HYLFH $+% 5$0
,QWHUIDFH
.%
'HOD\HG/RFNVWHSZLWK5HGXQGDQF\&KHFNHUV
.%
,0(0
/63
'0$&+08;B
'0$&+08;B
()38
,&DFKH
&RQWURO
'&,
'HOD\HG/RFNVWHSZLWK5HGXQGDQF\&KHFNHUV
&RQFHQWUDWRUB &RQFHQWUDWRUB &RQFHQWUDWRUB
(((&&
(((&&
(((&&
3$08
3$08
3$08
0+]
0+]
0+]
9/(
,0(0
&RQWURO
-7$*&
6,3,B LQWHUSURFHVVRU
+60
$''
'$7$
6:7B,$&
H]Q±0+]
GXDOLVVXH
1H[XVS
0DLQ&RUHB
'HOD\HG/RFNVWHSZLWK5HGXQGDQF\&KHFNHUV
'0$&+08;B
'0$&+08;B
'0$&+08;B
'0$&+08;B
)OH[5D\B
(7+(51(7B
6,3,B 'HEXJ
(7+(51(7B
&K
H'0$B
$+%B0
-7$*0
,17&B
$OOVKDGRZHG
PRGXOHVDUHLQ
GHO\HG/RFNVWHS
FRQILJXUDWLRQ
%XGG\'HYLFH 2YHUOD\
,QWHUIDFH 5$0
.%
13/153
16
Introduction
SPC58EEx, SPC58NEx
Figure 2. Periphery allocation
$,36B
;%$5B
;%,&B&RQFHQWUDWRUB
(7+(51(7B
*70
6038B
6$5B$'&BELWB
6$5B$'&BELWB
213ODWIRUP,3
2))3ODWIRUP,3
;%,&B
35$0B
6$5B$'&BELWB67'%<
3&0B
6$5B$'&BELWB683(59,625
3)/$6+B
36,B
)/(;5$
工商网监
湘ICP备2023018690号