SPC58NH92E7RMI0X

SPC58EHx, SPC58NHx SPC58 H Line - 32 bit Power Architecture automotive MCU Triple z4 cores 200 MHz, 10 MBytes Flash, HSM, ASIL-D Datasheet - production data eTQFP144 (20 x 20 x 1.0 mm) FPBGA302 (17 x 17 x 1.8 mm) eLQFP176 (24 x 24 x 1.4 mm) FPBGA386 (19 x 19 x 1.8 mm) Features • AEC-Q100 qualified • High performance e200z4 triple core: – 32-bit Power Architecture technology CPU – Core frequency as high as 200 MHz – Variable Length Encoding (VLE) – Floating Point, End-to-End Error Correction • 10496 KB (10240 KB code Flash + 256 KB data Flash) on-chip Flash memory: – Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation – Supports read while read between the two code Flash partitions – Hardware support for Flash context switching (for FOTA with multi software versions) • 1088 KB on-chip general-purpose SRAM (in addition to 192 KB core local data RAM): – 64 KB in CPU_0, 64 KB in CPU_1 and 64 KB in CPU_2 • 224 KB HSM dedicated Flash memory (192 KB code + 32 KB data) • Multi-channel direct memory access controller (eDMA): – One eDMA with 64 channels – One eDMA with 16 channels • One interrupt controller (INTC) June 2021 This is information on a product in full production. • Comprehensive new generation ASIL-D safety concept: – ASIL-D of ISO 26262 – One CPU channel in lockstep – Logic BIST – FCCU for collection and reaction to failure notifications – Memory BIST – Cyclic redundancy check (CRC) unit – Memory Error Management Unit (MEMU) for collection and reporting of error events in memories • Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC • Body cross triggering unit (BCTU): – Triggers ADC conversions from any eMIOS channel – Triggers ADC conversions from up to 2 dedicated PIT_RTIs • Enhanced modular IO subsystem (eMIOS): – up to 96 timed IO channels with 16-bit counter resolution • Enhanced analog-to-digital converter system with: – 4 independent fast 12-bit SAR analog converters – One supervisor 12-bit SAR analog converter – One standby 10-bit SAR analog converter – 100 ADC channels • Communication interfaces: – 24 LINFlexD modules – 10 deserial serial peripheral interface (DSPI) modules – 1 deserial serial peripheral interface (DSPI_LP) module available in low power mode DS12304 Rev 5 1/147 www.st.com SPC58EHx, SPC58NHx – 16 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support – Dual-channel FlexRay controller – One SD/SDIO/eMMC module – One OctalSPI module with double Chip Select – Two independent Ethernet controllers, one 10/100Mbps and the other one 10/100Mbps or 1Gbps, compliant IEEE 802.3-2008 and OPEN RGMII EPL v2.3 – Four I2C modules – Two PSI5 modules • Low power capabilities: – Versatile low power modes – Ultra low power standby with RTC – Smart Wake-up Unit for contact monitoring – Fast wakeup schemes • Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell • Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard • Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART • Low power supply options: – Single internal linear regulator with external ballast – External low voltage supply (1.2V) • Temperature range: – -40 °C to 105 °C – -40 °C to 125 °C Table 1. Device summary Part number Package 6 MB Dual core 8 MB Triple core Dual core 10 MB Triple core Dual core Triple core eTQFP144 SPC58EH84E5 SPC58NH84E5 SPC58EH90E5 SPC58NH90E5 SPC58EH92E5 SPC58NH92E5 eLQFP176 SPC58EH84E7 SPC58NH84E7 SPC58EH90E7 SPC58NH90E7 SPC58EH92E7 SPC58NH92E7 FPBGA302 SPC58EH84C3 SPC58NH84C3 SPC58EH90C3 SPC58NH90C3 SPC58EH92C3 SPC58NH92C3 FPBGA386 SPC58EH84C5 SPC58NH84C5 SPC58EH90C5 SPC58NH90C5 SPC58EH92C5 SPC58NH92C5 2/147 DS12304 Rev 5 SPC58EHx, SPC58NHx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 17 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.1 Power domains and power up/down sequencing . . . . . . . . . . . . . . . . . 24 4.4 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 Electromagnetic compatibility characteristics . . . . . . . . . . . . . . . . . . . . . . 26 4.6 Temperature profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.7 Device consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.8 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.8.1 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.8.2 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.8.3 I/O pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.9 Reset pad (PORST) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 44 4.10 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.11 4.12 4.10.1 PLL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.10.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.10.3 PLL_ETH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.11.1 Crystal oscillator 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.11.2 Crystal Oscillator 32 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.11.3 RC oscillator 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.11.4 Low power RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 ADC system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 DS12304 Rev 5 3/147 5 Contents SPC58EHx, SPC58NHx 4.12.1 ADC input description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.12.2 SAR ADC 12 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.12.3 SAR ADC 10 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.13 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.14 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.14.1 Power management integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.14.2 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.14.3 Voltage monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.15 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.16 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.16.1 Debug and calibration interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.16.2 DSPI timing with CMOS pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.16.3 Ethernet port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.16.4 FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.16.5 CAN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.16.6 UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.16.7 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.16.8 PSI5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.16.9 OctoSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.16.10 SDMMC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.1 eTQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 5.1.1 5.2 eLQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 5.2.1 5.3 4/147 Package mechanical drawings and data information . . . . . . . . . . . . . 122 FPBGA386 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.4.1 5.5 Package mechanical drawings and data information . . . . . . . . . . . . . 119 FPBGA302 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.3.1 5.4 Package mechanical drawings and data information . . . . . . . . . . . . . 114 Package mechanical drawings and data information . . . . . . . . . . . . . 125 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.5.1 eTQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.5.2 LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.5.3 FPBGA302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.5.4 FPBGA386 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.5.5 General notes for specifications at maximum junction temperature . . 129 DS12304 Rev 5 SPC58EHx, SPC58NHx Contents 6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 DS12304 Rev 5 5/147 5 Introduction 1 SPC58EHx, SPC58NHx Introduction This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet. 6/147 DS12304 Rev 5 SPC58EHx, SPC58NHx 2 Description Description The SPC58EHx, SPC58NHx microcontroller belongs to a family of devices superseding the SPC58x family. SPC58EHx, SPC58NHx builds on the legacy of the SPC5x family, while introducing new features coupled with higher throughput to provide substantial reduction of cost per feature and significant power and performance improvement (MIPS per mW). 2.1 Device feature summary Table 2 lists a summary of major features for the SPC58EHx, SPC58NHx device. The feature column represents a combination of module names and capabilities of certain modules. A detailed description of the functionality provided by each on-chip module is given later in this document. Table 2. Features list Feature Description SPC58 family 40 nm Processing shell Number of Cores 2 Number of checker cores 1 32 KB Instruction Local RAM 64 KB Data Single Precision Floating Point Yes SIMD (LSP) Yes VLE Yes 16 KB Instruction Cache 8 KB Data Streaming shell Number of Cores 1 Number of checker cores 0 32 KB Instruction Local RAM 64 KB Data Single Precision Floating Point Yes SIMD (LSP) Yes VLE Yes 16 KB Instruction Cache 8 KB Data Other Security (HSM Module) up to 1 DS12304 Rev 5 7/147 16 Description SPC58EHx, SPC58NHx Table 2. Features list (continued) Feature Description Core MPU: 24 per CPU MPU System MPU: 24 per XBAR Semaphores Yes CRC Channels 2x4 Software Watchdog Timer (SWT) 4 Core Nexus Class 3+ 4 x SCU Event Processor 4 x PMC Run control Module Yes System SRAM 1088 KB (including 256 KB of standby RAM) User Flash up to 10240 KB code / 256 KB data Security Flash up to 192 KB code / 32 KB data Flash fetch accelerator 2 x 2 x 4 x 256-bit DMA channels 80 DMA Nexus Class 3 LINFlexD 24 M_CAN supporting CAN-FD according to ISO 11898-1 2015 16 DSPI 11 I2C 4 PSI5 / PSI5-S bus 2/1 FlexRay 1 x Dual channel Ethernet 2 MAC with Time stamping, AVB and VLAN support 8 PIT channels 4 AUTOSAR® (STM) System Timers RTC/API 8/147 eMIOS 3 x 32 channels OctalSPI 1 (2 Chip select) SDMMC 1 GST 1 BCTU 96 channels Interrupt controller > 710 sources ADC (SAR) Five 12-bit (4+1 Supervisor); One 10-bit Temp. sensor Yes Self Test Controller Yes DS12304 Rev 5 SPC58EHx, SPC58NHx Description Table 2. Features list (continued) Feature Description PLL Dual PLL with FM External Power Supplies 1.2 V - 3.3 V - 5 V Integrated linear voltage regulator Yes Stop Mode Low Power Modes Halt Mode Smart Standby with output controller, analog and digital inputs Standby Mode DS12304 Rev 5 9/147 16 Description 2.2 SPC58EHx, SPC58NHx Block Diagram The figures below show the top-level block diagrams. Figure 1. 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Periphery allocation PBRIDGE_2 Backdoor_XBAR BCTU_0 STDBY_CTU_0 eMIOS_0 GST_0 XBAR_1 XBIC_Backdoor_XBAR ON-Platform IP OFF-Platform IP XBIC_Concentrator_1 SAR_ADC_12bit_0_seq SAR_ADC_12bit_2_seq SAR_ADC_10bit_STDBY_seq SMPU_1, 3 XBIC_1 SAR_ADC_12bit_SUPERVISOR_seq PCM_0 SAR_ADC_12bit_0, 2 PFLASH_1 SEMA42 SAR_ADC_10bit_0_STDBY SAR_ADC_12bit_SUPERVISOR INTC_1 PSI5_0 FLEXRAY I2C_0 I2C_2 SWT_0, 2, 3 STM_0, 2 eDMA_1 PRAM_2, 3 TDM_0 DSPI_0, 2, 4, 6, 8 LINFlex_0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22 CAN_SUB_0_MESSAGE_RAM DTS JDC STCU JTAGM MEMU IMA CRC_0 DMAMUX_0, 2 PSI5-S PIT_0 SAR_ADC_12bit_1, 3 PSI5_1 I2C_1 I2C_3 DSPI_1, 3, 5, 7, 9 LINFlex_1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23 CAN_SUB_1_MESSAGE_RAM WKPU_0 CAN_SUB_1_M_CAN_1, 2, 3, 4 MC_PCU FCCU CRC_1 MC_RGM DMAMUX_1, 3 PIT_1 RC1024K_DIG OSC40M_DIG OSC32K_DIG WKPU_1 CMU_1_CORE_XBAR CMU_2_HPBM PBRIDGE_0 XBAR_0, 2 SMPU 0, 2 PRAM_0,1 PFLASH_0 SWT_1 STM_1 eDMA_0 XBIC_2 PLL_DIG PLL_DIG_ETH CMU_3_PBRIDGE CMU_0_PLL0_XOSC_IRCOSC CMU_8_PSI5_f189 ETHERNET_0, 1 MC_CGM CMU_9_PSI5_f125 DSPI_LP MC_ME CMU_10_PSI5_1us SIUL2 CMU_11_FBRIDGE CMU_12_EMIOS CMU_14_PFBRIDGE CMU_15_MMC CMU_16_OctalSPI CMU_17_PER1 CMU_18_ETH_50M_125M PCM_1 CAN_SUB_2_MESSAGE_RAM CAN_SUB_2_M_CAN_1, 2, 3, 4 CAN_SUB_3_MESSAGE_RAM FLASH_0 FLASH_ALT_0 PASS SSCM BAR CMU_6_SARADC DS12304 Rev 5 eMIOS_2 AIPS_0 - Peripheral Cluster 0 PMC_DIG RC16M_DIG PBRIDGE_1 eMIOS_1 SAR_ADC_12bit_1_seq SAR_ADC_12bit_3_seq AIPS_1 - Peripheral Cluster 1 RTC/API AIPS_2 - Peripheral Cluster 2 CAN_SUB_0_M_CAN_0, 1, 2, 3 HSMHost I/F CAN_SUB_3_M_CAN_1, 2, 3, 4 CRC_2 DMAMUX_4 11/147 16 Description 2.3 SPC58EHx, SPC58NHx Features On-chip modules within SPC58EHx, SPC58NHx include the following features: • 12/147 Three main CPUs, dual issue, 32-bit CPU core complexes (e200z4), one of them having a checker core in lock-step – Power Architecture embedded specification compliance – Instruction set enhancement allowing variable length encoding (VLE), encoding a mix of 16-bit and 32-bit instructions, for code size footprint reduction – Single-precision floating point operations – Lightweight signal processing auxiliary processing unit (LSP APU) instruction support for digital signal processing (DSP) on Core_0, Core_1, Core_2 – 32 KB local instruction RAM and 64 KB local data RAM for Core_0, Core_1 and Core_2 – 16 KB I-Cache and 8 KB D-Cache for Core_0, Core_1 and Core_2 – 10 MB on-chip Flash – Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation – Supports read while read between the two code Flash partitions. • 1088 KB on-chip general-purpose SRAM (+ 192 KB data RAM and 96 KB instruction RAM included in the CPUs) • 224 KB HSM dedicated flash memory (192 KB code + 32 KB data) • Multi channel direct memory access controllers (eDMA) – One eDMA with 64 channels – One eDMA with 16 channels • One interrupt controller (INTC) in lock-step • Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for processing and streaming shell • Dual crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC • Hardware security module (HSM) compliant with EVITA full • System integration unit lite (SIUL) • Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART. • Enhanced analog-to-digital converter system with – One supervisor 12-bit SAR analog converter – Four separate fast 12-bit SAR analog converters – One separate 10-bit SAR analog converter for standby mode • Eleven deserial serial peripheral interface (DSPI) modules, one working even in low power mode • Twenty four LIN and UART communication interface (LINFlexD) modules – LINFlexD_0 is a Master/Slave – All others are Masters • Sixteen modular controller area network (MCAN) modules all supporting flexible data rate (CAN-FD) • Dual-channel FlexRay controller DS12304 Rev 5 SPC58EHx, SPC58NHx • Description On ethernet controller 10/100 Mbps (Ethernet 0) – Standard compliance Ethernet interface is compliant to following standards: – IEEE 802.3-2008 for Ethernet MAC, Media Independent Interface (MII), reduced Media Independent Interface (RMII) – IEEE 1588-2008 for precision networked clock synchronization – IEEE 802.1AS-2011 and 802.1-Qav-2009 for Audio Video (AV) traffic – IEEE 802.3az-2010 for Energy Efficient Ethernet (EEE) with MII interface – RMII specification version 1.2 from RMII consortium – Turbo MII, overclocked MII @200 Mbps – AMBA 2.0 for AHB master port and APB slave port – MAC Tx and Rx features: – Separate transmission, reception, and control interfaces to the application – 10, 100 Mbps data transfer rates with the following PHY interfaces: IEEE 802.3-compliant MII interface to communicate with an external Fast Ethernet PHY RMII interface to communicate with an external Fast Ethernet PHY – Half-duplex operation – Full-duplex flow control operations (IEEE 802.3x Pause packets and Priority flow control) – Network statistics with RMON or MIB Counters (RFC2819/RFC2665) – Support Ethernet packet timestamping as described in IEEE 1588-2002 and IEEE 1588-2008. Both one-step and two-step timestamping is supported in TX direction – Flexibility to control the Pulse-Per-Second (PPS) output signal (ptp_pps_o) – MDIO (Clause 22 and Clause 45) master interface for PHY device configuration and management – MAC Tx features: – Source Address field insertion or replacement, VLAN insertion, replacement, and deletion in transmitted packets with per-packet or static-global control – MAC Rx features: – Automatic Pad and CRC Stripping options: – Option to disable Automatic CRC checking – Preamble and SFD deletion – Separate 112-bit or 128-bit status – Programmable watchdog timeout limit – Fixed address filtering modes: Up to 31 additional 48-bit perfect (DA) address filters with masks for each byte Up to 31 48-bit SA address comparison check with masks for each byte Option to pass all multi-cast addressed packets Promiscuous mode to pass all packets without any filtering for network monitoring Pass all incoming packets (as per filter) with a status report – Additional packet filtering: DS12304 Rev 5 13/147 16 Description SPC58EHx, SPC58NHx VLAN tag-based: Perfect match and Hash-based filtering. Filtering based on either outer or inner VLAN tag is possible. Layer 3 and Layer 4-based: TCP or UDP over IPv4 or IPv6 Extended VLAN tag based filtering with 16 filters – IEEE 802.1Q VLAN tag detection – DMA block features: – 64-bit data transfers – 2-channel Transmit and Receive engines – Separate DMA channel in the Transmit path for each queue – Single or multiple DMA channels for any number of queues in Receive path – Optimization for packet-oriented DMA transfers with packet delimiters – Byte-aligned addressing for data buffer support – Dual-buffer (ring) descriptor support – Descriptor architecture to allow large blocks of data transfer with minimum CPU intervention (each descriptor can transfer up to 32 KB of data) – Audio and video features: Ethernet0 can be used in Audio Video (AV) mode, and the supported features are compliant to the industry standards for AV traffic: – Separate channels or queues for AV data transfer in 100 Mbps – Up to 2- queues on the Receive paths for AV traffic and 1-queue on the Transmit path for AV traffic – IEEE 802.1-Qav specified credit-based shaper (CBS) algorithm for Transmit channels • One ethernet controller 10/100/1000 Mbps (Ethernet 1) Features changes on top of Ethernet 0: – RGMII PHY interface with DoS on TX clock – Transaction layer supports 3-TX queues and 3 RX queues – DMA supports 3 TX and 3-RX channels – Checksum offload engine on TX Queue0 only – 16 KB each for both TX and RX FIFOs – 2 AV queues on TX and 3 AV queues on RX – MAC does not support half duplex operations – Flexible Receive Parsing based filtering mode: Programmable lookup table based flexible Parser for filtering all incoming packets as per the programmable instructions in the memory. partial/group DA/SA match (bit mask instead of byte mask). partial/group VLAN match (Only perfect match in fixed/register filter) link DA/SA filter with VLAN filter; fixed/register filter does not give that flexibility (sequential links) can do any of the fixed/register filter functions; 14/147 DS12304 Rev 5 SPC58EHx, SPC58NHx Description only difference is that, it can check for patterns sequentially (1 field at a time) unlike fixed/register filtering which can compare in parallel and at line rate. – TSN features: IEEE 802.1Qbv (EST) IEEE 802.1AS-Rev/D2.0 (timing and synchronization) IEEE 802.3br/D3.1 (frame preemption) IEEE 802.1Qbu/D3.1 (frame preemption) • SD/SDIO/MMC host interface that supports: – eMMC - MultiMedia Card Specification v4.51 – 1-bit, 4-bit, 8-bit interface – Full backward compatibility with legacy MMC cards (0-25 MHz), 25 MB/s – Full High Speed SDR bus mode (0-50 MHz), 50 MB/s – Full High Speed DDR bus mode (0-50 MHz), 100 MB/s – 3.3 V IO voltage – SD Card Specification v3.01 – Full support for Default Speed mode (0-25 MHz), 12.5 MB/s – Full support for High Speed (0-50 MHz) mode, 25 MB/s – 1-bit, 4-bit interface – 3.3 V IO voltage – SDIO Specification v3.0 – Full support for Default Speed mode (0-25 MHz) mode, 12.5 MB/s – Full support for High Speed (0-50 MHz) mode, 25 MB/s – 1-bit or 4-bit interface – 3.3 V IO voltage The current version supports only one SD3.01/SDIO3.0/MMC4.51 card at any one time. • OctalSPI host interface that supports: – – SPI mode – 1-bit, 4-bit, 8-bit interface – SDR for 1 bit interface only (SPI mode) – SDR and DDR for 4 and 8 bits interface (quad and Octal SPI mode) – 3.3 V IO voltage – Clock up to 100 MHz – SPI NOR device with DQS mode compliant Hyperbus(TM) bus mode – Compliant with “HyperBus™ Specification Low Signal Count, High Performance DDR Bus”, June 2017, revision F – DDR for 8-bit interface – 3.3 V IO voltage DS12304 Rev 5 15/147 16 Description SPC58EHx, SPC58NHx – Single-ended clock up to 100 MHz The current version supports up to two devices at any one time, which means it has to Chip selects sharing one 8 bits data bus. • 16/147 Low Power Supply options: – External Regulators (1.2 V core, 3.3 V–5 V IO) – Single internal Linear Regulator with external ballast • Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard. • Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1) • Standby power domain with smart wake-up sequence DS12304 Rev 5 SPC58EHx, SPC58NHx 3 Package pinouts and signal descriptions Package pinouts and signal descriptions Refer to the SPC58EHx, SPC58NHx IO_ Definition document. It includes the following sections: 1. Package pinouts 2. Pin descriptions a) Power supply and reference voltage pins b) System pins c) Generic pins DS12304 Rev 5 17/147 17 Electrical characteristics SPC58EHx, SPC58NHx 4 Electrical characteristics 4.1 Introduction The present document contains the target Electrical Specification for the 40 nm family 32-bit MCU SPC58EHx, SPC58NHx products. In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” (Controller Characteristics) is included in the “Symbol” column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” (System Requirement) is included in the “Symbol” column. The electrical parameters shown in this document are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 3 are used and the parameters are tagged accordingly in the tables where appropriate. Table 3. Parameter classifications Classification tag 18/147 Tag description P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design validation on a small sample size from typical devices. D Those parameters are derived mainly from simulations. DS12304 Rev 5 SPC58EHx, SPC58NHx 4.2 Electrical characteristics Absolute maximum ratings Table 4 describes the maximum ratings for the device. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Stress beyond the listed maxima, even momentarily, may affect device reliability or cause permanent damage to the device. Table 4. Absolute maximum ratings Value Symbol C Parameter Conditions Unit Min Typ Max VDD_LV SR D Core voltage operating life range(1) — –0.3 — 1.4 V VDD_HV_IO_MAIN VDD_HV_OSC VDD_HV_FLA VDD_HV_IO_EMMC VDD_HV_IO_ETH0 VDD_HV_IO_ETH1 SR D I/O supply voltage(2) — –0.3 — 6.0 V VSS_HV_ADV SR D ADC ground voltage Reference to digital ground –0.3 — 0.3 V VDD_HV_ADV SR D ADC Supply voltage(2) Reference to VSS_HV_ADV –0.3 — 6.0 V VSS_HV_ADR_S SR D SAR ADC ground reference — –0.3 — 0.3 V VDD_HV_ADR_S SR D SAR ADC voltage reference(2) Reference to VSS_HV_ADR_S –0.3 — 6.0 V VSS-VSS_HV_ADR_S SR D VSS_HV_ADR_S differential voltage — –0.3 — 0.3 V VSS-VSS_HV_ADV SR D VSS_HV_ADV differential voltage — –0.3 — 0.3 V — –0.3 — 6.0 Relative to Vss –0.3 — — Relative to VDD_HV_IO and VDD_HV_ADV — — 0.3 — — — 1 VIN TTRIN SR SR D D I/O input voltage range(2)(3) (4) Digital Input pad transition time(5) DS12304 Rev 5 V ms 19/147 21 Electrical characteristics SPC58EHx, SPC58NHx Table 4. Absolute maximum ratings (continued) Value Symbol IINJ TSTG TPAS C SR SR SR Parameter Conditions Unit Min Typ Max T Maximum DC injection current for each analog/digital PAD(6) — –5 — 5 mA T Maximum nonoperating Storage temperature range — –55 — 125 °C C Maximum nonoperating temperature during passive lifetime — –55 — 150(7) °C — — 20 years TSTORAGE SR — Maximum No supply; storage storage time, temperature in assembled part range –40 °C to programmed in 60 °C ECU TSDR SR T Maximum solder temperature Pbfree packaged(8) — — — 260 °C MSL SR T Moisture sensitivity level(9) — — — 3 — Maximum cumulated XRAY dose Typical range for X-rays source during inspection:80 ÷ 130 KV; 20 ÷ 50 μA — — 1 grey TXRAY dose SR T 1. VDD_LV: allowed 1.335 V - 1.400 V for 60 seconds cumulative time at the given temperature profile. Remaining time allowed 1.260 V - 1.335 V for 10 hours cumulative time at the given temperature profile. Remaining time as defined in Section 4.3: Operating conditions. 2. VDD_HV: allowed 5.5 V – 6.0 V for 60 seconds cumulative time at the given temperature profile, for 10 hours cumulative time with the device in reset at the given temperature profile. Remaining time as defined in Section 4.3: Operating conditions. 3. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3 V can be used for nominal calculations. 4. Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameter IINJ). 5. This limitation applies to pads with digital input buffer enabled. If the digital input buffer is disabled, there are no maximum limits to the transition time. 6. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in Section 4.8.3: I/O pad current specifications. 20/147 DS12304 Rev 5 SPC58EHx, SPC58NHx Electrical characteristics 7. 175°C are allowed for limited time. Mission profile with passive lifetime temperature >150°C have to be evaluated by ST to confirm that are granted by product qualification. 8. Solder profile per IPC/JEDEC J-STD-020D. 9. Moisture sensitivity per JDEC test method A112. DS12304 Rev 5 21/147 21 Electrical characteristics 4.3 SPC58EHx, SPC58NHx Operating conditions Table 5 describes the operating conditions for the device, and for which all the specifications in the data sheet are valid, except where explicitly noted. The device operating conditions must not be exceeded or the functionality of the device is not guaranteed. Table 5. Operating conditions Value(1) Symbol C Parameter Conditions Unit Min Typ Max FSYS(2) SR P Operating system clock frequency(3) — — — 200 MHz TA_125 Grade(4) SR D Operating Ambient temperature — –40 — 125 °C TJ_125 Grade(4) SR P Junction temperature under bias TA = 125 °C –40 — 150 °C TA_105 Grade(4) SR D Ambient temperature under bias — –40 — 105 °C TJ_105 Grade(4) SR D Operating Junction temperature TA = 105 °C –40 — 130 °C VDD_LV SR P Core supply voltage(5) — 1.14 1.20 1.26(6) (7) V VDD_HV_IO_MAIN VDD_HV_IO_EMMC VDD_HV_IO_ETH0 VDD_HV_IO_ETH1 VDD_HV_FLA VDD_HV_OSC SR P IO supply voltage — 3.0 — 5.5 V VDD_HV_ADV SR P ADC supply voltage — 3.0 — 5.5 V VSS_HV_ADVVSS SR D ADC ground differential voltage — –25 — 25 mV VDD_HV_ADR_S SR P SAR ADC reference voltage — 3.0 — 5.5 V D SAR ADC reference differential voltage — — — 25 mV P SAR ADC ground reference voltage — VDD_HV_ADR_SVDD_HV_ADV VSS_HV_ADR_S 22/147 SR SR DS12304 Rev 5 VSS_HV_ADV V SPC58EHx, SPC58NHx Electrical characteristics Table 5. Operating conditions (continued) Value(1) Symbol C Parameter Conditions Unit Min Typ Max VSS_HV_ADR_SVSS_HV_ADV SR D VSS_HV_ADR_S differential voltage — –25 — 25 mV VRAMP_LV SR D Slew rate on core power supply pins VDD_LV — — 20 V/ms VRAMP_HV SR D Slew rate on HV power supply — — — 100 V/ms VIN SR P I/O input voltage range — 0 — 5.5 V Digital pins and analog pins –3.0 — 3.0 mA Digital pins and analog pins –10 — 10 mA IINJ1 SR T Injection current (per pin) without performance degradation(8) (9) (10) IINJ2 SR D Dynamic Injection current (per pin) with performance degradation(10) (11) 1. The ranges in this table are design targets and actual data may vary in the given range. 2. The PRAM pipeline gasket has to be kept enabled through bit PCM*/BYP_GSKT_XBAR*_TO_PRAMC* to keep system work at maximum speed; The maximum frequency will go to half if the pipeline gasket is bypassed. 3. Maximum operating frequency is applicable to the cores and platform of the device. See the Clock Chapter in the Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the device. 4. In order to evaluate the actual difference between ambient and junction temperatures in the application, refer to Section 5.5: Package thermal characteristics. 5. Core voltage as measured on device pin to guarantee published silicon performance. 6. Core voltage can exceed 1.26 V with the limitations provided in Section 4.2: Absolute maximum ratings, provided that HVD134_C monitor reset is disabled. 7. 1.260 V - 1.290 V range allowed periodically for supply with sinusoidal shape and average supply value below or equal to 1.236 V at the given temperature profile. 8. Full device lifetime. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See Section 4.2: Absolute maximum ratings for maximum input current for reliability requirements. 9. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pins is above the supply rail, current will be injected through the clamp diode to the supply rails. For external RC network calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature. 10. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in Section 4.8.3: I/O pad current specifications. 11. Positive and negative Dynamic current injection pulses are allowed up to this limit. See the dedicated chapters for the different specification limits. See the Absolute Maximum Ratings table for maximum input current for reliability requirements. Refer to the following pulses definitions: Pulse1 (ISO 7637-2:2011), Pulse 2a (ISO 7637-2:2011 5.6.2), Pulse 3a (ISO 7637-2:2011 5.6.3), Pulse 3b (ISO 7637-2:2011 5.6.3). DS12304 Rev 5 23/147 24 Electrical characteristics 4.3.1 SPC58EHx, SPC58NHx Power domains and power up/down sequencing The following table shows the constraints and relationships for the different power domains. Supply1 (on rows) can exceed Supply2 (on columns), only if the cell at the given row and column is reporting ‘ok’. This limitation is valid during power-up and power-down phases, as well as during normal device operation. Table 6. Device supply relation during power-up/power-down sequence Supply2 VDD_HV_IO_ VDD_LV Supply1 VDD_LV(1) MAIN VDD_HV_FLA VDD_HV_OSC ok VDD_HV_IO_ VDD_HV_IO_ VDD_HV_IO_ VDD_HV_ADV VDD_HV_ADR ETH0 ETH1 EMMC ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok VDD_HV_IO_MAIN VDD_HV_FLA VDD_HV_OSC(2) ok VDD_HV_IO_ETH0 ok not allowed VDD_HV_IO_ETH1 ok not allowed ok VDD_HV_IO_EMMC ok not allowed ok ok VDD_HV_ADV ok not allowed ok ok not allowed VDD_HV_ADR ok not allowed ok ok not allowed ok not allowed 1. VDD_LV can be higher than VDD_HV supplies only during power-up/down transient ramps, in case of external LV regulator and if VDD_HV supply voltage level is lower than VDD_LV allowed max operating condition. 2. The application shall grant that these supplies are always at the same voltage level. During power-up, all functional terminals are maintained in a known state as described in the device pinout Microsoft Excel file attached to the IO_Definition document. 24/147 DS12304 Rev 5 SPC58EHx, SPC58NHx 4.4 Electrical characteristics Electrostatic discharge (ESD) The following table describes the ESD ratings of the device: • All ESD testing are in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits, • Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification requirements, which include the complete DC parametric and functional testing at room temperature and hot temperature, maximum DC parametric variation within 10% of maximum specification”. Table 7. ESD ratings Parameter ESD for Human Body Model (HBM)(1) ESD for field induced Charged Device Model (CDM)(2) C Conditions Value Unit T All pins 2000 V T All pins 500 V T Corner Pins 750 V 1. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing. 2. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level. DS12304 Rev 5 25/147 25 Electrical characteristics 4.5 SPC58EHx, SPC58NHx Electromagnetic compatibility characteristics EMC measurements at IC-level IEC standards are available from STMicroelectronics on request. 26/147 DS12304 Rev 5 SPC58EHx, SPC58NHx 4.6 Electrical characteristics Temperature profile The device is qualified in accordance to AEC-Q100 Grade1 requirements, such as HTOL 1,000 h and HTDR 1,000 hrs, TJ = 150 °C. Mission profile exceeding AEC-Q100 Grade 1, and with junction Temperature equal or lower than 150 °C have to be evaluated by ST to confirm that are covered by product qualification. Contact your STMicroelectronics Sales representative for validation. DS12304 Rev 5 27/147 27 Electrical characteristics 4.7 SPC58EHx, SPC58NHx Device consumption Table 8. Device consumption Value(1) Symbol IDD_LKG(2),(3) C CC Parameter Conditions Unit Min Typ Max C TJ = 40 °C — — 24 D TJ = 25 °C — — 16 D Leakage current on the VDD_LV supply D TJ = 55 °C — — 36 TJ = 95 °C — — 110 D TJ = 120 °C — — 220 P TJ = 150 °C — — 500 — — — 550 mA mA IDD_LV(3) CC P Dynamic current on the VDD_LV supply, very high consumption profile(4) IDD_HV CC P Total current on the VDD_HV supply(4) fMAX — — 100 mA IDD_LV_GW CC T Dynamic current on the VDD_LV supply, gateway profile(5) — — — 350 mA IDD_HV_GW CC T Dynamic current on the VDD_HV supply, gateway profile(5),(6) — — — 35 mA IDD_LV_BCM CC T Dynamic current on the VDD_LV supply, body profile(7) — — — 285 mA IDD_HV_BCM CC T Dynamic current on the VDD_HV supply, body profile(7),(6) — — — 40 mA IDD_MAIN_CORE_AC CC T Main Core dynamic current(8) fMAX — — 55 mA IDD_CHKR_CORE_AC CC T Checker Core dynamic operating current fMAX — — 35 mA IDD_HSM_AC CC T HSM platform dynamic operating current(9) fMAX/2 — — 30 mA T Dynamic current on the VDD_LV supply +Total current on the VDD_HV supply — — 106 150 mA T Dynamic current on the VDD_LV supply +Total current on the VDD_HV supply — — 14.5 60 mA IDDHALT(10) IDDSTOP(11) 28/147 CC CC DS12304 Rev 5 SPC58EHx, SPC58NHx Electrical characteristics Table 8. Device consumption (continued) Value(1) Symbol C Parameter Typ Max TJ = 25 °C — 130 380 TJ = 40 °C — — 550 TJ = 55 °C — — 820 TJ = 120 °C — 1.37 4 P TJ = 150 °C — 2.9 8 D TJ = 25 °C — 150 530 µA TJ = 40 °C — — 790 µA TJ = 55 °C — — 1.2 mA TJ = 120 °C — — 5.5 P TJ = 150 °C — — 11 D TJ = 25 °C — 190 680 µA TJ = 40 °C — — 1 mA TJ = 55 °C — — 1.5 TJ = 120 °C — 2.3 7 TJ = 150 °C — 5 14 D SSWU running over all STANDBY period with OPC/TU commands execution and keeping ADC off(14) TJ = 40 °C — 1 3.5 mA D SSWU running over all STANDBY period with OPC/TU/ADC commands execution and keeping ADC on(15) TJ = 40 °C — 3.5 5 mA C IDDSTBY8 CC D D C IDDSTBY128 (12) CC D D C IDDSTBY256(12) CC D D Total standby mode current on VDD_LV and VDD_HV supply, 8 KB RAM(13) Total standby mode current on VDD_LV and VDD_HV supply, 128 KB RAM(13) Total standby mode current on VDD_LV and VDD_HV supply, 256 KB RAM(13) P IDDSSWU1 IDDSSWU2 CC CC Unit Min D (12) Conditions µA mA mA mA 1. The ranges in this table are design targets and actual data may vary in the given range. 2. The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered, and they are computed in the dynamic IDD_LV and IDD_HV parameters. 3. IDD_LKG (leakage current) and IDD_LV (dynamic current) are reported as separate parameters, to give an indication of the consumption contributors. The tests used in validation, characterization and production are verifying that the total consumption (leakage + dynamic) is lower or equal to the sum of the maximum values provided (IDD_LKG + IDD_LV). The two parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions and the software profile used. 4. Use case: 3 x e200Z4 @200 MHz with all locksteps on, HSM @100 MHz, all IPs clock enabled, Flash access with prefetch disabled, Flash consumption includes parallel read and program/erase, all SARADC in continuous conversion, DMA continuously triggered by ADC conversion, 4 DSPI / 8 CAN / 8 LINFlex / FlexRay / ENET0 / ENET1 / eMMC and OctoSPI transmitting, RTC and STM running, 2 x EMIOS running (8 channels in OPWMT mode), FIRC, SIRC, FXOSC, PLL0-1 running. The switching activity estimated for dynamic consumption does not include I/O toggling, which is highly dependent on the application. Details of the software configuration are available separately. The total device consumption is IDD_LV + IDD_HV + IDD_LKG for the selected temperature. 5. GW use case: three cores running @200 MHz, no lockstep, HSM @100 MHz, INTC enabled, 1 EDMA triggered by ADC, PLL0 @200 MHz PLL1 @200 MHz, XOSC = 8/40 MHz, FLASH read only 25%, 12 x CAN running @40 MHz data 4 Mbps/1 Mbps/500 Kbps, 2 x SARADC running @15 MHz with 16 conversion channels, ETH 1 Gbps, OctoSPI @200 Mhz data 100 MB/sec, all other peripherals frozen. DS12304 Rev 5 29/147 30 Electrical characteristics SPC58EHx, SPC58NHx 6. IDD_HV_BCM and IDD_HV_GW consumption measured is averaged in time, by considering non-concurrent peaks from all the IP contributors (ADCs, FLASH, PADS, PMC, TSENS, Oscillators). Please consider IDD_HV parameter as peak value. IO consumption contribution may vary, depending on the application loads differences vs the validation board used. 7. BCM use case: two cores running @160 MHz, no lockstep, HSM @80 MHz, INTC enabled, 1 EDMA triggered by ADC, PLL0 @200 MHz PLL1 @160 MHz, XOSC = 8/40 MHz, FLASH read only 25%, 4 x CAN running @40 MHz data 4 Mbps, 5 x DSPI running @100 MHz data 4 Mbps, 2 EMIOS running @100 MHz - 12 PWM period=3 KHz, 5 x SARADC running @15 MHz with 23 conversion channels, 10 LIN/UART baud-rate 115200, all other peripherals frozen. 8. Dynamic consumption of one core, including the dedicated I/D-caches and I/D-MEMS contribution. 9. Dynamic consumption of the HSM module, including the dedicated memories, during the execution of Electronic Code Book crypto algorithm on 1 block of 16 byte of shared RAM. 10. Flash in Low Power. Sysclk at 160 MHz, PLL0_PHI at 160 MHz, XTAL at 40 MHz, FIRC 16 MHz ON, RCOSC1M off. MCAN: instances: 0, 1, 2, 3, 4, 5, 6 ON (configured but no reception or transmission), Ethernet ON (configured but no reception or transmission), ADC ON (continuously converting). All others IPs clock-gated. 11. Sysclk = RC16 MHz, RC16 MHz ON, RC1 MHz ON, PLL OFF. All possible peripherals off and clock gated. Flash in power down mode. 12. The consumption numbers shown here in IDD standby section are considering standby regulator specs, in case of external regulator mode, the consumption numbers can be higher. 13. STANDBY mode: device configured for minimum consumption, RC16 MHz off, RC1 MHz on. 14. SSWU1 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC off. The total standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the selected memory size and temperature. 15. SSWU2 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC on in continuous conversion. The total standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the selected memory size and temperature. 30/147 DS12304 Rev 5 SPC58EHx, SPC58NHx 4.8 Electrical characteristics I/O pad specification The following table describes the different pad type configurations. Table 9. I/O pad specification descriptions Pad type Description Weak configuration Provides a good compromise between transition time and low electromagnetic emission. Medium configuration Strong configuration Provides transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. Provides fast transition speed; used for fast interface. Very strong configuration Provides maximum speed and controlled symmetric behavior for rise and fall transition. Used for fast interface including Ethernet, SDMMC, OctalSPI and FlexRay interfaces requiring fine control of rising/falling edge jitter. Ultra strong configuration Provides very high speed interfaces till 125 MHz. Used for fast interface including Ethernet, SDMMC, OctalSPI and FlexRay interfaces. Input only pads Standby pads Note: These low input leakage pads are associated with the ADC channels. These pads (LP pads) are active during STANDBY. They are configured in CMOS level logic and this configuration cannot be changed. Moreover, when the device enters the STANDBY mode, the pad-keeper feature can be activated for LP pads. It means that: – if the pad voltage level is above the pad keeper high threshold, a weak pull-up resistor is automatically enabled – if the pad voltage level is below the pad keeper low threshold, a weak pull-down resistor is automatically enabled. For the pad-keeper high/low thresholds please consider (VDD_HV_IO_MAIN / 2) +/-20%. Each I/O pin on the device supports specific drive configurations. See the signal description table in the device reference manual for the available drive configurations for each I/O pin. PMC_DIG_VSIO register has to be configured to select the voltage level (3.3 V or 5.0 V) for each IO segment. Logic level is configurable in running mode while it is CMOS not-configurable in STANDBY for LP (low power) pads, so if a LP pad is used to wakeup from STANDBY, it should be configured as CMOS also in running mode in order to prevent device wrong behavior in STANDBY. The SPC58EHx, SPC58NHx microcontroller has many GPIOs in double bonding; this feature is in place for all packages but FPBGA386. Indeed some IO PADS are bonded together within the package, in order to provide different alternative functions to the same pin/ball. The application shall enable only one pad at a time for each pin/ball in double bonding, in order to avoid high current consumption, due to electrical contention, and reliability issues of the pad drivers. Refer to the SPC58EHx, SPC58NHx IO_ definition document, where double bonded ball/pins are clearly identified, paying attention during software design to strictly avoid the above situation depicted of electrical contention. 4.8.1 I/O input DC characteristics The following table provides input DC electrical characteristics, as described in Figure 3. DS12304 Rev 5 31/147 43 Electrical characteristics SPC58EHx, SPC58NHx Figure 3. I/O input electrical characteristics VIN VDD VIH VHYS VIL VINTERNAL (SIUL register) Table 10. I/O input electrical characteristics Value Symbol C Parameter Conditions Unit Min Typ Max TTL Vihttl SR P Input high level TTL — 2 — VDD_HV_IO + 0.3 V Vilttl SR P Input low level TTL — –0.3 — 0.8 V Vhysttl CC C Input hysteresis TTL — 0.3 — — V CMOS Vihcmos SR P Input high level CMOS — 0.65 * VDD — VDD_HV_IO + 0.3 V Vilcmos SR P Input low level CMOS — –0.3 — 0.35 * VDD V Vhyscmos CC C Input hysteresis CMOS — 0.10 * VDD — — V COMMON ILKG CC P Pad input leakage INPUT-ONLY pads TJ = 150 °C — — 200 nA ILKG CC P Pad input leakage MEDIUM pads TJ = 150 °C — — 360 nA ILKG CC P Pad input leakage STRONG pads TJ = 150 °C — — 1,000 nA 32/147 DS12304 Rev 5 SPC58EHx, SPC58NHx Electrical characteristics Table 10. I/O input electrical characteristics (continued) Value Symbol C Parameter Conditions Unit Min Typ Max ILKG CC P Pad input leakage VERY STRONG pads, TJ = 150 °C — — 1,000 nA ILKG CC P Pad input leakage ULTRA STRONG pads, TJ = 150 °C — — 1,000 nA CP1 CC D Pad capacitance — — — 10 pF Vdrift CC D Input Vil/Vih temperature drift In a 1 ms period, with a temperature variation 3 V TJ < 150 °C, VDD_HV_ADV > 3 V, V DD_HV_ADR_S > 3 V Total unadjusted error in 12-bit TJ < 150 °C, configuration(7) > 3 V, V Unit Min Max –4 4 –6 6 LSB –6 6 D High frequency mode, TJ < 150 °C, VDD_HV_ADV > 3 V, VDD_HV_ADR_S > 3 V –12 12 D Mode 1, TJ < 150 °C, VDD_HV_ADV > 3 V VDD_HV_ADR_S > 3 V –1.5 1.5 –2.0 2.0 DD_HV_ADV (12b) 3 V > VDD_HV_ADR_S > 2 V D TUE10 CC C C 58/147 Mode 1, TJ < 150 °C, VDD_HV_ADV > 3 V, Total unadjusted error 3 V > V DD_HV_ADR_S > 2 V in 10-bit Mode 2, TJ < 150 °C, configuration(7) VDD_HV_ADV > 3 V VDD_HV_ADR_S > 3 V Mode 3, TJ < 150 °C, VDD_HV_ADV > 3 V VDD_HV_ADR_S > 3 V DS12304 Rev 5 LSB (10b) –3.0 3.0 –4.0 4.0 SPC58EHx, SPC58NHx Electrical characteristics Table 27. SARn ADC electrical specification (continued) Value Symbol ΔTUE12 TUEINJ2 C CC CC D T Parameter TUE degradation addition, due to current injection in IINJ2 range.(8) Differential nonlinearity CC T Unit Min Max VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [0:25 mV] –1 1 VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [25:50 mV] –2 2 VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [50:75 mV] –4 4 VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [75:100 mV] –6 6 –2.5 2.5 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [25:50 mV] –4 4 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [50:75 mV] –7 7 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [75:100 mV] –12 12 TUE degradation due V DD_HV_ADV < VIN < to VDD_HV_ADR offset V DD_HV_ADR with respect to VDD_HV_ADR − VDD_HV_ADV VDD_HV_ADV ∈ [0:25 mV] P DNL(9) Conditions See Operating Conditions chapter Table 5, IINJ2 parameter. +8 Standard frequency mode, VDD_HV_ADV > 4 V VDD_HV_ADR_S > 4 V –1 High frequency mode, VDD_HV_ADV > 4 V VDD_HV_ADR_S > 4 V –1 LSB (12b) LSB 2 LSB (12b) 2 1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within the sampling window. Refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration. 2. Mode1: 6 sampling cycles + 10 conversion cycles at 13.33 MHz. 3. Mode2: 5 sampling cycles + 10 conversion cycles at 13.33 MHz. DS12304 Rev 5 59/147 63 Electrical characteristics SPC58EHx, SPC58NHx 4. Mode3: 6 sampling cycles + 10 conversion cycles at 16 MHz. 5. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven by the transfer of charge between internal capacitances during the conversion. 6. Current parameter values are for a single ADC. 7. TUE is granted with injection current within the range defined in Table 26, for parameters classified as T and D. 8. All channels of all SAR-ADC12bit and SAR-ADC10bit are impacted with same degradation, independently from the ADC and the channel subject to current injection. 9. DNL is granted with injection current within the range defined in Table 26, for parameters classified as T and D. 4.12.3 SAR ADC 10 bit electrical specification The ADC comparators are 10-bit Successive Approximation Register analog-to-digital converters with full capacitive DAC. The SARn architecture allows input channel multiplexing. Note: The functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maximum may affect device reliability or cause permanent damage to the device. Table 28. ADC-Comparator electrical specification Value Symbol C P Parameter Conditions SR tADCINIT SR — ADC initialization time tADCBIASINIT SR — ADC BIAS initialization time tADCINITSBY SR — ADC initialization time in standby tADCPRECH SR T ADC precharge time ΔVPRECH SR D Precharge voltage precision tADCSAMPLE tADCEVAL IADCREFH(3),(4) 60/147 SR SR CC T Clock frequency P ADC sample time P D T Max 7.5 13.33 >13.33 16.0 — 1.5 — µs — 5 — µs 8 — µs 1/fADCK — µs 0 0.25 V 5/fADCK(2) — µs 10-bit ADC mode, Standard channel 6/fADCK — µs 10-bit ADC mode 10/fADCK — ADC comparator mode 2/fADCK — Run mode (average across all codes) — 7 Power Down mode — 1 ADC comparator mode — 19.5 Standard frequency mode fADCK High frequency mode — 10-bit ADC mode, Fast channel ADC evaluation time ADC high reference current Standby Mode TJ < 150 °C (1) Unit Min DS12304 Rev 5 MHz µs µA SPC58EHx, SPC58NHx Electrical characteristics Table 28. ADC-Comparator electrical specification (continued) Value Symbol IADCREFL(5) IADV_S(5) TUE10 C CC CC Parameter Conditions Unit Min Max Run mode VDD_HV_ADR_S ≤ 5.5 V — 15 Power Down mode VDD_HV_ADR_S ≤ 5.5 V — 1 ADC comparator mode — 20.5 Run mode — 4 Power Down mode — 0.04 T TJ < 150 °C, VDD_HV_ADV > 3 V, VDD_HV_ADR_S > 3 V –2 2 P TJ < 150 °C, VDD_HV_ADV > 3 V, VDD_HV_ADR_S > 3 V –3 3 D ADC low reference current P V DD_HV_ADV power D supply current CC T D Total unadjusted error in 10-bit configuration(6) TJ < 150 °C, VDD_HV_ADV > 3 V, 3 V > VDD_HV_ADR_S > 2 V High frequency mode, TJ < 150 °C, VDD_HV_ADV > 3 V, VDD_HV_ADR_S > 3 V DS12304 Rev 5 µA mA LSB –3 3 –3 3 (10b) 61/147 63 Electrical characteristics SPC58EHx, SPC58NHx Table 28. ADC-Comparator electrical specification (continued) Value Symbol ΔTUE10 TUEINJ2 C CC CC Conditions TUE degradation due to VDD_HV_ADR offset D with respect to VDD_HV_ADV T P DNL(7) Parameter CC T Unit Min Max VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [0:25 mV] –1.0 1.0 VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [25:50 mV] –2.0 2.0 VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [50:75 mV] –3.5 3.5 VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [75:100 mV] –6.0 6.0 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [0:25 mV] –2.5 2.5 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [25:50 mV] –4.0 4.0 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [50:75 mV] –7.0 7.0 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [75:100 mV] –12.0 12.0 TUE degradation See Operating Conditions addition, due to current chapter Table 5, IINJ2 injection in IINJ2 parameter. (5) range. Standard frequency mode, VDD_HV_ADV > 4 V Differential non-linearity VDD_HV_ADR_S > 4 V std. mode High frequency mode, VDD_HV_ADV > 4 V VDD_HV_ADR_S > 4 V 3 –1 LSB (10b) LSB 2 LSB (10b) –1 2 1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within the sampling window. Refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration. 2. In case the ADC is used as Fast Comparator the sampling time is tADCSAMPLE = 2/fADCK. 3. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven by the transfer of charge between internal capacitances during the conversion. 62/147 DS12304 Rev 5 SPC58EHx, SPC58NHx Electrical characteristics 4. Current parameter values are for a single ADC. 5. All channels of all SAR-ADC12bit and SAR-ADC10bit are impacted with same degradation, independently from the ADC and the channel subject to current injection. 6. TUE is granted with injection current within the range defined in Table 26, for parameters classified as T and D. 7. DNL is granted with injection current within the range defined in Table 26, for parameters classified as T and D. DS12304 Rev 5 63/147 63 Electrical characteristics 4.13 SPC58EHx, SPC58NHx Temperature Sensor The following table describes the temperature sensor electrical characteristics. Table 29. Temperature sensor electrical characteristics Value Symbol C Parameter Conditions Unit Min Typ Max — CC — Temperature monitoring range — –40 — 150 °C TSENS CC T Sensitivity — — 5.18 — mV/°C TACC CC P Accuracy TJ < 150 C –3 — 3 °C 64/147 DS12304 Rev 5 SPC58EHx, SPC58NHx 4.14 Electrical characteristics Power management The power management module monitors the different power supplies as well as it generates the required internal supplies. The device can operate in the following configurations: Table 30. Power management regulators Device External regulator(1) Internal SMPS regulator SPC58EHx SPC58NHx X — Internal linear regulator external ballast Internal linear regulator internal ballast X — Clamp Auxiliary regulator(2) regulator(2) X Internal standby regulator(3) X X 1. The application can select between the internal or external regulator mode, by controlling the EXTREG_SEL pin of the device. If EXTREG_SEL is connected to VDD_HV_IO_MAIN, the external regulator mode is selected. 2. In external regulator mode, the auxiliary and clamp regulators can be optionally enabled, to support the compensation of overshoots and undershoots in the supply. In internal regulator mode, the auxiliary and clamp regulators are always active. 3. Standby regulator is automatically activated when the device enters standby mode. 4.14.1 Power management integration Use the integration schemes provided below to ensure the proper device function, according to the selected regulator configuration. The internal regulators are supplied by VDD_HV_IO_MAIN supply and are used to generate VDD_LV supply. Place capacitances on the board as near as possible to the associated pins and limit the serial inductance of the board to less than 5 nH. It is recommended to use the internal regulators only to supply the device itself. DS12304 Rev 5 65/147 74 Electrical characteristics SPC58EHx, SPC58NHx Figure 9. External regulator mode &)/$ 9''B+9B,2 9''B+9B,2 9''B+9B)/$ (;75(*B6(/ %&75/ &( 966 &%9 ([WHUQDO 5HJXODWRU 9''B+9B,2 &+9Q 9''B/9 966 $X[5HJ &/9Q 966 &ODPS5HJ 966B+9B$'9 9''B+9B$'9 &$'& 66/147 DS12304 Rev 5 SPC58EHx, SPC58NHx Electrical characteristics Figure 10. Internal regulator with external ballast mode &)/$ 966 &( 966 %&75/ (;75(*B6(/ &% 9''B+9B,2 4(;7 &%9 9''B+9B)/$ 9''B+9 9''B+9B,2 &+9Q 0DLQ5HJ 966 9''B/9 $X[5HJ &/9Q 966 &ODPS5HJ 966B+9B$'9 9''B+9B$'9 &$'& DS12304 Rev 5 67/147 74 Electrical characteristics SPC58EHx, SPC58NHx Figure 11. Standby regulator with external ballast mode &)/$ 966 9''B+9 &%9 &( 966 9''B+9B,2 (;75(*B6(/ %&75/ &% 9''B+9B)/$ 4(;7 9''B+9B,2 &+9Q 6WDQGE\UHJ 966 9''B/9 &/9Q 966 966B+9B$'9 9''B+9B$'9 &$'& Table 31. External components integration Symbol C Value Conditions(1) Parameter Unit Min Typ Max — 2× 2.2 — µF Total resistance including board track — — 50 mΩ Each VDD_LV/VSS pair — 47 — nF Common Components CE SR D Internal voltage regulator stability external capacitance.(2) (3) RE SR D Stability capacitor equivalent serial resistance CLVn SR Internal voltage regulator D decoupling external capacitance(2) (4) (5) RLVn SR D Stability capacitor equivalent serial resistance — — — 50 mΩ CBV SR D Bulk capacitance for HV supply(2) on one VDD_HV_IO_MAIN/ VSS pair — 4.7 — µF CHVn SR D on all VDD_HV_IO/VSS and VDD_HV_ADR/VSS pairs — 100 — nF 68/147 Decoupling capacitance for ballast and IOs(2) DS12304 Rev 5 SPC58EHx, SPC58NHx Electrical characteristics Table 31. External components integration (continued) Symbol C Value Conditions(1) Parameter CFLA SR D Decoupling capacitance for Flash supply(6) CADC SR D ADC supply external capacitance(2) Unit Min Typ Max — — 10 — nF VDD_HV_ADV/VSS_HV_ADV pair. — 2.2 — µF 2.0 — HV_IO Internal Linear Regulator with External Ballast Mode QEXT SR D Recommended external NPN transistors VQ SR D External NPN transistor collector voltage — NJD2873T4, BCP68 VDD_ V _MAIN CB SR Internal voltage regulator stability D external capacitance on ballast base(4) (7) — — 2.2 — µF RB SR D Stability capacitor equivalent serial resistance Total resistance including board track — — 50 mΩ 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TJ = –40 / 150 °C, unless otherwise specified. 2. Recommended X7R or X5R ceramic –50% / +35% variation across process, temperature, voltage and after aging. 3. CE capacitance is required both in internal and external regulator mode. 4. For noise filtering, add a high frequency bypass capacitance of 10 nF. 5. For applications it is recommended to implement at least 5 CLV capacitances. 6. Recommended X7R capacitors. For noise filtering, add a high frequency bypass capacitance of 100 nF. 7. CB capacitance is required if only the external ballast is implemented. DS12304 Rev 5 69/147 74 Electrical characteristics 4.14.2 SPC58EHx, SPC58NHx Voltage regulators Table 32. Linear regulator specifications Value Symbol C Parameter Conditions CC P Main regulator output voltage VMREG CC P Unit Min Typ Max Power-up, before trimming, no load 1.12 1.20 1.28 After trimming, maximum load 1.08 1.18 1.23 — — 700 mA — — 400 mA -200 — 200 mA IMREG = max — — 22 IMREG = 0 mA — — V Main regulator current provided to VDD_LV domain The maximum current required by T the device (IDD_LV) may exceed the maximum current which can be provided by the internal linear regulator. In this case, the internal regulator mode cannot be used. IDDMREG CC IDDCLAMP Main regulator rush current sinked from VDD_HV_IO_MAIN CC D domain during VDD_LV domain loading ΔIDDMREG CC T IMREGINT CC D Main regulator current D consumption Main regulator output current variation — Power-up condition 20 µs observation window mA Table 33. Auxiliary regulator specifications Value Symbol C Parameter Conditions CC P CC P IDDAUX CC T ΔIDDAUX CC T Aux regulator current variation IAUXINT CC D Aux regulator current D consumption Aux regulator output voltage VAUX 70/147 Unit Min Typ Max After trimming, internal regulator mode 1.08 1.18 1.21 After trimming, external regulator mode 1.03 1.12 1.16 — — — 250 mA 100 — 100 mA IMREG = max — — 1.1 IMREG = 0 mA — — 1.1 Aux regulator current provided to VDD_LV domain 20 µs observation window DS12304 Rev 5 V mA SPC58EHx, SPC58NHx Electrical characteristics Table 34. Clamp regulator specifications Value Symbol C Parameter Conditions CC P Clamp regulator output voltage VCLAMP CC P ΔIDDCLAMP CC T Clamp regulator current variation ICLAMPINT CC D Clamp regulator current consumption Unit Min Typ Max After trimming, internal regulator mode 1.17 1.21 1.32 After trimming, external regulator mode 1.24 1.28 1.39 20 µs observation window 100 — 100 mA — — 0.7 mA IMREG = 0 mA V Table 35. Standby regulator specifications Value Symbol VSBY IDDSBY 4.14.3 C Parameter Conditions CC P Standby regulator output voltage CC T Standby regulator current provided to VDD_LV domain After trimming, maximum load — Unit Min Typ Max 1.02 1.06 1.26 V — — 50 mA Voltage monitors The monitors and their associated levels for the device are given in Table 36. Figure 12 illustrates the workings of voltage monitoring threshold. DS12304 Rev 5 71/147 74 Electrical characteristics SPC58EHx, SPC58NHx Figure 12. Voltage monitor threshold definition VDD_xxx VHVD VLVD TVMFILTER TVMFILTER HVD TRIGGER (INTERNAL) TVMFILTER TVMFILTER LVD TRIGGER (INTERNAL) Table 36. Voltage monitor electrical characteristics Symbol C Supply/Parameter(1) Value(2) Conditions Unit Min Typ Max 1.80 2.18 2.40 V PowerOn Reset HV VPOR200_C CC P VDD_HV_IO_MAIN — Minimum Voltage Detectors HV VMVD270_C CC P VDD_HV_IO_MAIN — 2.71 2.76 2.80 V VMVD270_F CC P VDD_HV_FLA — 2.71 2.76 2.80 V CC P VDD_HV_IO_MAIN (in Standby) — 2.71 2.76 2.80 V VMVD270_SBY Low Voltage Detectors HV VLVD290_C CC P VDD_HV_IO_MAIN — 2.89 2.94 2.99 V VLVD290_F CC P VDD_HV_FLA — 2.89 2.94 2.99 V VLVD290_IE CC P VDD_HV_EMMC — 2.89 2.94 2.99 V VLVD290_AS CC P VDD_HV_ADV (ADCSAR pad) — 2.89 2.94 2.99 V VLVD290_IE1 CC P VDD_HV_IO_ETH1 — 2.89 2.94 2.99 V 72/147 DS12304 Rev 5 SPC58EHx, SPC58NHx Electrical characteristics Table 36. Voltage monitor electrical characteristics (continued) Symbol C Supply/Parameter(1) Value(2) Conditions Unit Min Typ Max VLVD290_IE0 CC P VDD_HV_IO_ETH0 — 2.89 2.94 2.99 V VLVD400_IE CC P VDD_HV_EMMC — 4.15 4.23 4.31 V VLVD400_AS CC P VDD_HV_ADV (ADCSAR pad) — 4.15 4.23 4.31 V VLVD400_IM CC P VDD_HV_IO_MAIN — 4.15 4.23 4.31 V VLVD400_IE1 CC P VDD_HV_IO_ETH1 4.15 4.23 4.31 V VLVD400_IE0 CC P VDD_HV_IO_ETH0 4.15 4.23 4.31 V — High Voltage Detectors HV VHVD400_C CC P VDD_HV_IO_MAIN 3.68 3.75 3.82 V VHVD400_IE1 CC P VDD_HV_IO_ETH1 3.68 3.75 3.82 V VHVD400_IE0 CC P VDD_HV_IO_ETH0 3.68 3.75 3.82 V 5.72 5.82 5.92 V — Upper Voltage Detectors HV VUVD600_C CC P VDD_HV_IO_MAIN VUVD600_F CC P VDD_HV_FLA — 5.72 5.82 5.92 V VUVD600_IE1 CC P VDD_HV_IO_ETH1 — 5.72 5.82 5.92 V VUVD600_IE0 CC P VDD_HV_IO_ETH0 — 5.72 5.82 5.92 V — 0.29 0.60 0.97 V PowerOn Reset LV VPOR031_C CC P VDD_LV Minimum Voltage Detectors LV VMVD082_C CC P VDD_LV — 0.85 0.88 0.91 V VMVD094_C CC P VDD_LV — 0.98 1.00 1.02 V VMVD094_FA CC P VDD_LV (Flash) — 1.00 1.02 1.04 V VMVD094_FB CC P VDD_LV (Flash) — 1.00 1.02 1.04 V Low Voltage Detectors LV VLVD100_C CC P VDD_LV — 1.06 1.08 1.11 V VLVD100_SB CC P VDD_LV (In Standby) — 0.99 1.01 1.03 V VLVD100_F CC P VDD_LV (Flash) — 1.08 1.10 1.12 V 1.28 1.31 1.33 V High Voltage Detectors LV VHVD134_C CC P VDD_LV — Upper Voltage Detectors LV VUVD140_C CC P VDD_LV — 1.34 1.37 1.39 V VUVD140_F CC P VDD_LV (Flash) — 1.34 1.37 1.39 V — 5 — 30 μs Common TVMFILTER CC D Voltage monitor filter(3) DS12304 Rev 5 73/147 74 Electrical characteristics SPC58EHx, SPC58NHx 1. Even if LVD/HVD monitor reaction is configurable, the application ensures that the device remains in the operative condition range, and the internal LVDx monitors are disabled by the application. Then an external voltage monitor with minimum threshold of VDD_LV(min) = 1.08 V measured at the device pad, has to be implemented. For HVDx, if the application disables them, then they need to grant that VDD_LV and VDD_HV voltage levels stay withing the limitations provided in Section 4.2: Absolute maximum ratings. 2. The values reported are Trimmed values, where applicable. 3. See Figure 12. Transitions shorter than minimum are filtered. Transitions longer than maximum are not filtered, and will be delayed by TVMFILTER time. Transitions between minimum and maximum can be filtered or not filtered, according to temperature, process and voltage variations. 74/147 DS12304 Rev 5 SPC58EHx, SPC58NHx 4.15 Electrical characteristics Flash memory The following table shows the Wait State configuration. Table 37. Wait State configuration APC 000 (1) 100(2) 001 (3) RWSC Frequency range (MHz) 0 f < 30 1 f < 60 2 f < 90 3 f < 120 4 f < 150 5 f < 180 6 f < 200 0 f < 30 1 f < 60 2 f < 90 3 f < 120 4 f < 150 5 f < 180 6 f < 200 2 55