SPEAr300
Embedded MPU with ARM926 core, flexible memory support,
powerful connectivity features and human machine interface
Features
■
ARM926EJ-S core up to 333 MHz
■
High-performance 8-channel DMA
■
Dynamic power-saving features
■
Configurable peripheral functions on 102
shared I/Os (please refer to Table 11:
PL_GPIO multiplexing scheme)
■
■
■
■
Memory
– 32 KB ROM and 56 KB internal SRAM
– LPDDR-333/DDR2-666 external memory
interface (up to 1 GB addressable memory)
– SDIO/MMC card interface
– Serial Flash memory interface (SMI)
– Flexible static memory controller (FSMC)
up to 16-bit data bus width, supporting
external SRAM, NAND/NOR Flash and
FPGAs
– Serial SPI Flash interface
Connectivity
– 2 x USB 2.0 Host
– USB 2.0 Device
– Fast Ethernet (MII port)
– 1x SSP Synchronous serial peripheral
(SPI, Microwire or TI protocol)
– 1x I2C
– 1x I2S,
– 1x fast IrDA interface
– 1x UART interface
– TDM bus (512 timeslots)
– Up to 8 additional I2C/SPI chip selects
Security
– C3 cryptographic accelerator
– Touchscreen support (using the ADC)
– 9 x 9 keyboard controller
– Glueless management of up to 8
SLICs/CODECs
■
Miscellaneous functions
– Integrated real time clock, watchdog, and
system controller
– 8-channel 10-bit ADC, 1 Msps
– 1-bit DAC
– JPEG codec accelerator
– Six 16-bit general purpose timers with
capture mode and programmable prescaler
– Up to 62 GPIOs
Applications
■
SPEAr300 embedded MPU is configurable in
13 sets of peripheral functions targeting a
range of applications:
– General purpose NAND Flash or NOR
Flash based devices
– Digital photo frames
– WiFi or IP phones (low end or high end)
– ATA PABX systems (with or without I2S)
– 8-bit or 14-bit camera (with or without LCD)
Table 1.
Peripherals supported
– Camera interface (ITU-601/656 and CSI2
support)
– TFT/STN LCD controller (resolution up to
1024 x 768 and up to 24 bpp)
April 2010
LFBGA289 (15 x 15 x 1.7 mm)
Order code
Device summary
Temp
range, C
Package
LFBGA289
SPEAR300-2 - 40 to 85 °C (15x15 mm)
pitch 0.8 mm
Doc ID 16324 Rev 2
Packing
Tray
1/83
www.st.com
1
Contents
SPEAr300
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1
2
2/83
Main features: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
ARM926EJ-S CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2
System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1
Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2
Power saving system mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3
Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4
General purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6
RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7
Multichannel DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8
Embedded memory units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9
Mobile DDR/DDR2 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.10
Serial memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.11
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 17
2.12
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.13
Fast IrDA controller (FIrDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.14
Synchronous serial port (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.15
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.16
SPI_I2C multiple slave control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.17
TDM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.18
I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.19
GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.20
Keyboard controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.21
CLCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.22
Camera interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.23
SDIO controller/MMC card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.24
Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.25
USB2 host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Contents
2.26
USB2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.27
JPEG (CODEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.28
Cryptographic co-processor (C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.29
8-channel ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.30
1-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1
Required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2
Dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3
Shared I/O pins (PL_GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4
3.3.1
PL_GPIO pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3.2
Configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3.3
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3.4
Boot pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3.5
GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3.6
Multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PL_GPIO pin sharing for debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6
5.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2
Maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.4
Overshoot and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.5
3.3V I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.6
LPDDR and DDR2 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.7
Power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.8
Removing power supplies for power saving . . . . . . . . . . . . . . . . . . . . . . . 55
5.9
Power on reset (MRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1
DDR2 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.1
DDR2 read cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.2
DDR2 write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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Contents
SPEAr300
6.1.3
6.2
DDR2 command timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
CLCD timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.2.1
CLCD timing characteristics direct clock . . . . . . . . . . . . . . . . . . . . . . . . 60
6.2.2
CLCD timing characteristics divided clock . . . . . . . . . . . . . . . . . . . . . . . 61
6.3
I2C
6.4
FSMC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.5
timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.4.1
8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.4.2
16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Ether MAC 10/100 Mbps timing characteristics . . . . . . . . . . . . . . . . . . . . 69
6.5.1
MII transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.5.2
MII receive timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.5.3
MDIO timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.6
SMI - Serial memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.7
SSP timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.8
6.7.1
SPI master mode timings (clock phase = 0) . . . . . . . . . . . . . . . . . . . . . 76
6.7.2
SPI master mode timings (clock phase = 1) . . . . . . . . . . . . . . . . . . . . . 77
UART (Universal asynchronous receiver/transmitter) . . . . . . . . . . . . . . . 78
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4/83
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SPEAr300
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Master clock, RTC, Reset and 3.3 V comparator pin descriptions . . . . . . . . . . . . . . . . . . 29
Power supply pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Debug pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Serial memory interface (SMI) pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
USB pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ADC pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DDR pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PL_GPIO pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Available peripherals in each configuration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PL_GPIO multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table shading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Ball sharing during debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Overshoot and undershoot specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Low voltage TTL DC input specification (3 V< VDD SDAL
7.4081
12.0530
ns
Those values are referred to the common internal source clock which has a period of:
tHCLK = 6 ns.
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SPEAr300
Timing requirements
Figure 19. Output signal waveforms for I2C signals
The timing of high and low level of SCL (tSCLHigh and tSCLLow) are programmable.
Table 32.
Table 33.
Table 34.
Time characteristics for I2C in high-speed mode
Parameter
Min
tSU-STA
157.5897
tHD-STA
325.9344
tSU-DAT
314.0537
tHD-DAT
0.7812
tSU-STO
637.709
tHD-STO
4742.1628
Unit
ns
Time characteristics for I2C in fast speed mode
Parameter
Min
tSU-STA
637.5897
tHD-STA
602.169
tSU-DAT
1286.0537
tHD-DAT
0.7812
tSU-STO
637.709
tHD-STO
4742.1628
Unit
ns
Time characteristics for I2C in standard speed mode
Parameter
Min
tSU-STA
4723.5897
tHD-STA
3991.9344
tSU-DAT
4676.0537
tHD-DAT
0.7812
tSU-STO
4027.709
tHD-STO
4742.1628
Unit
ns
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Timing requirements
Note:
1
SPEAr300
The timings shown in Figure 19 depend on the programmed value of TSCLHigh and TSCLLow,
so the values present in the three tables here above have been calculated using the
minimum programmable values of :
IC_HS_SCL_HCNT=19 and IC_HS_SCL_LCNT=53 registers (for High-Speed mode);
IC_FS_SCL_HCNT=99 and IC_FS_SCL_LCNT=215 registers (for Fast-Speed mode);
IC_SS_SCL_HCNT=664 and IC_SS_SCL_LCNT=780 registers (for Standard-Speed
mode).
Note:
1
These minimum values depend on the AHB clock (HCLK) frequency, which is 166 MHz.
2
A device may internally require a hold time of at least 300 ns for the SDA signal (referred to
the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL
(Please refer to the I2C Bus Specification v3-0 Jun 2007). However, the SDA data hold time
in the I2C controller of SPEAr300 is one-clock cycle based (6 ns with the HCLK clock at 166
MHz). This time may be insufficient for some slave devices. A few slave devices may not
receive the valid address due to the lack of SDA hold time and will not acknowledge even if
the address is valid. If the SDA data hold time is insufficient, an error may occur.
3
Workaround: If a device needs more SDA data hold time than one clock cycle, an RC delay
circuit is needed on the SDA line as illustrated in the following figure:
Figure 20. RC delay circuit
For example, R= K and C = 200 pF.
6.4
FSMC timing characteristics
The characterization timing is done considering an output load of 3 pF on the data, 15 pF on
NF_CE, NF_RE and NF_WE and 10 pF on NF_ALE and NF_CLE.
The operating conditions are V= 0.90 V, T=125 °C in worst case and V=1.10 V, T= 40 °C in
best case.
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6.4.1
Timing requirements
8-bit NAND Flash configuration
Figure 21. Output pads for 8-bit NAND Flash configuration
D
HCLK
SET
CLR
Q
Q
...
...
...
D
SET
CLR
Q
NFCLE
NFCE
NFWE
NFRE
NFRWPRT
NFALE
NFIO_0..7
Q
Figure 22. Input pads for 8-bit NAND Flash configuration
D
NFRB
HCLK
NFIO_0..7
CLPOWER
CLLP
CLLE
(NFIO_8..15)
CLFP
CLCP
CLAC
CLD_23..22
SET
CLR
D
SET
CLR
Q
Q
Q
Q
Figure 23. Output command signal waveforms for 8-bit NAND Flash configuration
NFCE
TCLE
NFCLE
TWE
NFWE
TIO
NFIO
Command
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Timing requirements
SPEAr300
Figure 24. Output address signal waveforms for 8-bit NAND Flash configuration
NFCE
TALE
NFALE
TWE
NFWE
TIO
NFIO
Address
Figure 25. In/out data address signal waveforms for 8-bit NAND Flash configuration
NFCE
TWE
NFWE
TIO
NFIO (out)
Data Out
TRE
TREAD
NFRE
TRE -> IO TNFIO -> FFs
NFIO (in)
Table 35.
Time characteristics for 8-bit NAND Flash configuration
Parameter
Note:
66/83
Min
Max
TCLE
-16.85 ns
-19.38 ns
TALE
-16.84 ns
-19.37 ns
TWE (s=1)
11.10 ns
13.04 ns
TRE (s=1)
11.18 ns
13.05 ns
TIO (h=1)
3.43 ns
8.86 ns
Values in Table 35 are referred to the common internal source clock which has a period of
THCLK = 6 ns.
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6.4.2
Timing requirements
16-bit NAND Flash configuration
Figure 26. Output pads for 16-bit NAND Flash configuration
D
HCLK
SET
CLR
NFCLE
NFCE
NFWE
NFRE
NFRWPRT
NFALE
NFIO_0..7
Q
Q
...
...
...
D
SET
CLR
Q
Q
CLPOWER
CLLP
CLLE
CLFP
CLCP
CLAC
CLD_23..22
(NFIO_8..15)
Figure 27. Input pads for 16-bit NAND Flash configuration
D
NFRB
NFIO_0..7
HCLK
SET
CLR
Q
Q
CLPOWER
CLLP
CLLE
CLFP
(NFIO_8..15)
...
...
CLCP
CLAC
D
CLD_23..22
SET
CLR
Q
Q
Figure 28. Output command signal waveforms 16-bit NAND Flash configuration
NFCE
TCLE
NFCLE
TWE
NFWE
TIO
NFIO
Command
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Timing requirements
SPEAr300
Figure 29. Output address signal waveforms 16-bit NAND Flash configuration
NFCE
TALE
NFALE
TWE
NFWE
TIO
NFIO
Address
Figure 30. In/out data signal waveforms for 16-bit NAND Flash configuration
NFCE
TWE
NFWE
TIO
NFIO (out)
Data Out
TRE
TREAD
NFRE
TRE -> IO TNFIO -> FFs
NFIO (in)
Table 36.
Time characteristics for 16-bit NAND Flash configuration
Parameter
Note:
68/83
Min
Max
TCLE
-16.85 ns
-19.38 ns
TALE
-16.84 ns
-19.37 ns
TWE (s=1)
11.10 ns
13.04 ns
TRE (s=1)
11.18 ns
13.05 ns
TIO (h=1)
3.27 ns
11.35 ns
Values in Table 36 are referred to the common internal source clock which has a period of
THCLK = 6 ns.
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SPEAr300
6.5
Timing requirements
Ether MAC 10/100 Mbps timing characteristics
The characterization timing is given for an output load of 5 pF on the MII TX clock and 10 pF
on the other pads. The operating conditions are in worst case V=0.90 V T=125° C and in
best case V=1.10 V T= 40° C.
6.5.1
MII transmit timing specifications
Figure 31. MII TX waveforms
MIITX_CLK
Tmax
Tclock
Tmin
MII_TXD0-MII_TXD3,
MII_TXEN, MII_TXER
Tf
Tr
Figure 32. Block diagram of MII TX pins
MII_TX[0..3],
MII_TXEN, MII_TXER
D
SET
Q
t2
CLK
CLR
Q
MII_TXCLK
t3
Table 37.
MII TX timings
Value using MII 10 Mb [tCLK
period = 40 ns 25 MHz]
Value using MII 100 Mb [tCLK
period = 400 ns 2.5 MHz]
tmax= t2max- t3min
6.8 ns
6.8 ns
tmin= t2min- t3max
2.9 ns
2.9 ns
tSETUP
33.2 ns
393.2 ns
Parameter
Note:
MII_TX[0..3],
MII_TXEN, MII_TXER
To calculate the tSETUP value for the PHY you have to consider the next tCLK rising edge, so
you have to apply the following formula: tSETUP = tCLK - tmax
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Timing requirements
6.5.2
SPEAr300
MII receive timing specifications
Figure 33. MII RX waveforms
MII_RXCLK
Tclock
Ts
MII_RXD0-MII_RXD3,
MII_RXER, MII_RXDV
Th
Tf
Tr
Figure 34. Block diagram of MII RX pins
t2
MII_RX[0..3],
MII_RXER, MII_RXDV
D
SET
Q
t1
CLR
MII_RXCLK
6.5.3
MDIO timing specifications
Figure 35. MDC waveforms
MDC
Tclock
MDIO
Input
Tf
Output
70/83
Tsetup Thold
Tmax
Tmi n
Doc ID 16324 Rev 2
Tr
Q
SPEAr300
Timing requirements
Figure 36. Paths from MDC/MDIO pads
Q
INPUT
Q
SET
t1
D
CL R
OUTPUT
CLK
D
SET
Q
t2
CL R
MDC
t3
Table 38.
MDIO
Q
MDC/MDIO timing
Parameter
Value
Frequency
tCLK period
614.4 ns
1.63 MHz
tCLK fall (tf)
1.18 ns
tCLK rise (tr)
1.14 ns
Output
tmax = ~tCLK /2
307 ns
tmin = ~tCLK /2
307 ns
Input
Note:
tSETUPmax = t1max - t3min
6.88 ns
tHOLDmin = t1min - t3max
-1.54 ns
When MDIO is used as output the data are launched on the falling edge of the clock as
shown in Figure 35.
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Timing requirements
6.6
SPEAr300
SMI - Serial memory interface
Figure 37. SMIDATAIN data path
tinput_delay
tD
tH
SMI_DATAIN
SMI_CLK_i
tS
tCD
SMI_CLK
HCLK
tSMIDATAIN arrival
Table 39.
SMIDATAIN timings
Signal
SMI_DATAIN
Parameter
Value
td_max
tSMIDATAIN_arrival_max - tinput_delay
td_min
tSMIDATAIN_arrival_min - tinput_delay
tcd_min
tSMI_CLK_i_arrival_min
tcd_max
tSMI_CLK_i_arrival_max
tSETUP_max
ts + td_max-tcd_min
tHOLD_min
th - td_min + tcd_max
Figure 38. SMIDATAOUT/SMICSn data paths
OUTPUT
HCLK
SMICLK
HCLK
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SPEAr300
Timing requirements
Figure 39. SMIDATAOUT timings
SMI_CLK
SMIDATAOUT(FAST)
SMIDATAOUT(SLOW)
tdelay_min
tdelay_max
tarrival
Table 40.
SMIDATAIN timings
Signal
SMI_DATAOUT
Parameter
Value
tdelay_max
tarrivalSMIDATAOUT_max - tarrival_SMI_CLK_min
tdelay_min
tarrivalSMIDATAOUT_min - tarrival_SMI_CLK_max
Figure 40. SMICSn fall timings
Table 41.
SMICSn fall timings
Signal
SMI_CSn fall
Parameter
Value
tdelay_max
tarrivalSMICSn_max_fall - tarrival_SMI_CLK_min_fall
tdelay_min
tarrivalSMICSn_min_fall - tarrival_SMI_CLK_max_fall
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Timing requirements
SPEAr300
Figure 41. SMICSn rise timings
Table 42.
SMICSn rise timings
Signal
SMI_CSn rise
Table 43.
Parameter
Value
tdelay_max
tarrivalSMICSn_max_rise - tarrival_SMI_CLK_min_fall
tdelay_min
tarrivalSMICSn_min_rise - tarrival_SMI_CLK_max_fall
Timing requirements for SMI
Input setup-hold/output delay
Parameter
Max
Min
Fall time
1.82
1.40
Rise time
1.63
1.19
Input setup time
8.27
Input hold time
-2.59
Unit
SMI_CLK
SMIDATAIN
SMIDATAOUT Output valid time
SMICS_0 Output
valid time
SMICS_1Output
valid time
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2.03
fall
1.92
rise
1.69
fall
1.78
rise
1.63
Doc ID 16324 Rev 2
ns
SPEAr300
6.7
Timing requirements
SSP timing characteristics
This module provides a programmable length shift register which allows serial
communication with other SSP devices through a 3 or 4 wire interface (SSP_CLK,
SSP_MISO, SSP_MOSI and SSP_CSn). The SSP supports the following features:
Note:
●
Master/Slave mode operations
●
Chip-selects for interfacing to multiple slave SPI devices.
●
3 or 4 wire interface (SSP_SCK, SSP_MISO, SSP_MOSI and SSP_CSn)
●
Single interrupt
●
Separate DMA events for SPI Receive and Transmit
●
16-bit shift register
●
Receive buffer register
●
Programmable character length (2 to 16 bits)
●
Programmable SSP clock frequency range
●
8-bit clock pre-scaler
●
Programmable clock phase (delay or no delay)
●
Programmable clock polarity
The following tables and figures show the characterization of the SSP using the SPI
protocol.
Table 44.
Timing requirements for SSP (all modes)
No.
Parameters
Value
Unit
24
ns
1
Tc(CLK)
2
Tw(CLKH)
Pulse duration, SSP_CLK high
0.49T - 0.51T
ns
3
Tw(CLKL)
Pulse duration, SSP_CLK low
0.51T - 0.49T
ns
Cycle time, SSP_CLK
T = Tc(CLK) = SSP_CLK period is equal to the SSP module master clock divided by a
configurable divider.
Figure 42. SSP_CLK timings
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Timing requirements
6.7.1
SPEAr300
SPI master mode timings (clock phase = 0)
Table 45.
Timing requirements for SPI master mode (clock phase = 0)
No.
Parameters
Min
Max
Unit
13
tsu(DIV-CLKL)
Setup time, MISO (input)
valid before SSP_CLK
(output) rising edge
Clock
Polarity = 0
-0.411
-0.342
ns
14
tsu(DIV-CLKH)
Setup time, MISO (input)
valid before SSP_CLK
(output) falling edge
Clock
Polarity = 1
-0.411
-0.342
ns
15
th(CLKL-DIV)
Hold time, MISO
Clock
(input)valid after SSP_CLK
Polarity = 0
(output) rising edge
0.912
1.720
ns
16
th(CLKH-DIV)
0.912
1.720
ns
Hold time, MISO (input)
valid after SSP_CLK
(output) falling edge
Clock
Polarity = 1
P = 1/SSP_CLK in nanoseconds (ns). For example, if the SSP_CLK frequency is 83 MHz,
use P = 12.048 ns
Table 46.
Switching characteristics over recommended operating conditions for
SPI master mode (clock phase = 0)
No.
Parameters
Max
Unit
17
td(CLKH-DOV)
Delay time, SSP_CLK
(output) falling edge to
MOSI (output) transition
Clock
Polarity = 0
-3.138
2.175
ns
18
td(CLKL-DOV)
Delay time, SSP_CLK
(output) rising edge to MOSI
(output) transition
Clock
Polarity = 1
-3.138
2.175
ns
19
td(ENL-CLKH/L)
20
td(CLKH/LENH)
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Min
Delay time, SSP_CSn (output) falling
edge to first SSP_CLK (output) rising or
falling edge
T/2
ns
Delay time, SSP_CLK (output) rising or
falling edge to SSP_CSn (output) rising
edge
T
ns
Doc ID 16324 Rev 2
SPEAr300
Timing requirements
Figure 43. SPI master mode external timing (clock phase = 0)
6.7.2
SPI master mode timings (clock phase = 1)
Table 47.
Timing requirements for SPI master mode (clock phase = 1)
No.
Parameters
tsu(DIV-
4
CLKL)
tsu(DIV-
5
CLKH)
6
th(CLKLDIV)
7
th(CLKHDIV)
Table 48.
Unit
Setup time, MISO (input)
valid before SSP_CLK
(output) falling edge
Clock
polarity = 0
-0.411
-0.342
ns
Setup time, MISO (input)
valid before SSP_CLK
(output) rising edge
Clock
polarity = 1
-0.411
-0.342
ns
Hold time, MISO (input)
valid after SSP_CLK
(output) falling edge
Clock
polarity = 0
0.912
1.720
ns
Hold time, MISO (input)
valid after SSP_CLK
(output) rising edge
Clock
polarity = 1
0.912
1.720
ns
Parameters
td(CLKHDOV)
9
Max
Switching characteristics over recommended operating conditions for
SPI master mode (clock phase = 1 )
No.
8
Min
td(CLKLDOV)
Min
Max
Unit
Delay time, SSP_CLK
(output) rising edge to
MOSI (output) transition
Clock
Polarity = 0
-3.138
2.175
ns
Delay time, SSP_CLK
(output) falling edge to
MOSI (output) transition
Clock
Polarity = 1
-3.138
2.175
ns
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Timing requirements
Table 48.
SPEAr300
Switching characteristics over recommended operating conditions for
SPI master mode (clock phase = 1 ) (continued)
No.
10
Parameters
td(ENLCLKH/L)
11
td(CLKH/LENH)
Min
Max
Delay time, SSP_CSn (output) falling
edge to first SSP_CLK (output) rising or
falling edge
T
ns
Delay time, SSP_CLK (output) rising or
falling edge to SSP_CSn (output) rising
edge
T/2
ns
Figure 44. SPI master mode external timing (clock phase = 1)
SSP_CSn
SSP_SCLK
(Clock Polarity = 0)
SSP_SCLK
(Clock Polarity = 1)
SSP_MISO
(Input)
SSP_MOSI
(Output)
6.8
UART (Universal asynchronous receiver/transmitter)
Figure 45. UART transmit and receive timings
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Unit
Doc ID 16324 Rev 2
SPEAr300
Timing requirements
Table 49.
UART transmit timing characteristics
S.No.
Parameters
1
UART Maximum Baud Rate
2
UART Pulse Duration Transmit
Data (TxD)
3
UART Transmit Start Bit
Table 50.
Min
Max
Unit
3
Mbps
0.99B(1)
B(1)
ns
0.99B(1)
B(1)
ns
UART receive timing characteristics
S.No.
Parameters
Min
Max
Units
4
UART Pulse Duration Receive
Data (RxD)
0.97B(1)
1.06B(1)
ns
5
UART Receive Start Bit
0.97B(1)
1.06B(1)
ns
where (1) B = UART baud rate
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Package information
7
SPEAr300
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 51.
LFBGA289 (15 x 15 x 1.7 mm) mechanical data
mm
inches
Dim.
Min.
Typ.
A
A1
Min.
Typ.
1.700
0.270
Max.
0.0669
0.0106
A2
0.985
0.0387
A3
0.200
0.0078
A4
0.800
0.0315
b
0.450
0.500
0.550
0.0177
0.0197
0.0217
D
14.850
15.000
15.150
0.5846
0.5906
0.5965
D1
E
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Max.
12.800
14.850
15.000
0.5039
15.150
0.5846
0.5906
E1
12.800
0.5039
e
0.800
0.0315
F
1.100
0.0433
0.5965
ddd
0.200
0.0078
eee
0.150
0.0059
fff
0.080
0.0031
Doc ID 16324 Rev 2
SPEAr300
Package information
Figure 46. LFBGA289 package dimensions
Table 52.
Thermal resistance characteristics
Package
JC °C/W)
JB °C/W)
LFBGA289
18.5
24.5
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Revision history
8
SPEAr300
Revision history
Table 53.
Document revision history
Date
Revision
15-Oct-2009
1
Initial release.
2
Changed the order of chapters in Section 2: Architecture overview
Updated Section 3.3: Shared I/O pins (PL_GPIOs) on page 35
Updated number of GPIOs in Table 10 on page 41
Updated Table 11: PL_GPIO multiplexing scheme on page 42
Added Section 3.4: PL_GPIO pin sharing for debug modes on
page 47
Updated Section 5: Electrical characteristics, Section 6.1: DDR2
timing characteristics, Section 6.3: I2C timing characteristics,
Section 6.4: FSMC timing characteristics and Section 6.7: SSP
timing characteristics
Added Table 52: Thermal resistance characteristics in Package
information.
29-Apr-2010
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Changes
Doc ID 16324 Rev 2
SPEAr300
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