SPMD150STP

SPMD150STP 1.5 A stepper motor driver module Features ■ Wide supply voltage range, up to 42 V ■ 1.5 A output average working current ■ Full/half step and micro-stepping drive capability ■ Logic signals TTL/CMOS compatible ■ Programmable motor phase current ■ Selectable slow/fast current decay ■ Non dissipative overcurrent protection ■ Remote shutdown ■ Thermal shutdown ■ Module size: 50.8 x 50.8 x 14.7 mm ■ Operating temperature range -40°C to 85 °C Table 1. Device summary Order code Description SPMD150STP The SPMD150STP is a highly integrated stepper motor driver module, that allows the user to easily design a complete motor control system for twophase bipolar stepper motors, interfacing directly the microprocessor to the motor. The SPMD150STP is an easy-to-use fully integrated answer to motion control issues. The phase current is chopper controlled, allowing good performances and high speed. Modules offer an extensive range of protection such as overcurrent and thermal shut-down, that make it “bullet” proof as required in modern motion control systems. Metallic case allows module to operate without external heat-sink or ventilation; moreover the sealed and molded package offers a complete protection against harsh environments. February 2010 Doc ID 17160 Rev 1 1/23 www.st.com 23 Contents SPMD150STP Contents 1 Block diagram and pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Function description and application information . . . . . . . . . . . . . . . . 11 4.1 Power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 Logic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 PWM current controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 Stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5.1 Half step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5.2 Normal drive mode (full-step two-phase-on) . . . . . . . . . . . . . . . . . . . . . 17 4.5.3 Wave drive mode (Full-step one-phase-on) . . . . . . . . . . . . . . . . . . . . . . 17 4.5.4 Microstepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.8 Case grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/23 Doc ID 17160 Rev 1 SPMD150STP 1 Block diagram and pin connection Block diagram and pin connection Figure 1. Block diagram Figure 2. Connection diagram (top view) Doc ID 17160 Rev 1 3/23 Block diagram and pin connection Table 2. Pin description Pin N. Name Function 1 VSS Logic stage supply voltage. This pin must be supplied with 3.3V or 5V source. 2 REF Voltage reference output. A voltage of 1.225V is available at this pin. It can be used to set the output current level. 3 RESET Reset pin. A logic level low restores the home state (State 1) on the phase sequence generator. A 10kΩ pull-up resistor is internally connected to VSS. 4 CLOCK Step clock. On the rising edge of this signal, the phase sequence generator changes its state position, consequently the motor performs a step. A 10kΩ pull-up resistor is internally connected to VSS. CW/CCW Spin direction control input. A logic level high sets clockwise motor rotation. A logic level Low sets counter clockwise motor rotation.Physical direction of rotation depends on windings connection also. A 10 kΩ pull-up resistor is internally connected to VSS. 5 6 7 8 VREFA Phase A/B current setting input. Connect this pin to a properly scaled REF (Pin2) voltage, to fix the maximum phase output current. Connecting a variable voltage source (i.e. microcontroller DAC), it is possible to perform microstepping drive. The pin is internally connected to a 100kΩ pull-down resistor, with a 470pF parallel capacitor. RCA Phase A/B current controller Off-Time set pin. Use this pin to set the desired Off-time of the switching current controller. A 470pF capacitor and 56kΩ resistor are internally connected between this pin and GND1 (Pin13), giving a 16μs -time. EN Module enable input. A high logic level enables module operation. EN (pin8) must be low, during power-up and power-down sequence, High during normal operation. (When this input is low, the output phases are in high impedance state, enabling the manual positioning of the motor). A 100kΩ pull-up resistor is internally connected to VSS. A 100nF capacitor is internally connected to GND1 9 Phase current decay mode selection input. A logic level high sets the slow decay mode. CONTROL A logic level low sets the fast decay mode A 10kΩ pull-up resistor is internally connected to VSS. 10 Half/Full step mode selection input. A logic level high sets the half step mode. HALF/FULL A logic level low sets the full step mode. A 10kΩ pull-up resistor is internally connected to VSS. 11 4/23 SPMD150STP VREFB Phase C/D current setting input. Connect this pin to a properly scaled REF (Pin2) voltage, to fix the maximum phase output current. Connecting a variable voltage source (i.e. microcontroller DAC), it is possible to perform micro-stepping drive. The pin is internally connected to a 100kΩ pull-down resistor, with a 470pF parallel capacitor. Doc ID 17160 Rev 1 SPMD150STP Block diagram and pin connection Table 2. Pin N. Pin description (continued) Name Function 12 RCB Phase C/D current controller -Time set pin. Use this pin to set the desired Off-time of the switching current controller. A 470pF capacitor and 56kΩ resistor are internally connected between this pin and GND1 (Pin13), giving a 16 µs -time. 13 GND1 Logic stage GND. Return path for the logic signals and VSS (pin1) supply voltage. 14 GND2 Power stage GND. Return path for the power stage and VS (pin19) supply voltage. 15 PHD Phase D output 16 PHC Phase C output 17 PHB Phase B output 18 PHA Phase A output 19 VS Power stage supply voltage. Module and motor supply voltage. Maximum voltage must not exceed the specified values. Doc ID 17160 Rev 1 5/23 Maximum ratings 2 SPMD150STP Maximum ratings Table 3. Absolute maximum ratings Symbol 6/23 Parameter Value Unit VS DC supply voltage (pin19) 50 V VSS DC logic supply voltage (pin1) 7 V -0.3 to 7 V 2.5 A Vinput Voltage range at pins VREFA, VREFB, RCA, RCB, EN, CLOCK, CW/CCW, HALF/FULL, CONTROL Io-pk Output peak current Tstg Storage temperature range – 40 to +105 °C Top Operating case temperature range – 40 to +85 °C Doc ID 17160 Rev 1 SPMD150STP 3 Electrical characteristics Electrical characteristics TA = 25 °C and VS = 24 V, VSS = 5 V unless otherwise specified. Table 4. Electrical characteristics Value Symbol Parameter Test conditions Unit Min Typ Max Power stage VS DC supply voltage IS Quiescent supply current (pin19) 10 All bridges 42 V 5 10 mA VSth(ON) Turn-on Input threshold 6.6 7 7.4 V VSth(OFF) Turn-off Input threshold 5.6 6 6.4 V ΔVVS-PH Output voltage drop (VS to pins 15,16,17,18) 0.9 V Output voltage drop (Pins15,16,17,18 to Io = 1.5A GND2) 1.1 V Phase average working current ±1.5 A 7.1 A ΔVPH-GND Io Io = -1.5A Protections block Io-sc Phase short circuit current Internally limited by overcurrent protection (Figure 7) 4 5.6 tOCD(ON) Overcurrent detection turn-on delay time (Figure 7) 200 ns tOCD(OFF) Overcurrent detection turn-off delay time (Figure 7) 100 ns Tj(OFF) Junction shutdown temperature 165 °C Logic interface VSS DC logic supply voltage ISS Quiescent supply current (pin 1) All inputs open VIL Low level input voltage Pin 5,9,10 VSS = 3 to 5.25V VIH High level input voltage Pin 5,9,10 VSS=3 to 5.25V Vth(ON) Turn-on input threshold Pin 3,4,8 VSS=3 to 5.25V (Figure 1, 2, 3, 4) Vth(OFF) Turn-off input threshold Pin 3,4,8 VSS=3 to 5.25V (Figure 1, 2, 3, 4) 0.8 1.3 V Vth(HYS) Input threshold hysteresis Pin 3,4,8 VSS=3 to 5.25V (Figure 1, 2, 3, 4) 0.25 0.5 V Low level Input current Pin 3,4,5,8,9,10 -0.5 mA IIL 3.0 Doc ID 17160 Rev 1 5 5.25 V 1.2 mA -0.3 0.8 V 2 Vss V 2.0 V 1.8 7/23 Electrical characteristics Table 4. SPMD150STP Electrical characteristics (continued) Value Symbol Parameter Test conditions Unit Min IIH VREF High level Input current Pin 3,4,5,8,9,10 Reference output voltage (pin 2) Typ Max 10 uA 1.21 1.225 1.24 V REF_res Reference output resistance (pin2) 10 kΩ VREFx_res Current setting input resistance (pin 6,11) 100 kΩ Timing definition tD(ON)EN Enable to output turn-on delay Io=2.5A, resistive load (Figure 3) 100 250 400 ns tD(OFF)EN Enable to output turn-off delay Io=2.5A, resistive load (Figure 3) 300 550 800 ns tRISE Output rise time Io=2.5A, resistive load (Figure 3) 40 250 ns tFALL Output fall time Io=2.5A, resistive load (Figure 3) 40 250 ns tDCLK Clock to output delay time Io=2.5A, resistive load (Figure 4) tCLK(MIN)L Clock minimum low level time (Figure 5) 1 µs tCLK(MIN)H Clock minimum high level time (Figure 5) 1 µs 50 kHz fCLK Clock frequency 2 µs tS(MIN) Minimum set-up time (Figure 6) 1 µs tH(MIN) Minimum hold time (Figure 6) 1 µs tR(MIN) Minimum reset time (Figure 6) 1 µs Minimum reset to clock delay time (Figure 6) 1 µs tRCLK(MIN) 8/23 Doc ID 17160 Rev 1 SPMD150STP Figure 3. Electrical characteristics Switching characteristic definition (1 9WK21 9WK2)) W ,287   W ',1 W)$// W'2))(1 Figure 4. W5,6( W'21(1 Clock to output delay time &/2&. 9WK21 W ,287 W ',1 Figure 5. W'&/. Minimum timing definition: clock &/2&. 9WK2)) 9WK21 W&/.0,1/ Doc ID 17160 Rev 1 9WK2)) W&/.0,1+ ',1 9/23 Electrical characteristics Figure 6. SPMD150STP Minimum timing definition: logic inputs &/2&. 9WK21 /2*,&,13876 W60,1 5(6(7 9WK2)) 9WK21 W50,1 Figure 7. W+0,1 W5&/.0,1 ',1 Overcurrent detection timing definition ,287 ,629(5 21 %5,'*( 2)) 9(1   W2&'21 10/23 Doc ID 17160 Rev 1 W2&'2)) ',1 SPMD150STP 4 Function description and application information Function description and application information SPMD150STP can be seen divided in several main blocks (see Figure 1): 4.1 ● Power stage, to drive the motor windings ● Logic interface, to interface the external signals to the internal circuitry ● PWM current controller, to fix and control the current flowing in the motor phase windings ● Decay control block, to control the phase current decay mode ● Phase sequence generator, to generate the motor phases driving sequence ● Protection block, performing over current protectionand thermal shut-down to protect the power bridges Power stage STMD150STP integrates two independent MOSFET full bridges, with intrinsic fast freewheeling diodes. Switching patterns are generated by the phase sequence generator and by the PWM current controller. The power MOSFET cross conduction in one bridge leg, is avoided introducing a dead time (tDT = 1 μs typical), between FETs switch off and the switch on. VS (pin19) and GND2 (pin14) must be connected to the supply voltage, which can range from 10 V to 42 V. 4.2 Logic interface Logic interface connects the external logic signal to the proper internal blocks. RESET (pin3), CLOCK (pin4), CW/CCW (pin5), CONTROL (pin9) and HALF/FULL (pin10) have a 10kΩ pull-up resistor to VSS (pin1), in order to prevent floating pins; VSS can be connected to 3.3 V or 5 V, allowing the interface with the most popular microcontroller. The internal structure is shown in Figure 8. EN (pin8) has identical input structure, with the exception that the MOSFET drain of the over-current and thermal protection is also connected to this pin (see Figure 9). Due to this connection some care needs to be taken in driving this pin. Inside the module a 100 kΩ resistor and a 100 nF capacitor is provided, an open collector driving is therefore the suggested solution. Doc ID 17160 Rev 1 11/23 Function description and application information 4.3 Figure 8. Logic inputs internal structure Figure 9. EN pin open collector driving SPMD150STP PWM current controller The control block is composed by a constant Off-time PWM current controller for both two bridges. The current control circuit senses the bridge current, by sensing the voltage drop across a sense resistor connected between the source of the two lower power MOSFETs and ground. As the current in the motor buildup, the voltage across the sense resistor increases proportionally. When the voltage on the sense resistor becomes greater than the voltage at the reference inputs VREFA (pin6) or VREFB (pin11), the sense comparator triggers a mono-stable circuit, switching the bridge off. The bridge MOSFETs remain off for the time set by pin RCA (pin7) or RCB (pin12); during this Off-time (see Figure 11, toff versus Roff and Coff), the motor phase current recirculates as defined by the selected decay mode, described in the next section. When the mono-stable circuit times out, the bridge will turn on again. Since the internal dead time tDT, used to prevent cross conduction in the bridge, delays the turn on of the power MOSFETs, the effective Off-time is the sum of the mono-stable time plus the tDT (1µs). To set the toff relative to Bridge A, it is necessary to connect a proper resistor Ra and/or a proper capacitor Ca in parallel between pin RCA and GND1, see Figure 10 and Figure 11; To set the toff relative to Bridge B, it is necessary to connect a proper resistor Rb and/or a proper capacitor Cb in parallel between pin RCB and GND1, see Figure 10 and Figure 11; A 56 kΩ resistor and a 470 pF capacitor are already present between pin RCA/B and GND1 inside the 12/23 Doc ID 17160 Rev 1 SPMD150STP Function description and application information module, fixing a typical 16 µs off time for both bridges. The toff value can be modified adding a capacitor to GND1, increasing the off time, or adding a resistor to GND1 decreasing the Off-time. Figure 10. toff setting circuit Roff = Ra // 56kΩ [kΩ], Coff = Ca + 470pF [pF] Figure 11. toff versus Roff and Coff To set the maximum motor phase current it is necessary to give the proper reference voltage at input VREFA (pin6) and VREFB (pin11). The relationship between the voltage at VREFx pin and the phase current IOUTx is the following: IOUTx = VREFx / 0.192 [A] An internal 100 kΩ resistor and a 470 pF capacitor are connected in parallel between VREFx and GND1 (see Figure 12). Doc ID 17160 Rev 1 13/23 Function description and application information SPMD150STP Figure 12. VREFA and VREFB internal connection The voltage at VREFA and VREFB can be supplied in two way: ● Using an external source (see Figure 13), driving VREFA and VREFB pins together or separately as in the micro-stepping mode (i.e: a micro-controller fixes a variable voltage to get variable current in the stepper motor phases). Figure 13. VREFx from an external source ● Using the module reference voltage source, REF (pin2) (see Figure 14), which supplies 1.225 V. The REF pin has a 10 kΩ resistor in series, take that in account during design. ● In this case a proper resistor Rx must be connected between REF and GND1, VREFA and VREFB will be connected together to REF pin (see Figure 14). Use following equation to calculate Rx: Rx = (500 x IOUTx) / [319 - (60 x IOUTx)] [kΩ] 14/23 Doc ID 17160 Rev 1 where IOUTx = [A] SPMD150STP Function description and application information Figure 14. VREFx from internal source 4.4 Decay modes The CONTROL input is used to select the behavior of the bridge during the off time. When the CONTROL pin is low, the fast decay mode is selected and both transistors in the bridge are switched off during the off time. When the CONTROL pin is high, the slow decay mode is selected and only the low side transistor of the bridge is switched off during the off time. Figure 15 shows the operation of the bridge in the fast decay mode. At the start of the off time, both of the power MOSFETs are switched off and the current recirculates through the two opposite free wheeling diodes. The current decays with a high di/dt, since the voltage across the coil is essentially the power supply voltage. After the dead time, the lower power MOSFET in parallel with the conducting diode is turned on in synchronous rectification mode. In applications where the motor current is low it is possible that the current can decay completely to zero during the off time. At this point if both of the power MOS were operating in the synchronous rectification mode it would then be possible for the current to build in the opposite direction. To prevent this only the lower power MOS is operated in synchronous rectification mode. This operation is called quasi-synchronous rectification mode. When the mono-stable circuit times out, the power FETs are turned on again after some delay set by the dead time to prevent cross conduction. Doc ID 17160 Rev 1 15/23 Function description and application information SPMD150STP Figure 15. Fast decay mode output stage configurations $217,0( %MV'($'7,0( ',1 &48$6,6