SR1LARU

SR1 4 pin Smart Reset™ Datasheet - production data Applications  Wearable  Activity tracker  Smartwatch  Smartglasses UDFN6 (1.00 x 1.45 mm) Features  Operating voltage range 2 V to 5.5 V  Low supply current 1 µA  Integrated test mode  Single Smart Reset™ push-button input with fixed extended reset setup delay (tSRC) from 0.5 s to 10 s in 0.5 s steps (typ.), option with internal input pull-up resistor  Push-button controlled reset pulse duration – Option 1: fully push-button controlled, no fixed or minimum pulse width guaranteed – Option 2: defined output reset pulse duration (tREC), factory-programmed  Single reset output – Active low or active high – Push-pull or open drain with optional pullup resistor  Fixed Smart Reset input logic voltage levels  Operating temperature: -40 °C to +85 °C  UDFN6 package 1.00 mm x 1.45 mm  ECOPACK®2 (RoHS compliant, HalogenFree) May 2014 This is information on a product in full production. DocID026048 Rev 2 1/21 www.st.com Contents SR1 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.4 Smart Reset input (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.5 Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.6 RST output undervoltage behavior (for open-drain option) . . . . . . . . . . . . 6 4 Typical application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 12 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/21 DocID026048 Rev 2 SR1 1 Description Description The Smart ResetTM devices provide a useful feature which ensures that inadvertent short reset push-button closures do not cause system resets. This is done by implementing an extended Smart Reset input delay time (tSRC), which ensures a safe reset and eliminates the need for a specific dedicated reset button. This reset configuration provides versatility and allows the application to distinguish between a software generated interrupt and a hard system reset. When the input pushbutton is connected to the microcontroller interrupt input, and is closed for a short time, the processor can only be interrupted. If the system still does not respond properly, continuing to keep the push-button closed for the extended setup time tSRC causes a hard reset of the processor through the reset output. The SR1 has one Smart Reset input (SR) with preset delayed Smart Reset setup time (tSRC). The reset output (RST) is asserted after the Smart Reset input is held active for the selected tSRC delay time. The RST output remains asserted either until the SR input goes to inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset pulse duration is fixed for tREC (i.e. factory-programmed). The device fully operates over a broad VCC range from 2.0 V to 5.5 V. 1.1 Test mode After pulling SR up to VTEST (VCC + 1.4 V) or above, the counter starts to count the initial shortened tSRC-INI (42 ms, typ.). After tSRC-INI expires, the RST output either goes down for tREC (if tREC option is used) or stays low as long as overvoltage on SR is detected (if tREC option is not used). This is feedback, and the user only knows that the device is locked in test mode. Each time the SR input is connected to ground in test mode, a shortened tSRC-SHORT (tSRC/128) is used instead of regular tSRC (0.5 s - 10 s). In this way the device can be quickly tested without repeating test mode triggering. Return to normal mode is possible by performing a new startup of the device (i.e. VCC goes to 0 V and back to its original state). The advantages of this solution are its high glitch immunity, user feedback regarding entry into test mode, and testability within the full VCC range. DocID026048 Rev 2 3/21 21 Description 1.2 SR1 Logic diagram Figure 1. SR1 logic diagram 9&& 65 65 567 *1' $0Y 1.3 Pin connections Figure 2. UDFN6 pin connections (top view) RST 1 VSS 2 SR 3 SR1 6 NC(1) 5 NC(1) 4 VCC UDFN6 AM07463v2 1. Not connected (not bonded); should be connected to VSS. 4/21 DocID026048 Rev 2 SR1 Device overview 2 Device overview Table 1. Signal names Pin n° Name Type Description 1 RST Output 2 VSS Supply ground 3 SR Input 4 VCC Supply voltage 5 NC - Not connected (not bonded); should be connected to VSS. 6 NC - Not connected (not bonded); should be connected to VSS. Reset output, active low, open drain. Ground Smart Reset input, active low. Positive supply voltage for the device. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between VCC and VSS pins. Figure 3. SR1 block diagram 65 W65& JHQHUDWRU W5(& JHQHUDWRU RSWLRQDO 567 2YHUYROWDJHGHWHFW  WHVWPRGHWULJJHU $09 DocID026048 Rev 2 5/21 21 Pin descriptions SR1 3 Pin descriptions 3.1 Power supply (VCC) This pin is used to provide power to the Smart Reset device. A 0.1 µF ceramic decoupling capacitor is recommended to be connected between the VCC and VSS pins, as close to the SR1 device as possible. 3.2 Power-up sequence In normal mode, if different input side (SR) and VCC voltage domains are used, power-on sequence must avoid meeting the test mode entry condition to avoid inadvertent test mode entry: there should not be logic high present on the SR input before the VCC power-up. However VCC and V(SR) rising at the same time is OK (e.g. if both are in the same voltage domain), the device will then safely start into normal operating mode, with RST output inactive (in High-Z mode for open-drain option). 3.3 Ground (VSS) This is the ground pin for the device. 3.4 Smart Reset input (SR) Push-button Smart Reset input, active low with optional pull-up resistor. SR input needs to be asserted for at least tSRC to assert the reset output (RST). By connecting a voltage higher than VCC + 1.4 V to the SR input the device enters test mode (see Section 1: Description on page 3 for more information). 3.5 Reset output (RST) RST is active low or active high, open drain or push-pull reset output with optional internal pull-up resistor. Output reset pulse width is optional as follows: 3.6  Neither fixed nor minimum output reset pulse duration (releasing the push-button while reset output is active, causes the output to de-assert)  Fixed, factory-programmed output reset pulse duration for tREC independent on Smart Reset input state. RST output undervoltage behavior (for open-drain option) High-Z on RST output below the specified operating voltage range is guaranteed at VCC power-on or in case that valid VCC dropped while the device was idle, i.e. while both output and input were inactive. 6/21 DocID026048 Rev 2 SR1 4 Typical application diagrams Typical application diagrams Figure 4. Typical application diagram - input, output and SR1 device in one voltage domain SR1 AM07466v1 Figure 5. Typical application diagram - SR1 device in a different voltage domain than input and output VCC VDD VCC VDD RST RESET SR1 MCU SR INT/ NMI VSS VSS PUSH - BUTTON SWITCH AM07466v2 1. Open-drain RST output type and fixed SR input logic threshold allows to use the device in different voltage domains. To prevent entering test mode by creating a condition V(SR) > VCC + 1.1 V typ., VCC should be powered up before or together with voltage on the SR input. DocID026048 Rev 2 7/21 21 Typical application diagrams SR1 Figure 6. Typical application diagram in different voltage domains - SR input in VBAT domain like VCC totally disables the test mode SR1 AM07466v3 8/21 DocID026048 Rev 2 SR1 5 Timing diagrams Timing diagrams Figure 7. RST output without tREC option 1. VCC should be powered up before or together with voltage on the SR input to prevent entering test mode by creating a condition V(SR) > VCC +1.1 V typ. Figure 8. RST output with tREC option 1. VCC should be powered up before or together with voltage on the SR input to prevent entering test mode by creating a condition V(SR) > VCC +1.1 V typ. DocID026048 Rev 2 9/21 21 Typical operating characteristics 6 SR1 Typical operating characteristics Figure 9. Supply current (ICC) vs. temperature (TA)   9&& 9 9&& 9 9&& 9             7HPSHUDWXUH7$ ƒ& $0 Figure 10. Smart Reset delay (tSRC) vs. temperature (TA), tSRC = 4.0 s (typ.) 6PDUW5HVHWGHOD\W 65& V   9&& 9 9&& 9  9&& 9              7HPSHUDWXUH7 $ ƒ& $0 10/21 DocID026048 Rev 2 SR1 Typical operating characteristics Figure 11. Test mode entry voltage (VTEST) vs. temperature (TA) 7HVWPRGHHQWU\YROWDJH97(67 9  9&& 9 9&& 9  9&& 9             7HPSHUDWXUH7$ƒ& $0 Figure 12. Initial test mode time (tSRC-INI) vs. temperature (TA) ,QLWLDOWHVWPRGHWLPHW 65&B,1, PV  9&& 9 9&& 9  9&& 9            7HPSHUDWXUH7$ƒ& $0 DocID026048 Rev 2 11/21 21 Maximum ratings 7 SR1 Maximum ratings Stressing the device above the rating listed in Table 2: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in Table 3: Operating and measurement conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics™ SURE program and other relevant quality documents. Table 2. Absolute maximum ratings Symbol TSTG TSLD(1) Parameter Storage temperature (VCC off) Lead solder temperature for 10 seconds VIO Input or output voltage VCC Supply voltage Value Unit -55 to +150 °C 260 °C -0.3 to 5.5 V -0.3 to 7 V ESD VHBM Electrostatic discharge protection, human body model (JESD22A114-B level 2) 2 kV VRCDM Electrostatic discharge protection, charged device model, all pins 1 kV 200 V VMM Electrostatic discharge protection, machine model, all pins (JESD22-A115-A level A) Latch-up (VCC pin, SR reset input pin) 1. 12/21 EIA/JESD78 Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. DocID026048 Rev 2 SR1 8 DC and AC parameters DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in Table 4: DC and AC characteristics are derived from tests performed under the measurement conditions summarized in Table 3: Operating and measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 3. Operating and measurement conditions Symbol VCC TA tR , tF Parameter Value Unit Supply voltage 2.0 to 5.5 V Ambient operating temperature -40 to +85 °C  5 ns Input pulse voltages 0.2 to 0.8 VCC V Input and output timing reference voltages 0.3 to 0.7 VCC V Input rise and fall times DocID026048 Rev 2 13/21 21 DC and AC parameters SR1 Table 4. DC and AC characteristics Symbol Parameter Unit 5.5 V 1.0 µA VCC  4.5 V, sinking 3.2 mA 0.3 V Reset output voltage low VCC  3.3 V, sinking 2.5 mA 0.3 V 0.3 V Supply voltage ICC Supply current Min. Typ.(2) Max. VCC VOL Test conditions(1) 2.0 SR = VCC, tREC and tSRC counter is not running 0.4 VCC  2.0 V, sinking 1 mA tREC Reset timeout delay, factory-programmed (device option) RPUO Internal output pull-up resistor on RST (device option) ILO Output leakage current VRST = 5.5 V, open drain device option without output pull-up resistor 140 210 280 ms 240 360 480 ms 65 -0.1 k 0.1 µA Smart Reset tSRC Smart Reset delay TA = -40 to +85 °C 0.8 x tSRC TA = 25 °C 0.9 x tSRC tSRC(3) 1.2 x tSRC s 1.1 x tSRC VIL SR input voltage low VSS-0.3 0.3 V VIH SR input voltage high 0.85 5.5 V RPUI Internal input pull-up resistor on SR (device option) ILEAK SR input leakage current device option without input pull-up resistor 65 -0.1 Input glitch immunity k 0.1 µA s tSRC Test mode VTEST Test mode entry voltage tSRC-INI Initial test mode time tSRC-SHORT VCC +0.9 VCC +1.1 VCC +1.4 V 28 42 56 ms Shortened Smart Reset delay tSRC / 128 1. Valid for ambient operating temperature TA = -40 to +85 °C, VCC = 2.0 to 5.5 V. 2. Typical values are at 25 °C and VCC = 3.3 V unless otherwise noted. 3. Factory-programmable in the range of 0.5 s to 10 s typ. in 0.5 s steps. 14/21 DocID026048 Rev 2 ms SR1 9 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 13. UDFN6, (1.00 x 1.45 x 0.50 mm), 0.50 mm pitch package outline ' 1 (     $ $ / N H E 8')1/ DocID026048 Rev 2 15/21 21 Package information SR1 Table 5. UDFN6, (1.00 x 1.45 x 0.50 mm), 0.50 mm pitch package mechanical data Dimensions Symbol (mm) Note(1) (inches) Min. Typ. Max. Min. Typ. Max. A 0.50 0.55 0.60 0.0197 0.0217 0.0236 A1 0.00 0.02 0.05 0.000 0.0008 0.0020 b 0.18 0.25 0.30 0.0071 0.0098 0.0118 D 1.40 1.45 1.50 0.0551 0.0571 0.0591 E 0.95 1.00 1.05 0.0374 0.0394 0.0413 e 0.45 0.50 0.55 0.0177 0.0197 0.0217 k 0.20 L 0.30 0.0138 0.0157 0.0079 0.35 0.40 0.0118 1. Package outline exclusive of any mold flashes dimensions and metal burrs. Figure 14. Footprint recommendation for UDFN6 (1.00 x 1.45 x 0.50 mm), 0.50 mm pitch      $0 16/21 DocID026048 Rev 2 SR1 10 Tape and reel information Tape and reel information Figure 15. Carrier tape $0 1. 10-sprocket hole pitch cumulative tolerance ±0.20. Figure 16. Pin 1 orientation 8VHUGLUHFWLRQRIIHHG $09 DocID026048 Rev 2 17/21 21 Part numbering 11 SR1 Part numbering Table 6. Ordering information scheme Example: SR1 H A R U Device type SR1 Smart Reset setup delay (tSRC)(1) C = factory programmable tSRC = 1.5 s (typ.) H = factory programmable tSRC = 4.0 s (typ.) L = factory programmable tSRC = 6.0 s (typ.) P = factory programmable tSRC = 7.5 s (typ.) U = factory programmable tSRC = 10.0 s (typ.) Inputs, outputs type(2) A = active low SR input with no pull-up, active low open drain RST output with no pull-up B = active low SR input with pull-up, active low open drain RST output with no pull-up Reset timeout period (tREC) A = factory programmable tREC = 210 ms (typ.) B = factory programmable tREC = 360 ms (typ.) R = push-button controlled (no defined tREC) Package U = UDFN-6L 1. Smart Reset delay (tSRC) is available from 0.5 s to 10 s in 0.5 s steps (typ.). Minimum order quantities may apply. Contact local sales office for availability. 2. Push-pull reset output type also available (active low or active high). SR input and open drain reset output available with optional pull-up resistor. Minimum order quantities may apply. Contact local sales office for availability. 18/21 DocID026048 Rev 2 SR1 12 Package marking information Package marking information Table 7. Package marking Part number tSRC (s) Smart Reset inputs(1) Output type(2) tREC option(3) Package Topmark SR1CARU 1.5 AL OD, AL No tREC UDFN6 CA SR1HARU 4.0 AL OD, AL No tREC UDFN6 HA SR1LARU 6.0 AL OD, AL No tREC UDFN6 LA SR1PAAU 7.5 AL OD, AL 210 ms UDFN6 PB SR1PARU 7.5 AL OD, AL No tREC UDFN6 PA SR1PBBU 7.5 AL + pull-up OD, AL 360 ms UDFN6 PC SR1UARU 10.0 AL OD, AL No tREC UDFN6 UA 1. AL = active low. 2. OD = open drain, AL = active low. 3. No tREC = push-button controlled reset pulse width, any other value represents typical value of tREC. Figure 17. Package marking (top view) $ % $ GRWSLQUHIHUHQFH % PDUNLQJDUHDWRSPDUN *$3060' DocID026048 Rev 2 19/21 21 Revision history 13 SR1 Revision history Table 8. Document revision history 20/21 Date Revision Changes 10-Mar-2014 1 Initial release 13-May-2014 2 Modified tREC values Table 4 on page 14 DocID026048 Rev 2 SR1 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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