SR2
6 pin Smart Reset™
Datasheet - production data
Applications
Wearable
Activity tracker
Smartwatch
Smartglasses
UDFN6 (1.6 x 1.3 mm)
Features
Operating voltage 1.65 V to 5.5 V
Low supply current 1.5 µA
Integrated test mode
Dual Smart Reset™ push-button inputs with
fixed extended reset setup delay (tSRC) from
0.5 s to 10 s in 0.5 s steps (typ.), option with
internal pull-up resistor
Push-button controlled reset pulse duration
– Option 1: fully push-button controlled, no
fixed or minimum pulse width guaranteed
– Option 2: defined output reset pulse
duration (tREC), factory-programmed
No power-on reset
Single reset output
– Active low or active high
– Push-pull or open drain with optional pullup resistor
Fixed Smart Reset™ input logic voltage levels
Operating temperature: - 40 °C to +85 °C
UDFN6 package: 1.6 mm x 1.3 mm
ECOPACK®2 (RoHS compliant, HalogenFree)
May 2014
This is information on a product in full production.
DocID026047 Rev 2
1/22
www.st.com
Contents
SR2
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
2
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Smart Reset™ input (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4
Smart Reset™ input (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5
Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10
Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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1
Description
Description
The Smart Reset™ devices provide a useful feature that ensures inadvertent short reset
push-button closures do not cause system resets. This is done by implementing extended
Smart Reset™ input delay time (tSRC) and combined push-button inputs, which together
ensures a safe reset and eliminates the need for a specific dedicated reset button.
This reset configuration provides versatility and allows the application to distinguish
between a software generated interrupt and a hard system reset. When the input pushbutton are connected to microcontroller interrupt inputs, and are closed for a short time, the
processor can only be interrupted. If the system still does not respond properly, continuing
to keep the push-button closed for the extended setup time tSRC causes a hard reset of the
processor through the reset output.
The SR2 has two combined delayed Smart Reset™ inputs (SR0, SR1) with preset delayed
Smart Reset™ setup time (tSRC). The reset output is asserted after both of the Smart
Reset™ inputs were held active for the selected tSRC delay time. Depending on selected
option the RST output remains asserted either until at least one SR input goes to inactive
logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset pulse
duration is fixed for tREC (i.e. factory-programmed). The reset output, RST, is active low or
active high, push-pull or open drain with optional pull-up resistor. The device fully operates
over a broad VCC range 1.65 V to 5.5 V. Below 1.575 V typ. the inputs are ignored and
outputs are deasserted; the deasserted reset output levels are then valid down to 1.0 V.
1.1
Test mode
After pull of SR0 up to VTEST or more (VCC + 1.4 V, max.) we start counting initial shorten
tSRC-INI (42 ms, typ.). After tSRC-INI expires, the RST output either goes down for tREC (if
tREC option is used) or stays low as long as overvoltage on SR0 in detected (if tREC option is
not used). This is a feedback and a user knows that the device is locked in the test mode.
Each time both SR inputs are connected to ground in test mode a shorten tSRC-SHORT (21
ms, typ.) is used instead of long tSRC (0.5 s -10 s). Return from to normal mode is possible
by a new startup of the device (i.e. VCC goes to 0 V and back to its original state). In this way
the device can be quickly tested without repeating test mode triggering. Advantage of this
solution is pretty high glitch immunity, feedback to user about entry to the test mode and
testability within full VCC range.
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Description
SR2
Figure 1. Logic diagram
VCC
SR 0
SR2
RST
SR1
GND
GAMS2602141440SG
Figure 2. Pin connections (top view)
VSS
1
SR 1
2
RST
3
SR2
6
V CC
5
SR 0
4
NC
GAMS2602141445SG
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SR2
Description
Table 1. Signal names
Pin Name
1
VSS
2
SR1
Type
Description
Supply ground Ground
Input
3
RST
Output
4
NC
-
5
SR0
Input
6
VCC
Secondary push-button Smart Reset™ input. Active low. Optional pull-up resistor
Reset output
(open drain with optional pull-up resistor, active low)
(push-pull – active low or active high)
Not connected (not bonded; should be connected to VSS)
Primary push-button Smart Reset™ input. Active low. Optional pull-up resistor
Positive supply voltage for the device. A 0.1 µF decoupling ceramic capacitor is
Supply voltage recommended to be connected between VCC and VSS pins, as close to the SR2
device as possible
Figure 3. Block diagram
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Pin descriptions
SR2
2
Pin descriptions
2.1
Power supply (VCC)
This pin is used to provide power to the Smart Reset™ device. A 0.1 µF ceramic decoupling
capacitor is recommended to be connected between the VCC and VSS pins, as close to the
SR2 device as possible.
2.2
Ground (VSS)
Ground pin for the device.
2.3
Smart Reset™ input (SR0)
Push-button Smart Reset™ input is active low with optional pull-up resistor. Both SR
inputs need to be asserted simultaneously for at least tSRC to assert the reset output (RST).
By connecting a voltage higher than VCC to the SR0 the device enters a test mode (see
Section 1: Description on page 3 for more information).
2.4
Smart Reset™ input (SR1)
Push-button Smart Reset™ input is active low with optional pull-up resistor. Both SR inputs
need to be asserted simultaneously for at least tSRC to assert the reset output (RST).
2.5
Reset output (RST)
RST is active low or active high, push-pull or open drain reset output with optional internal
pull-up resistor. Output reset pulse width is optional as follows:
Neither fixed nor minimum output reset pulse duration (releasing the push-button while
reset output is active, causes the output to deassert);
Fixed, factory-programmed output reset pulse duration for tREC independent on Smart
Reset™ input state.
If VCC drops below 1.575 V, the RST output is deasserted and its state is guaranteed down
to 1 V (see Figure 8).
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3
Typical application diagram
Typical application diagram
Figure 4. Single-button Smart Reset™ typical hookup
VCC
(1)
(2)
VCC
VCC
RST
RESET
SR2
MCU
SR0
SR1
INT / NMI
VSS
VSS
PUSH - BUTTON
SWITCH (3)
GAMS2602141450SG
1. External pull-up resistor requested if the reset output (RST) is open drain type without internal pull-up.
2. External pull-up resistor requested if the Smart Reset™ inputs (SR0 and SR1) have no internal pull-up.
3. When only one Smart Reset™ input push-button is used, tie both the SR inputs together.
DocID026047 Rev 2
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Typical application diagram
SR2
Figure 5. Dual-button Smart Reset™ typical hookup
VCC
(1)
(2)
VCC
(2)
VCC
RST
RESET
MCU
SR2
SR0
SR1
INT/ NMI
VSS
VSS
PUSH -BUTTON
SWITCH
PUSH - BUTTON
SWITCH
GAMS2602141500SG
1. External pull-up resistor requested if the reset output (RST) is open drain type without internal pull-up.
2. External pull-up resistor requested if the Smart Reset™ inputs (SR0 and SR1) have no internal pull-up.
8/22
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Timing waveforms
4
Timing waveforms
Figure 6. Option without tREC
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Figure 7. Option with tREC
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Timing waveforms
SR2
Figure 8. Undervoltage condition
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1. If undervoltage occurs (VCC drops below 1.575 V typ.) while reset output is active, the reset output is
released and goes inactive.
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Typical operating characteristics
Figure 9. Supply current (ICC) vs. temperature (TA)
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Figure 10. Smart Reset™ delay (tSRC) vs. temperature (TA), tSRC = 7.5 s (typ.)
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Typical operating characteristics
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Typical operating characteristics
SR2
Figure 11. Test mode entry voltage (VTEST) vs. temperature (TA)
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Figure 12. Initial test mode time (tSRC-INI) vs. temperature (TA)
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6
Maximum ratings
Maximum ratings
Stressing the device above the rating listed in Table 2: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in Table 3: Operating and
measurement conditions of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics™ SURE program and other relevant quality documents.
Table 2. Absolute maximum ratings
Symbol
TSTG
TSLD(1)
Parameter
Storage temperature (VCC off)
Lead solder temperature for 10 seconds
VIO
Input or output voltage
VCC
Supply voltage
Value
Unit
-55 to +150
°C
260
°C
-0.3 to
5.5(2)
V
-0.3 to 7
V
ESD
VHBM
Electrostatic discharge protection, human body model (JESD22A114-B level 2)
2
kV
VRCDM
Electrostatic discharge protection, charged device model, all pins
1
kV
200
V
EIA/JESD78
-
VMM
Electrostatic discharge protection, machine model, all pins
(JESD22-A115-A level A)
Latch-up (VCC pin, SR0 reset input pin)
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
2. For push-pull RST output type only from -0.3 V to VCC +0.3 V.
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DC and AC parameters
7
SR2
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters inTable 4: DC and AC characteristic that
follow, are derived from tests performed under the measurement conditions summarized in
Table 3: Operating and measurement conditions. Designers should check that the operating
conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 3. Operating and measurement conditions
Symbol
VCC
TA
14/22
Parameter
Value
Unit
Supply voltage
1.65 to 5.5
V
Ambient operating temperature
-40 to +85
°C
DocID026047 Rev 2
SR2
DC and AC parameters
Table 4. DC and AC characteristic
Symbol
Parameter
VCC
Supply voltage(3)
ICC
Supply current (inputs in
their inactive state, tSRC
counter is not running)
VOL
VOH
Reset output voltage low
Reset output voltage high
(push-pull output only)
Test conditions(1)
Typ.(2)
1.65
Max.
Unit
5.5
V
VCC = 3.0 V
1.1
2.5
µA
VCC = 5.0 V
1.5
3.0
µA
VCC 4.5 V, sinking 3.2 mA
0.3
V
VCC 3.3 V, sinking 2.5 mA
0.3
V
VCC 1.65 V, sinking 1 mA
0.3
V
VCC 4.5 V, ISOURCE = 0.8 mA
0.8 VCC
V
VCC 2.7 V, ISOURCE = 0.5 mA
0.8 VCC
V
VCC 1.65 V, ISOURCE = 0.25 mA
0.8 VCC
V
Reset timeout delay,
factory-programmed
(device option)
RPUO
Internal output pull-up
resistor on RST
(device option)
ILO
Output leakage current
VRST = 5.5 V, open drain device
option without output pull-up
resistor
tREC
Min.
240
360
480
65
-0.1
ms
k
0.1
µA
Smart ResetTM
tSRC
Smart Reset™ delay
TA = -40 to +85 °C
0.8 x tSRC
TA = 25 °C
0.9 x tSRC
tSRC(4)
1.2 x tSRC
s
1.1 x tSRC
VIL
SR0, SR1 input voltage
low
VSS -0.3
0.3
V
VIH
SR0, SR1 input voltage
high
0.85
5.5
V
ILI
SR0, SR1 input leakage
current
-0.1
0.1
µA
Input glitch immunity(5)
SR0 and SR1 asserted
tSRC
s
Test mode
VTEST
Test mode entry voltage
tSRC-INI Initial test mode time
tSRCSHORT
Shorten Smart Reset™
delay
VCC +0.9
VCC +1.1
VCC +1.4
V
28
42
56
ms
16.8
21
25.2
ms
1. Valid for ambient operating temperature TA = -40 to +85 °C, VCC = 1.65 to 5.5 V.
2. Typical values are at 25 °C and VCC = 3.3 V unless otherwise noted.
3. Reset outputs are deasserted below 1.575 V typ. and remain deasserted down to VCC = 1 V.
4. Factory-programmable in the range of 0.5 s to 10 s typ. in 0.5 s steps (see Table 7 for available delays).
5.
Input glitch immunity is equal to tSRC, when both inputs (SR0 and SR1) are low. Otherwise infinite.
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Package information
8
SR2
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 13. Package outline for UDFN6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch
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Package information
Table 5. Mechanical data for UDFN6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch
Dimensions
Symbol
Drawing (millimeters)
Drawing (inches)
Note
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.50
0.55
0.60
0.020
0.022
0.024
A1
0.00
0.02
0.05
0.0000
0.0008
0.0020
b
0.15
0.20
0.25
0.006
0.008
0.010
D
1.30 BSC
0.051 BSC
E
1.60 BSC
0.063 BSC
e
0.40 BSC
0.016 BSC
L
0.250
N
0.325
0.400
0.0098
6
0.0128
0.0157
6
Figure 14. Footprint recommendation for UDFN6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch
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Package information
SR2
Figure 15. Carrier tape for UDFN6 1.6 x 1.3 x 0.55 mm
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