SRK2001TR

SRK2001 Datasheet Adaptive synchronous rectification controller for LLC resonant converter Features • • • • • • • • • • • • • • • Secondary side synchronous rectification controller optimized for LLC resonant converter Dual gate driver for N-channel MOSFET Adaptive turn-off logic Turn-on logic with adaptive masking time Auto-compensation of parasitic inductance Low consumption mode: 50 μA quiescent current VCC operating voltage range 4.5 V to 32 V High voltage drain-to-source Kelvin sensing for each SR MOSFET 35 ns total delay at turn-off Protection against current reversal Safe management of load transient, light-load and startup conditions Intelligent automatic sleep mode at light-load with user programmable enter/exit load levels, with soft transitions and function disable Programmable exit load levels from burst mode Compatible with standard level MOSFET SSOP10 package Applications Product status link SRK2001 Product summary Order code SRK2001 Package Packing SRK2001TR SSOP10 Tube Product label • • • • • • AC-DC adapters All-in-one PC High-end flat panel TV 80+/85+ compliant ATX SMPS 90+/92+ compliant SERVER SMPS Industrial SMPS Tape & Reel Description The SRK2001 controller implements a control scheme specific for secondary side synchronous rectification in LLC resonant converters that use a transformer with center tap secondary winding for full wave rectification. It provides two high current gate drive outputs, each capable of directly driving one or more N-channel power MOSFET. Each gate driver is controlled separately and an interlock logic circuit prevents the two synchronous rectifier MOSFET from conducting simultaneously. The control scheme ensures that each synchronous rectifier is switched ON as the corresponding half-winding starts conducting and OFF as its current falls to zero. The turn-on logic with adaptive masking time and adaptive turn-off logic allow maximizing the conduction time of the SR MOSFET, eliminating the need for a parasitic inductance compensation circuit. The low consumption mode of the device allows meeting the most stringent requirements for converter power consumption in light-load and no-load conditions. A very low external component count is required when using this device. DS10811 - Rev 6 - September 2021 For further information contact your local STMicroelectronics sales office. www.st.com SRK2001 Block diagrams 1 Block diagrams Figure 1. Internal block diagram DVS1 SVS1 UVLO HV CLAMP and SWITCH VBUS VCC POWER MANAGEMENT GND DVS2 SVS2 TIMERS COMPARATORS EN ON ADC ZCD ADAPTIVE ON-TIME PROG OFF ADAPTIVE OFF-TIME CONTROL LOGIC GD1 CK DRIVER DRIVER GD2 Figure 2. Typical system block diagram PFC PRE-REGULATOR(OPTIONAL) LLC RESONANT HALF-BRIDGE WITH SYNCH RECTIFIER VOUT V INac L6562A L6563/S/H DS10811 - Rev 6 L6599A L6699 SRK2001 page 2/23 SRK2001 Pin connections and functions 2 Pin connections and functions Figure 3. Pin connections (top view) Table 1. Pin functions No. Name 1 VCC Supply voltage of the device. A bypass capacitor to GND located as close to IC pins as possible helps to obtain a clean supply voltage for the internal control circuitry and acts as an effective energy buffer for the pulsed gate drive currents. 2 GND Return of the device bias current and return of the gate drive currents. Route this pin to the common point where the source terminals of both synchronous rectifier MOSFET are connected. 3 GD1 (GD2) Gate driver output for section 1 (2). Each totem pole output stage is able to drive power MOSFET with high peak current levels. To avoid excessive gate voltages when the device is supplied with a high VCC, the high-level voltage of these pins is clamped to about 11 V. The pin has to be connected directly to the SR MOSFET gate terminal. SVS1 (SVS2) Source voltage sensing for section 1 (2): it is the reference voltage of the corresponding drain sensing signal on the DVS1,2 pin. These pins have to be connected directly to the respective source terminals of the corresponding synchronous rectifier MOSFET. DVS1 (DVS2) Drain voltage sensing for section 1 (2). These pins have to be connected to the respective drain terminals of the corresponding synchronous rectifier MOSFET using a series resistor of 100 Ω. PROG Programming pin for conduction duty cycle on sleep mode entry/exit. A resistor connected from this pin to GND, supplied by an internal precise current source, sets a voltage VPROG; depending on this voltage level, during the startup phase, the user can chose, according to the application requirements, the proper sleep mode or burst mode exiting the conduction duty cycle among the ones contained into two internal lookup tables (the values are predefined inside Table 5, Table 6 and Table 7). SeeTable 4 for the proper choice of resistor value. (8) 4 (7) 5 (6) 9 Function Enable pin function with internal pull-up and current source capability: – Automatic sleep mode function enable/disable: the sleep mode is disabled if the pin voltage is detected above an internal threshold (VSM_off) during the startup phase. 10 EN – Remote ON/OFF: during run the mode, when the pin voltage is sensed below the internal threshold VEN_OFF, the controller stops operating and enters a low consumption state; it resumes operation if the pin voltage exceeds the threshold VEN_ON. – During the startup phase, the pin voltage level allows selection of the predefined conduction duty cycle for sleep mode entering. A resistor connected from this pin to GND, supplied by an internal precise current source allows the user for this choice (two predefined values). See Table 4 to find the appropriate resistor value. DS10811 - Rev 6 page 3/23 SRK2001 Absolute maximum ratings 3 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Pin Parameter Value Unit VCC 1 DC supply voltage -0.3 to VCCZ V ICCZ 1 Internal Zener maximum current (VCC = VCCZ) 25 mA VPROG 10 PROG pin voltage rating -0.3 to 3.3 V VEN 9 EN pin voltage rating -0.3 to 3.3 V DVS1,2 5, 6 Drain sense voltage referred to source SVS1,2 -3 to 90 V SVS1,2 4, 7 Source sense voltage referred to GND -3 to 3 V Stressing the device above the rating listed in Table 2 may cause permanent damage to the device. Exposure to absolute maximum rated conditions may affect device reliability. DS10811 - Rev 6 page 4/23 SRK2001 Thermal data 4 Thermal data Table 3. Thermal data Symbol Parameter Value Unit Rth j-amb Max. thermal resistance, junction to ambient(1) 130 °C/W Rth j-case Max. thermal resistance, junction to case top(1) 10 °C/W 0.75 W Junction temperature operating range -40 to 150 °C Storage temperature -55 to 150 °C Ptot Tj Tstg Power dissipation at Tamb = 50 °C 1. With the pin 2 soldered to a dissipating copper area of 25 mm2, 35 μm thickness (PCB material FR4 1.6 mm thickness). DS10811 - Rev 6 page 5/23 SRK2001 Typical application schematic 5 Typical application schematic Figure 4. Typical application schematic Vin Q1 L6599A L6699 CRES Q2 Co SR1 SR2 100 Ω 100 Ω SRK2001 Cf DS10811 - Rev 6 VCC EN GND PROG GD1 GD2 SVS1 SVS2 DVS1 DVS2 RPG REN page 6/23 SRK2001 Electrical characteristics 6 Electrical characteristics Table 4. Electrical characteristics (Tj = -25 to 125 °C, VCC = 12 V, CGD1 = CGD2 = 4.7 nF, RPG = 0 Ω; unless otherwise specified, typical values refer to Tj = 25 °C). Symbol Parameter Test condition Min. Typ. Max. Unit Supply section VCC Operating range After turn-on 4.5 - 32 V VCC_On Turn-on supply voltage (1) 4.25 4.5 4.75 V VCC_Off Turn-off supply voltage (1) 4 4.25 4.5 V - 0.25 - V 33 36 39 V Hys Hysteresis VCCZ Clamp voltage ICCZ = 20 mA Iq_run Current consumption in run mode After turn-on (excluding SR MOS gate capacitance charging/ discharging) at 100 kHz - 700 - μA Operating supply current At 300 kHz - 35 - mA Quiescent current Low-consumption mode operation, with DVS1,2 pins not switching(2), Tj = -25 °C to 85 °C - 50 65 μA - - 90 V ICC Iq - Drain-source sensing inputs and synch functions VDS1,2_H Drain-to-source sensing operating voltage - VTH_A Arming voltage Positive-going edge - 1.4 - V VTH_PT Pre-triggering voltage Negative-going edge - 0.7 - V VTH_ON Turn-on threshold Negative-going edge -70 mV Tdiode_off Body diode residual conduction time after turnoff - - 75 - ns TD_On_min Minimum turn-on delay - - 100 - ns - 2 - μs 0.25 0.3 0.35 V 0.45 0.62 0.82 V μA TD_On_max Maximum turn-on delay At 100 kHz -130 -100 Enable pin remote on/off function VEN_OFF Disable threshold VEN_ON Enable threshold IEN_run Sourced current (1)Negative-going edge during run mode (1)Positive-going edge during run mode During run mode 4 6 8 REN = 100 k Ω 1% - 40 - REN = 180 k Ω 1% - 25 - RPG = 0 Ω - 80 - RPG = 100 kΩ 1% - 75 - RPG = 180 kΩ 1% - 65 - RPG open - 60 - RPG = 0 Ω - 75 - RPG = 100 kΩ 1% - 70 - Automatic sleep mode programming DOFF DON DON DS10811 - Rev 6 Min. operating duty cycle to enter sleep mode Restart duty cycle from sleep mode with REN = 100 kΩ 1% Restart duty cycle from sleep mode with REN = 180 kΩ 1% % % % page 7/23 SRK2001 Electrical characteristics Symbol Parameter Test condition DON Restart duty cycle from sleep mode with REN = 180 kΩ 1% Min. Typ. Max. Unit RPG = 180 kΩ 1% - 60 - RPG open - 55 - RPG = 0 Ω - 80 - RPG = 100 kΩ 1% - 75 - RPG = 180 kΩ 1% - 65 - RPG open - 0 - (1)At 9 10 11 μA - -0.35 - A - 4 - A - 140 - ns % Burst-mode exiting programming DON_BM IPROG Restart duty cycle with EN pin open at startup during primary burst mode operation Sourced current VCC startup % Gate drivers Isource_pk Output source peak current Isink_pk_ZCD Max. output sink peak current (3) ZCD comparator triggered turn-off(3) tr Rise time tf Fall time (OFF comparator) OFF comparator triggered turn-off - 80 - ns tf_ZCD Fall time (ZCD comparator) ZCD comparator triggered turn-off - 30 - ns Output clamp voltage IGD = -5 mA; VCC = 20 V; SRK2001/TR 9 11 13 V VCC = 0 to VCC_On, Isink = 5 mA - 1 1.3 V VGDclamp VGDL_UVLO UVLO saturation - 1. Parameters tracking each other. 2. Low consumption mode is one of the following: automatic sleep mode, converter burst mode detect or EN pin pulled low. 3. Parameter guaranteed by design. DS10811 - Rev 6 page 8/23 SRK2001 Operation description 7 Operation description The device block diagram is shown in Figure 1. The SRK2001 can be supplied through the VCC pin by the same converter output voltage, within a wide voltage range (from 4.5 V to 32 V), internally clamped to VCCZ (36 V typical). An internal UVLO (undervoltage lockout) circuit with hysteresis keeps the device switched off at supply voltage lower than the turn-on level VCC_On, with reduced consumption. After the startup, the operation with VCC floating (or disconnected by supply voltage) while pins DVS1,2 are switching is not allowed: this in order to avoid that a dV/dt on the DVS pin causing a high flowing current with possible damage to the IC. The core of the device is the control logic block, implemented by asynchronous logic: this digital circuit generates the logic signals to the output drivers, so that the two external power MOSFET are switched on and off, depending on the evolution of their drain-source voltages, sensed on the DVS-SVS pin pairs through the comparators block. The logic that controls the driving of the two SR MOSFET is based on two gate-driver state machines working in parallel in an interlocked way to avoid switching on both gate drivers at the same time. A third state machine manages the transitions from the normal operation to sleep mode and vice versa. 7.1 Drain voltage sensing The SRK2001 basic operation is such that each synchronous rectifier MOSFET is switched on whenever the corresponding transformer half-winding starts conducting (i.e., when the MOSFET body diode, or an external diode in parallel, starts conducting) and it is then switched off when the flowing current approaches zero. To understand the polarity and the level of this current, the IC is provided with two pairs of pins (DVS1-SVS1 and DVS2-SVS2) that sense the drain-source voltage of either MOSFET (Kelvin sensing). In order to limit dynamic current injection in any condition, at least 100 Ω resistors in series to DVS1,2 pins must be used. Referring to the typical waveforms in Figure 5, there are three significant voltage thresholds: the first one, VTH_A (= 1.4 V), sensitive to positive-going edges, arms the opposite gate driver (interlock function). The second one, VTH_PT (= 0.7 V), sensitive to negative-going edges provides a pre-trigger of the gate driver; the third one VTH-ON is the (negative) threshold that triggers the gate driver as the body diode of the SR MOSFET starts conducting. Depending on the configuration of pins PROG and EN, it has to be verified that the condition VDVS1 > VTH_A and VDVS2 > VTH_A, at the same time, does not fall in a critical range, otherwise the SRK2001 could behave unexpectedly. When the PROG and EN pins are open / open, the critical range is 11.5 to 25 µs, while for configurations other than open / open, it is 6.5 to 15 µs. From an application viewpoint, the operating points/ events to be guaranteed are • During burst mode operation by primary controller (light load operation) : VDVS1 > VTH_A and VDVS2 > VTH_A for more than the upper limit of the range • During well below resonance operation (worst case is minimum input voltage and maximum output load): VDVS1 > VTH_A and VDVS2 > VTH_A for less than the lower limit of the range • 7.2 During protection events by the primary controller that stop switching for a short time: VDVS1 > VTH_A and VDVS2 > VTH_A not within the critical range Turn-on The turn-on logic is such that each SR MOSFET is switched on when the sensed drain- source voltage goes below the VTH_ON threshold: to avoid false triggering of the gate driver, an adaptive masking delay TD_On is introduced. This delay assumes a minimum value at the high load and increases with decreasing load levels. The aim of TD_On is to avoid a premature turn-on at lower load conditions, triggered by capacitive currents (due to secondary side parasitic capacitance and not really related to the current flowing through the MOSFET body diode. DS10811 - Rev 6 page 9/23 SRK2001 Turn-on Figure 5. Typical waveforms Drain-source voltage SR2 Drain-source voltage SR1 I SR1 VTH_A I SR2 VTH_PT VTH_ON GD1 GD2 TCONDUCTION Half-cycle CLK Figure 6 shows the effect of this parasitic: in case at the reduced load a capacitive current spike should trigger the turn-on, there would be a current inversion (flowing from the output capacitor toward the SR MOSFET). This current inversion would cause a discharge of the output capacitor and consequently an increase of the rectified current rms value, in order to balance that discharge; this in turn would affect the converter efficiency. Therefore, the adaptive turn-on delay is aimed to maximize the efficiency in each load operating condition. Figure 7 shows the turn-on at the full load with minimum delay (TD_On_min) and at the reduced load with increased delay (up to TD_On.max equal to 40% of the clock cycle). Figure 6. Capacitive current spike effect at turn-on Capacitive current spike short TD_On I SR I SR gate drive Premature turn-on DS10811 - Rev 6 proper TD_On ISR gate drive Correct turn-on page 10/23 SRK2001 Adaptive turn-off Figure 7. Full load and light load turn-on 50% I SR VDS VDS 50% ISR Blanked turn-off crossing Blanked turn-off crossing VTH_ON VTH_ON Turn-off blanking time Turn-on masking delay Turn-off blanking time Turn-on masking delay Gate drive Gate drive At the startup and on sleep mode exit, the control circuit starts with a turn-on delay set to 30% of the clock cycle and progressively adapts it to the proper value. This allows reducing system perturbation both during the startup and while exiting the sleep mode during a fast zero to full load transition. After the turn-on, a blanking time (equal to 50% of the clock period) masks an undesired turn-off due to the drain-source voltage drop, consequent to MOSFET switch on (flowing current passes from the body diode to MOSFET channel resistance). 7.3 Adaptive turn-off The SR MOSFET turn-off may be triggered by an adaptive turn-off mechanism (two slope turn-off) or by the ZCD_OFF comparator (fast turn-off, see Section 7.4 ). Due to the stray inductance in series with the SR MOSFET RDS(on) (mainly the package stray inductance), the sensed drain-source signal is not really equal to the voltage drop across the MOSFET RDS(on), but it anticipates the time instant where the current reaches zero, causing a premature MOSFET turn-off. To overcome this problem (without adding any stray inductance compensation circuit), the device uses a turn-off mechanism based on an adaptive algorithm that turns off the SR MOSFET when the sensed drain voltage reaches zero adapting progressively the turn-off to the maximum conduction period. Figure 8. Adaptive turn-off VDS I SR V V Gate drive VDS I SR VTH_ON TH_ON TH_ON DS10811 - Rev 6 VDS I SR t diode Gate drive T T+ Tn Tn + 1 t0 Gate drive T+ t0 + t1 Tn + k page 11/23 SRK2001 ZCD comparator Figure 8 shows this adaptive algorithm: cycle-by-cycle the conduction time is maximized, allowing in a steadystate the maximum converter efficiency. During the startup and on sleep mode exit, the control circuit turns off the SR MOSFET at 50% of the clock cycle and progressively adapts this delay in order to maximize the SR MOSFET conduction time to help reduce system perturbations. 7.4 ZCD comparator The IC is equipped with a ZCD comparator that is always ready to quickly turn-off the SR MOSFET to avoid current inversion that would cause SR MOSFET failure and even half bridge destruction, if the primary controller not equipped with proper protections. The ZCD (zero current detection) comparator acts during fast load transitions or the short-circuit operation and when the above resonance operation occurs. It senses that the current has reached the zero level and triggers the gate drive circuit for a very fast MOSFET turn-off (with a total delay time TD_Off). The ZCD comparator threshold is not fixed but self-adaptive. In the steady-state load operation and in case of slow load transitions, the turn-off is prevalently managed by the adaptive mechanism (characterized by the two slope turn-off driving). Instead, during fast transitions or during above resonance operation, the ZCD_OFF comparator will take over, causing a fast MOSFET switch-off that prevents undesired current inversions. The ZCD_OFF comparator is blanked for 450 ns after the turn-on. Depending on SR MOSFET choice, some premature turn-off triggered by the ZCD_OFF comparator may be found due to the noise present on the drain-source sensed signal: this is worse with lower RDS_ON (due to worse signal to noise ratio) and lower stray inductance of the MOSFET package. Normally the load level where this may happen is such that the circuit has already entered a low consumption state (for example in burst mode from primary controller); if this is not the case, some noise reduction may be helpful, for example by using RC snubbers across the SR MOSFET drain-source. 7.5 Gate drive The IC is provided with two high current gate-drive outputs, each capable of driving one or more N-channel power MOSFET in parallel. The high-level voltage provided by the driver is clamped at VGDclamp in order to avoid excessive voltage levels on the gate in case the device is supplied with a high VCC, thus minimizing the gate charge provided in each switching cycle. The two gate drivers have a pull-down capability that ensures the SR MOSFET cannot be spuriously turned on even at low VCC: in fact, the drivers have a 1 V (typ.) saturation level at VCC below the turn-on threshold. As described in the previous paragraphs, either the SR MOSFET is switched on after the current starts flowing through the body diode, when the drain-source voltage is already low (equal to VF); therefore there is no Miller effect nor switching losses at the MOSFET turn-on, in which case the drive doesn't need to provide a fast turn-on. Also at the turn-off, during steady-state load conditions, when the decision depends on the adaptive control circuitry, there is no need to have a very fast drive with hard pull-down because the current has not yet reached zero and the operation is far from the current inversion occurrence. Moreover, slow transitions also help reduce the perturbation introduced into the system that arise due to the MOSFET turn-on and turn-off, contributing to improve the overall behavior of the LLC resonant converter. On the other side, during very fast load transitions or the short-circuit operation, when the turn-off decision is taken by ZCD logic, the MOSFET turn-off needs to be very fast to avoid current inversion: therefore the two gate drivers are designed to guarantee for a very short turn-off total delay TD_Off. In order to avoid current inversions, the SRK2001 stops driving SR MOSFET during any operating condition where the converter enters deeply into the below resonance region (i.e., switching frequency falls lower than 60% of resonance frequency). DS10811 - Rev 6 page 12/23 SRK2001 Intelligent automatic sleep mode 7.6 Intelligent automatic sleep mode A unique feature of this IC is its intelligent automatic sleep mode. The logic circuitry is able to detect a light-load condition for the converter and stop gate driving, reducing also the IC quiescent consumption. This improves converter efficiency at the light-load, where the power losses on the rectification body diodes (or external diodes in parallel to the MOSFET) become lower than the power losses in the MOSFET and those related to their driving. The IC is also able to detect an increase of the converter's load and automatically restarts gate driving. The algorithm used by the intelligent automatic sleep mode is based on a dual time measurement system: the duration of the half-switching period (i.e., the clock cycle in Figure 5) and the duration of the conduction time of the synchronous rectifier. The duration of a clock cycle is measured from the falling edge of a clock pulse to the rising edge of the subsequent clock pulse; the duration of the SR MOSFET conduction is measured from the moment its body diode starts conducting (drain-source voltage falling below VTH-ON) to the moment the gate drive is turned off, in case the device is operating, or to the moment the body diode ceases to conduct (drain-to-source voltage going above VTH-ON) during the sleep mode operation. While at the full load the SR MOSFET conduction time occupies almost 100% of the half-switching cycle, as the load is reduced, the conduction duty cycle is reduced and, as it falls below DOFF (see data in Table 4), the device enters the sleep mode. To prevent wrong decisions, the sleep mode condition must be confirmed for 512 consecutive clock cycles. Once in the sleep mode, SR MOSFET gate driving is re-enabled when the conduction duty cycle of the body diode (or the external diodes in parallel to the MOSFET) exceeds DON: the number of clock cycles needed to exit the sleep mode is proportional to the difference between the body diode conduction duty cycle and the programmed DON threshold. This allows a faster sleep-out in case of the heavy load transient low-to-high. Furthermore, in order to reduce the perturbation introduced by a sudden sleep mode state entering, a soft-sleep transition procedure is adopted, that progressively decreases the conduction time before entering the sleep mode state. After entering the sleep mode, timing is ignored for 8 switching cycles respectively to let the resulting transient in the output current fade-out, then the timing check is enabled. The automatic sleep mode function can be disabled by keeping the EN pin open at startup (see Section 5.8). This may be beneficial to the overall system behavior in case of conflict with the burst mode operation of the half-bridge converter driven by the primary controller. When automatic sleep mode is disabled, the SRK2001 can enter low consumption state (during which SR MOSFETs cannot be turned on) when it recognizes an interruption in the switching activity by the primary controller. 7.7 Burst-mode operation Normally, at reduced loads, resonant converters enter burst mode operation in order to increase converter efficiency. The SRK2001 detects that the primary controller has stopped switching and enters its low consumption state. The condition to detect burst mode operation is that both DVS1,2 pins are above the arming voltage VTH_A for at least 20 μs (typ). After the primary controller restarts switching, the SRK2001 resumes operation when it detects that the conduction duty cycle has increased above the value DON_BM programmed by the user through a proper choice of the RPG resistor (see Table 7). The number of clock cycles needed to exit burst mode is proportional to the difference between the body diode conduction duty cycle and the programmed DON threshold: this allows a faster sleep-out in case of the heavy load transient low-to-high. After recognizing that the conduction duty cycle is longer than the programmed DON, 12 switching cycles (i.e., 24 clock cycles) are still needed before the SRK2001 restarts driving the SR MOSFET (in order to allow the settlement of the internal timers, lost during the low consumption state, where most of the internal circuitry was not supplied or turned off). 7.8 EN and PROG pins: function and usage The EN pin and PROG pin allow the user to configure two different operating modes: • Automatic sleep mode function enabled (described in Section 7.6 ) • Automatic sleep mode function disabled The configuration is set when the VCC supply voltage rises above the turn-on threshold VCC_ON and the EN pin voltage is higher than the enable threshold (VEN_ON): during this pin-strap phase, the voltages on EN and PROG pins are detected and the corresponding values of DON and DOFF (see Table 5 and Table 6) are internally stored as long as VCC is within the supply range and EN pin voltage is above the disable threshold (VEN_OFF). DS10811 - Rev 6 page 13/23 SRK2001 EN and PROG pins: function and usage During normal operation the EN pin can be used as remote on-off input, using a small signal transistor connected to the pin, as shown in Figure 9: when the switch is closed, the pin voltage goes below the VEN_OFF threshold, the controller stops operating and enters a low consumption state; it resumes the operation when the switch is opened and the pin voltage surpasses the VEN_ON threshold. With VCC supply in the operating range, the pinstrap phase is repeated each time that the EN pin is driven low to high (above the VEN_ON threshold) during user remote ON-OFF. Figure 9. EN - PROG pin configurations AUTOMATIC SLEEP MODE CONFIG. NO AUTOMATIC SLEEP MODE CONFIG. R EN EN EN SRK2001 SRK2001 R PG PROG 7.8.1 R PG PROG Automatic sleep mode function enabled Automatic sleep mode is enabled when a resistor equal or below 180 kΩ is connected from the EN pin to GND during the startup phase (see Figure 9). During the startup phase (when the external NPN switch has to be kept open), an internal current generator IEN is enabled: its current is sourced to the EN pin and sets the voltage across the external resistor REN. By using a resistance value equal or below 180 kΩ, the voltage stays below the internal threshold and the automatic sleep mode function is enabled. The voltage level (i.e. the resistance value) also sets the conduction time (in terms of duty cycle) below which the SRK2001 enters sleep mode (see Table 5 and Table 6, DOFF column). The configuration is internally stored and then the internal current generator IEN is decreased to IEN_run. At the same time, during the startup phase, another internal current generator IPROG is enabled: its current is sourced to the PROG pin and sets the voltage across the external resistor RPG. Depending on this voltage level, the conduction time (in terms of duty cycle) above which the SRK2001 exits from sleep mode is set (see Table 5 and Table 6, DON column). This configuration is internally stored and then the internal current generator IPROG is disabled. The lookup tables show the allowed conduction time combinations, depending on REN and RPG values (1% tolerance resistors are recommended). DS10811 - Rev 6 page 14/23 SRK2001 EN and PROG pins: function and usage Table 5. Lookup table I: REN = 100 kΩ DOFF 40% DON RPG 80% RPG = 0 Ω 75% RPG = 100 kΩ 65% RPG = 180 kΩ 60% RPG open Table 6. Lookup table II: REN = 180 kΩ DOFF 25% 7.8.2 DON RPG 75% RPG = 0 Ω 70% RPG = 100 kΩ 60% RPG = 180 kΩ 55% RPG open Automatic sleep mode function disabled Automatic sleep mode is disabled when the EN pin is open during startup phase (see Figure 9). During the startup phase (when the external NPN switch is open), an internal pull-up brings the EN pin to a voltage above the internal threshold so that the automatic sleep mode function is disabled. The configuration is internally stored. At the same time, during the startup phase, another internal current generator IPROG is enabled: its current is sourced to the PROG pin and sets the voltage across the external resistor RPG. Depending on this voltage level, the conduction time (in terms of duty cycle) above which the SRK2001 exits from low consumption state, resuming normal operation, is set (see Table 7). This configuration is internally stored and then the internal current generator IPROG is disabled. When automatic sleep mode is disabled, the SRK2001 can no longer enter the low consumption state if the conduction duty cycle reduces, because of reduced load. However, the SRK2001 recognizes burst mode operation by the primary controller (or an external turn-off command on the EN pin). When half-bridge switching is stopped, the SRK2001 detects burst mode operation and enters the low consumption state, during which SR MOSFET cannot be turned on (see Section 7.7 ). As the primary controller restarts switching (or the EN pin goes back high), the SRK2001 resumes the operation when it detects that the conduction duty cycle has increased above the value DON_BM programmed by the user through a proper choice of the RPG resistor as summarized in Table 7. Table 7. Lookup table I: REN = 100 kΩ DS10811 - Rev 6 DON_BM RPG 80% RPG = 0 Ω 75% RPG = 100 kΩ 65% RPG = 180 kΩ 0% RPG open page 15/23 SRK2001 Layout guidelines 7.9 Layout guidelines The GND pin is the return of the bias current of the device and return for gate drive currents: it should be routed to the common point where the source terminals of both synchronous rectifier MOSFET are connected. When laying out the PCB, care must be taken in keeping the source terminals of both SR MOSFET as close to one another as possible and routing the trace that goes to the GND separately from the load current return path. This trace should be as short as possible and be as close to the physical source terminals as possible. Keeping the layout as geometrically symmetrical as possible will help render circuit operation electrically symmetrical. Also drain-source voltage sensing should be performed as physically close to the drain and source terminals as possible in order to minimize the stray inductance involved by the load current path that is in the drain-to-source voltage sensing circuit. The use of bypass capacitors between the VCC and GND is recommended. They should be low-ESR, low-ESL type and located as close to the IC pins as possible. Sometimes, a series resistor (in the tens of ohms) between the converter output voltage and the VCC pin, forming an RC filter along with the by-pass capacitor, can help obtain a cleaner VCC voltage. DS10811 - Rev 6 page 16/23 SRK2001 Package information 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 8.1 SSOP10 package information Figure 10. SSOP10 package outline DS10811 - Rev 6 page 17/23 SRK2001 SSOP10 package information Table 8. SSOP10 package mechanical data Symbol Dimensions (mm) Min. Typ. Max. A - - 1.75 A1 0.10 - 0.225 A2 1.30 1.40 1.50 A3 0.60 0.65 0.70 b 0.39 - 0.47 b1 0.38 0.41 0.44 c 0.20 - 0.24 c1 0.19 0.20 0.21 D 4.80 4.90 5 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e DS10811 - Rev 6 1.00 BSC h 0.25 - 0.50 L 0.50 - 0.80 K 0° - 8° page 18/23 SRK2001 Revision history Table 9. Document revision history Date Version Changes 16-Jan-2015 1 Initial release. 09-Feb-2015 2 Updated Table 5 on page 7 (updated “VGDclamp” - SRK2001L/LTR -removed “RGATE = 5.6 Ω”, removed min. and max. values). 12-May-2015 3 14-Feb-2017 4 Updated Section 5.5 on page 13. Minor modifications throughout document. Removed “SRK2001L/LTR” and “logic level MOSFETS” from Features, Table 1, Table 2, Table 5, and Section 5.5. Minor modifications throughout document. Updated Section 5.6 6-Sept-2018 5 Added Section 5.7: Burst mode operation Updated Section 5.8: EN and PROG pins: function and usage Throughout document: • updated document template • Section, figure and table indexes moved to bottom of document • minor text edits Old Section 1 "Block diagrams and pin connections" split into: • Section 1 Block diagrams • Section 2 Pin connections and functions Old Section 2 Maximum ratings" split into: 02-Sep-2021 6 • Section 3 Absolute maximum ratings • Section 4 Thermal data In Section 7.1 Drain voltage sensing: • Added new paragraphs, starting with "Depending on the configuration of pins PROG and EN..." In Section 7.7 Burst-mode operation: • Removed sentence from "For the correct operation of the SRK2001..." to "...it is recommended to keep the PROG pin open" In Section 7.8 EN and PROG pins: function and usage: • Updated paragraph "The configuration is set ..." • Replaced sentence "The small signal transistor has to be …" with "With VCC supply in the operating range..." In Section 8.1 SSOP10 package information: DS10811 - Rev 6 • updated Figure 10. SSOP10 package outline • updated Table 8. SSOP10 package mechanical data page 19/23 SRK2001 Contents Contents 1 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Pin connections and functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 5 Typical application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Operation description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 7.1 Drain voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.3 Adaptive turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.4 ZCD comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.5 Gate drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.6 Intelligent automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.7 Burst-mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.8 EN and PROG pins: function and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.9 8 7.8.1 Automatic sleep mode function enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.8.2 Automatic sleep mode function disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 8.1 SSOP10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 DS10811 - Rev 6 page 20/23 SRK2001 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. DS10811 - Rev 6 Internal block diagram . . . . . . . . . . . . . Typical system block diagram . . . . . . . . Pin connections (top view) . . . . . . . . . . Typical application schematic . . . . . . . . Typical waveforms . . . . . . . . . . . . . . . Capacitive current spike effect at turn-on Full load and light load turn-on . . . . . . . Adaptive turn-off . . . . . . . . . . . . . . . . . EN - PROG pin configurations . . . . . . . SSOP10 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 2 . 3 . 6 10 10 11 11 14 17 page 21/23 SRK2001 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Pin functions . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . Thermal data. . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . Lookup table I: REN = 100 kΩ . . . . Lookup table II: REN = 180 kΩ . . . . Lookup table I: REN = 100 kΩ . . . . SSOP10 package mechanical data Document revision history . . . . . . . DS10811 - Rev 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 5 . 7 15 15 15 18 19 page 22/23 SRK2001 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS10811 - Rev 6 page 23/23