ST10F269Z1-ST10F269Z2
16-bit MCU with MAC unit,
128- to 256-Kbyte Flash memory and 12-Kbyte RAM
Datasheet - production data
Features
• High performance 32 or 40 MHZ CPU with
DSP function
– 16-bit CPU With 4-stage pipeline
– 50 ns (or 62.5 ns) instruction cycle time at
40 MHz (or 32 MHz) max CPU Clock
– Multiply/accumulate unit (Mac) 16 X 16-bit
multiplication, 40-bit accumulator
– Repeat unit
– Enhanced boolean bit manipulation
facilities
– Additional instructions to support HLL and
operating systems
– Single-cycle context switching support
• Memory organization
– 128 - or 256-Kbyte on-chip Flash memory
single voltage with erase/program
controller
– Up to 1K erasing/programming cycles
– Up to 16-Mbyte linear address space for
code and data (5 Mbytes with CAN)
– 2-Kbyte on-chip internal RAM (IRAM)
– 10- Kbyte on-chip extension RAM (XRAM)
• Fast and flexible bus
– Programmable external bus characteristics
for different address ranges
– 8-bit or 16-bit external data bus
– Multiplexed or demultiplexed external
address / data buses
– Five programmable chip-select signals
– Hold-acknowledge bus arbitration support
• Interrupt
– 8-channel peripheral event controller for
single cycle interrupt driven data transfer
– 16-priority-level interrupt system with 56
sources, sampling rate down to 25 ns at
40 MHz (31.25 ns at 32 MHz)
September 2017
This is information on a product in full production.
TQFP144 (20 x 20 x 1.40 mm) (Thin Quad Flat Pack)
• Timers: two multi-functional general purpose
timer units with 5 timers
• Two 16-channel capture / compare units
• A/D converter
– 16-channel 10-bit
– 4.85 µs conversion time at 40 MHz CPU
clock (6.06 µs at 32 MHz)
• 4-channel PWM unit
• Serial channels
– Synchronous / asynchronous serial
channel
– High-speed synchronous channel
• Two CAN 2.0B interfaces operating on 1 or 2
CAN buses (30 or 2x15 message objects)
• Fail-safe protection
– Programmable watchdog timer
– Oscillator watchdog
• On-chip bootstrap loader
• Clock generation
– On-chip PLL
– Direct or prescaled clock input
• Real time clock
• Up to 111 general purpose I/O lines
– Individually programmable as Input, output
or special function
– Programmable threshold (hysteresis)
• Idle and Power-down modes
• Single voltage supply: 5V ±10% (embedded
regulator for 2.7 or 3.3 V core supply).
• Temperature ranges: -40 +125°C/ -40 to 85°C
• 144-pin TQFP package
DocID13266 Rev 2
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Contents
ST10F269Z1-ST10F269Z2
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
Pin Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Internal Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2
Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3
5.2.1
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.2
Instructions and Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.3
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.4
Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.5
Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.6
In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.7
Read/Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.8
Power Supply, Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Architectural Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.1
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.2
Command Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.3
Ready/Busy Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.4
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.5
Flash Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.6
Instructions Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.7
Reset Processing and Initial State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4
Flash Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.6
5.5.1
Handling of Flash Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5.2
Basic Flash Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.5.3
Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.6.1
2/206
Entering the Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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5.6.2
Memory Configuration After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.6.3
Loading the Startup Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.6.4
Exiting Bootstrap Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.6.5
Choosing the Baud Rate for the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.1
Multiplier-accumulator Unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.1.1
7
8
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.2
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3
MAC Coprocessor Specific Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 50
External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.1
Programmable Chip Select Timing Control . . . . . . . . . . . . . . . . . . . . . . . 55
7.2
READY Programmable Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.2
Interrupt Registers and Vectors Location List . . . . . . . . . . . . . . . . . . . . . . 57
8.3
Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.4
Exception and Error Traps List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9
Capture/Compare (CAPCOM) Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10
General Purpose Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1
GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.2
GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11
PWM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.2
I/Os Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.2.1
Open Drain Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.2.2
Input Threshold Control
12.2.3
Output Driver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.2.4
Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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12.3
PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.3.1
12.4
PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.4.1
12.5
12.9
Alternate Functions of Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.7.1
12.8
Alternate Functions of Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.6.1
12.7
Alternate Functions of PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12.5.1
12.6
Alternate Functions of PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Alternate Functions of Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.8.1
Alternate Functions of Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.8.2
Port 5 Schmitt Trigger Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.9.1
Alternate Functions of Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.10 Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.10.1 Alternate Functions of Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.11 Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
12.11.1 Alternate Functions of Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
13
A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
14
Serial Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.1
14.2
15
14.1.1
ASCO in Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.1.2
ASCO in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
High Speed Synchronous Serial Channel (SSC) . . . . . . . . . . . . . . . . . . .117
CAN Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
15.1
15.2
4/206
Asynchronous / Synchronous Serial Interface (ASCO) . . . . . . . . . . . . . .112
CAN Modules Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
15.1.1
CAN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
15.1.2
CAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
CAN Bus Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
15.2.1
Single CAN Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
15.2.2
Multiple CAN Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
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Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
16.1
16.2
RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
16.1.1
RTCCON: RTC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
16.1.2
RTCPH & RTCPL: RTC PRESCALER Registers . . . . . . . . . . . . . . . . 124
16.1.3
RTCDH & RTCDL: RTC DIVIDER Counters . . . . . . . . . . . . . . . . . . . . 125
16.1.4
RTCH & RTCL: RTC Programmable COUNTER Registers . . . . . . . . 126
16.1.5
RTCAH & RTCAL: RTC ALARM Registers . . . . . . . . . . . . . . . . . . . . . 126
Programming the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
17
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
18
System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
18.1
20
18.1.1
Asynchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
18.1.2
Synchronous Reset
(RSTIN pulse > 1040TCL and RPD pin at high level) . . . . . . . . . . . . . 134
18.1.3
Exit of Long Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
18.2
Short Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
18.3
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
18.4
Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
18.5
RSTOUT, RSTIN, Bidirectional Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 137
18.6
19
Long Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
18.5.1
RSTOUT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
18.5.2
Bidirectional Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
18.5.3
RSTIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Power Reduction Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
19.1
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
19.2
Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
19.2.1
Protected Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
19.2.2
Interruptible Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Special Function Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 146
20.1
Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
20.2
System Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
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Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
21.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
21.2
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
21.3
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
21.4
21.3.1
A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
21.3.2
Conversion Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
21.4.1
Test Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
21.4.2
Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
21.4.3
Clock Generation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
21.4.4
Prescaler Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
21.4.5
Direct Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
21.4.6
Oscillator Watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
21.4.7
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
21.4.8
External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
21.4.9
Memory Cycle Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
21.4.10 Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
21.4.11 Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
21.4.12 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
21.4.13 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
21.4.14 High-Speed Synchronous Serial Interface (SSC) Timing . . . . . . . . . . 194
22
Package Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
23
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
24
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
24.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
24.2
Functional problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
24.3
6/206
24.2.1
PWRDN.1 - Execution of PWRDN Instruction . . . . . . . . . . . . . . . . . . . 201
24.2.2
MAC.9 - CoCMP Instruction Inverted Operands . . . . . . . . . . . . . . . . . 201
24.2.3
MAC.10 - E Flag Evaluation for CoSHR and CoASHR Instructions
when Saturation Mode is Enabled 202
24.2.4
ST_PORT.3 - Bad Behavior of Hysteresis Function
on Input Falling Edge 203
Deviations from DC/AC preliminary specification . . . . . . . . . . . . . . . . . . 204
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
25
Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
DocID13266 Rev 2
7/206
7
List of tables
ST10F269Z1-ST10F269Z2
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
8/206
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
128-Kbyte or 256-Kbyte Flash Memory Block Organization . . . . . . . . . . . . . . . . . . . . . . . . 25
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory Configuration after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
MAC specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Pointer Post-modification Combinations for IDXi and Rwn. . . . . . . . . . . . . . . . . . . . . . . . . 53
MAC Registers Referenced as ‘CoReg‘ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Trap Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Compare Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
CAPCOM Timer Input Frequencies, Resolution and Periods (fCPU = 40 MHz) . . . . . . . . 64
CAPCOM Timer Input Frequencies, Resolution and Periods (fCPU = 32MHz) . . . . . . . . . 64
GPT1 Timer Input Frequencies, Resolution and Periods (fCPU = 40 MHz). . . . . . . . . . . . 66
PT1 Timer Input Frequencies, Resolution and Periods (fCPU = 32 MHz) . . . . . . . . . . . . . 66
GPT2 Timer Input Frequencies, Resolution and Period (fCPU = 40 MHz). . . . . . . . . . . . . 67
GPT2 Timer Input Frequencies, Resolution and Period (fCPU = 32 MHz). . . . . . . . . . . . . 67
PWM Unit Frequencies and Resolution at 40 MHz CPU Clock . . . . . . . . . . . . . . . . . . . . . 69
PWM Unit Frequencies and Resolution at 32 MHz CPU Clock . . . . . . . . . . . . . . . . . . . . . 70
Port Control Register Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Alternate Functions of Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Port 3 Alternative Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Port 4 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Port 5 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Port 6 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Port 7 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Port 8 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ADC Sample Clock and Conversion Clock at fCPU = 40 MHz. . . . . . . . . . . . . . . . . . . . . 110
ADC Sample Clock and Conversion Clock at fCPU = 32MHz . . . . . . . . . . . . . . . . . . . . . 111
Commonly Used Baud Rates by Reload Value and Deviation Errors at fCPU = 40 MHz 114
Commonly Used Baud Rates by Reload Value and Deviation Errors at fCPU = 32 MHz 114
Commonly Used Baud Rates by Reload Value and Deviation Errors (fCPU = 40 MHz) . 116
Commonly Used Baud Rates by Reload Value and Deviation Errors (fCPU = 32 MHz) . 116
Synchronous Baud Rate and Reload Values (fCPU = 40MHz) . . . . . . . . . . . . . . . . . . . . 118
Synchronous Baud Rate and Reload Values (fCPU = 32MHz) . . . . . . . . . . . . . . . . . . . . 118
WDTCON Bit Value on Different Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
WDTREL Reload Value (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
WDTREL Reload Value (fCPU = 3 2MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Reset Event Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PORT0 Latched Configuration for the Different Resets . . . . . . . . . . . . . . . . . . . . . . . . . . 140
PORT0 Bits Latched into the Different Registers After Reset. . . . . . . . . . . . . . . . . . . . . . 140
Special Function Registers Listed by Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
ADC Sampling and Conversion Timing (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . 166
ADC Sampling and Conversion Timing (fCPU = 32 MHz) . . . . . . . . . . . . . . . . . . . . . . . . 166
CPU Frequency Generation (CPU clock in the range 1 to 40 MHz) . . . . . . . . . . . . . . . . . 168
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
List of tables
CPU Frequency Generation (CPU clock in the range 1 to 32 MHz) . . . . . . . . . . . . . . . . . 168
External Clock Drive XTAL1 (max fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
External Clock Drive XTAL1 (max fCPU = 32 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Memory Cycle Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Multiplexed Bus Characteristics (max fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Multiplexed Bus Characteristics (max fCPU = 32 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Demultiplexed Bus Characteristics (max fCPU = 40 MHz). . . . . . . . . . . . . . . . . . . . . . . . 181
Demultiplexed Bus Characteristics (max fCPU = 32 MHz). . . . . . . . . . . . . . . . . . . . . . . . 182
CLKOUT and READY Characteristics (max fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . 189
CLKOUT and READY Characteristics (max fCPU = 32 MHz) . . . . . . . . . . . . . . . . . . . . . 189
external Bus Arbitration (max fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
External Bus Arbitration (max fCPU = 32 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Master Mode (max fCPU = 40 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Master Mode (max fCPU = 32 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Slave Mode (max fCPU = 40 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Slave Mode (max fCPU = 32 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
MAC.10 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
History of Fixed Functional Problems of the ST10F269Zxxx-D . . . . . . . . . . . . . . . . . . . . 203
Summary of Remaining Functional Problems Known on the ST10F269Zxxx-D . . . . . . . 204
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
DocID13266 Rev 2
9/206
9
List of figures
ST10F269Z1-ST10F269Z2
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
10/206
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ST10F269Z1-ST10F269Z2 On-chip Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bootstrap Loader Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Hardware Provisions to Activate the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Baud Rate Deviation Between Host and ST10F269Z1-ST10F269Z2 . . . . . . . . . . . . . . . . 44
CPU Block Diagram (MAC Unit not included). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MAC Unit Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chip Select Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CAPCOM Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Block Diagram of CAPCOM Timers T0 and T7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Block Diagram of CAPCOM Timers T1 and T8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Block Diagram of GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Block Diagram of GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Block Diagram of PWM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O lines support an alternate function (detailed in the following description
of each port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Output Drivers in Push-pull Mode and in Open Drain Mode. . . . . . . . . . . . . . . . . . . . . . . . 74
Hysteresis for Special Input Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PORT0 I/O and Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Block Diagram of a PORT0 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PORT1 I/O and Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Block Diagram of a PORT1 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
PORT2 I/O and Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Block Diagram of a PORT2 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PORT3 I/O and Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Block Diagram of Port 3 Pin with Alternate Input or Alternate Output Function . . . . . . . . . 90
Block Diagram of Pins P3.15 (CLKOUT) and P3.12 (BHE/WRH) . . . . . . . . . . . . . . . . . . . 91
PORT4 I/O and Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Block Diagram of a Port 4 Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Block Diagram of P4.4 and P4.5 Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Block Diagram of P4.6 and P4.7 Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
PORT5 I/O and Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Block Diagram of a Port 5 Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
PORT6 I/O and Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Block Diagram of Port 6 Pins with an Alternate Output Function . . . . . . . . . . . . . . . . . . . 101
Block Diagram of Pin P6.5 (HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
PORT 7 I/O and Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Block Diagram of Port 7 Pins P7.3...P7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Block Diagram of Port 7 Pins P7.7...P7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PORT 8I/O and Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Block Diagram of Port 8 Pins P8.7...P8.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Asynchronous Mode of Serial Channel ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Synchronous Mode of Serial Channel ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Synchronous Serial Channel SSC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Single CAN Bus Multiple Interfaces, Multiple Transceivers . . . . . . . . . . . . . . . . . . . . . . . 120
Single CAN Bus, Dual Interfaces, Single Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
List of figures
Connection to Two Different CAN Buses (e.g. for gateway application). . . . . . . . . . . . . . 121
ESFRs and Port Pins Associated with the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
RTC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
PRESCALER Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
DIVIDER Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Asynchronous Reset Sequence External Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Asynchronous Reset Sequence Internal Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Synchronous Reset Sequence External Fetch (RSTIN pulse > 1040 TCL) . . . . . . . . . . . 135
Synchronous Warm Reset Sequence External Fetch (4 TCL < RSTIN pulse < 1038 TCL 136
Internal (simplified) Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Minimum External Reset Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
External Reset Hardware Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
External R0C0 Circuit on RPD Pin For Exiting Powerdown Mode with External Interrupt 143
Simplified Powerdown Exit Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Powerdown Exit Sequence When Using an External Interrupt (PLL x 2) . . . . . . . . . . . . . 145
Supply / Idle Current as a Function of Operating Frequency . . . . . . . . . . . . . . . . . . . . . . 164
Input / Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Float Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Generation Mechanisms for the CPU Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Approximated Maximum PLL Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
External Memory Cycle: Multiplexed Bus, With/Without Read/Write Delay,
Normal ALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
External Memory Cycle: Multiplexed Bus, With/Without Read/Write Delay,
Extended ALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
External Memory Cycle: Multiplexed Bus, With/Without Read/Write Delay,
Normal ALE, Read / Write Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
External Memory Cycle: Multiplexed Bus, With/Without Read/Write Delay,
Extended ALE, Read / Write Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
External Memory Cycle: Demultiplexed Bus, With/Without Read/Write Delay,
Normal ALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
External Memory Cycle: Demultiplexed Bus, With/Without Read/Write Delay,
Extended ALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
External Memory Cycle: Demultiplexed Bus, With/Without Read/Write Delay,
Normal ALE, Read/Write Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
External Memory Cycle: Demultiplexed Bus, no Read/Write Delay,
Extended ALE, Read /Write Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
External Bus Arbitration (Releasing the Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
External Bus Arbitration (Regaining the Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
SSC Master Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
SSC Slave Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Package Outline TQFP144 (20 x 20 x 1.40 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Bad behavior of hysteresis function on input falling edge. . . . . . . . . . . . . . . . . . . . . . . . . 203
DocID13266 Rev 2
11/206
11
Introduction
1
ST10F269Z1-ST10F269Z2
Introduction
The ST10F269Z1-ST10F269Z2 are derivatives of the STMicroelectronics ST10 family of
16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 20
million instructions per second) with high peripheral functionality and enhanced I/Ocapabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip highspeed RAM, and clock generation via PLL.
The ST10F269Z1-ST10F269Z2 are processed in 0.35 mm CMOS technology. The MCU
core and the logic is supplied with a 5 V to 2.7 V on chip voltage regulator. The part is
supplied with a single 5 V supply and I/Os work at 5 V.
The device is upward compatible with the ST10F168 device, with the following set of
differences:
12/206
•
The Multiply/Accumulate unit is available as standard. This MAC unit adds powerful
DSP functions to the ST10 architecture, but maintains full compatibility for existing
code.
•
Flash control interface is now based on STMicroelectronics third generation of standalone Flash memories, with an embedded Erase/Program Controller. This completely
frees up the CPU during programming or erasing the Flash.
•
128-Kbyte Flash Option
•
Two dedicated pins (DC1 and DC2) on the 144-pin package are used for decoupling
the internally generated 2.7V core logic supply. Do not connect these two pins to 5.0 V
external supply. Instead, these pins should be connected to a decoupling capacitor
(ceramic type, value ≥ 330 nF).
•
The A/D Converter characteristics are different from previous ST10 derivatives ones.
Refer to Section 21.3.1: A/D Converter Characteristics.
•
The characterization is performed with CL = 50 pF max on output pins.
Refer to Section 21.3: DC Characteristics.
•
In order to reduce EMC, the rise/fall time and the sink/source capability of the drivers of
the I/O pads are programmable. Refer to Section 12.2: I/Os Special Features.
•
The Real Time Clock functionality is added.
•
The external interrupt sources can be selected with the EXISEL register.
•
The reset source is identified by a dedicated status bit in the WDTCON register.
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Introduction
Figure 1. Logic Symbol
VDD DC1 DC2
VSS
XTAL1
XTAL2
Port 0
16-bit
RSTIN
Port 1
16-bit
RSTOUT
RPD
VAREF
Port 2
16-bit
VAGND
NMI
EA
ST10F269
Port 3
15-bit
Port 4
8-bit
READY
ALE
Port 6
8-bit
RD
WR/WRL
Port 7
8-bit
Port 5
16-bit
Port 8
8-bit
DocID13266 Rev 2
13/206
205
Pin Data
2
ST10F269Z1-ST10F269Z2
Pin Data
ST10F269
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VAREF
VAGND
P5.10/AN10/T6EUD
P5.11/AN11/T5EUD
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.14/AN14/T4EUD
P5.15/AN15/T2EUD
VSS
VDD
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
VSS
DC1
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IOEX2IN
P2.11/CC11IOEX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN/T7IN
P3.0/T0IN
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
VSS
VDD
P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4
P6.5/HOLD
P6.6/HLDA
P6.7/BREQ
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO
DC2
VSS
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P7.4/CC28I0
P7.5/CC29I0
P7.6/CC30I0
P7.7/CC31I0
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
P5.8/AN8
P5.9/AN9
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
VSS
NMI
RSTOUT
RSTIN
VSS
XTAL1
XTAL2
VDD
P1H.7/A15/CC27IO
P1H.6/A14/CC26IO
P1H.5/A13/CC25IO
P1H.4/A12/CC24IO
P1H.3/A11
P1H.2/A10
P1H.1/A9
P1H.0/A8
VSS
VDD
P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9
VSS
VDD
Figure 2. Pin Configuration (top view)
14/206
DocID13266 Rev 2
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P0H.0/AD8
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2AD2
P0L.A/AD1
P0L.0/AD0
EA
ALE
READY
WR/WRL
RD
VSS
VDD
P4.7A23/CAN2_TxD
P4.6A22/CAN1_TxD
P4.5A21/CAN1_RxD
P4.4A20/CAN2_RxD
P4.3/A19
P4.2/A18
P4.1/A17
P4.0/A16
RPD
VSS
VDD
P3.15/CLKOUT
P3.13/SCLK
P3.12/BHE/WRH
P3.11/RXD0
P3.10/TXD0
P3.9/MTSR
P3.8/MRST
P3.7/T2IN
P3.6/T3IN
ST10F269Z1-ST10F269Z2
Pin Data
Table 1. Pin Description
Symbol
P6.0 - P6.7
Pin
Type
Function
1-8
I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
high impedance state. Port 6 outputs can be configured as push-pull or open
drain drivers. The following Port 6 pins have alternate functions:
1
O
P6.0
CS0
Chip Select 0 Output
...
...
...
...
...
5
O
P6.4
CS4
Chip Select 4 Output
6
I
P6.5
HOLD
External Master Hold Request Input
7
O
P6.6
HLDA
Hold Acknowledge Output
8
O
P6.7
BREQ
Bus Request Output
9-16
I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
high impedance state. Port 8 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 8 is selectable (TTL or special).
The following Port 8 pins have alternate functions:
9
I/O
P8.0
CC16IO
CAPCOM2: CC16 Capture Input / Compare Output
...
...
...
...
...
16
I/O
P8.7
CC23IO
CAPCOM2: CC23 Capture Input / Compare Output
19-26
I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
high impedance state. Port 7 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 7 is selectable (TTL or special).
The following Port 7 pins have alternate functions:
19
O
P7.0
POUT0
PWM Channel 0 Output
...
...
...
...
...
22
O
P7.3
POUT3
PWM Channel 3 Output
23
I/O
P7.4
CC28IO
CAPCOM2: CC28 Capture Input / Compare Output
...
...
...
...
...
26
I/O
P7.7
CC31IO
CAPCOM2: CC31 Capture Input / Compare Output
27-36
39-44
I
I
16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can
be the analog input channels (up to 16) for the A/D converter, where P5.x equals
ANx (Analog input channel x), or they are timer inputs:
39
I
P5.10
T6EUD
GPT2 Timer T6 External Up / Down Control Input
40
I
P5.11
T5EUD
GPT2 Timer T5 External Up / Down Control Input
41
I
P5.12
T6IN
GPT2 Timer T6 Count Input
42
I
P5.13
T5IN
GPT2 Timer T5 Count Input
43
I
P5.14
T4EUD
GPT1 Timer T4 External Up / Down Control Input
44
I
P5.15
T2EUD
GPT1 Timer T2 External Up / Down Control Input
P8.0 - P8.7
P7.0 - P7.7
P5.0 - P5.9
P5.10 - P5.15
DocID13266 Rev 2
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205
Pin Data
ST10F269Z1-ST10F269Z2
Table 1. Pin Description (continued)
Symbol
P2.0 - P2.7
P2.8 - P2.15
Pin
Type
Function
47-54
57-64
I/O
16-bit bidirectional I/O port, bit-wise programmable for input or output via
direction bit. Programming an I/O pin as input forces the corresponding output
driver to high impedance state. Port 2 outputs can be configured as push-pull or
open drain drivers. The input threshold of Port 2 is selectable (TTL or special).
The following Port 2 pins have alternate functions:
47
I/O
P2.0
16/206
CAPCOM: CC0 Capture Input / Compare Output
...
...
...
...
...
54
I/O
P2.7
CC7IO
CAPCOM: CC7 Capture Input / Compare Output
57
I/O
P2.8
CC8IO
CAPCOM: CC8 Capture Input / Compare Output
EX0IN
Fast External Interrupt 0 Input
I
P3.0 - P3.5
P3.6 - P3.13,
P3.15
CC0IO
...
...
...
...
...
64
I/O
P2.15
CC15IO
CAPCOM: CC15 Capture Input / Compare Output
I
EX7IN
Fast External Interrupt 7 Input
I
T7IN
CAPCOM2 Timer T7 Count Input
15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. Port 3 outputs can be configured as pushpull or open drain drivers. The input threshold of Port 3 is selectable (TTL or
special).
The following Port 3 pins have alternate functions:
65-70,
73-80,
81
I/O
I/O
I/O
65
I
P3.0
T0IN
CAPCOM Timer T0 Count Input
66
O
P3.1
T6OUT
GPT2 Timer T6 Toggle Latch Output
67
I
P3.2
CAPIN
GPT2 Register CAPREL Capture Input
68
O
P3.3
T3OUT
GPT1 Timer T3 Toggle Latch Output
69
I
P3.4
T3EUD
GPT1 Timer T3 External Up / Down Control Input
70
I
P3.5
T4IN
GPT1 Timer T4 Input for Count / Gate / Reload /
Capture
73
I
P3.6
T3IN
GPT1 Timer T3 Count / Gate Input
74
I
P3.7
T2IN
GPT1 Timer T2 Input for Count / Gate / Reload /
Capture
75
I/O
P3.8
MRST
SSC Master-Receiver / Slave-Transmitter I/O
76
I/O
P3.9
MTSR
SSC Master-Transmitter / Slave-Receiver O/I
77
O
P3.10
TxD0
ASC0 Clock / Data Output (Asynchronous /
Synchronous)
78
I/O
P3.11
RxD0
ASC0 Data Input (Asynchronous) or I/O (Synchronous)
79
O
P3.12
BHE
External Memory High Byte Enable Signal
WRH
External Memory High Byte Write Strobe
80
I/O
P3.13
SCLK
SSC Master Clock Output / Slave Clock Input
81
O
P3.15
CLKOUT
System Clock Output (=CPU Clock)
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Pin Data
Table 1. Pin Description (continued)
Symbol
P4.0 –P4.7
Pin
Type
Function
85-92
I/O
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. The input threshold is selectable (TTL or
special). Port 4.6 & 4.7 outputs can be configured as push-pull or open drain
drivers.
In case of an external bus configuration, Port 4 can be used to output the
segment address lines:
85
O
P4.0
A16
Segment Address Line
86
O
P4.1
A17
Segment Address Line
87
O
P4.2
A18
Segment Address Line
88
O
P4.3
A19
Segment Address Line
89
O
P4.4
A20
Segment Address Line
CAN2_RxD
CAN2 Receive Data Input
P4.5
A21
Segment Address Line
CAN1_RxD
CAN1 Receive Data Input
P4.6
A22
Segment Address Line
CAN1_TxD
CAN1 Transmit Data Output
A23
Most Significant Segment Address Line
CAN2_TxD
CAN2 Transmit Data Output
I
90
O
91
O
I
O
92
O
O
RD
WR/WRL
95
96
P4.7
O
External Memory Read Strobe. RD is activated for every external instruction or
data read access.
O
External Memory Write Strobe. In WR-mode this pin is activated for every
external data write access. In WRL mode this pin is activated for low Byte data
write accesses on a 16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in the SYSCON register for mode selection.
READY /
READY
97
I
Ready Input. The active level is programmable. When the Ready function is
enabled, the selected inactive level at this pin, during an external memory
access, will force the insertion of waitstate cycles until the pin returns to the
selected active level.
ALE
98
O
Address Latch Enable Output. In case of use of external addressing or of
multiplexed mode, this signal is the latch command of the address lines.
I
External Access Enable pin. A low level applied to this pin during and after Reset
forces the ST10F269Z1-ST10F269Z2 to start the program from the external
memory space. A high level forces the MCU to start in the internal memory
space.
EA
99
DocID13266 Rev 2
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205
Pin Data
ST10F269Z1-ST10F269Z2
Table 1. Pin Description (continued)
Symbol
Pin
Type
Function
I/O
Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state.
In case of an external bus configuration, PORT0 serves as the address (A) and
as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus
in demultiplexed bus modes.
Demultiplexed bus modes
Data Path Width:8-bit 16-bit
P0L.0 – P0L.7:D0 – D7D0 - D7
P0H.0 – P0H.7I/OD8 - D15
Multiplexed bus modes
Data Path Width:8-bit 16-bit
P0L.0 – P0L.7:AD0 – AD7AD0 - AD7
P0H.0 – P0H.7A8 – A15AD8 - AD15
118-125
128-135
I/O
Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. PORT1 is used as the 16-bit address bus
(A) in demultiplexed bus modes and also after switching from a demultiplexed
bus mode to a multiplexed bus mode.
The following PORT1 pins have alternate functions:
132
I
P1H.4
CC24IO
CAPCOM2: CC24 Capture Input
133
I
P1H.5
CC25IO
CAPCOM2: CC25 Capture Input
134
I
P1H.6
CC26IO
CAPCOM2: CC26 Capture Input
135
I
P1H.7
CC27IO
CAPCOM2: CC27 Capture Input
138
I
XTAL1 Oscillator amplifier and/or external clock input.
P0L.0 - P0L.7,
100-107,
P0H.0
108,
P0H.1 111-117
P0H.7
P1L.0 - P1L.7
P1H.0 P1H.7
XTAL1
XTAL2 Oscillator amplifier circuit output.
XTAL2
137
O
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in
the AC Characteristics must be observed.
RSTIN
140
I
Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a
specified duration while the oscillator is running resets the ST10F269Z1ST10F269Z2. An internal pull-up resistor permits power-on reset using only a
capacitor connected to VSS. In bidirectional reset mode (enabled by setting bit
BDRSTEN in SYSCON register), the RSTIN line is pulled low for the duration of
the internal reset sequence.
RSTOUT
141
O
Internal Reset Indication Output. This pin is driven to a low level during hardware,
software or watchdog timer reset. RSTOUT remains low until the EINIT (end of
initialization) instruction is executed.
NMI
142
I
Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU
to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when
the PWRDN (power down) instruction is executed, the NMI pin must be low in
order to force the ST10F269Z1-ST10F269Z2 to go into power down mode. If NMI
is high and PWDCFG =’0’, when PWRDN is executed, the part will continue to
run in normal mode.
If not used, pin NMI should be pulled high externally.
VAREF
37
-
A/D converter reference voltage.
VAGND
38
-
A/D converter reference ground.
18/206
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Pin Data
Table 1. Pin Description (continued)
Symbol
Pin
Type
Function
RPD
84
-
Timing pin for the return from interruptible powerdown mode and synchronous /
asynchronous reset selection.
VDD
46, 72,
82,93,
109,
126,
136, 144
-
Digital Supply Voltage = +5 V during normal operation and idle mode.
VSS
18,45,
55,71,
83,94,
110,
127,
139, 143
-
Digital Ground.
DC1
DC2
56
17
-
2.7V Decoupling pin: a decoupling capacitor of ≥ 330 nF must be connected
between this pin and nearest VSS pin.
DocID13266 Rev 2
19/206
205
Functional Description
3
ST10F269Z1-ST10F269Z2
Functional Description
The architecture of ST10F269Z1-ST10F269Z2 combines advantages of both RISC and
CISC processors and an advanced peripheral subsystem. The block diagram gives an
overview of the different on-chip components and the high bandwidth internal bus structure
of the ST10F269Z1-ST10F269Z2.
Figure 3. Block Diagram
32
16
128K/256K Byte
Flash Memory
2K Byte
Internal
RAM
16
CPU-Core and MAC Unit
Watchdog
16
PEC
10K Byte
XRAM
Interrupt Controller
8
Port 6
8
Port 5
BRG
3.3V
Port 2
CAPCOM1
CAPCOM2
Port 7
15
DocID13266 Rev 2
8
XTAL2
Voltage
Regulator
BRG
Port 3
16
PWM
SSC
ASC usart
GPT1
GPT2
16
10-Bit ADC
16
20/206
16
CAN2
External Bus
Controller
P4.4 CAN2_RXD
P4.7 CAN2_TXD
XTAL1
CAN1
Port 4 Port 1 Port 0
P4.5 CAN1_RXD
P4.6 CAN1_TXD
Oscillator
and PLL
Port 8
8
16
ST10F269Z1-ST10F269Z2
4
Memory Organization
Memory Organization
The memory space of the ST10F269Z1-ST10F269Z2 is configured in a unified memory
architecture. Code memory, data memory, registers and I/O ports are organized within the
same linear address space of 16 Mbytes. The entire memory space can be accessed Byte
wise or Word wise. Particular portions of the on-chip memory have additionally been made
directly bit addressable.
•
Flash: 128 K or 256 Kbytes of on-chip Flash memory.
•
IRAM: 2 Kbytes of on-chip internal RAM (dual-port) is provided as a storage for data,
system stack, general purpose register banks and code. A register bank is 16
Wordwide (R0 to R15) and / or Bytewide (RL0, RH0, …, RL7, RH7) general purpose
registers.
•
XRAM: 10 Kbytes of on-chip extension RAM (single port XRAM) is provided as a
storage for data, user stack and code.
The XRAM is divided into 2 areas, the first 2 Kbytes named XRAM1 and the second
8 Kbytes named XRAM2, connected to the internal XBUS and are accessed like an
external memory in 16-bit demultiplexed bus-mode without wait state or read/write
delay (50 ns access at 40 MHz CPU clock and 62.5 ns access at 32 MHz CPU clock).
Byte and Word accesses are allowed.
The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON
register), and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is
cleared, then any access in the address range 00’E000h - 00’E7FFh will be directed to
external memory interface, using the BUSCONx register corresponding to address
matching ADDRSELx register
The XRAM2 address range is 00’C000h - 00’DFFFh if XPEN (bit 2 of SYSCON
register), and XRAM2 (bit 3 of XPERCON register are set). If bit XRAM2EN or XPEN is
cleared, then any access in the address range 00’C000h - 00’DFFFh will be directed to
external memory interface, using the BUSCONx register corresponding to address
matching ADDRSELx register.
As the XRAM appears like external memory, it cannot be used as system stack or as
register banks. The XRAM is not provided for single bit storage and therefore is not bit
addressable.
•
SFR/ESFR: 1024 bytes (2 x 512 bytes) of address space is reserved for the special
function register areas. SFRs are Wordwide registers which are used to control and to
monitor the function of the different on-chip units.
•
CAN1: Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 Module access.
The CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting
CAN1EN bit 0 of the new XPERCON register. Accesses to the CAN Module use
demultiplexed addresses and a 16-bit data bus (byte accesses are possible). Two wait
states give an access time of 100 ns at 40 MHz CPU clock (or 125 ns at 32 MHz CPU
clock). No tri-state wait states are used.
•
CAN2: Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 Module access.
The CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting
CAN2EN bit 1 of the new XPERCON register. Accesses to the CAN Module use
demultiplexed addresses and a 16-bit data bus (byte accesses are possible). Two wait
states give an access time of 100 ns at 40 MHz CPU clock (or 125 ns at 32 MHz CPU
clock). No tri-state wait states are used.
In order to meet the needs of designs where more memory is required than is provided
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Memory Organization
ST10F269Z1-ST10F269Z2
on chip, up to 16M Bytes of external RAM and/or ROM can be connected to the
microcontroller.
Note:
If one or the two CAN modules are used, Port 4 cannot be programmed to output all
8 segment address lines. Thus, only 4 segment address lines can be used, reducing the
external memory space to 5 Mbytes (1 Mbyte per CS line).
•
Visibility of XBUS Peripherals
In order to keep the ST10F269Z1-ST10F269Z2 compatible with the ST10C167 and
with the ST10F167, the XBUS peripherals can be selected to be visible and / or
accessible on the external address / data bus. CAN1EN and CAN2EN bits of
XPERCON register must be set. If these bits are cleared before the global enabling
with XPEN-bit in SYSCON register, the corresponding address space, port pins and
interrupts are not occupied by the peripheral, thus the peripheral is not visible and not
available. Refer to Section 20: Special Function Register Overview.
Figure 4. ST10F269Z1-ST10F269Z2 On-chip Memory Mapping
Segment 2 Segment 3 Segment 4
14
RAM, SFR and X-pheripherals are
mapped into the address space.
05’0000
00’FFFF
Block6 = 64K Bytes*
10
SFR : 512 Bytes
04’0000
00’FE00
00’FDFF
Block5 = 64K Bytes*
0C
03’0000
08
02’0000
IRAM : 2K Bytes
00’F600
Block4 = 64K Bytes
00’F1FF
ESFR : 512 Bytes
Segment 1
07
Block3 = 32K Bytes
06
00’EFFF
01’8000
05
04
Bank 1H
01’0000
00’F000
CAN1 : 256 Bytes
Block2**
Block1**
Block0**
Bank 1L
00’EF00
00’EEFF
CAN2 : 256 Bytes
00’EE00
03
Segment 0
00’C000
00’EC14
02
Real Time Clock
00’EC00
01
00’6000
00’4000
Block2 = 8K Bytes
Block1 = 8K Bytes
Bank OL
00’E7FF
XRAM1 : 2K Bytes
Block0 = 16K Bytes
00
00’0000
Data
Page
Number
Absolute
Memory
Address
00’E000
00’DFFF
Internal
Flash
Memory
XRAM2 : 8K Bytes
00’C000
*Reserved area for 128K versions.
** Bank 0L may be remapped from segment 0 to segment 1 (Bank 1L) by setting SYSCON-ROMS1 (before EINIT)
Data Page Number and Absolute Memory Address are hexadecimal values.
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Memory Organization
XPERCON (F024H / 12H)
ESFR Reset Value: - - 05h
15
14
13
12
11
10
9
8
7
6
5
4
-
-
-
-
-
-
-
-
-
-
-
RTCEN
RW
CAN1EN
3
2
XRAM2EN XRAM1EN
RW
RW
1
0
CAN2EN
CAN1EN
RW
RW
CAN1 Enable Bit
‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and
P4.6 pins can be used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is
only directed to external memory if CAN2EN is also ‘0’.
‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed.
CAN2EN
CAN2 Enable Bit
‘0’: Accesses to the on-chip CAN2 XPeripheral and its functions are disabled. P4.4 and
P4.7 pins can be used as general purpose I/Os. Address range 00’EE00h-00’EEFFh is
only directed to external memory if CAN1EN is also ‘0’.
‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed.
XRAM1E
N
XRAM1 Enable Bit
‘0’: Accesses to external memory within space 00’E000h to 00’E7FFh. The 2K Bytes of
internal XRAM1 are disabled.
’1’: Accesses to the internal 2K Bytes of XRAM1.
XRAM2E
N
XRAM2 Enable Bit
‘0’: Accesses to the external memory within space 00’C000h to 00’DFFFh. The 8K Bytes
of internal XRAM2 are disabled.
’1’: Accesses to the internal 8K Bytes of XRAM2.
RTCEN
RTC Enable Bit
’0’: Accesses to the on-chip Real Time Clock are disabled, external access is performed.
Address range 00’EC00h-00’ECFFh is only directed to external memory if CAN1EN and
CAN2EN are ’0’ also
’1’: The on-chip Real Time Clock is enabled and can be accessed.
When both CAN are disabled via XPERCON setting, then any access in the address range
00’EE00h - 00’EFFFh will be directed to external memory interface, using the BUSCONx
register corresponding to address matching ADDRSELx register. P4.4 and P4.7 can be
used as General Purpose I/O when CAN2 is disabled, and P4.5 and P4.6 can be used as
General Purpose I/O when CAN1 is disabled.
The default XPER selection after Reset is identical to XBUS configuration of ST10C167:
XCAN1 is enabled, XCAN2 is disabled, XRAM1 (2 Kbyte compatible XRAM) is enabled,
XRAM2 (new 8 Kbyte XRAM) is disabled.
Register XPERCON cannot be changed after the global enabling of XPeripherals, i.e. after
the setting of bit XPEN in the SYSCON register.
In EMUlation mode, all the XPERipherals are enabled (XPERCON bit are all set). The
access to external memory and/or XBus is controlled by the bondout chip.
When the Real Time Clock is disabled (RTCEN = 0), the clock oscillator is switch-off if the
ST10 enters in power-down mode. Otherwise, when the Real Time Clock is enabled, the bit
RTCOFF of the RTCCON register allows to choose the power-down mode of the clock
oscillator (See Section 16: Real Time Clock).
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5
Internal Flash Memory
5.1
Overview
•
128-K or 256-Kbyte on-chip Flash memory
•
Two possibilities of Flash mapping into the CPU address space
•
Flash memory can be used for code and data storage
•
32-bit, zero waitstate read access (50 ns cycle time at fCPU = 40 MHz and 62.5 ns cycle
time at fCPU = 32 MHz
•
Erase-Program Controller (EPC) similar to M29F400B ST stand-alone Flash memory
•
•
–
Word-by-Word Programmable (16 ms typical)
–
Data polling and Toggle Protocol for EPC Status
–
Ready/Busy signal connected on XP2INT interrupt line
–
Internal Power-On detection circuit
Memory Erase in blocks
–
One 16-Kbyte, two 8-Kbyte, one 32-Kbyte, one to three 64-Kbyte blocks
–
Each block can be erased separately (1.5 second typical)
–
Chip erase (8.5 second typical)
–
Each block can be separately protected against programming and erasing
–
Each protected block can be temporary unprotected
–
When enabled, the read protection prevents access to data in Flash memory using
a program running out of the Flash memory space. Access to data of internal
Flash can only be performed with an inner protected program
Erase Suspend and Resume Modes
–
Read and Program another Block during erase suspend
•
Single Voltage operation, no need of dedicated supply pin
•
Low Power Consumption:
–
45 mA max. Read current
–
60 mA max. Program or Erase current
–
Automatic Stand-by-mode (50 mA maximum)
•
1000 Erase-Program Cycles per block, 20 years of data retention time
•
Operating temperature: -40 to +125°C
5.2
Operational Overview
5.2.1
Read Mode
In standard mode (the normal operating mode) the Flash appears like an on-chip ROM with
the same timing and functionality. The Flash module offers a fast access time, allowing zero
waitstate access with CPU frequency up to 40 MHz. Instruction fetches and data operand
reads are performed with all addressing modes of the ST10F269Z1-ST10F269Z2
instruction set.
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Internal Flash Memory
In order to optimize the programming time of the internal Flash, blocks of 8 Kbytes,
16 Kbytes, 32 Kbytes, 64 Kbytes can be used. But the size of the blocks does not apply to
the whole memory space, see details in Table 2.
Table 2. 128-Kbyte or 256-Kbyte Flash Memory Block Organization
Block
Addresses (Segment 0)
Addresses (Segment 1)
Size (Kbyte)
0
1
2
3
4
5(1)
6(1)
00’0000h to 00’3FFFh
00’4000h to 00’5FFFh
00’6000h to 00’7FFFh
01’8000h to 01’FFFFh
02’0000h to 02’FFFFh
03’0000h to 03’FFFFh(1)
04’0000h to 04’FFFFh(1)
01’0000h to 01’3FFFh
01’4000h to 01’5FFFh
01’6000h to 01’7FFFh
01’8000h to 01’FFFFh
02’0000h to 02’FFFFh
03’0000h to 03’FFFFh(1)
04’0000h to 04’FFFFh(1)
16
8
8
32
64
64(1)
64(1)
1. Not available on 128K versions (reserved areas).
5.2.2
Instructions and Commands
All operations besides normal read operations are initiated and controlled by command
sequences written to the Flash Command Interface (CI). The Command Interface (CI)
interprets words written to the Flash memory and enables one of the following operations:
•
Read memory array
•
Program Word
•
Block Erase
•
Chip Erase
•
Erase Suspend
•
Erase Resume
•
Block Protection
•
Block Temporary Unprotection
•
Code Protection
Commands are composed of several write cycles at specific addresses of the Flash
memory. The different write cycles of such command sequences offer a fail-safe feature to
protect against an inadvertent write.
A command only starts when the Command Interface has decoded the last write cycle of an
operation. Until that last write is performed, Flash memory remains in Read Mode
Note:
As it is not possible to perform write operations in the Flash while fetching code from Flash,
the Flash commands must be written by instructions executed from internal RAM or external
memory.
Command write cycles do not need to be consecutively received, pauses are allowed, save
for Block Erase command. During this operation all Erase Confirm commands must be sent
to complete any block erase operation before time-out period expires (typically 96 ms).
Command sequencing must be followed exactly. Any invalid combination of commands will
reset the Command Interface to Read Mode.
5.2.3
Status Register
This register is used to flag the status of the memory and the result of an operation. This
register can be accessed by read cycles during the Erase-Program Controller (EPC)
operation.
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5.2.4
ST10F269Z1-ST10F269Z2
Erase Operation
This Flash memory features a block erase architecture with a chip erase capability too.
Erase is accomplished by executing the six cycle erase command sequence. Additional
command write cycles can then be performed to erase more than one block in parallel.
When a time-out period elapses (96 ms) after the last cycle, the Erase-Program Controller
(EPC) automatically starts and times the erase pulse and executes the erase operation.
There is no need to program the block to be erased with ‘0000h’ before an erase operation.
Termination of operation is indicated in the Flash status register. After erase operation, the
Flash memory locations are read as 'FFFFh’ value.
5.2.5
Erase Suspend
A block erase operation is typically executed within 1.5 second for a 64-Kbyte block.
Erasure of a memory block may be suspended, in order to read data from another block or
to program data in another block, and then resumed.
5.2.6
In-System Programming
In-system programming is fully supported. No special programming voltage is required.
Because of the automatic execution of erase and programming algorithms, write operations
are reduced to transferring commands and data to the Flash and reading the status. Any
code that programs or erases Flash memory locations (that writes data to the Flash) must
be executed from memory outside the on-chip Flash memory itself (on-chip RAM or external
memory).
A boot mechanism is provided to support in-system programming. It works using serial link
via USART interface and a PC compatible or other programming host.
5.2.7
Read/Write Protection
The Flash module supports read and write protection in a very comfortable and advanced
protection functionality. If Read Protection is installed, the whole Flash memory is protected
against any "external" read access; read accesses are only possible with instructions
fetched directly from program Flash memory. For update of the Flash memory a temporary
disable of Flash Read Protection is supported.
The device also features a block write protection. Software locking of selectable memory
blocks is provided to protect code and data. This feature will disable both program and
erase operations in the selected block(s) of the memory. Block Protection is accomplished
by block specific lock-bit which are programmed by executing a four cycle command
sequence. The locked state of blocks is indicated by specific flags in the according block
status registers. A block may only be temporarily unlocked for update (write) operations.
With the two possibilities for write protection - whole memory or block specific - a flexible
installation of write protection is supported to protect the Flash memory or parts of it from
unauthorized programming or erase accesses and to provide virus-proof protection for all
system code blocks. All write protection also is enabled during boot operation.
5.2.8
Power Supply, Reset
The Flash module uses a single power supply for both read and write functions. Internally
generated and regulated voltages are provided for the program and erase operations from
5 V supply. Once a program or erase cycle has been completed, the device resets to the
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Internal Flash Memory
standard read mode. At power-on, the Flash memory has a setup phase of some
microseconds (dependent on the power supply ramp-up). During this phase, Flash can not
be read. Thus, if EA pin is high (execution will start from Flash memory), the CPU remains in
reset state until the Flash can be accessed.
5.3
Architectural Description
The Flash module distinguishes two basic operating modes, the standard read mode and
the command mode. The initial state after power-on and after reset is the standard read
mode.
5.3.1
Read Mode
The Flash module enters the standard operating mode, the read mode:
•
After Reset command
•
After every completed erase operation
•
After every completed programming operation
•
After every other completed command execution
•
Few microseconds after a CPU-reset has started
•
After incorrect address and data values of command sequences or writing them in an
improper sequence
•
After incorrect write access to a read protected Flash memory
The read mode remains active until the last command of a command sequence is decoded
which starts directly a Flash array operation, such as:
•
erase one or several blocks
•
program a word into Flash array
•
protect / temporary unprotect a block.
In the standard read mode read accesses are directly controlled by the Flash memory array,
delivering a 32-bit double Word from the addressed position. Read accesses are always
aligned to double Word boundaries. Thus, both low order address bit A1 and A0 are not
used in the Flash array for read accesses. The high order address bit A17/A16 define the
physical 64-Kbyte segment being accessed within the Flash array.
5.3.2
Command Mode
Every operation besides standard read operations is initiated by commands written to the
Flash command register. The addresses used for command cycles define in conjunction
with the actual state the specific step within command sequences. With the last command of
a command sequence, the Erase-Program Controller (EPC) starts the execution of the
command. The EPC status is indicated during command execution by:
5.3.3
•
The Status Register,
•
The Ready/Busy signal.
Ready/Busy Signal
The Ready/Busy (R/B) signal is connected to the XPER2 interrupt node (XP2IC). When R/B
is high, the Flash is busy with a Program or Erase operation and will not accept any
additional program or erase instruction. When R/B is Low, the Flash is ready for any
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Read/Write or Erase operation. The R/B will also be low when the memory is put in Erase
Suspend mode.
This signal can be polled by reading XP2IC register, or can be used to trigger an interrupt
when the Flash goes from Busy to Ready.
5.3.4
Flash Status Register
The Flash Status register is used to flag the status of the Flash memory and the result of an
operation. This register can be accessed by Read cycles during the program-Erase
Controller operations. The program or erase operation can be controlled by data polling on
bit FSB.7 of Status Register, detection of Toggle on FSB.6 and FSB.2, or Error on FSB.5
and Erase Time-out on FSB.3 bit. Any read attempt in Flash during EPC operation will
automatically output these five bits. The EPC sets bit FSB.2, FSB.3, FSB.5, FSB.6 and
FSB.7. Other bits are reserved for future use and should be masked.
Flash Status
Note:
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The Address of Flash Status Register is the address of the word being programmed when
Programming operation is in progress, or an address within block being erased when
Erasing operation is in progress.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
FSB.7
FSB.6
FSB.5
-
FSB.3
FSB.2
-
-
R
R
R
R
R
FSB.7
Flash Status bit 7: Data Polling Bit
Programming Operation: this bit outputs the complement of the bit 7 of the word being
programmed, and after completion, will output the bit 7 of the word programmed.
Erasing Operation: outputs a ‘0’ during erasing, and ‘1’ after erasing completion.
If the block selected for erasure is (are) protected, FSB.7 will be set to ‘0’ for about 100 µs,
and then return to the previous addressed memory data value.
FSB.7 will also flag the Erase Suspend Mode by switching from ‘0’ to ‘1’ at the start of the
Erase Suspend.
During Program operation in Erase Suspend Mode, FSB.7 will have the same behavior as in
normal Program execution outside the Suspend mode.
FSB.6
Flash Status bit 6: Toggle Bit
Programming or Erasing Operations: successive read operations of Flash Status register will
deliver complementary values. FSB.6 will toggle each time the Flash Status register is read.
The Program operation is completed when two successive reads yield the same value. The
next read will output the bit last programmed, or a ‘1’ after Erase operation
FSB.6 will be set to‘1’ if a read operation is attempted on an Erase Suspended block. In
addition, an Erase Suspend/Resume command will cause FSB.6 to toggle.
FSB.5
Flash Status bit 5: Error Bit
This bit is set to ‘1’ when there is a failure of Program, block or chip erase operations.This bit
will also be set if a user tries to program a bit to ‘1’ to a Flash location that is currently
programmed with ‘0’.
The error bit resets after Read/Reset instruction.
In case of success, the Error bit will be set to ‘0’ during Program or Erase and then will output
the bit last programmed or a ‘1’ after erasing
FSB.3
Flash Status bit 3: Erase Time-out Bit
This bit is cleared by the EPC when the last Block Erase command has been entered to the
Command Interface and it is awaiting the Erase start. When the time-out period is finished,
after 96 µs, FSB.3 returns back to ‘1’.
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FSB.2
5.3.5
Internal Flash Memory
Flash Status bit 2: Toggle Bit
This toggle bit, together with FSB.6, can be used to determine the chip status during the
Erase Mode or Erase Suspend Mode. It can be used also to identify the block being Erased
Suspended. A Read operation will cause FSB.2 to Toggle during the Erase Mode. If the
Flash is in Erase Suspend Mode, a Read operation from the Erase suspended block or a
Program operation into the Erase suspended block will cause FSB.2 to toggle.
When the Flash is in Program Mode during Erase Suspend, FSB.2 will be read as ‘1’ if
address used is the address of the word being programmed.
After Erase completion with an Error status, FSB.2 will toggle when reading the faulty sector.
Flash Protection Register
The Flash Protection register is a non-volatile register that contains the protection status.
This register can be read by using the Read Protection Status (RP) command, and
programmed by using the dedicated Set Protection command.
Flash Protection Register (PR)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CP
-
-
-
-
-
-
-
-
BP6
BP5
BP4
BP3
BP2
BP1
BP0
(1)
(1)
1. Not available for 128K versions (reserved areas)
BPx
Block x Protection Bit (x = 0...6)
‘0’: the Block Protection is enabled for block x. Programming or erasing the
block is not possible, unless a Block Temporary Unprotection command is
issued.
1’: the Block Protection is disabled for block x.
Bit is ‘1’ by default, and can be programmed permanently to ‘0’ using the Set
Protection command but then cannot be set to ‘1’ again. It is therefore possible
to temporally disable the Block Protection using the Block Temporary
Unprotection instruction.
CP
Code Protection Bit
‘0’: the Flash Code Protection is enabled. Read accesses to the Flash for
execution not performed in the Flash itself are not allowed, the returned value
will be 009Bh, whatever the content of the Flash is.
1’: the Flash Code Protection is disabled: read accesses to the Flash from
external or internal RAM are allowed
Bit is ‘1’ by default, and can be programmed permanently to ‘0’ using the Set
Protection command but then cannot be set to ‘1’ again. It is therefore possible
to temporally disable the Code Protection using the Code Temporary
Unprotection instruction.
5.3.6
Instructions Description
Twelve instructions dedicated to Flash memory accesses are defined as follows:
•
Read/Reset (RD). The Read/Reset instruction consist of one write cycle with data
XXF0h. it can be optionally preceded by two CI enable coded cycles (data xxA8h at
address 1554h + data xx54h at address 2AA8h). Any successive read cycle following a
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Read/Reset instruction will read the memory array. A Wait cycle of 10 µs is necessary
after a Read/Reset command if the memory was in program or Erase mode.
•
Program Word (PW). This instruction uses four write cycles. After the two Cl enable
coded cycles, the Program Word command xxA0h is written at address 1554h. The
following write cycle will latch the address and data of the word to be programmed.
Memory programming can be done only by writing 0's instead of 1's, otherwise an error
occurs. During programming, the Flash Status is checked by reading the Flash Status
bit FSB.2, FSB.5, FSB.6 and FSB.7 which show the status of the EPC. FSB.2, FSB.6
and FSB.7 determine if programming is on going or has completed, and FSB.5 allows a
check to be made for any possible error.
•
Block Erase (BE). This instruction uses a minimum of six command cycles. The erase
enable command xx80h is written at address 1554h after the two-cycle CI enable
sequence.
The erase confirm code xx30h must be written at an address related to the block to be
erased preceded by the execution of a second CI enable sequence. Additional erase
confirm codes must be given to erase more than one block in parallel. Additional erase
confirm commands must be written within a defined time-out period. The input of a new
Block Erase command will restart the time-out period.
When this time-out period has elapsed, the erase starts. The status of the internal timer
can be monitored through the level of FSB.3, if FSB.3 is ‘0’, the Block Erase command
has been given and the time-out is running; if FSB.3 is ‘1’, the time-out has expired and
the EPC is erasing the block(s).
If the second command given is not an erase confirm or if the coded cycles are wrong,
the instruction aborts, and the device is reset to Read Mode. It is not necessary to
program the block with 0000h as the EPC will do this automatically before the erasing
to FFFFh. Read operations after the EPC has started, output the Flash Status Register.
During the execution of the erase by the EPC, the device accepts only the Erase
Suspend and Read/Reset instructions. Data Polling bit FSB.7 returns ‘0’ while the
erasure is in progress, and ‘1’ when it has completed. The Toggle bit FSB.2 and FSB.6
toggle during the erase operation. They stop when erase is completed. After
completion, the Error bit FSB.5 returns ‘1’ if there has been an erase failure because
erasure has not completed even after the maximum number of erase cycles have been
executed by the EPC, in this case, it will be necessary to input a Read/Reset to the
Command Interface in order to reset the EPC.
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•
Chip Erase (CE). This instruction uses six write cycles. The Erase Enable command
xx80h, must be written at address 1554h after CI-Enable cycles. The Chip Erase
command xx10h must be given on the sixth cycle after a second CI-Enable sequence.
An error in command sequence will reset the CI to Read mode. It is NOT necessary to
program the block with 0000h as the EPC will do this automatically before the erasing
to FFFFh. Read operations after the EPC has started output the Flash Status Register.
During the execution of the erase by the EPC, Data Polling bit FSB.7 returns ‘0’ while
the erasure is in progress, and ‘1’ when it has completed. The FSB.2 and FSB.6 bit
toggle during the erase operation. They stop when erase is finished. The FSB.5 error
bit returns "1" in case of failure of the erase operation. The error flag is set after the
maximum number of erase cycles have been executed by the EPC. In this case, it will
be necessary to input a Read/Reset to the Command Interface in order to reset the
EPC.
•
Erase Suspend (ES). This instruction can be used to suspend a Block Erase operation
by giving the command xxB0h without any specific address. No CI-Enable cycles is
required. Erase Suspend operation allows reading of data from another block and/or
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the programming in another block while erase is in progress. If this command is given
during the time-out period, it will terminate the time-out period in addition to erase
Suspend. The Toggle bit FSB.6, when monitored at an address that belongs to the
block being erased, stops toggling when Erase Suspend Command is effective, It
happens between 0.1 ms and 15 ms after the Erase Suspend Command has been
written. The Flash will then go in normal Read Mode, and read from blocks not being
erased is valid, while read from block being erased will output FSB.2 toggling. During a
Suspend phase the only instructions valid are Erase Resume and Program Word. A
Read / Reset instruction during Erase suspend will definitely abort the Erase and result
in invalid data in the block being erased.
Note:
•
Erase Resume (ER). This instruction can be given when the memory is in Erase
Suspend State. Erase can be resumed by writing the command xx30h at any address
without any Cl-enable sequence.
•
Program during Erase Suspend. The Program Word instruction during Erase
Suspend is allowed only on blocks that are not Erase-suspended. This instruction is the
same than the Program Word instruction.
•
Set Protection (SP). This instruction can be used to enable both Block Protection (to
protect each block independently from accidental Erasing-Programming Operation)
and Code Protection (to avoid code dump). The Set Protection Command must be
given after a special CI-Protection Enable cycles (see instruction table). The following
Write cycle, will program the Protection Register. To protect the block x (x = 0 to 6), the
data bit x must be at ‘0’. To protect the code, bit 15 of the data must be ‘0’. Enabling
Block or Code Protection is permanent and can be cleared only by ST. Block
Temporary Unprotection and Code Temporary Unprotection instructions are available
to allow the customer to update the code.
The new value programmed in protection register will only become active after a reset.
Bit that are already at ’0’ in protection register must be confirmed at ’0’ also in data latched
during the 4th cycle of set protection command, otherwise an error may occur.
•
Note:
Read Protection Status (RP). This instruction is used to read the Block Protection
status and the Code Protection status. To read the protection register (see Table 3), the
CI-Protection Enable cycles must be executed followed by the command xx90h at
address x2A54h. The following Read Cycles at any odd word address will output the
Block Protection Status. The Read/Reset command xxF0h must be written to reset the
protection interface.
After a modification of protection register (using Set Protection command), the Read
Protection Status will return the new PR value only after a reset.
•
Block Temporary Unprotection (BTU). This Instruction can be used to temporary
unprotect all the blocks from Program / Erase protection. The Unprotection is disabled
after a Reset cycle. The Block Temporary Unprotection command xxC1h must be given
to enable Block Temporary Unprotection. The Command must be preceded by the CIProtection Enable cycles and followed by the Read/Reset command xxF0h.
•
Set Code Protection (SCP). This kind of protection allows the customer to protect the
proprietary code written in Flash. If installed and active, Flash Code Protection
prevents data operand accesses and program branches into the on-chip Flash area
from any location outside the Flash memory itself. Data operand accesses and
branches to Flash locations are only and exclusively allowed for instructions executed
from the Flash memory itself. Every read or jump to Flash performed from another
memory (like internal RAM, external memory) while Code Protection is enabled, will
give the opcode 009Bh related to TRAP #00 illegal instruction. The CI-Protection
Enable cycles must be sent to set the Code Protection. By writing data 7FFFh at any
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odd word address, the Code Protected status is stored in the Flash Protection Register
(PR). Protection is permanent and cannot be cleared by the user. It is possible to
temporarily disable the Code Protection using Code Temporary Unprotection
instruction.
Note:
Bits that are already at ’0’ in protection register must be confirmed at ’0’ also in data latched
during the 4th cycle of set protection command, otherwise an error may occur.
•
Code Temporary Unprotection (CTU). This instruction must be used to temporary
disable Code Protection. This instruction is effective only if executed from Flash
memory space. To restore the protection status, without using a reset, it is necessary to
use a Code Temporary Protection instruction. System reset will reset also the Code
Temporary Unprotected status. The Code Temporary Unprotection command consists
of the following write cycle:
MOVMEM, Rn;This instruction MUST be executed from Flash memory space.
Where MEM is an absolute address inside memory space, Rn is a register loaded with
data 0FFFFh.
•
Code Temporary Protection (CTP). This instruction allows to restore Code
Protection. This operation is effective only if executed from Flash memory and is
necessary to restore the protection status after the use of a Code Temporary
Unprotection instruction.
The Code Temporary Protection command consists of the following write cycle:
MOVMEM, Rn ;This instruction MUST be executed from Flash memory space
Where MEM is an absolute address inside memory space, Rn is a register loaded with
data 0FFFBh.
Note that Code Temporary Unprotection instruction must be used when it is necessary
to modify the Flash with protected code (SCP), since the write/erase routines must be
executed from a memory external to Flash space. Usually, the write/erase routines,
executed in RAM, ends with a return to Flash space where a CTP instruction restore
the protection.
125
Instruction
Table 3. Instructions
Read/Reset
RD
1+
Read/Reset
RD
3+
Program Word
PW
4
Block Erase
BE
6
Chip Erase
CE
6
Erase Suspend
ES
1
Erase Resume
ER
1
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1st
Cycle
Mne Cycle
Addr.1
X2
Data
xxF0h
Addr.1
x1554h
2nd
Cycle
3rd
Cycle
4th Cycle
5th
Cycle
6th
Cycle
7th
Cycle
Read Memory Array until a new write cycle is initiated
x2AA8h
xxxxxh
Read Memory Array until a new write
cycle is initiated
Data
xxA8h
xx54h
xxF0h
Addr.1
x1554h
x2AA8h
x1554h
WA 3
Data
xxA8h
xx54h
xxA0h
WD 4
Addr.1
x1554h
x2AA8h
x1554h
x1554h
x2AA8h
BA
BA’ 5
Data
xxA8h
xx54h
xx80h
xxA8h
xx54h
xx30h
xx30h
Addr.1
x1554h
x2AA8h
x1554h
x1554h
x2AA8h
x1554h
Data
xxA8h
xx54h
xx80h
xxA8h
xx54h
xx10h
Addr.1
X2
Data
xxB0h
Addr.1
X2
Data
xx30h
Read Data Polling or
Toggle bit until Program
completes.
Note 6
Read until Toggle stops, then read or program all data needed
from block(s) not being erased then Resume Erase.
Read Data Polling or Toggle bit until Erase completes or Erase
is suspended another time.
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Table 3. Instructions (continued)
Instruction
Set Block/Code
Protection
Read
Protection
Status
SP
RP
Block
Temporary
Unprotection
1st
Cycle
2nd
Cycle
3rd
Cycle
4th Cycle
Addr.1
x2A54h
x15A8h
x2A54h
Any odd
word
address 9
Data
xxA8h
xx54h
xxC0h
WPR 7
Addr.1
x2A54h
x15A8h
x2A54h
Any odd
word
address 9
Mne Cycle
BTU
4
4
4
Code
Temporary
Unprotection
CTU
1
Code
Temporary
Protection
CTP
1
Data
xxA8h
xx54h
xx90h
Read PR
Addr.1
x2A54h
x15A8h
x2A54h
X2
Data
xxA8h
xx54h
xxC1h
xxF0h
Addr.1
MEM 8
Data
FFFFh
Addr.1
MEM 8
Data
FFFBh
5th
Cycle
6th
Cycle
7th
Cycle
-
Read Protection Register
until a new write cycle is
initiated.
-
Write cycles must be executed from Flash.
Write cycles must be executed from Flash.
1. Address bit A14, A15 and above are don’t care for coded address inputs.
2. X = Don’t Care.
3. WA = Write Address: address of memory location to be programmed.
4. WD = Write Data: 16-bit data to be programmed.
5. Optional, additional blocks addresses must be entered within a time-out delay (96 µs) after last write entry, time-out status
can be verified through FSB.3 value. When full command is entered, read Data Polling or Toggle bit until Erase is
completed or suspended.
6. Read Data Polling or Toggle bit until Erase completes.
7. WPR = Write protection register. To protect code, bit 15 of WPR must be ‘0’. To protect block N (N=0,1,...), bit N of WPR must
be ‘0’. Bit that are already at ‘0’ in protection register must also be ‘0’ in WPR, else a writing error will occurs (it is not
possible to write a ‘1’ in a bit already programmed at ‘0’).
8. MEM = any address inside the Flash memory space. Absolute addressing mode must be used (MOV MEM, Rn), and
instruction must be executed from Flash memory space.
9. Odd word address = 4n-2 where n = 0, 1, 2, 3..., ex. 0002h, 0006h...
Generally, command sequences cannot be written to Flash by instructions fetched from the
Flash itself. Thus, the Flash commands must be written by instructions, executed from
internal RAM or external memory.
Command cycles on the CPU interface need not to be consecutively received (pauses
allowed). The CPU interface delivers dummy read data for not used cycles within command
sequences.
All addresses of command cycles shall be defined only with Register-indirect addressing
mode in the according move instructions. Direct addressing is not allowed for command
sequences. Address segment or data page pointer are taken into account for the command
address value.
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5.3.7
ST10F269Z1-ST10F269Z2
Reset Processing and Initial State
The Flash module distinguishes two kinds of CPU reset types
The lengthening of CPU reset:
5.4
•
is not reported to external devices by bidirectional pin
•
is not enabled in case of external start of CPU after reset.
Flash Memory Configuration
The default memory configuration of the ST10F269Z1-ST10F269Z2 Memory is determined
by the state of the EA pin at reset. This value is stored in the Internal ROM Enable bit
(named ROMEN) of the SYSCON register.
When ROMEN = 0, the internal Flash is disabled and external ROM is used for startup
control. Flash memory can later be enabled by setting the ROMEN bit of SYSCON to 1. The
code performing this setting must not run from a segment of the external ROM to be
replaced by a segment of the Flash memory, otherwise unexpected behavior may occur.
For example, if external ROM code is located in the first 32 Kbytes of segment 0, the first
32 Kbytes of the Flash must then be enabled in segment 1. This is done by setting the
ROMS1 bit of SYSCON to 0 before or simultaneously with setting of ROMEN bit. This must
be done in the externally supplied program before the execution of the EINIT instruction.
If program execution starts from external memory, but access to the Flash memory mapped
in segment 0 is later required, then the code that performs the setting of ROMEN bit must be
executed either in the segment 0 but above address 00’8000h, or from the internal RAM.
Bit ROMS1 only affects the mapping of the first 32 Kbytes of the Flash memory. All other
parts of the Flash memory (addresses 01’8000h - 04’FFFFh) remain unaffected.
The SGTDIS Segmentation Disable / Enable must also be set to 0 to allow the use of the full
256 Kbytes of on-chip memory in addition to the external boot memory. The correct
procedure on changing the segmentation registers must also be observed to prevent an
unwanted trap condition:
•
Instructions that configure the internal memory must only be executed from external
memory or from the internal RAM.
•
An Absolute Inter-Segment Jump (JMPS) instruction must be executed after Flash
enabling, to the next instruction, even if this next instruction is located in the
consecutive address.
•
Whenever the internal Memory is disabled, enabled or remapped, the DPPs must be
explicitly (re)loaded to enable correct data accesses to the internal memory and/or
external memory.
5.5
Application Examples
5.5.1
Handling of Flash Addresses
All command, Block, Data and register addresses to the Flash have to be located within the
active Flash memory space. The active space is that address range to which the physical
Flash addresses are mapped as defined by the user. When using data page pointer (DPP)
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for block addresses make sure that address bit A15 and A14 of the block address are
reflected in both LSBs of the selected DPPS.
Note:
For Command Instructions, address bit A14, A15, A16 and A17 are don’t care. This simplify
a lot the application software, because it minimize the use of DPP registers when using
Command in the Command Interface.
Direct addressing is not allowed for Command sequence operations to the Flash. Only
Register-indirect addressing can be used for command, block or write-data accesses.
5.5.2
Basic Flash Access Control
When accessing the Flash all command write addresses have to be located within the active
Flash memory space. The active Flash memory space is that logical address range which is
covered by the Flash after mapping. When using data page pointer (DPP) for addressing
the Flash, make sure that address bit A15 and A14 of the command addresses are reflected
in both LSBs of the selected data page pointer (A15 - DPPx.1 and A14 - DPPx.0).
In case of the command write addresses, address bit A14, A15 and above are don’t care.
Thus, command writes can be performed by only using one DPP register. This allow to have
a more simple and compact application software.
Another - advantageous - possibility is to use the extended segment instruction for
addressing.
Note:
The direct addressing mode is not allowed for write access to the Flash address/command
register. Be aware that the C compiler may use this kind of addressing. For write accesses
to Flash module always the indirect addressing mode has to be selected.
The following basic instruction sequences show examples for different addressing
possibilities.
Principle example of address generation for Flash commands and registers:
When using data page pointer (DPP0 is this example)
MOVDPP0,#08h;adjust data page pointers according to the
;addresses: DPP0 is used in this example, thus
;ADDRESS must have A14 and A15 bit set to ‘0’.
MOVRwm,#ADDRESS;ADDRESS could be a dedicated command sequence
;address 2AA8h, 1554h ... ) or the Flash write
;address
MOVRwn,#DATA;DATA could be a dedicated command sequence data
;(xxA0h,xx80h ... ) or data to be programmed
MOV[Rwm],Rwn;indirect addressing
When using the extended segment instruction:
MOVRwm,#ADDRESS;ADDRESS could be a dedicated command sequence
;address (2AA8h, 1554h ... ) or the Flash write
;address
MOVRwo,#DATA;DATA could be a dedicated command sequence data
;(xxA0h,xx80h ... ) or data to be programmed
MOVRwn,#SEGMENT ;the value of SEGMENT represents the segment
;number and could be 0, 1, 2, 3 or 4 (depending
;on sector mapping) for 256KByte Flash.
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EXTSRwn,#LENGTH;the value of Rwn determines the 8-bit segment
;valid for the corresponding data access for any
;long or indirect address in the following(s)
;instruction(s). LENGTH defines the number of
;the effected instruction(s) and has to be a value ;between 1...4
MOV[Rwm],Rwo;indirect addressing with segment number from
;EXTS
5.5.3
Programming Examples
Most of the microcontroller programs are written in the C language where the data page
pointers are automatically set by the compiler. But because the C compiler may use the not
allowed direct addressing mode for Flash write addresses, it is necessary to program the
organizational Flash accesses (command sequences) with assembler in-line routines which
use indirect addressing.
Example 1 Performing the command Read/Reset
We assume that in the initialization phase the lowest 32 Kbytes of Flash memory (sector 0)
have been mapped to segment 1.
According to the usual way of ST10 data addressing with data page pointers, address bit
A15 and A14 of a 16-bit command write address select the data page pointer (DPP) which
contains the upper 10-bit for building the 24-bit physical data address. Address bit A13...A0
represent the address offset. As the bit A14...A17 are "don’t care" when written a Flash
command in the Command Interface (CI), we can choose the most convenient DPPx
register for address handling.
The following examples are making usage of DPP0. We just have to make sure, that DPP0
points to active Flash memory space.
To be independent of mapping of sector 0 we choose for all DPPs which are used for Flash
address handling, to point to segment 2.
For this reason we load DPP0 with value 08h (00 0000 l000b).
MOVR5, #01554h;load auxilary register R5 with command address ;(used in
command cycle 1)
MOVR6, #02AA8h;load auxilary register R6 with command address ;(used in
command cycle 2)
SCXTDPPO, #08h;push data page pointer 0 and load it to point to ;segment 2
MOVR7, #0A8h;load register R7 with 1st CI enable command
MOV[R5], R7;command cycle 1
MOVR7, #054h;load register R7 with 2cd CI enable command
MOV[R6], R7;command cycle 2
MOVR7, #0F0h;load register R7 with Read/Reset command
MOV[R5], R7;command cycle 3. Address is don’t care
POPDPP0;restore DPP0 value
In the example above the 16-bit registers R5 and R6 are used as auxiliary registers for
indirect addressing.
Example 2 Performing a Program Word command
We assume that in the initialization phase the lowest 32 Kbytes of Flash memory (sector 0)
have been mapped to segment 1.The data to be written is loaded in register R13, the
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address to be programmed is loaded in register R11/R12 (segment number in R11, segment
offset in R12).
MOVR5, #01554h;load auxilary register R5 with command address ;(used in
command cycle 1)
MOVR6, #02AA8h;load auxilary register R6 with command address ;(used in
command cycle 2)
SXCTDPPO, #08h;push data page pointer 0 and load it to point to ;segment 2
MOVR7, #0A8h;load register R7 with 1st CI enable command
MOV[R5], R7;command cycle 1
MOVR7, #054h;load register R7 with 2cd CI enable command
MOV[R6], R7;command cycle 2
MOVR7, #0A0h;load register R7 with Program Word command
MOV[R5], R7;command cycle 3
POPDPP0;restore DPP0: following addressing to the Flash ;will use EXTended
instructions
;R11 contains the segment to be programmed
;R12 contains the segment offset address to be ;programmed
;R13 contains the data to be programmed
EXTSR11, #1;use EXTended addressing for next MOV instruction
MOV[R12], R13;command cycle 4: the EPC starts execution of ;Programming
Command
Data_Polling:
EXTSR11, #1;use EXTended addressing for next MOV instruction
MOVR7, [R12];read Flash Status register (FSB) in R7
MOVR6, R7;save it in R6 register
;Check if FSB.7 = Data.7 (i.e. R7.7 = R13.7)
XORR7, R13
JNBR7.7, Prog_OK
;Check if FSB.5 = 1 (Programming Error)
JNBR6.5, Data_Polling
;Programming Error: verify is Flash programmed ;data is OK
EXTSR11, #1;use EXTended addressing for next MOV instruction
MOVR7, [R12];read Flash Status register (FSB) in R7
;Check if FSB.7 = Data.7
XORR7, R13
JNBR7.7, Prog_OK
;Programming failed: Flash remains in Write ;Operation.
;To go back to normal Read operations, a Read/Reset ;command
;must be performed
Prog_Error:
MOVR7, #0F0h;load register R7 with Read/Reset command
EXTSR11, #1;use EXTended addressing for next MOV instruction
MOV[R12], R7;address is don’t care for Read/Reset command
...
;here place specific Error handling code
...
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...
;When programming operation finished succesfully, ;Flash is set back
automatically to normal Read Mode
Prog_OK:
....
....
Example 3 Performing the Block Erase command
We assume that in the initialization phase the lowest 32 Kbytes of Flash memory (sector 0)
have been mapped to segment 1.The registers R11/R12 contain an address related to the
block to be erased (segment number in R11, segment offset in R12, for example R11 = 01h,
R12 = 4000h will erase the block 1 - first 8-Kbyte block).
MOVR5, #01554h;load auxilary register R5 with command address ;(used in
command cycle 1)
MOVR6, #02AA8h;load auxilary register R6 with command address ;(used in
command cycle 2)
SXCTDPPO, #08h;push data page pointer 0 and load it to point ;to ;segment 2
MOVR7, #0A8h;load register R7 with 1st CI enable command
MOV[R5], R7;command cycle 1
MOVR7, #054h;load register R7 with 2cd CI enable command
MOV[R6], R7;command cycle 2
MOVR7, #080h;load register R7 with Block Erase command
MOV[R5], R7;command cycle 3
MOVR7, #0A8h;load register R7 with 1st CI enable command
MOV[R5], R7;command cycle 4
MOVR7, #054h;load register R7 with 2cd CI enable command
MOV[R6], R7;command cycle 5
POPDPP0;restore DPP0: following addressing to the Flash ;will use EXTended
instructions
;R11 contains the segment of the block to be erased
;R12 contains the segment offset address of the ;block to be erased
MOVR7, #030h;load register R7 with erase confirm code
EXTSR11, #1;use EXTended addressing for next MOV instruction
MOV[R12], R7;command cycle 6: the EPC starts execution of ;Erasing Command
Erase_Polling:
EXTSR11, #1;use EXTended addressing for next MOV instruction
MOVR7, [R12];read Flash Status register (FSB) in R7
;Check if FSB.7 = ‘1’ (i.e. R7.7 = ‘1’)
JB R7.7, Erase_OK
;Check if FSB.5 = 1 (Erasing Error)
JNBR7.5, Erase_Polling
;Programming failed: Flash remains in Write ;Operation.
;To go back to normal Read operations, a Read/Reset ;command
;must be performed
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Erase_Error:
MOVR7, #0F0h;load register R7 with Read/Reset command
EXTSR11, #1;use EXTended addressing for next MOV instruction
MOV[R12], R7;address is don’t care for Read/Reset command
...
;here place specific Error handling code
...
...
;When erasing operation finished succesfully,
;Flash is set back automatically to normal Read Mode
Erase_OK:
....
....
5.6
Bootstrap Loader
The built-in bootstrap loader (BSL) of the ST10F269 provides a mechanism to load the
startup program through the serial interface after reset. In this case, no external memory or
internal Flash memory is required for the initialization code starting at location 00’0000h
(see Figure 5).
The bootstrap loader moves code/data into the internal RAM, but can also transfer data via
the serial interface into an external RAM using a second level loader routine. Flash Memory
(internal or external) is not necessary, but it may be used to provide lookup tables or “corecode” like a set of general purpose subroutines for I/O operations, number crunching,
system initialization, etc.
The bootstrap loader can be used to load the complete application software into ROMless
systems, to load temporary software into complete systems for testing or calibration, or to
load a programming routine for Flash devices.
The BSL mechanism can be used for standard system startup as well as for special
occasions like system maintenance (firmer update) or end-of-line programming or testing.
5.6.1
Entering the Bootstrap Loader
The ST10F269 enters BSL mode when pin P0L.4 is sampled low at the end of a hardware
reset. In this case the built-in bootstrap loader is activated independent of the selected bus
mode.
The bootstrap loader code is stored in a special Boot-ROM. No part of the standard mask
Memory or Flash Memory area is required for this.
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After entering BSL mode and the respective initialization the ST10F269 scans the RXD0
line to receive a zero Byte, one start bit, eight ‘0’ data bits and one stop bit.
From the duration of this zero Byte it calculates the corresponding Baud rate factor with
respect to the current CPU clock, initializes the serial interface ASC0 accordingly and
switches pin TxD0 to output.
Using this baud rate, an identification Byte is returned to the host that provides the loaded
data.
This identification byte identifies the device to be booted. The identification byte is D5h for
ST10F269.
Figure 5. Bootstrap Loader Sequence
R
P
1)
4)
2)
R
3)
T
5)
C
6)
Internal Boot Memory (BSL) routine
32 Byte user software
1) BSL initialization time
2) Zero Byte (1 start bit, eight ‘0’ data bits, 1 stop bit), sent by host.
3) Identification Byte (D5h), sent by ST10F269.
4) 32 Bytes of code / data, sent by host.
5) Caution: TxD0 is only driven a certain time after reception of the zero
Byte.
When the ST10F269 has entered BSL mode, the following configuration is automatically set
(values that deviate from the normal reset values, are marked):
Watchdog Timer:
Disabled
Register SYSCON:
0E00h
Context Pointer CP:
FA00h
Register STKUN:
FA40h
Stack Pointer SP:
FA40h
Register STKOV:
FA0Ch 0C
Register S0CON:
8011h
Register BUSCON0:
acc. to startup
configuration
Register S0BG:
Acc. to ‘00’ Byte
P3.10 / TXD0:
‘1’
DP3.10:
‘1’
In this case, the watchdog timer is disabled, so the bootstrap loading sequence is not time
limited.
Pin TXD0 is configured as output, so the ST10F269 can return the identification byte.
Even if the internal Flash is enabled, no code can be executed out of it.
The hardware that activates the BSL during reset may be a simple pull-down resistor on
P0L.4 for systems that use this feature upon every hardware reset.
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A switchable solution (via jumper or an external signal) can be used for systems that only
temporarily use the bootstrap loader
(see Figure 6).
After sending the identification Byte the ASC0 receiver is enabled and is ready to
receive the initial 32 Bytes from the host. A half duplex connection is therefore sufficient to
feed the BSL.
5.6.2
Memory Configuration After Reset
The configuration (and the accessibility) of the ST10F269’s memory areas after reset in
Bootstrap-Loader mode differs from the standard case. Pin EA is not evaluated when BSL
mode is selected, and accesses to the internal Flash area are partly redirected, while the
ST10F269 is in BSL mode (see Table 4). All code fetches are made from the special BootROM, while data accesses read from the internal user Flash. Data accesses will return
undefined values on ROMless devices.
The code in the Boot-ROM is not an invariant feature of the ST10F269. User software
should not try to execute code from the internal Flash area while the BSL mode is still
active, as these fetches will be redirected to the Boot-ROM. The Boot-ROM will also “move”
to segment 1, when the internal Flash area is mapped to segment 1 (see Table 4).
Figure 6. Hardware Provisions to Activate the BSL
External
Signal
POL.4
POL.4
Normal Boot
BSL
RPOL.4
8kΩ
RPOL.4
8kΩ
Circuit 2
Circuit 1
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Internal Flash Memory
ST10F269Z1-ST10F269Z2
Table 4. Memory Configuration after Reset
Segment
16 Mbytes
Access to:
16 Mbytes
255
255
external
bus
disabled
2
-
external
bus
enabled
1
0
16 Mbytes
Access:
depends on
reset config
EA, Port0
2
1
IRAM
IRAM
IRAM
Flash
Segment
255
2
1
Test
Access to:
Segment
0
internal
Flash
Flash enabled
User
Test
Flash
internal
Flash
Flash enabled
User
0
User
Flash
depends on
reset config
EA, Port0
BSL mode active
Yes (P0L.4=’0’)
Yes (P0L.4=’0’)
No (P0L.4=’1’)
EA pin
High
Low
Access to application
Code fetch from internal
Flash area
Test-Flash access
Test-Flash access
User Flash access
Data fetch from internal
Flash area
User Flash access
User Flash access
User Flash access
5.6.3
Loading the Startup Code
After sending the identification byte the BSL enters a loop to receive 32 bytes via ASC0.
These bytes are stored sequentially into locations 00’FA40h through 00’FA5Fh of the
internal RAM. So up to 16 instructions may be placed into the RAM area. To execute the
loaded code the BSL then jumps to location 00’FA40h, which is the first loaded instruction.
The bootstrap loading sequence is now terminated, the ST10F269Z1-ST10F269Z2 remain
in BSL mode, however. Most probably the initially loaded routine will load additional code or
data, as an average application is likely to require substantially more than 16 instructions.
This second receive loop may directly use the pre-initialized interface ASC0 to receive data
and store it to arbitrary user-defined locations.
This second level of loaded code may be the final application code. It may also be another,
more sophisticated, loader routine that adds a transmission protocol to enhance the integrity
of the loaded code or data. It may also contain a code sequence to change the system
configuration and enable the bus interface to store the received data into external memory.
This process may go through several iterations or may directly execute the final application.
In all cases the ST10F269 will still run in BSL mode, that means with the watchdog timer
disabled and limited access to the internal Flash area.
All code fetches from the internal Flash area (00’0000h...00’7FFFh or 01’0000h...01’7FFFh,
if mapped to segment 1) are redirected to the special Boot-ROM. Data fetches access will
access the internal Boot-ROM of the ST10F269, if any is available, but will return undefined
data on ROMless devices.
5.6.4
Exiting Bootstrap Loader Mode
In order to execute a program in normal mode, the BSL mode must be terminated first. The
ST10F269 exits BSL mode upon a software reset (ignores the level on P0L.4) or a hardware
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ST10F269Z1-ST10F269Z2
Internal Flash Memory
reset (P0L.4 must be high). After a reset the ST10F269Z1-ST10F269Z2 will start executing
from location 00’0000h of the internal Flash or the external memory, as programmed via pin
EA.
5.6.5
Choosing the Baud Rate for the BSL
The calculation of the serial baud rate for ASC0 from the length of the first zero Byte that is
received, allows the operation of the bootstrap loader of the ST10F269Z1-ST10F269Z2 with
a wide range of baud rates. However, the upper and lower limits have to be kept, in order to
insure proper data transfer.
f CPU
-------------------------------------------------B
32 × ( S0BRL + 1 )
S
The ST10F269Z1-ST10F269Z2 use timer T6 to measure the length of the initial zero Byte.
The quantization uncertainty of this measurement implies the first deviation from the real
baud rate, the next deviation is implied by the computation of the S0BRL reload value from
the timer contents. The formula below shows the association:
T6 – 36
S0BRL = -------------------72
f CPU
9
, T6 = --- × ----------------4 B Host
For a correct data transfer from the host to the ST10F269Z1-ST10F269Z2 the maximum
deviation between the internal initialized baud rate for ASC0 and the real baud rate of the
host should be below 2.5 %. The deviation (FB, in percent) between host baud rate and
ST10F269Z1-ST10F269Z2 baud rate can be calculated via the formula below:
B Contr – B Host
F B = ------------------------------------------- × 100 % , FB ≤ 2.5 %
B Contr
Function (FB) does not consider the tolerances of oscillators and other devices supporting
the serial communication.
This baud rate deviation is a nonlinear function depending on the CPU clock and the baud
rate of the host. The maximum of the function (FB) increases with the host baud rate due to
the smaller baud rate pre-scaler factors and the implied higher quantization error (see
Figure 7).
The minimum baud rate (BLow in Figure 7) is determined by the maximum count capacity of
timer T6, when measuring the zero Byte, and it depends on the CPU clock. Using the
maximum T6 count 216 in the formula the minimum baud rate can be calculated. The lowest
standard baud rate in this case would be 1200 baud. Baud rates below BLow would cause
T6 to overflow. In this case ASC0 cannot be initialized properly.
The maximum baud rate (BHigh in Figure 7) is the highest baud rate where the deviation still
does not exceed the limit, so all baud rates between BLow and BHigh are below the deviation
limit. The maximum standard baud rate that fulfills this requirement is 19200 baud.
Higher baud rates, however, may be used as long as the actual deviation does not exceed
the limit. A certain baud rate (marked ’I’ in Figure 7) may violate the deviation limit, while an
even higher baud rate (marked ’II’ in Figure 7) stays very well below it. This depends on the
host interface.
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Internal Flash Memory
ST10F269Z1-ST10F269Z2
Figure 7. Baud Rate Deviation Between Host and ST10F269Z1-ST10F269Z2
I
FB
2.5%
BLow
BHigh
BHOST
II
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6
Central Processing Unit (CPU)
Central Processing Unit (CPU)
The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and
dedicated SFRs. Additional hardware has been added for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Most of the ST10F269Z1-ST10F269Z2 instructions can be executed in one instruction cycle
which requires 50 ns at 25 MHz CPU clock and 62.5 ns at 32 MHz CPU clock. For example,
shift and rotate instructions are processed in one instruction cycle independent of the
number of bits to be shifted.
Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x
16-bit multiplication in 5 cycles and a 32/16-bit division in 10 cycles.
The jump cache reduces the execution time of repeatedly performed jumps in a loop, from
2 cycles to 1 cycle.
The CPU uses a bank of 16 word registers to run the current context. This bank of General
Purpose Registers (GPR) is physically stored within the on-chip Internal RAM (IRAM) area.
A Context Pointer (CP) register determines the base address of the active register bank to
be accessed by the CPU.
The number of register banks is only restricted by the available Internal RAM space. For
easy parameter passing, a register bank may overlap others.
A system stack of up to 1024 bytes is provided as a storage for temporary data. The system
stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack
pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer
value upon each stack access for the detection of a stack overflow or underflow.
Figure 8. CPU Block Diagram (MAC Unit not included)
16
CPU
MDH
MDL
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr
4-Stage
Pipeline
memory
R15
Mul./Div.-HW
Bit-Mask Gen.
128K/256K Byte
Flash
2K Byte
Internal
RAM
ALU
Bank
n
General
Purpose
Registers
16-Bit
32
PSW
SYSCON
Barrel-Shift
CP
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
Data Pg. Ptrs
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Code Seg. Ptr.
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Bank
i
16
Bank
0
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Central Processing Unit (CPU)
ST10F269Z1-ST10F269Z2
The System Configuration Register SYSCON
This bit-addressable register provides general system configuration and control functions.
The reset value for register SYSCON depends on the state of the PORT0 pins during reset.
SYSCON (FF12H / 89H)
SFR Reset Value: 0xx0h
15
14
13
12
11
10
9
8
7
6
5
4
STKSZ
ROM
S1
SGT
DIS
ROM
EN
BYT
DIS
CLK
EN
WR
CFG
CS
CFG
PWD
CFG
OWD
DIS
RW
RW
RW
RW1
RW1
RW
RW1
RW
RW
RW
3
2
BDR XPEN
STEN
RW
RW
1
0
VISI XPERBLE SHARE
RW
RW
1. These bits are set directly or indirectly according to PORT0 and EA pin configuration during reset sequence.
2. Register SYSCON cannot be changed after execution of the EINIT instruction.
XPEN
XBUS Peripheral Enable Bit
0
Accesses to the on-chip X-Peripherals and their functions are disabled
1
The on-chip X-Peripherals are enabled and can be accessed.
BDRSTEN
Bidirectional Reset Enable
0
RSTIN pin is an input pin only. SW Reset or WDT Reset have no effect on this pin
1
RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset
sequence.
OWDDIS
Oscillator Watchdog Disable Control
0
Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors
XTAL1 activity. If there is no activity on XTAL1 for at least 1 ms, the CPU clock is
switched automatically to PLL’s base frequency (2 to 10MHz).
1
OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1
signal. The PLL is turned off to reduce power supply current.
PWDCFG
Power Down Mode Configuration Control
0
Power Down Mode can only be entered during PWRDN instruction execution if NMI
pin is low, otherwise the instruction has no effect. To exit Power Down Mode, an
external reset must occurs by asserting the RSTIN pin.
1
Power Down Mode can only be entered during PWRDN instruction execution if all
enabled fast external interrupt EXxIN pins are in their inactive level. Exiting this
mode can be done by asserting one enabled EXxIN pin.
CSCFG
6.1
Chip Select Configuration Control
0
Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE
1
Unlatched Chip Select lines: CSx change with rising edge of ALE
Multiplier-accumulator Unit (MAC)
The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order
to improve the performances of the ST10 Family in signal processing algorithms.
Signal processing needs at least three specialized units operating in parallel to achieve
maximum performance:
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•
A Multiply-Accumulate Unit,
•
An Address Generation Unit, able to feed the MAC Unit with 2 operands per cycle,
•
A Repeat Unit, to execute series of multiply-accumulate instructions.
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Central Processing Unit (CPU)
The existing ST10 CPU has been modified to include new addressing capabilities which
enable the CPU to supply the new co-processor with up to 2 operands per instruction cycle.
This new co-processor (so-called MAC) contains a fast multiply-accumulate unit and a
repeat unit.
The co-processor instructions extend the ST10 CPU instruction set with multiply, multiplyaccumulate, 32-bit signed arithmetic operations.
A new transfer instruction CoMOV has also been added to take benefit of the new
addressing capabilities.
6.1.1
Features
Enhanced Addressing Capabilities
•
New addressing modes including a double indirect addressing mode with pointer postmodification.
•
Parallel Data Move: this mechanism allows one operand move during MultiplyAccumulate instructions without penalty.
•
New transfer instructions CoSTORE (for fast access to the MAC SFRs) and CoMOV
(for fast memory to memory table transfer).
Multiply-Accumulate Unit
•
One-cycle execution for all MAC operations.
•
16 x 16-bit signed/unsigned parallel multiplier.
•
40-bit signed arithmetic unit with automatic saturation mode.
•
40-bit accumulator.
•
8-bit left/right shifter.
•
Full instruction set with multiply and multiply-accumulate, 32-bit signed arithmetic and
compare instructions.
Program Control
•
Repeat Unit: allows some MAC co-processor instructions to be repeated up to 8192
times. Repeated instructions may be interrupted.
•
MAC interrupt (Class B Trap) on MAC condition flags.
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Central Processing Unit (CPU)
ST10F269Z1-ST10F269Z2
Figure 9. MAC Unit Architecture
Operand 1
16
GPR Pointers (1)
Operand 2
16
IDX0 Pointer
IDX1 Pointer
QR0 GPR Offset Register
QR1 GPR Offset Register
QX0 IDX Offset Register
QX1 IDX Offset Register
16 x 16
signed/unsigned
Multiplier
Concatenation
32
32
Mux
Sign Extend
MRW
Scaler
0h
40
Repeat Unit
Interrupt
Controller
08000h
40 40
0h
Mux
40
MCW
40
40
Mux
40
A
B
40-bit Signed Arithmetic Unit
ST10 CPU
MSW
Flags MAE
40
MAH
MAL
Control Unit
40
8-bit Left/Right
Shifter
1. Shared with standard ALU.
6.2
Instruction Set Summary
Table 5 lists the instructions of the ST10F269Z1-ST10F269Z2. The various addressing
modes, instruction operation, parameters for conditional execution of instructions, opcodes
and a detailed description of each instruction can be found in the “ST10 Family
Programming Manual”.
Table 5. Instruction Set Summary
Mnemonic
Description
Bytes
ADD(B)
Add word (byte) operands
2/4
ADDC(B)
Add word (byte) operands with Carry
2/4
SUB(B)
Subtract word (byte) operands
2/4
SUBC(B)
Subtract word (byte) operands with Carry
2/4
MUL(U)
(Un)Signed multiply direct GPR by direct GPR (16-16-bit)
2
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Central Processing Unit (CPU)
Table 5. Instruction Set Summary (continued)
Mnemonic
Description
Bytes
DIV(U)
(Un)Signed divide register MDL by direct GPR (16-/16-bit)
2
DIVL(U)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)
2
CPL(B)
Complement direct word (byte) GPR
2
NEG(B)
Negate direct word (byte) GPR
2
AND(B)
Bit-wise AND, (word/byte operands)
2/4
OR(B)
Bit-wise OR, (word/byte operands)
2/4
XOR(B)
Bit-wise XOR, (word/byte operands)
2/4
BCLR
Clear direct bit
2
BSET
Set direct bit
2
BMOV(N)
Move (negated) direct bit to direct bit
4
BAND, BOR, BXOR
AND/OR/XOR direct bit with direct bit
4
BCMP
Compare direct bit to direct bit
4
BFLDH/L
Bit-wise modify masked high/low byte of bit-addressable direct word memory
with immediate data
4
CMP(B)
Compare word (byte) operands
2/4
CMPD1/2
Compare word data to GPR and decrement GPR by 1/2
2/4
CMPI1/2
Compare word data to GPR and increment GPR by 1/2
2/4
PRIOR
Determine number of shift cycles to normalize direct word GPR and store
result in direct word GPR
2
SHL / SHR
Shift left/right direct word GPR
2
ROL / ROR
Rotate left/right direct word GPR
2
ASHR
Arithmetic (sign bit) shift right direct word GPR
2
MOV(B)
Move word (byte) data
2/4
MOVBS
Move byte operand to word operand with sign extension
2/4
MOVBZ
Move byte operand to word operand with zero extension
2/4
JMPA, JMPI, JMPR
Jump absolute/indirect/relative if condition is met
4
JMPS
Jump absolute to a code segment
4
J(N)B
Jump relative if direct bit is (not) set
4
JBC
Jump relative and clear bit if direct bit is set
4
JNBS
Jump relative and set bit if direct bit is not set
4
CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met
4
CALLS
Call absolute subroutine in any code segment
4
PCALL
Push direct word register onto system stack and call absolute subroutine
4
TRAP
Call interrupt service routine via immediate trap number
2
PUSH, POP
Push/pop direct word register onto/from system stack
2
SCXT
Push direct word register onto system stack and update register with word
operand
4
RET
Return from intra-segment subroutine
2
RETS
Return from inter-segment subroutine
2
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Central Processing Unit (CPU)
ST10F269Z1-ST10F269Z2
Table 5. Instruction Set Summary (continued)
Mnemonic
Description
Bytes
Return from intra-segment subroutine and pop direct
word register from system stack
2
RETI
Return from interrupt service subroutine
2
SRST
Software Reset
4
IDLE
Enter Idle Mode
4
PWRDN
Enter Power Down Mode (supposes NMI-pin being low)
4
RETP
SRVWDT
Service Watchdog Timer
4
DISWDT
Disable Watchdog Timer
4
EINIT
Signify End-of-Initialization on RSTOUT-pin
4
ATOMIC
Begin ATOMIC sequence
2
EXTR
Begin EXTended Register sequence
2
EXTP(R)
Begin EXTended Page (and Register) sequence
2/4
EXTS(R)
Begin EXTended Segment (and Register) sequence
2/4
NOP
Null operation
2
6.3
MAC Coprocessor Specific Instructions
Table 6 gives an overview of the MAC instruction set. All the mnemonics are listed with the
addressing modes that can be used with each instruction.
For each combination of mnemonic and addressing mode this table indicates if it is
repeatable or not.
New addressing capabilities enable the CPU to supply the MAC with up to 2 operands per
instruction cycle. MAC instructions: multiply, multiply-accumulate, 32-bit signed arithmetic
operations and the CoMOV transfer instruction have been added to the standard instruction
set. Full details are provided in the ‘ST10 Family Programming Manual’. Double indirect
addressing requires two pointers. Any GPR can be used for one pointer, the other pointer is
provided by one of two specific SFRs IDX0 and IDX1. Two pairs of offset registers QR0/QR1
and QX0/QX1 are associated with each pointer (GPR or IDXi).
The GPR pointer allows access to the entire memory space, but IDXi are limited to the
internal Dual-Port RAM, except for the CoMOV instruction.
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Central Processing Unit (CPU)
Table 6. MAC specific instructions
Mnemonic
Addressing Modes
Repeatability
CoMUL
CoMULu
CoMULus
CoMULsu
CoMULCoMULuCoMULusCoMULsuCoMUL, rnd
CoMULu, rnd
CoMULus, rnd
CoMULsu, rnd
CoMAC
CoMACu
CoMACus
CoMACsu
CoMACCoMACuCoMACusCoMACsuCoMAC, rnd
CoMACu, rnd
CoMACus, rnd
CoMACsu, rnd
CoMACR
CoMACRu
CoMACRus
CoMACRsu
CoMACR, rnd
CoMACRu, rnd
CoMACRus, rnd
CoMACRsu, rnd
CoNOP
CoNEG
CoNEG, rnd
CoRND
CoSTORE
CoMOV
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
No
No
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
Yes
Yes
Rwn, Rwm
[IDXi⊗], [Rwn⊗]
Rwn, [RWm⊗]
No
No
No
[Rwm⊗]
[IDXi⊗]
[IDXi⊗], [Rwm⊗]
Yes
Yes
-
No
Rwn, CoReg
[Rwn⊗] , Coreg
[IDXi⊗], [Rwm⊗]
No
Yes
Yes
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Central Processing Unit (CPU)
ST10F269Z1-ST10F269Z2
Table 6. MAC specific instructions (continued)
Mnemonic
Addressing Modes
Repeatability
CoMACM
CoMACMu
CoMACMus
CoMACMsu
CoMACMCoMACMuCoMACMusCoMACMsuCoMACM, rnd
CoMACMu, rnd
CoMACMus, rnd
CoMACMsu, rnd
[IDXi⊗], [Rwm⊗]
Yes
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
Yes
Yes
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
No
No
Rwm
#data4
[Rwm⊗]
Yes
No
Yes
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
No
No
CoMACMR
CoMACMRu
CoMACMRus
CoMACMRsu
CoMACMR, rnd
CoMACMRu, rnd
CoMACMRus, rnd
CoMACMRsu, rnd
CoADD
CoADD2
CoSUB
CoSUB2
CoSUBR
CoSUB2R
CoMAX
CoMIN
CoLOAD
CoLOADCoLOAD2
CoLOAD2CoCMP
CoSHL
CoSHR
CoASHR
CoASHR, rnd
CoABS
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Central Processing Unit (CPU)
Table 7 shows the various combinations of pointer post-modification for each of these 2 new
addressing modes. In this document the symbols “[RwnÄ]” and “[IDXiÄ]” refer to these
addressing modes.
Table 7. Pointer Post-modification Combinations for IDXi and Rwn
Symbol
Mnemonic
(IDXi) ←(IDXi)
[IDXi]
“[IDXi⊗]” stands for
“[Rwn⊗]” stands for
Address Pointer Operation
(no-op)
[IDXi+]
(IDXi) ←(IDXi) + 2
(i=0,1)
[IDXi-]
(IDXi) ←(IDXi) - 2
(i=0,1)
[IDXi + QXj]
(IDXi) ←(IDXi) + (QXj)
(i, j =0,1)
[IDXi - QXj]
(IDXi) ←(IDXi) - (QXj)
(i, j =0,1)
[Rwn]
(Rwn) ←(Rwn)
(no-op)
[Rwn+]
(Rwn) ←(Rwn) + 2
(n=0-15)
[Rwn-]
(Rwn) ←(Rwn) - 2
(n=0-15)
[Rwn + QRj]
(Rwn) ←(Rwn) + (QRj)
(n=0-15; j =0,1)
[Rwn - QRj]
(Rwn) ←(Rwn) - (QRj)
(n=0-15; j =0,1)
Table 8. MAC Registers Referenced as ‘CoReg‘
Registers
Description
Address in Opcode
MSW
MAC-Unit Status Word
00000b
MAH
MAC-Unit Accumulator High
00001b
MAS
“limited” MAH /signed
00010b
MAL
MAC-Unit Accumulator Low
00100b
MCW
MAC-Unit Control Word
00101b
MRW
MAC-Unit Repeat Word
00110b
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External Bus Controller
7
ST10F269Z1-ST10F269Z2
External Bus Controller
All of the external memory accesses are performed by the on-chip external bus controller.
The EBC can be programmed to single chip mode when no external memory is required, or
to one of four different external memory access modes:
•
16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed
•
16- / 18- / 20- / 24-bit addresses and 16-bit data, multiplexed
•
16- / 18- / 20- / 24-bit addresses and 8-bit data, multiplexed
•
16- / 18- / 20- / 24-bit addresses and 8-bit data, demultiplexed
In demultiplexed bus modes addresses are output on PORT1 and data is input / output on
PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use
PORT0 for input / output.
Timing characteristics of the external bus interface (memory cycle time, memory tri-state
time, length of ALE and read / write delay) are programmable giving the choice of a wide
range of memories and external peripherals.
Up to 4 independent address windows may be defined (using register pairs ADDRSELx /
BUSCONx) to access different resources and bus characteristics.
These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3
and BUSCON2 overrides BUSCON1.
All accesses to locations not covered by these 4 address windows are controlled by
BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated in order
to save external glue logic. Access to very slow memories is supported by a ‘Ready’
function.
A HOLD / HLDA protocol is available for bus arbitration which shares external resources
with other bus masters.
The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN
once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In
master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to’1’ the
slave mode is selected where pin HLDA is switched to input. This directly connects the
slave controller to another master controller without glue logic.
For applications which require less external memory space, the address space can be
restricted to 1 Mbytes, 256 Kbytes or to 64 Kbytes. Port 4 outputs all 8 address lines if an
address space of 16M Bytes is used, otherwise four, two or no address lines.
Chip select timing can be made programmable. By default (after reset), the CSx lines
change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the
SYSCON register the CSx lines change with the rising edge of ALE.
The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers.
When the READY function is enabled for a specific address window, each bus cycle within
the window must be terminated with the active level defined by bit RDYPOL in the
associated BUSCON register.
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7.1
External Bus Controller
Programmable Chip Select Timing Control
The ST10F269 allows the user to adjust the position of the CSx line changes. By default
(after reset), the CSx lines change half a CPU clock cycle (12.5 ns at 40 MHz of CPU clock
and 31.25 ns at 32 MHz of CPU clock) after the rising edge of ALE. With the CSCFG bit set
in the SYSCON register the CSx lines change with the rising edge of ALE, thus the CSx
lines and the address lines change at the same time (see Figure 10).
7.2
READY Programmable Polarity
The active level of the READY pin can be selected by software via the RDYPOL bit in the
BUSCONx registers.
When the READY function is enabled for a specific address window, each bus cycle within
this window must be terminated with the active level defined by this RDYPOL bit in the
associated BUSCON register.
BUSCONx registers are described in Section 20.2: System Configuration Registers.
Note:
ST10F269Z1-ST10F269Z2 have no internal pull-up resistor on READY pin.
Figure 10. Chip Select Delay
Normal Demultiplexed
Segment (P4)
ALE Lengthen Demultiplexed
Bus Cycle
Bus Cycle
Address (P1)
ALE
Normal CSx
Unlatched CSx
Data
Data
BUS (P0)
RD
Data
Data
BUS (P0)
WR
Read/Write
Read/Write
Delay
Delay
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8
ST10F269Z1-ST10F269Z2
Interrupt System
The interrupt response time for internal program execution is from 125 ns to 300 ns at
40 MHz CPU clock and from 156.25 ns to 375 ns at 32 MHz CPU clock.
The ST10F269Z1-ST10F269Z2 architecture supports several mechanisms for fast and
flexible response to service requests that can be generated from various sources (internal
or external) to the microcontroller. Any of these interrupt requests can be serviced by the
Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’
from the current CPU activity to perform a PEC service. A PEC service implies a single Byte
or Word data transfer between any two memory locations with an additional increment of
either the PEC source or destination pointer. An individual PEC transfer counter is implicitly
decremented for each PEC service except when performing in the continuous transfer
mode. When this counter reaches zero, a standard interrupt is performed to the
corresponding source related vector location. PEC services are very well suited to perform
the transmission or the reception of blocks of data. The ST10F269 has 8 PEC channels,
each of them offers such fast interrupt-driven data transfer capabilities.
An interrupt control register which contains an interrupt request flag, an interrupt enable flag
and an interrupt priority bit-field is dedicated to each existing interrupt source. Thanks to its
related register, each source can be programmed to one of sixteen interrupt priority levels.
Once starting to be processed by the CPU, an interrupt service can only be interrupted by a
higher prioritized service request. For the standard interrupt processing, each of the
possible interrupt sources has a dedicated vector location.
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
8.1
External Interrupts
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge,
falling edge or both edges).
Fast external interrupts may also have interrupt sources selected from other peripherals; for
example the CANx controller receive signal (CANx_RxD) can be used to interrupt the
system. This new function is controlled using the ‘External Interrupt Source Selection’
register EXISEL.
EXISEL (F1DAH / EDH)
ESFR Reset Value: 0000H
15
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14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EXI7SS
EXI6SS
EXI5SS
EXI4SS
EXI3SS
EXI2SS
EXI1SS
EXI0SS
RW
RW
RW
RW
RW
RW
RW
RW
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EXIxSS
8.2
Interrupt System
External Interrupt x Source Selection (x=7...0)
‘00’: Input from associated Port 2 pin.
‘01’: Input from “alternate source”.
‘10’: Input from Port 2 pin ORed with “alternate source”.
‘11’: Input from Port 2 pin ANDed with “alternate source”.
EXIxSS
Port 2 pin
Alternate Source
0
P2.8
CAN1_RxD
1
P2.9
CAN2_RxD
2
P2.10
RTCSI (Timed)
3
P2.11
RTCAI (Alarm)
4...7
P2.12...15
Not used (zero)
Interrupt Registers and Vectors Location List
Table 9 shows all the available ST10F269 interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:
Table 9. Interrupt Sources
Source of Interrupt or PEC Service
Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Register 0
CC0IR
CC0IE
CC0INT
00’0040h
10h
CAPCOM Register 1
CC1IR
CC1IE
CC1INT
00’0044h
11h
CAPCOM Register 2
CC2IR
CC2IE
CC2INT
00’0048h
12h
CAPCOM Register 3
CC3IR
CC3IE
CC3INT
00’004Ch
13h
CAPCOM Register 4
CC4IR
CC4IE
CC4INT
00’0050h
14h
CAPCOM Register 5
CC5IR
CC5IE
CC5INT
00’0054h
15h
CAPCOM Register 6
CC6IR
CC6IE
CC6INT
00’0058h
16h
CAPCOM Register 7
CC7IR
CC7IE
CC7INT
00’005Ch
17h
CAPCOM Register 8
CC8IR
CC8IE
CC8INT
00’0060h
18h
CAPCOM Register 9
CC9IR
CC9IE
CC9INT
00’0064h
19h
CAPCOM Register 10
CC10IR
CC10IE
CC10INT
00’0068h
1Ah
CAPCOM Register 11
CC11IR
CC11IE
CC11INT
00’006Ch
1Bh
CAPCOM Register 12
CC12IR
CC12IE
CC12INT
00’0070h
1Ch
CAPCOM Register 13
CC13IR
CC13IE
CC13INT
00’0074h
1Dh
CAPCOM Register 14
CC14IR
CC14IE
CC14INT
00’0078h
1Eh
CAPCOM Register 15
CC15IR
CC15IE
CC15INT
00’007Ch
1Fh
CAPCOM Register 16
CC16IR
CC16IE
CC16INT
00’00C0h
30h
CAPCOM Register 17
CC17IR
CC17IE
CC17INT
00’00C4h
31h
CAPCOM Register 18
CC18IR
CC18IE
CC18INT
00’00C8h
32h
CAPCOM Register 19
CC19IR
CC19IE
CC19INT
00’00CCh
33h
CAPCOM Register 20
CC20IR
CC20IE
CC20INT
00’00D0h
34h
CAPCOM Register 21
CC21IR
CC21IE
CC21INT
00’00D4h
35h
CAPCOM Register 22
CC22IR
CC22IE
CC22INT
00’00D8h
36h
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Table 9. Interrupt Sources (continued)
Source of Interrupt or PEC Service
Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Register 23
CC23IR
CC23IE
CC23INT
00’00DCh
37h
CAPCOM Register 24
CC24IR
CC24IE
CC24INT
00’00E0h
38h
CAPCOM Register 25
CC25IR
CC25IE
CC25INT
00’00E4h
39h
CAPCOM Register 26
CC26IR
CC26IE
CC26INT
00’00E8h
3Ah
CAPCOM Register 27
CC27IR
CC27IE
CC27INT
00’00ECh
3Bh
CAPCOM Register 28
CC28IR
CC28IE
CC28INT
00’00F0h
3Ch
CAPCOM Register 29
CC29IR
CC29IE
CC29INT
00’0110h
44h
CAPCOM Register 30
CC30IR
CC30IE
CC30INT
00’0114h
45h
CAPCOM Register 31
CC31IR
CC31IE
CC31INT
00’0118h
46h
CAPCOM Timer 0
T0IR
T0IE
T0INT
00’0080h
20h
CAPCOM Timer 1
T1IR
T1IE
T1INT
00’0084h
21h
CAPCOM Timer 7
T7IR
T7IE
T7INT
00’00F4h
3Dh
CAPCOM Timer 8
T8IR
T8IE
T8INT
00’00F8h
3Eh
GPT1 Timer 2
T2IR
T2IE
T2INT
00’0088h
22h
GPT1 Timer 3
T3IR
T3IE
T3INT
00’008Ch
23h
GPT1 Timer 4
T4IR
T4IE
T4INT
00’0090h
24h
GPT2 Timer 5
T5IR
T5IE
T5INT
00’0094h
25h
GPT2 Timer 6
T6IR
T6IE
T6INT
00’0098h
26h
GPT2 CAPREL Register
CRIR
CRIE
CRINT
00’009Ch
27h
A/D Conversion Complete
ADCIR
ADCIE
ADCINT
00’00A0h
28h
A/D Overrun Error
ADEIR
ADEIE
ADEINT
00’00A4h
29h
ASC0 Transmit
S0TIR
S0TIE
S0TINT
00’00A8h
2Ah
ASC0 Transmit Buffer
S0TBIR
S0TBIE
S0TBINT
00’011Ch
47h
ASC0 Receive
S0RIR
S0RIE
S0RINT
00’00ACh
2Bh
ASC0 Error
S0EIR
S0EIE
S0EINT
00’00B0h
2Ch
SSC Transmit
SCTIR
SCTIE
SCTINT
00’00B4h
2Dh
SSC Receive
SCRIR
SCRIE
SCRINT
00’00B8h
2Eh
SSC Error
SCEIR
SCEIE
SCEINT
00’00BCh
2Fh
PWM Channel 0...3
PWMIR
PWMIE
PWMINT
00’00FCh
3Fh
CAN1 Interface
XP0IR
XP0IE
XP0INT
00’0100h
40h
CAN2 Interface
XP1IR
XP1IE
XP1INT
00’0104h
41h
FLASH Ready / Busy
XP2IR
XP2IE
XP2INT
00’0108h
42h
PLL Unlock/OWD
XP3IR
XP3IE
XP3INT
00’010Ch
43h
Hardware traps are exceptions or error conditions that arise during run-time. They cause
immediate non-maskable system reaction similar to a standard interrupt service (branching
to a dedicated vector table location).
The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any other program execution. Hardware trap services cannot not
be interrupted by standard interrupt or by PEC interrupts.
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8.3
Interrupt System
Interrupt Control Registers
All interrupt control registers are identically organized. The lower 8 bits of an interrupt
control register contain the complete interrupt status information of the associated source,
which is required during one round of prioritization, the upper 8 bits of the respective register
are reserved. All interrupt control registers are bit addressable and all bits can be read or
written via software.
This allows each interrupt source to be programmed or modified with just one instruction.
When accessing interrupt control registers through instructions which operate on Word data
types, their upper 8 bits (15...8) will return zeros, when read, and will discard written data.
The layout of the Interrupt Control registers shown below applies to each xxIC register,
where xx stands for the mnemonic for the respective source.
xxIC (yyyyh / zzh)
SFR Area Reset Value: - - 00h
15
14
13
12
11
10
9
8
7
6
-
-
-
-
-
-
-
-
xxIR
xxIE
5
4
ILVL
3
2
1
GLVL
0
RW
RW
RW
RW
GLVL
Group Level
ILVL
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
Interrupt Priority Level
xxIE
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
Interrupt Enable Control Bit (individually enables/disables a specific source)
xxIR
‘0’: Interrupt Request is disabled
‘1’: Interrupt Request is enabled
Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
8.4
Exception and Error Traps List
Table 10 shows all of the possible exceptions or error conditions that can arise during runtime.
Table 10. Trap Priorities
Exception Condition
Reset Functions:
– Hardware Reset
– Software Reset
– Watchdog Timer Overflow
Trap
Flag
-
Trap
Vector
Vector
Location
Trap
Number
Trap(1)
Priority
RESET
RESET
RESET
00’0000h
00’0000h
00’0000h
00h
00h
00h
III
III
III
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Table 10. Trap Priorities (continued)
Trap
Flag
Trap
Vector
Vector
Location
Trap
Number
Trap(1)
Priority
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
00’0008h
00’0010h
00’0018h
02h
04h
06h
II
II
II
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
0Ah
0Ah
0Ah
0Ah
0Ah
I
I
I
I
I
Reserved
-
-
[002Ch - 003Ch]
[0Bh - 0Fh]
Software Traps
TRAP Instruction
-
-
Any
0000h – 01FCh
in steps of 4h
Any
[00h - 7Fh]
Exception Condition
Class A Hardware Traps:
– Non-Maskable Interrupt
– Stack Overflow
– Stack Underflow
Class B Hardware Traps:
Undefined Opcode
Protected Instruction Fault
Illegal word Operand Access
Illegal Instruction Access
Illegal External Bus Access
Current
CPU
Priority
1. All the class B traps have the same trap number (and vector) and the same lower priority compare to the class A traps and
to the resets.
Each class A traps has a dedicated trap number (and vector). They are prioritized in the second priority level.
The resets have the highest priority level and the same trap number.
The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced.
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9
Capture/Compare (CAPCOM) Units
Capture/Compare (CAPCOM) Units
The ST10F269 has two 16 channels CAPCOM units as described in Figure 11. These
support generation and control of timing sequences on up to 32 channels with a maximum
resolution of 200 ns at 40 MHz CPU clock and 250 ns at 32 MHz CPU clock. The CAPCOM
units are typically used to handle high speed I/O tasks such as pulse and waveform
generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software
timing, or time recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases
for the capture/compare register array
(See Figure 12 and Figure 13).
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to application specific requirements. In addition, external count inputs
for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers
relative to external events.Each of the two capture/compare register arrays contain 16 dual
purpose capture/compare registers, each of which may be individually allocated to either
CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare
functions. Each of the 32 registers has one associated port pin which serves as an input pin
for triggering the capture function, or as an output pin to indicate the occurrence of a
compare event. Figure 11 shows the basic structure of the two CAPCOM units.
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Figure 11. CAPCOM Unit Block Diagram
Reload Register TxREL
CPU
Clock
x = 0, 7
2n n = 3...10
TxIN
Pin
Interrupt
Request
Tx
Input
Control
CAPCOM Timer Tx
Mode
Control
(Capture
or
Compare)
Sixteen 16-bit
(Capture/Compare)
Registers
GPT2 Timer T6
Over / Underflow
Pin
16
Capture inputs
Compare outputs
16
Capture / Compare(1)
Interrupt Requests
Pin
CPU
Clock
2n n = 3...10
Ty
Input
Control
Interrupt
Request
CAPCOM Timer Ty
GPT2 Timer T6
Over / Underflow
Reload Register TyREL
1. The CAPCOM2 unit provides 16 capture inputs, but only 12 compare outputs. CC24I to CC27I are inputs only.
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Capture/Compare (CAPCOM) Units
Figure 12. Block Diagram of CAPCOM Timers T0 and T7
Reload Register TxREL
Txl
Input
Control
CPU
Clock
X
GPT2 Timer T6
Over / Underflow
MUX
CAPCOM Timer Tx
TxIR
Interrupt
Request
Edge Select
TxR
Txl TxM
TxIN Pin
x = 0, 7
Txl
Figure 13. Block Diagram of CAPCOM Timers T1 and T8
Reload Register TxREL
Txl
CPU
Clock
X
GPT2 Timer T6
Over / Underflow
MUX
CAPCOM Timer Tx
TxM
Note:
TxR
TxIR
Interrupt
Request
x = 1, 8
When an external input signal is connected to the input lines of both T0 and T7, these timers
count the input signal synchronously. Thus the two timers can be regarded as one timer
whose contents can be compared with 32 capture registers.
When a capture/compare register has been selected for capture mode, the current contents
of the allocated timer will be latched (captured) into the capture/compare register in
response to an external event at the port pin which is associated with this register. In
addition, a specific interrupt request for this capture/compare register is generated.
Either a positive, a negative, or both a positive and a negative external signal transition at
the pin can be selected as the triggering event. The contents of all registers which have
been selected for one of the five compare modes are continuously compared with the
contents of the allocated timers.
When a match occurs between the timer value and the value in a capture /compare register,
specific actions will be taken based on the selected compare mode (see Table 11).
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The input frequencies fTx, for the timer input selector Tx, are determined as a function of the
CPU clocks. The timer input frequencies, resolution and periods which result from the
selected pre-scaler option in TxI when using a 40 MHz or a 32 MHz CPU clock, are listed in
Table 12 and Table 13.
The numbers for the timer periods are based on a reload value of 0000h. Note that some
numbers may be rounded to 3 significant figures.
Table 11. Compare Modes
Compare Modes
Function
Mode 0
Interrupt-only compare mode; several compare interrupts per timer period are possible
Mode 1
Pin toggles on each compare match; several compare events per timer period are possible
Mode 2
Interrupt-only compare mode; only one compare interrupt per timer period is generated
Mode 3
Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer
period is generated
Double Register
Mode
Two registers operate on one pin; pin toggles on each compare match; several compare events
per timer period are possible.
Table 12. CAPCOM Timer Input Frequencies, Resolution and Periods (fCPU = 40 MHz)
fCPU = 25 MHz
Pre-scaler for fCPU
Timer Input Selection TxI
000b
001b
010b
011b
100b
101b
110b
111b
8
16
32
64
128
256
512
1024
Input Frequency
5 MHz
Resolution
200 ns
2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25kHz 78.125kHz
400 ns
0.8 µs
Period
13.1 ms
26.2 ms
52.4 ms
1.6 µs
3.2 µs
104.8 ms 209.7 ms
39.1 kHz
6.4 µs
12.8 µs
25.6 µs
419.4 ms
838.9 ms
1.678 s
Table 13. CAPCOM Timer Input Frequencies, Resolution and Periods (fCPU = 32MHz)
fCPU = 32 MHz
Pre-scaler for fCPU
Timer Input Selection TxI
000b
001b
010b
011b
100b
101b
110b
111b
8
16
32
64
128
256
512
1024
Input Frequency
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
Resolution
250 ns
500 ns
1 μs
2 μs
4 μs
8 μs
16 μs
32 μs
Period
16.4 ms
32.8 ms
65.5 ms
131 ms
262.1 ms
524.3 ms
1.05 s
2.1 s
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10
General Purpose Timer Unit
General Purpose Timer Unit
The GPT unit is a flexible multifunctional timer/counter structure which is used for time
related tasks such as event timing and counting, pulse width and duty cycle measurements,
pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized
into two separate modules GPT1 and GPT2. Each timer in each module may operate
independently in several different modes, or may be concatenated with another timer of the
same module.
10.1
GPT1
Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for
one of four basic modes of operation: timer, gated timer, counter mode and incremental
interface mode.
In timer mode, the input clock for a timer is derived from the CPU clock, divided by a
programmable prescaler.
In counter mode, the timer is clocked in reference to external events.
Pulse width or duty cycle measurement is supported in gated timer mode where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input.
Table 14 and Table 15 list the timer input frequencies, resolution and periods for each prescaler option at 40 MHz or 32 MHz CPU clock. This also applies to the Gated Timer Mode of
T3 and to the auxiliary timers T2 and T4 in Timer and Gated Timer Mode. The count
direction (up/down) for each timer is programmable by software or may be altered
dynamically by an external signal on a port pin (TxEUD).
In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to
the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD.
Direction and count signals are internally derived from these two input signals so that the
contents of the respective timer Tx corresponds to the sensor position. The third position
sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has output toggle latches (TxOTL) which changes state on each timer over flow /
underflow. The state of this latch may be output on port pins (TxOUT) for time out monitoring
of external hardware components, or may be used internally to clock timers T2 and T4 for
high resolution of long duration measurements.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or
capture registers for timer T3. When used as capture or reload registers, timers T2 and T4
are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at
their associated input pins (TxIN).
Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or
by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are
configured to alternately reload T3 on opposite state transitions of T3OTL with the low and
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high times of a PWM signal, this signal can be constantly generated without software
intervention.
Table 14. GPT1 Timer Input Frequencies, Resolution and Periods (fCPU = 40 MHz)
Timer Input Selection T2I / T3I / T4I
fCPU = 40 MHz
000b
Pre-scaler factor
001b
010b
011b
100b
101b
110b
128
256
512
111b
8
16
32
64
Input Freq
5 MHz
2.5 MHz
1.25 MHz
625 kHz
1024
Resolution
200 ns
400 ns
0.8 µs
1.6 µs
3.2 µs
6.4 µs
12.8 µs
25.6 µs
Period maximum
13.1 ms
26.2 ms
52.4 ms
104.8 ms
209.7 ms
419.4 ms
838.9 ms
1.678 s
312.5kHz 156.25 kHz 78.125kHz
39.1 kHz
Table 15. PT1 Timer Input Frequencies, Resolution and Periods (fCPU = 32 MHz)
Timer Input Selection T2I / T3I / T4I
fCPU = 32 MHz
Pre-scaler factor
Input Freq
000b
001b
010b
011b
100b
101b
110b
111b
8
16
32
64
128
256
512
1024
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5KHz 31.125KHz
Resolution
250 ns
500 ns
1 μs
2 μs
4 μs
8 μs
16 μs
32 μs
Period maximum
16.4 ms
32.8 ms
65.5 ms
131 ms
262.1 ms
524.3 ms
1.05 s
2.1 s
Figure 14. Block Diagram of GPT1
U/D
T2EUD
CPU Clock
Interrupt
Request
GPT1 Timer T2
2n
n=3...10
T2IN
T
2
Reload
M
Capture
CPU Clock
2n n=3...10
T3IN
T
3
GPT1 Timer T3
M
T3OUT
T3OTL
U/D
T3EUD
Capture
T
Reload
CPU Clock
2n n=3...10
GPT1 Timer T4
U/D
T4EUD
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M
T4IN
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Interrupt
Request
ST10F269Z1-ST10F269Z2
10.2
General Purpose Timer Unit
GPT2
The GPT2 module provides precise event control and time measurement. It includes two
timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an
input clock which is derived from the CPU clock via a programmable prescaler or with
external signals. The count direction (up/down) for each timer is programmable by software
or may additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, or it may be output on a port pin
(T6OUT). The overflow / underflow of timer T6 can additionally be used to clock the
CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL
register may capture the contents of timer T5 based on an external signal transition on the
corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture
procedure. This allows absolute time differences to be measured or pulse multiplication to
be performed without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1
timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental
Interface Mode.
Table 16 and Table 17 list the timer input frequencies, resolution and periods for each prescaler option at 40 MHz or 32 MHz CPU clock.
This also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in Timer and
Gated Timer Mode.
Table 16. GPT2 Timer Input Frequencies, Resolution and Period (fCPU = 40 MHz)
fCPU = 40MHz
Pre-scaler factor
Input Freq
Resolution
Period maximum
Timer Input Selection T5I / T6I
000b
001b
010b
011b
100b
4
10MHz
100ns
6.55ms
8
5MHz
200ns
13.1ms
16
2.5MHz
400ns
26.2ms
32
1.25MHz
0.8µs
52.4ms
64
625kHz
1.6µs
104.8ms
101b
110b
111b
128
256
512
312.5kHz 156.25kHz 78.125kHz
3.2µs
6.4µs
12.8µs
209.7ms
419.4ms
838.9ms
Table 17. GPT2 Timer Input Frequencies, Resolution and Period (fCPU = 32 MHz)
fCPU = 32MHz
Pre-scaler factor
Input Freq
Resolution
Period maximum
Timer Input Selection T5I / T6I
000b
001b
010b
011b
100b
101b
110b
111b
4
8MHz
125ns
8.19ms
8
4MHz
250ns
16.4ms
16
2MHz
500ns
32.8ms
32
1MHz
1μs
65.5ms
64
500KHz
2μs
131ms
128
250KHz
4μs
262.1ms
256
125KHz
8μs
524.3ms
512
62.5KHz
16μs
1.05s
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ST10F269Z1-ST10F269Z2
Figure 15. Block Diagram of GPT2
T5EUD
U/D
CPU Clock
n
2 n=2...9
T5IN
Clear
T
5
GPT2
M
o
Interrupt
Request
Timer T5
Capture
Interrupt
Request
CAPIN
GPT2 CAPREL
Reload
T6IN
CPU Clock
2n n=2...9
T
6
GPT2
M
o
Toggle FF
Timer T6
U/D
T6EUD
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Interrupt
Request
DocID13266 Rev 2
T60TL
T6OUT
to CAPCOM
Timers
ST10F269Z1-ST10F269Z2
11
PWM Module
PWM Module
The pulse width modulation module can generate up to four PWM output signals using
edge-aligned or center-aligned PWM. In addition, the PWM module can generate PWM
burst signals and single shot outputs. Table 18 and Table 19 show the PWM frequencies for
different resolutions. The level of the output signals is selectable and the PWM module can
generate interrupt requests.
Figure 16. Block Diagram of PWM Modules
PPx Period Register *
Match
Comparator
Clock 1
Clock 2
Input
Control
Run
*
PTx
16-bit Up/Down Counter
Comparator
Up/Down/
Clear Control
Match
POUTx
Output Control
Enable
Shadow Register
* User readable / writeable register
Write Control
PWx Pulse Width Register *
Table 18. PWM Unit Frequencies and Resolution at 40 MHz CPU Clock
Mode 0
Resolution
8-bit
10-bit
12-bit
14-bit
16-bit
CPU Clock/1
25ns
156.25kHz
39.1kHz
9.77kHz
2.44Hz
610Hz
CPU Clock/64
1.6μs
2.44Hz
610Hz
152.6Hz
38.15Hz
9.54Hz
Mode 1
Resolution
8-bit
10-bit
12-bit
14-bit
16-bit
CPU Clock/1
25ns
78.12kHz
19.53kHz
4.88kHz
1.22kHz
305.17Hz
CPU Clock/64
1.6μs
1.22kHz
305.17Hz
76.29Hz
19.07Hz
4.77Hz
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ST10F269Z1-ST10F269Z2
Table 19. PWM Unit Frequencies and Resolution at 32 MHz CPU Clock
Mode 0
Resolution
8-bit
10-bit
12-bit
14-bit
16-bit
CPU Clock/1
31.25ns
125KHz
31.25KHz
7.81KHz
1.953KHz
976.6Hz
CPU Clock/64
2.00μs
1.953KHz
488.3Hz
122.1Hz
30.52Hz
7.63Hz
Mode 1
Resolution
8-bit
10-bit
12-bit
14-bit
16-bit
CPU Clock/1
31.25ns
62.5KHz
15.62KHz
3.90KHz
976.6Hz
244.1Hz
CPU Clock/64
2.00μs
976.6Hz
244.1Hz
61Hz
15.26Hz
3.81Hz
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12
Parallel Ports
12.1
Introduction
Parallel Ports
The ST10F269 MCU provides up to 111 I/O lines with programmable features. These
capabilities bring very flexible adaptation of this MCU to wide range of applications.
ST10F269 has 9 groups of I/O lines gathered as following:
•
Port 0 is a 2 time 8-bit port named P0L (Low as less significant byte) and P0H (high as
most significant byte)
•
Port 1 is a 2 time 8-bit port named P1L and P1H
•
Port 2 is a 16-bit port
•
Port 3 is a 15-bit port (P3.14 line is not implemented)
•
Port 4 is a 8-bit port
•
Port 5 is a 16-bit port input only
•
Port 6, Port 7 and Port 8 are 8-bit port
These ports may be used as general purpose bidirectional input or output, software
controlled with dedicated registers.
For example the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured (bitwise) for push-pull or open drain operation using ODPx registers.
In addition, the sink and the source capability and the rise / fall time of the transition of the
signal of some of the push-pull buffers can be programmed to fit the driving requirements of
the application and to minimize EMI. This feature is implemented on Port 0, 1, 2, 3, 4, 6, 7
and 8 with the control registers POCONx. The output drivers capabilities of ALE, RD, WR
control lines are programmable with the dedicated bits of POCON20 control register.
The input threshold levels are programmable (TTL/CMOS) for 5 ports (2, 3, 4, 7, 8). The
logic level of a pin is clocked into the input latch once per state time, regardless whether the
port is configured for input or output. The threshold is selected with the PICON register
control bits.
A write operation to a port pin configured as an input causes the value to be written into the
port output latch, while a read operation returns the latched state of the pin itself. A readmodify-write operation reads the value of the pin, modifies it, and writes it back to the output
latch.
Writing to a pin configured as an output (DPx.y=‘1’) causes the output latch and the pin to
have the written value, since the output buffer is enabled. Reading this pin returns the value
of the output latch. A read-modify-write operation reads the value of the output latch,
modifies it, and writes it back to the output latch, thus also modifying the level at the pin.
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- - - - - - - - YYYYYYYY
- - - - - - - - YYYYYYYY
P7
P8
- - - - - - - - YYYYYYYY
- - - - - - - - YYYYYYYY
- - - - - - - - YYYYYYYY
- - - - - - - - YYYYYYYY
Y - Y Y Y Y YYYYYYYYYY
Y : Bit has an I/O function
- : Bit has no I/O dedicated function or is not implemented
E : Register belongs to ESFR area
P2LIN P2HIN
P3LIN P3HIN
P4LIN
P6LIN (to be implemented)
P7LIN
P8LIN
- - - - - - - - YYYYYYYY
P6
PICON:
DP7
Y Y Y Y Y Y YYYYYYYYYY
P5
DP8
DP6
- - - - - - - - YYYYYYYY
P4
DP4
DP3
Y - Y Y Y Y YYYYYYYYYY
P3
Y Y Y Y Y Y YYYYYYYYYY
- - - - - - - - YYYYYYYY
DP1H E
P1H - - - - - - - - Y Y Y Y Y Y Y Y
DP2
- - - - - - - - YYYYYYYY
DP1L E
P1L - - - - - - - - Y Y Y Y Y Y Y Y
Y Y Y Y Y Y YYYYYYYYYY
- - - - - - - - YYYYYYYY
DP0H E
P0H - - - - - - - - Y Y Y Y Y Y Y Y
P2
- - - - - - - - YYYYYYYY
DP0L E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Direction Control Registers
P0L - - - - - - - - Y Y Y Y Y Y Y Y
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data Input / Output Register
ODP8
ODP7
ODP6
P5DIDIS
ODP4
ODP3
ODP2
PICON
- - - - - - - - YYYYYYYY
- - - - - - - - YYYYYYYY
- - - - - - - - YYYYYYYY
E
E
E
Y Y Y Y Y Y YYYYYYYYYY
- - - - - - - - YY - - - - - -
- - Y - Y Y YYYYYYYYYY
E
E
Y Y Y Y Y Y YYYYYYYYYY
- - - - - - - - YY - YYYYY
E
E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Threshold / Open Drain Control
- - - - - - - - YYYYYYYY
- - - - - - - - YYYYYYYY
Y Y Y Y Y Y YYYYYYYYYY
Y - Y Y Y Y YYYYYYYYYY
E
E
E
E
- - - - - - - - YYYYYYYY
- - - - - - - - YYYYYYYY
- - - - - - - - YYYYYYYY
E
E
POCON20 * E
* RD, WR, ALE lines only
POCON8
POCON7
- - - - - - - - YYYYYYYY
- - - - - - - - YYYYYYYY
- - - - - - - - YYYYYYYY
E
E
- - - - - - - - YYYYYYYY
E
E
POCON6
POCON4
POCON3
POCON2
POCON1H
POCON1L
POCON0H
POCON0L
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Output Driver Control Register
Parallel Ports
ST10F269Z1-ST10F269Z2
Figure 17. I/O lines support an alternate function (detailed in the following description
of each port)
ST10F269Z1-ST10F269Z2
Parallel Ports
12.2
I/Os Special Features
12.2.1
Open Drain Mode
Some of the I/O ports of ST10F269 support the open drain capability. This programmable
feature may be used with an external pull-up resistor, in order to get an AND wired logical
function.
This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections),
and is controlled through the respective Open Drain Control Registers ODPx. These
registers allow the individual bit-wise selection of the open drain mode for each port line. If
the respective control bit ODPx.y is ‘0’ (default after reset), the output driver is in the pushpull mode. If ODPx.y is ‘1’, the open drain configuration is selected. Note that all ODPx
registers are located in the ESFR space (See Figure 18).
12.2.2
Input Threshold Control
The standard inputs of the ST10F269 determine the status of input signals according to TTL
levels. In order to accept and recognize noisy signals, CMOS-like input thresholds can be
selected instead of the standard TTL thresholds for all pins of Port 2, Port 3, Port 4, Port 7
and Port 8. These special thresholds are defined above the TTL thresholds and feature a
defined hysteresis to prevent the inputs from toggling while the respective input signal level
is near the thresholds.
The Port Input Control register PICON is used to select these thresholds for each byte of the
indicated ports, this means the 8-bit ports P4, P7 and P8 are controlled by one bit each
while ports P2 and P3 are controlled by two bits each.
All options for individual direction and output mode control are available for each pin,
independent of the selected input threshold. The input hysteresis provides stable inputs
from noisy or slowly changing external signals (See Figure 19).
PICON (F1C4h / E2h)
ESFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
P8LIN P7LIN
RW
RW
5
-
4
3
RW
RW
PxLIN
Port x Low Byte Input Level Selection
PxHIN
0:
Pins Px.7...Px.0 switch on standard TTL input levels
1:
Pins Px.7...Px.0 switch on special threshold input levels
Port x High Byte Input Level Selection
0:
1:
2
1
0
P4LIN P3HIN P3LIN P2HIN P2LIN
RW
RW
RW
Pins Px.15...Px.8 switch on standard TTL input levels
Pins Px.15...Px.8 switch on special threshold input levels
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Figure 18. Output Drivers in Push-pull Mode and in Open Drain Mode
External
Pullup
Pin
Q
Pin
Q
Push-Pull Output Driver
Open Drain Output Driver
Figure 19. Hysteresis for Special Input Thresholds
Hysteresis
Input level
Bit state
12.2.3
Output Driver Control
The port output control registers POCONx allow to select the port output driver
characteristics of a port. The aim of these selections is to adapt the output drivers to the
application’s requirements, and to improve the EMI behavior of the device. Two
characteristics may be selected:
Edge characteristic defines the rise/fall time for the respective output. Slow edges reduce
the peak currents that are sinked/sourced when changing the voltage level of an external
capacitive load. For a bus interface or pins that are changing at frequency higher than
1MHz, however, fast edges may still be required.
Driver characteristic defines either the general driving capability of the respective driver, or
if the driver strength is reduced after the target output level has been reached or not.
Reducing the driver strength increases the output’s internal resistance, which attenuates
noise that is imported via the output line. For driving LEDs or power transistors, however, a
stable high output current may still be required as described below.
This rise / fall time of 4 I/O pads (a nibble) is selected using 2-bit named PNxEC. That
means Port Nibble (x = nibble number, it could be 3 as for Port 2.15 to 2.12) Edge
Characteristic.
The sink / source capability of the same 4 I/O pads is selected using 2-bit named PNxDC.
That means Port Nibble (x = nibble number) Drive Characteristic (See Table 20).
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Parallel Ports
POCONx (F0yyh / zzh) for 8-bit Ports
ESFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
PN1DC
PN1EC
PN0DC
PN0EC
RW
RW
RW
RW
POCONx (F0yyh / zzh) for 16-bit Ports
ESFR Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PN3DC
PN3EC
PN2DC
PN2EC
PN1DC
PN1EC
PN0DC
PN0EC
RW
RW
RW
RW
RW
RW
RW
RW
PNxEC
PNxDC
Port Nibble x Edge Characteristic (rise/fall time)
00: Fast edge mode, rise/fall times depend on the size of the driver.
01: Slow edge mode, rise/fall times ~60 ns
10: Reserved
11:
Reserved
Port Nibble x Driver Characteristic (output current)
00: High Current mode:
Driver always operates with maximum strength.
01: Dynamic Current mode:
Driver strength is reduced after the target level has been reached.
10: Low Current mode:
Driver always operates with reduced strength.
11:
Reserved
Note: In case of reading an 8 bit P0CONX register, high Byte (bit 15..8) is read as 00h
Table 20 lists the defined POCON registers and the allocation of control bit-fields and port
pins.
Table 20. Port Control Register Allocation
Control
Register
POCON0L
POCON0H
POCON1L
POCON1H
POCON2
POCON3
POCON4
POCON6
POCON7
POCON8
Physical
Address
8-bit
Address
F080h
F082h
F084h
F086h
F088h
F08Ah
F08Ch
F08Eh
F090h
F092h
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
Controlled Port Nibble
3
P2.15...12
P3.15, 3.13, 3.12
2
1
0
P2.11...8
P3.11...8
P0L.7...4
P0H.7...4
P1L.7...4
P1H.7...4
P2.7...4
P3.7...4
P4.7...4
P6.7...4
P7.7...4
P8.7...4
P0L.3...0
P0H.3...0
P1L.3...0
P1H.3...0
P2.3...0
P3.3...0
P4.3...0
P6.3...0
P7.3...0
P8.3...0
Dedicated Pins Output Control
Programmable pad drivers also are supported for the dedicated pins ALE, RD and WR. For
these pads, a special POCON20 register is provided.
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POCON20 (F0AAh / 55h)
ESFR Reset Value: --00H
12.2.4
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
PN1DC
PN1EC
PN0DC
PN0EC
RW
RW
RW
RW
PN0EC
RD, WR Edge Characteristic (rise/fall time)
00: Fast edge mode, rise/fall times depend on the size of the driver.
01: Slow edge mode, rise/fall times ~60 ns
10: Reserved
11:
Reserved
PN0DC
RD, WR Driver Characteristic (output current)
00: High Current mode:
Driver always operates with maximum strength.
01: Dynamic Current mode:
Driver strength is reduced after the target level has been reached.
10: Low Current mode:
Driver always operates with reduced strength.
11:
Reserved
PN1EC
ALE Edge Characteristic (rise/fall time)
00: Fast edge mode, rise/fall times depend on the size of the driver.
01: Slow edge mode, rise/fall times ~60 ns
10: Reserved
11:
Reserved
PN1DC
ALE Driver Characteristic (output current)
00: High Current mode:
Driver always operates with maximum strength.
01: Dynamic Current mode:
Driver strength is reduced after the target level has been reached.
10: Low Current mode:
Driver always operates with reduced strength.
11:
Reserved
Alternate Port Functions
Each port line has one associated programmable alternate input or output function.
•
PORT0 and PORT1 may be used as address and data lines when accessing external
memory.
•
Port 2, Port 7 and Port 8 are associated with the capture inputs or compare outputs of
the CAPCOM units and/or with the outputs of the PWM module.
Port 2 is also used for fast external interrupt inputs and for timer 7 input.
•
Port 3 includes the alternate functions of timers, serial interfaces, the optional bus
control signal BHE and the system clock output (CLKOUT).
•
Port 4 outputs the additional segment address bit A16 to A23 in systems where
segmentation is enabled to access more than 64 Kbytes of memory.
•
Port 5 is used as analog input channels of the A/D converter or as timer control signals.
•
Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select
signals.
If an alternate output function of a pin is to be used, the direction of this pin must be
programmed for output (DPx.y=‘1’), except for some signals that are used directly after reset
and are configured automatically. Otherwise the pin remains in the high-impedance state
and is not effected by the alternate output function. The respective port latch should hold a
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‘1’, because its output is ANDed with the alternate output data (except for PWM output
signals).
If an alternate input function of a pin is used, the direction of the pin must be programmed
for input (DPx.y=‘0’) if an external device is driving the pin. The input direction is the default
after reset. If no external device is connected to the pin, however, one can also set the
direction for this pin to output. In this case, the pin reflects the state of the port output latch.
Thus, the alternate input function reads the value stored in the port output latch. This can be
used for testing purposes to allow a software trigger of an alternate input function by writing
to the port output latch.
On most of the port lines, the application software must set the proper direction when using
an alternate input or output function of a pin. This is done by setting or clearing the direction
control bit DPx.y of the pin before enabling the alternate function. There are port lines,
however, where the direction of the port line is switched automatically.
For instance, in the multiplexed external bus modes of PORT0, the direction must be
switched several times for an instruction fetch in order to output the addresses and to input
the data. Obviously, this cannot be done through instructions. In these cases, the direction
of the port line is switched automatically by hardware if the alternate function of such a pin is
enabled.
To determine the appropriate level of the port output latches check how the alternate data
output is combined with the respective port latch output.
There is one basic structure for all port lines supporting only one alternate input function.
Port lines with only one alternate output function, however, have different structures. It has
to be adapted to support the normal and the alternate function features.
All port lines that are not used for these alternate functions may be used as general purpose
I/O lines. When using port pins for general purpose output, the initial output value should be
written to the port latch prior to enabling the output drivers, in order to avoid undesired
transitions on the output pins. This applies to single pins as well as to pin groups (see
examples below).
SINGLE_BIT:BSETP4.7; Initial output level is "high"
BSETDP4.7; Switch on the output driver
BIT_GROUP:BFLDHP4, #24H, #24H; Initial output level is "high"
BFLDHDP4, #24H, #24H; Switch on the output drivers
Note:
When using several BSET pairs to control more pins of one port, these pairs must be
separated by instructions, which do not apply to the respective port (See Section 6: Central
Processing Unit (CPU).
12.3
PORT0
The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0,
respectively. Both halves of PORT0 can be written (via a PEC transfer) without effecting the
other half.
If this port is used for general purpose I/O, the direction of each line can be configured via
the corresponding direction registers DP0H and DP0L.
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P0L (FF00h / 80h)
SFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
P0L.7 P0L.6
5
4
3
2
1
0
P0L.5
P0L.4
P0L.3
RW
RW
RW
RW
RW
P0L.2 P0L.1
RW
RW
P0L.0
RW
7
6
5
4
3
2
1
0
P0H (FF02h / 81h)
SFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0
RW
P0X.y
RW
RW
RW
RW
RW
RW
RW
Port Data Register P0H or P0L Bit y
DP0L (F100h / 80h)
ESFR Reset Value: --00H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
DP0L.7
DP0L.6
DP0L.5
DP0L.4
DP0L.3
DP0L.2
DP0L.1
DP0L.0
RW
RW
RW
RW
RW
RW
RW
RW
DP0H (F102h / 81h)
ESFR Reset Value: --00H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
DP0H.7
DP0H.6
DP0H.5
DP0H.4
DP0H.3
DP0H.2
DP0H.1
DP0H.0
RW
RW
RW
RW
RW
RW
RW
RW
DP0X.y
12.3.1
Port Direction Register DP0H or DP0L Bit y
DP0X.y = 0: Port line P0X.y is an input (high-impedance)
DP0X.y = 1: Port line P0X.y is an output
Alternate Functions of PORT0
When an external bus is enabled, PORT0 is used as data bus or address/data bus.
Note that an external 8-bit demultiplexed bus only uses P0L, while P0H is free for I/O
(provided that no other bus mode is enabled).
PORT0 is also used to select the system start-up configuration. During reset, PORT0 is
configured to input, and each line is held high through an internal pull-up device.
Each line can now be individually pulled to a low level (see Section 21.3: DC
Characteristics) through an external pull-down device. A default configuration is selected
when the respective PORT0 lines are at a high level. Through pulling individual lines to a
low level, this default can be changed according to the needs of the applications.
The internal pull-up devices are designed in such way that an external pull-down resistors
(see Data Sheet specification) can be used to apply a correct low level.
These external pull-down resistors can remain connected to the PORT0 pins also during
normal operation, however, care has to be taken in order to not disturb the normal function
of PORT0 (this might be the case, for example, if the external resistor value is too low).
With the end of reset, the selected bus configuration will be written to the BUSCON0
register.
78/206
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Parallel Ports
The configuration of the high byte of PORT0, will be copied into the special register RP0H.
This read-only register holds the selection for the number of chip selects and segment
addresses. Software can read this register in order to react according to the selected
configuration, if required.
When the reset is terminated, the internal pull-up devices are switched off, and PORT0 will
be switched to the appropriate operating mode.
During external accesses in multiplexed bus modes PORT0 first outputs the 16-bit intrasegment address as an alternate output function. PORT0 is then switched to highimpedance input mode to read the incoming instruction or data. In 8-bit data bus mode, two
memory cycles are required for word accesses, the first for the low Byte and the second for
the high Byte of the Word.
During write cycles PORT0 outputs the data Byte or Word after outputting the address.
During external accesses in demultiplexed bus modes PORT0 reads the incoming
instruction or data Word or outputs the data Byte or Word.
Figure 20. PORT0 I/O and Alternate Functions
Alternate Function
P0H
PORT0
P0L
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0H.0
P0L.7
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
P0L.0
General Purpose
Input/Output
a)
b)
c)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D7
D6
D5
D4
D3
D2
D1
D0
8-bit
Demultiplexed Bus
16-bit
Demultiplexed Bus
d)
A15
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
8-bit
Multiplexed Bus
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
16-bit
Multiplexed Bus
When an external bus mode is enabled, the direction of the port pin and the loading of data
into the port output latch are controlled by the bus controller hardware.
The input of the port output Buffer is disconnected from the internal bus and is switched to
the line labeled “Alternate Data Output” via a multiplexer.
The alternate data can be the 16-bit intra-segment address or the 8/16-bit data information.
The incoming data on PORT0 is read on the line “Alternate Data Input”. While an external
bus mode is enabled, the user software should not write to the port output latch, otherwise
unpredictable results may occur.
When the external bus modes are disabled, the contents of the direction register last written
by the user becomes active.
Figure 21 shows the structure of a PORT0 pin.
DocID13266 Rev 2
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Parallel Ports
ST10F269Z1-ST10F269Z2
Figure 21. Block Diagram of a PORT0 pin
Write DP0H.y / DP0L.y
Alternate
Direction
1
MUX
Direction
Latch
0
Read DP0H.y / DP0L.y
Alternate
Function
Enable
Internal Bus
Alternate
Data
Output
Write P0H.y / P0L.y
1
Port Data
Output
Port Output
Latch
MUX
P0H.y
P0L.y
Output
Buffer
0
Read P0H.y / P0L.y
Clock
1
MUX
Input
Latch
0
12.4
y = 7...0
PORT1
The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1,
respectively. Both halves of PORT1 can be written (via a PEC transfer) without effecting the
other half.
If this port is used for general purpose I/O, the direction of each line can be configured via
the corresponding direction registers DP1H and DP1L.
P1L (FF04h / 82h)
SFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
P1L.7 P1L.6
5
4
3
P1L.5
P1L4
P1L.3
2
1
P1L.2 P1L.1
0
P1L.0
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
P1H (FF06h / 83h)
SFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
P1H.7 P1H.6 P1H.5 P1H.4 P1H.3 P1H.2 P1H.1 P1H.0
RW
P1X.y
80/206
Port Data Register P1H or P1L Bit y
DocID13266 Rev 2
RW
RW
RW
RW
RW
RW
RW
ST10F269Z1-ST10F269Z2
Parallel Ports
DP1L (F104h / 82h)
ESFR Reset Value: --00H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
DP1L.7
DP1L.6
DP1L.5
DP1L.4
DP1L.3
DP1L.2
DP1L.1
DP1L.0
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
DP1H (F106h / 83h)
ESFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
DP1H.7 DP1H.6 DP1H.5 DP1H.4 DP1H.3 DP1H.2 DP1H.1 DP1H.0
RW
DP1X.y
12.4.1
RW
RW
RW
RW
RW
RW
RW
Port Direction Register DP1H or DP1L Bit y
DP1X.y = 0: Port line P1X.y is an input (high-impedance)
DP1X.y = 1: Port line P1X.y is an output
Alternate Functions of PORT1
When a demultiplexed external bus is enabled, PORT1 is used as address bus.
Note: Demultiplexed bus modes use PORT1 as a 16-bit port. Otherwise all 16 port lines can
be used for general purpose I/O.
The upper 4 pins of PORT1 (P1H.7...P1H.4) are used as capture input lines
(CC27IO...CC24IO).
During external accesses in demultiplexed bus modes PORT1 outputs the 16-bit intrasegment address as an alternate output function.
During external accesses in multiplexed bus modes, when no BUSCON register selects a
demultiplexed bus mode, PORT1 is not used and is available for general purpose I/O.
Figure 22. PORT1 I/O and Alternate Functions
Alternate Function
P1H
PORT1
P1L
P1H.7
P1H.6
P1H.5
P1H.4
P1H.3
P1H.2
P1H.1
P1H.0
P1L.7
P1L.6
P1L.5
P1L.4
P1L.3
P1L.2
General Purpose Input/Output
a)
b)
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
8/16-bit Demultiplexed Bus
DocID13266 Rev 2
CC27IO
CC26IO
CC25IO
CC24IO
CAPCOM2 Capture Inputs only
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Parallel Ports
ST10F269Z1-ST10F269Z2
When an external bus mode is enabled, the direction of the port pin and the loading of data
into the port output latch are controlled by the bus controller hardware.
The input of the port Buffer latch is disconnected from the internal bus and is switched to the
line labeled “Alternate Data Output” via a multiplexer. The alternate data is the 16-bit intrasegment address. While an external bus mode is enabled, the user software should not
write to the port output latch, otherwise unpredictable results may occur. When the external
bus modes are disabled, the contents of the direction register last written by the user
becomes active.
Figure 23 shows the structure of a PORT1 pin.
Figure 23. Block Diagram of a PORT1 pin
Write DP1H.y / DP1L.y
1
“1”
MUX
Direction
Latch
0
Read DP1H.y / DP1L.y
Alternate
Function
Enable
Internal Bus
Alternate
Data
Output
Write P1H.y / P1L.y
1
Port Data
Output
Port Output
Latch
MUX
P1H.y
P1L.y
Output
Buffer
0
Read P1H.y / P1L.y
Clock
1
MUX
Input
Latch
0
12.5
y = 7...0
Port 2
If this 16-bit port is used for general purpose I/O, the direction of each line can be configured
via the corresponding direction register DP2. Each port line can be switched into push/pull
or open drain mode via the open drain control register ODP2.
P2 (FFC0h / E0h)
SFR Reset Value: 0000H
82/206
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P2.15
P2.14
P2.13
P2.12
P2.11
P2.10
P2.9
P2.8
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
P2.y
Parallel Ports
Port Data Register P2 Bit y
DP2 (FFC2h / E1h)
SFR Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DP2.15 DP2.14 DP2.13 DP2.12 DP2.11 DP2.10 DP2.9 DP2.8 DP2.7 DP2.6 DP2.5 DP2.4 DP2.3 DP2.2 DP2.1 DP2.0
RW
RW
RW
DP2.y
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
4
3
2
1
0
Port Direction Register DP2 Bit y
DP2.y = 0: Port line P2.y is an input (high-impedance)
DP2.y = 1: Port line P2.y is an output
ODP2 (F1C2h / E1h)
ESFR Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2
.15
.14
.13
.12
.11
.10
.9
.8
.7
.6
.5
.4
.3
.2
.1
.0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
ODP2.y
12.5.1
Port 2 Open Drain Control Register Bit y
ODP2.y = 0: Port line P2.y output driver in push/pull mode
ODP2.y = 1: Port line P2.y output driver in open drain mode
Alternate Functions of Port 2
All Port 2 lines (P2.15...P2.0) serve as capture inputs or compare outputs
(CC15IO...CC0IO) for the CAPCOM1 unit.
When a Port 2 line is used as a capture input, the state of the input latch, which represents
the state of the port pin, is directed to the CAPCOM unit via the line “Alternate Pin Data
Input”. If an external capture trigger signal is used, the direction of the respective pin must
be set to input.
If the direction is set to output, the state of the port output latch will be read since the pin
represents the state of the output latch.
This can be used to trigger a capture event through software by setting or clearing the port
latch. Note that in the output configuration, no external device may drive the pin, otherwise
conflicts would occur.
When a Port 2 line is used as a compare output (compare modes 1 and 3), the compare
event (or the timer overflow in compare mode 3) directly effects the port output latch. In
compare mode 1, when a valid compare match occurs, the state of the port output latch is
read by the CAPCOM control hardware via the line “Alternate Latch Data Input”, inverted,
and written back to the latch via the line “Alternate Data Output”.
The port output latch is clocked by the signal “Compare Trigger” which is generated by the
CAPCOM unit. In compare mode 3, when a match occurs, the value '1' is written to the port
output latch via the line “Alternate Data Output”. When an overflow of the corresponding
timer occurs, a '0' is written to the port output latch. In both cases, the output latch is clocked
by the signal “Compare Trigger”.
The direction of the pin should be set to output by the user, otherwise the pin will be in the
high-impedance state and will not reflect the state of the output latch.
DocID13266 Rev 2
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Parallel Ports
ST10F269Z1-ST10F269Z2
As can be seen from the port structure in Figure 25, the user software always has free
access to the port pin even when it is used as a compare output. This is useful for setting up
the initial level of the pin when using compare mode 1 or the double-register mode. In these
modes, unlike in compare mode 3, the pin is not set to a specific value when a compare
match occurs, but is toggled instead.
When the user wants to write to the port pin at the same time a compare trigger tries to clock
the output latch, the write operation of the user software has priority. Each time a CPU write
access to the port output latch occurs, the input multiplexer of the port output latch is
switched to the line connected to the internal bus. The port output latch will receive the value
from the internal bus and the hardware triggered change will be lost.
As all other capture inputs, the capture input function of pins P2.15...P2.0 can also be used
as external interrupt inputs (200 ns sample rate at 40 MHz CPU clock and 250 ns sample
rate at 32 MHz CPU clock).
The upper eight Port 2 lines (P2.15...P2.8) also can serve as Fast External Interrupt inputs
from EX0IN to EX7IN (Fast external interrupt sampling rate is 25 ns at 40 MHz CPU clock
and 31.25 ns at 32 MHz CPU clock).
P2.15 in addition serves as input for CAPCOM2 timer T7 (T7IN). Table 21 summarizes the
alternate functions of Port 2.
Table 21. Alternate Functions of Port 2
Port 2 Pin
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
84/206
Alternate
Function a)
CC0IO
CC1IO
CC2IO
CC3IO
CC4IO
CC5IO
CC6IO
CC7IO
CC8IO
CC9IO
CC10IO
CC11IO
CC12IO
CC13IO
CC14IO
CC15IO
Alternate Function b)
EX0IN
EX1IN
EX2IN
EX3IN
EX4IN
EX5IN
EX6IN
EX7IN
Fast External Interrupt 0 Input
Fast External Interrupt 1 Input
Fast External Interrupt 2 Input
Fast External Interrupt 3 Input
Fast External Interrupt 4 Input
Fast External Interrupt 5 Input
Fast External Interrupt 6 Input
Fast External Interrupt 7 Input
DocID13266 Rev 2
Alternate Function c)
T7IN T7 External Count Input
ST10F269Z1-ST10F269Z2
Parallel Ports
Figure 24. PORT2 I/O and Alternate Functions
Alternate Function
Port 2
P2.15
P2.14
P2.13
P2.12
P2.11
P2.10
P2.9
P2.8
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
General Purpose
Input / Output
a)
b)
CC15IO
CC14IO
CC13IO
CC12IO
CC11IO
CC10IO
CC9IO
CC8IO
CC7IO
CC6IO
CC5IO
CC4IO
CC3IO
CC2IO
CAPCOM1
Capture Input / Compare Output
c)
EX7IN
EX6IN
EX5IN
EX4IN
EX3IN
EX2IN
EX1IN
Fast External
Interrupt Input
DocID13266 Rev 2
T7IN
CAPCOM2
Timer T7 Input
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Parallel Ports
ST10F269Z1-ST10F269Z2
The pins of Port 2 combine internal bus data with alternate data output before the port latch
input.
Figure 25. Block Diagram of a PORT2 pin
Write ODP2.y
Open Drain
Latch
Read ODP2.y
Write DP2.y
Direction
Latch
Internal Bus
Read DP2.y
1
Alternate
Data
Output
Output
Latch
MUX
Output
Buffer
0
Write Port P2.y
P2.y
CCyIO
EXxIN
≥1
Compare Trigger
Read P2.y
Clock
1
MUX
0
Alternate Data Input
Fast External Interrupt Input
12.6
Input
Latch
x = 7...0
y = 15...0
Port 3
If this 15-bit port is used for general purpose I/O, the direction of each line can be configured
by the corresponding direction register DP3. Most port lines can be switched into push-pull
86/206
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Parallel Ports
or open drain mode by the open drain control register ODP2 (pins P3.15, P3.14 and P3.12
do not support open drain mode).
Due to pin limitations register bit P3.14 is not connected to an output pin.
P3 (FFC4h / E2h)
SFR Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P3.15
-
P3.13
P3.12
P3.11
P3.10
P3.9
P3.8
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
P3.y
Port Data Register P3 Bit y
DP3 (FFC6h / E3h)
SFR Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DP3
-
DP3
DP3
DP3
DP3
DP3
DP3
DP3
DP3
DP3
DP3
DP3
DP3
DP3
DP3
.13
.12
.11
.10
.9
.8
.7
.6
.5
.4
.3
.2
.1
.0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
4
3
2
1
0
.15
RW
DP3.y
Port Direction Register DP3 Bit y
DP3.y = 0: Port line P3.y is an input (high-impedance)
DP3.y = 1: Port line P3.y is an output
ODP3 (F1C6h / E3h)
ESFR Reset Value: 0000H
15
14
13
12
-
-
ODP3
-
RW
RW
RW
.13
ODP3.y
RW
11
10
9
8
7
6
5
ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3
.11
.10
.9
.8
.7
.6
.5
.4
.3
.2
.1
.0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Port 3 Open Drain Control Register Bit y
ODP3.y = 0: Port line P3.y output driver in push-pull mode
ODP3.y = 1: Port line P3.y output driver in open drain mode
DocID13266 Rev 2
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Parallel Ports
12.6.1
ST10F269Z1-ST10F269Z2
Alternate Functions of Port 3
The pins of Port 3 serve for various functions which include external timer control lines, the
two serial interfaces and the control lines BHE/WRH and CLKOUT.
Table 22. Port 3 Alternative Functions
Port 3 Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.14
P3.15
Alternate Function
T0INCAPCOM1 Timer 0 Count Input
T6OUTTimer 6 Toggle Output
CAPINGPT2 Capture Input
T3OUTTimer 3 Toggle Output
T3EUDTimer 3 External Up/Down Input
T4INTimer 4 Count Input
T3INTimer 3 Count Input
T2INTimer 2 Count Input
MRSTSSC Master Receive / Slave Transmit
MTSRSSC Master Transmit / Slave Receive
TxD0ASC0 Transmit Data Output
RxD0ASC0 Receive Data Input (Output in synchronous mode)
BHE/WRHByte High Enable / Write High Output
SCLKSSC Shift Clock Input/Output
---No pin assigned
CLKOUTSystem Clock Output
Figure 26. PORT3 I/O and Alternate Functions
Alternate Function
No Pin
Port 3
a)
b)
P3.15
CLKOUT
P3.13
P3.12
P3.11
P3.10
P3.9
P3.8
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
SCLK
BHE
RxD0
TxD0
MTSR
MRST
T2IN
T3IN
T4IN
T3EUD
T3OUT
CAPIN
T6OUT
WRH
General Purpose Input/Output
The structure of the Port 3 pins depends on their alternate function (see Figure 27 and
Figure 28). When the on-chip peripheral associated with a Port 3 pin is configured to use the
alternate input function, it reads the input latch, which represents the state of the pin, via the
line labeled “Alternate Data Input”. Port 3 pins with alternate input functions are: T0IN, T2IN,
T3IN, T4IN, T3EUD and CAPIN.
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ST10F269Z1-ST10F269Z2
Parallel Ports
When the on-chip peripheral associated with a Port 3 pin is configured to use the alternate
output function, its “Alternate Data Output” line is ANDed with the port output latch line.
When using these alternate functions, the user must set the direction of the port line to
output (DP3.y=1) and must set the port output latch (P3.y=1). Otherwise the pin is in its
high-impedance state (when configured as input) or the pin is stuck at '0' (when the port
output latch is cleared). When the alternate output functions are not used, the “Alternate
Data Output” line is in its inactive state, which is a high level ('1').
Port 3 pins with alternate output functions are: T6OUT, T3OUT, TxD0, BHE and CLKOUT.
When the on-chip peripheral associated with a Port 3 pin is configured to use both the
alternate input and output function, the descriptions above apply to the respective current
operating mode. The direction must be set accordingly. Port 3 pins with alternate
input/output functions are: MTSR, MRST, RxD0 and SCLK.
Note:
Enabling the CLKOUT function automatically enables the P3.15 output driver. Setting bit
DP3.15=’1’ is not required.
DocID13266 Rev 2
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Parallel Ports
ST10F269Z1-ST10F269Z2
Figure 27. Block Diagram of Port 3 Pin with Alternate Input or Alternate Output Function
Write ODP3.y
Open Drain
Latch
Internal Bus
Read ODP3.y
Write DP3.y
Direction
Latch
Read DP3.y
Alternate
Data Output
Write DP3.y
Port Output
Latch
Port Data
Output
&
Output
Buffer
P3.y
Read P3.y
Clock
1
MUX
0
Alternate
Data
Input
Input
Latch
y = 13, 11...0
Pin P3.12 (BHE/WRH) is another pin with an alternate output function, however, its structure
is slightly different.
After reset the BHE or WRH function must be used depending on the system start-up
configuration. In either of these cases, there is no possibility to program any port latches
before. Thus, the appropriate alternate function is selected automatically. If BHE/WRH is not
used in the system, this pin can be used for general purpose I/O by disabling the alternate
function (BYTDIS = ‘1’ / WRCFG=’0’).
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DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Parallel Ports
Figure 28. Block Diagram of Pins P3.15 (CLKOUT) and P3.12 (BHE/WRH)
Write DP3.x
1
“1”
MUX
Direction
Latch
0
Read DP3.x
Internal Bus
Alternate
Function
Enable
Write P3.x
Alternate
Data
Output
Port Output
Latch
1
MUX
P3.12/BHE
P3.15/CLKOUT
Output
Buffer
0
Read P3.x
Clock
1
MUX
Input
Latch
0
x = 15, 12
Note:
Enabling the BHE or WRH function automatically enables the P3.12 output driver. Setting bit
DP3.12=’1’ is not required.
During bus hold pin P3.12 is switched back to its standard function and is then controlled by
DP3.12 and P3.12. Keep DP3.12 = ’0’ in this case to ensure floating in hold mode.
12.7
Port 4
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured
via the corresponding direction register DP4.
P4 (FFC8h / E4h)
SFR Reset Value: --00H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
RW
RW
RW
RW
RW
RW
RW
RW
P4.y
Port Data Register P4 Bit y
DocID13266 Rev 2
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Parallel Ports
ST10F269Z1-ST10F269Z2
DP4 (FFCAh / E5h)
SFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
5
4
3
2
1
0
DP4.7 DP4.6 DP4.5 DP4.4 DP4.3 DP4.2 DP4.1 DP4.0
RW
DP4.y
6
RW
RW
RW
RW
RW
RW
RW
Port Direction Register DP4 Bit y
DP4.y = 0: Port line P4.y is an input (high-impedance)
DP4.y = 1: Port line P4.y is an output
For CAN configuration support (see section 15), Port 4 has an open drain function,
controlled with the ODP4 register:
ODP4 (F1CAh / E5h)
ESFR Reset Value: --00H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
ODP4.7
ODP4.6
-
-
-
-
-
-
RW
RW
ODP4.y
Port 4 Open Drain Control Register Bit y
ODP4.y = 0: Port line P4.y output driver in push/pull mode
ODP4.y = 1: Port line P4.y output driver in open drain mode if P4.y is not a segment
address line output
Note:
Only bit 6 and 7 are implemented, all other bit will be read as “0”.
12.7.1
Alternate Functions of Port 4
During external bus cycles that use segmentation (address space above 64K Bytes) a
number of Port 4 pins may output the segment address lines. The number of pins that is
used for segment address output determines the external address space which is directly
accessible. The other pins of Port 4 may be used for general purpose I/O. If segment
address lines are selected, the alternate function of Port 4 may be necessary to access
external memory directly after reset. For this reason Port 4 will be switched to this alternate
function automatically.
The number of segment address lines is selected via PORT0 during reset. The selected
value can be read from bitfield SALSEL in register RP0H (read only) in order to check the
configuration during run time.
The CAN interfaces use 2 or 4 pins of Port 4 to interface each CAN Modules to an external
CAN transceiver. In this case the number of possible segment address lines is reduced.
92/206
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Parallel Ports
Table 23 summarizes the alternate functions of Port 4 depending on the number of selected
segment address lines (coded via bitfield SALSEL)
Table 23. Port 4 Alternate Functions
Standard Function
SALSEL = 01
64 Kbytes
Port 4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
GPIO
GPIO
GPIO
GPIO
GPIO/CAN2_RxD
GPIO/CAN1_RxD
GPIO/CAN1_TxD
GPIO/CAN2_TxD
Alternate Function
SALSEL = 11
256 Kbytes
Segment Address A16
Segment Address A17
GPIO
GPIO
GPIO/CAN2_RxD
GPIO/CAN1_RxD
GPIO/CAN1_TxD
GPIO/CAN2_TxD
Alternate Function
SALSEL = 00
1 Mbyte
Alternate Function
SALSEL = 10
16 Mbytes
Segment. Address A16
Segment Address A17
Segment Address A18
Segment Address A19
GPIO/CAN2_RxD
GPIO/CAN1_RxD
GPIO/CAN1_TxD
GPIO/CAN2_TxD
Segment Address A16
Segment Address A17
Segment Address A18
Segment Address A19
Segment Address A20
Segment Address A21
Segment Address A22
Segment Address A23
Figure 29. PORT4 I/O and Alternate Functions
Alternate Function
Port 4
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
General Purpose
Input / Output
b)
a)
A23
A22
A21
A20
A19
A18
A17
A16
Segment Address
Lines
DocID13266 Rev 2
CAN2_TxD
CAN1_TxD
CAN1_RxD
CAN2_RxD
Cans I/O and General Purpose
Input / Output
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Parallel Ports
ST10F269Z1-ST10F269Z2
Figure 30. Block Diagram of a Port 4 Pin
Write DP4.y
“1”
1
MUX
Direction
Latch
0
Read DP4.y
Internal Bus
Alternate
Function
Enable
Write P4.y
Alternate
Data
Output
Port Output
Latch
1
P4.y
MUX
Output
Buffer
0
Read P4.y
Clock
1
MUX
Input
Latch
0
94/206
DocID13266 Rev 2
y = 7...0
ST10F269Z1-ST10F269Z2
Parallel Ports
Figure 31. Block Diagram of P4.4 and P4.5 Pins
Write DP4.x
“1”
1
“0”
MUX
Direction
Latch
1
MUX
0
0
Internal Bus
Read DP4.x
“0”
1
Alternate
Function
Enable
0
Write P4.x
MUX
Alternate
Data
Output
Port Output
Latch
1
P4.x
MUX
0
Output
Buffer
Read P4.x
Clock
1
MUX
Input
Latch
0
CANy.RxD
&
XPERCON.a
(CANyEN)
XPERCON.b
(CANzEN)
x = 5, 4
y = 1, 2 (CAN Channel)
z = 2, 1
a = 0, 1
b = 1, 0
≤1
DocID13266 Rev 2
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Parallel Ports
ST10F269Z1-ST10F269Z2
Figure 32. Block Diagram of P4.6 and P4.7 Pins
Write ODP4.x
Open Drain
Latch
1
MUX
Read ODP4.x
"0"
0
Write DP4.x
1
"1"
1
"1"
MUX
MUX
Internal Bus
Direction
Latch
0
0
Read DP4.x
1
"0"
Write P4.x
MUX
Alternate
Function
Enable
0
Alternate
Data
Output
1
1
MUX
Port Output
Latch
MUX
0
0
Output
Buffer
Read P4.x
P4.x
Clock
1
MUX
Input
Latch
0
CANy.TxD
Data output
XPERCON.a
(CANyEN)
≤1
XPERCON.b
(CANzEN)
12.8
x = 6, 7
y = 1, 2 (CAN Channel)
z = 2, 1
a = 0, 1
b = 1, 0
Port 5
This 16-bit input port can only read data. There is no output latch and no direction register.
Data written to P5 will be lost.
P5 (FFA2h / D1h)
SFR Reset Value: XXXXH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P5.15
P5.14
P5.13
P5.12
P5.11
P5.10
P5.9
P5.8
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
P5.y
96/206
Port Data Register P5 Bit y (Read only)
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
12.8.1
Parallel Ports
Alternate Functions of Port 5
Each line of Port 5 is also connected to one of the multiplexer of the Analog/Digital
Converter. All port lines (P5.15...P5.0) can accept analog signals (AN15...AN0) to be
converted by the ADC. No special programming is required for pins that shall be used as
analog inputs. Some pins of Port 5 also serve as external timer control lines for GPT1 and
GPT2.
Table 24 summarizes the alternate functions of Port 5.
Table 24. Port 5 Alternate Functions
Port 5 Pin
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
P5.9
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
Alternate Function a)
Alternate Function b)
Analog Input AN0
Analog Input AN1
Analog Input AN2
Analog Input AN3
Analog Input AN4
Analog Input AN5
Analog Input AN6
Analog Input AN7
Analog Input AN8
Analog Input AN9
Analog Input AN10
Analog Input AN11
Analog Input AN12
Analog Input AN13
Analog Input AN14
Analog Input AN15
T6EUDTimer 6 external Up/Down Input
T5EUDTimer 5 external Up/Down Input
T6INTimer 6 Count Input
T5INTimer 5 Count Input
T4EUDTimer 4 external Up/Down Input
T2EUDTimer 2 external Up/Down Input
Figure 33. PORT5 I/O and Alternate Functions
Alternate Function
Port 5
a)
P5.15
P5.14
P5.13
P5.12
P5.11
P5.10
P5.9
P5.8
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
General Purpose Inputs
b)
T2EUD
T4EUD
T5IN
T6IN
T5EUD
T6EUD
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
A/D Converter Inputs
DocID13266 Rev 2
Timer Inputs
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Parallel Ports
ST10F269Z1-ST10F269Z2
Port 5 pins have a special port structure (see Figure 34), first because it is an input only
port, and second because the analog input channels are directly connected to the pins
rather than to the input latches.
Figure 34. Block Diagram of a Port 5 Pin
Channel
Select
Analog
Switch
Internal Bus
to Sample + Hold
Circuit
P5.y/ANy
Read Port P5.y
Clock
Input
Latch
Read
Buffer
12.8.2
y = 15...0
Port 5 Schmitt Trigger Analog Inputs
A Schmitt trigger protection can be activated on each pin of Port 5 by setting the dedicated
bit of register P5DIDIS.
P5DIDIS (FFA4H / D2H)
SFR Reset Value: 0000H
15
14
13
12
11
10
9
P5DI P5DI P5DI P5DI P5DI P5DI P5DI
DIS.15 DIS.14 DIS.13 DIS.12 DIS.11 DIS.10 DIS.9
RW
RW
P5DIDIS.y
12.9
RW
RW
RW
RW
RW
8
7
6
5
4
3
2
1
0
P5DI
DIS.8
P5DI
DIS.7
P5DI
DIS.6
P5DI
DIS.5
P5DI
DIS.4
P5DI
DIS.3
P5DI
DIS.2
P5DI
DIS.1
P5DI
DIS.0
RW
RW
RW
RW
RW
RW
RW
RW
RW
Port 5 Digital Disable Register Bit y
P5DIDIS.y = 0: Port line P5.y digital input is enabled (Schmitt trigger enabled)
P5DIDIS.y = 1: Port line P5.y digital input is disabled (Schmitt trigger disabled,
necessary for input leakage current reduction)
Port 6
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured
via the corresponding direction register DP6. Each port line can be switched into push/pull
or open drain mode via the open drain control register ODP6.
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DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Parallel Ports
P6 (FFCCh / E6h)
SFR Reset Value: --00H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
P6.y
Port Data Register P6 Bit y
DP6 (FFCEH / E7H)
SFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
DP6.7 DP6.6 DP6.5 DP6.4 DP6.3 DP6.2 DP6.1 DP6.0
RW
DP6.y
RW
RW
RW
RW
RW
RW
RW
Port Direction Register DP6 Bit y
DP6.y = 0: Port line P6.y is an input (high impedance)
DP6.y = 1: Port line P6.y is an output
ODP6 (F1CEH / E7H)
ESFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
RW
ODP6.y
12.9.1
6
5
4
3
2
1
0
ODP6.7 ODP6.6 ODP6.5 ODP6.4 ODP6.3 ODP6.2 ODP6.1 ODP6.0
RW
RW
RW
RW
RW
RW
RW
Port 6 Open Drain Control Register Bit y
ODP6.y = 0: Port line P6.y output driver in push-pull mode
ODP6.y = 1: Port line P6.y output driver in open drain mode
Alternate Functions of Port 6
A programmable number of chip select signals (CS4...CS0) derived from the bus control
registers (BUSCON4...BUSCON0) can be output on 5 pins of Port 6.
The number of chip select signals is selected via PORT0 during reset. The selected value
can be read from bit-field CSSEL in register RP0H (read only) in order to check the
configuration during run time.
Table 25 summarizes the alternate functions of Port 6 depending on the number of selected
chip select lines (coded via bit-field CSSEL).
Table 25. Port 6 Alternate Functions
Port 6
Alternate Function
CSSEL = 10
Alternate Function
CSSEL = 01
P6.0
P6.1
P6.2
P6.3
P6.4
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
P6.5
P6.6
P6.7
HOLD External hold request input
HLDA Hold acknowledge output
BREQ Bus request output
Chip select CS0
Chip select CS1
General purpose I/O
General purpose I/O
General purpose I/O
Alternate Function
CSSEL = 00
Chip select CS0
Chip select CS1
Chip select CS2
General purpose I/O
General purpose I/O
DocID13266 Rev 2
Alternate Function
CSSEL = 11
Chip select
Chip select
Chip select
Chip select
Chip select
CS0
CS1
CS2
CS3
CS4
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Parallel Ports
ST10F269Z1-ST10F269Z2
Figure 35. PORT6 I/O and Alternate Functions
Alternate Function
Port 6
a)
BREQ
HLDA
HOLD
CS4
CS3
CS2
CS1
CS0
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
General Purpose Input/Output
The chip select lines of Port 6 have an internal weak pull-up device. This device is switched
on during reset. This feature is implemented to drive the chip select lines high during reset in
order to avoid multiple chip selection.
After reset the CS function must be used, if selected so. In this case there is no possibility to
program any port latches before. Thus the alternate function (CS) is selected automatically
in this case.
Note:
100/206
The open drain output option can only be selected via software earliest during the
initialization routine; at least signal CS0 will be in push/pull output driver mode directly after
reset.
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Parallel Ports
Figure 36. Block Diagram of Port 6 Pins with an Alternate Output Function
Write ODP6.y
Open Drain
Latch
1
MUX
Read ODP6.y
"0"
0
Write DP6.y
"1"
1
MUX
Internal Bus
Direction
Latch
0
Read DP6.y
Alternate
Function
Enable
Write DP6.y
Alternate
Data
Output
Port Output
Latch
1
MUX
Output
Buffer
0
P6.y
Read P6.y
Clock
1
MUX
Input
Latch
0
DocID13266 Rev 2
y = (0...4, 6, 7)
101/206
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Parallel Ports
ST10F269Z1-ST10F269Z2
Figure 37. Block Diagram of Pin P6.5 (HOLD
Write ODP6.5
Open Drain
Latch
Read ODP6.5
Write DP6.5
Internal Bus
Direction
Latch
Read DP6.5
Write P6.5
Port Output
Latch
P6.5/HOLD
Output
Buffer
Read P6.5
Clock
1
MUX
Input
Latch
0
Alternate Data Input
12.10
Port 7
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured
via the corresponding direction register DP7. Each port line can be switched into push-pull
or open drain mode via the open drain control register ODP7.
P7 (FFD0h / E8h)
SFR Reset Value: --00H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
P7.7
P7.6
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0
RW
RW
RW
RW
RW
RW
RW
RW
P7.y
102/206
Port Data Register P7 Bit y
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Parallel Ports
DP7 (FFD2h / E9h)
SFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
5
4
3
2
1
0
DP7.7 DP7.6 DP7.5 DP7.4 DP7.3 DP7.2 DP7.1 DP7.0
RW
DP7.y
6
RW
RW
RW
RW
RW
RW
RW
Port Direction Register DP7 Bit y
DP7.y = 0: Port line P7.y is an input (high impedance)
DP7.y = 1: Port line P7.y is an output
ODP7 (F1D2h / E9h)
ESFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
RW
ODP7.y
12.10.1
6
5
4
3
2
1
0
ODP7.7 ODP7.6 ODP7.5 ODP7.4 ODP7.3 ODP7.2 ODP7.1 ODP7.0
RW
RW
RW
RW
RW
RW
RW
Port 7 Open Drain Control Register Bit y
ODP7.y = 0: Port line P7.y output driver in push-pull mode
ODP7.y = 1: Port line P7.y output driver in open drain mode
Alternate Functions of Port 7
The upper 4 lines of Port 7 (P7.7...P7.4) serve as capture inputs or compare outputs
(CC31IO...CC28IO) for the CAPCOM2 unit.
The usage of the port lines by the CAPCOM unit, its accessibility via software and the
precautions are the same as described for the Port 2 lines.
As all other capture inputs, the capture input function of pins P7.7...P7.4 can also be used
as external interrupt inputs (200 ns sample rate at 40 MHz CPU clock and 250 ns sample
rate at 32 MHz CPU clock).
The lower 4 lines of Port 7 (P7.3...P7.0) serve as outputs from the PWM module
(POUT3...POUT0).
At these pins the value of the respective port output latch is EXORed with the value of the
PWM output rather than ANDed, as the other pins do.
This allows to use the alternate output value either as it is (port latch holds a ‘0’) or to invert
its level at the pin (port latch holds a ‘1’).
Note that the PWM outputs must be enabled via the respective PENx bit in PWMCON1.
DocID13266 Rev 2
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Parallel Ports
ST10F269Z1-ST10F269Z2
Table 26 summarizes the alternate functions of Port 7.
Table 26. Port 7 Alternate Functions
Port 7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
Alternate Function
POUT0PWM mode channel 0 output
POUT1PWM mode channel 1 output
POUT2PWM mode channel 2 output
POUT3PWM mode channel 3 output
CC28IOCapture input / compare output channel 28
CC29IOCapture input / compare output channel 29
CC30IOCapture input / compare output channel 30
CC31IOCapture input / compare output channel 31
Figure 38. PORT 7 I/O and Alternate Functions
Port 7
P7.7
P7.6
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0
General Purpose Input/Output
CC31IO
CC30IO
CC29IO
CC28IO
POUT3
POUT2
POUT1
POUT0
Alternate Function
The structure of Port 7 differs in the way the output latches are connected to the internal bus
and to the pin driver. Pins P7.3...P7.0 (POUT3...POUT0) EXOR the alternate data output
with the port latch output, which allows to use the alternate data directly or inverted at the
pin driver.
104/206
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Parallel Ports
Figure 39. Block Diagram of Port 7 Pins P7.3...P7.0
Write ODP7.y
Open Drain
Latch
Read ODP7.y
Write DP7.y
Internal Bus
Direction
Latch
Read DP7.y
Alternate
Data
Output
Write DP7.y
Port Output
Latch
Port Data
Output
=1
Output
Buffer
EXOR
P7.y/POUTy
Read P7.y
Clock
1
MUX
Input
Latch
0
DocID13266 Rev 2
y = 0...3
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Parallel Ports
ST10F269Z1-ST10F269Z2
Figure 40. Block Diagram of Port 7 Pins P7.7...P7.
Write ODP7.y
Open Drain
Latch
Read ODP7.y
Write DP7.y
Internal Bus
Direction
Latch
Read DP7.y
1
Alternate
Data
Output
Output
Latch
MUX
Output
Buffer
0
Write Port P7.y
Compare Trigger
P7.y
CCzIO
≥1
Read P7.y
Clock
1
MUX
0
Input
Latch
Alternate Latch
Data Input
Alternate Pin
Data Input
12.11
y = (4...7)
z = (28...31)
Port 8
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured
via the corresponding direction register DP8. Each port line can be switched into push/pull
or open drain mode via the open drain control register ODP8.
106/206
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Parallel Ports
P8 (FFD4h / EAh)
SFR Reset Value: --00H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
P8.7
P8.6
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
P8.y
Port Data Register P8 Bit y
DP8 (FFD6h / EBh)
SFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
DP8.7 DP8.6 DP8.5 DP8.4 DP8.3 DP8.2 DP8.1 DP8.0
RW
DP8.y
RW
RW
RW
RW
RW
RW
RW
Port Direction Register DP8 Bit y
DP8.y = 0: Port line P8.y is an input (high impedance)
DP8.y = 1: Port line P8.y is an output
ODP8 (F1D6h / EBh)
ESFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
RW
ODP8.y
12.11.1
6
5
4
3
2
1
0
ODP8.7 ODP8.6 ODP8.5 ODP8.4 ODP8.3 ODP8.2 ODP8.1 ODP8.0
RW
RW
RW
RW
RW
RW
RW
Port 8 Open Drain Control Register Bit y
ODP8.y = 0: Port line P8.y output driver in push-pull mode
ODP8.y = 1: Port line P8.y output driver in open drain mode
Alternate Functions of Port 8
The 8 lines of Port 8 serve as capture inputs or as compare outputs (CC23IO...CC16IO) for
the CAPCOM2 unit.
The usage of the port lines by the CAPCOM unit, its accessibility via software and the
precautions are the same as described for the Port 2 lines.
As all other capture inputs, the capture input function of pins P8.7...P8.0 can also be used
as external interrupt inputs (200ns sample rate at 40MHz CPU clock and 250ns sample rate
at 32MHz CPU clock).
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Parallel Ports
ST10F269Z1-ST10F269Z2
Table 27 summarizes the alternate functions of Port 8.
Table 27. Port 8 Alternate Functions
Port 7
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
Alternate Function
CC16IOCapture input / compare output channel 16
CC17IOCapture input / compare output channel 17
CC18IOCapture input / compare output channel 18
CC19IOCapture input / compare output channel 19
CC20IOCapture input / compare output channel 20
CC21IOCapture input / compare output channel 21
CC22IOCapture input / compare output channel 22
CC23IOCapture input / compare output channel 23
Figure 41. PORT 8I/O and Alternate Functions
Port 8
P8.7
P8.6
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
CC23IO
CC22IO
CC21IO
CC20IO
CC19IO
CC18IO
CC17IO
CC16IO
General Purpose Input / Output
Alternate Function
The structure of Port 8 differs in the way the output latches are connected to the internal bus
and to the pin driver (see Figure 42). Pins P8.7...P8.0 (CC23IO...CC16IO) combine internal
bus data and alternate data output before the port latch input, as do the Port 2 pins
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Parallel Ports
Figure 42. Block Diagram of Port 8 Pins P8.7...P8.0
Write ODP8.y
Open Drain
Latch
Read ODP8.y
Write DP8.y
Internal Bus
Direction
Latch
Read DP8.y
1
Alternate
Data
Output
Output
Latch
MUX
Output
Buffer
0
Write Port P8.y
Compare Trigger
P8.y
CCzIO
≥1
Read P8.y
Clock
1
MUX
0
Input
Latch
Alternate Latch
Data Input
Alternate Pin
Data Input
DocID13266 Rev 2
y = (7...0)
z = (16...23)
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A/D Converter
13
ST10F269Z1-ST10F269Z2
A/D Converter
A 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit is
integrated on-chip. The sample time (for loading the capacitors) and the conversion time is
programmable and can be adjusted to the external circuitry.
To remove high frequency components from the analog input signal, a low-pass filter must
be connected at the ADC input.
Overrun error detection / protection is controlled by the ADDAT register. Either an interrupt
request is generated when the result of a previous conversion has not been read from the
result register at the time the next conversion is complete, or the next conversion is
suspended until the previous result has been read. For applications which require less than
16 analog input channels, the remaining channel inputs can be used as digital input port
pins. The A/D converter of the ST10F269 supports different conversion modes:
•
Single channel single conversion: the analog level of the selected channel is
sampled once and converted. The result of the conversion is stored in the ADDAT
register.
•
Single channel continuous conversion: the analog level of the selected channel is
repeatedly sampled and converted. The result of the conversion is stored in the ADDAT
register.
•
Auto scan single conversion: the analog level of the selected channels are sampled
once and converted. After each conversion the result is stored in the ADDAT register.
The data can be transferred to the RAM by interrupt software management or using the
powerful Peripheral Event Controller (PEC) data transfer.
•
Auto scan continuous conversion: the analog level of the selected channels are
repeatedly sampled and converted. The result of the conversion is stored in the ADDAT
register. The data can be transferred to the RAM by interrupt software management or
using the PEC data transfer.
•
Wait for ADDAT read mode: when using continuous modes, in order to avoid to
overwrite the result of the current conversion by the next one, the ADWR bit of
ADCON control register must be activated. Then, until the ADDAT register is read, the
new result is stored in a temporary buffer and the conversion is on hold.
•
Channel injection mode: when using continuous modes, a selected channel can be
converted in between without changing the current operating mode. The 10-bit data of
the conversion are stored in ADRES field of ADDAT2. The current continuous mode
remains active after the single conversion is completed
Table 28. ADC Sample Clock and Conversion Clock at fCPU = 40 MHz
ADCTC
Conversion Clock tCC
TCL(1) = 1/2 x fXTAL
At fCPU = 40 MHz
00
TCL x 24
0.3μs
01
Reserved, do not use
10
11
ADSTC
tSC =
At fCPU = 40 MHz
00
tCC
0.3μs(2)
Reserved
01
tCC x 2
0.6μs (2)
TCL x 96
1.2 μs
10
tCC x 4
1.2μs (2)
TCL x 48
0.6 μs
11
tCC x 8
2.4μs (2)
1. Section 21.4.5 for TCL definition.
2. tCC = TCL x 24.
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Sample Clock tSC
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ST10F269Z1-ST10F269Z2
A/D Converter
Table 29. ADC Sample Clock and Conversion Clock at fCPU = 32MHz
ADCON 15/14
ADCTC
Conversion Clock tCC
TCL(1) = 1/2 x fXTAL
ADCON 13/12
ADSTC
At fCPU = 32MHz
Sample Clock tSC
tSC =
At fCPU = 32MHz
00
TCL x 24
0.375μs
00
tCC
0.375μs (2)
01
Reserved, do not use
Reserved
01
tCC x 2
0.75μs (2)
10
TCL x 96
1.5 μs
10
tCC x 4
1.50μs (2)
11
TCL x 48
0.75 μs
11
tCC x 8
3.00μs (2)
1. Section 21.4.5 for TCL definition.
2. tCC = TCL x 24.
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Serial Channels
14
ST10F269Z1-ST10F269Z2
Serial Channels
Serial communication with other microcontrollers, microprocessors, terminals or external
peripheral components is provided by two serial interfaces: the asynchronous / synchronous
serial channel (ASCO) and the high-speed synchronous serial channel (SSC). Two
dedicated baud rate generators set up all standard baud rates without the requirement of
oscillator tuning. For transmission, reception and erroneous reception, 3 separate interrupt
vectors are provided for each serial channel.
14.1
Asynchronous / Synchronous Serial Interface (ASCO)
The asynchronous / synchronous serial interface (ASCO) provides serial communication
between the ST10F269 and other microcontrollers, microprocessors or external peripherals.
A set of registers is used to configure and to control the ASCO serial interface:
14.1.1
•
P3, DP3, ODP3 for pin configuration
•
SOBG for baud rate generator
•
SOTBUF for transmit buffer
•
SOTIC for transmit interrupt control
•
SOTBIC for transmit buffer interrupt control
•
SOCON for control
•
SORBUF for receive buffer (read only)
•
SORIC for receive interrupt control
•
SOEIC for error interrupt control
ASCO in Asynchronous Mode
In asynchronous mode, 8 or 9-bit data transfer, parity generation and the number of stop bit
can be selected. Parity framing and overrun error detection is provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered. Fullduplex communication up to 1.25 Mbaud at 40 MHz CPU Clock (and up to 1 Mbaud at
32 MHz CPU Clock) is supported in this mode.
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Serial Channels
Figure 43. Asynchronous Mode of Serial Channel ASC0
Reload Register
CPU
Clock
2
16
Baud Rate Timer
S0R
S0FE S0PE S0OE
S0M S0STP
Clock
S0RIR
Receive Interrupt
Request
Serial Port Control
S0TIR
Transmit Interrupt
Request
Shift Clock
S0EIR
Error Interrupt
Request
S0REN
S0FEN
S0PEN
S0OEN
Input
RXD0/P3.11
S0LB
Pin
0
MUX
Transmit Shift
Register
Receive Shift
Register
Sampling
1
Pin
TXD0 / P3.10
Output
Receive Buffer
Register S0RBUF
Transmit Buffer
Register S0TBUF
Internal Bus
Asynchronous Mode baud rates
For asynchronous operation, the baud rate generator provides a clock with 16 times the rate
of the established baud rate. Every received bit is sampled at the 7th, 8th and 9th cycle of
this clock. The baud rate for asynchronous operation of serial channel ASC0 and the
required reload value for a given baud rate can be determined by the following formulas:
fCPU
BAsync =
16 x [2 + (S0BRS)] x [(S0BRL) + 1]
fCPU
S0BRL = (
16 x [2 + (S0BRS)] x BAsync
)-1
(S0BRL) represents the content of the reload register, taken as unsigned 13-bit integer,
(S0BRS) represents the value of bit S0BRS (‘0’ or ‘1’), taken as integer.
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Using the above equation, the maximum baud rate can be calculated for any given clock
speed. Baud rate versus reload register value (SOBRS=0 and SOBRS=1) is described in
Table 30 and Table 31.
Table 30. Commonly Used Baud Rates by Reload Value and Deviation Errors at fCPU = 40 MHz
S0BRS = ‘0’, fCPU = 25 MHz
Baud Rate (baud)
Deviation
Error(1)
S0BRS = ‘1’, fCPU = 25 MHz
Reload Value
(hexa)
Baud Rate (baud) Deviation Error
Reload Value
(hexa)
1 250 000
0.0% / 0.0%
0000 / 0000
833 333
0.0% / 0.0%
0000 / 0000
112 000
+1.5% / -7.0%
000A / 000B
112 000
+6.3% / -7.0%
0006 / 0007
56 000
+1.5% / -3.0%
0015 / 0016
56 000
+6.3% / -0.8%
000D / 000E
38 400
+1.7% / -1.4%
001F / 0020
38 400
+3.3% / -1.4%
0014 / 0015
19 200
+0.2% / -1.4%
0040 / 0041
19 200
+0.9% / -1.4%
002A / 002B
9 600
+0.2% / -0.6%
0081 / 0082
9 600
+0.9% / -0.2%
0055 / 0056
4 800
+0.2% / -0.2%
0103 / 0104
4 800
+0.4% / -0.2%
00AC / 00AD
2 400
+0.2% / -0.0%
0207 / 0208
2 400
+0.1% / -0.2%
015A / 015B
1 200
0.1% / 0.0%
0410 / 0411
1 200
+0.1% / -0.1%
02B5 / 02B6
600
0.0% / 0.0%
0822 / 0823
600
+0.1% / -0.0%
056B / 056C
300
0.0% / 0.0%
1045 / 1046
300
0.0% / 0.0%
0AD8 / 0AD9
153
0.0% / 0.0%
1FE8 / 1FE9
102
0.0% / 0.0%
1FE8 / 1FE9
1. The deviation errors given in Table 30 are rounded. To avoid deviation errors use a baud rate crystal (providing a multiple of
the ASC0/SSC sampling frequency).
Table 31. Commonly Used Baud Rates by Reload Value and Deviation Errors at fCPU = 32 MHz
S0BRS = ‘0’, fCPU = 32MHz
S0BRS = ‘1’, fCPU = 32MHz
Baud Rate (baud)
Deviation
Error(1)
Reload Value
1000 000
±0.0%
0000h
666 667
±0.0%
0000h
56000
+5.0% / -0.8%
0010h / 001h
56000
+8.2% / -0.8%
000Ah / 000Bh
38400
+0.2% / -3.5%
0019h / 0020h
38400
+2.1% / -3.5%
0010h / 0011h
19200
+0.2% / -1.7%
0033h / 0034h
19200
+2.1% / -0.8%
0021h / 0022h
9600
+0.2% / -0.8%
0067h/ 0068h
9600
+0.6% / -0.8%
0044h / 0045h
4800
+0.5% / -0.3%
00CFh / 00CEh
4800
+0.6% / -0.1%
0089h / 008Ah
2400
+0.2% / -0.1%
019Fh / 01A0h
2400
+0.3% / -0.1%
0114h / 0115h
1200
+0.1% / -0.1%
0340h / 0341h
1200
+0.1% / -0.1%
022Ah / 022Bh
600
+0.1% / -0.1%
0681h / 0682h
600
+0.1% / -0.1%
0456h / 0457h
95
+0.1% / -0.1%
291Dh / 291Eh
75
+0.1% / 0.1%
22B7h / 22B8h
-
-
-
63
+0.1% / -0.1%
2955h / 2956h
Baud Rate (baud) Deviation Error
Reload Value
1. The deviation errors given in Table 31 are rounded. To avoid deviation errors use a baud rate crystal (providing a multiple of
the ASC0/SSC sampling frequency).
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14.1.2
Serial Channels
ASCO in Synchronous Mode
In synchronous mode, data are transmitted or received synchronously to a shift clock which
is generated by the ST10F269. Half-duplex communication up to 5 Mbaud (at 40 MHz fCPU)
or 4 Mbaud (at 32 MHz) is possible in this mode.
Figure 44. Synchronous Mode of Serial Channel ASC0
Reload Register
CPU
Clock
2
S0R
S0M = 000B
S0OE
Clock
S0REN
S0RIR
Receive Interrupt
Request
S0TIR
Transmit Interrupt
Request
S0EIR
Error Interrupt
Request
S0OEN
Output
TDX0/P3.10
Serial Port Control
S0LB
Pin
Input/Output
RXD0/P3.11
4
Baud Rate Timer
Shift Clock
Receive
0
Pin
Receive Shift
Register
Transmit Shift
Register
Receive Buffer
Register S0RBUF
Transmit Buffer
Register S0TBUF
MUX
1
Transmit
Internal Bus
Synchronous Mode Baud Rates
For synchronous operation, the baud rate generator provides a clock with 4 times the rate of
the established baud rate. The baud rate for synchronous operation of serial channel ASC0
can be determined by the following formula:
BSync =
fCPU
4 x [2 + (S0BRS)] x [(S0BRL) + 1]
fCPU
S0BRL = (
4 x [2 + (S0BRS)] x BSync
)-1
(S0BRL) represents the content of the reload register, taken as unsigned 13-bit integers,
(S0BRS) represents the value of bit S0BRS (‘0’ or ‘1’), taken as integer.
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ST10F269Z1-ST10F269Z2
Using the above equation, the maximum baud rate can be calculated for any clock speed as
given in Table 32 and Table 33.
Table 32. Commonly Used Baud Rates by Reload Value and Deviation Errors (fCPU = 40 MHz)
S0BRS = ‘0’
Baud Rate (baud)
Deviation
Error(1)
S0BRS = ‘1’
Reload Value
(hexa)
Baud Rate (baud) Deviation Error
Reload Value
(hexa)
5 000 000
0.0% / 0.0%
0000 / 0000
3 333 333
0.0% / 0.0%
0000 / 0000
112 000
+1.5% / -0.8%
002B / 002C
112 000
+2.6% / -0.8%
001C / 001D
56 000
+0.3% / -0.8%
0058 / 0059
56 000
+0.9% / -0.8%
003A / 003B
38 400
+0.2% / -0.6%
0081 / 0082
38 400
+0.9% / -0.2%
0055 / 0056
19 200
+0.2% / -0.2%
0103 / 0104
19 200
+0.4% / -0.2%
00AC / 00AD
9 600
+0.2% / -0.0%
0207 / 0208
9 600
+0.1% / -0.2%
015A / 015B
4 800
+0.1% / -0.0%
0410 / 0411
4 800
+0.1% / -0.1%
02B5 / 02B6
2 400
0.0% / 0.0%
0822 / 0823
2 400
+0.1% / -0.0%
056B / 056C
1 200
0.0% / 0.0%
1045 / 1046
1 200
0.0% / 0.0%
0AD8 / 0AD9
900
0.0% / 0.0%
15B2 / 15B3
600
0.0% / 0.0%
15B2 / 15B3
612
0.0% / 0.0%
1FE8 / 1FE9
407
0.0% / 0.0%
1FFD / 1FFE
1. The deviation errors given in Table 32 are rounded. To avoid deviation errors use a baud rate crystal (providing a multiple of
the ASC0/SSC sampling frequency).
Table 33. Commonly Used Baud Rates by Reload Value and Deviation Errors (fCPU = 32 MHz)
S0BRS = ‘0’
Baud Rate (baud)
Deviation
Error(1)
S0BRS = ‘1’
Reload Value
Baud Rate (baud) Deviation Error
Reload Value
4 000 000
±0.0%
0000h
2 666 667
±0.0%
0000h
224 000
+5.0% / -0.8%
0011h / 0012h
224 000
+8.2% / -0.8%
000Bh / 000Ch
112 000
+2.0% / -0.8%
0023h / 0024h
112 000
+3.5% / -0.8%
0017h / 0018h
56 000
+0.6% / -0.8%
0046h / 0047h
56 000
+1.3% / -0.8%
002Fh / 0030h
38 400
+0.2% / -0.85%
0077h / 0078h
38 400
+0.6% / -0.8%
0044h / 0045h
19 200
+0.2% / -0.3%
00BFh / 00C0h
19 200
+0.6% / -0.1%
008Ah / 008Bh
9 600
+0.2% / -0.1%
01A0h/ 01A1h
9 600
+0.3% / -0.1%
0115h / 0116h
4 800
+0.0% / -0.1%
0340h / 0341h
4 800
+0.1% / -0.1%
022Bh / 022Ch
2 400
+0.0% / -0.0%
0682h / 0683h
2 400
+0.0% / -0.1%
0456h / 0457h
1 200
+0.0% / -0.0%
004h / 0D05h
1 200
+0.0% / -0.0%
08ACh / 08ADh
600
+0.0% / -0.0%
1A0Ah / 1A0Bh
600
+0.0% / -0.0%
115Bh / 115C7h
490
+0.0% / -0.0%
1FE2h / 1FE3h
320
+0.2%
1FFFh
1. The deviation errors given in Table 33 are rounded. To avoid deviation errors use a baud rate crystal (providing a multiple of
the ASC0/SSC sampling frequency).
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14.2
Serial Channels
High Speed Synchronous Serial Channel (SSC)
The High-Speed Synchronous Serial Interface SSC provides flexible high-speed serial
communication between the ST10F269 and other microcontrollers, microprocessors or
external peripherals.
The SSC supports full-duplex and half-duplex synchronous communication. The serial clock
signal can be generated by the SSC itself (master mode) or be received from an external
master (slave mode). Data width, shift direction, clock polarity and phase are
programmable.
This allows communication with SPI-compatible devices. Transmission and reception of
data is double-buffered. A 16-bit baud rate generator provides the SSC with a separate
serial clock signal. The serial channel SSC has its own dedicated 16-bit baud rate generator
with 16-bit reload capability, allowing baud rate generation independent from the timers.
Figure 45. Synchronous Serial Channel SSC Block Diagram
CPU
Clock
Slave Clock
Pin
Clock Control
Baud Rate Generator
Shift
Clock
SCLK
Master Clock
Receive Interrupt Request
SSC Control
Block
Transmit Interrupt Request
Error Interrupt Request
Status
Control
Pin
MTSR
Pin
MRST
Pin
Control
16-Bit Shift Register
Transmit Buffer
Register SSCTB
Receive Buffer
Register SSCRB
Internal Bus
Baud Rate Generation
The baud rate generator is clocked by fCPU/2. The timer is counting downwards and can be
started or stopped through the global enable bit SSCEN in register SSCCON. Register
SSCBR is the dual-function Baud Rate Generator/Reload register. Reading SSCBR, while
the SSC is enabled, returns the content of the timer. Reading SSCBR, while the SSC is
disabled, returns the programmed reload value. In this mode the desired reload value can
be written to SSCBR.
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Serial Channels
Note:
ST10F269Z1-ST10F269Z2
Never write to SSCBR, while the SSC is enabled.
The formulas below calculate the resulting baud rate for a given reload value and the
required reload value for a given baud rate:
fCPU
Baud rateSSC =
2 x [(SSCBR) + 1]
fCPU
SSCBR = (
)-1
2 x Baud rateSSC
(SSCBR) represents the content of the reload register, taken as unsigned 16-bit integer.
Table 34 lists some possible baud rates against the required reload values and the resulting
bit times for a 25 MHz CPU clock.
Table 34. Synchronous Baud Rate and Reload Values (fCPU = 40MHz)
Baud Rate
Bit Time
Reload Value
-
-
10 Mbaud
100 ns
0001h
5 Mbaud
200 ns
0003h
2.5 Mbaud
400 ns
0007h
1 Mbaud
1 μs
0013h
100 Kbaud
10 μs
00C7h
10 Kbaud
100 μs
07CFh
1 Kbaud
1 ms
4E1Fh
306 baud
3.26 ms
FF4Eh
Reserved use a reload value >
0.
Table 35 lists some possible baud rates against the required reload values and the resulting
bit times for a 32MHz CPU clock.
Table 35. Synchronous Baud Rate and Reload Values (fCPU = 32MHz)
Baud Rate
Bit Time
Reload Value
-
-
8 Mbaud
125 ns
0001h
4 Mbaud
250 s
0003h
2 Mbaud
500 ns
0007h
1 Mbaud
1 μs
000Fh
500 Kbaud
2 μs
001Fh
100 Kbaud
10 μs
009Fh
10 Kbaud
100 μs
030Ch
1 Kbaud
1 ms
3E7Fh
5.24 ms
FFFFh
Reserved use a reload value >
0.
244.14 baud
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15
CAN Modules
CAN Modules
The two integrated CAN modules (CAN1 and CAN2) are identical and handle the
completely autonomous transmission and reception of CAN frames according to the CAN
specification V2.0 part B (active).
Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers
as well as extended frames with 29-bit identifiers. These two CAN modules are both
identical to the CAN module of the ST10F167.
Because of duplication of the CAN controllers, the following adjustments are to be
considered:
•
Same internal register addresses of both CAN controllers, but with base addresses
differing in address bit A8; separate chip select for each CAN module. Refer to
Section 4: Memory Organization.
•
The CAN1 transmit line (CAN1_TxD) is the alternate function of the Port P4.6 pin and
the receive line (CAN1_RxD) is the alternate function of the Port P4.5 pin.
•
The CAN2 transmit line (CAN2_TxD) is the alternate function of the Port P4.7 pin and
the receive line (CAN2_RxD) is the alternate function of the Port P4.4 pin.
•
Interrupt request line of the CAN1 module is connected to the XBUS interrupt line XP0,
interrupt of the CAN2 module is connected to the line XP1.
•
The CAN modules must be selected with corresponding CANxEN bit of XPERCON
register before the bit XPEN of SYSCON register is set.
•
The reset default configuration is: CAN1 is enabled, CAN2 is disabled.
15.1
CAN Modules Memory Mapping
15.1.1
CAN1
Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 Module access. CAN1 is
enabled by setting XPEN bit 2 of the SYSCON register and by setting bit 0 of the XPERCON
register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus
(Byte accesses are possible). Two wait states give an access time of 125 ns at 40 MHz
CPU clock or at 32 MHz CPU clock. No tri-state wait states are used.
15.1.2
CAN2
Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 Module access. CAN2 is
enabled by setting XPEN bit 2 of the SYSCON register and by setting bit 1 of the XPERCON
register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus
(Byte accesses are possible). Two wait states give an access time of 125 ns at 40 MHz or
32 MHz CPU clock. No tri-state wait states are used.
If one or both CAN modules is used, Port 4 cannot be programmed to output all 8 segment
address lines. Thus, only 4 segment address lines can be used, reducing the external
memory space to 5 Mbytes (1 Mbyte per CS line).
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CAN Modules
15.2
ST10F269Z1-ST10F269Z2
CAN Bus Configurations
Depending on application, CAN bus configuration may be one single bus with a single or
multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F269 is
able to support these 2 cases.
15.2.1
Single CAN Bus
The single CAN Bus multiple interfaces configuration may be implemented using 2 CAN
transceivers as shown in Figure 46.
Figure 46. Single CAN Bus Multiple Interfaces, Multiple Transceivers
CAN1
RxD TxD
CAN2
RxD TxD
CAN
Transceiver
CAN
Transceiver
CAN_H
CAN bus
CAN_H
The ST10F269 also supports single CAN Bus multiple (dual) interfaces using the open drain
option of the CANx_TxD output as shown in Figure 47. Thanks to the OR-Wired
Connection, only one transceiver is required. In this case the design of the application must
take in account the wire length and the noise environment.
Figure 47. Single CAN Bus, Dual Interfaces, Single Transceiver
CAN1
RxD TxD
CAN2
RxD TxD
*
*
+5V
2.7kΩ
CAN
Transceiver
CAN_H
CAN_H
CAN bus
* Open drain output
15.2.2
Multiple CAN Bus
The ST10F269 provides 2 CAN interfaces to support such kind of bus configuration as
shown in Figure 48.
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CAN Modules
Figure 48. Connection to Two Different CAN Buses (e.g. for gateway application)
CAN1
RxD TxD
CAN2
RxD TxD
CAN
Transceiver
CAN
Transceiver
CAN_H
CAN_H
CAN
bus 1
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CAN
bus 2
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Real Time Clock
16
ST10F269Z1-ST10F269Z2
Real Time Clock
The Real Time Clock is an independent timer, which clock is directly derived from the clock
oscillator on XTAL1 input so that it can keep on running even in Idle or Power down mode (if
enabled to). Registers access is implemented onto the XBUS. This module is designed for
the following purposes:
•
Generate the current time and date for the system
•
Cyclic time based interrupt, provides Port 2 external interrupts every second and every
n seconds (n is programmable) if enabled.
•
58-bit timer for long term measurement
•
Capable to exit the ST10 chip from power down mode (if PWDCFG of SYSCON set)
after a programmed delay.
The real time clock is base on two main blocks of counters. The first block is a prescaler
which generates a basic reference clock (for example a 1 second period). This basic
reference clock is coming out of a 20-bit DIVIDER (4-bit MSB RTCDH counter and 16-bit
LSB RTCDL counter). This 20-bit counter is driven by an input clock derived from the onchip high frequency CPU clock, predivided by a 1/64 fixed counter (see Figure 50). This 20bit counter is loaded at each basic reference clock period with the value of the 20-bit
PRESCALER register (4-bit MSB RTCPH register and 16-bit LSB RTCPL register). The
value of the 20-bit RTCP register determines the period of the basic reference clock.
A timed interrupt request (RTCSI) may be sent on each basic reference clock period. The
second block of the RTC is a 32-bit counter (16-bit RTCH and 16-bit RTCL). This counter
may be initialized with the current system time. RTCH/RTCL counter is driven with the basic
reference clock signal. In order to provide an alarm function the contents of RTCH/RTCL
counter is compared with a 32-bit alarm register (16-bit RTCAH register and 16-bit RTCAL
register). The alarm register may be loaded with a reference date. An alarm interrupt
request (RTCAI), may be generated when the value of RTCH/RTCL counter matches the
reference date of RTCAH/RTCAL register.
The timed RTCSI and the alarm RTCAI interrupt requests can trigger a fast external
interrupt via EXISEL register of port 2 and wake-up the ST10 chip when running power
down mode. Using the RTCOFF bit of RTCCON register, the user may switch off the clock
oscillator when entering the power down mode.
Figure 49. ESFRs and Port Pins Associated with the RTC
EXISEL
- - - - - - - - YYYY - - - -
CCxIC
- - - - - - - - YYYYYYYY
EXISEL External Interrupt Source Selection register (Port 2)
1 second timed interrupt request (RTCSI) triggers firq[2] and alarm interrupt request (RTCAI) triggers firq[3]
RTC data and control registers are implemented onto the XBUS.
122/206
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ST10F269Z1-ST10F269Z2
Real Time Clock
Figure 50. RTC Block Diagram
Clock Oscillator
RTCAI RTCSI
RTCCON
AlarmIT
Programmable ALARM Register
RTCAH
RTCAL
Basic Clock IT
Programmable PRESCALER Register
RTCPH
Reload
=
RTCH
RTCPL
RTCDH
RTCL
32 bit COUNTER
RTCDL
/64
20 bit DIVIDER
16.1
RTC registers
16.1.1
RTCCON: RTC Control Register
The functions of the RTC are controlled by the RTCCON control register. If the RTOFF bit is
set, the RTC dividers and counters clock is disabled and registers can be written, when the
ST10 chip enters power down mode the clock oscillator will be switch off. The RTC has 2
interrupt sources, one is triggered every basic clock period, the other one is the alarm.
RTCCON includes an interrupt request flag and an interrupt enable bit for each of them.
This register is read and written via the XBUS.
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Real Time Clock
ST10F269Z1-ST10F269Z2
RTCCON (EC00h)
XBUS Reset Value: --00H
15
14
13
12
11
10
9
8
7
6
5
4
-
-
-
-
-
-
-
-
RTCOFF
-
-
-
3
2
1
0
RTCAEN RTCAIR RTCSEN RTCSIR
RW
RW
RW
RW
RW
RTCOFF 2
RTC Switch Off Bit
‘0’: clock oscillator and RTC keep on running even if ST10 in power down mode‘1’:
clock oscillator is switch off if ST10 enters power down mode, RTC dividers and
counters are stopped and registers can be written
RTCAEN 2
RTC Alarm Interrupt ENable
‘0’: RTCAI is disabled
‘1’: RTCAI is enabled, it is generated every n seconds
RTCAIR 1
RTC Alarm Interrupt Request flag (when the alarm is triggered)
‘0’: the bit was reseted less than a n seconds ago
‘1’: the interrupt was triggered
RTCSEN 2
RTC Second interrupt ENable
‘0’: RTCSI is disabled
‘1’: RTCSI is enabled, it is generated every second
RTCSIR 1
RTC Second Interrupt Request flag (every second)
‘0’: the bit was reseted less than a second ago
‘1’: the interrupt was triggered
1. As RTCCON register is not bit-addressable, the value of these bits must be read by checking their
associated CCxIC register. The 2 RTC interrupt signals are connected to Port2 in order to trigger an
external interrupt that wake up the chip when in power down mode.
2. All the bit of RTCCON are active high.
16.1.2
RTCPH & RTCPL: RTC PRESCALER Registers
The 20-bit programmable prescaler divider is loaded with 2 registers.
The 4 most significant bit are stored into RTCPH and the 16 Less significant bit are stored in
RTCPL. In order to keep the system clock, those registers are not reset.
They are write protected by bit RTOFF of RTCCON register, write operation is allowed if
RTOFF is set.
RTCPL (EC06h)
XBUS Reset Value: XXXXH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
RTCPL
RW
RTCPH (EC08h)
XBUS Reset Value: ---XH
15
14
13
12
11
10
9
8
RESERVED
7
RTCPH
RW
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Real Time Clock
Figure 51. PRESCALER Register
3
2
1
0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RTCPL
RTCPH
19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
20 bit word counter
The value stored into RTCPH, RTCPL is called RTCP (coded on 20-bit). The dividing ratio
of the Prescaler divider is: ratio = 64 x (RTCP)
16.1.3
RTCDH & RTCDL: RTC DIVIDER Counters
Every basic reference clock the DIVIDER counters are reloaded with the value stored
RTCPH and RTCPL registers. To get an accurate time measurement it is possible to read
the value of the DIVIDER, reading the RTCDH, RTCDL. Those counters are read only. After
any bit changed in the programmable PRESCALER register, the new value is loaded in the
DIVIDER.
RTCDL (EC0Ah)
XBUS Reset Value: XXXXH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
RTCDL
R
RTCDH (EC0Ch)
XBUS Reset Value: ---XH
15
14
13
12
11
10
9
8
7
RESERVED
RTCDH
R
Those registers are not reset, and are read only.
When RTCD increments to reach 00000h, The 20-bit word stored into RTCPH, RTCPL
registers is loaded in RTCD.
Figure 52. DIVIDER Counters
3
2
1
0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RTCDL
RTCDH
19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
20 bit word internal value of the Prescaler divider
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Real Time Clock
ST10F269Z1-ST10F269Z2
Bit 15 to bit 4 of RTCPH and RTCDH are not used. When reading, the return value of those
bit will be zeros.
16.1.4
RTCH & RTCL: RTC Programmable COUNTER Registers
The RTC has 2 x 16-bit programmable counters which count rate is based on the basic time
reference (for example 1 second). As the clock oscillator may be kept working, even in
power down mode, the RTC counters may be used as a system clock. In addition RTC
counters and registers are not modified at any system reset. The only way to force their
value is to write them via the XBUS.
Those counters are write protected as well. The bit RTOFF of the RTCCON register must be
set (RTC dividers and counters are stopped) to enable a write operation on RTCH or RTCL.
A write operation on RTCH or RTCL register loads directly the corresponding counter. When
reading, the current value in the counter (system date) is returned.
The counters keeps on running while the clock oscillator is working.
RTCL (EC0Eh)
XBUS Reset Value: XXXXH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RTCL
RW
RTCH (EC10h)
XBUS Reset Value: XXXXH
15
14
13
12
11
10
9
8
RTCH
RW
Note:
Those registers are nor reset.
16.1.5
RTCAH & RTCAL: RTC ALARM Registers
When the programmable counters reach the 32-bit value stored into RTCAH & RTCAL
registers, an alarm is triggered and the interrupt request RTAIR is generated. Those
registers are not protected.
RTCAL (EC12h)
XBUS Reset Value: XXXXH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
RTCAL
RW
RTCAH (EC14h)
XBUS Reset Value: XXXXH
15
14
13
12
11
10
9
8
7
RTCAH
RW
Note:
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Those registers are not reset.
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
16.2
Real Time Clock
Programming the RTC
RTC interrupt request signals are connected to Port2, pad 10 (RTCSI) and pad 11 (RTCAI).
An alternate function Port2 is to generate fast interrupts firq[7:0]. To trigger firq[2] and firq[3]
the following configuration has to be set.
EXICON ESFR controls the external interrupt edge selection, RTC interrupt requests are
rising edge active.
EXICON (F1C0h)
SFR Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EXI7ES
EXI6ES
EXI5ES
EXI4ES
EXI3ES 1 2
EXI2ES 1 3
EXI1ES
EXI0ES
RW
RW
RW
RW
RW
RW
RW
RW
1. EXI2ES and EXI3ES must be configured as "01b" because RCT interrupt request lines are rising edge
active.
2. Alarm interrupt request line (RTCAI) is linked with EXI3ES.
3. Timed interrupt request line (RTCSI) is linked with EXI2ES.EXISEL ESFR enables the Port2 alternate
sources. RTC interrupts are alternate sources 2 and 3.
EXISEL (F1DAh)
ESFR Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EXI7SS
EXI6SS
EXI5SS
EXI4SS
EXI3SS 2
EXI2SS 3
EXI1SS
EXI0SS
RW
RW
RW
RW
RW
RW
RW
RW
EXIxSS
External Interrupt x Source Selection (x=7...0)
‘00’: Input from associated Port 2 pin.
‘01’: Input from “alternate source”. 1
‘10’: Input from Port 2 pin ORed with “alternate source”. 1
‘11’: Input from Port 2 pin ANDed with “alternate source”.
1. Advised configuration.
2. Alarm interrupt request (RTCAI) is linked with EXI3SS.
3. Timed interrupt request (RTCSI) is linked with EXI2SS.
Interrupt control registers are common with CAPCOM1 Unit: CC10IC (RTCSI) and CC11IC
(RTCAI).
CCxIC
SFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
CCxIR CCxIE
RW
DocID13266 Rev 2
RW
5
4
3
2
1
0
ILVL
GLVL
RW
RW
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Real Time Clock
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CC10IC: FF8Ch/C6h
CC11IC: FF8Eh/C7h
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Source of
interrupt
Request
Flag
Enable Flag
Interrupt
Vector
Vector
Location
Trap
Number
External interrupt 2
CC10IR
CC10IE
CC10INT
00’0068h
1Ah/26
External interrupt 3
CC11IR
CC11IE
CC11INT
00’006Ch
1Bh/27
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
17
Watchdog Timer
Watchdog Timer
The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from
malfunctioning for long periods of time.
The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in
the time interval until the EINIT (end of initialization) instruction has been executed.
Therefore, the chip start-up procedure is always monitored. The software must be designed
to service the watchdog timer before it overflows. If, due to hardware or software related
failures, the software fails to do so, the watchdog timer overflows and generates an internal
hardware reset. It pulls the RSTOUT pin low in order to allow external hardware
components to be reset.
Each of the different reset sources is indicated in the WDTCON register.
The indicated bits are cleared with the EINIT instruction. The origin of the reset can be
identified during the initialization phase.
WDTCON (FFAEh / D7h)
SFR Reset Value: 00xxH
15
14
13
12
11
10
9
8
WDTREL
7
6
5
4
3
2
1
0
-
-
PONR
LHWR
SHWR
SWR
WDTR
WDTIN
HR
HR
HR
HR
HR
RW
RW
WDTIN
Watchdog Timer Input Frequency Selection
‘0’: Input Frequency is fCPU/2.
‘1’: Input Frequency is fCPU/128.
WDTR1-3
Watchdog Timer Reset Indication Flag
Set by the watchdog timer on an overflow.
Cleared by a hardware reset or by the SRVWDT instruction.
SWR1-3
Software Reset Indication Flag
Set by the SRST execution.
Cleared by the EINIT instruction.
SHWR1-3
Short Hardware Reset Indication Flag
Set by the input RSTIN.
Cleared by the EINIT instruction.
LHWR1-3
Long Hardware Reset Indication Flag
Set by the input RSTIN.
Cleared by the EINIT instruction.
PONR1- 2-3
Power-On (Asynchronous) Reset Indication Flag
Set by the input RSTIN if a power-on condition has been detected.
Cleared by the EINIT instruction.
1. More than one reset indication flag may be set. After EINIT, all flags are cleared.
2. Power-on is detected when a rising edge from VDD = 0 V to VDD > 2.0 V is recognized on the internal 3.3V
supply.
3. These bits cannot be directly modified by software.
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Watchdog Timer
ST10F269Z1-ST10F269Z2
The PONR flag of WDTCON register is set if the output voltage of the internal 3.3V supply
falls below the threshold (typically 2 V) of the power-on detection circuit. This circuit is
efficient to detect major failures of the external 5 V supply but if the internal 3.3 V supply
does not drop under 2 V, the PONR flag is not set. This could be the case on fast switch-off
/ switch-on of the 5 V supply. The time needed for such a sequence to activate the PONR
flag depends on the value of the capacitors connected to the supply and on the exact value
of the internal threshold of the detection circuit.
Table 36. WDTCON Bit Value on Different Resets
Reset Source
PONR
LHWR
SHWR
SWR
WDTR
X
X
X
X
-
1) 2)
X
X
X
-
Long Hardware Reset
-
X
X
X
-
Short Hardware Reset
-
-
X
X
-
Software Reset
-
-
-
X
-
Watchdog Reset
-
-
-
X
X
Power On Reset
Power on after partial supply
failure
1. PONR bit may not be set for short supply failure.
2. For power-on reset and reset after supply partial failure, asynchronous reset must be used.
In case of bi-directional reset is enabled, and if the RSTIN pin is latched low after the end of
the internal reset sequence, then a Short hardware reset, a software reset or a watchdog
reset will trigger a Long hardware reset. Thus, Reset Indications flags will be set to indicate
a Long Hardware Reset.
The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 128. The high
Byte of the watchdog timer register can be set to a pre-specified reload value (stored in
WDTREL).
Each time it is serviced by the application software, the high byte of the watchdog timer is
reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced
Table 37 shows the watchdog time range for 25 MHz CPU clock and Table 38 shows the
watchdog time range for 32 MHz CPU clock.
Table 37. WDTREL Reload Value (fCPU = 40 MHz)
Reload value in WDTREL
Prescaler
2 (WDTIN = ‘0’)
128 (WDTIN = ‘1’)
FFh
12.8μs
819.2ms
00h
3.276ms
209.7ms
Table 38. WDTREL Reload Value (fCPU = 3 2MHz)
Reload value in WDTREL
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Prescaler
2 (WDTIN = ‘0’)
128 (WDTIN = ‘1’)
FFh
16.0μs
1.024ms
00h
4.096ms
262.1ms
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ST10F269Z1-ST10F269Z2
Watchdog Timer
The watchdog timer period is calculated with the following formula:
1
P WDT = --------------- × 512 × ( 1 + [ WDTIN ] × 63 ) × ( 256 – [ WDTREL ] )
f CPU
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System Reset
18
ST10F269Z1-ST10F269Z2
System Reset
System reset initializes the MCU in a predefined state. There are five ways to activate a
reset state. The system start-up configuration is different for each case as shown in
Table 39.
Table 39. Reset Event Definition
18.1
Reset Source
Short-cut
Conditions
Power-on reset
Long Hardware reset (synchronous &
asynchronous)
Short Hardware reset (synchronous reset)
Watchdog Timer reset
Software reset
PONR
Power-on
LHWR
t RSTIN > 1040 TCL
SHWR
WDTR
SWR
4 TCL < t RSTIN < 1038 TCL
WDT overflow
SRST execution
Long Hardware Reset
The reset is triggered when RSTIN pin is pulled low, then the MCU is immediately forced in
reset default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it
aborts external bus cycle, it switches buses (data, address and control signals) and I/O pin
drivers to high-impedance, it pulls high PORT0 pins and the reset sequence starts.
To get a long hardware reset, the duration of the external RSTIN signal must be longer than
1040 TCL. The level of RPD pin is sampled during the whole RSTIN pulse duration. A low
level on RPD pin determines an asynchronous reset while a high level leads to a
synchronous reset.
Note:
A reset can be entered as synchronous and exit as asynchronous if VRPD voltage drops
below the RPD pin threshold (typically 2.5 V for VDD = 5 V) when RSTIN pin is low or when
RSTIN pin is internally pulled low.
18.1.1
Asynchronous Reset
Figure 53 and Figure 54 show asynchronous reset condition (RPD pin is at low level).
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System Reset
Figure 53. Asynchronous Reset Sequence External Fetch
1
2
3
4
5
6
7
8
9
CPU Clock
6 or 8 TCL(1)
Asynchronous
Reset Condition
RSTIN
RPD
RSTOUT
5 TCL
ALE
RD
Reset Configuration
PORT0
1st Instruction External Fetch
Latching point of PORT0
for system start-up
configuration
Internal reset
EXTERNAL FETCH
1. RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(fCPU = fXTAL / 2), else it is 4 CPU clock cycles (8 TCL).
Figure 54. Asynchronous Reset Sequence Internal Fetch
1
2
3
CPU Clock
6 or 8 TCL (1)
RSTIN
Asynchronous
Reset Condition
Flash under reset for internal charge pump ramping up
2.5µs max.(2)
RPD
RSTOUT
PORT0
Reset Configuration
Latching point of PORT0
for PLL configuration
PLL factor
latch command
Latching point of PORT0
for remaining bits
Internal reset signal
INTERNAL FETCH
Flash read signal
1st fetch
from Flash
1. RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(fCPU = fXTAL / 2), else it is 4 CPU clock cycles (8 TCL).
2. 2.1 µs typical value.
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System Reset
ST10F269Z1-ST10F269Z2
Power-on reset
The asynchronous reset must be used during the power-on of the MCU. Depending on the
crystal frequency, the on-chip oscillator needs about 10ms to 50ms to stabilize. The logic of
the MCU does not need a stabilized clock signal to detect an asynchronous reset, so it is
suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the
RPD pin must be held at low level until the MCU clock signal is stabilized and the system
configuration value on PORT0 is settled.
Hardware reset
The asynchronous reset must be used to recover from catastrophic situations of the
application. It may be triggered by the hardware of the application. Internal hardware logic
and application circuitry are described in Section 18.6: Reset Circuitry, Figure 57, Figure 58
and Figure 59.
18.1.2
Synchronous Reset
(RSTIN pulse > 1040TCL and RPD pin at high level)
The synchronous reset is a warm reset. It may be generated synchronously to the CPU
clock. To be detected by the reset logic, the RSTIN pulse must be low at least for 4 TCL (2
periods of CPU clock).
Then the I/O pins are set to high impedance and RSTOUT pin is driven low. After the RSTIN
level is detected, a short duration of 12 TCL (6 CPU clocks) maximum elapses, during which
pending internal hold states are canceled and the current internal access cycle, if any, is
completed. External bus cycle is aborted.
The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON register was
previously set by software. This bit is always cleared on power-on or after any reset
sequence.
The internal sequence lasts for 1024 TCL (512 periods of CPU clock). After this duration the
pull-down of RSTIN pin for the bidirectional reset function is released and the RSTIN pin
level is sampled. At this step the sequence lasts 1040 TCL (4 TCL + 12 TCL + 1024 TCL). If
the RSTIN pin level is low, the reset sequence is extended until RSTIN level becomes high.
Refer to Figure 55.
Note:
134/206
If VRPD voltage drops below the RPD pin threshold (typically 2.5 V for VDD = 5 V) when
RSTIN pin is low or when RSTIN pin is internally pulled low, the ST10 reset circuitry disables
the bidirectional reset function and RSTIN pin is no more pulled low. The reset is processed
as an asynchronous reset.
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
System Reset
Figure 55. Synchronous Reset Sequence External Fetch (RSTIN pulse > 1040 TCL)
4 TCL
min.
12 TCL
max.
6 or 8 TCL1)
1
2
3
4
5
6
7
8
9
CPU Clock
1024 TCL
Internally pulled low 2)
RSTIN
RPD
200μA Discharge
If VRPD > 2.5V Asynchronous
3)
Reset is not entered.
RSTOUT
5 TCL
ALE
RD
Reset Configuration
PORT0
Latching point of PORT0
for system start-up configuration
Internal reset signal
1. RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(fCPU = fXTAL / 2), else it is 4 CPU clock cycles (8 TCL).
2. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is
cleared after reset.
3. If during the reset condition (RSTIN low), VRPD voltage drops below the threshold voltage (typically 2.5 V for 5 V
operation), the ST10 reset circuitry disables the bidirectional reset function and RSTIN pin is no more pulled low.
18.1.3
Exit of Long Hardware Reset
If the RPD pin level is low when the RSTIN pin is sampled high, the MCU completes an
asynchronous reset sequence.
If the RPD pin level is high when the RSTIN pin is sampled high, the MCU completes a
synchronous reset sequence.
The system configuration is latched from PORT0 after a duration of 8 TCL / 4 CPU clocks (6
TCL / 3 CPU clocks if PLL is bypassed) and in case of external fetch, ALE, RD and R/W
pins are driven to their inactive level. The MCU starts program execution from memory
location 00'0000h in code segment 0. This starting location will typically point to the general
initialization routine. Refer to Table 40 for PORT0 latched configuration.
18.2
Short Hardware Reset
A short hardware reset is a warm reset. It may be generated synchronously to the CPU
clock (synchronous reset).
The short hardware is triggered when RSTIN signal duration is shorter or equal to 1038
TCL, the RPD pin must be pulled high.
To properly activate the internal reset logic of the MCU, the RSTIN pin must be held low, at
least, during 4 TCL (2 periods of CPU clock). The I/O pins are set to high impedance and
RSTOUT pin is driven low. After RSTIN level is detected, a short duration of 12 TCL (6 CPU
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System Reset
ST10F269Z1-ST10F269Z2
clocks) maximum elapses, during which pending internal hold states are canceled and the
current internal access cycle if any is completed. External bus cycle is aborted. The internal
pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON register was previously set
by software. This bit is always cleared on power-on or after any reset sequence.
The internal reset sequence starts for 1024 TCL (512 periods of CPU clock).
After that duration the pull-down of RSTIN pin for the bidirectional reset function is released
and the RSTIN pin level is sampled high while RPD level is high.
The short hardware reset ends and the MCU restarts.To be processed as a short hardware
reset, the external RSTIN signal must last a maximum of 1038 TCL (4 TCL + 10 TCL + 1024
TCL). The system configuration is latched from PORT0 after a duration of 8 TCL / 4 CPU
clocks (6 TCL / 3 CPU clocks if PLL is bypassed) and in case of external fetch, ALE, RD and
R/W pins are driven to their inactive level. Program execution starts from memory location
00'0000h in code segment 0. This starting location will typically point to the general
initialization routine. Timings of synchronous reset sequence are summarized in Figure 56.
Refer to Table 40 for PORT0 latched configuration.
Note:
If the RSTIN pin level is sampled low, the reset sequence is extended until RSTIN level
becomes high leading to a long hardware reset (synchronous or asynchronous reset)
because RSTIN signal duration has lasted longer than 1040TCL.
If the VRPD voltage has dropped below the RPD pin threshold, the reset is processed as an
asynchronous reset.
Figure 56. Synchronous Warm Reset Sequence External Fetch (4 TCL < RSTIN pulse < 1038 TCL
4 TCL 10 TCL 2)
min.
min.
6 or 8 TCL4)
1024 TCL
1
2
3
4
5
6
7
8
9
CPU Clock
1)
Internally pulled low 3)
RSTIN
RPD
200μA Discharge
RSTOUT
If VRPD > 2.5V Asynchronous
5)
Reset is not entered.
5 TCL
ALE
RD
PORT0
1st Instr.
Reset Configuration
Latching point of PORT0
for system start-up configuration
Internal reset signal
1. RSTIN assertion can be released there.
2. Maximum internal synchronization is 6 CPU cycles (12 TCL).
3. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is
cleared after reset.
4. RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(fCPU = fXTAL / 2), else it is 4 CPU clock cycles (8 TCL).
5. If during the reset condition (RSTIN low), VRPD voltage drops below the threshold voltage (typically 2.5 V for 5 V
operation), the ST10 reset circuitry disables the bidirectional reset function and RSTIN pin is no more pulled low.
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ST10F269Z1-ST10F269Z2
18.3
System Reset
Software Reset
The reset sequence can be triggered at any time using the protected instruction SRST
(software reset). This instruction can be executed deliberately within a program, for example
to leave bootstrap loader mode, or upon a hardware trap that reveals a system failure.
Upon execution of the SRST instruction, the internal reset sequence (1024 TCL) is started.
The microcontroller behavior is the same as for a short hardware reset, except that only
P0.12...P0.6 bits are latched at the end of the reset sequence, while previously latched
values of P0.5...P0.2 are cleared.
18.4
Watchdog Timer Reset
When the watchdog timer is not disabled during the initialization or when it is not regularly
serviced during program execution it will overflow and it will trigger the reset sequence.
Unlike hardware and software resets, the watchdog reset completes a running external bus
cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after
the programmed wait states. When READY is sampled inactive (high) after the programmed
wait states the running external bus cycle is aborted. Then the internal reset sequence
(1024 TCL) is started.
The microcontroller behavior is the same as for a short hardware reset, except that only
P0.12...P0.6 bits are latched, while previously latched values of P0.5...P0.2 are cleared.
18.5
RSTOUT, RSTIN, Bidirectional Reset
18.5.1
RSTOUT Pin
The RSTOUT pin is driven active (low level) at the beginning of any reset sequence
(synchronous/asynchronous hardware, software and watchdog timer resets). RSTOUT pin
stays active low beyond the end of the initialization routine, until the protected EINIT
instruction (End of Initialization) is completed.
18.5.2
Bidirectional Reset
The bidirectional reset function is enabled by setting SYSCON.BDRSTEN (bit 3). This
function is disabled by any reset sequence which always clears the SYSCON.BDRSTEN
bit.
It can only be enabled during the initialization routine, before EINIT instruction is completed.
If VRPD voltage drops below the RPD pin threshold (typically 2.5V for VDD = 5V) when
RSTIN pin is low or when RSTIN pin is internally pulled low, the ST10 reset circuitry disables
the bidirectional reset function and RSTIN pin is no more pulled low. The reset is processed
as an asynchronous reset.
The bidirectional reset function is useful for external peripherals with on-chip memory
because the reset signal output on RSTIN pin is de-activated before the CPU starts its first
instruction fetch.
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System Reset
18.5.3
ST10F269Z1-ST10F269Z2
RSTIN pin
When the bidirectional reset function is enabled, the open-drain of the RSTIN pin is
activated, pulling down the reset signal, for the duration of the internal reset sequence. See
Figure 55 and Figure 56. At the end of the sequence the pull-down is released and the
RSTIN pin gets back its input function.
The bidirectional reset function can be used:
•
to convert SW or WD resets to a hardware reset so that the configuration can be (re-)
latched from PORT0.
•
to make visible SW or WDT resets at RSTIN pin whenever RSTIN is the only reset
signal used by the application (RSTOUT not used).
•
to get a die-activated reset signal before CPU starts its first instruction fetch.
The configuration latched from PORT0 is determined by the kind of reset generated by the
application. (Refer to Table 40).
Converting a SW or WDT reset to a hardware reset allows the PLL to re-lock or the PLL
configuration to be re-latched, provided a SW or WDT reset is generated by the application
program is case of PLL unlock or input clock fail.
18.6
Reset Circuitry
The internal reset circuitry is described in Figure 57.
An internal pull-up resistor is implemented on RSTIN pin. (50 kΩ minimum, to 250 kΩ
maximum). The minimum reset time must be calculated using the lowest value. In addition,
a programmable pull-down (SYSCON.BDRSTEN bit 3) drives the RSTIN pin according to
the internal reset state. The RSTOUT pin provides a signals to the application. (Refer to
Section 18.5: RSTOUT, RSTIN, Bidirectional Reset).
A weak internal pull-down is connected to the RPD pin to discharge external capacitor to
VSS at a rate of 100 mA to 200 mA. This Pull-down is turned on when RSTIN pin is low.
If bit PWDCFG of SYSCON register is set, an internal pull-up resistor is activated at the end
of the reset sequence. This pull-up charges the capacitor connected to RPD pin.
If the bidirectional reset function is not used, the simplest way to reset ST10F269 is to
connect external components as shown in Figure 58. It works with reset from application
(hardware or manual) and with power-on. The value of C1 capacitor, connected on RSTIN
pin with internal pull-up resistor (50 kΩ to 250 kΩ), must lead to a charging time long
enough to let the internal or external oscillator and / or the on-chip PLL to stabilize.
The R0-C0 components on RPD pin are mainly implemented to provide a time delay to exit
Power down mode (see Section 19: Power Reduction Modes). Nevertheless, they drive
RPD pin level during resets and they lead to different reset modes as explained hereafter.
On power-on, C0 is total discharged, a low level on RPD pin forces an asynchronous
hardware reset. C0 capacitor starts to charge through R0 and at the end of reset sequence
ST10F269 restarts. RPD pin threshold is typically 2.5 V.
Depending on the delay of the next applied reset, the MCU can enter a synchronous reset
or an asynchronous reset. If RPD pin is below 2.5 V an asynchronous reset starts, if RPD
pin is above 2.5 V a synchronous reset starts (see Section 18.1: Long Hardware Reset and
Section 18.2: Short Hardware Reset).
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ST10F269Z1-ST10F269Z2
System Reset
Note that an internal pull-down is connected to RPD pin and can drive a 100mA to 200mA
current. This Pull-down is turned on when RSTIN pin is low.
To properly use the bidirectional reset features, the schematic (or equivalent) of Figure 59
must be implemented. R1-C1 only work for power-on or manual reset in the same way as
explained previously. D1 diode brings a faster discharge of C1 capacitor at power-off during
repetitive switch-on / switch-off sequences. D2 diode performs an OR-wired connection, it
can be replaced with an open drain buffer. R2 resistor may be added to increase the pull-up
current to the open drain in order to get a faster rise time on RSTIN pin when bidirectional
function is activated.
The start-up configurations and some system features are selected on reset sequences as
described in Table 40 and Table 41.
Table 40 describes what is the system configuration latched on PORT0 in the five different
reset ways. Table 41 summarizes the state of bits of PORT0 latched in RP0H, SYSCON,
BUSCON0 registers.
Figure 57. Internal (simplified) Reset Circuitry
EINIT Instruction
Clr
Q
RSTOUT
Set
Reset State
Machine
Clock
Internal
Reset
Signal
VDD
SRST instruction
watchdog overflow
Trigger
RSTIN
Clr
BDRSTEN
Reset Sequence
(512 CPU Clock Cycles)
VDD
Asynchronous
Reset
RPD
From/to Exit
Powerdown
Circuit
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(~200μA)
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System Reset
ST10F269Z1-ST10F269Z2
Figure 58. Minimum External Reset Circuitry
VDD
R0
RSTIN
RPD
+
External
Hardware
RSTOUT
ST10F269
+
b)
a)
C1
C0
a) Manual hardware reset1
b) For automatic power-up and
interruptible power-down mode
Figure 59. External Reset Hardware Circuitry
VDD
R2
VDD
RSTIN
RSTOUT
R0
VDD
External
Hardware
ST10F269
D1
R1
D2
RPD
+
+
C0
C1
Open - drain
External
Inverter
Reset Source
Table 40. PORT0 Latched Configuration for the Different Resets
Reserved
BSL
Reserved
Reserved
Adapt Mode
Emu Mode
P0L.7
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
P0L.0
-
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
-
-
-
-
-
-
P0H.6
P0H.7
Bus Type
P0H.0
WR confide.
Chip Selects
P0H.1
-
-
P0H.3
-
Watchdog Reset
Sample event
P0H.4
Software Reset
X: Pin is sampled
-: Pin is not sampled
P0H.5
P0H.2
Clock Options
Seem. Add. Lines
PORT0
Short Hardware Reset
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
Long Hardware Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Power-On Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DocID13266 Rev 2
I5
I4
I3
I2
I1
I0
R
BSL
R
R
ADP
EMU
SALSEL
SALSEL
CSSEL
CSSEL
WRC
I6
CLKCFG
I7
CLKCFG BUSTYP
WRC
X1
CSSEL
X1
h0
CSSEL
SALSEL
1
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h1
X1
SALSEL
RP0H 2
X
PORT0
bit
Name
X1
h2
CLKCFG
h3
X1
h4
CLKCFG
h5
X1
h6
CLKCFG
h7
X1
PORT0
bit
Nebr.
CLKCFG BUSTYP
Table 41. PORT0 Bits Latched into the Different Registers After Reset
ST10F269Z1-ST10F269Z2
System Reset
Table 41. PORT0 Bits Latched into the Different Registers After Reset (continued)
X1
X1
Internal
X1
X1
X1
X1
I0
Internal
X1
X1
X1
X1
X1
X1
I1
Internal
I2
X1
I3
X1
I4
X1
X1
I5
BTYP
I6
X1
BTYP WRCFG 3
I7
X1
-
X1
h0
X1
ALE
BYTDIS 3
CTL0 4
To Port 6 Logic
X1
BUS
ACT0 4
h1
X1
h2
-
X1
X1
Internal
Logic
h3
To Port 4 Logic
X1
BUSCO
N0
To Clock Generator
SYSCO
N
X1
h4
X1
h5
X1
h6
X1
h7
X1
PORT0
bit
Nebr.
1. Not latched from PORT0.
2. Only RP0H low byte is used and the bit-fields are latched from PORT0 high byte to RP0H low byte.
3. Indirectly depend on PORT0.
4. Bits set if EA pin is 1.
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Power Reduction Modes
19
ST10F269Z1-ST10F269Z2
Power Reduction Modes
Two different power reduction modes with different levels of power reduction have been
implemented in the ST10F269. In Idle mode only CPU is stopped, while peripheral still
operate. In Power Down mode both CPU and peripherals are stopped.
Both mode are software activated by a protected instruction and are terminated in different
ways as described in the following sections.
Note:
All external bus actions are completed before Idle or Power Down mode is entered.
However, Idle or Power Down mode is not entered if READY is enabled, but has not been
activated (driven low for negative polarity, or driven high for positive polarity) during the last
bus access.
19.1
Idle Mode
Idle mode is entered by running IDLE protected instruction. The CPU operation is stopped
and the peripherals still run.
Idle mode is terminate by any interrupt request. Whatever the interrupt is serviced or not,
the instruction following the IDLE instruction will be executed after return from interrupt
(RETI) instruction, then the CPU resumes the normal program.
Note that a PEC transfer keep the CPU in Idle mode. If the PEC transfer does not succeed,
the Idle mode is terminated. Watchdog timer must be properly programmed to avoid any
disturbance during Idle mode.
19.2
Power Down Mode
Power Down mode starts by running PWRDN protected instruction. Internal clock is
stopped, all MCU parts are on hold including the watchdog timer.
There are two different operating Power Down modes: protected mode and interruptible
mode. The internal RAM contents can be preserved through the voltage supplied via the
VDD pins. To verify RAM integrity, some dedicated patterns may be written before entering
the Power Down mode and have to be checked after Power Down is resumed.
Caution:
It is mandatory to keep VDD = +5 V ± 10% during power-down mode, because the on-chip
voltage regulator is turned in power saving mode and it delivers 2.5 V to the core logic, but it
must be supplied at nominal VDD = +5 V.
19.2.1
Protected Power Down Mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is cleared. The Protected
Power Down mode is only activated if the NMI pin is pulled low when executing PWRDN
instruction (this means that the PWRD instruction belongs to the NMI software routine). This
mode is only deactivated with an external hardware reset on RSTIN pin.
Note:
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During power down the on-chip voltage regulator automatically lowers the internal logic
supply voltage to 2.5 V, to save power and to keep internal RAM and registers contents.
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ST10F269Z1-ST10F269Z2
19.2.2
Power Reduction Modes
Interruptible Power Down Mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is set (See Section 20:
Special Function Register Overview).
The Interruptible Power Down mode is only activated if all the enabled Fast External
Interrupt pins are in their inactive level (see EXICON register description below).
This mode is deactivated with an external reset applied to RSTIN pin or with an interrupt
request applied to one of the Fast External Interrupt pins. To allow the internal PLL and
clock to stabilize, the RSTIN pin must be held low according the recommendations
described in Section 18: System Reset.
EXICON (F1C0H / E0H)
XSFR Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EXI7ES
EXI6ES
EXI5ES
EXI4ES
EXI3ES
EXI2ES
EXI1ES
EXI0ES
RW
RW
RW
RW
RW
RW
RW
RW
EXIxES(x=7...0)
External Interrupt x Edge Selection Field (x=7...0)
0 0: Fast external interrupts disabled: standard mode
EXxIN pin not taken in account for entering/exiting Power Down mode.
0 1: Interrupt on positive edge (rising)
Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as
‘high’ active level)
1 0: Interrupt on negative edge (falling)
Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’
active level)
1 1: Interrupt on any edge (rising or falling)
Always enter Power Down mode, exit if EXxIN level changed.
EXxIN inputs are normally sampled interrupt inputs. However, the Power Down mode
circuitry uses them as level-sensitive inputs.
An EXxIN (x = 3...0) Interrupt Enable bit (bit CCxIE in respective CCxIC register) need not
be set to bring the device out of Power Down mode. An external RC circuit must be
connected to RPD pin, as shown in Figure 60.
Figure 60. External R0C0 Circuit on RPD Pin For Exiting Powerdown Mode with External Interrupt
VDD
S
R0T
220kΩ minimum
RPD
+
C0
1μF Typical
To exit Power Down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be
asserted for at least 40 ns.
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Power Reduction Modes
ST10F269Z1-ST10F269Z2
This signal enables the internal oscillator and PLL circuitry, and also turns on the weak pulldown (see Figure 61).
The discharge of the external capacitor provides a delay that allows the oscillator and PLL
circuits to stabilize before the internal CPU and Peripheral clocks are enabled. When the
RPD voltage drops below the threshold voltage (about 2.5 V), the Schmitt trigger clears Q2
flip-flop, thus enabling the CPU and Peripheral clocks, and the device resumes code
execution.
If the Interrupt was enabled (bit CCxIE=’1’ in the respective CCxIC register) before entering
Power Down mode, the device executes the interrupt service routine, and then resumes
execution after the PWRDN instruction (see note below).
If the interrupt was disabled, the device executes the instruction following PWRDN
instruction, and the Interrupt Request Flag (bit CCxIR in the respective CCxIC register)
remains set until it is cleared by software.
Note:
Due to the internal pipeline, the instruction that follows the PWRDN instruction is executed
before the CPU performs a call of the interrupt service routine when exiting power-down
mode
Figure 61. Simplified Powerdown Exit Circuitry
VDD
D Q
Q1
cdQ
enter
PowerDown
stop pll
stop oscillator
VDD
Pull-up
RPD
Weak Pull-down
(~ 200μA)
external
interrupt
reset
VDD
CPU and Peripherals clocks
D Q
Q2
System clock
Q
cd
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ST10F269Z1-ST10F269Z2
Power Reduction Modes
Figure 62. Powerdown Exit Sequence When Using an External Interrupt (PLL x 2)
XTAL1
CPU clk
Internal
Powerdown
signal
External
Interrupt
RPD
ExitPwrd
(internal)
~ 2.5 V
delay for oscillator/pll
stabilization
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Special Function Register Overview
20
ST10F269Z1-ST10F269Z2
Special Function Register Overview
The following table lists all SFRs which are implemented in the ST10F269 in alphabetical
order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within
the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical
Address”.
A SFR can be specified by its individual mnemonic name. Depending on the selected
addressing mode, a SFR can be accessed via its physical address (using the Data Page
Pointers), or via its short 8-bit address (without using the Data Page Pointers).
The reset value is defined as following:
•
X means the full nibble is not defined at reset.
•
x means some bits of the nibble are not defined at reset.
Table 42. Special Function Registers Listed by Name
Name
Physical
address
8-bit
address
ADCICb
FF98h
CCh
ADCONb
ADDAT
ADDAT2
ADDRSEL1
ADDRSEL2
ADDRSEL3
ADDRSEL4
ADEICb
BUSCON0b
BUSCON1b
BUSCON2b
BUSCON3b
BUSCON4b
CAPREL
CC0
CC0ICb
CC1
CC1ICb
CC2
CC2ICb
CC3
CC3ICb
CC4
CC4ICb
CC5
CC5ICb
CC6
CC6ICb
FFA0h
FEA0h
F0A0hE
FE18h
FE1Ah
FE1Ch
FE1Eh
FF9Ah
FF0Ch
FF14h
FF16h
FF18h
FF1Ah
FE4Ah
FE80h
FF78h
FE82h
FF7Ah
FE84h
FF7Ch
FE86h
FF7Eh
FE88h
FF80h
FE8Ah
FF82h
FE8Ch
FF84h
D0h
50h
50h
0Ch
0Dh
0Eh
0Fh
CDh
86h
8Ah
8Bh
8Ch
8Dh
25h
40h
BCh
41h
BDh
42h
BEh
43h
BFh
44h
C0h
45h
C1h
46h
C2h
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Description
A/D Converter end of Conversion Interrupt Control
Register
A/D Converter Control Register
A/D Converter Result Register
A/D Converter 2 Result Register
Address Select Register 1
Address Select Register 2
Address Select Register 3
Address Select Register 4
A/D Converter Overrun Error Interrupt Control Register
Bus Configuration Register 0
Bus Configuration Register 1
Bus Configuration Register 2
Bus Configuration Register 3
Bus Configuration Register 4
GPT2 Capture/Reload Register
CAPCOM Register 0
CAPCOM Register 0 Interrupt Control Register
CAPCOM Register 1
CAPCOM Register 1 Interrupt Control Register
CAPCOM Register 2
CAPCOM Register 2 Interrupt Control Register
CAPCOM Register 3
CAPCOM Register 3 Interrupt Control Register
CAPCOM Register 4
CAPCOM Register 4 Interrupt Control Register
CAPCOM Register 5
CAPCOM Register 5 Interrupt Control Register
CAPCOM Register 6
CAPCOM Register 6 Interrupt Control Register
DocID13266 Rev 2
Reset
value
- - 00h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0xx0h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
ST10F269Z1-ST10F269Z2
Special Function Register Overview
Table 42. Special Function Registers Listed by Name (continued)
Name
CC7
CC7ICb
CC8
CC8ICb
CC9
CC9ICb
CC10
CC10ICb
CC11
CC11ICb
CC12
CC12ICb
CC13
CC13ICb
CC14
CC14ICb
CC15
CC15ICb
CC16
CC16ICb
CC17
CC17ICb
CC18
CC18ICb
CC19
CC19ICb
CC20
CC20ICb
CC21
CC21ICb
CC22
CC22ICb
CC23
CC23ICb
CC24
CC24ICb
CC25
CC25ICb
CC26
CC26ICb
CC27
CC27ICb
CC28
CC28ICb
CC29
Physical
address
FE8Eh
FF86h
FE90h
FF88h
FE92h
FF8Ah
FE94h
FF8Ch
FE96h
FF8Eh
FE98h
FF90h
FE9Ah
FF92h
FE9Ch
FF94h
FE9Eh
FF96h
FE60h
F160hE
FE62h
F162hE
FE64h
F164hE
FE66h
F166hE
FE68h
F168hE
FE6Ah
F16AhE
FE6Ch
F16ChE
FE6Eh
F16EhE
FE70h
F170hE
FE72h
F172hE
FE74h
F174hE
FE76h
F176hE
FE78h
F178hE
FE7Ah
8-bit
address
47h
C3h
48h
C4h
49h
C5h
4Ah
C6h
4Bh
C7h
4Ch
C8h
4Dh
C9h
4Eh
CAh
4Fh
CBh
30h
B0h
31h
B1h
32h
B2h
33h
B3h
34h
B4h
35h
B5h
36h
B6h
37h
B7h
38h
B8h
39h
B9h
3Ah
BAh
3Bh
BBh
3Ch
BCh
3Dh
Description
CAPCOM Register 7
CAPCOM Register 7 Interrupt Control Register
CAPCOM Register 8
CAPCOM Register 8 Interrupt Control Register
CAPCOM Register 9
CAPCOM Register 9 Interrupt Control Register
CAPCOM Register 10
CAPCOM Register 10 Interrupt Control Register
CAPCOM Register 11
CAPCOM Register 11 Interrupt Control Register
CAPCOM Register 12
CAPCOM Register 12 Interrupt Control Register
CAPCOM Register 13
CAPCOM Register 13 Interrupt Control Register
CAPCOM Register 14
CAPCOM Register 14 Interrupt Control Register
CAPCOM Register 15
CAPCOM Register 15 Interrupt Control Register
CAPCOM Register 16
CAPCOM Register 16 Interrupt Control Register
CAPCOM Register 17
CAPCOM Register 17 Interrupt Control Register
CAPCOM Register 18
CAPCOM Register 18 Interrupt Control Register
CAPCOM Register 19
CAPCOM Register 19 Interrupt Control Register
CAPCOM Register 20
CAPCOM Register 20 Interrupt Control Register
CAPCOM Register 21
CAPCOM Register 21 Interrupt Control Register
CAPCOM Register 22
CAPCOM Register 22 Interrupt Control Register
CAPCOM Register 23
CAPCOM Register 23 Interrupt Control Register
CAPCOM Register 24
CAPCOM Register 24 Interrupt Control Register
CAPCOM Register 25
CAPCOM Register 25 Interrupt Control Register
CAPCOM Register 26
CAPCOM Register 26 Interrupt Control Register
CAPCOM Register 27
CAPCOM Register 27 Interrupt Control Register
CAPCOM Register 28
CAPCOM Register 28 Interrupt Control Register
CAPCOM Register 29
DocID13266 Rev 2
Reset
value
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
147/206
205
Special Function Register Overview
ST10F269Z1-ST10F269Z2
Table 42. Special Function Registers Listed by Name (continued)
Name
CC29ICb
CC30
CC30ICb
CC31
CC31ICb
CCM0b
CCM1b
CCM2b
CCM3b
CCM4b
CCM5b
CCM6b
CCM7b
CP
CRICb
CSP
DP0Lb
DP0Hb
DP1Lb
DP1Hb
DP2b
DP3b
DP4b
DP6b
DP7b
DP8b
DPP0
DPP1
DPP2
DPP3
EXICONb
EXISELb
IDCHIP
IDMANUF
IDMEM
IDPROG
IDX0b
IDX1b
MAH
MAL
MCWb
MDCb
MDH
MDL
MRWb
148/206
Physical
address
F184hE
FE7Ch
F18ChE
FE7Eh
F194hE
FF52h
FF54h
FF56h
FF58h
FF22h
FF24h
FF26h
FF28h
FE10h
FF6Ah
FE08h
F100hE
F102hE
F104hE
F106hE
FFC2h
FFC6h
FFCAh
FFCEh
FFD2h
FFD6h
FE00h
FE02h
FE04h
FE06h
F1C0hE
F1DAhE
F07ChE
F07EhE
F07AhE
F078hE
FF08h
FF0Ah
FE5Eh
FE5Ch
FFDCh
FF0Eh
FE0Ch
FE0Eh
FFDAh
8-bit
address
C2h
3Eh
C6h
3Fh
CAh
A9h
AAh
ABh
ACh
91h
92h
93h
94h
08h
B5h
04h
80h
81h
82h
83h
E1h
E3h
E5h
E7h
E9h
EBh
00h
01h
02h
03h
E0h
EDh
3Eh
3Fh
3Dh
3Ch
84h
85h
2Fh
2Eh
EEh
87h
06h
07h
EDh
Description
CAPCOM Register 29 Interrupt Control Register
CAPCOM Register 30
CAPCOM Register 30 Interrupt Control Register
CAPCOM Register 31
CAPCOM Register 31 Interrupt Control Register
CAPCOM Mode Control Register 0
CAPCOM Mode Control Register 1
CAPCOM Mode Control Register 2
CAPCOM Mode Control Register 3
CAPCOM Mode Control Register 4
CAPCOM Mode Control Register 5
CAPCOM Mode Control Register 6
CAPCOM Mode Control Register 7
CPU Context Pointer Register
GPT2 CAPREL Interrupt Control Register
CPU Code Segment Pointer Register (read only)
P0L Direction Control Register
P0h Direction Control Register
P1L Direction Control Register
P1h Direction Control Register
Port 2 Direction Control Register
Port 3 Direction Control Register
Port 4 Direction Control Register
Port 6 Direction Control Register
Port 7 Direction Control Register
Port 8 Direction Control Register
CPU Data Page Pointer 0 Register (10-bit)
CPU Data Page Pointer 1 Register (10-bit)
CPU Data Page Pointer 2 Register (10-bit)
CPU Data Page Pointer 3 Register (10-bit)
External Interrupt Control Register
External Interrupt Source Selection Register
Device Identifier Register (n is the device revision)
Manufacturer Identifier Register
On-chip Memory Identifier Register
Programming Voltage Identifier Register
MAC Unit Address Pointer 0
MAC Unit Address Pointer 1
MAC Unit Accumulator - High Word
MAC Unit Accumulator - Low Word
MAC Unit Control Word
CPU Multiply Divide Control Register
CPU Multiply Divide Register – High Word
CPU Multiply Divide Register – Low Word
MAC Unit Repeat Word
DocID13266 Rev 2
Reset
value
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
FC00h
- - 00h
0000h
- - 00h
- - 00h
- - 00h
- - 00h
0000h
0000h
00h
00h
00h
00h
0000h
0001h
0002h
0003h
0000h
0000h
10Dnh
0401h
3040h
0040h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
ST10F269Z1-ST10F269Z2
Special Function Register Overview
Table 42. Special Function Registers Listed by Name (continued)
Name
MSWb
ODP2b
ODP3b
ODP4b
ODP6b
ODP7b
ODP8b
ONESb
P0Lb
P0Hb
P1Lb
P1Hb
P2b
P3b
P4b
P5b
P6b
P7b
P8b
P5DIDISb
POCON0L
POCON0H
POCON1L
POCON1H
POCON2
POCON3
POCON4
POCON6
POCON7
POCON8
POCON20
PECC0
PECC1
PECC2
PECC3
PECC4
PECC5
PECC6
PECC7
PICONb
PP0
PP1
PP2
PP3
PSWb
Physical
address
FFDEh
F1C2hE
F1C6hE
F1CAhE
F1CEhE
F1D2hE
F1D6hE
FF1Eh
FF00h
FF02h
FF04h
FF06h
FFC0h
FFC4h
FFC8h
FFA2h
FFCCh
FFD0h
FFD4h
FFA4h
F080hE
F082hE
F084hE
F086hE
F088hE
F08AhE
F08ChE
F08EhE
F090hE
F092hE
F0AAhE
FEC0h
FEC2h
FEC4h
FEC6h
FEC8h
FECAh
FECCh
FECEh
F1C4hE
F038hE
F03AhE
F03ChE
F03EhE
FF10h
8-bit
address
EFh
E1h
E3h
E5h
E7h
E9h
EBh
8Fh
80h
81h
82h
83h
E0h
E2h
E4h
D1h
E6h
E8h
EAh
D2h
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
55h
60h
61h
62h
63h
64h
65h
66h
67h
E2h
1Ch
1Dh
1Eh
1Fh
88h
Description
MAC Unit Status Word
Port 2 Open Drain Control Register
Port 3 Open Drain Control Register
Port 4 Open Drain Control Register
Port 6 Open Drain Control Register
Port 7 Open Drain Control Register
Port 8 Open Drain Control Register
Constant Value 1’s Register (read only)
PORT0 Low Register (Lower half of PORT0)
PORT0 High Register (Upper half of PORT0)
PORT1 Low Register (Lower half of PORT1)
PORT1 High Register (Upper half of PORT1)
Port 2 Register
Port 3 Register
Port 4 Register (8-bit)
Port 5 Register (read only)
Port 6 Register (8-bit)
Port 7 Register (8-bit)
Port 8 Register (8-bit)
Port 5 Digital Disable Register
PORT0 Low Outpout Control Register (8-bit)
PORT0 High Output Control Register (8-bit)
PORT1 Low Output Control Register (8-bit)
PORT1 High Output Control Register (8-bit)
Port2 Output Control Register
Port3 Output Control Register
Port4 Output Control Register (8-bit)
Port6 Output Control Register (8-bit)
Port7 Output Control Register (8-bit)
Port8 Output Control Register (8-bit)
ALE, RD, WR Output Control Register (8-bit)
PEC Channel 0 Control Register
PEC Channel 1 Control Register
PEC Channel 2 Control Register
PEC Channel 3 Control Register
PEC Channel 4 Control Register
PEC Channel 5 Control Register
PEC Channel 6 Control Register
PEC Channel 7 Control Register
Port Input Threshold Control Register
PWM Module Period Register 0
PWM Module Period Register 1
PWM Module Period Register 2
PWM Module Period Register 3
CPU Program Status Word
DocID13266 Rev 2
Reset
value
0200h
0000h
0000h
- - 00h
- - 00h
- - 00h
- - 00h
FFFFh
- - 00h
- - 00h
- - 00h
- - 00h
0000h
0000h
00h
XXXXh
- - 00h
- - 00h
- - 00h
0000h
- - 00h
- - 00h
- - 00h
- - 00h
0000h
0000h
- - 00h
- - 00h
- - 00h
- - 00h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0000h
0000h
0000h
0000h
0000h
149/206
205
Special Function Register Overview
ST10F269Z1-ST10F269Z2
Table 42. Special Function Registers Listed by Name (continued)
Name
Physical
address
8-bit
address
PT0
PT1
PT2
PT3
PW0
PW1
PW2
PW3
PWMCON0b
PWMCON1b
PWMICb
QR0
QR1
QX0
QX1
RP0Hb
S0BG
S0CONb
S0EICb
S0RBUF
S0RICb
F030hE
F032hE
F034hE
F036hE
FE30h
FE32h
FE34h
FE36h
FF30h
FF32h
F17EhE
F004hE
F006hE
F000hE
F002hE
F108hE
FEB4h
FFB0h
FF70h
FEB2h
FF6Eh
18h
19h
1Ah
1Bh
18h
19h
1Ah
1Bh
98h
99h
BFh
02h
03h
00h
01h
84h
5Ah
D8h
B8h
59h
B7h
S0TBICb
F19ChE
CEh
S0TBUF
S0TICb
SP
SSCBR
SSCCONb
SSCEICb
SSCRB
SSCRICb
SSCTB
SSCTICb
STKOV
STKUN
SYSCONb
T0
T01CONb
T0ICb
T0REL
T1
T1ICb
T1REL
T2
T2CONb
FEB0h
FF6Ch
FE12h
F0B4hE
FFB2h
FF76h
F0B2hE
FF74h
F0B0hE
FF72h
FE14h
FE16h
FF12h
FE50h
FF50h
FF9Ch
FE54h
FE52h
FF9Eh
FE56h
FE40h
FF40h
58h
B6h
09h
5Ah
D9h
BBh
59h
BAh
58h
B9h
0Ah
0Bh
89h
28h
A8h
CEh
2Ah
29h
CFh
2Bh
20h
A0h
150/206
Description
PWM Module Up/Down Counter 0
PWM Module Up/Down Counter 1
PWM Module Up/Down Counter 2
PWM Module Up/Down Counter 3
PWM Module Pulse Width Register 0
PWM Module Pulse Width Register 1
PWM Module Pulse Width Register 2
PWM Module Pulse Width Register 3
PWM Module Control Register 0
PWM Module Control Register 1
PWM Module Interrupt Control Register
MAC Unit Offset Register QR0
MAC Unit Offset Register QR1
MAC Unit Offset Register QX0
MAC Unit Offset Register QX1
System Start-up Configuration Register (read only)
Serial Channel 0 Baud Rate Generator Reload Register
Serial Channel 0 Control Register
Serial Channel 0 Error Interrupt Control Register
Serial Channel 0 Receive Buffer Register (read only)
Serial Channel 0 Receive Interrupt Control Register
Serial Channel 0 Transmit Buffer Interrupt Control
Register
Serial Channel 0 Transmit Buffer Register (write only)
Serial Channel 0 Transmit Interrupt Control Register
CPU System Stack Pointer Register
SSC Baud Rate Register
SSC Control Register
SSC Error Interrupt Control Register
SSC Receive Buffer (read only)
SSC Receive Interrupt Control Register
SSC Transmit Buffer (write only)
SSC Transmit Interrupt Control Register
CPU Stack Overflow Pointer Register
CPU Stack Underflow Pointer Register
CPU System Configuration Register
CAPCOM Timer 0 Register
CAPCOM Timer 0 and Timer 1 Control Register
CAPCOM Timer 0 Interrupt Control Register
CAPCOM Timer 0 Reload Register
CAPCOM Timer 1 Register
CAPCOM Timer 1 Interrupt Control Register
CAPCOM Timer 1 Reload Register
GPT1 Timer 2 Register
GPT1 Timer 2 Control Register
DocID13266 Rev 2
Reset
value
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0000h
0000h
0000h
0000h
- - XXh
0000h
0000h
- - 00h
- - XXh
- - 00h
- - 00h
0000h
- - 00h
FC00h
0000h
0000h
- - 00h
XXXXh
- - 00h
0000h
- - 00h
FA00h
FC00h
0xx0h 1
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
0000h
ST10F269Z1-ST10F269Z2
Special Function Register Overview
Table 42. Special Function Registers Listed by Name (continued)
Physical
address
Name
T2ICb
T3
T3CONb
T3ICb
T4
T4CONb
T4ICb
T5
T5CONb
T5ICb
T6
T6CONb
T6ICb
T7
T78CONb
T7ICb
T7REL
T8
T8ICb
T8REL
TFRb
WDT
WDTCONb
XP0ICb
XP1ICb
XP2ICb
XP3ICb
XPERCON
ZEROSb
FF60h
FE42h
FF42h
FF62h
FE44h
FF44h
FF64h
FE46h
FF46h
FF66h
FE48h
FF48h
FF68h
F050hE
FF20h
F17AhE
F054hE
F052hE
F17ChE
F056hE
FFACh
FEAEh
FFAEh
F186hE
F18EhE
F196hE
F19EhE
F024hE
FF1Ch
8-bit
address
B0h
21h
A1h
B1h
22h
A2h
B2h
23h
A3h
B3h
24h
A4h
B4h
28h
90h
BEh
2Ah
29h
BFh
2Bh
D6h
57h
D7h
C3h
C7h
CBh
CFh
12h
8Eh
Description
GPT1 Timer 2 Interrupt Control Register
GPT1 Timer 3 Register
GPT1 Timer 3 Control Register
GPT1 Timer 3 Interrupt Control Register
GPT1 Timer 4 Register
GPT1 Timer 4 Control Register
GPT1 Timer 4 Interrupt Control Register
GPT2 Timer 5 Register
GPT2 Timer 5 Control Register
GPT2 Timer 5 Interrupt Control Register
GPT2 Timer 6 Register
GPT2 Timer 6 Control Register
GPT2 Timer 6 Interrupt Control Register
CAPCOM Timer 7 Register
CAPCOM Timer 7 and 8 Control Register
CAPCOM Timer 7 Interrupt Control Register
CAPCOM Timer 7 Reload Register
CAPCOM Timer 8 Register
CAPCOM Timer 8 Interrupt Control Register
CAPCOM Timer 8 Reload Register
Trap Flag Register
Watchdog Timer Register (read only)
Watchdog Timer Control Register
CAN1 Module Interrupt Control Register
CAN2 Module Interrupt Control Register
Flash ready/busy interrupt control register
PLL unlock Interrupt Control Register
XPER Configuration Register
Constant Value 0’s Register (read only)
Reset
value
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
0000h
00xxh 2
- - 00h 3
- - 00h 3
- - 00h 3
- - 00h 3
- - 05h
0000h
1. The system configuration is selected during reset.
2. Bit WDTR indicates a watchdog timer triggered reset.
3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus peripherals. Some software
controlled interrupt requests may be generated by setting the XPnIR bits (of XPnIC register) of the unused X-peripheral
nodes.
20.1
Identification Registers
The ST10F269 has four Identification registers, mapped in ESFR space. These registers
contain:
Note:
•
A manufacturer identifier,
•
A chip identifier, with its revision,
•
A internal memory and size identifier and programming voltage description.
256K and 128K versions of ST10F269 have the same IDMEM corresponding to 256K.
DocID13266 Rev 2
151/206
205
Special Function Register Overview
ST10F269Z1-ST10F269Z2
Both versions are based on the same device with the only difference that the two upper
banks of Flash are not tested on 128K versions. Therefore, there is no way to detect by
software if a device is a 128K version or a 256K version.
IDMANUF (F07Eh / 3Fh)1
ESFR Reset Value: 0401h
15
14
13
12
11
10
9
8
7
6
5
MANUF
4
3
2
1
0
0
0
0
0
1
R
MANUF
Manufacturer Identifier - 020h: STMicroelectronics Manufacturer (JTAG worldwide
normalization).
IDCHIP (F07Ch / 3Eh)1
ESFR Reset Value: 10DXh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
1
0
2
1
0
CHIPID
REVID
R
R
REVID
Device Revision Identifier
CHIPID
Device Identifier - 10Dh: ST10F269 identifier.
IDMEM (F07Ah / 3Dh)1
ESFR Reset Value: 3040
15
14
13
12
11
10
9
8
7
6
MEMTYP
MEMSIZE
R
R
5
4
3
MEMSIZE
Internal Memory Size is calculated using the following formula:
Size = 4 x [MEMSIZE] (in Kbyte) - 040h for ST10F269 (256 Kbyte)
MEMTYP
Internal Memory Type - 3h for ST10F269 (Flash memory).
IDPROG (F078h / 3Ch)1
ESFR Reset Value: 0040h
15
14
13
12
11
10
9
8
6
5
4
PROGVDD
R
R
3
PROGVDD
Programming VDD Voltage
VDD voltage when programming EPROM or FLASH devices is calculated using the
following formula: VDD = 20 x [PROGVDD] / 256 (volts) - 40h for ST10F269 (5V).
PROGVPP
Programming VPP Voltage (no need of external VPP) - 00h
1. All identification words are read only registers.
152/206
7
PROGVPP
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
20.2
Special Function Register Overview
System Configuration Registers
The ST10F269 has registers used for different configuration of the overall system. These
registers are described below.
SYSCON (FF12H / 89H)
SFR Reset Value: 0xx0H
15 14 13
STKSZ
12
11
10
9
8
7
6
5
PWD
ROMS1 SGTDIS ROMEN BYTDIS CLKEN WRCFG CSCFG
CFG
RW
RW
RW
RW1
RW1
RW
RW1
RW
RW
4
OWD
DIS
RW
3
2
1
0
BDR
XPERXPEN VISIBLE
STEN
SHARE
RW
RW
RW
RW
1. These bit are set directly or indirectly according to PORT0 and EA pin configuration during reset sequence.
2. Register SYSCON cannot be changed after execution of the EINIT instruction.
XPER-SHARE XBUS Peripheral Share Mode Control
‘0’: External accesses to XBUS peripherals are disabled
‘1’: XBUS peripherals are accessible via the external bus during hold mode
VISIBLE
Visible Mode Control
‘0’: Accesses to XBUS peripherals are done internally
‘1’: XBUS peripheral accesses are made visible on the external pins
XPEN
XBUS Peripheral Enable bit
‘0’: Accesses to the on-chip X-Peripherals and XRAM are disabled
‘1’: The on-chip X-Peripherals are enabled.
BDRSTEN
Bidirectional Reset Enable
‘0’: RSTIN pin is an input pin only. (SW Reset or WDT Reset have no effect on this
pin)
‘1’: RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during
reset sequence.
OWDDIS
Oscillator Watchdog Disable Control
‘0’: Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors
XTAL1 activity. If there is no activity on XTAL1 for at least 1 ms, the CPU clock is
switched automatically to PLL’s base frequency (from 2 to 10MHz).
‘1’: OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by
XTAL1 signal. The PLL is turned off to reduce power supply current.
PWDCFG
Power Down Mode Configuration Control
‘0’: Power Down Mode can only be entered during PWRDN instruction execution if
NMI pin is low, otherwise the instruction has no effect. Exit power down only with
reset.
‘1’: Power Down Mode can only be entered during PWRDN instruction execution if
all enabled fast external interrupt EXxIN pins are in their inactive level. Exiting this
mode can be done by asserting one enabled EXxIN pin or with external reset.
CSCFG
Chip Select Configuration Control
‘0’: Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE
‘1’: Unlatched Chip Select lines: CSx change with rising edge of ALE.
DocID13266 Rev 2
153/206
205
Special Function Register Overview
WRCFG
ST10F269Z1-ST10F269Z2
Write Configuration Control (Inverted copy of bit WRC of RP0H)
‘0’: Pins WR and BHE retain their normal function
‘1’: Pin WR acts as WRL, pin BHE acts as WRH.
CLKEN
System Clock Output Enable (CLKOUT)
‘0’: CLKOUT disabled: pin may be used for general purpose I/O
‘1’: CLKOUT enabled: pin outputs the system clock signal.
BYTDIS
Disable/Enable Control for Pin BHE (Set according to data bus width)
‘0’: Pin BHE enabled
‘1’: Pin BHE disabled, pin may be used for general purpose I/O.
ROMEN
Internal Memory Enable (Set according to pin EA during reset)
‘0’: Internal Memory disabled: accesses to the Memory area use the external bus
‘1’: Internal Memory enabled.
SGTDIS
Segmentation Disable/Enable Control
‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit)
‘1’: Segmentation disabled (Only IP is saved/restored).
ROMS1
Internal Memory Mapping
‘0’: Internal Memory area mapped to segment 0 (00’0000H...00’7FFFH)
‘1’: Internal Memory area mapped to segment 1 (01’0000H...01’7FFFH).
STKSZ
System Stack Size
Selects the size of the system stack (in the internal RAM) from 32 to 1024 words.
BUSCON0 (FF0CH / 86H)
SFR Reset Value: 0xx0H
15
CSWEN0
RW
14
13
12
11
CSREN0 RDYPOL0 RDYEN0
RW
RW
-
10
RW2
RW
9
BUS ACT0 ALE CTL0
8
7
-
BTYP
RW2
6
RW1
5
4
3
MTTC0 RWDC0
RW
RW
5
4
2
1
0
MCTC
RW
BUSCON1 (FF14H / 8AH)
SFR Reset Value: 0000H
15
CSWEN1
RW
14
13
12
CSREN1 RDYPOL1 RDYEN1
RW
RW
11
10
9
8
7
-
BUSACT1
ALECTL1
-
BTYP
RW
RW
RW
6
RW
3
MTTC1 RWDC1
RW
RW
5
4
2
1
0
MCTC
RW
BUSCON2 (FF16H / 8BH)
SFR Reset Value: 0000H
15
CSWEN2
RW
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14
13
12
CSREN2 RDYPOL2 RDYEN2
RW
RW
RW
11
10
9
8
7
-
BUSACT2
ALECTL2
-
BTYP
RW
RW
DocID13266 Rev 2
6
RW
MTTC2 RWDC2
RW
RW
3
2
1
MCTC
RW
0
ST10F269Z1-ST10F269Z2
Special Function Register Overview
BUSCON3 (FF18H / 8CH)
SFR Reset Value: 0000H
15
CSWEN3
14
13
12
CSREN3 RDYPOL3 RDYEN3
RW
RW
RW
11
10
9
8
7
-
BUSACT3
ALECTL3
-
BTYP
RW
RW
RW
6
RW
5
4
3
MTTC3 RWDC3
RW
RW
5
4
2
1
0
MCTC
RW
BUSCON4 (FF1AH / 8DH)
SFR Reset Value: 0000H
15
CSWEN4
14
13
12
CSREN4 RDYPOL4 RDYEN4
RW
RW
RW
11
10
9
8
7
-
BUSACT4
ALECTL4
-
BTYP
RW
RW
RW
6
RW
MTTC4 RWDC4
RW
3
2
1
0
MCTC
RW
RW
1. BTYP (bit 6 and 7) are set according to the configuration of the bit l6 and l7 of PORT0 latched at the end of
the reset sequence.
2. BUSCON0 is initialized with 0000h, if EA pin is high during reset. If EA pin is low during reset, bit BUSACT0
and ALECTRL0 are set (’1’) and bit field BTYP is loaded with the bus configuration selected via PORT0.
MCTC
Memory Cycle Time Control (Number of memory cycle time
wait states)
0 0 0 0: 15 wait states (Nber = 15 - [MCTC])
...
1 1 1 1: No wait state
RWDCx
Read/Write Delay Control for BUSCONx
‘0’: With read/write delay: activate command 1 TCL after falling
edge of ALE
‘1’: No read/write delay: activate command with falling edge of ALE
MTTCx
Memory Tristate Time Control
‘0’: 1 wait state
‘1’: No wait state
BTYP
External Bus Configuration
0 0: 8-bit Demultiplexed Bus
0 1: 8-bit Multiplexed Bus
1 0: 16-bit Demultiplexed Bus
1 1: 16-bit Multiplexed Bus
Note: For BUSCON0, BTYP bit-field is defined via PORT0 during
reset.
ALECTLx
ALE Lengthening Control
‘0’: Normal ALE signal
‘1’: Lengthened ALE signal
BUSACTx
Bus Active Control
‘0’: External bus disabled
‘1’: External bus enabled (within the respective address window,
see ADDRSEL)
RDYENx
READY Input Enable
‘0’: External bus cycle is controlled by bit field MCTC only
‘1’: External bus cycle is controlled by the READY input signal
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Special Function Register Overview
RDYPOLx
ST10F269Z1-ST10F269Z2
Ready Active Level Control
‘0’: Active level on the READY pin is low, bus cycle terminates with
a ‘0’ on READY pin,
‘1’: Active level on the READY pin is high, bus cycle terminates
with a ‘1’ on READY pin.
CSRENx
Read Chip Select Enable
‘0’: The CS signal is independent of the read command (RD)
‘1’: The CS signal is generated for the duration of the read
command
CSWENx
Write Chip Select Enable
‘0’: The CS signal is independent of the write command
(WR,WRL,WRH)
‘1’: The CS signal is generated for the duration of the write
command
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Special Function Register Overview
RP0H (F108h / 84h)
ESFR Reset Value: --XXH
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
CLKSEL
SALSEL
CSSEL
WRC
R1-2
R2
R2
R2
Write Configuration Control
WRC 2
‘0’: Pin WR acts as WRL, pin BHE acts as WRH
‘1’: Pins WR and BHE retain their normal function
CSSEL
Chip Select Line Selection (Number of active CS outputs)
2
0 0: 3 CS lines: CS2...CS0
0 1: 2 CS lines: CS1...CS0
1 0: No CS line at all
1 1: 5 CS lines: CS4...CS0 (Default without pull-downs)
Segment Address Line Selection (Number of active segment address
outputs)
SALSEL 2
0 0: 4-bit segment address: A19...A16
0 1: No segment address lines at all
1 0: 8-bit segment address: A23...A16
1 1: 2-bit segment address: A17...A16 (Default without pull-downs)
CLKSEL
System Clock Selection
1-2
000: fCPU = 2.5 x fOSC
001: fCPU = 0.5 x fOSC
010: fCPU = 1.5 x fOSC
011: fCPU = fOSC
100: fCPU = 5 x fOSC
101: fCPU = 2 x fOSC
110: fCPU = 3 x fOSC
111: fCPU = 4 x fOSC
1. RP0H.7 to RP0H.5 bits are loaded only during a long hardware reset. As pull-up resistors are active on each
Port P0H pins during reset, RP0H default value is "FFh".
2. These bits are set according to Port 0 configuration during any reset sequence.
3. RP0H is a read only register.
EXICON (F1C0H / E0H)
ESFR Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EXI7ES
EXI6ES
EXI5ES
EXI4ES
EXI3ES
EXI2ES
EXI1ES
EXI0ES
RW
RW
RW
RW
RW
RW
RW
RW
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Special Function Register Overview
ST10F269Z1-ST10F269Z2
EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0)
0 0:
Fast external interrupts disabled: standard mode
EXxIN pin not taken in account for entering/exiting Power Down mode.
0 1:
Interrupt on positive edge (rising)
Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’
active level)
1 0:
Interrupt on negative edge (falling)
Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’
active level)
1 1:
Interrupt on any edge (rising or falling)
Always enter Power Down mode, exit if EXxIN level changed.
EXISEL (F1DAH / EDH)
ESFR Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EXI7SS
EXI6SS
EXI5SS
EXI4SS
EXI3SS
EXI2SS
EXI1SS
EXI0SS
RW
RW
RW
RW
RW
RW
RW
RW
EXIxSS
External Interrupt x Source Selection (x=7...0)
‘00’: Input from associated Port 2 pin.
‘01’: Input from “alternate source”.
‘10’: Input from Port 2 pin ORed with “alternate source”.
‘11’:
Input from Port 2 pin ANDed with “alternate source”.
EXIxSS
Port 2 pin
Alternate Source
0
P2.8
CAN1_RxD
1
P2.9
CAN2_RxD
2
P2.10
RTCSI
3
P2.11
RTCAI
4...7
P2.12...15
Not used (zero)
XP3IC (F19EH / CFH)1
ESFR Reset Value: --00H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
XP3IR XP3IE
RW
4
3
2
1
0
XP3ILVL
GLVL
RW
RW
RW
1. XP3IC register has the same bit field as xxIC interrupt registers
xxIC (yyyyh / zzh)
SFR Area Reset Value: --00h
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15
14
13
12
11
10
9
8
7
6
-
-
-
-
-
-
-
-
xxIR
xxIE
ILVL
GLVL
RW
RW
RW
RW
DocID13266 Rev 2
5
4
3
2
1
0
ST10F269Z1-ST10F269Z2
Special Function Register Overview
GLVL
Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
ILVL
Interrupt Priority Level
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
xxIE
Interrupt Enable Control Bit (individually enables/disables a specific source)
‘0’: Interrupt Request is disabled
‘1’: Interrupt Request is enabled
xxIR
Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
XPERCON (F024H / 12H)
ESFR Reset Value: --05h
15
14
13
12
11
10
9
8
7
6
5
-
-
-
-
-
-
-
-
-
-
-
4
2
RTCEN XRAM2EN XRAM1EN
RW
CAN1EN
3
RW
RW
1
0
CAN2EN
CAN1EN
RW
RW
CAN1 Enable Bit
‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and
P4.6 pins can be used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is
only directed to external memory if CAN2EN is also ‘0’.
‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed.
CAN2EN
CAN2 Enable Bit
‘0’: Accesses to the on-chip CAN2 XPeripheral and its functions are disabled. P4.4 and
P4.7 pins can be used as general purpose I/Os. Address range 00’EE00h-00’EEFFh is
only directed to external memory if CAN1EN is also ‘0’.
‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed.
XRAM1E
N
XRAM1 Enable Bit
‘0’: Accesses to external memory within space 00’E000h to 00’E7FFh. The 2K Bytes of
internal XRAM1 are disabled.
’1’: Accesses to the internal 2K Bytes of XRAM1.
XRAM2E
N
XRAM2 Enable Bit
‘0’: Accesses to the external memory within space 00’C000h to 00’DFFFh. The 8K Bytes
of internal XRAM2 are disabled.
’1’: Accesses to the internal 8K Bytes of XRAM2.
RTCEN
RTC Enable Bit
’0’: Accesses to the on-chip Real Time Clock are disabled, external access performed.
Address range 00’EC00h-00’ECFFh is only directed to external memory if CAN1EN and
CAN2EN are ’0’ also
’1’: The on-chip Real Time Clock is enabled and can be accessed.
When both CAN are disabled via XPERCON setting, then any access in the address range
00’EE00h - 00’EFFFh will be directed to external memory interface, using the BUSCONx
register corresponding to address matching ADDRSELx register. P4.4 and P4.7 can be
used as General Purpose I/O when CAN2 is not enabled, and P4.5 and P4.6 can be used
as General Purpose I/O when CAN1 is not enabled.
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Special Function Register Overview
ST10F269Z1-ST10F269Z2
The default XPER selection after Reset is identical to XBUS configuration of ST10C167:
XCAN1 is enabled, XCAN2 is disabled, XRAM1 (2-Kbyte compatible XRAM) is enabled,
XRAM2 (new 8-Kbyte XRAM) is disabled.
Register XPERCON cannot be changed after the global enabling of XPeripherals, i.e. after
setting of bit XPEN in SYSCON register.
In EMUlation mode, all the XPERipherals are enabled (XPERCON bit are all set).
When the Real Time Clock is disabled (RTCEN = 0), the clock oscillator is switch off if ST10
enters in power-down mode. Otherwise, when the Real Time Clock is enabled, the bit
RTCOFF of the RTCCON register allows to choose the power-down mode of the clock
oscillator.
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Electrical Characteristics
21
Electrical Characteristics
21.1
Absolute Maximum Ratings
Table 43. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
-0.5, +6.5
V
-0.5, (VDD +0.5)
V
-0.3, (VDD +0.3)
V
(1)
Voltage on VDD pins with respect to ground
VDD
Voltage on any pin with respect to ground
VIO
(1)
Voltage on VAREF pin with respect to ground
VAREF
(1)
(1)
IOV
Input Current on any pin during overload condition
ITOV
Absolute Sum of all input currents during overload condition(1)
-10, +10
mA
|100|
mA
Ptot
Power Dissipation(1)
1.5
W
TA
Ambient Temperature under bias
-40, +125
°C
Temperature(1)
Tstg
-65, +150
°C
Storage
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS) the voltage on pins with respect
to ground (VSS) must not exceed the values defined by the Absolute Maximum Ratings.
21.2
Parameter Interpretation
The parameters listed in the following tables represent the characteristics of the ST10F269
and its demands on the system. Where the ST10F269 logic provides signals with their
respective timing characteristics, the symbol “CC” for Controller Characteristics, is included
in the “Symbol” column.
Where the external system must provide signals with their respective timing characteristics
to the ST10F269, the symbol “SR” for System Requirement, is included in the “Symbol”
column.
21.3
DC Characteristics
VDD = 5 V ± 10%, VSS = 0 V, Reset active, fCPU = 40 MHz with TA = -40 to +119°C or
fCPU = 32 MHz with TA = -40 to +125°C
Table 44. DC Characteristics
Symbol
Parameter
Test
Conditions
Min.
Max.
Unit
VIL
SR Input low voltage
–
-0.5
0.2 VDD -0.1
V
VILS
SR Input low voltage (special threshold)
–
-0.5
2.0
V
VIH
SR Input high voltage (all except RSTIN and XTAL1)
–
0.2 VDD +
0.9
VDD + 0.5
V
VIH1
SR Input high voltage RSTIN
–
0.6 VDD
VDD + 0.5
V
VIH2
SR Input high voltage XTAL1
–
0.7 VDD
VDD + 0.5
V
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ST10F269Z1-ST10F269Z2
Table 44. DC Characteristics (continued)
Symbol
VIHS
Parameter
Test
Conditions
Min.
Max.
Unit
–
0.8 VDD 0.2
VDD + 0.5
V
SR Input high voltage (special threshold)
HYS
Input Hysteresis (special threshold)
3
–
250
–
mV
Output low voltage (PORT0, PORT1, Port 4,
ALE, RD, WR, BHE, CLKOUT, RSTOUT)
1
IOL = 2.4mA
–
0.45
V
1
IOL1 = 1.6mA
–
0.45
V
1
IOH = -500μA
IOH = -2.4mA
0.9 VDD
2.4
–
–
V
1/
2
IOH = – 250μA
IOH = – 1.6mA
0.9 VDD
2.4
–
–
V
V
⎥ IOZ1 ⎥ CC Input leakage current (Port 5)
0V < VIN < VDD
–
200
nA
⎥ IOZ2 ⎥ CC Input leakage current (all other)
0V < VIN < VDD
–
1
μA
–
5
mA
VOL
CC
VOL1
CC Output low voltage (all other outputs)
VOH
CC
VOH1
CC Output high voltage (all other outputs)
Output high voltage (PORT0, PORT1, Port4,
ALE, RD, WR, BHE, CLKOUT, RSTOUT)
⎥ IOV ⎥
SR Overload current
3/
4
RRST
CC RSTIN pull-up resistor
3
–
50
250
kΩ
VOUT = 2.4V
–
-40
μA
IRWH
Read / Write inactive current
5/
6
IRWL
Read / Write active current
5/
VOUT = VOLmax
7
-500
–
μA
IALEL
ALE inactive current
5/
VOUT = VOLmax
6
40
–
μA
IALEH
ALE active current
5/
7
VOUT = 2.4V
–
500
μA
IP6H
Port 6 inactive current
5/
6
VOUT = 2.4V
–
-40
μA
IP6L
Port 6 active current
5/
7
VOUT =
VOL1max
-500
–
μA
5/
6
VIN = VIHmin
–
-10
μA
5/
7
VIN = VILmax
-100
–
μA
0V < VIN < VDD
–
20
μA
5
-
mA/V
IP0H
PORT0 configuration current
IP0L
⎥ IIL ⎥
CC XTAL1 input current
gm
On-chip oscillator transconductance
3
CIO
CC Pin capacitance (digital inputs / outputs)
3/
5
f = 1MHz,
TA = 25°C
–
10
pF
ICC
Power supply current
8
RSTIN = VIH1
fCPU in [MHz]
–
20 + 2.5 x fCPU
mA
IID
Idle mode supply current
9
RSTIN = VIH1
fCPU in [MHz]
–
20 + fCPU
mA
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Electrical Characteristics
Table 44. DC Characteristics (continued)
Symbol
IPD
IPD2
Test
Conditions
Parameter
Power-down mode supply current
10
VDD = 5.5V
TA = 25°C
TA = 85°C
TA = 125°C
VDD = 5.5V
Power-down mode supply current (Real time 10
T = 55°C
clock enabled, oscillator enabled)
12 f A = 25MHz
OSC
Min.
Max.
Unit
–
_
_
15 11
50 11
190 11
μA
μA
μA
–
2 + fOSC / 4
mA
1. ST10F269 pins are equipped with low-noise output drivers which significantly improve the device’s EMI performance. These
low-noise drivers deliver their maximum current only until the respective target output level is reached. After this, the output
current is reduced. This results in increased impedance of the driver, which attenuates electrical noise from the connected
PCB tracks. The current specified in column “Test Conditions” is delivered in any cases.
2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float
and the voltage results from the external circuitry.
3. Partially tested, guaranteed by design characterization.
4. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the
specified range (i.e. VOV > VDD+0.5V or VOV < -0.5V). The absolute sum of input overload currents on all port pins may not
exceed 50 mA. The supply voltage must remain within the specified limits.
5. This specification is only valid during Reset, or during Hold-mode or Adapt-mode. Port 6 pins are only affected if they are
used for CS output and if their open drain function is not enabled.
6. The maximum current may be drawn while the respective signal line remains inactive.
7. The minimum current must be drawn in order to drive the respective signal line active.
8. The power supply current is a function of the operating frequency. This dependency is illustrated in Figure 63. These
parameters are tested at VDDmax and 40 MHz (or 32 MHz) CPU clock with all outputs disconnected and all inputs at VIL or
VIH. The chip is configured with a demultiplexed 16-bit bus, direct clock drive, 5 chip select lines and 2 segment address
lines, EA pin is low during reset. After reset, PORT 0 is driven with the value ‘00CCh’ that produces infinite execution of
NOP instruction with 15 wait-states, R/W delay, memory tristate wait state, normal ALE. Peripherals are not activated.
9. Idle mode supply current is a function of the operating frequency. These parameters are tested at VDDmax and 40 MHz (or
32 MHz) CPU clock with all outputs disconnected and all inputs at VIL or VIH.
10. This parameter value includes leakage currents. With all inputs (including pins configured as inputs) at 0V to 0.1V or at
VDD – 0.1V to VDD, VREF = 0V, all outputs (including pins configured as outputs) disconnected.
11. Typical IPD value is 5 µA @ TA=25°C, 20 µA @ TA=85°C and 60 µA @ TA=125°C.
12. Partially tested, guaranteed by design characterization using 22 pF loading capacitors on crystal pins.
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Electrical Characteristics
ST10F269Z1-ST10F269Z2
Figure 63. Supply / Idle Current as a Function of Operating Frequency
ICCmax
120mA
I [mA]
ICCtyp
100
60mA
IIDmax
IIDtyp
10
0
21.3.1
20
10
40
30
fCPU [MHz]
A/D Converter Characteristics
VDD = 5 V ± 10%, VSS = 0 V, TA = -40 to +85°C or -40 to +125°C,
4.0 V ≤ VAREF ≤ VDD + 0.1V, VSS 0.1 V ≤ VAGND ≤ VSS + 0.2 V
Table 45. A/D Converter Characteristics
Symbol
VAREFSR
Parameter
Test Condition
Limit Values
Unit
minimum
maximum
4.0
VDD + 0.1
V
Analog Reference voltage
VAINSR
Analog input voltage
1-8
VAGND
VAREF
V
IAREFCC
Reference supply current
running mode
power-down mode
7
–
–
500
1
μA
μA
CAINCC
ADC input capacitance
Not sampling
Sampling
7
–
–
10
15
pF
pF
tSCC
Sample time
2-4
48 TCL
1 536 TCL
tCCC
Conversion time
3-4
388 TCL
2 884 TCL
DNLCC
Differential Nonlinearity
5
-0.5
+0.5
LSB
INLCC
Integral Nonlinearity
5
-1.5
+1.5
LSB
OFSCC
Offset Error
5
-1.0
+1.0
LSB
5
-2.0
+2.0
LSB
tS in [ns] 2 - 7
–
(tS / 150) - 0.25
kΩ
TUECC
Total unadjusted error
RASRCSR
Internal resistance of analog source
KCC
Coupling Factor between inputs
6-7
–
1/500
1. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be
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Electrical Characteristics
X000h or X3FFh, respectively.
2. During the tS sample time the input capacitance Cain can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within the tS sample time. After
the end of the tS sample time, changes of the analog input voltage have no effect on the conversion result. Values for the
tSC sample clock depend on the programming. Referring to the tC conversion time formula of Section 21.3.2: Conversion
Timing Control and to Table 46:
tS min = 2 tSC min = 2 tCC min = 2 * 24 TCL = 48 TCL
tS max = 2 tSC max = 2 * 8 tCC max = 2 * 8 * 96 TCL = 1536 TCL
TCL is defined in Section 21.4.2: Definition of Internal Timing, Section 21.4.4: Prescaler Operation, and Section 21.4.5: Direct
Drive:
3. The conversion time formula is: tC = 14 tCC + tS + 4 TCL (= 14 tCC + 2 tSC + 4 TCL).
The tC parameter includes the tS sample time, the time for determining the digital result and the time to load the result
register with the result of the conversion. Values for the tCC conversion clock depend on the programming. Referring to
Table 46:
tC min = 14 tCC min. + tS min + 4 TCL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL
tC max = 14 tCC max +tS max + 4 TCL = 14 x 96 TCL + 1536 TCL + 4 TCL = 2884 TCL
4. This parameter is fixed by ADC control logic.
5. DNL, INL, TUE are tested at VAREF = 5.0 V, VAGND = 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all
other voltages within the defined voltage range.‘LSB’ has a value of VAREF / 1024.
The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum 2 not selected
analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA.
6. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channel with
an absolute overload current less than 10 mA.
7. Partially tested, guaranteed by design characterization.
8.To remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be
connected at the ADC input. The cut-off frequency of this filter should avoid 2 opposite transitions during the ts sampling
time of the ST10 ADC: fcut-off ≤ 1 / 5 ts to 1/10 ts, where ts is the sampling time of the ST10 ADC and is not related to the
Nyquist frequency determined by the tc conversion time.
21.3.2
Conversion Timing Control
When a conversion is started, first the capacitances of the converter are loaded via the
respective analog input pin to the current analog input voltage. The time to load the
capacitances is referred to as the sample time ts. Next the sampled voltage is converted to
a digital value in 10 successive steps, which correspond to the 10-bit resolution of the ADC.
The next 4 steps are used for equalizing internal levels (and are kept for exact timing
matching with the 10-bit A/D converter module implemented in the ST10F168).
The current that has to be drawn from the sources for sampling and changing charges
depends on the time that each respective step takes, because the capacitors must reach
their final voltage level within the given time, at least with a certain approximation. The
maximum current, however, that a source can deliver, depends on its internal resistance.
The sample time tS (= 2 tSC) and the conversion time tc (= 14 tCC + 2 tSC + 4 TCL) can be
programmed relatively to the ST10F269 CPU clock. This allows adjusting the A/D converter
of the ST10F269 to the properties of the system:
Fast Conversion can be achieved by programming the respective times to their absolute
possible minimum. This is preferable for scanning high frequency signals. The internal
resistance of analog source and analog supply must be sufficiently low, however.
High Internal Resistance can be achieved by programming the respective times to a higher
value, or the possible maximum. This is preferable when using analog sources and supply
with a high internal resistance in order to keep the current as low as possible. However the
conversion rate in this case may be considerably lower.
The conversion times are programmed via the upper four bit of register ADCON. Bit field
ADCTC (conversion time control) selects the basic conversion clock tCC, used for the 14
steps of converting. The sample time tS is a multiple of this conversion time and is selected
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by bit field ADSTC (sample time control). The table below lists the possible combinations.
The timings refer to the unit TCL, where fCPU = 1/2 TCL.
Table 46. ADC Sampling and Conversion Timing (fCPU = 40 MHz)
Conversion Clock tCC
ADCTC
Sample Clock tSC
ADSTC
tSC =
At fCPU = 40MHz
and ADCTC = 00
tCC
0.3μs
01
tCC x 2
0.6μs
10
tCC x 4
1.2μs
tCC x 8
2.4μs
TCL = 1/2 x fXTAL
At fCPU = 40MHz
00
TCL x 24
0.3μs
01
Reserved, do not use
Reserved
10
TCL x 96
1.2 μs
11
TCL x 48
0.6 μs
11
00
A complete conversion will take 14 tCC + 2 tSC + 4 TCL (fastest conversion rate = 4.85 ms at
40 MHz). This time includes the conversion itself, the sample time and the time required to
transfer the digital value to the result register.
Table 47. ADC Sampling and Conversion Timing (fCPU = 32 MHz)
ADCON.15/14
ADCTC
Sample Clock tSC
Conversion Clock tCC
TCL = 1/2 x fXTAL
At fCPU = 32MHz
ADCON.13/12
ADSTC
tSC =
At fCPU = 32MHz
and ADCTC = 00
00
TCL x 24
0.375μs
00
tCC
0.375μs
01
Reserved, do not use
Reserved
01
tCC x 2
0.75μs
10
TCL x 96
1.5 μs
10
tCC x 4
1.50μs
11
TCL x 48
0.75 μs
11
tCC x 8
3.00μs
A complete conversion will take 14 tCC + 2 tSC + 4 TCL (fastest conversion rate = 6.06 ms at
32 MHz). This time includes the conversion itself, the sample time and the time required to
transfer the digital value to the result register.
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21.4
AC characteristics
21.4.1
Test Waveforms
Figure 64. Input / Output Waveforms
2.4V
0.2VDD+0.9
0.2VDD+0.9
Test Points
0.45V
0.2VDD-0.1
0.2VDD-0.1
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
Figure 65. Float Waveforms
VOH
VOH -0.1V
VLoad +0.1V
Timing
Reference
Points
VLoad
VLoad -0.1V
VOL +0.1V
VOL
For timing purposes a port pin is no longer floating when VLOAD changes of ±100mV.
It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20mA).
21.4.2
Definition of Internal Timing
The internal operation of the ST10F269 is controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (for example pipeline) or external (for example
bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock, called “TCL”.
The CPU clock signal can be generated by different mechanisms. The duration of TCL and
its variation (and also the derived external timing) depends on the mechanism used to
generate fCPU.
This influence must be regarded when calculating the timings for the ST10F269.
The example for PLL operation shown in Figure 66 refers to a PLL factor of 4.
The mechanism used to generate the CPU clock is selected during reset by the logic levels
on pins P0.15-13 (P0H.7-5).
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Figure 66. Generation Mechanisms for the CPU Clock
Phase locked loop operation
fXTAL
fCPU
TCL TCL
Direct Clock Drive
fXTAL
fCPU
TCL TCL
Prescaler Operation
fXTAL
fCPU
TCL
21.4.3
TCL
Clock Generation Modes
Table 48 associates the combinations of these three bits with the respective clock
generation mode.
Table 48. CPU Frequency Generation (CPU clock in the range 1 to 40 MHz)
P0H.7 P0H.6 P0H.5 CPU Frequency fCPU = fXTAL x F
External Clock Input
Range1
Notes
1
1
1
fXTAL x 4
2.5 to 10MHz
Default configuration
1
1
0
fXTAL x 3
3.33 to 13.33MHz
-
1
0
1
fXTAL x 2
5 to 20MHz
-
1
0
0
fXTAL x 5
2 to 8MHz
-
0
1
1
fXTAL x 1
1 to 40MHz
Direct drive2
0
1
0
fXTAL x 1.5
6.66 to 26.66MHz
-
0
0
1
fXTAL x 0.5
2 to 80MHz
CPU clock via prescaler3
0
0
0
fXTAL x 2.5
4 to 16MHz
-
1. The external clock input range refers to a CPU clock range of 1 to 40 MHz.
2. The maximum input frequency depends on the duty cycle of the external clock signal.
3. The maximum input frequency is 25 MHz when using an external crystal with the internal oscillator; providing that internal
serial resistance of the crystal is less than 40Ω. However, higher frequencies can be applied with an external clock source
on pin XTAL1, but in this case, the input clock signal must reach the defined levels VIL and VIH2.
Table 49. CPU Frequency Generation (CPU clock in the range 1 to 32 MHz)
P0H.7 P0H.6 P0H.5 CPU Frequency fCPU = fXTAL x F
External Clock Input
Range1
Notes
1
1
1
fXTAL x 4
2.5 to 8MHz
Default configuration
1
1
0
fXTAL x 3
3.33 to 10.67MHz
-
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Table 49. CPU Frequency Generation (CPU clock in the range 1 to 32 MHz) (continued)
P0H.7 P0H.6 P0H.5 CPU Frequency fCPU = fXTAL x F
External Clock Input
Range1
Notes
-
1
0
1
fXTAL x 2
5 to 16MHz
1
0
0
fXTAL x 5
2 to 6.4MHz
-
0
1
1
fXTAL x 1
1 to 32MHz
Direct drive2
0
1
0
fXTAL x 1.5
6.67 to 21.33MHz
-
0
0
1
fXTAL x 0.5
2 to 64MHz
CPU clock via prescaler3
0
0
0
fXTAL x 2.5
4 to 12.8MHz
-
1. The external clock input range refers to a CPU clock range of 1 to 32 MHz.
2. The maximum input frequency depends on the duty cycle of the external clock signal.
3. The maximum input frequency is 32 MHz when using an external crystal with the internal oscillator; providing that internal
serial resistance of the crystal is less than 40Ω. However, higher frequencies can be applied with an external clock source
on pin XTAL1, but in this case, the input clock signal must reach the defined levels VIL and VIH2.
21.4.4
Prescaler Operation
When pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the
internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock fXTAL.
The timings listed in the AC Characteristics that refer to TCL therefore can be calculated
using the period of fXTAL for any TCL.
Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set,
then the PLL is switched off.
21.4.5
Direct Drive
When pins P0.15-13 (P0H.7-5) equal ’011’ during reset the on-chip phase locked loop is
disabled and the CPU clock is directly driven from the internal oscillator with the input clock
signal.
The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of
fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
fXTAL.
Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value
can be calculated by the following formula:
TCL min = 1 ⁄ f XT ALl xl DCmin
DC = duty cycle
For two consecutive TCLs, the deviation caused by the duty cycle of fXTAL is compensated,
so the duration of 2TCL is always 1 / fXTAL.
The minimum value TCLmin has to be used only once for timings that require an odd number
of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula:
2TCL = 1 ⁄ f XTAL
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The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration
of TCL (TCLmax = 1 / fXTAL x DCmax) instead of TCLmin.
If the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set,
then the PLL is switched off.
21.4.6
Oscillator Watchdog (OWD)
An on-chip watchdog oscillator is implemented in the ST10F269. This feature is used for
safety operation with external crystal oscillator (using direct drive mode with or without
prescaler). This watchdog oscillator operates as described below.
The reset default configuration enables the watchdog oscillator. It can be disabled by setting
the OWDDIS (bit 4) of SYSCON register.
When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the
watchdog counter. The PLL free-running frequency is between 2 and 10 MHz. On each
transition of external clock, the watchdog counter is cleared. If an external clock failure
occurs, then the watchdog counter overflows (after 16 PLL clock cycles).
The CPU clock signal will be switched to the PLL free-running clock signal, and the
oscillator watchdog Interrupt Request (XP3INT) is flagged. The CPU clock will not switch
back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware
reset can switch the CPU clock source back to direct clock input.
When the OWD is disabled, the CPU clock is always external oscillator clock and the PLL is
switched off to decrease consumption supply current.
21.4.7
Phase Locked Loop
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and it provides the CPU clock (see Table 48 and Table 49). The PLL
multiplies the input frequency by the factor F which is selected via the combination of pins
P0.15-13 (fCPU = fXTAL x F). With every F’th transition of fXTAL the PLL circuit synchronizes
the CPU clock to the input clock. This synchronization is done smoothly, so the CPU clock
frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is
locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of
individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated
using the minimum TCL that is possible under the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes fCPU to
keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is referred to
one TCL period. It decreases according to the formula and to Figure 67 given below. For N
periods of TCL the minimum value is computed using the corresponding deviation DN:
TCL
MIN
= TCL
NOM
DN ⎞
⎛
× ⎜ 1 – -------------⎟
⎜
100 ⎟
⎝
⎠
D N = ±( 4 – N ⁄ 15 ) [ % ]
where N = number of consecutive TCL periods and 1 ≤ N ≤ 40. So for a period of 3 TCL
periods (N = 3):
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D3 =4 - 3/15 = 3.8%
3TCLmin =3TCLNOM x (1 - 3.8/100)
=3TCLNOM x 0.962
3TCLmin=36.075ns (at fCPU = 40MHz)
3TCLmin=45.1ns (at fCPU = 32MHz)
This is especially important for bus cycles using wait states and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baud rates, etc.) the deviation caused by the PLL jitter is
negligible.
Figure 67. Approximated Maximum PLL Jitter
Max.jitter [%]
This approximated formula is valid for
1 ≤N ≤40 and 10MHz ≤fCPU ≤40MHz
±4
±3
±2
±1
2
21.4.8
4
8
16
32
N
External Clock Drive XTAL1
VDD = 5 V ± 10%, VSS = 0 V, TA = -40 to +119 °C
Table 50. External Clock Drive XTAL1 (max fCPU = 40 MHz)
Parameter
Symbol
fCPU = fXTAL
fCPU = fXTAL / 2
fCPU = fXTAL x F
F = 1.5/2,/2.5/3/4/5
Unit
Minimum Maximum Minimum Maximum Minimum Maximum
Oscillator period
High time
tOSCSR
t1SR
25 1
10
2
2
–
–
Low time
t2SR
10
Rise time
t3SR
–
32
–
2
Fall time
t4SR
–
3
12.5
5
2
5
2
–
–
–
–
32
–
2
3
40 x N
10
2
10
2
100 x N
ns
–
ns
–
ns
–
32
ns
–
2
ns
3
1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 25 MHz is the maximum
input frequency when using an external crystal oscillator. However, 40 MHz can be applied with an external clock source.
2. The input clock signal must reach the defined levels VIL and VIH2.
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VDD = 5 V ± 10%, VSS = 0 V, TA = -40 to +125 °C
Table 51. External Clock Drive XTAL1 (max fCPU = 32 MHz)
Parameter
fCPU = fXTAL
Symbol
fCPU = fXTAL / 2
fCPU = fXTAL x F
F = 1.5/2,/2.5/3/4/5
Unit
Minimum Maximum Minimum Maximum Minimum Maximum
Oscillator period
High time
31.251
tOSCSR
–
2
t1SR
12.5
15.625
–
2
6.25
2
2
–
31.25 x N
–
12.5
2
2
–
ns
–
ns
–
ns
Low time
t2SR
12.5
–
6.25
–
12.5
Rise time
t3SR
–
3.1252
–
1.562
–
3.1252
ns
–
2
–
2
–
2
ns
Fall time
t4SR
3.125
1.56
3.125
1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 25 MHz is the maximum
input frequency when using an external crystal oscillator. However, 32 MHz can be applied with an external clock source.
2. The input clock signal must reach the defined levels VIL and VIH2.
Figure 68. External Clock Drive XTAL1
t3
t1
t4
VIL
VIH2
t2
tOSC
21.4.9
Memory Cycle Variables
The table below uses three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes, how these variables are computed.
Table 52. Memory Cycle Variables
Description
Symbol
Values
ALE Extension
tA
TCL x [ALECTL]
Memory Cycle Time wait states
tC
2TCL x (15 - [MCTC])
Memory Tri-state Time
tF
2TCL x (1 - [MTTC])
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21.4.10
Electrical Characteristics
Multiplexed Bus
VDD = 5 V ± 10%, VSS = 0 V, TA = -40 to +119°C, CL = 50 pF,
ALE cycle time = 6 TCL + 2 tA + tC + tF (75 ns at 40 MHz CPU clock without wait states).
Table 53. Multiplexed Bus Characteristics (max fCPU = 40 MHz)
Parameter
Variable CPU Clock
1/2 TCL = 1 to 40 MHz
Unit
Symbol
Max. CPU Clock
= 40 MHz
Minimum
Maximum
Minimum
Maximum
ALE high time
4 + tA
–
TCL - 8.5 + tA
–
ns
t6CC
Address setup to ALE
2 + tA
–
TCL - 10.5 + tA
–
ns
t7CC
Address hold after ALE1
4 + tA
–
TCL - 8.5 + tA
–
ns
t8CC
ALE falling edge to RD, WR
(with RW-delay)
4 + tA
–
TCL - 8.5 + tA
–
ns
t9CC
ALE falling edge to RD, WR
(no RW-delay)
-8.5 + tA
–
-8.5 + tA
–
ns
t10CC
Address float after RD, WR
(with RW-delay)1
–
6
–
6
ns
t11CC
Address float after RD, WR
(no RW-delay)1
–
18.5
–
TCL + 6
ns
t12CC
RD, WR low time
(with RW-delay)
15.5 + tC
–
2 TCL -9.5 + tC
–
ns
t13CC
RD, WR low time
(no RW-delay)
28 + tC
–
3 TCL -9.5 + tC
–
ns
t14SR
RD to valid data in
(with RW-delay)
–
6 + tC
–
2 TCL - 19 + tC
ns
t15SR
RD to valid data in
(no RW-delay)
–
18.5 + tC
–
3 TCL - 19 + tC
ns
t16SR
ALE low to valid data in
–
18.5
+ tA + tC
–
3 TCL - 19
+ tA + tC
ns
t17SR
Address/Unlatched CS to valid
data in
–
22 + 2tA + tC
–
4 TCL - 28
+ 2tA + tC
ns
t18SR
Data hold after RD
rising edge
0
–
0
–
ns
t5CC
t19SR
Data float after RD1
t22CC
Data valid to WR
t23CC
–
16.5 + tF
–
2 TCL - 8.5 + tF
ns
10 + tC
–
2 TCL -15 + tC
–
ns
Data hold after WR
4 + tF
–
2 TCL - 8.5 + tF
–
ns
t25CC
ALE rising edge after RD, WR
15 + tF
–
2 TCL -10 + tF
–
ns
t27CC
Address/Unlatched CS hold
after RD, WR
10 + tF
–
2 TCL -15 + tF
–
ns
t38CC
ALE falling edge to Latched CS
-4 - tA
10 - tA
-4 - tA
10 - tA
ns
t39SR
Latched CS low to Valid Data
In
–
18.5 + tC +
2tA
–
3 TCL - 19
+ tC + 2tA
ns
t40CC
Latched CS hold after RD, WR
27 + tF
–
3 TCL - 10.5 + tF
–
ns
t42CC
ALE fall. edge to RdCS, WrCS
(with RW delay)
7 + tA
–
TCL - 5.5+ tA
–
ns
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Symbol
Max. CPU Clock
= 40 MHz
Parameter
Variable CPU Clock
1/2 TCL = 1 to 40 MHz
Unit
Table 53. Multiplexed Bus Characteristics (max fCPU = 40 MHz) (continued)
Minimum
Maximum
Minimum
Maximum
-5.5 + tA
–
-5.5 + tA
–
ns
t43CC
ALE fall. edge to RdCS, WrCS
(no RW delay)
t44CC
Address float after RdCS,
WrCS (with RW delay)1
–
0
–
0
ns
t45CC
Address float after RdCS,
WrCS (no RW delay)1
–
12.5
–
TCL
ns
t46SR
RdCS to Valid Data In
(with RW delay)
–
4 + tC
–
2 TCL - 21 + tC
ns
t47SR
RdCS to Valid Data In
(no RW delay)
–
16.5 + tC
–
3 TCL - 21 + tC
ns
t48CC
RdCS, WrCS Low Time
(with RW delay)
15.5 + tC
–
2 TCL - 9.5 + tC
–
ns
t49CC
RdCS, WrCS Low Time
(no RW delay)
28 + tC
–
3 TCL - 9.5 + tC
–
ns
t50CC
Data valid to WrCS
10 + tC
–
2 TCL - 15+ tC
–
ns
t51SR
Data hold after RdCS
0
–
0
–
ns
t52SR
Data float after RdCS1
–
16.5 + tF
–
2 TCL - 8.5+tF
ns
t54CC
Address hold after
RdCS, WrCS
6 + tF
–
2 TCL - 19 + tF
–
ns
t56CC
Data hold after WrCS
6 + tF
–
2 TCL - 19 + tF
–
ns
1. Partially tested, guaranteed by design characterization.
VDD = 5 V ± 10%, VSS = 0 V, TA = -40 to +125°C, CL = 50 pF,
ALE cycle time = 6 TCL + 2 tA + tC + tF (187.5 ns at 32 MHz CPU clock without wait states).
Symbol
Parameter
Maximum CPU Clock =
32 MHz
Variable CPU Clock
1/2 TCL = 1 to 32 MHz
Minimum
Maximum
Minimum
Maximum
Unit
Table 54. Multiplexed Bus Characteristics (max fCPU = 32 MHz)
t42CC
ALE high time
5.625 + tA
–
TCL - 10 + tA
–
ns
t6CC
Address setup to ALE
0.625 + tA
–
TCL - 15+ tA
–
ns
t7CC
Address hold after ALE1
5.625 + tA
–
TCL - 10 + tA
–
ns
t8CC
ALE falling edge to RD, WR
(with RW-delay)
5.625 + tA
–
TCL - 10 + tA
–
ns
t9CC
ALE falling edge to RD, WR
(no RW-delay)
-10 + tA
–
-10 + tA
–
ns
t10CC
Address float after RD, WR
(with RW-delay)1
–
6
–
6
ns
t11CC
Address float after RD, WR
(no RW-delay)1
–
21.625
–
TCL + 6
ns
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Table 54. Multiplexed Bus Characteristics (max fCPU = 32 MHz) (continued)
Parameter
Variable CPU Clock
1/2 TCL = 1 to 32 MHz
Minimum
Maximum
Minimum
Maximum
Unit
Symbol
Maximum CPU Clock =
32 MHz
t12CC
RD, WR low time
(with RW-delay)
21.25 + tC
–
2TCL - 10 + tC
–
ns
t13CC
RD, WR low time
(no RW-delay)
36.875 + tC
–
3TCL - 10 + tC
–
ns
t14SR
RD to valid data in
(with RW-delay)
–
11.25 + tC
–
2TCL - 20+ tC
ns
t15SR
RD to valid data in
(no RW-delay)
–
26.875 + tC
–
3TCL - 20+ tC
ns
t16SR
ALE low to valid data in
–
26.875 + tA + tC
–
3TCL - 20
+ tA + tC
ns
t17SR
Address/Unlatched CS to valid
data in
–
32.5 + 2tA + tC
–
4TCL - 30
+ 2tA + tC
ns
t18SR
Data hold after RD
rising edge
0
–
0
–
ns
t19SR
Data float after RD1
–
17.25 + tF
–
2TCL - 14 + tF
ns
t22CC
Data valid to WR
11.25 + tC
–
2TCL - 20 + tC
–
ns
t23CC
Data hold after WR
17.25 + tF
–
2TCL - 14 + tF
–
ns
t25CC
ALE rising edge after RD, WR
17.25 + tF
–
2TCL - 14 + tF
–
ns
t27CC
Address/Unlatched CS hold
after RD, WR
17.25 + tF
–
2TCL - 14 + tF
–
ns
t38CC
ALE falling edge to Latched
CS
-4 - tA
10 - tA
-4 - tA
10 - tA
ns
t39SR
Latched CS low to Valid Data
In
–
26.875 + tC + 2tA
–
3TCL - 20
+ tC + 2tA
ns
t40CC
Latched CS hold after RD, WR 32.875 + tF
–
3TCL - 14 + tF
–
ns
t42CC
ALE fall. edge to RdCS, WrCS
(with RW delay)
11.625 + tA
–
TCL - 4 + tA
–
ns
t43CC
ALE fall. edge to RdCS, WrCS
(no RW delay)
-4 + tA
–
-4 + tA
–
ns
t44CC
Address float after RdCS,
WrCS (with RW delay)1
–
0
–
0
ns
t45CC
Address float after RdCS,
WrCS (no RW delay)1
–
15.625
–
TCL
ns
t46SR
RdCS to Valid Data In
(with RW delay)
–
7.25 + tC
–
2TCL - 24 + tC
ns
t47SR
RdCS to Valid Data In
(no RW delay)
–
22.875 + tC
–
3TCL - 24 + tC
ns
t48CC
RdCS, WrCS Low Time
(with RW delay)
21.25 + tC
–
2TCL - 10 + tC
–
ns
t49CC
RdCS, WrCS Low Time
(no RW delay)
36.875 + tC
–
3TCL - 10 + tC
–
ns
t50CC
Data valid to WrCS
17.25 + tC
–
2TCL - 14+ tC
–
ns
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Electrical Characteristics
ST10F269Z1-ST10F269Z2
Symbol
Parameter
Maximum CPU Clock =
32 MHz
Variable CPU Clock
1/2 TCL = 1 to 32 MHz
Minimum
Maximum
Minimum
Maximum
Unit
Table 54. Multiplexed Bus Characteristics (max fCPU = 32 MHz) (continued)
t51SR
Data hold after RdCS
0
–
0
–
ns
t52SR
Data float after RdCS1
–
11.25 + tF
–
2TCL - 20 + tF
ns
t54CC
Address hold after
RdCS, WrCS
11.25 + tF
–
2TCL - 20 + tF
–
ns
11.25 + tF
–
2TCL - 20 + tF
–
ns
t56
CC
Data hold after WrCS
1. Partially tested, guaranteed by design characterization.
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Electrical Characteristics
Figure 69. External Memory Cycle: Multiplexed Bus, With/Without Read/Write Delay,
Normal ALE
CLKOUT
t
t
t
ALE
t
t
t
t
t
t
CSx
t
t
t
A23-A16
(A15-A8)
BHE
A
t
t
Read Cycle
Address/Data
Bus (P0)
t
t
A
D
t
t
t
t
RD
t
t
t
t
t
Write Cycle
t
Address/Data
Bus (P0)
A
D
t
WR
WRL
WRH
t
t
t
t
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ST10F269Z1-ST10F269Z2
Figure 70. External Memory Cycle: Multiplexed Bus, With/Without Read/Write Delay,
Extended ALE
CLKOUT
t
t
ALE
t
t
t
t
CSx
t
t
A23-A16
(A15-A8)
BHE
Read Cycle
Address/Data
Bus (P0)
A
t
t
D
A
t
t
t
t
t
t
RD
t
t
t
Write Cycle
Address/Data
Bus (P0)
A
D
t
t
WR
WRL
WRH
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t
t
t
t
t
DocID13266 Rev 2
ST10F269Z1-ST10F269Z2
Electrical Characteristics
Figure 71. External Memory Cycle: Multiplexed Bus, With/Without Read/Write Delay,
Normal ALE, Read / Write Chip Select
CLKOUT
t
t
t
ALE
t
t
t
A23-A16
(A15-A8)
BHE
A
t
Read Cycle
Address/Data
Bus (P0)
t
t
t
A
D
t
t
t
t
RdCSx
t
t
t
t
t
Write Cycle
Address/Data
Bus (P0)
t
A
D
t
WrCSx
t
t
t
t
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ST10F269Z1-ST10F269Z2
Figure 72. External Memory Cycle: Multiplexed Bus, With/Without Read/Write Delay,
Extended ALE, Read / Write Chip Select
CLKOUT
t
t
ALE
t
t
A23-A16
(A15-A8)
BHE
Read Cycle
Address/Data
Bus (P0)
A
t
t
D
A
t
t
t
t
t
RdCSx
t
t
t
Write Cycle
Address/Data
Bus (P0)
A
D
t
t
t
t
t
WrCSx
t
t
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21.4.11
Electrical Characteristics
Demultiplexed Bus
VDD = 5 V ± 10%, VSS = 0V, TA = -40 to +119°C, CL = 50pF,
ALE cycle time = 4 TCL + 2 tA + tC + tF (50 ns at 40 MHz CPU clock without wait states)
Symbol
Parameter
Maximum CPU Clock
= 40 MHz
Minimum
Maximum
Variable CPU Clock
1/2 TCL = 1 to 40 MHz
Minimum
Maximum
Unit
Table 55. Demultiplexed Bus Characteristics (max fCPU = 40 MHz)
t5CC
ALE high time
4 + tA
–
TCL - 8.5 + tA
–
ns
t6CC
Address setup to ALE
2 + tA
–
TCL - 10.5 + tA
–
ns
t80CC
Address/Unlatched CS setup to
RD, WR
(with RW-delay)
16.5 + 2tA
–
2 TCL - 8.5 + 2tA
–
ns
t81CC
Address/Unlatched CS setup to
RD, WR
(no RW-delay)
4 + 2tA
–
TCL - 8.5 + 2tA
–
ns
t12CC
RD, WR low time
(with RW-delay)
15.5 + tC
–
2 TCL - 9.5 + tC
–
ns
t13CC
RD, WR low time
(no RW-delay)
28 + tC
–
3 TCL - 9.5 + tC
–
ns
t14SR
RD to valid data in
(with RW-delay)
–
6 + tC
–
2 TCL - 19 + tC
ns
t15SR
RD to valid data in
(no RW-delay)
–
18.5 + tC
–
3 TCL - 19 + tC
ns
t16SR
ALE low to valid data in
–
18.5 + tA +
tC
–
3 TCL - 19
+ tA + tC
ns
t17SR
Address/Unlatched CS to valid
data in
–
22 + 2tA + tC
–
4 TCL - 28
+ 2tA + tC
ns
t18SR
Data hold after RD
rising edge
0
–
0
–
ns
t20SR
Data float after RD rising edge
(with RW-delay)1 3
–
16.5 + tF
–
2 TCL - 8.5
+ tF + 2tA 1
ns
t21SR
Data float after RD rising edge
(no RW-delay) 1 3
–
4 + tF
–
TCL - 8.5
+ tF + 2tA 1
ns
10 + tC
–
2 TCL - 15 + tC
–
ns
4 + tF
–
TCL - 8.5 + tF
–
ns
t22CC
Data valid to WR
t24CC
Data hold after WR
t26CC
ALE rising edge after RD, WR
-10 + tF
–
-10 + tF
–
ns
t28CC
Address/Unlatched CS hold
after RD, WR 2
0 (no tF)
-5 + tF
(tF > 0)
–
0 (no tF)
-5 + tF
(tF > 0)
–
ns
t28hCC
Address/Unlatched CS hold
after WRH
-5 + tF
–
-5 + tF
–
ns
t38CC
ALE falling edge to Latched CS
-4 - tA
6 - tA
-4 - tA
6 - tA
ns
t39SR
Latched CS low to Valid Data In
–
18.5
+ tC + 2tA
–
3 TCL - 19
+ tC + 2tA
ns
t41CC
Latched CS hold after RD, WR
2 + tF
–
TCL - 10.5 + tF
–
ns
t82CC
Address setup to RdCS, WrCS
(with RW-delay)
–
2 TCL - 10.5 +
2tA
–
ns
14.5 + 2tA
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ST10F269Z1-ST10F269Z2
Symbol
Parameter
Maximum CPU Clock
= 40 MHz
Variable CPU Clock
1/2 TCL = 1 to 40 MHz
Unit
Table 55. Demultiplexed Bus Characteristics (max fCPU = 40 MHz) (continued)
Minimum
Maximum
Minimum
Maximum
2 + 2tA
–
TCL - 10.5 + 2tA
–
ns
t83CC
Address setup to RdCS, WrCS
(no RW-delay)
t46SR
RdCS to Valid Data In
(with RW-delay)
–
4 + tC
–
2 TCL - 21 + tC
ns
t47SR
RdCS to Valid Data In
(no RW-delay)
–
16.5 + tC
–
3 TCL - 21 + tC
ns
t48CC
RdCS, WrCS Low Time
(with RW-delay)
15.5 + tC
–
2 TCL - 9.5
+ tC
–
ns
t49CC
RdCS, WrCS Low Time
(no RW-delay)
28 + tC
–
3 TCL - 9.5 + tC
–
ns
t50CC
Data valid to WrCS
10 + tC
–
2 TCL - 15 + tC
–
ns
t51SR
Data hold after RdCS
0
–
0
–
ns
t53SR
Data float after RdCS
(with RW-delay) 3
–
16.5 + tF
–
2 TCL - 8.5 + tF
ns
t68SR
Data float after RdCS
(no RW-delay) 3
–
4 + tF
–
TCL - 8.5 + tF
ns
t55CC
Address hold after
RdCS, WrCS
-8.5 + tF
–
-8.5 + tF
–
ns
t57CC
Data hold after WrCS
2 + tF
–
TCL - 10.5 + tF
–
ns
1. RW-delay and tA refer to the next following bus cycle.
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address
changes before the end of RD have no impact on read cycles.
3. Partially tested, guaranteed by design characterization.
VDD = 5 V ± 10%, VSS = 0V, TA = -40 to +85°C, CL = 50pF,
ALE cycle time = 4 TCL + 2 tA + tC + tF (125ns at 32MHz CPU clock without wait states)
RW-delay and tA refer to the next following bus cycle.
Table 56. Demultiplexed Bus Characteristics (max fCPU = 32 MHz)
Symbol
Parameter
Maximum CPU Clock =
32 MHz
Variable CPU Clock
1/2 TCL = 1 to 32 MHz
Minimum
Maximum
Minimum
Maximum
Unit
t5CC
ALE high time
5.625 + tA
–
TCL - 10+ tA
–
ns
t6CC
Address setup to ALE
0.625 + tA
–
TCL - 15+ tA
–
ns
t80CC
Address/Unlatched CS setup
to RD, WR
(with RW-delay)
21.25 + 2tA
–
2TCL - 10 + 2tA
–
ns
t81CC
Address/Unlatched CS setup
to RD, WR
(no RW-delay)
5.625 + 2tA
–
TCL -10 + 2tA
–
ns
t12CC
RD, WR low time
(with RW-delay)
21.25 + tC
–
2TCL - 10 + tC
–
ns
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Electrical Characteristics
Table 56. Demultiplexed Bus Characteristics (max fCPU = 32 MHz) (continued)
Symbol
Parameter
Maximum CPU Clock =
32 MHz
Variable CPU Clock
1/2 TCL = 1 to 32 MHz
Minimum
Maximum
Minimum
Maximum
Unit
t13CC
RD, WR low time
(no RW-delay)
36.875 + tC
–
3TCL - 10 + tC
–
ns
t14SR
RD to valid data in
(with RW-delay)
–
11.25 + tC
–
2TCL - 20 + tC
ns
t15SR
RD to valid data in
(no RW-delay)
–
26.875 + tC
–
3TCL - 20 + tC
ns
t16SR
ALE low to valid data in
–
26.875 + tA +
tC
–
3TCL - 20
+ tA + tC
ns
t17SR
Address/Unlatched CS to
valid data in
–
32.5 + 2tA +
tC
–
4TCL - 30
+ 2tA + tC
ns
t18SR
Data hold after RD
rising edge
0
–
0
–
ns
t20SR
Data float after RD rising
edge (with RW-delay)1 - 3
–
26 + tF
–
2TCL - 14
+ tF + 2tA1
ns
t21SR
Data float after RD rising
edge (no RW-delay) 1 - 3
–
5.625 + tF
–
TCL - 10
+ tF + 2tA1
ns
t22CC
Data valid to WR
11.25 + tC
–
2TCL- 20 + tC
–
ns
t24CC
Data hold after WR
5.625 + tF
–
TCL - 10+ tF
–
ns
t26CC
ALE rising edge after RD,
WR
-10 + tF
–
-10 + tF
–
ns
t28CC
Address/Unlatched CS hold
after RD, WR 2
–
ns
0 (no tF)
-5 + tF
> 0)
(tF
–
0 (no tF)
-5 + tF
(tF >
0)
t28hCC
Address/Unlatched CS hold
after WRH
-5 + tF
–
-5 + tF
–
ns
t38CC
ALE falling edge to Latched
CS
-4 - tA
10 - tA
-4 - tA
10 - tA
ns
t39SR
Latched CS low to Valid Data
In
–
26.875 + tC+
2tA
–
3TCL - 20
+ tC + 2tA
ns
t41CC
Latched CS hold after RD,
WR
1.625 + tF
–
TCL - 14 + tF
–
ns
t82CC
Address setup to RdCS,
WrCS
(with RW-delay)
17.25 + 2tA
–
2TCL - 14 + 2tA
–
ns
t83CC
Address setup to RdCS,
WrCS
(no RW-delay)
1.625 + 2tA
–
TCL -14 + 2tA
–
ns
t46SR
RdCS to Valid Data In
(with RW-delay)
–
7.25 + tC
–
2TCL - 24 + tC
ns
t47SR
RdCS to Valid Data In
(no RW-delay)
–
22.875 + tC
–
3TCL - 24 + tC
ns
t48CC
RdCS, WrCS Low Time
(with RW-delay)
21.25 + tC
–
2TCL - 10 + tC
–
ns
t49CC
RdCS, WrCS Low Time
(no RW-delay)
36.875 + tC
–
3TCL - 10 + tC
–
ns
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Table 56. Demultiplexed Bus Characteristics (max fCPU = 32 MHz) (continued)
Symbol
t50CC
Parameter
Data valid to WrCS
Maximum CPU Clock =
32 MHz
Variable CPU Clock
1/2 TCL = 1 to 32 MHz
Unit
Minimum
Maximum
Minimum
Maximum
17.25 + tC
–
2TCL - 14 + tC
–
ns
t51SR
Data hold after RdCS
0
–
0
–
ns
t53SR
Data float after RdCS
(with RW-delay) 3
–
21.25 + tF
–
2TCL - 10 + tF
ns
t68SR
Data float after RdCS
(no RW-delay) 3
–
0 + tF
–
TCL - 10 + tF
ns
t55CC
Address hold after
RdCS, WrCS
-10 + tF
–
-10 + tF
–
ns
t57CC
Data hold after WrCS
1.625 + tF
–
TCL - 14 + tF
–
ns
1. RW-delay and tA refer to the next following bus cycle.
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address
changes before the end of RD have no impact on read cycles.
3. Partially tested, guaranteed by design characterization.
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Electrical Characteristics
Figure 73. External Memory Cycle: Demultiplexed Bus, With/Without Read/Write Delay,
Normal ALE
CLKOUT
t
t
t
ALE
t
t
t
t
t
1)
t
CSx
t
t
t
A23-A16
A15-A0 (P1)
BHE
A
t
Read Cycle
Data Bus (P0)
(D15-D8) D7-D0
D
t
t
t
t
t
t
RD
t
t
Write Cycle
Data Bus (P0)
(D15-D8) D7-D0
D
t
t
t
t
WR
WRL
WRH
t
t
1. 1. Un-latched CSx = t41u = t41 TCL =10.5 + tF.
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Electrical Characteristics
ST10F269Z1-ST10F269Z2
Figure 74. External Memory Cycle: Demultiplexed Bus, With/Without Read/Write Delay,
Extended ALE
CLKOUT
t
t
ALE
t
t
t
CSx
t
t
A23-A16
A15-A0 (P1)
BHE
A
Read Cycle
Data Bus (P0)
(D15-D8) D7-D0
D
t
t
t
t
RD
t
t
Write Cycle
Data Bus (P0)
(D15-D8) D7-D0
D
t
t
t
WR
WRL
WRH
t
t
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Electrical Characteristics
Figure 75. External Memory Cycle: Demultiplexed Bus, With/Without Read/Write Delay,
Normal ALE, Read/Write Chip Select
CLKOUT
t
t
t
ALE
t
t
A23-A16
A15-A0 (P1)
BHE
t
A
t
Read Cycle
Data Bus (P0)
(D15-D8) D7-D0
D
t
t
t
t
t
t
RdCSx
t
t
Write Cycle
Data Bus (P0)
(D15-D8) D7-D0
D
t
t
t
t
WrCSx
t
t
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ST10F269Z1-ST10F269Z2
Figure 76. External Memory Cycle: Demultiplexed Bus, no Read/Write Delay,
Extended ALE, Read /Write Chip Select
CLKOUT
t
t
ALE
t
t
A23-A16
A15-A0 (P1)
BHE
A
Read Cycle
Data Bus (P0)
(D15-D8) D7-D0
D
t
t
t
t
RdCSx
t
t
Write Cycle
Data Bus (P0)
(D15-D8) D7-D0
D
t
t
t
WrCSx
t
t
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21.4.12
Electrical Characteristics
CLKOUT and READY
VDD = 5V ± 10%, VSS = 0V, TA = -40 to + 119°C, CL = 50 pF
Table 57. CLKOUT and READY Characteristics (max fCPU = 40 MHz)
Parameter
Variable CPU Clock
1/2TCL = 1 to 40 MHz
Unit
Symbol
Maximum CPU Clock
= 40 MHz
Minimum
Maximum
Minimum
Maximum
CLKOUT cycle time
25
25
2TCL
2TCL
t30CC
CLKOUT high time
4
–
TCL – 8.5
–
ns
t31CC
CLKOUT low time
3
–
TCL – 9.5
–
ns
t32CC
CLKOUT rise time
–
4
–
4
ns
t33CC
CLKOUT fall time
–
4
–
4
ns
t34CC
CLKOUT rising edge to
ALE falling edge
-2 + tA
8 + tA
-2 + tA
8 + tA
ns
t35SR
Synchronous READY
setup time to CLKOUT
12.5
–
12.5
–
ns
t36SR
Synchronous READY
hold time after CLKOUT
2
–
2
–
ns
t37SR
Asynchronous READY
low time
35
–
2TCL + 10
–
ns
t58SR
Asynchronous READY
setup time 1)
12.5
–
12.5
–
ns
t59SR
Asynchronous READY
hold time 1)
2
–
2
–
ns
t60SR
Async. READY hold time after
RD, WR high (Demultiplexed
Bus) 2)
0
0 + 2tA + tC + tF
0
TCL - 12.5
+ 2tA + tC + tF 2)
ns
t29CC
2)
ns
1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even
more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.
VDD = 5 V ± 10%, VSS = 0V, TA = -40 to + 125°C, CL = 50 pF
Symbol
Parameter
Maximum CPU Clock
= 32 MHz
Variable CPU Clock
1/2TCL = 1 to 32 MHz
Minimum
Maximum
Minimum
Maximum
Unit
Table 58. CLKOUT and READY Characteristics (max fCPU = 32 MHz)
t29CC
CLKOUT cycle time
31.25
31.25
2TCL
2TCL
ns
t30CC
CLKOUT high time
9.625
–
TCL – 6
–
ns
t31CC
CLKOUT low time
5.625
–
TCL – 10
–
ns
t32CC
CLKOUT rise time
–
4
–
4
ns
t33CC
CLKOUT fall time
–
4
–
4
ns
t34CC
CLKOUT rising edge to
ALE falling edge
-3 + tA
+7 + tA
-3 + tA
+7 + tA
ns
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Electrical Characteristics
ST10F269Z1-ST10F269Z2
Symbol
Parameter
Maximum CPU Clock
= 32 MHz
Variable CPU Clock
1/2TCL = 1 to 32 MHz
Minimum
Maximum
Minimum
Maximum
Unit
Table 58. CLKOUT and READY Characteristics (max fCPU = 32 MHz) (continued)
t35SR
Synchronous READY
setup time to CLKOUT
14
–
14
–
ns
t36SR
Synchronous READY
hold time after CLKOUT
4
–
4
–
ns
t37SR
Asynchronous READY
low time
45.25
–
2TCL + 14
–
ns
t58SR
Asynchronous READY
setup time 1)
14
–
14
–
ns
t59SR
Asynchronous READY
hold time 1)
4
–
4
–
ns
t60SR
Async. READY hold time after
RD, WR high (Demultiplexed
Bus) 2)
0
0 + 2tA
+ tC + tF 2
0
TCL - 15.625 +
2tA + tC + tF 2
ns
1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even
more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.
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Electrical Characteristics
Figure 77. CLKOUT and READY
READY
wait state
Running cycle 1)
t
MUX / Tri-state 6)
t
CLKOUT
t
t
t
t
ALE
7)
RD, WR
2)
Synchronous
READY
t
3)
t
t
4) t
t
t
3)
3)
Asynchronous
READY
t
t
t
3)
5)
t
6)
1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled
LOW at this sampling point terminates the currently running bus cycle.
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to
CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is
guaranteed, if READY is removed in response to the command (see Note 4).
6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state
may be inserted here.
For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC wait state this delay is zero.
7. The next external bus cycle may start here.
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21.4.13
ST10F269Z1-ST10F269Z2
External Bus Arbitration
VDD = 5 V ± 10%, VSS = 0V, TA = -40 to +119°C, CL = 50pF
Symbol
Maximum CPU Clock
= 40 MHz
Parameter
Variable CPU Clock
1/2TCL = 1 to 40 MHz
Minimum
Maximum
Minimum
Maximum
Unit
Table 59. external Bus Arbitration (max fCPU = 40 MHz)
t61SR
HOLD input setup time
to CLKOUT
15
–
15
–
ns
t62CC
CLKOUT to HLDA high
or BREQ low delay
–
12.5
–
12.5
ns
t63CC
CLKOUT to HLDA low
or BREQ high delay
–
12.5
–
12.5
ns
t64CC
CSx release 1
–
15
–
15
ns
t65CC
CSx drive
-4
15
-4
15
ns
–
15
–
15
ns
-4
15
-4
15
ns
t66CC
Other signals release
t67CC
Other signals drive
1
1. Partially tested, guaranteed by design characterization
VDD = 5 V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50 pF
Table 60. External Bus Arbitration (max fCPU = 32 MHz)
Symbol
Maximum CPU Clock
= 32 MHz
Parameter
Variable CPU Clock
1/2TCL = 1 to 32 MHz
Minimum
Maximum
Minimum
Maximum
Unit
t61SR
HOLD input setup time
to CLKOUT
20
–
20
–
ns
t62CC
CLKOUT to HLDA high
or BREQ low delay
–
15.625
–
15.625
ns
t63CC
CLKOUT to HLDA low
or BREQ high delay
–
15.625
–
15.625
ns
t64CC
CSx release 1
–
15
–
15
ns
t65CC
CSx drive
-4
15
-4
15
ns
–
15
–
15
ns
-4
15
-4
15
ns
t66CC
Other signals release
t67CC
Other signals drive
1
1. Partially tested, guaranteed by design characterization
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Electrical Characteristics
Figure 78. External Bus Arbitration (Releasing the Bus)
CLKOUT
t
HOLD
t
1
HLDA
t
BREQ
2)
t
3)
CSx
(P6.x)
t
1)
Others
1. The ST10F269 will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t64.
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Electrical Characteristics
ST10F269Z1-ST10F269Z2
Figure 79. External Bus Arbitration (Regaining the Bus)
2)
C
L
t
H
O
t
H
L
t
B
R
t
t
1)
t
C
S
t
O
t
1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regainsequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F269
requesting the bus.
2. The next ST10F269 driven bus cycle may start here.
21.4.14
High-Speed Synchronous Serial Interface (SSC) Timing
Master Mode
VCC = 5 V ±10%, VSS = 0V, CPU clock = 40 MHz, TA = -40 to +119°C, CL = 50pF
Table 61. Master Mode (max fCPU = 40 MHz)
Symbol
Parameter
t300
t301
t302
t303
t304
t305
CC
CC
CC
CC
CC
CC
t306
CC
t307p
Read data setup time before
SR latch edge, phase error
detection on (SSCPEN = 1)
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SSC clock cycle time
SSC clock high time
SSC clock low time
SSC clock rise time
SSC clock fall time
Write data valid after shift edge
Write data hold after shift edge
1
Maximum baud rate = 10 Mbaud
( = 0001h)
Variable baud rate
(=0001hFFFFh)
Unit
Minimum
100
40
40
–
–
–
Maximum
100
–
–
10
10
15
Minimum
8 TCL
t300/2 - 10
t300/2 - 10
–
–
–
Maximum
262144 TCL
–
–
10
10
15
ns
ns
ns
ns
ns
ns
-2
–
-2
–
ns
37.5
–
2TCL+12.5
–
ns
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ST10F269Z1-ST10F269Z2
Electrical Characteristics
Table 61. Master Mode (max fCPU = 40 MHz) (continued)
Symbol
t308p
t307
t308
Parameter
Maximum baud rate = 10 Mbaud
( = 0001h)
Read data hold time after latch
SR edge, phase error detection on
(SSCPEN = 1)
Read data setup time before
SR latch edge, phase error
detection off (SSCPEN = 0)
Read data hold time after latch
SR edge, phase error detection off
(SSCPEN = 0)
Variable baud rate
(=0001hFFFFh)
Unit
Minimum
Maximum
Minimum
Maximum
50
–
4TCL
–
ns
25
–
2TCL
–
ns
0
–
0
–
ns
1. Timing guaranteed by design.
The formula for SSC Clock Cycle time is: t300 = 4 TCL * ( + 1), where
represents the content of the SSC baud rate register, taken as unsigned 16-bit integer.
VCC = 5 V ±10%, VSS = 0V, CPU clock = 32 MHz, TA = -40 to +125°C, CL = 50 pF
Table 62. Master Mode (max fCPU = 32 MHz)
Symbol
t310
t311
t312
t313
t314
t315
t316
SR
SR
SR
SR
SR
CC
CC
t317p
SR
t318p1 SR
t317
SR
t318
SR
Maximum baud rate =
6.25 Mbaud
( = 0001h)
Parameter
SSC clock cycle time
SSC clock high time
SSC clock low time
SSC clock rise time
SSC clock fall time
Write data valid after shift edge
Write data hold after shift edge
Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
Read data hold time after latch edge,
phase error detection on
(SSCPEN = 1)
Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
Read data hold time after latch edge,
phase error detection off
(SSCPEN = 0)
Variable baud rate
(=0001hFFFFh)
Symb
ol
Minimum
125
52.5
52.5
–
–
–
0
Maximum
–
–
–
10
10
45.25
–
Minimum
8 TCL
t310/2 - 10
t310/2 - 10
–
–
–
0
Maximum
262144 TCL
–
–
10
10
2 TCL + 14
–
t310
t311
t312
t313
t314
t315
t316
78.125
–
4TCL +
15.625
–
t317p
109.375
–
6TCL +
15.625
–
t318p1
6
–
6
–
t317
41.25
–
2TCL + 10
–
t318
1. Timing guaranteed by design.
The formula for SSC Clock Cycle time is: t300 = 4 TCL * ( + 1), where
represents the content of the SSC baud rate register, taken as unsigned 16-bit integer.
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Electrical Characteristics
ST10F269Z1-ST10F269Z2
Figure 80. SSC Master Timing
t
2)
1)
t
t
SCLK
t
t
MTSR
1st Out Bit
t
2nd Out Bit
t
t
t
2nd.In Bit
1st.In Bit
t
Last Out Bit
t
MRST
t
t
Last.In Bit
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift
edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high
transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
Slave mode
VCC = 5 V ±10%, VSS = 0V, CPU clock = 40 MHz, TA = -40 to +119°C, CL = 50 pF
Table 63. Slave Mode (max fCPU = 40 MHz)
Symbol
Maximum baud rate =
10 Mbaud
( = 0001h)
Parameter
Variable baud rate
(=0001hFFFFh)
Minimum
Maximum
Minimum
Maximum
Unit
t310
SR SSC clock cycle time
100
100
8 TCL
262144 TCL
ns
t311
SR SSC clock high time
40
–
t310/2 - 10
–
ns
t312
SR SSC clock low time
40
–
t310/2 - 10
–
ns
t313
SR SSC clock rise time
–
10
–
10
ns
t314
SR SSC clock fall time
–
10
–
10
ns
t315
CC Write data valid after shift edge
–
39
–
2 TCL + 14
ns
t316
CC Write data hold after shift edge
0
–
0
–
ns
t317p
Read data setup time before latch
SR edge, phase error detection on
(SSCPEN = 1)
62
–
4TCL + 12
–
ns
87
–
6TCL + 12
–
ns
Read data hold time after latch edge,
t318p1 SR phase error detection on
(SSCPEN = 1)
t317
Read data setup time before latch
SR edge, phase error detection off
(SSCPEN = 0)
6
–
6
–
ns
t318
Read data hold time after latch edge,
SR phase error detection off
(SSCPEN = 0)
31
–
2TCL + 6
–
ns
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Electrical Characteristics
The formula for SSC Clock Cycle time is: t310 = 4 TCL * ( + 1), where
represents the content of the SSC baud rate register, taken as unsigned 16-bit integer.
VCC = 5 V ±10%, VSS = 0V, CPU clock = 32 MHz, TA = -40 to +125°C, CL = 50 pF
Table 64. Slave Mode (max fCPU = 32 MHz)
Symbol
Maximum baud rate =
6.25 Mbaud
( = 0001h)
Parameter
Minimum
Maximum
Variable baud rate
(=0001hFFFFh)
Unit
Minimum
Maximum
t310
SR SSC clock cycle time
125
–
8 TCL
262144 TCL
ns
t311
SR SSC clock high time
52.5
–
t310/2 - 10
–
ns
t312
SR SSC clock low time
52.5
–
t310/2 - 10
–
ns
t313
SR SSC clock rise time
–
10
–
10
ns
t314
SR SSC clock fall time
–
10
–
10
ns
t315
CC Write data valid after shift edge
–
45.25
–
2 TCL + 14
ns
t316
CC Write data hold after shift edge
0
–
0
–
ns
t317p
Read data setup time before latch
SR edge, phase error detection on
(SSCPEN = 1)
78.125
–
4TCL +
15.625
–
ns
109.375
–
6TCL +
15.625
–
ns
6
–
6
–
ns
41.25
–
2TCL + 10
–
ns
Read data hold time after latch edge,
t318p1 SR phase error detection on
(SSCPEN = 1)
t317
Read data setup time before latch
SR edge, phase error detection off
(SSCPEN = 0)
t318
Read data hold time after latch edge,
SR phase error detection off
(SSCPEN = 0)
The formula for SSC Clock Cycle time is: t310 = 4 TCL * ( + 1), where
represents the content of the SSC baud rate register, taken as unsigned 16-bit integer.
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ST10F269Z1-ST10F269Z2
Figure 81. SSC Slave Timing
t
1)
2)
t
t
SCLK
t
t
MRST
1st Out Bit
t
2nd Out Bit
1st.In Bit
t
t
Last Out Bit
t
MTSR
t
t
2nd.In Bit
t
Last.In Bit
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift
edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high
transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
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ST10F269Z1-ST10F269Z2
22
Package Mechanical data
Package Mechanical data
Figure 82. Package Outline TQFP144 (20 x 20 x 1.40 mm)
!
!
E
!
%
%
%
"
MM
INCH
3%!4).'0,!.%
C
,
$
$
$
,
+
Dimensions
A
A1
A2
B
C
D
D1
D3
e
E
E1
E3
L
L1
K
Millimeters 1
Minimum
0.05
1.35
0.17
0.09
0.45
Typical
Inches (approx)
Maximum
Minimum
1.60
0.15
1.45
0.27
0.20
1.40
0.22
22.00
20.00
17.50
0.50
22.00
20.00
17.50
0.60
1.00
MM
INCH
'!'%0,!.%
0.75
0.002
0.053
0.0067
0.0035
0.018
Typical
0.055
0.0087
0.866
0.787
0.689
0.020
0.866
0.787
0.689
0.024
0.039
Maximum
0.063
0.006
0.057
0.011
0.008
0.030
0° (Minimum), 7° (Maximum)
1. Package dimensions are in mm. The dimensions quoted in inches are rounded.
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Ordering Information
23
ST10F269Z1-ST10F269Z2
Ordering Information
Table 65. Ordering information
Sales type
Flash
Program
Memory
(bytes)
Temperature range
Package
ST10F269Z2T3
256K
-40°C to +125°C if CPU clock ≤ 32 MHz<
-40°C to +119°C if 32 MHz < CPU clock ≤ 40 MHz
TQFP144 (20 x 20 x 1.40 mm)
ST10F269Z2T6
256K
-40°C to +85°C if CPU clock ≤ 32 MHz<
-40°C to +79°C if 32 MHz < CPU clock ≤ 40 MHz
TQFP144 (20 x 20 x 1.40 mm)
ST10F269Z1T3
128K
-40°C to +125°C if CPU clock ≤ 32 MHz<
-40°C to +119°C if 32 MHz < CPU clock ≤ 40 MHz
TQFP144 (20 x 20 x 1.40 mm)
ST10F269Z1T6
128K
-40°C to +85°C if CPU clock ≤ 32 MHz<
-40°C to +79°C if 32 MHz < CPU clock ≤ 40 MHz
TQFP144 (20 x 20 x 1.40 mm)
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Known limitations
24
Known limitations
24.1
Description
This section describes the functional and electrical problems known in the D revision of the
ST10F269Zxxx-D.
The revision number can be found in the third line on the ST10F269 package. It looks like:
’xxxxxxxxx D’, where "D" identifies the revision number.
24.2
Functional problems
The following malfunctions are known in this step:
24.2.1
PWRDN.1 - Execution of PWRDN Instruction
When instruction PWRDN is executed while pin NMI is at a high level (if PWRDCFG bit is
clear in SYSCON register) or while at least one of the port 2 pins used to exit from powerdown mode (if PWRDCFG bit is set in SYSCON register) is at the active level, power down
mode is not entered, and the PWRDN instruction is ignored.
However, under the conditions described below, the PWRDN instruction is not ignored, and
no further instructions are fetched from external memory, i.e. the CPU is in a quasi-idle
state.
This problem only occurs in on of the following situations:
Note:
•
The instructions following the PWRDN instruction are located in an external memory,
and a multiplexed bus configuration with memory tristate waitstate (bit MT-TCx = 0) is
used.
•
The instruction preceding the PWRDN instruction writes to external memory or an
XPeripheral (XRAM,CAN), and the instructions following the PWRDN instruction are
located in external memory. In this case, the problem occurs for any bus configuration.
The on-chip peripherals are still working correctly, in particular the Watchdog Timer, if not
disabled, resets the device upon an overflow. Interrupts and PEC transfers, however, cannot
be processed. In case NMI is asserted low while the device is in this quasi-idle state, powerdown mode is entered. No problem occurs if the NMI pin is low (if PWRDCFG = 0) or if all
P2 pins used to exit from power-down mode are at inactive level (if PWRDCFG = 1): the
chip normally enters powerdown mode.
Workaround
Ensure that no instruction that writes to external memory or an XPeripheral precedes the
PWRDN instruction, otherwise insert a NOP instruction in front of PWRDN. When a
multiplexed bus with memory tristate wait state is used, the PWRDN instruction must be
executed from internal RAM or XRAM.
24.2.2
MAC.9 - CoCMP Instruction Inverted Operands
The ST10 Family Programming Manual describes the CoCMP instruction as: subtracts a
40-bit signed operand from th 40-bit accumulator content (acc - op2\op1), and updates the
N, Z and C flags in the MSW register, leaving the accumulator unchanged. On the device
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Known limitations
ST10F269Z1-ST10F269Z2
the reverse operation (op2\op1 - acc) has been implemented in the Mac Unit. Therefore, the
N and C flags are set according to the reverse operation (Z flag is not affected).
Workaround
Change interpretation of the N and C flags in the MSW register.
Example:
MOV R12, #07h
MOV R13, #06h
MOV R14, #0
CoLOAD R14, R12; Accumulator = 70000h
CoCMP R14, R13; Compares 70000h to 60000h
Here the content of MSW is 0500h, i.e. C = 1, Z = 0 and N = 1.
To test if the Accumulator was greater than or equal the compared value, the "normal" test,
according to the description in the ST10 Programming Manual, would be:
JNB MSW.10, Greater ; If C flag cleared, then greater than or equal
With the implementation, this test does not provide the expected result.
To obtain the correct comparison, use instead:
JB MSW.10, Greater ; C flag set: 60000h < 70000h (60000h-70000h implemented)
; i.e. the accumulator is greater than or equal compared value
24.2.3
MAC.10 - E Flag Evaluation for CoSHR and CoASHR Instructions
when Saturation Mode is Enabled
The Logical and the Arithmetic Right Shift instructions (CoSHR/CoASHR) are specified not
to be affected by the saturation mode (MS bit of the MCW register): the shift operation is
always made on the 40 bits of the accumulator. The result shifted in the accumulator is
never saturated. Only when the saturation mode is enabled, the evaluation of the E Flag (in
the MSW register) is erroneous.
Comment to the example:
In this example below (Table 66), the E Flag is kept cleared however MAE is used: bit 0 of
MAE has been shifted into bit 15 of MAH. The MAE part has been used and it contents
significant bits but the E Flag has not been set.
The content of the flags is given after the execution of the instruction.
Table 66. MAC.10 Example
MS Bit is Set, Saturation Mode is Enabled
Code
Accumulator value
(Hexa)
Status of Flags After Instruction Execution
SL
E
SV
C
Z
N
Remark
MOV R5, #5555h
0x-- ---- ----
-
-
-
-
-
-
-
CoLOAD R5, R5
0x00 5555 5555
0
0
0
0
0
0
Right
NOP
0x00 5555 5555
0
0
0
0
0
0
Right
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Known limitations
Table 66. MAC.10 Example (continued)
MS Bit is Set, Saturation Mode is Enabled
Status of Flags After Instruction Execution
Accumulator value
(Hexa)
Code
SL
E
SV
C
Z
N
Remark
MOV MSW, #007Fh
7F 5555 5555
0
0
0
0
0
0
Right
NOP
7F 5555 5555
0
0
0
0
0
0
Right
CoSHR #1
3F AAAA AAAA
0
0*
0
0
0
0
*E is wrong
Workaround
If the MAE flag is used, the saturation mode must be disabled before running Logical and/or
Arithmetic Right Shift instructions and re-enable just after.
24.2.4
ST_PORT.3 - Bad Behavior of Hysteresis Function
on Input Falling Edge
In the following conditions, a slow falling edge on a ST10F269 input may generate multiple
events:
•
A falling edge is occurring.
•
AND the falling edge has a transition time between Vih and Vil longer than the CPU
clock period.
Figure 83. Bad behavior of hysteresis function on input falling edge
Vih
Input signal
(falling edge)
Vil
“1”
Internal
signal
“0”
t2
t1
PROBLEM
(t2 - t1) > 1/Fcpu
Workaround
Add external hardware on the ST10 input in order to have a fast falling edge (lower than
1/Fcpu).
Table 67. History of Fixed Functional Problems of the ST10F269Zxxx-D
Name of modification
ST_PORT.2
Short description
Wrong Port Direction after Return From Power Down Mode
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D
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ST10F269Z1-ST10F269Z2
Table 68. Summary of Remaining Functional Problems Known on the ST10F269Zxxx-D
Name
Short description
PWRDN.1
Execution of PWRDN Instruction
MAC.9
CoCMP Instruction Inverted Operands
MAC.10
E Flag Evaluation for CoSHR and CoASHR Instructions when Saturation Mode is Enabled
ST_PORT.3
Bad Behavior of Hysteresis Function on Input Falling Edge
24.3
Deviations from DC/AC preliminary specification
Note about on-chip oscillator
The XTAL2 output is not designed to provide a valid signal when XTAL1 is supplied by an
external clock signal. It may happen, if the external clock signal is not perfectly symmetrical
and centered on VDD / 2, that XTAL2 signal is not equal to XTAL1. This is due to the design
of the oscillator, which has a auto-adaptation gain control dedicated to external crystal.
If an external clock signal is directly provided on XTAL1 pin, then leave XTAL2 pin
disconnected to achieve the lowest consumption of the on-chip oscillator.
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25
Revision history
Revision history
Table 69. Document revision history
Date
Revision
15-Sep-2003
1
Initial release.
2
– PQFP144 package removed (no more in
production)
– The limitations previously appearing a specific
Errata Sheet part, are now available in
Section 24: Known limitations.
28-Sep-2017
Changes
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