ST10F272M
16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
Datasheet − production data
Features
■
■
■
16-bit CPU with DSP functions
– 50ns instruction cycle time at 40 MHz max
CPU clock
– Multiply/accumulate unit (MAC) 16 x 16-bit
multiplication, 40-bit accumulator
– Enhanced boolean bit manipulations
– Single-cycle context switching support
On-chip memories
– 256 Kbyte Flash memory (32-bit fetch)
– Single voltage Flash memories with
erase/program controller and 100 K
erasing/programming cycles.
– Up to 16 Mbyte linear address space for
code and data (5 Mbytes with CAN or I2C)
– 2 Kbyte internal RAM (IRAM)
– 18 Kbyte extension RAM (XRAM)
– Programmable external bus configuration &
characteristics for different address ranges
– 5 programmable chip-select signals
– Hold-acknowledge bus arbitration support
Interrupt
– 8-channel peripheral event controller for
single cycle interrupt driven data transfer
– 16-priority-level interrupt system with 56
sources, sampling rate down to 25 ns
/4)3
[[PP
*$3*5,
■
24-channel A/D converter
– 16-channel 10-bit, accuracy ± 2 LSB
– 8-channel 10-bit, accuracy ± 5 LSB
– 4.85 µs minimum conversion time
■
4-channel PWM unit + 4-channel XPWM
■
2 CAN 2.0B interfaces operating on 1 or 2 CAN
busses (64 or 2x32 message, C-CAN version)
■
Fail-safe protection
– Programmable watchdog timer
– Oscillator watchdog
■
On-chip bootstrap loader
■
Clock generation
– On-chip PLL with 4 to 8 MHz oscillator
– Direct or prescaled clock input
■
Real-time clock and 32 kHz on-chip oscillator
■
Up to 111 general purpose I/O lines
– Individually programmable as input, output
or special function
– Programmable threshold (hysteresis)
■
Timers
– 2 multi-functional general purpose timer
units with 5 timers
■
Two 16-channel capture/compare units
■
Idle, power-down and stand-by modes
■
Serial channels
– 2 synch./asynch. serial channels
– 2 high-speed synchronous channels
– One I2C standard interface
■
Single voltage supply: 5 V ± 10 % (embedded
regulator for 1.8 V core supply)
■
Temperature range: -40 to +125 °C
September 2013
This is information on a product in full production.
Doc ID 12968 Rev 4
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1
Contents
ST10F272M
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2
Special characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.1
1.2.1 X-peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.2
1.2.2 Improved supply ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.2
Modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.3
Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4
Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5
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5.2.1
5.4.1
Flash control register 0 low (FCR0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4.2
Flash control register 0 high (FCR0H) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4.3
Flash control register 1 low (FCR1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4.4
Flash control register 1 high (FCR1H) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4.5
Flash data register 0 low (FDR0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4.6
Flash data register 0 high (FDR0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4.7
Flash data register 1 low (FDR1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.8
Flash data register 1 high (FDR1H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.9
Flash address register low (FARL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.10
Flash address register high (FARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4.11
Flash error register (FER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.5.1
Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.5.2
Flash non-volatile write protection I register (FNVWPIR) . . . . . . . . . . . 36
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5.5.3
Flash non-volatile access protection register 0 (FNVAPR0) . . . . . . . . . 36
5.5.4
Flash non-volatile access protection register 1 low (FNVAPR1L) . . . . . 36
5.5.5
Flash non-volatile access protection register 1 high (FNVAPR1H) . . . . 37
5.5.6
X-bus Flash volatile temporary access unprotection register
(XFVTAUR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5.7
Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.5.8
Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.5.9
Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.6
Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.7
Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1
Selection among user-code, standard or selective bootstrap . . . . . . . . . . 43
6.2
Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3
Alternate and selective boot mode (ABM and SBM) . . . . . . . . . . . . . . . . 44
6.3.1
Activation of the ABM and SBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.2
User mode signature integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.3
Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1
Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2
Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.3
MAC co-processor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8
External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9
Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.1
X-peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2
Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10
Capture/compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11
General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12
11.1
GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.2
GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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ST10F272M
Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.2
I/O’s special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.3
13.2.1
Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.2.2
Input threshold control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
14
A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
15
Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
15.1
Asynchronous/synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . 68
15.2
ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
15.3
ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
15.4
High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 69
16
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
17
CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
17.1
Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
17.2
CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
17.2.1
Single CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
17.2.2
Multiple CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
17.2.3
Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
18
Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
19
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
20
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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20.1
Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
20.2
Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
20.3
Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
20.4
Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
20.5
Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
20.6
Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
20.7
Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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Contents
20.8
Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
20.9
Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
21.1
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
21.2
Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
21.3
21.2.1
Protected power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
21.2.2
Interruptible power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
21.3.1
Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
21.3.2
Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
21.3.3
Real-time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
21.3.4
Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
22
Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 107
23
Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
24
23.1
Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
23.2
X-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
23.3
Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
23.4
Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
24.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
24.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
24.3
Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
24.4
Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
24.5
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
24.6
Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
24.7
A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
24.8
24.7.1
Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
24.7.2
A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
24.7.3
Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
24.7.4
Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
24.8.1
Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
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24.8.2
Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
24.8.3
Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
24.8.4
Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
24.8.5
Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
24.8.6
Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
24.8.7
Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
24.8.8
Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
24.8.9
PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
24.8.10 PLL lock/unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
24.8.11 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
24.8.12 32 kHz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
24.8.13 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
24.8.14 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
24.8.15 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
24.8.16 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
24.8.17 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
24.8.18 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
24.8.19 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
24.8.20 High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . . 168
25
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
25.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
25.2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .LQFP144 mechanical data 172
26
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Summary of IFlash address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Address space reserved for the Flash module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Flash modules sectorization (read operations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash modules sectorization (write operations or with ROMS1 = ‘1’ or bootstrap mode) . . 26
Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Banks (BxS) and sectors (BxFy) status bits meaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Flash data register 0 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Flash data register 1 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Flash non-volatile write protection I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Flash non-volatile access protection register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Flash non-volatile access protection register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Flash non-volatile access protection register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
X-bus Flash volatile temporary access unprotection register . . . . . . . . . . . . . . . . . . . . . . . 37
Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ST10F272M boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
MAC instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
X-interrupt detailed mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
CAPCOM timer input frequencies, resolutions and periods at 40 MHz . . . . . . . . . . . . . . . 57
GPT1 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 59
GPT2 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 60
PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 62
ASC asynchronous baudrates by reload value and deviation errors (fCPU = 40 MHz) . . . . 68
ASC synchronous baudrates by reload value and deviation errors (fCPU = 40 MHz) . . . . . 69
Synchronous baudrate and reload values (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . 70
WDTREL reload value (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 100
Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
List of special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
List of X-bus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
List of Flash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
IDMANUF register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Doc ID 12968 Rev 4
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List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
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ST10F272M
IDCHIP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
IDMEM register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
IDPROG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Flash data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
A/D converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
PLL characteristics (VDD = 5 V ± 10 %, VSS = 0 V, TA = -40 to +125 °C) . . . . . . . . . . . . 148
Main oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Main oscillator negative resistance (module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
32 kHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Minimum values of negative resistance (module) for 32 kHz oscillator . . . . . . . . . . . . . . 150
External clock drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Multiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Demultiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
CLKOUT and READY timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
External bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
SSC slave mode timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Doc ID 12968 Rev 4
ST10F272M
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ST10F272M on-chip memory mapping (ROMEN = 1/XADRS = 800Bh - reset value) . . . . 24
Flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Write operation control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
CPU block diagram (MAC unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
X-interrupt basic structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . . 73
Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . . 73
Connection to two different CAN buses (example, gateway application) . . . . . . . . . . . . . . 74
Connection to one CAN bus with internal parallel mode enabled. . . . . . . . . . . . . . . . . . . . 74
Asynchronous power-on reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Asynchronous power-on reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Asynchronous hardware reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Asynchronous hardware reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Synchronous short/long hardware reset (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Synchronous short/long hardware reset (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Synchronous long hardware reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Synchronous long hardware reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SW/WDT unidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SW/WDT unidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SW/WDT bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SW/WDT bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SW/WDT bidirectional reset (EA = 0) followed by a HW reset . . . . . . . . . . . . . . . . . . . . . . 93
Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . 97
Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . 98
Port0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . . 101
External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Supply current versus the operating frequency (run and idle modes) . . . . . . . . . . . . . . . 129
A/D conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
ST10F272M PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Doc ID 12968 Rev 4
9/176
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
10/176
ST10F272M
External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE. . . . 155
External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE. . 156
External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS. . . 157
External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS . 158
External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE . . . . . . . 161
External memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE . . . . . 162
External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS . . . . 163
External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS . . 164
CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
LQFP144 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Doc ID 12968 Rev 4
ST10F272M
Introduction
1
Introduction
1.1
Description
The ST10F272M device is a new derivative of the STMicroelectronics ST10 family of 16-bit
single-chip CMOS microcontrollers.
The ST10F272M combines high CPU performance (up to 20 million instructions per second)
with high peripheral functionality and enhanced I/O capabilities. It also provides on-chip
high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation
via PLL.
The ST10F272M is processed in 0.18mm CMOS technology. The MCU core and the logic is
supplied with a 5 V to 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V
supply and I/Os work at 5 V.
The ST10F272M is an optimized version of the ST10F272E, upward compatible with the
following set of differences:
●
Maximum CPU frequency is 40 MHz
●
Reduced range for the Standby Voltage: VStby must be in the range of 4.5 to 5.5 V.
●
Identification registers: the IDMEM register reflects the Flash type difference and can
be used to differentiate the two devices by software
●
Improved EMC behavior thanks to the introduction of an internal RC filter on the 5 V for
the ballast transistors
1.2
Special characteristics
1.2.1
1.2.1 X-peripheral clock gating
This new feature have been implemented on the ST10F272M: Once the EINIT instruction
has been executed, only the X-peripherals enabled in the XPERCON register will be
clocked.
The new feature allows to reduce the power consumption and also should improve the
emissions as it avoids to propagate useless clock signals across the device.
1.2.2
1.2.2 Improved supply ring
An RC filter has been introduced in the 5 V power supply ring of the ballast transistor. In
addition, the supply rings for the internal voltage regulators and the I/Os have been split.
These two modifications should improve the behavior of the device regarding conducted
emissions.
Doc ID 12968 Rev 4
11/176
Introduction
Figure 1.
ST10F272M
Logic symbol
9
9'' 966
;7$/
;7$/
;7$/
;7$/
3RUW
ELW
567,1
567287
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3RUW
ELW
3RUW
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3RUW
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53'
*$3*5,
12/176
Doc ID 12968 Rev 4
ST10F272M
Pin data
Pin configuration (top view)
67)0
3+$'
3/$'
3/$'
3/$'
3/$'
3/$'
3/$'
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Doc ID 12968 Rev 4
13/176
Pin data
Table 1.
Symbol
ST10F272M
Pin description
Pin
1-8
P6.0 - P6.7
Type
I/O
Function
8-bit bidirectional I/O port, bitwise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
high impedance state. Port 6 outputs can be configured as push-pull or open
drain drivers. The input threshold of port 6 is selectable (TTL or CMOS). The
following port 6 pins have alternate functions:
1
O
P6.0
CS0
Chip select 0 output
...
...
...
...
...
5
O
P6.4
CS4
Chip select 4 output
I
P6.5
HOLD
External master hold request input
SCLK1
SSC1: master clock output/slave clock input
HLDA
Hold acknowledge output
MTSR1
SSC1: master-transmitter/slave-receiver I/O
BREQ
Bus request output
MRST1
SSC1: master-receiver/slave-transmitter I/O
6
I/O
O
P6.6
7
I/O
O
P6.7
8
I/O
9-16
I/O
8-bit bidirectional I/O port, bitwise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
high impedance state. Port 8 outputs can be configured as push-pull or open
drain drivers. The input threshold of port 8 is selectable (TTL or CMOS).
The following port 8 pins have alternate functions:
I/O
P8.0
CC16IO
CAPCOM2: CC16 capture input/compare output
XPWM0
PWM1: channel 0 output
9
O
...
P8.0 - P8.7
...
...
...
...
I/O
P8.3
CC19IO
CAPCOM2: CC19 capture input/compare output
XPWM0
PWM1: channel 3 output
12
O
13
I/O
P8.4
CC20IO
CAPCOM2: CC20 capture input/compare output
14
I/O
P8.5
CC21IO
CAPCOM2: CC21 capture input/compare output
I/O
P8.6
CC22IO
CAPCOM2: CC22 capture input compare output
RxD1
ASC1: Data input (asynchronous) or I/O (synchronous)
CC23IO
CAPCOM2: CC23 capture input/compare output
TxD1
ASC1: Clock/data output (asynchronous/synchronous)
15
I/O
I/O
P8.7
16
O
14/176
Doc ID 12968 Rev 4
ST10F272M
Table 1.
Pin data
Pin description (continued)
Symbol
P7.0 - P7.7
P5.0 - P5.9
P5.10 - P5.15
P2.0 - P2.7
P2.8 - P2.15
Pin
Type
Function
19-26
I/O
8-bit bidirectional I/O port, bitwise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
high impedance state. Port 7 outputs can be configured as push-pull or open
drain drivers. The input threshold of port 7 is selectable (TTL or CMOS).
The following port 7 pins have alternate functions:
19
O
P7.0
POUT0
PWM0: channel 0 output
...
...
...
...
...
22
O
P7.3
POUT3
PWM0: channel 3 output
23
I/O
P7.4
CC28IO
CAPCOM2: CC28 capture input/compare output
...
...
...
...
...
26
I/O
P7.7
CC31IO
CAPCOM2: CC31 capture input/compare output
27-36
39-44
I
I
16-bit input-only port with Schmitt-trigger characteristics. The pins of port 5 can
be the analog input channels (up to 16) for the A/D converter, where P5.x equals
ANx (Analog input channel x), or they are timer inputs. The input threshold of
Port 5 is selectable (TTL or CMOS). The following port 5 pins have alternate
functions:
39
I
P5.10
T6EUD
GPT2: timer T6 external up/down control input
40
I
P5.11
T5EUD
GPT2: timer T5 external up/down control input
41
I
P5.12
T6IN
GPT2: timer T6 count input
42
I
P5.13
T5IN
GPT2: timer T5 count input
43
I
P5.14
T4EUD
GPT1: timer T4 external up/down control input
44
I
P5.15
T2EUD
GPT1: timer T2 external up/down control input
47-54
57-64
I/O
16-bit bidirectional I/O port, bitwise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
high impedance state. Port 2 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS).
The following port 2 pins have alternate functions:
47
I/O
P2.0
CC0IO
CAPCOM: CC0 capture input/compare output
...
...
...
...
...
54
I/O
P2.7
CC7IO
CAPCOM: CC7 capture input/compare output
57
I/O
P2.8
CC8IO
CAPCOM: CC8 capture input/compare output
EX0IN
Fast external interrupt 0 input
I
...
...
...
...
...
64
I/O
P2.15
CC15IO
CAPCOM: CC15 capture input/compare output
I
EX7IN
Fast external interrupt 7 input
I
T7IN
CAPCOM2: timer T7 count input
Doc ID 12968 Rev 4
15/176
Pin data
Table 1.
ST10F272M
Pin description (continued)
Symbol
P3.0 - P3.5
P3.6 - P3.13,
P3.15
16/176
Pin
Type
Function
65-70,
73-80,
81
I/O
I/O
I/O
15-bit (P3.14 is missing) bidirectional I/O port, bitwise programmable for input or
output via direction bit. Programming an I/O pin as input forces the
corresponding output driver to high impedance state. Port 3 outputs can be
configured as push-pull or open drain drivers. The input threshold of port 3 is
selectable (TTL or CMOS). The following port 3 pins have alternate functions:
65
I
P3.0
T0IN
CAPCOM1: timer T0 count input
66
O
P3.1
T6OUT
GPT2: timer T6 toggle latch output
67
I
P3.2
CAPIN
GPT2: register CAPREL capture input
68
O
P3.3
T3OUT
GPT1: timer T3 toggle latch output
69
I
P3.4
T3EUD
GPT1: timer T3 external up/down control input
70
I
P3.5
T4IN
GPT1; timer T4 input for count/gate/reload/capture
73
I
P3.6
T3IN
GPT1: timer T3 count/gate input
74
I
P3.7
T2IN
GPT1: timer T2 input for count/gate/reload/capture
75
I/O
P3.8
MRST0
SSC0: master-receiver/slave-transmitter I/O
76
I/O
P3.9
MTSR0
SSC0: master-transmitter/slave-receiver I/O
77
O
P3.10
TxD0
ASC0: clock/data output (asynchronous/synchronous)
78
I/O
P3.11
RxD0
ASC0: data input (asynchronous) or I/O (synchronous)
79
O
P3.12
BHE
External memory high byte enable signal
WRH
External memory high byte write strobe
80
I/O
P3.13
SCLK0
SSC0: master clock output/slave clock input
81
O
P3.15
CLKOUT
System clock output
(programmable divider on CPU clock)
Doc ID 12968 Rev 4
ST10F272M
Table 1.
Symbol
Pin data
Pin description (continued)
Pin
Type
Function
85-92
I/O
Port 4 is an 8-bit bidirectional I/O port. It is bitwise programmable for input or
output via direction bit. Programming an I/O pin as input forces the
corresponding output driver to high impedance state. The input threshold is
selectable (TTL or CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured
as push-pull or open drain drivers. In case of an external bus configuration,
port 4 can be used to output the segment address lines:
85
O
P4.0
A16
Segment address line
86
O
P4.1
A17
Segment address line
87
O
P4.2
A18
Segment address line
88
O
P4.3
A19
Segment address line
A20
Segment address line
CAN2_RxD
CAN2: receive data input
I/O
SCL
I2C Interface: serial clock
O
A21
Segment address line
CAN1_RxD
CAN1: receive data input
I
CAN2_RxD
CAN2: receive data input
O
A22
Segment address line
CAN1_TxD
CAN1: transmit data output
O
CAN2_TxD
CAN2: transmit data output
O
A23
Most significant segment address line
CAN2_TxD
CAN2: transmit data output
SDA
I2C Interface: serial data
O
P4.0 - P4.7
89
90
91
92
I
I
O
O
I/O
RD
WR/WRL
95
96
P4.4
P4.5
P4.6
P4.7
O
External memory read strobe. RD is activated for every external instruction or
data read access.
O
External memory write strobe. In WR-mode this pin is activated for every
external data write access. In WRL mode this pin is activated for low byte data
write accesses on a 16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in the SYSCON register for mode selection.
READY/
READY
97
I
Ready input. The active level is programmable. When the ready function is
enabled, the selected inactive level at this pin, during an external memory
access, will force the insertion of waitstate cycles until the pin returns to the
selected active level.
ALE
98
O
Address latch enable output. In case of use of external addressing or of
multiplexed mode, this signal is the latch command of the address lines.
Doc ID 12968 Rev 4
17/176
Pin data
Table 1.
ST10F272M
Pin description (continued)
Symbol
EA / VSTBY
Pin
99
Type
Function
I
External access enable pin.
A low level applied to this pin during and after reset forces the ST10F272M to
start the program from the external memory space. A high level forces
ST10F272M to start in the internal memory space. This pin is also used (when
Stand-by mode is entered, that is ST10F272M under reset and main VDD turned
off) to bias the 32 kHz oscillator amplifier circuit and to provide a reference
voltage for the low-power embedded voltage regulator which generates the
internal 1.8V supply for the RTC module (when not disabled) and to retain data
inside the Stand-by portion of the XRAM (16 Kbyte). It can range from 4.5 to 5.5
V. In running mode, this pin can be tied low during reset without affecting 32 kHz
oscillator, RTC and XRAM activities, since the presence of a stable VDD
guarantees the proper biasing of all those modules.
Two 8-bit bidirectional I/O ports P0L and P0H, bitwise programmable for input or
output via direction bit. Programming an I/O pin as input forces the
corresponding output driver to high impedance state. The input threshold of
Port 0 is selectable (TTL or CMOS). In case of an external bus configuration,
PORT0 serves as the address (A) and as the address/data (AD) bus in
multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.
Demultiplexed bus modes
P0L.0 - P0L.7, 100-107,
P0H.0,
108,
P0H.1 - P0H.7 111-117
I/O
Data path width
8-bit
16-bit
P0L.0 – P0L.7:
D0 – D7
D0 - D7
P0H.0 – P0H.7:
I/O
D8 - D15
Multiplexed bus modes
Data path width
8-bit
16-bit
P0L.0 – P0L.7:
AD0 – AD7
AD0 - AD7
P0H.0 – P0H.7:
A8 – A15
AD8 - AD15
Two 8-bit bidirectional I/O ports P1L and P1H, bitwise programmable for input or
output via direction bit. Programming an I/O pin as input forces the
corresponding output driver to high impedance state. port1 is used as the 16-bit
address bus (A) in demultiplexed bus modes: If at least BUSCONx is configured
such that the demultiplexed mode is selected, the pins of port1 are not available
for general purpose I/O function. The input threshold of port 1 is selectable (TTL
or CMOS). The pins of P1L also serve as the additional (up to eight) analog input
channels for the A/D converter, where P1L.x equals ANy (Analog input channel
y, where y = x + 16). This additional function has a higher priority on
demultiplexed bus function. The following port1 pins have alternate functions:
118-125
128-135
I/O
132
I
P1H.4
CC24IO
CAPCOM2: CC24 capture input
133
I
P1H.5
CC25IO
CAPCOM2: CC25 capture input
134
I
P1H.6
CC26IO
CAPCOM2: CC26 capture input
135
I
P1H.7
CC27IO
CAPCOM2: CC27 capture input
XTAL1
138
I
XTAL1
Main oscillator amplifier circuit and/or external clock input
XTAL2
137
O
XTAL2
Main oscillator amplifier circuit output
P1L.0 - P1L.7,
P1H.0 - P1H.7
18/176
Doc ID 12968 Rev 4
ST10F272M
Table 1.
Symbol
Pin data
Pin description (continued)
Pin
Type
Function
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high/low and rise/fall times specified in
the AC characteristics must be observed.
XTAL3
143
I
XTAL3
32 kHz oscillator amplifier circuit input
XTAL4
144
O
XTAL4
32 kHz oscillator amplifier circuit output
When 32 kHz oscillator amplifier is not used, to avoid spurious consumption,
XTAL3 must be tied to ground while XTAL4 has to be left open. Additionally, bit
OFF32 in RTCCON register must be set. 32 kHz oscillator can only be driven by
an external crystal, and not by a different clock source.
RSTIN
140
I
Reset input with CMOS Schmitt-trigger characteristics. A low level at this pin for
a specified duration while the oscillator is running resets the ST10F272M. An
internal pull-up resistor permits power-on reset using only a capacitor connected
to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON
register), the RSTIN line is pulled low for the duration of the internal reset
sequence.
RSTOUT
141
O
Internal reset indication output. This pin is driven to a low level during hardware,
software or watchdog timer reset. RSTOUT remains low until the EINIT (end of
initialization) instruction is executed.
NMI
142
I
Non-maskable interrupt input. A high to low transition at this pin causes the CPU
to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when
the PWRDN (power-down) instruction is executed, the NMI pin must be low in
order to force the ST10F272M to go into power-down mode. If NMI is high and
PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal
mode. If not used, pin NMI should be pulled high externally.
VAREF
37
-
A/D converter reference voltage and analog supply
VAGND
38
-
A/D converter reference and analog ground
RPD
84
-
Timing pin for the return from interruptible power-down mode and synchronous/
asynchronous reset selection.
VDD
17, 46,
72,82,93
, 109,
126, 136
-
Digital supply voltage = +5 V during normal operation, idle and power-down
modes. It can be turned off when stand-by RAM mode is selected.
VSS
18,45,
55,71,
83,94,
110,
127, 139
-
Digital ground
V18
56
-
1.8 V decoupling pin: a decoupling capacitor (typical value of 10 nF, max 100 nF)
must be connected between this pin and nearest VSS pin.
Doc ID 12968 Rev 4
19/176
Functional description
3
ST10F272M
Functional description
The architecture of the ST10F272M combines advantages of both RISC and CISC
processors and an advanced peripheral subsystem. The block diagram gives an overview of
the different on-chip components and the high bandwidth internal bus structure of the
ST10F272M.
Figure 3.
Block diagram
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20/176
Doc ID 12968 Rev 4
ST10F272M
4
Memory organization
Memory organization
The memory space of the ST10F272M is configured in a unified memory architecture. Code
memory, data memory, registers and I/O ports are organized within the same linear address
space of 16 Mbytes. The entire memory space can be accessed bytewise or wordwise.
Particular portions of the on-chip memory have additionally been made directly bit
addressable.
IFlash: 256 Kbytes of on-chip Flash memory. It is divided in eight blocks (B0F0...B0F7) that
constitute the bank 0. When bootstrap mode is selected, the test-Flash block B0TF
(4 Kbytes) appears at address 00’0000h: refer to Section 5: Internal Flash memory for more
details on memory mapping in boot mode. The summary of address range for IFlash is the
following:
Table 2.
Summary of IFlash address range
Blocks
User mode
Size (bytes)
B0TF
Not visible
4K
B0F0
00’0000h - 00’1FFFh
8K
B0F1
00’2000h - 00’3FFFh
8K
B0F2
00’4000h - 00’5FFFh
8K
B0F3
00’6000h - 00’7FFFh
8K
B0F4
01’8000h - 01’FFFFh
32K
B0F5
02’0000h - 02’FFFFh
64K
B0F6
03’0000h - 03’FFFFh
64K
B0F7
04’0000h - 04’FFFFh
64K
IRAM: 2 Kbytes of on-chip internal RAM (dual-port) is provided as a storage for data,
system stack, general purpose register banks and code. A register bank is 16 wordwide (R0
to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group.
XRAM: 16K + 2K bytes of on-chip extension RAM (single port XRAM) is provided as a
storage for data, user stack and code. The XRAM is divided into two areas, the first 2 Kbytes
named XRAM1 and the second 16 Kbytes named XRAM2, connected to the internal XBUS
and are accessed like an external memory in 16-bit demultiplexed bus-mode without wait
state or read/write delay (50 ns access at 40 MHz CPU clock). Byte and word accesses are
possible.
The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register),
and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then
any access in the address range 00’E000h - 00’E7FFh will be directed to external memory
interface, using the BUSCONx register corresponding to address matching ADDRSELx
register.
The XRAM2 address range is the one selected programming XADRS3 register, if XPEN (bit
2 of SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is
cleared, then any access in the address range programmed for XRAM2 will be directed to
external memory interface, using the BUSCONx register corresponding to address
matching ADDRSELx register.
Doc ID 12968 Rev 4
21/176
Memory organization
ST10F272M
After reset, the XRAM2 address range is 09’0000h - 09’3FFFh and is mirrored every
16 Kbyte boundary until 0F’FFFFh.
XRAM2 also represents the stand-by RAM, which can be maintained biased through
EA / VSTBY pin when main supply VDD is turned off. As the XRAM appears like external
memory, it cannot be used as system stack or as register banks. The XRAM is not provided
for single bit storage and therefore is not bit addressable.
SFR/ESFR: 1024 bytes (2 x 512 bytes) of address space is reserved for the special function
register areas. SFRs are wordwide registers which are used to control and to monitor the
function of the different on-chip units.
CAN1: Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 module access. The
CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit
0 of the XPERCON register. Accesses to the CAN module use demultiplexed addresses
and a 16-bit data bus (only word accesses are possible). Two wait states give an access
time of 100ns at 40 MHz CPU clock. No tri-state wait states are used.
CAN2: Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 Module access. The
CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit
1 of the new XPERCON register. Accesses to the CAN module use demultiplexed
addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an
access time of 100ns at 40 MHz CPU clock. No tri-state wait states are used.
Note:
If one or the two CAN modules are used, port 4 cannot be programmed to output all eight
segment address lines. Thus, only four segment address lines can be used, reducing the
external memory space to 5 Mbytes (1 Mbyte per CS line).
RTC: Address range 00’ED00h - 00’EDFFh is reserved for the RTC Module access. The
RTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON
register. Accesses to the RTC Module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz
CPU clock. No tristate waitstate is used.
PWM1: Address range 00’EC00h - 00’ECFFh is reserved for the PWM1 module access.
The PWM1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the
XPERCON register. Accesses to the PWM1 Module use demultiplexed addresses and a 16bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns
at 40 MHz CPU clock. No tristate waitstate is used. Only word access is possible.
ASC1: Address range 00’E900h - 00’E9FFh is reserved for the ASC1 module access. The
ASC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON
register. Accesses to the ASC1 module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz
CPU clock. No tristate waitstate is used.
SSC1: Address range 00’E800h - 00’E8FFh is reserved for the SSC1 Module access. The
SSC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON
register. Accesses to the SSC1 module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz
CPU clock. No tristate waitstate is used.
I2C: Address range 00’EA00h - 00’EAFFh is reserved for the I2C module access. The I2C is
enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register.
Accesses to the I2C module use demultiplexed addresses and a 16-bit data bus (only word
accesses are possible). Two waitstates give an access time of 100 ns at 40 MHz CPU clock.
No tristate waitstate is used.
22/176
Doc ID 12968 Rev 4
ST10F272M
Memory organization
X-miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set
of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON
register and bit 10 of the XPERCON register. Accesses to this additional features use
demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two
waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used.
The following set of features are provided:
●
CLKOUT programmable divider
●
XBUS interrupt management registers
●
ADC multiplexing on P1L register
●
Port1L digital disable register for extra ADC channels
●
CAN2 multiplexing on P4.5/P4.6
●
CAN1-2 main clock prescaler
●
Main voltage regulator disable for power-down mode
●
TTL/CMOS threshold selection for port0, port1, and port5
●
Flash temporary unprotection
In order to meet the needs of designs where more memory is required than is provided on
chip, up to 16 Mbytes of external memory can be connected to the microcontroller.
Visibility of XBUS peripherals
In order to keep the ST10F272M compatible with the ST10F168/ST10F269, the XBUS
peripherals can be selected to be visible on the external address / data bus. Different bits for
X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the
global enabling with XPEN bit in SYSCON register, the corresponding address space, port
pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and
not available. Refer to Chapter 23: Register set on page 108.
XPERCON and X-peripheral clock gating
As already mentioned, the XPERCON register must be programmed to enable the single Xbus modules separately. The XPERCON is a read/write ESFR register.
The new feature of clock gating has been implemented by means of this register: Once the
EINIT instruction has been executed, all the peripherals (except RAMs and XMISC) not
enabled in the XPERCON register are not be clocked. The clock gating can reduce power
consumption and improve EMI when the user doesn’t use all X-peripherals.
Note:
When the clock has been gated in the disabled peripherals, no reset will be raised once the
EINIT instruction has been executed.
Doc ID 12968 Rev 4
23/176
Memory organization
ST10F272M on-chip memory mapping (ROMEN = 1/XADRS = 800Bh - reset value)
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