ST10R172LT1

ST10R172L 16-BIT LOW VOLTAGE ROMLESS MCU DATASHEET ■ High Performance 16-bit CPU ● ● ● ● ● ● ● ● ■ Memory Organisation ● ● ■ CPU Frequency: 0 to 50 MHz 40ns instruction cycle time at 50-MHz CPU clock 4-stage pipeline Register-based design with multiple variable register banks Enhanced boolean bit manipulation facilities Additional instructions to support HLL and operating systems Single-cycle context switching support 1024 bytes on-Chip special function register area 1KByte on-chip RAM Up to 16 MBytes linear address space for code and data (1 MByte with SSP used) ● ● ● u d o Programmable external bus characteristics for different address ranges 8-bit or 16-bit external data bus Multiplexed or demultiplexed external address/data buses Five programmable chip-select signals Hold and hold-acknowledge bus arbitration support e t e l Pr so ● b O ■ One Channel PWM Unit ■ Fail Safe Protection ● ● ■ ● ● ■ Timers WDT P.1 u d o r P e t e l o Interrupt Controller &PEC ASC s b O ● ● ■ GPT1/2 P.3 P.5 PWM P.7 ● Two multi-functional general purpose timer units with 5 timers Clock Generation via on-chip PLL, or via direct or prescaled clock input Synchronous/asynchronous High-speed-synchronous serial port SSP ■ Up to 77 general purpose I/O lines ■ No bootstrap loader ■ Electrical Characteristics ● ● ● 5V Tolerant I/Os 5V Fail-Safe Inputs (Port 5) Power: 3.3 Volt +/-0.3V Idle and power down modes Support ● ■ Po.2 Serial Channels ● ■ P.0 ) s ( ct XSSP ST10 CORE Programmable watchdog timer Oscillator Watchdog 8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller (PEC) 16-priority-level interrupt system with 17 sources, sample-rate down to 40 ns OSC P.4 DPRAM ● Interrupt P.6 PLL ct External Memory Interface ● ) (s Dedicated pins C-compilers, macro-assembler packages, emulators, evaluation boards, HLLdebuggers, simulators, logic analyser disassemblers, programming boards Package ● 100-Pin Thin Quad Flat Pack (TQFP) Rev. 1.2 March 2001 1/68 1 Table of Contents 1 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 MEMORY MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 INTERRUPT AND TRAP FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 INTERRUPT SOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ) s ( ct 5.2 HARDWARE TRAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 u d o 6 PARALLEL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 r P e 7 EXTERNAL BUS CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 t e l o 8 PWM MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 GENERAL PURPOSE TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 s b O 9.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ) (s 9.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 t c u 10 SERIAL CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 d o r 11 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 P e 12 SYSTEM RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 t e l o 13 POWER REDUCTION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 s b O 14 SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 15 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15.2 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 68 2/68 1 Table of Contents 15.3 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 15.3.1 Cpu Clock Generation Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 15.3.2 Memory Cycle Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 15.3.3 Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 15.3.4 Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 15.3.5 CLKOUT and READY/READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.3.6 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 15.3.7 External Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 ) s ( ct 15.3.8 Synchronous Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 16 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 u d o 17 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 3/68 ST10R172L - PIN DESCRIPTION PIN DESCRIPTION 100999897969594939291908988878685848382818079787776 ST10R172L d Figure 1 TQFP-100 pin configuration (top view) t c u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 s b O e t e ol o r P P5.13/T5IN P5.14/T4EUD P5.15/T2EUD VSS XTAL1 XTAL2 VDD P3.0 P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8 P3.9 P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13 P3.15/CLKOUT P4.0/A16 P4.1/A17 P4.2/A18 RPD 26272829303132333435363738394041424344454647484950 e t e ol Pr P4.3/A19 VSS VDD P4.4/A20/SSPCE1 P4.5/A21/SSPCE0 P4.6/A22/SSPDAT P4.7/A23/SSPCLK RD WR/WRL READY/READY ALE EA VDD VSS ) (s P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 VDD VSS 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 s b O 1 4/68 1 P5.12/T6IN P5.11/T5EUD P5.10/T6EUD P7.3/POUT3 P7.2 P7.1 P7.0 P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/BREQ P6.6/HLDA P6.5/HOLD P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0 NMI RSTOUT RSTIN VDD VSS P1H.7/A15 u d o ) s ( ct P1H.6/A14 P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 VSS VDD P1H.1/A9 P1H.0/A8 P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 P0H.1/AD9 P0H.0/AD8 Pin Number (TQFP) Input (I) Output (O) Kind1) P5.10 98-100 I 5S –P5.15 1- 3 I 5S 6-bit input-only port with Schmitt-Trigger characteristics. Port 5 pins also serve as timer inputs: 98 I 5S P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input 99 I 5S P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input 100 I 5S P5.12 T6IN GPT2 Timer T6 Count Input 1 I 5S P5.13 T5IN GPT2 Timer T5 Count Input 2 I 5S P5.14 T4EUD 3 I 5S P5.15 T2EUD XTAL1 5 I 3T XTAL1: XTAL2 6 O 3T s b O t e l o ) (s t c u d o r P e Function Symbol ST10R172L - PIN DESCRIPTION XTAL2: ) s ( ct u d o r P e s b O t e l o GPT1 Timer T4 Ext.Up/Down Ctrl.Input GPT1 Timer T2 Ext.Up/Down Ctrl.Input Input to the oscillator amplifier and internal clock generator Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Observe minimum and maximum high/low and rise/fall times specified in the AC Characteristics. Table 1 Pin definitions 5/68 1 Kind1) 8-21 I/O 5T P3.15 22 I/O 5T 5T P3.1 T6OUT GPT2 Timer T6 toggle latch output 10 I 5T P3.2 CAPIN GPT2 Register CAPREL capture input 11 O 5T P3.3 T3OUT GPT1 Timer T3 toggle latch output 12 I 5T P3.4 T3EUD 13 I 5T P3.5 T4IN 14 I 5T P3.6 15 I 5T 18 O 20 6/68 1 ) s ( ct O e t e ol O A 15-bit (P3.14 is missing) bidirectional I/O port. Port 3 is bitwise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The following pins have alternate functions: 9 19 bs Function Input (I) Output (O) P3.0 – P3.13 Symbol Pin Number (TQFP) ST10R172L - PIN DESCRIPTION 22 ) (s u d o r P e s b O t e l o GPT1 Timer T3 ext.up/down ctrl.input GPT1 Timer T4 input for count/gate/ reload/capture T3IN GPT1 Timer T3 count/gate input P3.7 T2IN GPT1 Timer T2 input for count/gate/ reload/capture 5T P3.10 TxD0 ASC0 clock/data output (asyn./syn.) I/O 5T P3.11 RxD0 ASC0 data input (asyn.) or I/O (syn.) O 5T P3.12 BHE Ext. Memory High Byte Enable Signal O 5T WRH Ext. Memory High Byte Write Strobe O 5T CLKOUT System clock output (=CPU clock) u d o ct Pr P3.15 Table 1 Pin definitions Pin Number (TQFP) Input (I) Output (O) Kind1) P4.0– P4.7 23-26 29-32- I/O 5T An 8-bit bidirectional I/O port. Port 8 is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 4 can be used to output the segment address lines for external bus configuration. 23 O 5T P4.0 A16 Least Significant Segment Addr. Line ... ... ... ... ... ... 26 O 5T P4.3 A19 Segment Address Line 29 O 5T P4.4 A20 Segment Address Line O 5T O 5T O 5T O 5T I/O 5T 30 31 32 s b O WR/ WRL READY/ READY ) (s P4.6 t c u od r P e Chip Enable Line 1 Segment Address Line SSPCE0 SSPChip Enable Line 0 A22 Segment Address Line SSPDAT SSP Data Input/Output Line A23 Most Significant Segment Addr. Line SSPCLK SSP Clock Output Line 5T O 5T 33 O 5T External Memory Read Strobe. RD is activated for every external instruction or data read access. 34 O 5T External Memory Write Strobe. In WR-mode, this pin is activated for every external data write access. In WRL-mode, this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection. 35 I 5T Ready Input. Active level is programmable. When the Ready function is enabled, the selected inactive level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to the selected active level. Polarity is programmable. r P e P4.7 s b O A21 u d o t e l o SSPCE1 P4.5 ) s ( ct O t e l o RD Function Symbol ST10R172L - PIN DESCRIPTION Table 1 Pin definitions 7/68 1 Pin Number (TQFP) Input (I) Output (O) Kind1) ALE 36 O 5T Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. EA 37 I 5T External Access Enable pin. Low level at this pin during and after reset forces the ST10R172L to begin instruction execution out of external memory. A high level forces execution out of the internal ROM. The ST10R172L must have this pin tied to ‘0’. PORT0: I/O P0L.0– P0L.7, 41 - 48 P0H.0 P0H.7 51 - 58 Function Symbol ST10R172L - PIN DESCRIPTION ) s ( ct u d o r P e 5T PORT0 has two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. For external bus configuration, PORT0 acts as address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. t e l o ) (s s b O Demultiplexed bus modes ct du ete o r P O PORT1: 59- 66 P1H.0 P1H.7 67, 68 71-76 16-bit P0L.0 – P0L.7: D0 – D7 D0 - D7 P0H.0 – P0H.7: I/O D8 - D15 Data Path Width: I/O P1L.0– P1L.7, 8-bit Multiplexed bus modes ol bs Data Path Width: 5T 8-bit P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7 P0H.0 – P0H.7: A8 – A15 AD8 – AD15 PORT1 has two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. PORT1 acts as a 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. Table 1 Pin definitions 8/68 1 16-bit Pin Number (TQFP) Input (I) Output (O) Kind1) RSTIN 79 I 5T RSTOUT 80 81 O NMI P6.0P6.7 82-89 I I/O 5T 5S 5T Function Symbol ST10R172L - PIN DESCRIPTION Reset Input with Schmitt-Trigger characteristics. Resets the device when a low level is applied for a specified duration while the oscillator is running. An internal pullup resistor enables power-on reset using only a capacitor connected to VSS. With a bonding option, the RSTIN pin can also be pulled-down for 512 internal clock cycles for hardware, software or watchdog timer triggered resets ) s ( ct u d o Internal Reset Indication Output. This pin is set to a low level when the part is executes hardware-, software- or watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. r P e t e l o Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If it is not used, NMI should be pulled high externally. s b O An 8-bit bidirectional I/O port. Port 6 is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers. ) (s t c u d o r The following Port 6 pins have alternate functions: ... ... ... ... ... 86 O 5T P6.4 CS4 Chip Select 4 Output 87 I 5T P6.5 HOLD External Master Hold Request Input (Master mode: O, Slave mode: I) 88 I/O 5T P6.6 HLDA Hold Acknowledge Output 89 O 5T P6.7 BREQ Bus Request Output 82 ... P e s b O t e l o O 5T P6.0 CS0 Chip Select 0 Output Table 1 Pin definitions 9/68 1 Kind1) 90 - 93 I/O 5T Function Input (I) Output (O) P2.8 – P2.11 Pin Number (TQFP) Symbol ST10R172L - PIN DESCRIPTION Port 2 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. ) s ( ct The following Port 2 pins have alternate functions: P7.0 – P7.3 90 I 5T P2.8 EX0IN Fast External Interrupt 0 Input ... ... ... ... ... ... 93 I 5T P2.11 EX3IN Fast External Interrupt 3 Input 94 - 97 I/O 5T Port 7 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 7outputs can be configured as push/pull or open drain drivers. u d o r P e t e l o s b O The following Port 7 pins have alternate functions: 97 O 5T RPD 40 I/O 5T VDD 7, 28, 38, 49, 69, 78 - e t e ol VSS s b O 4, 27, 39, 50, 70, 77 - POUT3 PWM (Channel 3) Output ct u d o Pr ) (s P7.3 Input timing pin for the return from powerdown circuit and power-up asynchronous reset. PO Digital supply voltage. PO Digital ground. Table 1 Pin definitions 1) The following I/O kinds are used. Refer to ELECTRICAL CHARACTERISTICS on page 31 for a detailed description. PO: Power pin 3T: 3 V tolerant pin (voltage max. respect to Vss is -0.5 to VDD + 0.5) 5V: 5 V tolerant pin (voltage max. respect to Vss is -0.5 to 5.5 only if chip is powered) 5S: 5 V tolerant and fail-safe pin (-0.5-5.5 max. voltage w.r.t. Vss even if chip is not powered). 10/68 1 ST10R172L - FUNCTIONAL DESCRIPTION 2 FUNCTIONAL DESCRIPTION ST10R172L architecture combines the advantages of both RISC and CISC processors with an advanced peripheral subsystem. The following block diagram overviews the different onchip components and the internal bus structure. I/O CS(4:0) HOLD HLDA BREQ I/O A(23:16), SSPCLK, SSPDAT, SSPCE(1:0) dedicated pins Port 6 8-bit Port 4 8-bit OSC WDT EA, ALE, RD, WR/WRL, READY, NMI, RSTIN, RSTOUT I/O I/O, D(7:0) D(15:8), D(7:0) I/O A(15:8), AD(7:0) A(15:0) AD(15:8), AD(7:0) Port 1 2x8-bit XSSP 4-bit t e l o XTAL2 PLL u d o s b O e t e ol Pr ) (s ASC Port 3 15-bit I/O CLKOUT, BHE/WRH, RxD0, TxD0, T2IN, T3IN, T4IN, T3EUD, T3OUT, CAPIN, T6OUT s b O ST10 CORE 1KByte ct u d o r P e XTAL1 DPRAM Port 0 2x8-bit ) s ( ct Interrupt Controller & PEC GPT1/2 PWM Port 7 4-bit Port 2 4-bit I/O POUT3 I/O EXIN(3:0) Port 5 6-bit I T2EUD, T4EUD, T5IN, T6IN, T5EUD, T6EUD Figure 2 Block diagram 11/68 1 ST10R172L - MEMORY MAPPING 3 MEMORY MAPPING The ST10R172L is a ROMless device, the internal RAM space is 1 KByte. The RAM address space is used for variables, register banks, the system stack, the PEC pointers (in 00’FCE0h - 00’FCFFh) and the bit-addressable space (in 00’FD00h - 00’FDFFh). 00’FFFFh 00’FFFFh 00’F000h RAM/SFR 00’EFFFh 256 Byte 00’EF00h XSSP 00’FF3Fh 00’FF20h Data Page 3 SFR Area (reserved) ) s ( ct 00’FE3Fh 00’FE20h 00’FE00h External memory u d o 00’F000h RAM Data Page 2 e t e l Pr 1K-Byte 00’FA00h o s b 00’8000h O ) s ( t c Data Page 1 u d o internal memory r P e t e l o 00’1FFFh 8K-byte bs 00’0000h O Block 1 00’4000h 00’F200h 00’FF3Fh 00’FF20h ESFR Area (reserved) Data Page 0 Block 0 00’F03Fh 00’F020h 00’0000h System Segment 0 64 K-Byte Figure 3 Memory map 12/68 1 00’F000h DPRAM / SFR Area 4 K-Byte ST10R172L - CENTRAL PROCESSING UNIT 4 CENTRAL PROCESSING UNIT The main core of the CPU contains a 4-stage instruction pipeline, a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most instructions can be executed in one machine cycle requiring 40ns at 50MHz CPU clock. The CPU includes an actual register context consisting of 16 wordwide GPRs physically located in the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, one register bank may overlap others. ) s ( ct A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are compared against the stack pointer value during each stack access to detect stack overflow or underflow. u d o r P e t e l o CPU MDH MDL SP STKOV STKUN Mul./Div.-HW Bit-Mask Gen. Exec. Unit Instr. Ptr Instr. Reg 4-Stage Pipeline t c u d o r PSW SYSCON b O so let P e BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Pg. Ptrs ) (s ALU s b O R15 16 Internal General RAM Purpose 1KByte Registers R15 16-Bit Barrel-Shift Context Ptr ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr. R0 IDX0 QX0 QR0 IDX1 QX1 QR1 16 R0 Figure 4 CPU block diagram 13/68 1 ST10R172L - INTERRUPT AND TRAP FUNCTIONS 5 INTERRUPT AND TRAP FUNCTIONS The architecture of the ST10R172L supports several mechanisms for fast and flexible response to the service requests that can be generated from various sources, internal or external to the microcontroller. Any of these interrupt requests can be programmed to be serviced, either by the Interrupt Controller or by the Peripheral Event Controller (PEC). In a standard interrupt service, program execution is suspended and a branch to the interrupt service routine is performed. For a PEC service, just one cycle is ‘stolen’ from the current CPU activity. A PEC service is a single, byte or word data transfer between any two memory locations, with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is decremented for each PEC service, except in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source-related vector location. PEC services are very well suited, for example, to the transmission or reception of blocks of data. The ST10R172L has 8 PEC channels, each of which offers fast interrupt-driven data transfer capabilities. ) s ( ct u d o r P e A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield, exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher priority service request. For standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. t e l o ) (s s b O Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs, feature programmable edge detection (rising edge, falling edge or both edges). t c u d o r Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number. P e t e l o s b O 14/68 1 ST10R172L - INTERRUPT AND TRAP FUNCTIONS 5.1 Interrupt Sources Source of Interrupt or PEC Service Request Request Flag Enable Flag Interrupt Vector Vector Location Trap Number External Interrupt 0 CC8IR CC8IE CC8INT 60h 18h External Interrupt 1 CC9IR CC9IE CC9INT 64h 19h External Interrupt 2 CC10IR CC10IE CC10INT 68h 1Ah External Interrupt 3 CC11IR CC11IE CC11INT 6Ch GPT1 Timer 2 T2IR T2IE T2INT 88h GPT1 Timer 3 T3IR T3IE T3INT 8Ch GPT1 Timer 4 T4IR T4IE T4INT 90h 24h GPT2 Timer 5 T5IR T5IE T5INT r P e 23h 94h 25h GPT2 Timer 6 T6IR T6IE T6INT 98h 26h GPT2 CAPREL Register CRIR CRINT 9Ch 27h ASC0 Transmit S0TIR S0TINT A8h 2Ah ASC0 Transmit Buffer s ( t c S0TIE S0TBIR S0TBIE S0TBINT 11Ch 47h S0RIR S0RIE S0RINT ACh 2Bh S0EIR S0EIE S0EINT B0h 2Ch PWMIR PWMIE PWMINT FCh 3Fh SSP Interrupt XP1IR XP1IE XP1INT 104h 41h PLL Unlock XP3IR XP3IE XP3INT 10Ch 43h u d o ASC0 Receive ASC0 Error ete PWM Channel 3 s b O ol Pr bs O ) CRIE t e l o u d o ) s ( ct 1Bh 22h Table 2 List of possible interrupt sources, flags, vector and trap numbers 15/68 1 ST10R172L - INTERRUPT AND TRAP FUNCTIONS 5.2 Hardware traps Exceptions or error conditions that arise during run-time are called Hardware Traps. Hardware traps cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can not normally be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during run-time: Exception Condition Trap Flag Vector Trap Vector Location Reset Functions: Hardware Reset RESET Software Reset RESET Watchdog Timer Overflow RESET ) s ( ct u d o r P e 00’0000h Trap Priority 00h III 00’0000h 00h III 00’0000h 00h III NMITRAP 00’0008h 02h II STOTRAP 00’0010h 04h II STKUF STUTRAP 00’0018h 06h II UNDOPC BTRAP 00’0028h 0Ah I PRTFLT BTRAP 00’0028h 0Ah I Illegal word operand access ILLOPA BTRAP 00’0028h 0Ah I Class A Hardware Traps: Non-Maskable Interrupt NMI Stack Overflow STKOF d o r Class B Hardware Traps: Undefined opcode P e Protected instruction fault t e l o bs )- t(s uc Stack Underflow O Trap Number so let b O Illegal instruction access ILLINA BTRAP 00’0028h 0Ah I Illegal external bus access ILLBUS BTRAP 00’0028h 0Ah I [2Ch – 3Ch] [0Bh – 0Fh] Reserved Software Traps TRAP Instruction Any [00’0000h Any Current – 00’01FCh] [00h – 7Fh] CPU steps of 4h Priority Table 3 Exceptions or error conditions 16/68 1 ST10R172L - PARALLEL PORTS 6 PARALLEL PORTS The ST10R172L provides up to 77 I/O lines organized into 7 input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs by direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation by control registers. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for timer control signals. Port 2 lines can be used as fast external interrupt lines. Port 7 includes alternate function for the PWM signal. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. ) s ( ct u d o r P e 7 t e l o s b O EXTERNAL BUS CONTROLLER All external memory accesses are performed by the on-chip External Bus Controller which can be programmed either to single chip mode when no external memory is required, or to the following external memory access modes: 16-bit data, demultiplexed t c u od 16-bit data, multiplexed Pr 8-bit data, multiplexed 8-bit data, demultiplexed e t e ol ) (s 16-/18-/20-/24-bit addresses 16-/18-/20-/24-bit addresses 16-/18-/20-/24-bit addresses 16-/18-/20-/24-bit addresses In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0/P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. s b O Memory cycle time, memory tri-state time, length of ALE and read write delay are programmable so that a wide range of different memory types and external peripherals can be used. Up to 4 independent address windows can be defined (via ADDRSELx / BUSCONx register pairs) to access different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 etc. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated to reduce external glue logic. Access to very slow memories is supported by the READY function. A HOLD/HLDA protocol is available for bus arbitration so that external resources can be shared with other bus masters. In slave mode, the slave controller can be connected to another master controller without glue logic. For applications which require less than 16 MBytes 17/68 1 ST10R172L - PWM MODULE of external memory space, the address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. 8 PWM MODULE A 1-channel Pulse Width Modulation (PWM) Module operates on channel 3. The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centrealigned PWM. In addition, the PWM module can generate PWM burst signals and single shot outputs. The table below shows the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM module can generate interrupt requests. Mode 0 edge aligned Resolution 8-bit 10-bit 12-bit CPU clock/1 20ns 195.3 KHz 48.83KHz 12.21KHz CPU clock/64 1.28ns 3.052KHz 762.9Hz 190.7Hz Mode 1 center aligned Resolution 8-bit 10-bit CPU clock/1 20ns 97.66KHz CPU clock/64 1.28ns 1.525Hz t c u ) (s 14-bit ) s ( ct u d o Pr 3.052KHz 762.9Hz 47.68Hz 11.92Hz 12-bit 14-bit 16-bit 24.41KHz 6.104KHz 1.525KHz 381.5Hz 381.5 Hz 95.37Hz 23.84Hz 0Hz s b O e t e ol Table 4 PWM unit frequencies and resolution at 50MHz CPU clock d o r P e t e l o s b O 18/68 1 16-bit ST10R172L - GENERAL PURPOSE TIMERS 9 GENERAL PURPOSE TIMERS The GPTs are flexible multifunctional timer/counters used for time-related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation or pulse multiplication. The GPT unit contains five 16-bit timers, organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. 9.1 GPT1 Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of four basic modes of operation: timer, gated timer, counter mode and incremental interface mode. In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler. In counter mode, the timer is clocked in reference to external events. Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. Table 5 GPT1 timer input frequencies, resolution and periods lists the timer input frequencies, resolution and periods for each pre-scaler option at 50MHz CPU clock. This also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in Timer and Gated Timer Mode ) s ( ct u d o r P e t e l o ) (s s b O The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). t c u In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. d o r P e t e l o Timer T3 has output toggle latches (TxOTL) which changes state on each timer over-flow/ underflow. The state of this latch may be output on port pins (TxOUT) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. s b O In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. 19/68 1 ST10R172L - GENERAL PURPOSE TIMERS Timer input selection FCPU=50MHz 000b 001b 010b 011b 100b 101b 110b 111b Prescaler Factor 8 16 32 64 128 256 512 1024 Input Frequency 6.25 MHz 3.125 MHz 1.5625 MHz 781 KHz 391 KHz 195 KHz 97.5 KHz 48.83 KHz Resolution 160ns 320ns 640ns 1.28 us 2.56 us 5.12 us 10.24 us 20.48 us Period 10.49ms 20.97ms 41.94ms 83.88ms 168ms 336ms 672ms u d o Table 5 GPT1 timer input frequencies, resolution and periods U/D T2EUD r P e t e l o n 2 n=3...10 T2 Mode T2IN CPU Clock 2n n=3...10 T3EUD T3IN ete ol s b O CPU Clock T4EUD 2n n=3...10 ) (s ct du o r P T4IN T3 Mode s b O Reload Capture T3OUT GPT1 Timer T3 Interrupt Request Mode GPT1 Timer T4 U/D Figure 5 GPT1 block diagram 20/68 1 T3OTL U/D Capture Reload T4 1.342s Interrupt Request GPT1 Timer T2 CPU Clock ) s ( ct Interrupt Request ST10R172L - GENERAL PURPOSE TIMERS 9.2 GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported by the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of T6OTL may be used to clock timer T5, or may be output on a port pin T6OUT. The overflows/underflows of timer T6 reload the CAPREL register. The CAPREL register captures the contents of T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performedwithout software overhead. ) s ( ct u d o r P e t e l o Timer input selection FCPU=50MHz 000b 001b 010b Prescaler Factor 4 8 16 Input Frequency 12.5 MHz 6.25 MHz 3.125 MHz Resolution 80ns Period 5.24ms e t e ol Pr 100b 101b 110b 111b 64 128 256 512 1.563 MHz 781 KHz 391 KHz 195 KHz 97.6 KHz 320ns 640ns 1.28 us 2.56 us 5.12 us 10.24 us 20.97ms 41.94ms 83.88ms 167.7ms 335.5ms 671ms ) s ( ct u d o 160ns 10.49ms bs 011b -O 32 Table 6 GPT2 timer input frequencies, resolution and periods s b O 21/68 1 ST10R172L - SERIAL CHANNELS T5EUD CPU Clock U/D 2n n=2...9 T5IN T5 Interrupt Request GPT2 Timer T5 Mode Clear Capture Interrupt Request CAPIN GPT2 CAPREL ) s ( ct Reload T6IN CPU Clock r P e Toggle FF T6 2n n=2...9 u d o Interrupt Request GPT2 Timer T6 t e l o Mode U/D T6EUD T60TL T6OUT s b O Figure 6 GPT2 block diagram 10 ) (s SERIAL CHANNELS t c u Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a Synchronous Serial Port (SSP). d o r P e ASC0 t e l o A dedicated baud rate generator sets up standard baud rates without oscillator tuning. 3 separate interrupt vectors are provided for transmission, reception, and erroneous reception. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). s b O In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities have been included to increase the reliability of data transfers. A parity bit can be generated automatically on transmission, or checked on reception. Framing error detection recognizes data frames with missing stop bits. An overrun error is generated if the last character received was not read out of the receive buffer register at the time the reception of a new character is complete.The table below lists 22/68 1 ST10R172L - SERIAL CHANNELS various commonly used baud rates together with the required reload values and the deviation errors compared to the intended baudrate. S0BRS = ‘0’, fCPU = 50MHz S0BRS = ‘1’, f CPU = 50MHz Baud Rate Deviation Error (Baud) Reload Value Baud Rate Deviation Error (Baud) Reload Value 1562500 0.0% / 0.0% 0000H / 0000H 1041666 0.0% / 0.0% 0000H / 0000H 56000 +3.3% / -0.4% 001AH / 001BH 56000 +3.3% / -2.1% 0011H / 0012H 38400 +1.7% / -0.8% 0027H / 0028H 38400 +0.5% / -3.1% 001AH / 001BH 19200 +0.5% / -0.8% 0050H / 0051H 19200 +0.5% /-1.4% 9600 +0.5% / -0.1% 00A1H/ 00A2H 9600 +0.5% / -0.5% 006BH / 006CH 4800 +0.2% / -0.1% 0144H / 0145H 4800 0.0% / -0.5% 00D8H / 00D9H 2400 0.0% / -0.1% 028AH / 028BH 2400 0.0% / -0.2% 01B1H / 01B2H 1200 0.0% / -0.1% 0515H / 0516H 1200 0.0% / -0.1% 0363H / 0364H 600 0.0% / 0.0% 0A2BH / 0A2CH 0.0% / -0.1% 06C7H / 06C8H 190 +0.4% /+0.4% 1FFFH / 1FFFH 75 0.0% / 0.0% 363FH / 3640H 127 +0.1% / +0.1% 1FFFH / 1FFFH t c u (s) -O bs 600 u d o ete ol ) s ( ct Pr 0035H / 0036H d o r Table 7 Commonly used baud rates, required reload values and deviation errors P e SSP transmits 1...3 bytes or receives 1 byte after sending 1...3 bytes synchronously to a shift clock which is generated by the SSP. The SSP can start shifting with the LSB or with the MSB and is used to select shifting and latching clock edges, and clock polarity. Up to two chip select lines may be activated in order to direct data transfers to one or both of two peripheral devices. t e l o s b O When the SSP is enabled, the four upper pins of Port4 can not be used as general purpose IO. Note that the segment address selection done via the system start-up configuration during reset has priority and overrides the SSP functions on these pins. SSPCKS Value Synchronous baud rate 000 SSP clock = CPU clock divided by 2 25 MBit/s 001 SSP clock = CPU clock divided by 4 12.5 MBit/s 010 SSP clock = CPU clock divided by 8 6.25 MBit/s Table 8 Synchronous baud rate and SSPCKS reload values 23/68 1 ST10R172L - WATCHDOG TIMER SSPCKS Value Synchronous baud rate 011 SSP clock = CPU clock divided by 16 3.13 MBit/s 100 SSP clock = CPU clock divided by 32 1.56 MBit/s 101 SSP clock = CPU clock divided by 64 781 KBit/s 110 SSP clock = CPU clock divided by 128 391 KBit/s 111 SSP clock = CPU clock divided by 256 195 KBit/s ) s ( ct Table 8 Synchronous baud rate and SSPCKS reload values 11 u d o WATCHDOG TIMER r P e The Watchdog Timer is a fail-safe mechanism which limits the malfunction time of the controller. The Watchdog Timer is always enabled after device reset and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. In this way, the chip’s start-up procedure is always monitored. The software must be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to maintain the Watchdog Timer, it will overflow generating an internal hardware reset and pulling the RSTOUT pin low to reset external hardware components. t e l o ) (s s b O The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a pre-specified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. The table below shows the watchdog time range which for a 50MHz CPU clock rounded to 3 significant figures. t c u d o r P e t e l o Reload value Prescaler for fCPU in WDTREL 2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’) FFH 10.24 µs 655 µs 00H 2.62 ms 168 ms s b O Table 9 Watchdog timer range 24/68 1 ST10R172L - SYSTEM RESET 12 SYSTEM RESET The following type of reset are implemented on the ST10R172L: Asynchronous hardware reset: Asynchronous reset does not require a stabilized clock signal on XTAL1 as it is not internally resynchronized, it resets the microcontroller into its default reset state. Asynchronous reset is required on chip power-up and can be used during catastrophic situations. The rising edge of the RSTIN pin is internally resynchronized before exiting the reset condition, therefore, only the entry to hardware reset is asynchronous. Synchronous hardware reset (warm reset): A warm synchronous hardware reset is triggered when the reset input signal RSTIN is latched low and Vpp pin is high. The I/Os are immediately (asynchronously) set in high impedance, RSTOUT is driven low. After RSTIN negation is detected, a short transition period elapses, during which pending internal hold states are cancelled and any current internal access cycles are completed, external bus cycles are aborted. Then, the internal reset sequence is active for 1024 TCL (512 CPU clock cycles). During this reset sequence, if bit BDRSTEN was previously set by software (bit 3 in SYSCON register), RSTIN pin is driven low and internal reset signal is asserted to reset the microcontroller in its default state. Note that after all reset sequence, bit BDRSTEN is cleared. After the reset sequence has been completed, the RSTIN input is sampled. When the reset input signal is active at that time the internal reset condition is prolonged until RSTIN becomes inactive. ) s ( ct u d o r P e t e l o ) (s s b O Software reset: The reset sequence can be triggered at any time by the protected instruction SRST (software reset). This instruction can be executed deliberately within a program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals a system failure. As for a synchronous hardware reset, if bit BDRSTEN was previously set by software (bit 3 in SYSCON register), the reset sequence lasts 1024 TCL (512 CPU clock cycles), and drives the RSTIN pin low. t c u d o r P e Watchdog timer reset: When the watchdog timer is not disabled during the initialization or serviced regularly during program execution it will overflow and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle does not use READY, or if READY is sampled active (low) after the programmed waitstates. When READY is sampled inactive (high) after the programmed waitstates the running external bus cycle is aborted. Then the internal reset sequence is started. The watchdog reset cannot occur while the ST10R172L is in bootstrap loader mode. t e l o s b O Bidirectional reset: The bidirectional reset is activated by setting bit BDRSTEN (bit 3 in SYSCON register). This reset makes the watchdog timer reset and software reset externally visible. It is active for the duration of an internal reset sequences caused by a watchdog timer reset and software reset. Therefore, the bidirectional reset transforms an internal watchdog timer reset or software reset into an external hardware reset with a minimum duration of 1024 TCL. 25/68 1 ST10R172L - POWER REDUCTION MODES 13 POWER REDUCTION MODES Two different power reduction modes with different levels of power reduction can be entered under software control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode can be terminated by any reset or interrupt request. In Power Down mode both the CPU and the peripherals are stopped. Power Down mode can now be configured by software in order to be terminated only by a hardware reset or by an external interrupt source on fast external interrupt pins. ) s ( ct All external bus actions are completed before Idle or Power Down mode is entered. However, Idle or Power Down mode is not entered if READY is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access. 14 u d o r P e SPECIAL FUNCTION REGISTERS The following table lists all ST10R172L SFRs in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. t e l o s b O An SFR can be specified by its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed by its physical address (using the Data Page Pointers), or by its short 8-bit address (without using the Data Page Pointers). ) (s t c u Name Physical Address 8-Bit Description Address Reset Value ADDRSEL1 FE18h P e 0Ch Address Select Register 1 0000h FE1Ah 0Dh Address Select Register 2 0000h FE1Ch 0Eh Address Select Register 3 0000h FE1Eh 0Fh Address Select Register 4 0000h d o r ADDRSEL2 t e l o ADDRSEL3 s b O ADDRSEL4 BUSCON0 b FF0Ch 86h Bus Configuration Register 0 0XX0h BUSCON1 b FF14h 8Ah Bus Configuration Register 1 0000h BUSCON2 b FF16h 8Bh Bus Configuration Register 2 0000h BUSCON3 b FF18h 8Ch Bus Configuration Register 3 0000h BUSCON4 b FF1Ah 8Dh Bus Configuration Register 4 0000h FE4Ah 25h GPT2 Capture/Reload Register 0000h FF88h C4h EX0IN Interrupt Control Register 0000h CAPREL CC8IC b Table 10 Special functional registers 26/68 1 ST10R172L - SPECIAL FUNCTION REGISTERS Name Physical Address 8-Bit Description Address Reset Value CC9IC b FF8Ah C5h EX1IN Interrupt Control Register 0000h CC10IC b FF8Ch C6h EX2IN Interrupt Control Register 0000h CC11IC b FF8Eh C7h EX3IN Interrupt Control Register 0000h FE10h 08h CPU Context Pointer Register FC00h FF6Ah B5h GPT2 CAPREL Interrupt Control Register FE08h 04h CPU Code Segment Pointer Register (read only) CP CRIC b CSP DP0L b F100h E 80h P0L Direction Control Register DP0H b F102h E 81h P0h Direction Control Register DP1L b F104h E 82h P1L Direction Control Register DP1H b F106h E 83h P1h Direction Control Register DP2 b FFC2h E1h Port 2 Direction Control Register DP3 b FFC6h E3h Port 3 Direction Control Register DP4 b FFCAh E5h DP6 b FFCEh E7h DP7 b FFD2h DPP0 bs DPP3 O bs (s) -O 00h 00h 00h 00h -0--h 0000h 00h Port 6 Direction Control Register 00h E9h Port 7 Direction Control Register -0h 00h CPU Data Page Pointer 0 Register (10 bits) 0000h FE02h 01h CPU Data Page Pointer 1 Register (10 bits) 0001h FE04h 02h CPU Data Page Pointer 2 Register (10 bits) 0002h FE06h 03h CPU Data Page Pointer 3 Register (10 bits) 0003h e t e ol DPP2 o r P 0000h Port 4 Direction Control Register ct u d o Pr FE00h DPP1 e t e ol du ) s ( ct 0000h EBUSCON b F10Eh E 87H Extended BUSCON register 0000h EXICON F1C0h E E0h External Interrupt Control Register 0000h IDCHIP F07Ch E 3Eh Device Identifier Register 1101h IDMANUF F07Eh E 3Fh Manufacturer/Process Identifier Register 0201h IDMEM F07Ah E 3Dh On-chip Memory Identifier Register 0000h IDPROG F078h E 3Ch Programming Voltage Identifier Register 0000h 87h CPU Multiply Divide Control Register 0000h MDC b b FF0Eh Table 10 Special functional registers 27/68 1 ST10R172L - SPECIAL FUNCTION REGISTERS Name Physical Address 8-Bit Description Address Reset Value MDH FE0Ch 06h CPU Multiply Divide Register – High Word 0000h MDL FE0Eh 07h CPU Multiply Divide Register – Low Word 0000h ODP2 b F1C2h E E1h Port 2 Open Drain Control Register -0--h ODP3 b F1C6h E E3h Port 3 Open Drain Control Register 0000h ODP6 b F1CEh E E7h Port 6 Open Drain Control Register ODP7 b F1D2h E E9h Port 7 Open Drain Control Register FF1Eh 8Fh Constant Value 1’s Register (read only) ) s ( ct ONES 00h -0h du o r P FFFFh P0L b FF00h 80h Port 0 Low Register (Lower half of PORT0) 00h P0H b FF02h 81h Port 0 High Register (Upper half of PORT0) 00h P1L b FF04h 82h Port 1 Low Register (Lower half of PORT1) 00h P1H b FF06h 83h Port 1 High Register (Upper half of PORT1) P2 b FFC0h E0h Port 2 Register (4 bits) P3 b FFC4h E2h P4 b FFC8h E4h P5 b FFA2h P6 b FFCCh e t e ol bs (s) -O 00h -0--h Port 3 Register 0000h Port 4 Register (8 bits) 00h D1h Port 5 Register (read only) XXXXh E6h Port 6 Register (8 bits) 00h FFD0h E8h Port 7Register (4 bits) -0h FEC0h 60h PEC Channel 0 Control Register 0000h FEC2h 61h PEC Channel 1 Control Register 0000h PECC2 FEC4h 62h PEC Channel 2 Control Register 0000h PECC3 FEC6h 63h PEC Channel 3 Control Register 0000h PECC4 FEC8h 64h PEC Channel 4 Control Register 0000h PECC5 FECAh 65h PEC Channel 5 Control Register 0000h PECC6 FECCh 66h PEC Channel 6 Control Register 0000h PECC7 FECEh 67h PEC Channel 7 Control Register 0000h PP3 F03Eh 1Fh PWM Module Period Register 3 0000h e t e ol P7 PECC0 bs PECC1 O b ct u d o Pr E Table 10 Special functional registers 28/68 1 ST10R172L - SPECIAL FUNCTION REGISTERS Physical Address 8-Bit Description Address Reset Value FF10h 88h CPU Program Status Word 0000h PW3 FE36h 1Bh PWM Module Pulse Width Register 3 0000h PWMCON0 b FF30h 98h PWM Module Control Register 0 0000h PWMCON1 b FF32h 99h PWM Module Control Register 1 0000h PWMIC b F17Eh E BFh PWM Module Interrupt Control Register RP0H b F108h E 84h System Start-up Configuration Register (Rd. only) XXh FEB4h 5Ah Serial Channel 0 baud rate generator reload reg Name PSW b S0BG ) s ( ct 0000h du o r P 0000h S0CON b FFB0h D8h Serial Channel 0 Control Register S0EIC b FF70h B8h Serial Channel 0 Error Interrupt Control Register 0000h FEB2h 59h Serial Channel 0 receive buffer reg. (rd only) XXh B7h Serial Channel 0 Receive Interrupt Control Reg. CEh Serial Channel 0 transmit buffer interrupt control reg 0000h Serial Channel 0 transmit buffer register (wr only) 00h S0RBUF S0RIC b FF6Eh S0TBIC b F19Ch S0TBUF S0TIC b SP E 58h FF6Ch du ete bs ) s ( ct FEB0h o r P FE12h SSPCON0 e t e ol -O 0000h 0000h B6h Serial Channel 0 Transmit Interrupt Control Regis- 0000h ter 09h CPU System Stack Pointer Register FC00h EF00h X --- SSP Control Register 0 0000h EF02h X --- SSP Control Register 1 0000h SSPRTB EF04h X --- SSP Receive/Transmit Buffer XXXXh SSPTBH EF06h X --- SSP Transmit Buffer High XXXXh STKOV FE14h 0Ah CPU Stack Overflow Pointer Register FA00h STKUN FE16h 0Bh CPU Stack Underflow Pointer Register FC00h FF12h 89h CPU System Configuration Register 0xx0h1) FE40h 20h GPT1 Timer 2 Register 0000h ol SSPCON1 s b O SYSCON b T2 T2CON b FF40h A0h GPT1 Timer 2 Control Register 0000h T2IC b FF60h B0h GPT1 Timer 2 Interrupt Control Register 0000h Table 10 Special functional registers 29/68 1 ST10R172L - SPECIAL FUNCTION REGISTERS Name Physical Address 8-Bit Description Address Reset Value T3 FE42h 21h GPT1 Timer 3 Register 0000h T3CON b FF42h A1h GPT1 Timer 3 Control Register 0000h T3IC b FF62h B1h GPT1 Timer 3 Interrupt Control Register 0000h FE44h 22h GPT1 Timer 4 Register 0000h T4 T4CON b FF44h A2h GPT1 Timer 4 Control Register T4IC b FF64h B2h GPT1 Timer 4 Interrupt Control Register FE46h 23h GPT2 Timer 5 Register T5 ) s ( ct 0000h 0000h o r P du 0000h T5CON b FF46h A3h GPT2 Timer 5 Control Register T5IC b FF66h B3h GPT2 Timer 5 Interrupt Control Register 0000h FE48h 24h GPT2 Timer 6 Register 0000h T6 e t e ol bs T6CON b FF48h A4h GPT2 Timer 6 Control Register T6IC b FF68h B4h GPT2 Timer 6 Interrupt Control Register TFR b FFACh D6h WDT FEAEh 57h WDTCON FFAEh XP1IC b ete XP3IC ol ZEROS s b O b F19Eh b FF1Ch Watchdog Timer Register (read only) 0000h D7h Watchdog Timer Control Register 000xh2) E du C7h SSP Interrupt Control Register 0000h E CFh PLL unlock Interrupt Control Register 0000h 8Eh Constant Value 0’s Register (read only) 0000h Table 10 Special functional registers 1. The system configuration is selected during reset. Note 2. Bit WDTR indicates a watchdog timer triggered reset. 1 0000h 0000h Note 30/68 0000h Trap Flag Register ct o r P F18Eh (s) -O 0000h ST10R172L - ELECTRICAL CHARACTERISTICS 15 ELECTRICAL CHARACTERISTICS 15.1 Absolute Maximum Ratings • Ambient temperature under bias (TA): ......................................................-40°C to +85 °C • Storage temperature (TST):....................................................................... – 65 to +150 °C • Voltage on VDD pins with respect to ground (VSS):..................................... – 0.5 to +4.0 V • Voltage on any pin with respect to ground (VSS): ................................ –0.5 to VDD +0.5 V • Voltage on any 5V tolerant pin with respect to ground (VSS): .......................–0.5 to 5.5 V • Voltage on any 5V fail-safe pin with respect to ground (VSS): .......................–0.5 to 5.5 V • Input current on any pin during overload condition: .................................. –10 to +10 mA • Absolute sum of all input currents during overload condition: .............................|100 mA| • Power dissipation:.....................................................................................................1.0 W ) s ( ct u d o r P e t e l o Note Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VDD or VIN