ST1S09PUR

ST1S09 2 A, 1.5 MHz PWM step-down switching regulator with synchronous rectification Features ■ 1.5 MHz fixed frequency PWM with current control mode ■ 2 A output current capability ■ Typical efficiency: > 90% ■ 2 % DC output voltage tolerance ■ Two versions available: power good or inhibit ■ Integrated output over-voltage protection ■ Non switching quiescent current: (typ) 1.5 mA over temperature range ■ RDSON (typ) 100 mΩ ■ Utilizes tiny capacitors and inductors ■ Operating junction temp. -30 °C to 125 °C ■ Available in DFN6 (3 x 3 mm) exposed pad Description The ST1S09 is a step-down DC-DC converter optimized for powering low output voltage applications. It supplies a current in excess of 2 A over an input voltage range from 2.7 V to 6 V. A high PWM switching frequency (1.5 MHz) allows the use of tiny surface-mount components. Table 1. DFN6 (3 x 3 mm) Moreover, since the required synchronous rectifier is integrated, the number of the external components is reduced to minimum: a resistor divider, an inductor and two capacitors. The Power Good function continuously monitors the output voltage. An open drain Power Good flag is released when the output voltage is within regulation. In addition, a low output ripple is guaranteed by the current mode PWM topology and by the use of low ESR SMD ceramic capacitors. The device is thermally protected and the output current limited to prevent damages due to accidental short circuit. The ST1S09 is available in the DFN6 (3 x 3 mm) package. Device summary Order codes Package ST1S09PUR DFN6D (3 x 3 mm) ST1S09APUR (1) DFN6D (3 x 3 mm) ST1S09IPUR DFN6D (3 x 3 mm) 1. Available on request. April 2010 Doc ID 13632 Rev 4 1/18 www.st.com 18 ST1S09 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 Doc ID 13632 Rev 4 ST1S09 Diagram 1 Diagram Figure 1. Schematic diagram (*) Only for ST1S09IPU (**) Only for ST1S09PU Doc ID 13632 Rev 4 3/18 Pin configuration ST1S09 2 Pin configuration Figure 2. Pin connections (top view) ST1S09 Table 2. ST1S09A Pin description Pin n° Symbol 1 FB 2 GND 3 SW 4 VIN_SW 5 VIN_A 6 INH/PG/NC Exposed Pad GND 4/18 ST1S09I Name and function Feedback voltage System ground Switching pin Power supply for the MOSFET switch Power supply for analog circuit Inhibit (to turn off the device) / Power Good / Not Connected To be connected to PCB ground plane for optimal electrical and thermal performance Doc ID 13632 Rev 4 ST1S09 Maximum ratings 3 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VIN_SW Positive power supply voltage -0.3 to 7 V VIN_A Positive power supply voltage -0.3 to 7 V VINH Inhibit voltage (I version) -0.3 to VI + 0.3 V SWITCH Voltage Max. voltage of output pin -0.3 to 7 V VFB Feedback voltage -0.3 to 3 V PG Power Good open drain -0.3 to 7 V TJ Max junction temperature -40 to 150 °C TSTG Storage temperature range -65 to 150 °C TLEAD Lead temperature (soldering) 10 sec 260 °C Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 4. Thermal data Symbol Parameter Value Unit RthJC Thermal resistance junction-case 10 °C/W RthJA Thermal resistance junction-ambient 55 °C/W Table 5. Symbol ESD performance Parameter Test conditions Value Unit ESD ESD protection voltage HBM 2 kV ESD ESD protection voltage MM 500 V Doc ID 13632 Rev 4 5/18 Electrical characteristics 4 ST1S09 Electrical characteristics Refer to Figure 21 application circuit VIN_SW = VIN_A = 5 V, VO = 1.2 V, C1 = 4.7 µF, C2 = 22 µF, L1 = 2.7 µH, TJ = -30 to 125 °C (unless otherwise specified. Typical values are referred to 25 °C) Table 6. Symbol Electrical characteristics for ST1S09PU Parameter Test conditions Min. Typ. Max. Unit 784 800 816 mV 600 nA 5.5 V 3.9 V FB Feedback voltage IFB VFB pin bias current VI Input voltage IO = 10 mA to 2 A 4.5 Under voltage lock out threshold VI Rising 3.5 Hysteresis Over voltage protection threshold VO rising Over voltage protection hysteresis VO falling 5 % Overvoltage clamping current VO = 1.2 V 300 mA Quiescent current Not switching UVLO 3.7 150 mV 1.05 VO 1.1 VO V OVP IOVP IQ 1.5 (1) 2.5 Output current VI = 4.5 to 5.5 V %VO/ΔVI Output line regulation VI = 4.5 V to 5.5 V, IO = 100 mA (1) 0.16 %VO/ΔIO Output load regulation IO = 10 mA to 2 A (1) 0.2 0.6 % PWM switching frequency VFB = 0.65 V 1.2 1.5 1.8 MHz 80 87 % 0.92 VO V IO PWMfS DMAX Maximum duty cycle 2 mA Power good output threshold PG A %VO/ ΔVI Power good output voltage low ISINK = 6 mA open drain output RDSON-N NMOS switch on resistance ISW = 750 mA 0.1 Ω RDSON-P PMOS switch on resistance ISW = 750 mA 0.1 Ω Switching current limitation (1) 2.5 IO = 10 mA to 100 mA, VO = 3.3 V 65 IO = 100 mA to 2 A, VO = 3.3 V 82 ISWL ν TSHDN THYS Efficiency (1) 0.4 2.9 3.5 V A % 87 Thermal shutdown 150 °C Thermal shutdown hysteresis 20 °C %VO/ΔIO Load transient response IO = 100 mA to 1 A, TA = 25 °C tR = tF ≥ 200 ns (1) -10 +10 %VO %VO/ΔIO Short circuit removal response IO = 10 mA to IO = short, TA = 25 °C (1) -10 +10 %VO 1. Guaranteed by design, but not tested in production. 6/18 Doc ID 13632 Rev 4 ST1S09 Electrical characteristics Refer to Figure 22 application circuit VIN_SW = VIN_A = VINH = 5 V, VO = 1.2 V, C1 = 4.7 µF, C2 = 22 µF, L1 = 2.7 µH, TJ = -30 to 125 °C (unless otherwise specified. Typical values are referred to 25 °C) Table 7. Symbol Electrical characteristics for ST1S09IPU Parameter Test conditions FB Feedback voltage IFB VFB pin bias current VI Minimum input voltage IO = 10 mA to 2 A Over voltage protection threshold VO rising Over voltage protection hysteresis VO falling Min. Typ. Max. Unit 784 800 816 mV 600 nA 2.7 V 1.05 VO 1.1 VO V OVP IQ Quiescent current IO Output current VINH 5 VINH > 1.2 V, not switching 1.5 VINH < 0.4 V, T = - 30 °C to 85 °C Inhibit threshold VI = 2.7 to 5.5 V (1) 2.5 mA 1 µA 2 Device ON, VI = 2.7 to 5.5 V 1.3 Device ON, VI = 2.7 to 5 V 1.2 A V Device OFF IINH % 0.4 Inhibit pin current 2 µA %VO/ ΔVI %VO/ΔVI Output line regulation VI = 2.7 V to 5.5 V, IO = 100 mA (1) 0.16 %VO/ΔIO Output load regulation IO = 10 mA to 2 A (1) 0.2 0.6 %VO/ ΔIO PWM switching frequency VFB = 0.65 V 1.2 1.5 1.8 MHz 80 87 % PWMfS DMAX Maximum duty cycle RDSON-N NMOS switch on resistance ISW = 750 mA 0.1 Ω RDSON-P PMOS switch on resistance ISW = 750 mA 0.1 Ω Switching current limitation (1) 2.5 IO = 10 mA to 100 mA, VO = 3.3 V 65 IO = 100 mA to 2 A, VO = 3.3 V 82 ISWL ν TSHDN THYS Efficiency (1) 2.9 3.5 A % 87 Thermal shutdown 150 °C Thermal shutdown hysteresis 20 °C %VO/ΔIO Load transient response IO = 100 mA to 1 A, TA = 25 °C tR = tF ≥ 200 ns (1) -10 +10 %VO %VO/ΔIO Short circuit removal response IO = 10 mA to IO = short, TA = 25 °C (1) -10 +10 %VO 1. Guaranteed by design, but not tested in production. Doc ID 13632 Rev 4 7/18 Typical performance characteristics 5 ST1S09 Typical performance characteristics L = 3.3 µH, CI = 4.7 µF, CO = 22 µF, unless otherwise specified. 840 830 820 810 800 790 780 770 760 Voltage feedback vs. temperature Figure 4. VI=5V, IO=10mA VO@1.2V IFBK [nA] VFBK [mV] Figure 3. -75 -50 -25 0 25 50 75 Feedback pin bias current vs. temp. 840 740 640 540 440 340 240 140 40 -60 VI=5V -75 100 125 150 175 -50 -25 0 25 T [°C] Figure 5. 3 Quiescent current non switching vs. temperature VI=5V Figure 6. VO@1.2V 2 VINH [V] Iq [mA] 2.5 1.5 1 0.5 0 -75 -50 -25 0 25 50 75 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 VI=5V, IO=from 10mA to 2A -75 100 125 150 175 Inhibit voltage vs. input voltage Figure 8. -50 -25 0 25 50 75 100 125 150 175 ON Output voltage vs. input voltage VO@1.2V 1.20 OFF 1.00 VO [V] VINH [V] OFF T [°C] VI=from 2.7 to 5.5V, IO=2A 0.80 0.60 0.40 0.20 2 3 4 5 VI [V] 6 7 VCC =VINH=from 0 to 5.5V, IO=2A 0.00 0 1 2 3 VI [V] 8/18 100 125 150 175 ON 1.40 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 75 Inhibit voltage vs. temperature T [°C] Figure 7. 50 T [°C] Doc ID 13632 Rev 4 4 5 6 ST1S09 Typical performance characteristics 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 Line regulation vs. temperature VO@1.2V Figure 10. Load regulation vs. temperature VI = from 2.7V to 5.5V, IO = 100mA load [%VO/ΔIO] line [%VOt/ΔVI] Figure 9. -75 -50 -25 0 25 50 75 1.1 0.9 0.7 0.5 0.3 0.1 -0.1 -0.3 -0.5 VI = 5V, IO from10mA to 2A VO@1.2V -75 -50 -25 100 125 150 175 0 25 VO@1.2V -75 -50 -25 VI=5V, VFB=0.6V 0 25 50 75 100 125 150 175 90 88 86 84 82 80 78 76 74 72 70 VO@3.3V -75 -50 -25 0 25 50 75 100 125 150 175 T [°C] Figure 13. Under voltage lock out threshold vs. temperature Figure 14. Efficiency vs. output current 95 85 Efficiency [%] UVLO [V] 100 125 150 175 VI=5V, VFB=0.6V T [°C] 4 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3 75 Figure 12. Maximum duty cycle vs. temperature Dmax[%] PWM freq.[MHz] Figure 11. PWM Switching frequency vs. temperature 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 50 T [°C] T [°C] -50 -25 VO=1.2V 65 55 VIN=5V 45 35 VO@1.2V -75 VO=3.3V 75 IO=10mA 0 25 50 75 100 125 150 175 25 0 500 1000 Iout [mA] 1500 2000 T [°C] Doc ID 13632 Rev 4 9/18 Typical performance characteristics ST1S09 Figure 16. Over voltage protection vs. temperature 1.4 100 95 90 85 80 75 70 65 60 55 50 45 40 Resistor 1.2kΩ from VI and VSW VO=3.3V 1.3 VSW=1.2V OVP %VO Efficiency [%] Figure 15. Efficiency vs. temperature VO=1.2V VI=5V, IO=100mA VI=5V, VO=3.3V, CFB=100nF 1.2 1.1 OVP ON 1 0.9 0.8 -75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 T [°C] Figure 17. Over voltage protection vs. temperature 75 100 125 150 175 Figure 18. Over voltage protection hyst. vs. temperature 14 1.4 OVP % Hysteresis Resistor 1.2kΩ from VI and VSW 1.3 VSW=0.8V OVP %VO 50 T [°C] VI=5V, VO=3.3V, CFB=100nF 1.2 1.1 OVP ON 1 0.9 Resistor 1.2kΩ from VI and VSW 12 VSW=0.8V 10 VI=5V, VO=3.3V, CFB=100nF 8 6 4 OVP ON 2 0 0.8 -75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175 T [°C] T [°C] Figure 19. Load transient Figure 20. Inhibit transient VINH VO VO IO IO VI = 5 V, VO = 1.2 V, IO = 100 mA to1 A, L = 3.3 µH, CI = 4.7 µF, CO = 22 µF 10/18 VI = 5V, VINH = 0 to 2 V, IO = 2 A, L = 3.3 µH, CI = 4.7 µF, CO = 22 µF, VO = 3.3 V Doc ID 13632 Rev 4 ST1S09 6 Typical application Typical application Figure 21. Application circuits Figure 22. Application circuits Doc ID 13632 Rev 4 11/18 Application information 7 ST1S09 Application information The ST1S09 is an adjustable current mode PWM step-down DC-DC converter with internal 2 A power switch, packaged in a DFN6 3 x 3 mm. The device is a complete 2 A switching regulator with its internal compensation eliminating the need for additional components. The constant frequency, current mode, PWM architecture and stable operation with ceramic capacitors results in low, predictable output ripple. The over-voltage protection circuit acts when the output voltage is over 10 % of the rated voltage and within 200 ns the low side MOSFET will be turned on to clamp the output transient. The current limit for clamping is about 400 mA. When the output voltage drops to about 5 % above the nominal level, the device returns to nominal closed loop switching operation. The open drain Power Good (PG) pin is released when the output voltage is higher than 0.92 x VO_NOM. If the output voltage is below 0.92 x VO, the PG pin goes to low impedance. Other circuits fitted to the device protection are the thermal shut-down block, which turns off the regulator when the junction temperature exceeds 150 °C (typ), and the cycle-by-cycle current limiting, which provides protection against shorted outputs. As an adjustable regulator, the ST1S09’s output voltage is determined by an external resistor divider. The desired value is given by the following equation: Equation 1 VO = VFB [1 + R1 / R2] To utilize the device, only a few components are required: an inductor, two capacitors and the resistor divider. The inductor chosen must be able to reach peak current level without saturating. Its value can be selected while taking into account that a large inductor value increases the efficiency at low output current and reduces output voltage ripple, while a smaller inductor can be chosen when it is important to reduce package size and the total cost of the application. Finally, the ST1S09 has been designed to work properly with X5R or X7R SMD ceramic capacitors both at the input and at the output. These types of capacitors, due to their very low series resistance (ESR), minimize the output voltage ripple. Other low ESR capacitors can be used according to the need of the application without compromising the correct functioning of the device. 12/18 Doc ID 13632 Rev 4 ST1S09 8 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 13632 Rev 4 13/18 Package mechanical data ST1S09 DFN6D (3x3) Mechanical Data mm. inch. Dim. Min. A 0.80 A1 0 A3 0.02 Max. Min. 1.00 0.031 0.05 0 0.20 b 0.23 D 2.90 D2 2.23 E 2.90 E2 1.50 e L Typ. 3.00 3.00 0.40 Max. 0.039 0.001 0.002 0.008 0.45 0.009 3.10 0.114 2.50 0.088 3.10 0.114 1.75 0.059 0.95 0.30 Typ. 0.018 0.118 0.122 0.098 0.118 0.122 0.069 0.037 0.50 0.012 0.016 0.020 7946637B 14/18 Doc ID 13632 Rev 4 ST1S09 Package mechanical data Figure 23. DFN6 (3 x 3 mm) footprint recommended data Doc ID 13632 Rev 4 15/18 Package mechanical data ST1S09 Tape & Reel QFNxx/DFNxx (3x3) Mechanical Data mm. inch. Dim. Min. Typ. A Min. Typ. 330 13.2 12.8 D 20.2 0.795 N 60 2.362 0.504 0.519 18.4 0.724 Ao 3.3 0.130 Bo 3.3 0.130 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 Doc ID 13632 Rev 4 Max. 12.992 C T 16/18 Max. ST1S09 Revision history 9 Revision history Table 8. Document revision history Date Revision Changes 18-Jun-2007 1 First release. 05-Jul-2007 2 Removed incorrect watermark. 31-Jan-2008 3 Modified: Table 6 on page 6. 19-Apr-2010 4 Modified: Table 1 on page 1. Doc ID 13632 Rev 4 17/18 ST1S09 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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