ST1S31PUR

ST1S31 3 A DC step-down switching regulator Datasheet - production data Applications  µP/ASIC/DSP/FPGA core and I/O supplies  Point of load for: STB, TVs, DVDs  Optical storage, hard disk drive, printers, audio/graphic cards VFDFPN 3 x 3 - 8L SO8 Description The ST1S31 device is an internally compensated 1.5 MHz fixed-frequency PWM synchronous stepdown regulator. The ST1S31 operates from 2.8 V to 5.5 V input, while it regulates an output voltage as low as 0.8 V and up to VIN. Features  3 A DC output current  2.8 V to 5.5 V input voltage  Output voltage adjustable from 0.8 V The ST1S31 integrates a 60 m high-side switch and a 45 m synchronous rectifier allowing very high efficiency with very low output voltages.  1.5 MHz switching frequency  Internal soft-start and enable  Integrated 60 m and 45 m power MOSFETs  All ceramic capacitor  Power Good (POR) The peak current mode control with internal compensation delivers a very compact solution with a minimum component count. The ST1S31 device is available in 3 mm x 3 mm, 8 lead VFDFPN and SO8 packages.  Cycle-by-cycle current limiting  Current foldback short-circuit protection  VFDFPN 3 x 3 - 8L, SO8 packages Figure 1. Application circuit / 9,1 9,16: 9287 6: 9,1$ &LQBD (1 5 676 9)% &LQBVZ &RXW 3* *1' 5 August 2018 This is information on a product in full production. DocID022998 Rev 5 1/36 www.st.com Contents ST1S31 Contents 1 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 4.1 Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 Error amplifier and control loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 Light load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4 Thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 Layout consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2/36 8.1 VFDFPN 3 x 3 - 8L package information . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.2 SO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DocID022998 Rev 5 ST1S31 Contents 9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DocID022998 Rev 5 3/36 36 Pin settings ST1S31 1 Pin settings 1.1 Pin connection Figure 2. Pin connection (top view) 1.2 Pin description Table 1. Pin description 4/36 No. Type Description 1 VINA 2 EN Enable input. With EN higher than 1.5 V the device is ON and with EN lower than 0.5 V the device is OFF. 3 FB Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.8 V. To have higher regulated voltages an external resistor divider is required from VOUT to the FB pin. 4 AGND Unregulated DC input voltage Ground Open drain Power Good (POR) pin. It is released (open drain) when the output voltage is higher than 0.92 * VOUT with a delay of 170 s. If the output voltage is below 0.92 * VOUT, the POR pin goes to low impedance immediately. If not used, it can be left floating or to GND. 5 PG 6 VINSW 7 SW 8 PGND Power ground ePAD (VFDFPN package only) exposed pad connected to ground assuring electrical contact and heat conduction. Power input voltage Regulator output switching pin DocID022998 Rev 5 ST1S31 2 Maximum ratings Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Value VIN Input voltage VEN Enable voltage VSW Output switching voltage VPG Power-on reset voltage (Power Good) -0.3 to VIN VFB Feedback voltage -0.3 to 1.5 PTOT Power dissipation at TA < 60 °C TOP Tstg Unit -0.3 to 7 -0.3 to VIN -1 to VIN V 1.5 (VFDFPN) 0.9 (SO8) W Operating junction temperature range -40 to 150 °C Storage temperature range -55 to 150 °C Thermal data Table 3. Thermal data Symbol RthJA Parameter Maximum thermal resistance junction ambient(1) Value VFDFPN 50 SO8 100 Unit °C/W 1. Package mounted on demonstration board. DocID022998 Rev 5 5/36 36 Electrical characteristics 3 ST1S31 Electrical characteristics TJ = 25 °C, VIN = 5 V, unless otherwise specified. Table 4. Electrical characteristics Values Symbol Parameter Test condition Unit Min. Typ. Operating input voltage range (1) VINON Turn-on VCC threshold (1) 2.4 VINOFF Turn-off VCC threshold (1) 2.0 VIN 2.8 Max. 5.5 V RDSON-P High-side switch ON-resistance ISW = 300 mA 60 m RDSON-N Low-side switch ON-resistance ISW = 300 mA 45 m Maximum limiting current (2) ILIM 4.0 A Oscillator FSW DMAX Switching frequency Maximum duty cycle 1.2 (2) 1.5 95 1.9 MHz 100 % Dynamic characteristics VFB Feedback voltage (1) Io = 10 mA to 4 A 0.792 0.8 0.808 0.776 0.8 0.824 V %VOUT/ IOUT Reference load regulation Io = 10 mA to 4 A(2) 0.2 0.6 % %VOUT/ VIN Reference line regulation VIN = 2.8 V to 5.5 V(2) 0.2 0.3 % Quiescent current Duty cycle = 0, no load VFB = 1.2 V 630 1200 µA Total standby quiescent current OFF 1 µA DC characteristics IQ IQST-BY Enable Device ON level VEN EN threshold voltage IEN EN current 1.5 V Device OFF level 0.5 0.1 µA Power Good PG threshold 92 PG hystereris 30 %VFB 50 PG mV PG output voltage low Isink = 6 mA open drain PG rise delay 6/36 400 170 DocID022998 Rev 5 µs ST1S31 Electrical characteristics Table 4. Electrical characteristics (continued) Values Symbol Parameter Test condition Unit Min. Typ. Max. Soft-start TSS Soft-start duration 400 Thermal shutdown 150 Hystereris 20 µs Protection TSHDN °C 1. Specification referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are assured by design, characterization and statistical correlation. 2. Guaranteed by design. DocID022998 Rev 5 7/36 36 Functional description 4 ST1S31 Functional description The ST1S31 device is based on a “peak current mode”, constant frequency control. The output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.8 V) providing an error signal that, compared to the output of the current sense amplifier, controls the ON and OFF time of the power switch. The main internal blocks are shown in the block diagram in Figure 3. They are:  A fully integrated oscillator that provides the internal clock and the ramp for the slope compensation avoiding sub-harmonic instability  The soft-start circuitry to limit inrush current during the startup phase  The transconductance error amplifier  The pulse width modulator and the relative logic circuitry necessary to drive the internal power switches  The drivers for embedded P-channel and N-channel power MOSFET switches  The high-side current sensing block  The low-side current sense to implement diode emulation  A voltage monitor circuitry (UVLO) that checks the input and internal voltages  A thermal shutdown block, to prevent thermal runaway. Figure 3. Block diagram AM11417v1 8/36 DocID022998 Rev 5 ST1S31 4.1 Functional description Output voltage adjustment The error amplifier reference voltage is 0.8 V typical. The output voltage is adjusted according to the following formula (see Figure 1 on page 1): Equation 1 R1 V OUT = 0.8   1 + ------- R2 The internal architecture of the device requires a minimum off time, cycle-by-cycle, for the output voltage regulation. The minimum off time is typically equal to 94 ns. The control loop compensates for conversion losses with duty cycle control. Since the power losses are proportional to the delivered output power, the duty cycle increases with the load current request. Figure 4 shows the maximum regulated output voltage over the input voltage range at different loading conditions. Figure 4. Maximum output voltage over loading conditions 4.2 Soft-start The soft-start is essential to assure the correct and safe startup of the step-down converter. It avoids inrush current surge and makes the output voltage rise monotonically. The soft-start is managed by ramping the reference of the error amplifier from 0 V to 0.8 V. The internal soft-start capacitor is charged with a resistor to 0.8 V, then the FB pin follows the reference so that the output voltage is regulated to rise to the set value monotonically. DocID022998 Rev 5 9/36 36 Functional description 4.3 ST1S31 Error amplifier and control loop stability The error amplifier provides the error signal to be compared with the high-side switch current through the current sense circuitry. The non inverting input is connected with the internal 0.8 V reference, while the inverting input is the FB pin. The compensation network is internal and connected between the E/A output and GND. The error amplifier of the ST1S31 device is a transconductance operational amplifier, with high bandwidth and high output impedance. Table 5. Characteristics of the uncompensated error amplifier Description Value DC gain 94 dB gm 238 µA/V Ro 96 M The ST1S31 device embeds the compensation network that assures the stability of the loop in the whole operating range. All the tools needed to check the loop stability are shown on the next pages of this section. In Figure 5 the simple small signal model for the peak current mode control loop is shown. Figure 5. Block diagram of the loop for the small signal analysis VIN GCO(s) Slope Compensation High side Switch L Current sense Logic And Driver VOUT GDIV (s) Cout Low side Switch PWM comparator 0.8V R1 VC Rc VFB Error Amp R2 Cc G EA(s) AM11418v1 Three main terms can be identified to obtain the loop transfer function: 1. From control (output of E/A) to output, GCO(s) 2. From output (VOUT) to the FB pin, GDIV(s) 3. From the FB pin to control (output of E/A), GEA(s). The transfer function from control to output GCO(s) results: 10/36 DocID022998 Rev 5 ST1S31 Functional description Equation 2 s  1 + ----  z R LOAD 1 G CO  s  = ------------------  ---------------------------------------------------------------------------------------------  ----------------------  F H  s  Ri R out  T SW s  ------ 1 + ----------------------------   m C   1 – D  – 0.5   1 +  L p where RLOAD represents the load resistance, Ri the equivalent sensing resistor of the current sense circuitry (0.369 ), p the single pole introduced by the LC filter and z the zero given by the ESR of the output capacitor. FH(s) accounts for the sampling effect performed by the PWM comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency. Equation 3 1  Z = ------------------------------ESR  C OUT Equation 4 m C   1 – D  – 0.5 1  p = -------------------------------------- + --------------------------------------------R LOAD  C OUT L  C OUT  f SW where: Equation 5 Se   m C = 1 + -----Sn  S = V  f pp SW  e  V IN – V OUT  S = -----------------------------  Ri  n L Sn represents the ON-time slope of the sensed inductor current, Se the slope of the external ramp (VPP peak-to-peak amplitude - 0.535 V) that implements the slope compensation to avoid sub-harmonic oscillations at duty cycle over 50%. The sampling effect contribution FH(s) is: Equation 6 1 F H  s  = -----------------------------------------2 s s 1 + ------------------- + ------2 n  QP  n where: Equation 7 1 Q P = ---------------------------------------------------------   m C   1 – D  – 0.5  and Equation 8  n =   f SW DocID022998 Rev 5 11/36 36 Functional description ST1S31 The resistor to adjust the output voltage that gives the term from output voltage to the FB pin. GDIV(s) is: R2 G DIV  s  = -------------------R1 + R2 The transfer function from FB to Vc (output of E/A) introduces the singularities (poles and zeroes) to stabilize the loop. The small signal model of the error amplifier with the internal compensation network can be seen in Figure 6. Figure 6. Small signal model for the error amplifier V FB Ro Vd Gm*Vd Co Rc Cc Cp Cc VREF AM11419v1 RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability and can be neglected. So GEA(s) results: Equation 9 G EA0   1 + s  R c  C c  G EA  s  = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 s  R0   C0 + Cp   Rc  Cc + s   R0  Cc + R0   C0 + Cp  + Rc  Cc  + 1 where GEA = Gm · Ro. The poles of this transfer function are (if Cc >> C0+CP): Equation 10 1 f P LF = ---------------------------------2    R0  Cc Equation 11 1 f P HF = ---------------------------------------------------2    Rc   C0 + Cp  whereas the zero is defined as: Equation 12 1 f Z = --------------------------------2    Rc  Cc 12/36 DocID022998 Rev 5 ST1S31 Functional description The embedded compensation network is RC = 80 k, CC = 55 pF while CP and CO can be considered as negligible. The error amplifier output resistance is 96 Mso the relevant singularities are: Equation 13 f Z = 36 2 kHz f P LF = 30 Hz So closing the loop, the loop gain GLOOP(s) is: Equation 14 G LOOP  s  = G CO  s   G DIV  s   G EA  s  Example 1: VIN = 5 V, VOUT = 1.2 V, Iomax = 3 A, L = 1.0 H, Cout = 47 µF (MLCC), R1 = 10 k, R2 = 20 k(see Section 5.2 and Section 5.3 for inductor and output capacitor selection guidelines). The module and phase bode plot are reported in Figure 7 and Figure 8. The bandwidth is 117 kHz and the phase margin is 63 degrees. Figure 7. Module bode plot DocID022998 Rev 5 13/36 36 Functional description ST1S31 Figure 8. Phase bode plot 4.4 Overcurrent protection The ST1S31 device implements overcurrent protection sensing the current flowing through the high-side current switch. If the current exceeds the overcurrent threshold the high-side is turned off, implementing a cycle-by-cycle current limitation. Since the regulation loop is no longer fixing the duty cycle, the output voltage is unregulated and the FB pin falls accordingly to the new duty cycle. If the FB falls below 0.2 V, the peak current limit is reduced to around 2.3 A and the switching frequency is reduced to assure that the inductor current is properly limited below the above mentioned value and above 1.2 A. This strategy is called “current foldback”. The mechanism to adjust the switching frequency during the current foldback condition exploits the low-side current sense circuitry. If FB is lower than 0.2 V, the high-side power MOSFET is turned off when the current reaches the current foldback threshold (2.3 A), then, after a proper deadtime that avoids the cross conduction, the low-side is turned on until the low-side current is lower than a valley threshold (1.2 A). Once the low-side is turned off, the high-side is immediately turned on. In this way the frequency is adjusted to keep the inductor current ripple between the current foldback value (2.3 A) and valley threshold (1.2 A), so properly limiting the output current in case of overcurrent or short-circuit. It should be noted that in some cases, mainly with very low output voltages, the hard overcurrent can cause the FB to find the new equilibrium just over the current foldback threshold (0.2 V). In this case no frequency reduction is enabled, then the inductor current may diverge. This means that the ripple current during the minimum ON-time is higher than the ripple current during the OFF-time (the switching period minus the minimum ON-time), so pulse-by-pulse, the average current is rising, exceeding the current limit. In order to avoid too high current, a further protection is activated when the high-side current exceeds a further current threshold (OCP2) slightly over the current limit (OCP1). If the current triggers the second threshold, the converter stops switching, the reference of the error amplifier is pulled down and then it restarts with a soft-start procedure. If the overcurrent condition is still active, the current foldback with frequency reduction properly limits the output current to 2.3 A. 14/36 DocID022998 Rev 5 ST1S31 4.5 Functional description Enable function The enable feature allows the device to be put into standby mode. With the EN pin is lower than 0.4 V, the device is disabled and the power consumption is reduced to less than 10 A. With the EN pin higher than 1.2 V, the device is enabled. If the EN pin is left floating, an internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VIN compatible. 4.6 Light load operation With peak current mode control loop the output of the error amplifier is proportional to the load current. In the ST1S31 device, to increase light load efficiency when the output of the error amplifier falls below a certain threshold, the high-side turn-on is prevented. This mechanism reduces the switching frequency at light load in order to save the switching losses. 4.7 Hysteretic thermal shutdown The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C, the device restarts in normal operation. DocID022998 Rev 5 15/36 36 Application information ST1S31 5 Application information 5.1 Input capacitor selection The capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 15 2 2 2D D I RMS = I O  D – --------------- + ------2  where Io is the maximum DC output current, D is the duty cycle, and is the efficiency. Considering = 1, this function has a maximum at D = 0.5 and is equal to Io/2. The peak-to-peak voltage across the input capacitor can be calculated as: Equation 16 IO D D V PP = -------------------------   1 – ----  D + ----   1 – D  + ESR  I O C IN  F SW    where ESR is the equivalent series resistance of the capacitor. Given the physical dimension, ceramic capacitors can well meet the requirements of the input filter sustaining a higher input RMS current than electrolytic / tantalum types. In this case the equation of CIN as a function of the target peak-to-peak voltage ripple (VPP) can be written as follows: Equation 17 IO D D C IN = ---------------------------   1 – ----  D + ----   1 – D  V PP  F SW    neglecting the small ESR of ceramic capacitors. Considering = 1, this function has its maximum in D = 0.5, therefore, given the maximum peak-to-peak input voltage (VPP_MAX), the minimum input capacitor (CIN_MIN) value is: Equation 18 IO C IN_MIN = -----------------------------------------------2  V PP_MAX  F SW Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage ripple in the order of 1% of VINMAX. 16/36 DocID022998 Rev 5 ST1S31 Application information The placement of the input capacitor is very important to avoid noise injection and voltage spikes on the input voltage pin. So the CIN must be placed as close as possible to the VIN_SW pin. In Table 6 some multilayer ceramic capacitors suitable for this device are given. Table 6. Input MLCC capacitors Manufacturer Series Cap value (µF) Rated voltage (V) Murata GRM21 10 10 C3225 10 25 C3216 10 16 LMK212 22 10 TDK TAIYO YUDEN A ceramic bypass capacitor, as close as possible to the VINA pin so that additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability on the output voltage due to noise. The value of the bypass capacitor can go from 330 nF to 1 µF. 5.2 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value to have the expected current ripple must be selected. The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current. In continuous current mode (CCM), the inductance value can be calculated by Equation 19: Equation 19 V IN – V OUT V OUT I L = ------------------------------  T ON = --------------  T OFF L L where TON is the conduction time of the high-side switch and TOFF is the conduction time of the low-side switch (in CCM, FSW = 1/(TON + TOFF)). The maximum current ripple, given the VOUT, is obtained at maximum TOFF, that is, at minimum duty cycle (see previous section to calculate minimum duty). So by fixing IL = 20% to 30% of the maximum output current, the minimum inductance value can be calculated: Equation 20 V OUT 1 – D MIN L MIN = ----------------  ----------------------I MAX F SWMIN where FSWMIN is the minimum switching frequency, according to Table 4. The slope compensation, to prevent the sub-harmonic instability in the peak current control loop, is internally managed and so fixed. This implies a further lower limit for the inductor value. To assure sub-harmonic stability: Equation 21 L  V out   2  V pp  f sw  where VPP is the peak-to-peak value of the slope compensation ramp. The inductor value selected based on Equation 20 must satisfy Equation 21. The peak current through the inductor is given by Equation 22: DocID022998 Rev 5 17/36 36 Application information ST1S31 Equation 22 I L I L PK = I O + -------2 So if the inductor value decreases, the peak current (which must be lower than the current limit of the device) increases. The higher the inductor value, the higher the average output current that can be delivered, without reaching the current limit. In Table 7 some inductor part numbers are listed. Table 7. Inductors Manufacturer Coilcraft Series Inductor value (µH) Saturation current (A) XAL50xx 1.2 to 3.3 6.3 to 9 XAL60xx 2.2 to 5.6 7.4 to 11 MSS1048 1.0 to 3.8 6.5 to 11 WE-HCI 7030 1.5 to 4.7 7 to 14 WE-PD type L 1.5 to 3.5 6.4 to 10 DR73 1.0 to 2.2 5.5 to7.9 DR74 1.5 to 3.3 5.4 to 8.35 Würth Coiltronics 5.3 Output capacitor selection The current in the output capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. Equation 23 I MAX V OUT = ESR  I MAX + ------------------------------------8  C OUT  f SW For a ceramic (MLCC) capacitor, the capacitive component of the ripple dominates the resistive one. While for an electrolytic capacitor the opposite is true. As the compensation network is internal, the output capacitor should be selected in order to have a proper phase margin and then a stable control loop. The equations of Section 5.2 help to check loop stability given the application conditions, the value of the inductor and of the output capacitor. 18/36 DocID022998 Rev 5 ST1S31 Application information In Table 8 some capacitor series are listed. Table 8. Output capacitors Series Cap value (µF) Rated voltage (V) ESR (m) GRM32 22 to 100 6.3 to 25