ST1S32
4 A DC step-down switching regulator
Datasheet — production data
Features
■
4 A DC output current
■
2.8 V to 5.5 V input voltage
■
Output voltage adjustable from 0.8 V
■
1.5 MHz switching frequency
■
Internal soft-start and enable
■
Integrated 60 mΩ and 45 mΩ Power MOSFETs
■
All ceramic capacitor
■
Power Good (POR)
■
Cycle-by-cycle current limiting
■
Current foldback short-circuit protection
■
VFDFPN 8 4x4x1.0 package
VFDFPN 8 4x4x1.0
Description
The ST1S32 is an internally compensated 1.5
MHz fixed-frequency PWM synchronous stepdown regulator. The ST1S32 operates from 2.8 V
to 5.5 V input, while it regulates an output voltage
as low as 0.8 V and up to VIN.
Applications
■
µP/ASIC/DSP/FPGA core and I/O supplies
■
Point of Load for: STB, TV, DVD
■
Optical storage, hard disk drives, printers,
audio/graphic cards
The ST1S32 integrates a 60 mΩ high-side switch
and a 45 mΩ synchronous rectifier, allowing very
high efficiency with very low output voltages.
The peak current mode control with internal
compensation delivers a very compact solution
with a minimum component count.
The ST1S32 is available in 4 mm x 4 mm, 8-lead
VFDFPN package.
Figure 1.
Application circuit
L
VIN
VINSW
VOUT
SW
VINA
Cin_a
R3
R1
ST1S32
EN
VFB
Cout
PG
Cin_sw
GND
R2
AM12608V1
May 2012
This is information on a product in full production.
Doc ID 023246 Rev 1
1/29
www.st.com
29
Contents
ST1S32
Contents
1
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
4.1
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
Error amplifier and control loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5
Light load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6
Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4
Thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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Doc ID 023246 Rev 1
ST1S32
Pin settings
1
Pin settings
1.1
Pin connection
Figure 2.
1.2
Pin connection (top view)
Pin description
Table 1.
Pin description
No.
Type
1
VINA
2
EN
Enable input. With EN higher than 1.5 V the device in ON and with EN
lower than 0.5 V the device is OFF.
3
FB
Feedback input. Connecting the output voltage directly to this pin the
output voltage is regulated at 0.8 V. To have higher regulated voltages an
external resistor divider is required from VOUT to the FB pin.
4
AGND
5
PG
6
VINSW
7
SW
8
PGND
Description
Unregulated DC input voltage.
Ground.
Open drain Power Good (POR) pin. It is released (open drain) when the
output voltage is higher than 0.92 * VOUT with a delay of 170 us. If the
output voltage is below 0.92 * VOUT, the POR pin goes to low impedance
immediately.
If not used, it can be left floating or to GND.
Power input voltage.
Regulator output switching pin.
Power Ground.
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Maximum ratings
2
ST1S32
Maximum ratings
Table 2.
Absolute maximum ratings
Symbol
2.1
Parameter
VIN
Input voltage
VEN
Enable voltage
VSW
Output switching voltage
VPG
Power-on reset voltage (Power Good)
-0.3 to VIN
VFB
Feedback voltage
-0.3 to 1.5
PTOT
Power dissipation at TA < 60 °C
TOP
Tstg
Unit
-0.3 to 7
-0.3 to VIN
-1 to VIN
V
2.25
W
Operating junction temperature range
-40 to 150
°C
Storage temperature range
-55 to 150
°C
Value
Unit
40
°C/W
Thermal data
Table 3.
Symbol
RthJA
Thermal data
Parameter
Maximum thermal resistance junctionambient (1)
1. Package mounted on demonstration board.
4/29
Value
Doc ID 023246 Rev 1
ST1S32
3
Electrical characteristics
Electrical characteristics
TJ=25 °C, VIN=5 V, unless otherwise specified.
Table 4.
Electrical characteristics
Values
Symbol
Parameter
Test condition
Unit
Min.
Typ.
VIN
Operating input voltage
range
(1)
VINON
Turn-on VCC threshold
(1)
2.4
VINOFF
Turn-off VCC threshold
(1)
2.0
2.8
Max.
5.5
V
RDSON-P
High-side switch onresistance
ISW=300 mA
60
mΩ
RDSON-N
Low-side switch onresistance
ISW=300 mA
45
mΩ
ILIM
Maximum limiting current (2)
5.0
Switching frequency
1.2
A
Oscillator
FSW
DMAX
Maximum duty cycle
(2)
1.5
95
1.9
MHz
100
%
Dynamic characteristics
VFB
Feedback voltage
Io=10 mA to 4 A(1)
0.792
0.8
0.808
0.776
0.8
0.824
V
%VOUT/
ΔIOUT
Reference load regulation Io=10 mA to 4 A(2)
0.2
0.6
%
%VOUT/
ΔVIN
Reference line regulation VIN= 2.8 V to 5.5 V (2)
0.2
0.3
%
630
1200
μA
10
μA
DC characteristics
IQ
IQST-BY
Quiescent current
Duty cycle=0, no load
VFB=1.2 V
Total standby quiescent
current
OFF
Enable
Device ON level
VEN
EN threshold voltage
IEN
EN current
1.5
V
Device OFF level
0.5
0.1
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μA
5/29
Electrical characteristics
Table 4.
ST1S32
Electrical characteristics (continued)
Values
Symbol
Parameter
Test condition
Unit
Min.
Typ.
Max.
Power Good
PG threshold
92
PG hystereris
30
%VFB
50
PG
mV
PG output voltage low
Isink= 6 mA open drain
400
170
μs
Soft-start duration
400
μs
Thermal shutdown
150
Hystereris
20
PG rise delay
Soft-start
TSS
Protection
TSHDN
°C
1. Specifications referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range
are assured by design, characterization and statistical correlation.
2. Guaranteed by design.
6/29
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ST1S32
4
Functional description
Functional description
The ST1S32 is based on a “peak current mode”, constant frequency control. The output
voltage VOUT is sensed by the Feedback pin (FB) compared to an internal reference (0.8 V)
providing an error signal that, compared to the output of the current sense amplifier, controls
the ON and OFF time of the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
●
A fully integrated oscillator that provides the internal clock and the ramp for the slope
compensation avoiding sub-harmonic instability
●
The soft-start circuitry to limit inrush current during the startup phase
●
The transconductance error amplifier
●
The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switches
●
The drivers for embedded P-channel and N-channel Power MOSFET switches
●
The high-side current sensing block
●
The low-side current sense to implement diode emulation
●
A voltage monitor circuitry (UVLO) that checks the input and internal voltages
●
A thermal shutdown block, to prevent thermal run-away.
Figure 3.
Block diagram
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Functional description
4.1
ST1S32
Soft-start
The soft-start is essential to assure the correct and safe startup of the step-down converter.
It avoids inrush current surge and makes the output voltage rise monothonically.
The soft-start is managed by ramping the reference of the error amplifier from 0 V to 0.8 V.
The internal soft-start capacitor is charged with a resistor to 0.8 V, then the FB pin follows
the reference so that the output voltage is regulated to rise to the set value monothonically.
4.2
Error amplifier and control loop stability
The error amplifier provides the error signal to be compared with the high-side switch
current through the current sense circuitry. The non-inverting input is connected with the
internal 0.8 V reference, whilst the inverting input is the FB pin. The compensation network
is internal and connected between the E/A output and GND.
The error amplifier of the ST1S32 is a transconductance operational amplifier, with high
bandwidth and high output impedance.
The characteristics of the uncompensated error amplifier are:
Table 5.
Characteristics of the uncompensated error amplifier
Description
Value
DC gain
94 dB
gm
238 μA/V
Ro
96 MΩ
The ST1S32 embeds the compensation network that assures the stability of the loop in the
whole operating range. Here below are all the tools needed to check the loop stability.
In Figure 4. the simple small signal model for the peak current mode control loop is shown.
8/29
Doc ID 023246 Rev 1
ST1S32
Functional description
Figure 4.
Block diagram of the loop for the small signal analysis
VIN
GCO(s)
Slope
Compensation
High side
Switch
L
Current sense
Logic
And
Driver
VOUT
GDIV (s)
Cout
Low side
Switch
PWM comparator
0.8V
R1
VC
Rc
VFB
Error Amp
R2
Cc
G EA(s)
AM12609V1
Three main terms can be identified to obtain the loop transfer function:
1.
from control (output of E/A) to output, GCO(s);
2.
from output (VOUT) to the FB pin, GDIV(s);
3.
from the FB pin to control (output of E/A), GEA(s).
The transfer function from control to output GCO(s) results:
Equation 1
R LOAD
1
G CO ( s ) = ------------------ ⋅ ----------------------------------------------------------------------------------------------------- ⋅
Ri
R out ⋅ TSW
1 + ------------------------------ ⋅ [ m C ⋅ ( 1 – D ) – 0.5 ]
L
s-⎞
⎛ 1 + ---⎝
ωz⎠
--------------------- ⋅ FH ( s )
s⎞
⎛ 1 + ---⎝
ωp⎠
where RLOAD represents the load resistance, Ri the equivalent sensing resistor of the
current sense circuitry (0.369 Ω), ωp the single pole introduced by the LC filter and ωz the
zero given by the ESR of the output capacitor.
FH(s) accounts for the sampling effect performed by the PWM comparator on the output of
the error amplifier that introduces a double pole at one half of the switching frequency.
Equation 2
1
ωZ = ---------------------------------ESR ⋅ C OUT
Doc ID 023246 Rev 1
9/29
Functional description
ST1S32
Equation 3
m C ⋅ ( 1 – D ) – 0.5
1
ωp = ---------------------------------------+ ----------------------------------------------R LOAD ⋅ C OUT
L ⋅ C OUT ⋅ f SW
where:
Equation 4
Se
⎛
⎜ m C = 1 + -----Sn
⎜
⎜S = V ⋅ f
pp
SW
⎜ e
⎜
V
–
V
IN
OUT
⎜ S = ----------------------------- ⋅ Ri
⎝ n
L
Sn represents the ON-time slope of the sensed inductor current, Se the slope of the external
ramp (VPP peak-to-peak amplitude - 0.535 V) that implements the slope compensation to
avoid sub-harmonic oscillations at duty cycle over 50%.
The sampling effect contribution FH(s) is:
Equation 5
1
F H ( s ) = -----------------------------------------2
s
s
1 + --------------------- + ----ωn ⋅ Q P ω2
n
where:
Equation 6
1
Q P = --------------------------------------------------------------π ⋅ [ m C ⋅ ( 1 – D ) – 0.5 ]
and
Equation 7
ωn = π ⋅ fSW
The transfer function GDIV(s) from VOUT to FB results:
R2
G DIV ( s ) = ------------------R1 + R2
The transfer function from FB to Vc (output of E/A) introduces the singularities (poles and
zeroes) to stabilize the loop. In Figure 5, the small signal model of the error amplifier with the
internal compensation network is shown.
10/29
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ST1S32
Functional description
Figure 5.
Small signal model for the error amplifier
V FB
Ro
Vd
Gm*Vd
Co
Rc
Cc
Cp
Cc
VREF
AM11419v1
RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect
system stability and can be neglected.
So, GEA(s) results:
Equation 8
G EA0 ⋅ ( 1 + s ⋅ R c ⋅ C c )
G EA ( s ) = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2
s ⋅ R 0 ⋅ ( C 0 + C p ) ⋅ R c ⋅ C c + s ⋅ ( R0 ⋅ C c + R 0 ⋅ ( C0 + C p ) + R c ⋅ C c ) + 1
where GEA= Gm · Ro
The poles of this transfer function are (if Cc >> C0+CP):
Equation 9
1
f P LF = -----------------------------------------2 ⋅ π ⋅ R0 ⋅ Cc
Equation 10
1
fP HF = -----------------------------------------------------------2 ⋅ π ⋅ Rc ⋅ ( C0 + Cp )
whereas the zero is defined as:
Equation 11
1
fZ = ----------------------------------------2 ⋅ π ⋅ Rc ⋅ Cc
The embedded compensation network is RC=80 kΩ, CC=55 pF while CP and CO can be
considered as negligible. The error amplifier output resistance is 212 MΩ, so the relevant
singularities are:
Doc ID 023246 Rev 1
11/29
Functional description
ST1S32
Equation 12
fZ = 36, 2 kHz
f P LF = 30 Hz
So, closing the loop, the loop gain GLOOP(s) is:
Equation 13
G LOOP ( s ) = G CO ( s ) ⋅ G DIV ( s ) ⋅ G EA ( s )
Example:
VIN=5 V, VOUT=1.2 V, Iomax=4 A, L=1.0 uH, Cout=47 uF (MLCC), R1=10 kΩ, R2=20
kΩ (see Section 5.2 and Section 5.3 for inductor and output capacitor selection
guidelines).
The module and phase Bode plot are reported in Figure 6.
The bandwidth is 117 kHz and the phase margin is 63 degrees.
Figure 6.
Module Bode plot
120
102
84
Module [dB]
66
48
30
12
6
24
42
60
0.1
12/29
1
10
100
3
4
1 .10
1 .10
Frequency [Hz]
Doc ID 023246 Rev 1
5
1 .10
6
1 .10
7
1 .10
AM11420v1
ST1S32
Functional description
Figure 7.
Phase Bode plot
10
17.5
45
Phase
72.5
100
127.5
155
182.5
210
0.1
1
10
100
3
4
1 .10
1 .10
Frequency [Hz]
5
1 .10
6
1 .10
7
1 .10
AM11421v1
4.3
Overcurrent protection
The ST1S32 implements overcurrent protection sensing the current flowing through the
high-side current switch.
If the current exceeds the overcurrent threshold, the high-side is turned off, implementing a
cycle-by-cycle current limitation. Since the regulation loop is no longer fixing the duty cycle,
the output voltage is unregulated and the FB pin falls accordingly to the new duty cycle.
If the FB pin falls below 0.2 V, the peak current limit is reduced to around 2.3 A and the
switching frequency is reduced to assure that the inductor current is properly limited below
the above mentioned value and above 1.2 A. This strategy is called “current foldback”.
The mechanism to adjust the switching undercurrent foldback condition exploits the low-side
current sense circuitry. If FB is lower than 0.2 V, the high-side Power MOSFET is turned off
when the current reaches the current foldback threshold (2.3 A), then, after a proper dead
time that avoids the cross conduction, the low-side is turned on until the low-side current is
lower than a valley threshold (1.2 A). Once the low-side is turned off, the high-side is
immediately turned on. In this way the frequency is adjusted to keep the inductor current
ripple between the current foldback value (2.3 A) and valley threshold (1.2 A), therefore
properly limiting the output current in case of overcurrent or short-circuit.
It should be noted that in some cases, mainly with very low output voltages, the hard
overcurrent can make the FB find the new equilibrium just over the current foldback
threshold (0.2 V). In this case no frequency reduction is enabled, then the inductor current
may diverge. That is, the ripple current during the minimum ON-time is higher than the ripple
current during the OFF-time (the switching period minus the minimum ON-time), so pulseby-pulse the average current is rising, exceeding the current limit.
In order to avoid too high current, a further protection is activated when the high-side current
exceeds a further current threshold (OCP2) slightly over the current limit (OCP1). If the
current triggers the second threshold, the converter stops switching, the reference of the
error amplifier is pulled down and then it restarts with a soft-start procedure. If the
overcurrent condition is still active, the current foldback with frequency reduction properly
limits the output current to 2.3 A.
Doc ID 023246 Rev 1
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Functional description
4.4
ST1S32
Enable function
The enable feature allows the device to be put into standby mode. With the EN pin lower
than 0.4 V, the device is disabled and the power consumption is reduced to less than 10 uA.
With the EN pin higher than 1.2 V, the device is enabled. If the EN pin is left floating, an
internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the
device is disabled. The pin is also VIN compatible.
4.5
Light load operation
With peak current mode control loop the output of the error amplifier is proportional to the
load current. In the ST1S32, to increase light load efficiency, when the output of the error
amplifier falls below a certain threshold, the high-side turn-on is prevented.
This mechanism reduces the switching frequency at light load in order to save the switching
losses.
4.6
Hysteretic thermal shutdown
The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150 oC. Once the junction temperature goes back to about 130 oC,
the device restarts in normal operation.
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ST1S32
Application information
5
Application information
5.1
Input capacitor selection
The capacitor connected to the input must be capable of supporting the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.
So the input capacitor must have an RMS current rating higher than the maximum RMS
input current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 14
I RMS = IO ⋅
2
2
⋅ D + -----D----------------D–2
2
η
η
where Io is the maximum DC output current, D is the duty cycle, and η is the efficiency.
Considering η=1, this function has a maximum at D=0.5 and is equal to Io/2.
The peak-to-peak voltage across the input capacitor can be calculated as:
Equation 15
IO
V PP = ---------------------------- ⋅
C IN ⋅ FSW
D
⎛1 – D
----⎞⎠ ⋅ D + ---- ⋅ ( 1 – D ) + ESR ⋅ I O
⎝
η
η
where ESR is the equivalent series resistance of the capacitor.
Given the physical dimension, ceramic capacitors can well meet the requirements of the
input filter sustaining a higher input RMS current than electrolytic / tantalum types. In this
case, the equation of CIN as a function of the target peak-to-peak voltage ripple (VPP) can
be written as follows:
Equation 16
IO
CIN = ----------------------------- ⋅
V PP ⋅ FSW
D
⎛1 – D
----⎞ ⋅ D + ---- ⋅ ( 1 – D )
⎝
η
η⎠
neglecting the small ESR of ceramic capacitors.
Considering η=1, this function has its maximum in D=0.5, therefore, given the maximum
peak-to-peak input voltage (VPP_MAX), the minimum input capacitor (CIN_MIN) value is:
Equation 17
IO
C IN_MIN = ---------------------------------------------------2 ⋅ V PP_MAX ⋅ FSW
Doc ID 023246 Rev 1
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Application information
ST1S32
Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage ripple in the order
of 1% of VINMAX.
The placement of the input capacitor is very important in order to avoid noise injection and
voltage spikes on the input voltage pin. So the CIN must be placed as close as possible to
the VIN_SW pin.
In Table 6 some multi-layer ceramic capacitors suitable for this device are reported.
Table 6.
Input MLCC capacitors
Manufacturer
Series
Cap value (µF)
Rated voltage (V)
Murata
GRM21
10
10
C3225
10
25
C3216
10
16
LMK212
22
10
TDK
Taiyo Yuden
A ceramic bypass capacitor, as close as possible to the VINA pin, so that additional parasitic
ESR and ESL are minimized, is suggested in order to prevent instability on the output
voltage due to noise. The value of the bypass capacitor can go from 330 nF to 1µF.
5.2
Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value in order to have the expected current ripple must be selected.
The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current.
In continuous current mode (CCM), the inductance value can be calculated by the following
equation:
Equation 18
VIN – V OUT
V OUT
ΔI L = ------------------------------ ⋅ T ON = -------------- ⋅ T OFF
L
L
where TON is the conduction time of the high-side switch and TOFF is the conduction time of
the low-side switch (in CCM, FSW=1/(TON + TOFF)). The maximum current ripple, given the
VOUT, is obtained at maximum TOFF, that is at minimum duty cycle (see previous section to
calculate minimum duty). So by fixing ΔIL=20% to 30% of the maximum output current, the
minimum inductance value can be calculated as:
Equation 19
V OUT 1 – DMIN
L MIN = ---------------- ⋅ ----------------------ΔI MAX FSWMIN
where FSWMIN is the minimum switching frequency, according to Table 4.
16/29
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ST1S32
Application information
The slope compensation, to prevent the sub-harmonic instability in peak current control
loop, is internally managed and so fixed. This implies a further lower limit for the inductor
value. To assure the sub-harmonic stability:
Equation 20
L > V out ⁄ ( 2 • V pp • f sw )
where Vpp is the peak-to-peak value of the slope compensation ramp.
The inductor value selected, based on Equation 19, must satisfy Equation 20.
The peak current through the inductor is given by:
Equation 21
I L,
PK
ΔI
= I O + -------L2
So if the inductor value decreases, the peak current (that must be lower than the current
limit of the device) increases. The higher the inductor value, the higher the average output
current that can be delivered, without reaching the current limit.
In Table 7 some inductor part numbers are listed.
Table 7.
Inductors
Manufacturer
Coilcraft
Series
Inductor value (µH)
Saturation current (A)
XAL50xx
1.2 to 3.3
6.3 to 9
XAL60xx
2.2 to 5.6
7.4 to 11
MSS1048
1.0 to 3.8
6.5 to 11
WE-HCI 7030
1.5 to 4.7
7 to 14
WE-PD type L
1.5 to 3.5
6.4 to 10
DR73
1.0 to 2.2
5.5 to 7.9
DR74
1.5 to 3.3
5.4 to 8.35
Wurth
Coiltronics
5.3
Output capacitor selection
The current in the output capacitor has a triangular waveform which generates a voltage
ripple across it. This ripple is due to the capacitive component (charge or discharge of the
output capacitor) and the resistive component (due to the voltage drop across its ESR). So
the output capacitor must be selected in order to have a voltage ripple compliant with the
application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.
Doc ID 023246 Rev 1
17/29
Application information
ST1S32
Equation 22
ΔI MAX
ΔV OUT = ESR ⋅ ΔI MAX + -----------------------------------------8 ⋅ C OUT ⋅ f SW
For the ceramic (MLCC) capacitor the capacitive component of the ripple dominates the
resistive one. While for the electrolythic capacitor the opposite is true.
As the compensation network is internal, the output capacitor should be selected in order to
have a proper phase margin and then a stable control loop.
The equations of Section 4.2 help to check loop stability, given the application conditions,
the value of the inductor and the output capacitor.
In Table 8 some capacitor series are listed.
Table 8.
Output capacitors
Manufacturer
Series
Cap value (μF)
Rated voltage (V)
ESR (mΩ)
GRM32
22 to 100
6.3 to 25
