ST25R3911B-AQFT

ST25R3911B Datasheet High performance HF reader / NFC initiator with 1.4 W supporting VHBR and AAT Features • • • QFN32/VFQFPN32 (5 × 5 mm) Wafer • • • • • • • • • • • • • • Product status link ST25R3911B ISO 18092 (NFCIP-1) Active P2P ISO14443A, ISO14443B, ISO15693 and FeliCa™ Supports VHBR (3.4 Mbit/s PICC to PCD framing, 6.8 Mbit/s AFE and PCD to PICC framing) Capacitive sensing - Wake-up Automatic antenna tuning system providing tuning of antenna LC tank Automatic modulation index adjustment AM and PM demodulator channels with automatic selection DPO (Dynamic power output) Up to 1.4 W in case of differential output User selectable and automatic gain control Transparent and stream modes to implement MIFARE™ classic compliant or other custom protocols Possibility of driving two antennas in single ended mode Oscillator input capable of operating with 13.56 MHz or 27.12 MHz crystal with fast start-up 6 Mbit/s SPI with 96 bytes FIFO Wide supply voltage range from 2.4 V to 5.5 V Wide temperature range: -40 °C to 125 °C QFN32, 5x5 mm package with wetable flank or wafer delivery Description The ST25R3911B is a highly integrated NFC Initiator / HF reader IC, including the analog front end (AFE) and a highly integrated data framing system for ISO 18092 (NFCIP-1) initiator, ISO 18092 (NFCIP-1) active target, ISO 14443A and B reader (including high bit rates), ISO 15693 reader and FeliCa™ reader. Implementation of other standard and custom protocols like MIFARE™ Classic is possible using the AFE and implementing framing in the external microcontroller (Stream and Transparent modes). The ST25R3911B is positioned perfectly for the infrastructure side of the NFC system, where users need optimal RF performance and flexibility combined with low power. Thanks to automatic antenna tuning (AAT) technology, the device is optimized for applications with directly driven antennas. The ST25R3911B is alone in the domain of HF reader ICs as it contains two differential low impedance (1 Ohm) antenna drivers. The ST25R3911B includes several features that make it very suited for low power applications. It contains a low power capacitive sensor that can be used to detect the presence of a card without switching on the reader field. The presence of a card can also be detected by performing a measurement of amplitude or phase of signal on antenna LC tank, and comparing it to the stored reference. It also contains a low power RC oscillator and wake-up timer that can be used to wake up the system after a defined time period, and to check for the presence of a tag using one or more low power detection techniques (capacitive, phase or amplitude). The ST25R3911B is designed to operate from a wide (2.4 V to 5.5 V) power supply range; peripheral interface IO pins support power supply range from 1.65 V to 5.5 V. DS11793 - Rev 7 - April 2022 For further information contact your local STMicroelectronics sales office. www.st.com ST25R3911B Functional overview 1 Functional overview The ST25R3911B is suitable for a wide range of applications, among them • E-government • Access control • • • 1.1 Payment, EMVCo® 2.6b NFC infrastructure Ticketing Block diagram The block diagram is shown in Figure 1. Figure 1. ST25R3911B block diagram VDD_IO XTO XTI XTAL oscillator VDD Regulators POR and Bias Logic Transmitter FIFO SPI IRQ MCU_CLK Level shifters Control logic A/D converter RFO1 RFO2 Phase and amplitude detector SPI Receiver TRIMx RFI1 RFI2 Framing RC oscillator ST25R3911B DS11793 - Rev 7 Wake-Up timer External field detector Capacitive sensor CSI CSO page 2/116 ST25R3911B Block diagram 1.1.1 Transmitter The transmitter incorporates drivers that drive external antenna through pins RFO1 and RFO2. Single sided and differential driving is possible. The transmitter block additionally contains a sub-block that modulates transmitted signal (OOK or configurable AM modulation). The ST25R3911B transmitter is intended to directly drive antennas (without 50 Ω cable, usually antenna is on the same PCB). Operation with 50 Ω cable is also possible, but in that case some of the advanced features are not available. 1.1.2 Receiver The receiver detects transponder modulation superimposed on the 13.56 MHz carrier signal. The receiver contains two receive chains (one for AM and another for PM demodulation) composed of a peak detector followed by two gain and filtering stages and a final digitizer stage. The filter characteristics are adjusted to optimize performance for each mode and bit rate (sub-carrier frequencies from 212 kHz to 6.8 MHz are supported). The receiver chain inputs are the RFI1 and RFI2 pins. The receiver chain incorporates several features that enable reliable operation in challenging phase and noise conditions. 1.1.3 Phase and amplitude detector The phase detector monitors the phase difference between the transmitter output signals (RFO1 and RFO2) and the receiver input signals (RFI1 and RFI2). The amplitude detector is observing the amplitude of the receiver input signals (RFI1 and RFI2) through self-mixing. The amplitude of the receiver input signals (RFI1 and RFI2) is directly proportional to the amplitude of the antenna LC tank signal. The phase detector and the amplitude detector can be used for the following purposes: • PM demodulation, by observing RFI1 and RFI2 phase variation • Average phase difference between RFOx pins and RFIx pins is used to check and optimize antenna tuning • Amplitude of signal present on RFI1 and RFI2 pins is used to check and optimize antenna tuning 1.1.4 A/D converter The ST25R3911B contains a built-in analog to digital (A/D) converter. Its input can be multiplexed from different sources, and it is used in several applications (such as measurement of RF amplitude and phase, calibration of modulation depth). The result of the A/D conversion is stored in the A/D converter Output register and can be read via SPI. 1.1.5 Capacitive sensor The capacitive sensor is used to implement low power detection of transponder presence, it measures the capacitance between two copper patches connected to the CSI and CSO pins. The capacitance changes with the presence of an object (card, hand). During calibration the reference capacitance (representing parasitic capacitance of the environment) is stored. In normal operation the capacitance is periodically measured and compared to the stored reference value, if the measured capacitance differs from the stored reference value by more than a register defined threshold, then an interrupt is sent to the external controller. 1.1.6 External field detector The External field detector is a low power block used in NFC mode to detect the presence of an external RF field. It supports two different detection thresholds, Peer Detection Threshold and Collision Avoidance Threshold. The Peer Detection Threshold is used in the NFCIP-1 target mode to detect the presence of an initiator field, and is also used in active communication initiator mode to detect the activation of the target field. The Collision Avoidance Threshold is used to detect the presence of an RF field during the NFCIP-1 RF Collision Avoidance procedure. 1.1.7 Quartz crystal oscillator The quartz crystal oscillator can operate with 13.56 MHz and 27.12 MHz crystals. At start-up the transconductance of the oscillator is increased to achieve a fast start-up. The start-up time varies with crystal type, temperature and other parameters, hence the oscillator amplitude is observed and an interrupt is sent when stable oscillator operation is reached. The use of a 27.12 MHz crystal is mandatory for VHBR operation. The oscillator block also provides a clock signal to the external microcontroller (MCU_CLK), according to the settings in the IO configuration register 1. DS11793 - Rev 7 page 3/116 ST25R3911B Block diagram 1.1.8 Power supply regulators Integrated power supply regulators ensure a high power supply rejection ratio for the complete reader system. If the reader system PSRR has to be improved, the command Adjust regulators is sent. As a result of this command, the power supply level of VDD is measured in maximum load conditions and the regulated voltage reference is set 250 mV below this measured level to assure a stable regulated supply. The resulting regulated voltage is stored in the Regulator and timer display register. It is also possible to define regulated voltage by writing to the Regulator voltage control register. To decouple any noise sources from different parts of the IC there are three regulators integrated with separated external blocking capacitors (the regulated voltage of all of them is the same in 3.3 V supply mode). One regulator is for the analog blocks, one for the digital blocks, and one for the antenna drivers. This block additionally generates a reference voltage for the analog processing (AGD - analog ground). This voltage also has an associated external buffer capacitor. 1.1.9 POR and Bias This block provides the bias current and the reference voltages to all other blocks. It also incorporates a Power on Reset (POR) circuit that provides a reset at power-up and at low supply voltage levels. 1.1.10 RC oscillator and Wake-Up timer The ST25R3911B includes several possibilities of low power detection of card presence (capacitive sensor, phase measurement, amplitude measurement). The RC oscillator and the register configurable Wake-Up timer are used to schedule the periodic card presence detection. 1.1.11 ISO-14443 and NFCIP-1 framing This block performs framing for receive and transmit according to the selected ISO mode and bit rate settings. In reception it takes the demodulated sub-carrier signal from the receiver. It recognizes the SOF, EOF and data bits, performs parity and CRC check, organizes the received data in bytes and places them in the FIFO. During transmit, it operates inversely, it takes bytes from the FIFO, generates parity and CRC bits, adds SOF and EOF and performs final encoding before passing the modulation signal to the transmitter. In Transparent mode, the framing and FIFO are bypassed, the digitized sub-carrier signal (the receiver output), is directly sent to the MISO pin, and the signal applied to the MOSI pin is directly used to modulate the transmitter. 1.1.12 FIFO The ST25R3911B contains a 96-byte FIFO. Depending on the mode, it contains either data that has been received or data to be transmitted. 1.1.13 Control logic The control logic contains I/O registers that define operation of device. 1.1.14 SPI A 4-wire Serial Peripheral Interface (SPI) is used for communication between the external microcontroller and the ST25R3911B. DS11793 - Rev 7 page 4/116 ST25R3911B Application information 1.2 Application information The minimum configurations required to operate the ST25R3911B are shown in Figure 2 and Figure 3. Figure 2. Minimum configuration with single sided antenna driving (including EMC filter) 1.65 to 5.5 V 2.4 to 5.5 V VDD_IO VDD /SS MISO MOSI SCLK IRQ MCU_CLK MCU AGD VSS VSP_A VSN_A VSP_D XTI VSN_D XTO VSP_RF TRIM1_x / NC VSN_RF TRIM2_x / NC Antenna coil RF01 RF02 RFI1 RFI2 ST25R3911B MS70723V1 Figure 3. Minimum configuration with differential antenna driving (including EMC filter) 1.65 to 5.5 V 2.4 to 5.5 V VDD_IO MCU VDD /SS MISO MOSI SCLK IRQ MCU_CLK XTI AGD VSS VSP_A VSN_A VSP_D VSN_D XTO VSP_RF TRIM1_x VSN_RF TRIM2_x CSO CSI Antenna coil RF01 RF02 RFI1 RFI2 ST25R3911B MS42416V1 DS11793 - Rev 7 page 5/116 ST25R3911B Application information 1.2.1 Operating modes The ST25R3911B operating mode is defined by the contents of the Operation control register. At power-up all bits of the Operation control register are set to 0, the ST25R3911B is in power-down mode. In this mode AFE static power consumption is minimized, only the POR and part of the bias are active, while the regulators are transparent and are not operating. The SPI is still functional in this mode so all settings of ISO mode definition and configuration registers can be done. Control bit en (bit 7 of the Operation control register) is controlling the quartz crystal oscillator and regulators. When this bit is set, the device enters in ready mode. In this mode, the quartz crystal oscillator and regulators are enabled. An interrupt is sent to inform the microcontroller when the oscillator frequency is stable. Enable of receiver and transmitter are separated so it is possible to operate one without switching on the other (control bits rx_en and tx_en). In some cases this may be useful, if the reader field is maintained and there is no transponder response expected, the receiver can be switched-off to save current. Another example is the NFCIP-1 active communication receive mode in which the RF field is generated by the initiator and only the receiver operates. Asserting the Operation control register bit wu while the other bits are set to 0 puts the ST25R3911B into the wake-up mode that is used to perform low-power detection of card presence. In this mode, the low-power RC oscillator and register configurable wake-up timer are used to schedule periodic measurement(s). When a difference in the measured value from the predefined reference is detected, an interrupt is sent to wake up the microcontroller. 1.2.2 Transmitter The transmitter contains two identical push-pull driver blocks connected to the pins RFO1 and RFO2. These drivers are differentially driving the external antenna LC tank. It is also possible to operate only one of the two drivers by setting the IO configuration register 1 bit single to 1. Each driver is composed of eight segments having binary weighted output resistance. The MSB segment typical ON resistance is 2 Ω, when all segments are turned on; the output resistance is typically 1 Ω. All segments are turned on to define the normal transmission (non-modulated) level. It is also possible to switch off certain segments when driving the non-modulated level to reduce the amplitude of the signal on the antenna and/or to reduce the antenna Q factor without making any hardware changes. The RFO normal level definition register defines which segments are turned on to define the normal transmission (non-modulated) level. Default setting is that all segments are turned on. Using the single driver mode the number of the antenna LC tank components (and therefore the cost) is halved, but also the output power is reduced. In single mode it is possible to connect two antenna LC tanks to the two RFO outputs and multiplex between them by controlling the IO configuration register 1 bit rfo2. In order to transmit the data the transmitter output level needs to be modulated. Both AM and OOK modulation are supported. The type of modulation is defined by setting the bit tr_am in the Auxiliary definition register. During the OOK modulation (for example ISO14443A) the transmitter drivers stop driving the carrier frequency. As consequence the amplitude of the antenna LC tank oscillation decays, the time constant of the decay is defined with the LC tank Q factor. The decay time in case of OOK modulation can be shortened by asserting the Auxiliary definition register bit ook_hr. When this bit is set to logic one the drivers are put in tristate during the OOK modulation. AM modulation (for example ISO14443B) is done by increasing the output driver impedance during the modulation time. This is done by reducing the number of driver segments that are turned on. The AM modulated level can be automatically adjusted to the target modulation depth by defining the target modulation depth in the AM modulation depth: definition and calibration and sending the Calibrate modulation depth direct command. Refer to Section 1.2.20 AM modulation depth: definition and calibration for further details. Slow transmitter ramping When the transmitter is enabled it starts to drive the antenna LC tank with full power, the ramping of the field emitted by antenna is defined by antenna LC tank Q factor. However there are some reader systems where the reader field has to ramp up with a longer transition time when it is enabled. The STIF (Syndicat des transports d'Ile de France) specification requires a transition time from 10% to 90% of field longer than or equal to 10 μs. The ST25R3911B supports that feature. It is realized by collapsing VSP_RF regulated voltage when transmitter is disabled and ramping it when transmitter is enabled. Typical transition time is 15 μs at 3 V supply and 20 μs at 5 V supply. Procedure to implement the slow transition: 1. When transmitter is disabled set IO configuration register 2 bit slow_up to 1. Keep this state for at least 2 ms to allow discharge of VSP_RF. DS11793 - Rev 7 page 6/116 ST25R3911B Application information 2. 3. 1.2.3 Enable transmitter, its output will ramp slowly. Before sending any command set the bit slow_up back to 0. Receiver The receiver performs demodulation of the transponder subcarrier modulation that is superimposed on the 13.56 MHz carrier frequency. It performs AM and/or PM demodulation, amplification, band-pass filtering and digitalization of subcarrier signals. Additionally, it performs RSSI measurement, automatic gain control (AGC) and squelch. In typical applications the receiver inputs RFI1 and RFI2 are outputs of capacitor dividers connected directly to the terminals of the antenna coil. This concept ensures that the two input signals are in phase with the voltage on the antenna coil. The design of the capacitive divider must ensure that the RFI1 and RFI2 input signal peak values do not exceed the VSP_A supply voltage level. The receiver comprises two complete receive channels, one for the AM demodulation and another one for the PM demodulation. In case both channels are active the selection of the channel used for reception framing is done automatically by the receive framing logic. The receiver is switched on when Operation control register bit rx_en is set to 1. Additionally, the Operation control register contains bits rx_chn and rx_man; rx_chn defines whether both, AM and PM, demodulation channels is active or only one of them, while bit rx_man defines the channel selection mode in case both channels are active (automatic or manual). Operation of the receiver is controlled by four receiver configuration registers. The operation of the receiver is additionally controlled by the signal rx_on that is set high when a modulated signal is expected on the receiver input. This signal is used to control RSSI and AGC and also enables processing of the receiver output by the framing logic. Signal rx_on is automatically set to high after the Mask receive timer expires. Signal rx_on can also be directly controlled by the controller by sending direct commands Mask receive data and Unmask receive data. Figure 4 details the receiver block diagram. Figure 4. Receiver block diagram AM Demodulator Mixer rec1 rec2 rec4 rec3 RF_IN1 AGC Squelch RSSI M U X RSSI_AM Peak detector Digital sub-carrier RX_on sg_on RF_IN2 rec3 rec4 AGC Squelch RSSI PM Demodulator Mixer RSSI_PM Digital sub-carrier rec3 Demodulation stage AC coupling + 1st gain stage rec1 Low-pass High-pass + 2nd gain stage + 3rd gain stage Digitizing stage Demodulation stage The first stage performs demodulation of the transponder subcarrier signal, superimposed on the HF field carrier. Two different blocks are implemented for AM demodulation: • Peak detector • AM demodulator mixer. The choice of the used demodulator is made by the Receiver configuration register 1 bit amd_sel. DS11793 - Rev 7 page 7/116 ST25R3911B Application information The peak detector performs AM demodulation using a peak follower. Both the positive and negative peaks are tracked to suppress any common mode signal. The peak detector is limited in speed; it can operate for subcarrier frequencies up to fc/8 (1700 kHz). Its demodulation gain is G = 0.7. Its input is taken from one demodulator input only (usually RFI1). The AM demodulator mixer uses synchronous rectification of both receiver inputs (RFI1 and RFI2). Its gain is G = 0.55. The mixer demodulator is optimized for VHBR subcarrier frequencies (fc/8 and higher). For subcarrier frequency fc/8 (1700 kHz) both peak follower and mixer demodulator can be used, while for fc/4 and fc/2 only the mixer demodulator can be used. PM demodulation is also done by a mixer. The PM demodulator mixer has differential outputs with 60 mV differential signal for 1% phase change (16.67 mV / °). Its operation is optimized for subcarrier frequencies up to fc/8 (1700 kHz). In case the demodulation is done externally, it is possible to multiplex the LF signals applied to pins RFI1 and RFI2 directly to the gain and filtering stage by selecting the Receiver configuration register 2 bit lf_en. Filtering and gain stages The receiver chain has band pass filtering characteristics. Filtering is optimized to pass subcarrier frequencies while rejecting carrier frequency and low frequency noise and DC component. Filtering and gain is implemented in three stages, where the first and the last stage have first order high pass characteristics, and the second stage has second order low-pass characteristic. Gain and filtering characteristics can be optimized by writing the Receiver configuration register 1 (filtering), the Receiver configuration register 3 (gain in first stage) and the Receiver configuration register 4 (gain in second and third stage). The gain of the first stage is about 20 dB and can be reduced in six 2.5 dB steps. There is also a special boost mode available, which boosts the maximum gain by additional 5.5 dB. In case of VHBR (fc/8 and fc/4) the gain is lower. The first stage gain can only be modified by writing Receiver configuration register 3. The default setting of this register is the minimum gain. The default first stage zero is set at 60 kHz, it can also be lowered to 40 kHz or to 12 kHz by writing option bits in the Receiver configuration register 1. The control of the first and third stage zeros is done with common control bits (see Table 1). Table 1. First and third stage zero setting rec1 h200 rec1 h80 rec1 z12k First stage zero Third stage zero 0 0 0 60 kHz 400 kHz 1 0 0 60 kHz 200 kHz 0 1 0 40 kHz 80 kHz 0 0 1 12 kHz 200 kHz 0 1 1 12 kHz 80 kHz 1 0 1 12 kHz 200 kHz Others Not used The gain in the second and third stage is 23 dB and can be reduced in six 3 dB steps. The gain of these two stages is included in the AGC and Squelch loops. It can also be manually set in Receiver configuration register 4. Sending of direct command Reset Rx Gain must be sent to reset the AGC, Squelch and RSSI block. Sending this command clears the current Squelch setting and loads the gain reduction configuration from Receiver configuration register 4 into the internal shadow registers of the AGC and Squelch block. The second stage has a second order low-pass filtering characteristic, the pass band is adjusted according to the subcarrier frequency using the bits lp2 to lp0 of the Receiver configuration register 1. See Table 2 for -1 dB cut-off frequency for different settings. DS11793 - Rev 7 page 8/116 ST25R3911B Application information Table 2. Low pass control rec1 lp2 rec1 lp1 rec1 lp0 -1 dB point 0 0 0 1200 kHz 0 0 1 600 kHz 0 1 0 300 kHz 1 0 0 2 MHz 1 0 1 7 MHz Others Not used Table 3 provides information on the recommended filter settings. For all supported operation modes and receive bit rates there is an automatic preset defined, additionally some alternatives are listed. Automatic preset is done by sending direct command Analog preset. There is no automatic preset for Stream and Transparent modes. Since the selection of the filter characteristics also modifies gain, the gain range for different filter settings is also listed. Table 3. Receiver filter selection and gain range Gain (dB) rec1lp rec1h200 rec1h80 rec1z12k Max all Min1 Max1 Max23 Min23 Min all With boost Comments 000 0 0 0 43.4 28.0 26.4 11.0 49.8 Automatic preset for ISO14443A fc/128 and NFC Forum Type 1 Tag 000 1 0 0 44.0 29.0 27.5 12.0 49.7 Automatic preset for ISO14443B fc/128 ISO14443 fc/64 001 1 0 0 44.3 29 27.0 11.7 49.8 Recommended for 424/484 kHz subcarrier 000 0 1 0 41.1 25.8 23.6 8.3 46.8 Alternative choice for ISO14443 fc/32 and fc/16 100 0 1 0 32.0 17.0 17.2 2.0 37.6 Automatic preset for ISO14443 fc/32 and fc/16 Alternative choice for fc/8 (1.7 kb/s) 100 0 0 0 32.0 17.0 17.2 2.0 37.6 Alternative choice for fc/8 (1.7 kb/s) Automatic preset FeliCa™ (fc/64, fc/32) 000 0 1 1 41.1 25.8 23.6 8.3 46.8 101 0 1 0 30.0 20.0 12.0 2.0 34.0 Alternative choice for fc/8 and fc/4 101 1 0 0 30.0 20.0 12.0 2.0 34.0 Automatic preset for fc/8 and fc/4 000 1 0 1 36.5 21.5 24.9 9.9 41.5 Automatic preset for NFCIP-1 (initiator and target) Alternative choice for ISO14443 fc/32 and fc/16 Digitizing stage The digitizing stage produces a digital representation of the subcarrier signal coming from the receiver. This digital signal is then processed by the receiver framing logic. The digitizing stage consists of a window comparator with adjustable digitizing window (five possible settings, 3 dB steps, adjustment range from ±33 mV to ±120 mV). Adjustment of the digitizing window is included in the AGC and Squelch loops. In addition, the digitizing window can also be set manually in the Receiver configuration register 4. DS11793 - Rev 7 page 9/116 ST25R3911B Application information AGC, Squelch and RSSI As mentioned above, the second and third gain stage gain and the digitizing stage window are included in the AGC and Squelch loops. Eleven settings are available. The default state features minimum digitizer window and maximum gain. The first four steps increase the digitizer window in 3 dB steps, the next six steps additionally reduce the gain in the second and third gain stage, again in 3 dB steps. The initial setting with whom Squelch and AGC start is defined in Receiver configuration register 4. The Gain reduction state register displays the actual state of gain that results from Squelch, AGC and initial settings in Receiver configuration register 4. During bit anticollision like Type A, the AGC should be disabled. Squelch This feature is designed for operation of the receiver in noisy conditions. The noise can come from tags (caused by the processing of reader commands), or it can come from a noisy environment. This noise may be misinterpreted as start of transponder response, resulting in decoding errors. During execution of the Squelch procedure the output of the digitizing comparator is observed. In case there are more than two transitions on this output in a 50 μs time period, the receiver gain is reduced by 3 dB, and the output is observed during the next 50 μs. This procedure is repeated until the number of transitions in 50 μs is lower or equal to two, or until the maximum gain reduction is reached. This gain reduction can be cleared sending the direct command Reset Rx gain. There are two possibilities of performing squelch: automatic mode and using the direct command Squelch. 1. Automatic mode is enabled in case bit sqm_dyn in the Receiver configuration register 2 is set. It is activated automatically 18.88 μs after end of Tx and is terminated when the Mask receive timer expires. This mode is primarily intended to suppress noise generated by tag processing during the time when a tag response is not expected (covered by Mask receive timer). 2. Command Squelch is accepted in case it is sent when signal rx_on is low. It can be used when the time window in which noise is present is known by the controller. AGC AGC (Automatic gain control) is used to reduce gain to keep the receiver chain out of saturation. With gain properly adjusted the demodulation process is also less influenced by system noise. AGC action starts when signal rx_on is asserted high and is reset when it is reset to low. At the high to low transitions of the rx_on signal the state of the receiver gain is stored in the Gain reduction state register. Reading this register at a later stage gives information on the gain setting used during last reception. When AGC is switched on the receiver gain is reduced so that the input to the digitizer stage is not saturated. The AGC system comprises a comparator with a window 3.5 times larger than that of the digitizing window comparator. When the AGC function is enabled the gain is reduced until there are no transitions on the output of its window comparator. This procedure ensures that the input to the digitizing window comparator is less than 3.5 times larger than its threshold. AGC operation is controlled by the control bits agc_en, agc_m and agc_fast in the Receiver configuration register 2. Bit agc_en enables the AGC operation, bit agc_m defines the AGC mode, and bit agc_alg defines the AGC algorithm. Two AGC modes are available. The AGC can operate during the complete Rx process (as long as signal rx_on is high), or it can be enabled only during the first eight subcarrier pulses. Two AGC algorithms are available. The AGC can either start by presetting code 4h (max digitizer window, max gain) or by resetting the code to 0h (min digitizer window, max gain). The algorithm with preset code is faster, therefore it is recommended for protocols with short SOF (like ISO14443A fc/128). Default AGC settings are: • AGC is enabled • AGC operates during complete Rx process • algorithm with preset is used. DS11793 - Rev 7 page 10/116 ST25R3911B Application information RSSI The receiver also performs the RSSI (Received Signal Strength Indicator) measurement for both channels. The RSSI measurement is started after the rising edge of rx_on. It stays active as long as signal rx_on is high, it is frozen while rx_on is low. The RSSI is a peak hold system, and the value can only increase from the initial zero value. Every time the AGC reduces the gain the RSSI measurement is reset and starts from zero. Result of RSSI measurements is a 4-bit value that can be observed by reading the RSSI display register. The LSB step is 2.8 dB, and the maximum code is Dh (13d). Since the RSSI measurement is of peak hold type the RSSI measurement result does not follow any variations in the signal strength (the highest value is kept). In order to follow RSSI variations it is possible to reset the RSSI bits and restart the measurement by sending the direct command Clear RSSI. Receiver in NFCIP-1 active communication mode There are several features built into the receiver to enable reliable reception of active. NFCIP-1 communication. All these settings are automatically preset by sending the direct command Analog preset after the NFCIP-1 mode has been configured. In addition to the filtering options, there are two NFCIP-1 active communication mode specific configuration bits stored in the Receiver configuration register 3. Bit lim enables clipping circuits that are positioned after the first and second gain stages. The function of the clipping circuits is to limit the signal level for the following filtering stage (when the NFCIP-1 peer is close the input signal level can be quite high). Bit rg_nfc forces gain reduction of second and third filtering stage to -6 dB while keeping the digitizer comparator window at maximum level. 1.2.4 Capacitive sensor The Capacitive sensor block (Figure 5) gives the possibility of low power detection of tag presence. The capacitive measurement system comprises two electrodes. One is the excitation electrode emitting an electrical field of a fixed frequency in the range of a few hundred kHz (CSO) and the second one is the sensing electrode (CSI). The amount of charge generated in the sensing electrode represents the capacitance between the two electrodes. The capacitive sensor electrodes are tolerant to parasitic capacitance to ground (up to 25 pF) and to input leakage (up to 1 MΩ). Since the charge on the sensing electrode is generated with the frequency of the excitation electrode, a synchronous rectifier is used to detect it. This ensures good rejection of interference and high tolerance to parasitic capacitances (to all nodes except the excitation electrode). The synchronous rectifier output is a DC voltage linearly proportional to the capacitance between the excitation and sensing electrode. The output DC voltage is converted by the A/D converter in absolute mode. The result is stored in the Section 1.3.33 A/D converter output register (see also Section 1.2.8 A/D converter). Figure 5. Capacitive sensor block diagram Oscillator A/D converter Synchronous rectifier CSO CSI Any conductive object (human hand or tag antenna windings) approaching the two electrodes changes the capacitance between the excitation and sensing electrode as it 'shortens' the distance between the two by providing conductance on the part of the path between the two electrodes. DS11793 - Rev 7 page 11/116 ST25R3911B Application information The capacitance measurement is started by sending the direct command Measure Capacitance. The ST25R3911B can also be configured to automatically wake-up and perform periodic capacitance measurements. The result is compared to a stored reference or to an average of previous measurements and in case the difference is greater than a predefined value an IRQ is triggered to wake-up the controller (see also Section 1.2.5 Wake-up mode). The capacitive sensor gain can be adjusted in Capacitive sensor control register. The default gain is 2.8 V/pF (typical value), the maximum gain is 6.5 V/pF (typical value). Since the LSB of the A/D converter corresponds to approximately 7.8 mV, the default gain results in a sensitivity of 2.8 fF/LSB (1.2 fF/LSB in case of maximum gain). The duration of the capacitance measurement is 200 μs, and the current consumption during the measurement is 1.1 mA (typical value). As an example, if the capacitive measurement is performed every 100 ms in Wake-Up mode, then the resulting average current consumption is 5.8 μA (3.6 μA is the standby consumption in Wake-Up mode). Capacitor sensor calibration The capacitive sensor comprises a calibration unit that internally compensates the parasitic capacitances between CSI and CSO, thus leaving full measurement range for information about capacitance variation. Five bits are used to control the calibration. The minimum calibration step and the available calibration range are, respectively, 0.1 pF and 3.1 pF. The calibration can be done manually by writing to the Capacitive sensor control register or automatically by sending the direct command Calibrate Capacitive Sensor. The status of the Calibrate Capacitive Sensor command and the resulting calibration value are stored in the Capacitive sensor display register. In order to avoid interference of the capacitive sensor with the Xtal oscillator and the reader magnetic field and to assure repetitive results it is strongly recommended to perform capacitance measurement and calibration in Power-down mode only. 1.2.5 Wake-up mode Asserting the Operation control register bit wu while the other bits are set to 0 puts the ST25R3911B in wake-up mode, used to perform low power detection of card presence. The ST25R3911B includes several possibilities of low power detection of a card presence (capacitive sensor, phase measurement, amplitude measurement). An integrated low power 32 kHz RC oscillator and a register configurable wake-up timer are used to schedule periodic detection. Usually the presence of a card is detected by a so-called polling loop. In this process the reader field is periodically turned on and the controller checks whether a card is present using RF commands. This procedure consumes a lot of energy since the reader field has to be turned on for 5 ms before a command can be issued. Low power detection of card presence is performed by detecting a change in the reader environment, produced by a card. When a change is detected, an interrupt is sent to the controller. As a result, the controller can perform a regular polling loop. In the wake-up mode the ST25R3911B periodically performs the configured reader environment measurements and sends an IRQ to the controller when a difference to the configured reference value is detected. Detection of card presence can be done by performing phase,amplitude and capacitive sensor measurements. Presence of a card close to the reader antenna coil produces a change of the antenna LC tank signal phase and amplitude. The reader field activation time needed to perform the phase or the amplitude measurement is extremely short (~20 μs) compared to the activation time needed to send a protocol activation command. Additionally the power level during the measurement can be lower than the power level during normal operation since the card does not have to be powered to produce a coupling effect. The emitted power can be reduced by changing the RFO normal level definition register. The capacitive sensor detects a change of the parasitic capacitance between the two excitation electrodes. This change in capacitance can be caused by a card antenna or a hand holding the card. See Section 1.1.5 Capacitive sensor for a detailed information on the capacitive sensor. The registers on locations from 31h to 3Dh are dedicated to wake-up timer configuration and display. The wake-up Timer Control register is the main Wake-up timer control register. The timeout period between the successive detections and the measurements are selected in this register. Timeouts in the range from 10 to 800 ms are available, 100 ms is the default value. Any combination of available measurements can be selected (one, two or all of them). The next twelve registers (32h to 3Dh) are configuring the three possible detection measurements and storing the results, four registers are used for each measurement. DS11793 - Rev 7 page 12/116 ST25R3911B Application information An IRQ is sent when the difference between a measured value and the reference value is larger than the configured threshold value. There are two possible definitions for the reference value: 1. The ST25R3911B can calculate the reference based on previous measurements (auto-averaging) 2. The controller determines the reference and stores it in a register The first register in the series of four is the Amplitude measurement configuration register. The difference to the reference value that triggers the IRQ, the method of reference value definition and the weight of the last measurement result in case of auto-averaging are defined in this register. The next register is storing the reference value in case the reference is defined by the controller. The following two registers are display registers. The first one stores the auto-averaging reference, and the second one stores the result of the last measurement. The wake-up mode configuration registers have to be configured before the wake-up mode is entered. Any modification of the wake-up mode configuration while it is active may result in unpredictable behavior. Auto-averaging In case of auto-averaging the reference value is recalculated after every measurement as NewAverage = OldAverage + (MeasuredValue - OldAverage) / Weight The calculation is done on 13 bits to have sufficient precision.The auto-averaging process is initialized when the wake-up mode is entered for the first time after initialization (at power-up or after Set default command). The initial value is taken from the measurement display registers (for example Amplitude measurement display register) until the content of this register is not zero. Every Measurement Configuration register contains a bit that defines whether the measurement that causes an interrupt is taken in account for the average value calculation (for example bit am_aam of the Amplitude measurement display register). 1.2.6 Quartz crystal oscillator The quartz crystal oscillator can operate with 13.56 MHz and 27.12 MHz crystals. The operation of quartz crystal oscillator is enabled when the Operation control register bit en is set to one. An interrupt is sent to inform the microcontroller when the oscillator frequency is stable (see Section 1.3.24 Main interrupt register). The status of oscillator can be observed by observing the Auxiliary display register bit osc_ok. This bit is set to ‘1’ when oscillator frequency is stable. The oscillator is based on an inverter stage supplied by a controlled current source. A feedback loop controls the bias current in order to regulate amplitude on XTI pin to 1 Vpp. To enable a fast reader start-up an interrupt is sent when the oscillator amplitude exceeds 750 mVpp. Division by two ensures that 13.56 MHz signal has a duty cycle of 50%, which is better for the transmitter performance (no PW distortion). Use of 27.12 MHz crystal is therefore recommended for better performance. In case of 13.56 MHz crystal, the bias current of stage that is digitizing oscillator signal is increased to assure as low PW distortion as possible. Note: In case of VHBR reception (bit rates fc/8 and above) it is mandatory to use the 27.12 MHz crystal since high frequency clock is needed for receive framing. The oscillator output is also used to drive a clock signal output pin MCU_CLK) that can be used by the external microcontroller. The MCU_CLK pin is configured in the IO configuration register 2. 1.2.7 Timers The ST25R3911B embeds several timers that eliminate the need to run counters in the controller, thus reducing the effort of the controller code implementation, and improve portability of code to different controllers. Every timer has one or more associated configuration registers in which the timeout duration and different operating modes are defined. These configuration registers have to be set while the corresponding timer is not running. Any modification of timer configuration while the timer is active may result in unpredictable behaviour. All timers except the wake-up timer are stopped by direct command clear. Note: If bit nrt_emv in the General purpose and no-response timer control register is set to 1, the no-response timer is not stopped Mask receive timer and no-response timer Mask Receive timer and no-response timer are both automatically started at the end of transmission (at the end of EOF). DS11793 - Rev 7 page 13/116 ST25R3911B Application information Mask receive timer The Mask receive timer is blocking the receiver and reception process in framing logic by keeping the rx_on signal low after the end of Tx during the time the tag reply is not expected. While the Mask receive timer is running, the Squelch is automatically turned on (if enabled). Mask receive timer does not produce an IRQ. The Mask receive timer timeout is configured in the Mask receive timer register. In the NFCIP-1 active communication mode the Mask receive timer is started when the peer NFC device (a device with whom communication is going on) switches on its field. The Mask receive timer has a special use in the low power Initial NFC Target Mode. After the initiator field has been detected the controller turns on the oscillator, regulator and receiver. Mask receive timer is started by sending direct command Start Mask receive timer. After the Mask receive timer expires the receiver output starts to be observed to detect start of the initiator message. In this mode the Mask receive timer clock is additionally divided by eight it (one count is 512/fc) to cover range up to about 9.6 ms. No-response timer As its name indicates, this timer is intended to observe whether a tag response is detected in a configured time started by end of transmission. The I_nre flag in the Timer and NFC interrupt register is signaling interrupt events resulting from this timer timeout. The no-response timer is configured by writing the two registers No-response timer register 1 and No-response timer register 2. Operation options of the no-response timer are defined by setting bits nrt_emv and nrt_step in the General purpose and no-response timer control register. Bit nrt_step configures the time step of the no-response timer. Two steps are available, 64/fc (4.72 μs) to cover range up to 309 ms, and 4096/fc, covering the range up to 19.8 s. Bit nrt_emv controls the timer operation mode: • When this bit is set to 0 (default mode) the IRQ is produced in case the no-response timer expires before a start of a tag reply is detected and rx_on is forced to low to stop receiver process. In the opposite case, when start of a tag reply is detected before timeout, the timer is stopped, and no IRQ is produced. • When this bit is set to 1 the timer unconditionally produces an IRQ when it expires, it is also not stopped by direct command Clear. This means that IRQ is independent of the fact whether or not a tag reply was detected. In case at the moment of timeout a tag reply is being processed no other action is taken, in the opposite case, when no tag response is being processed additionally the signal rx_on is forced to low to stop receive process. The no-response timer can also be started using direct command Start no-response timer. The purpose of this command is to extend the no-response timer timeout beyond the range defined in the no-response timer control registers. In case this command is sent while the timer is running, it is reset and restarted. In NFCIP-1 active communication mode the no-response timer cannot be started using the direct command. In case this timer expires before the peer NFC device (a device with whom communication is going on) switches on its field an interrupt is sent. In all modes, where timer is set to nonzero value, it is a must that M_txe is not set and interrupt I_txe is read via SPI for synchronization between transmitter and timer. General purpose timer The triggering of the general purpose timer is configured by setting the General purpose and no-response timer control register. It can be used to survey the duration of the reception process (triggering by start of reception, after SOF) or to time out the PCD to PICC response time (triggered by end of reception, after EOF). In the NFCIP-1 active communication mode it is used to timeout the field switching off. In all cases an IRQ is sent when it expires. The general purpose timer can also be started by sending the direct command Start general purpose timer. In case this command is sent while the timer is running, it is reset and restarted. DS11793 - Rev 7 page 14/116 ST25R3911B Application information Wake-up timer Wake timer is primarily used in the wake-up mode (see Section 1.2.5 Wake-up mode). Additionally it can be used by sending a direct command Start wake-up Timer. This command is accepted in any operation mode except wake-up mode. When this command is sent the RC oscillator used as clock source for wake-up timer is started, timeout is defined by setting in the Wake-up timer control register. When the timer expires, an IRQ with the I_wt flag in the Error and wake-up interrupt register is sent. wake-up timer is useful in the Low Power operation mode, in which other timers cannot be used (in the Low Power operation mode the crystal oscillator, which is clock source for the other timers, is not running). Note: The tolerance of wake-up timer timeout is defined by tolerance of the RC oscillator. 1.2.8 A/D converter The ST25R3911B features an 8-bit successive approximation A/D converter. Inputs to the A/D converter can be multiplexed from different sources to be used in several direct commands and adjustment procedures. The result of the last A/D conversion is stored in the A/D converter output register. The A/D converter has two operating modes, absolute and relative. • In absolute mode the low reference is 0 V and the high reference is 2 V. This means that A/D converter input range is from 0 to 2 V, 00h code means that input is 0 V or lower, FFh means that input is 2 V - 1 LSB or higher (LSB is 7.8125 mV). • In relative mode low reference is 1/6 of VSP_A and high reference is 5/6 of VSP_A, so the input range is from 1/6 to 5/6 VSP_A. Relative mode is used only in phase measurement (phase detector output is proportional to power supply). In all other cases absolute mode is used. 1.2.9 Phase and amplitude detector This block is used to provide input to A/D converter to perform measurements of amplitude and phase, expected by direct commands Measure amplitude and Measure phase. Several phase and amplitude measurements are also performed by direct commands Calibrate modulation depth and Calibrate antenna. Phase detector The phase detector monitors the phase difference between the transmitter output signals (RFO1 and RFO2) and the receiver input signals RFI1 and RFI2, which are proportional to the signal on the antenna LC tank. These signals are first elaborated by digitizing comparators, then digitized signals are processed by a phase detector with a strong low-pass filter to get average phase difference. The phase detector output is inversely proportional to the phase difference between the two inputs. The 90° phase shift results in VSP_A/2 output voltage, in case both inputs are in phase output voltage is VSP_A, in case they are in opposite phase output voltage is 0 V. During execution of direct command Measure phase this output is multiplexed to A/D converter input (A/D converter is in relative mode during execution of command Measure phase). Since the A/D converter range is from 1/6 to 5/6 VSP_A the actual phase detector range is from 30º to 150º. Figure 6 and Figure 7 show the two inputs and the output of phase detector, respectively, in case of 90º and 135º shifts. DS11793 - Rev 7 page 15/116 ST25R3911B Application information Figure 6. Phase detector inputs and output in case of 90º phase shift VSP_A Input 1 0 VSP_A Input 2 0 VSP_A Output VSP_A/2 0 Figure 7. Phase detector inputs and output in case of 135º phase shift VSP_A Input 1 0 VSP_A Input 2 0 VSP_A Output VSP_A/2 0 Amplitude detector Signals from pins RFI1 and RFI2 are used as inputs to the self-mixing stage. The output of this stage is a DC voltage proportional to amplitude of signal on pins RFI1 and RFI2. During execution of direct command Measure amplitude this output is multiplexed to A/D converter input. 1.2.10 External field detector The External field detector is used to detect the presence of an external device generating an RF field. It is automatically switched on in NFCIP-1 active communication modes; it can also be used in other modes. The External field detector supports two different detection thresholds, Peer detection threshold and Collision avoidance threshold. The two thresholds can be independently set by writing the External field detector threshold register. The actual state of the External field detector output can be checked by reading the Auxiliary display register. Input to this block is the signal from the RFI1 pin. Peer detection threshold This threshold is used to detect the field emitted by peer NFC device with which the NFC communication is going on (initiator field in case the ST25R3911B is a target and the opposite, target field in case the ST25R3911B is an initiator). It can be selected in the range from 75 to 800 mVpp. When this threshold is enabled, the External field detector is in low-power mode. An interrupt is generated when an external field is detected, and also when it is switched off. With such an implementation, it can also be used to detect when the external field disappears. This is useful to detect the moment when the peer NFC device (it can be either an initiator or a target) has stopped emitting an RF field. DS11793 - Rev 7 page 16/116 ST25R3911B Application information The External field detector is automatically enabled in the low-power Peer detection mode when NFCIP-1 mode (initiator or target) is selected in the Bit rate definition register. Additionally, it can be enabled by setting bit en_fd in the Auxiliary display register. Collision avoidance threshold The NFC field on direct commands must not be used for normal R/W operation. Instead, the bit efd_o of the External field detector in the auxiliary display register must be evaluated before turning on the field. The threshold can be selected in the range from 25 to 800 mVpp. For RF collision avoidance in the NFCIP-1 active communication, the RF collision avoidance is executed by sending the NFC field on direct command. The recommended values is rfe = 0x7. 1.2.11 Power supply system The ST25R3911B (Figure 8) features two positive supply pins, VDD and VDD_IO. VDD is the main power supply pin. It supplies the ST25R3911B blocks through three regulators (VSP_A, VSP_D and VSP_RF). VDD range from 2.4 to 5.5 V is supported. VDD_IO is used to define supply level for digital communication pins (/SS, MISO, MOSI, SCLK, IRQ, MCU_CLK). Digital communication pins interface with ST25R3911B logic through level shifters, therefore the internal supply voltage can be either higher or lower than VDD_IO. VDD_IO range from 1.65 to 5.5 V is supported. Figure 8. ST25R3911B power supply VDD EN sup3V 1 kΩ VSP_D REG Power-down support VSP_A REG 50 Ω BGR and AGC VSP_RF REG VSP_RF VSP_A VSP_D AGD RV reg 2Ah adjust AUTOREG reg 2Bh Figure 8 shows the building blocks of the ST25R3911B power supply system and the signals that control it. The power supply system contains three regulators, a power-down support block, a block generating analog reference voltage (AGD) and a block performing automatic power supply adjustment procedure. The three regulators are providing supply to analog blocks (VSP_A), logic (VSP_D) and transmitter (VSP_RF). The use of VSP_A and VSP_D regulators is mandatory at 5 V power supply to provide regulated voltage to analog and logic blocks that only use 3.3 V devices. The use of VSP_A and VSP_D regulators at 3 V supply and VSP_RF regulator at any supply voltage is recommended to improve system PSRR. Regulated voltage can be adjusted automatically to have maximum possible regulated voltage while still having good PSRR. All regulator pins also have corresponding negative supply pins that are externally connected to ground potential (VSS). The reason for separation is in decoupling of noise induced by voltage drops on the internal power supply lines. Figure 2 and Figure 3 show typical ST25R3911B application schematics with all regulators used. All regulator pins and AGD voltage are buffered with capacitors. Recommended blocking capacitor values are detailed in Table 4. DS11793 - Rev 7 page 17/116 ST25R3911B Application information Table 4. Recommended blocking capacitor values Pins Recommended capacitors AGD-VSS 1 μF, in parallel with 10 nF VSP_A-VSN_A 2.2 μF, in parallel with 10 nF VSP_D-VSN_D 2.2 μF, in parallel with 10 nF VSP_RF-VSN_RF 2.2 μF, in parallel with 10 nF Regulators have two basic operation modes depending on supply voltage, 3.3 V supply mode (max 3.6 V) and 5 V supply mode (max 5.5 V). The supply mode is set by writing bit sup3 V in the IO configuration register 2. Default setting is 5 V, hence this bit has to be set to 1 after power-up in case of 3.3 V supply. In 3.3 V mode all regulators are set to the same regulated voltage in range from 2.4 V to 3.4 V, while in 5 V only the VSP_RF can be set in range from 3.9 V to 5.1 V, while VSP_A and VSP_D are fixed to 3.4 V. The regulators are operating when signal en is high (en is configuration bit in Operation control register. When signal en is low the ST25R3911B is in low power Power-down mode. In this mode consumption of the power supply system is also minimized. VSP_RF regulator The purpose of this regulator is to improve PSRR of the transmitter (the noise of the transmitter power supply is emitted and fed back to the receiver). The VSP_RF regulator operation is controlled and observed by writing and reading two regulator registers: • Regulator voltage control register controls the regulator mode and regulated voltage. Bit reg_s controls regulator mode. In case it is set to 0 (default state) the regulated voltage is set using direct command Adjust regulators. When bit reg_s is asserted to 1 regulated voltage is defined by bits rege_3 to rege_1 of the same register. The regulated voltage adjustment range depends on the power supply mode. In case of 5 V supply mode the adjustment range is between 3.9 V and 5.1 V in steps of 120 mV, in case of 3.3 V supply mode the adjustment range is from 2.4 V to 3.4 V with steps of 100 mV. Default regulated voltage is the maximum one (5.1 V and 3.4 V in case of 5 V and 3.3 V supply mode respectively). • Regulator and Timer Display register is a read only register that displays actual regulated voltage when regulator is operating. It is especially useful in case of automatic mode, since the actual regulated voltage, which is the result of direct command Adjust regulators, can be observed. The VSP_RF regulator also includes a current limiter that limits the regulator typically to current of 200 mArms in normal operation (500 mA in case of short). In case the transmitter output current higher the 200 mArms is required, VSP_RF regulator cannot be used to supply the transmitter, VSP_RF has to be externally connected to VDD (connection of VSP_RF to supply voltage higher than VDD is not allowed). The voltage drop of the transmitter current is the main source of the ST25R3911B power dissipation. This voltage drop is composed of drop in the transmitter driver and in the drop on VSP_RF regulator. Due to this it is recommended to set regulated voltage using direct command Adjust regulators. It results in good power supply rejection ration with relatively low dissipated power due to regulator voltage drop. In power‑down mode the VSP_RF regulator is not operating. VSP_RF pin is connected to VDD through 1 kΩ resistor. Connection through resistors ensures smooth power-up of the system and a smooth transition from power‑down mode to other operating modes. VSP_A and VSP_D regulators VSP_A and VSP_D regulators are used to supply the ST25R3911B analog and digital blocks, respectively. In 3.3 V mode, VSP_A and VSP_D regulator are set to the same regulated voltage as the VSP_RF regulator, in 5 V mode VSP_A and VSP_D regulated voltage is fixed to 3.4 V. The use of VSP_A and VSP_D regulators is obligatory in 5 V mode since analog and digital blocks supplied with these two pins contain low voltage transistors that support maximum supply voltage of 3.6 V. In 3.3 V supply mode the use of regulators is strongly recommended in order to improve PSRR of analog processing. For low cost applications it is possible to disable the VSP_D regulator and to supply digital blocks through external short between VSP_A and VSP_D (configuration bit vspd_off in the I/O Configuration register 2. If the VSP_D regulator is disabled VSP_D can alternatively be supplied from VDD (in 3.3 V mode only) in case VSP_A is not more than 300 mV lower than VDD. DS11793 - Rev 7 page 18/116 ST25R3911B Application information Power-down support block In the Power-down mode the regulators are disabled in order to save current. In this mode a low power‑down support block that maintains the VSP_D and VSP_A below 3.6 V is enabled. Typical regulated voltage in this mode is 3.1 V at 5 V supply and 2.2 V at 3 V supply. When 3.3 V supply mode is set the Power-down support block is disabled, its output is connected to VDD through 1 kΩ resistor. Typical consumption of Power-down support block is 600 nA at 5 V supply. Measurement of supply voltages Using direct command Measure power supply it is possible to measure VDD and regulated voltages VSP_A, VSP_D, and VSP_RF. 1.2.12 Communication with an external microcontroller The ST25R3911B is a slave device and the external microcontroller initiates all communication. Communication is performed by a 4-wire Serial Peripheral Interface (SPI). The ST25R3911B sends an interrupt request (pin IRQ) to the microcontroller, which can use clock signal available on pin MCU_CLK when the oscillator is running. Serial Peripheral Interface (SPI) While signal /SS is high the SPI interface is in reset, while it is low the SPI is enabled. It is recommended to keep /SS high whenever the SPI is not in use. MOSI is sampled at the falling edge of SCLK. All communication is done in blocks of 8 bits (bytes). First two bits of first byte transmitted after high to low transition of /SS define SPI operation mode. Table 5. Serial data interface (4-wire interface) signal lines Name Signal /SS Digital input MOSI Digital input MISO Digital output with tristate SCLK Digital input Signal level Description SPI Enable (active low) Serial data input CMOS Serial data output Clock for serial communication MSB bit is always transmitted first (valid for address and data). Read and Write modes support address auto-incrementing. This means that if some additional data bytes are sent/read after the address and first data byte, they are written to/read from addresses incremented by ‘1’. Figure 9 defines possible modes. Figure 9. Exchange of signals with microcontroller DS11793 - Rev 7 MOSI MISO MOSI MISO Bidirectional data IO signal to MCU ST25R3911B ST25R3911B Separate SPI input and output signals to MCU MOSI I/O MISO page 19/116 ST25R3911B Application information MISO output is usually in tristate, it is only driven when output data is available. Due to this the MOSI and the MISO can be externally shorted to create a bidirectional signal. During the time the MISO output is in tristate, it is possible to switch on a 10 kΩ pull down by activating option bits miso_pd1 and miso_pd2 in the IO configuration register 2. Table 6 provides information on the SPI operation modes. Reading and writing of registers is possible in any ST25R3911B operation mode. FIFO operations are possible in case en (bit 7 of the Operation control register) is set and Xtal oscillator frequency is stable. Table 6. SPI operation modes Pattern (communication bits) Mode Mode Trailer Related data M1 M0 C5 C4 C3 C2 C1 C0 Register write 0 0 A5 A4 A3 A2 A1 A0 Register read 0 1 A5 A4 A3 A2 A1 A0 FIFO load 1 0 0 0 0 0 0 0 FIFO read 1 0 1 1 1 1 1 1 Direct command mode 1 1 C5 C4 C3 C2 C1 C0 Data byte (or more bytes in case of auto-incrementing) One or more bytes of FIFO data - Writing data to addressable registers (Write mode) Figure 10 and Figure 11 show cases of writing a single byte and writing multiple bytes with auto-incrementing address. After the SPI operation mode bits, the address of register to be written is provided. Then one or more data bytes are transferred from the SPI, always from the MSB to the LSB. The data byte is written in register on falling edge of its last clock. In case the communication is terminated by putting /SS high before a packet of 8 bits (one byte) is sent, writing of this register is not performed. In case the register on the defined address does not exist or it is a read only register no write is performed. Figure 10. SPI communication: writing a single byte /SS Raising edge indicates end of Write Mode SCLK MOSI X 0 0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X Two leading bits indicate Mode SCLK rising edge Data transferred from MCU DS11793 - Rev 7 SCLK falling edge Data is sampled Data is moved to address page 20/116 ST25R3911B Application information Figure 11. SPI communication: writing multiple bytes /SS /SS raising edge indicates end of Write mode SCLK MOSI X 0 0 A AA A AA DDDD D DDD DD DD D DDD DD 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 D DD DDDD DD D 1 0 7 6 5 4 3 2 1 0 SCLK falling edge Data moved to address + 1 Two leading 0s indicate Write mode SCLK falling edge Data moved to address X SCLK falling edge Data moved to address + n SCLK falling edge Data moved to address + (n-1) Reading data from addressable registers (Read mode) After the SPI operation mode bits the address of register to be read has to be provided from the MSB to the LSB. Then one or more data bytes are transferred to MISO output, always from the MSB to the LSB. As in case of the write mode also the read mode supports auto-incrementing address. MOSI is sampled at the falling edge of SCLK (like shown in the following diagrams), data to be read from the ST25R3911B internal register is driven to MISO pin on rising edge of SCLK and is sampled by the master at the falling edge of SCLK. In case the register on defined address does not exist all 0 data is sent to MISO. Figure 12 is an example for reading of single byte. Figure 12. SPI communication: reading a single byte /SS /SS raising edge indicates end of Read mode SCLK MOSI X 0 1 MISO A5 A4 A3 A2 A1 tristate Two leading bits indicate Mode X A0 D7 D6 SCLK rising edge Data moved from Address A5-A0 D5 D4 D3 D2 D1 D0 tristate SCLK falling edge Data transferred to MCU SCLK rising edge SCLK falling edge Data transferred from MCU Data is sampled DS11793 - Rev 7 page 21/116 ST25R3911B Application information Loading transmitting data into FIFO Loading the transmitting data into the FIFO is similar to writing data into an addressable registers. Difference is that in case of loading more bytes all bytes go to the FIFO. SPI operation mode bits 10 indicate FIFO operations. In case of loading transmitting data into FIFO all bits are set to 0. Then a bit-stream, the data to be sent (1 to 96 bytes), can be transferred. In case the command is terminated by putting /SS high before a packet of 8 bits (one byte) is sent, writing of that particular byte in FIFO is not performed. Figure 13 shows how to load the Transmitting Data into the FIFO. Figure 13. SPI communication: loading of FIFO /SS /SS raising edge indicates end of FIFO Mode SCLK MOSI X 1 0 0 0 10 pattern indicates FIFO Mode 0 0 0 0 1 to 96 bytes X Start of paylod data SCLK rising edge SCLK falling edge Data transferred from MCU Data is sampled Reading received data from FIFO Reading received data from the FIFO is similar to reading data from an addressable registers. Difference is that in case of reading more bytes they all come from the FIFO. SPI operation mode bits 10 indicate FIFO operations. In case of reading the received data from the FIFO all bits are set to 1. On the following SCLK rising edges the data from FIFO appears as in case of read data from addressable registers. If the command is terminated by putting /SS high before a packet of 8 bits (one byte) is read, that particular byte is considered unread and will be the first one read in next FIFO read operation. DS11793 - Rev 7 page 22/116 ST25R3911B Application information Figure 14. SPI communication: reading of FIFO /SS /SS raising edge indicates end of FIFO Mode SCLK MOSI X 1 0 1 MISO 1 1 1 1 1 X 1 to 96 bytes tristate 10 pattern indicates FIFO Mode tristate SCLK rising edge Data moved from FIFO SCLK rising edge SCLK falling edge Data transferred from MCU Data is sampled SCLK falling edge Data transferred to MCU Direct command mode Direct command mode has no arguments, so a single byte is sent. SPI operation mode bits 11 indicate Direct command mode. The following six bits define command code, sent MSB to LSB. The command is executed on falling edge of last clock (see Figure 15). While execution of some Direct Commands is immediate, there are others that start a process of certain duration (calibration, measurement…). During execution of such commands it is not allowed to start another activity over the SPI interface. After execution of such a command is terminated an IRQ is sent. Figure 15. SPI communication: direct command /SS /SS raising edge indicates start of command execution SCLK MOSI X 1 1 Two leading 1s indicate Command Mode C5 C4 SCLK rising edge Data transferred from MCU C3 C2 C1 C0 X SCLK falling edge Data is sampled Direct command chaining As shown in Figure 16, direct commands with immediate execution can be followed by another SPI mode (Read, Write or FIFO) without deactivating the /SS signal in between. DS11793 - Rev 7 page 23/116 ST25R3911B Application information Figure 16. SPI communication: direct command chaining /SS Direct command Read, Write or FIFO Mode SPI timing Table 7. SPI timing Symbol Parameter Min Typ Max Unit Comments General timing (VDD = VDD_IO = VSP_D = 3.3 V, 25 °C) TSCLK SCLK period 167 - - TSCLK=TSCLKL+TSCLKH, use of shorter SCLK period may lead to incorrect FIFO operation. TSCLKL SCLK low 70 - 1 - TSCLKH SCLK high 70 - - - TSSH SPI reset (/SS high) 100 - - TNCSL /SS falling to SCLK rising 25 - - First SCLK pulse TNCSH SCLK falling to /SS rising 300 - - Last SCLK pulse ns - TDIS Data in set-up time 10 - - - TDIH Data in hold time 10 - - - Read timing (VDD = VDD_IO = VSP_D = 3.3 V, 25 °C, CLOAD ≤ 50 pF) TDOD TDOHZ Data out delay Data out to high impedance delay - 20 20 - ns - Figure 17. SPI general timing /SS tNCSL tSCLKH ... tSCLKL ... SCLK tDIS MOSI MISO DS11793 - Rev 7 tNCSH tDIH DATAI DATAI ... DATAI ... page 24/116 ST25R3911B Application information Figure 18. SPI read timing /SS ... ... SCLK ... DATAI MOSI DATAO MISO ... DATAO tDOD tDOHZ Interrupt interface There are three interrupt registers implemented in the ST25R3911B: Main interrupt register contains information about six interrupt sources, while two bits reference to interrupt sources detailed in Timer and NFC interrupt register and Error and wake-up interrupt register. When an interrupt condition is met the source of interrupt bit is set in the Main interrupt register and the IRQ pin transitions to high. Table 8. IRQ output Name IRQ Signal Digital output Signal level CMOS Description Interrupt output pin The microcontroller then reads the Main interrupt register to distinguish between different interrupt sources. The interrupt registers 0x17, 0x18 and 0x19 are to be read in one attempt. After a particular Interrupt register is read, its content is reset to 0. Exceptions to this rule are the bits pointing to auxiliary registers. These bits are only cleared when corresponding auxiliary register is read. IRQ pin transitions to low after the interrupt bit(s) that caused its transition to high has (have) been read. Note: There may be more than one interrupt bit set in case the microcontroller does not immediately read the interrupt registers after the IRQ signal has been set and another event causing interrupt has occurred. In that case the IRQ pin transitions to low after the last bit that caused interrupt is read. If an interrupt from a certain source is not required, it can be disabled by setting corresponding bit in the Mask Interrupt registers. When masking a given interrupt source the interrupt is not produced, but the source of interrupt bit is still set in Interrupt registers. FIFO water level and FIFO status registers The ST25R3911B contains a 96 byte FIFO. In case of transmitting the Control logic shifts the data that was previously loaded by the external microcontroller to the Framing Block and further to the transmitter. During reception, the demodulated data is stored in the FIFO and the external microcontroller can download received data at a later moment. Transmit and receive capabilities of the ST25R3911B are not limited by the FIFO size due to a FIFO water level interrupt system. During transmission an interrupt is sent (IRQ due to FIFO water level in the Main interrupt register) when the content of data in the FIFO passes from (water level + 1) to water level and the complete transmit frame has not been loaded in the FIFO yet. The external microcontroller can now add more data in the FIFO. The same stands for the reception: when the number of received bytes passes from (water level - 1) to water level, an interrupt is sent to inform the external controller that data has to be downloaded from FIFO in order not to lose the received data due to FIFO overflow. DS11793 - Rev 7 page 25/116 ST25R3911B Application information During transmission water level IRQ is additionally set in case all transmission bytes have not been written in FIFO yet and if number of bytes written into FIFO is lower than water level. In this case an IRQ is sent when number of bytes in FIFO drops below 4. Note: FIFO IRQ is not produced while SPI is active in FIFO load or read mode. Due to this the FIFO loading/reading rate has to be higher than Tx/Rx bit rate, once FIFO loading/reading is finished the /SS pin has to be pulled to VDD (logic remains in FIFO load/read mode as long as /SS remains low). The external controller has to serve the FIFO faster than data is transmitted or received. Using SCLK frequency that is at least double than the actual receive or transmit bit rate is recommended. There are two settings of the FIFO water level available for receive and transmit in the IO configuration register 1. At the beginning of a data reception the FIFO, FIFO status register 1 and FIFO status register 2 are cleared automatically. After data reception is terminated the external microcontroller needs to know how much data is still stored in the FIFO: This information is available in the FIFO status register 1 and FIFO status register 2 that display number of bytes in the FIFO that were not read out. FIFO status register 1 can also be read while reception and transmission processes are active to get info about current number of bytes in FIFO. In that case user has to take in account that Rx/Tx process is going on and that the number of data bytes in FIFO may have already changed by the time the reading of register is finished. The FIFO status register 2 contains the information on whether the last received byte was completed or not. An incomplete byte can occur on certain protocols that use frames shorter than one byte for status information or for example, if the receive data stream breaks in the middle due to an unexpected card removal. The status of the last received byte and the number of valid bits received is stored in the bits fifo_ncp, fifo_lb, and np_lb. These bits are cleared when the FIFO status register 2 is read and must be stored in the MCU if needed for further processing. The FIFO status register 2 additionally contains two bits that indicate that the FIFO was not correctly served during reception or transmission process (FIFO overflow and FIFO underflow). FIFO overflow is set when too much data is written in FIFO. In case this bit is set during reception the external controller did not react on time on water level IRQ and more than 96 bytes were written in the FIFO. The received data is of course corrupted in such a case. During transmission this means that controller has written more data than FIFO size. The data to be transmitted was corrupted. FIFO underflow is set when data was read from empty FIFO. In case this bit is set during reception the external controller read more data than was actually received. During transmission this means that controller has failed to provide the quantity of data defined in number of transmitted bytes registers on time. Pin MCU_CLK Pin MCU_CLK may be used as clock source for the external microcontroller. Depending on the operation mode either a low frequency clock (32 kHz) from the RC oscillator or the clock signal derived from crystal oscillator is available on pin MCU_CLK. The MCU_CLK output pin is controlled by bits out_c1, out_cl0 and lf_clk_off in the IO configuration register 1. Bits out_cl enable the use of pin MCU_CLK as clock source and define the division for the case the crystal oscillator is running (13.56 MHz, 6.78 MHz and 3.39 MHz are available). Bit lf_clk_off controls the use of low frequency clock (32 kHz) in case the crystal oscillator is not running. By default configuration (defined at power-up) the 3.39 MHz clock is selected and the low frequency clock is enabled. In Transparent mode (see Section 1.2.22 Stream mode and transparent mode) the use of MCU_CLK is mandatory since clock that is synchronous to the field carrier frequency is needed to implement receive and transmit framing in the external controller. The use of MCU_CLK is recommended also for the case where the internal framing is used. Using MCU_CLK as the microcontroller clock source generates noise synchronous with the reader carrier frequency and is therefore filtered out by the receiver, while using some other incoherent clock source may produce noise that perturbs the reception. Use of MCU_CLK is also better for EMC compliance. DS11793 - Rev 7 page 26/116 ST25R3911B Application information 1.2.13 Direct commands Table 9. Direct commands Command code (hex) Command Command chaining Comments Operation mode (1) Interrupt after termination C1 Set default Puts the ST25R3911B in default state (same as after power-up) No No All C2, C3 Clear Stops all activities and clears FIFO Yes No en C4 Transmit with CRC Starts a transmit sequence using automatic CRC generation Yes No en, tx_en C5 Transmit without CRC Starts a transmit sequence without automatic CRC generation Yes No en, tx_en C6 Transmit REQA Transmits REQA command (ISO14443A mode only) Yes No en, tx_en C7 Transmit WUPA Transmits WUPA command (ISO14443A mode only) Yes No en, tx_en C8 NFC initial field ON Performs initial RF collision avoidance and switch on the field Yes Yes en (2) C9 NFC response field ON Performs response RF collision avoidance and switch on the field Yes Yes en(2) CA NFC response field ON with n=0 Performs response RF collision avoidance with n=0 and switch on the field Yes Yes en(2) CB Go to normal NFC mode Accepted in NFCIP-1 active communication bit rate detection mode Yes No - CC Analog preset Presets Rx and Tx configuration based on state of Mode definition register and Bit rate definition register Yes No All D0 Mask receive data Receive after this command is ignored Yes No en, rx_en D1 Unmask receive data Receive data following this command is normally processed (this command has priority over Internal mask receive timer) Yes No en, rx_en D2 - Not used - - - D3 Measure amplitude Amplitude of signal present on RFI inputs is measured. The result is stored in A/D converter No output register Yes en D4 Squelch Performs gain reduction based on the current noise level No No en, rx_en D5 Reset Rx gain Clears the current squelch setting and loads the manual gain reduction from Receiver configuration register 1 No No en D6 Adjust regulators Adjusts supply regulators according to the current supply voltage level No Yes en (3) D7 Calibrate modulation depth Starts sequence that activates the Tx, measures the modulation depth, and adapts it to comply with the specified modulation depth No Yes en D8 Calibrate antenna Starts the sequence to adjust parallel capacitances connected to TRIMx_y pins so that the antenna LC tank is in resonance No Yes en D9 Measure phase Measurement of phase difference between the signal on RFO and RFI No Yes en DA Clear RSSI Clears RSSI bits and restarts the measurement Yes No en DS11793 - Rev 7 page 27/116 ST25R3911B Application information Command code (hex) Command Command chaining Comments Operation mode (1) Interrupt after termination DC Transparent mode Amplitude of signal present on RFI inputs is measured, result is stored in A/D converter output register No Yes en DD Calibrate capacitive sensor Calibrates capacitive sensor No Yes See note(4) DE Measure capacitance Perform capacitor sensor measurement No Yes See note(5) DF Measure power supply - No Yes en E0 Start general-purpose timer Yes No en E1 Start wake-up timer - Yes No All except wu E2 Start mask receive timer - Yes No See note (6) E3 Start no-response timer - Yes No en, rx_en FC Test access Enable/W to test registers Yes No All Other Fx - Reserved for test - - - Other codes - Not used - - - 1. Defines the bits of the Operation control register that must be set to accept a particular command. 2. After termination of this command I_cat or I_cac IRQ is sent. 3. This command is not accepted in case the external definition of the regulated voltage is selected in the Regulator voltage control register (bit reg_s is set to high). 4. Accepted in all modes in case bit cs_mcal of the Capacitive sensor control register is set to 0. It is recommended to execute this command in power-down mode. 5. Accepted in all modes, it is recommended to execute this command in power-down mode. 6. Accepted only in the Initial NFC active target communication mode. Set default This direct command puts the ST25R3911B in the same state as power-up initialization. All registers are initialized to the default state. The only exceptions are for I/O IO configuration register 1, IO configuration register 2 and Operation control register (not affected by the Set default command) that are set to default state only at power-up. Note: Results of different calibration and adjust commands are also lost. This direct command is accepted in all operating modes. In case this command is sent while en (bit 7 of the Operation control register) is not set FIFO and FIFO status registers are not cleared. Direct command chaining is not allowed since this command clears all registers. IRQ due to termination of direct command is not produced. Clear This direct command stops all current activities (transmission or reception), clears FIFO, clears FIFO status registers and stops all timers except wake-up timer. If bit nrt_emv in the General purpose and no-response timer control register is set to 1, the No-Response timer is not stopped. If nfc_ar (in the Mode definition register) is set to 1, the internal timer for the Response RF collision avoidance is not stopped, and the Response RF collision avoidance takes place once this timer expires. To set nfc_ar to 0 before sending the direct command Clear to stop any Response RF collision avoidance activity too. It also clears collision and interrupt registers. This command has to be sent first in a sequence preparing a transmission before writing data to be transmitted in FIFO (except in case of direct commands Transmit REQA and Transmit WUPA). This command is accepted in case en (bit 7 of the Operation control register) is set and the crystal oscillator frequency is stable. Direct command chaining is possible. IRQ due to termination of direct command is not produced. DS11793 - Rev 7 page 28/116 ST25R3911B Application information Transmit commands All Transmit commands (Transmit with CRC, Transmit without CRC, Transmit REQA and Transmit WUPA) are accepted only in case the transmitter is enabled (bit tx_en is set). Before sending the commands Transmit with CRC and Transmit without CRC direct command, the Clear has to be sent, followed by the definition of the number of the transmitted bytes and the writing of the data to be transmitted in FIFO. Direct commands Transmit REQA and Transmit WUPA are used to transmit the ISO14443A commands REQA and WUPA respectively. It is not necessary to send the Clear command before these two commands. The number of valid bits in the last byte must be set to zero (nbtx in the Number of transmitted bytes register 2) prior to executing Transmit REQA or Transmit WUPA. Direct command chaining is possible. IRQ due to termination of direct command is not produced. NFC field ON commands These commands are used to perform the RF collision avoidance for NFCIP-1 active communication, and switch the field on in case no collision is detected. The collision avoidance threshold defined in the External field detector threshold register is used to observe the RF_IN inputs and to determine whether there is some other device emitting the 13.56 MHz field, present close to the ST25R3911B antenna. In case collision is not detected the reader field is switched on automatically (bit tx_en in the Operation control register is set) and an IRQ with I_cat flag in Timer and NFC interrupt register is sent after minimum guard time defined by the NFCIP-1 standard to inform the controller that message transmission using a Transmit command can be initiated. If a presence of external field is detected, an IRQ with I_cac flag is sent. In such case a transmission cannot be performed, NFC field ON command has to be repeated as long as collision is not detected anymore. Command NFC Initial field ON performs Initial collision avoidance according to NFCIP-1 standard; the number n is defined by nfc_n1 and nfc_n0 bits in Auxiliary definition register. Command NFC response field ON performs Response collision avoidance according to NFCIP-1 standard; number n is defined by bits nfc_n1 and nfc_n0 in Auxiliary definition register. Command NFC response field ON with n=0 performs Response collision avoidance where n is 0. The implemented active delay time is on lower NFCIP-1 specification limit, since the actual active delay time also includes detection of the field deactivation, controller processing delay and sending the NFC field ON command. This command is accepted in case en (bit 7 of the Operation control register) is set and both the crystal oscillator frequency and the amplitude are stable. Figure 19. Direct command NFC initial field ON RF on TRFW Start TIDT n x TRFW TIRFG MS42450V1 DS11793 - Rev 7 page 29/116 ST25R3911B Application information Figure 20. Direct command NFC response field ON RF on TRFW Start TADT n x TRFW TARFG MS42451V1 Table 10. Timing parameters of NFC field ON commands Symbol Parameter Value TIDT Initial delay time 4096 TRWF RF waiting time 512 TIRFG Initial guard time >5 TADT Active delay time 768 TARFG Active guard time 1024 Unit /fc Comments NFC initial field ON - ms NFC initial field ON /fc NFC response field ON Go to normal NFC mode This command is used to transition from NFC target bit rate detection mode to normal mode. Additionally, it copies the content of the NFCIP bit rate detection display register to the NFCIP bit rate detection display register, and correctly sets the bit tr_am in the Auxiliary definition register. Analog preset This command is used to preset receiver and transmitter configuration based on state of Mode definition register and Bit rate definition register. In case of sub-carrier bit stream or BPSK bit stream mode, this command should not be used. The list of configuration bits that are preset is given in Table 11. DS11793 - Rev 7 page 30/116 ST25R3911B Application information Table 11. Register preset bits Bit Bit name Function Address 02h: Table 21. Operation control register 5 rx_chn 1: one channel enabled → NFCIP-1 active communication (both initiator and target) 3 tx_en 0: disable TX operation → NFCIP-1 active communication (both initiator and target) Note: In case of any target mode or NFCIP-1 initiator mode, the tx_en bit is set to 0 to disable the transmitter if it is enabled. In NFCIP-1 mode the switching on of the transmitter field is controlled by dedicated commands. Address 05h: Table 27. ISO14443A and NFC 106kb/s settings register 5 nfc_f0 1: Adds SB (F0) and LEN byte during Tx and skip SB (F0) byte during Tx → NFCIP-1 active communication (both initiator and target) Address 09h: Table 35. Auxiliary definition register Tx modulation type (depends on mode definition and Tx bit rate) 5 tr_am 0: OOK → ISO144443A, NFCIP-1 106 kb/s (both initiator and target), NFC Forum Type 1 Tag 1: AM → ISO144443B, FeliCa™, NFCIP-1 212 kb/s, and 424 kb/s Enables External field detector with Peer detection threshold 4 en_fd 0: All modes except NFCIP-1 active communication 1: NFCIP-1 active communication (both initiator and target) Address 0Ah: Table 36. Receiver configuration register 1 7 ch_sel 0: Enables AM channel → NFCIP-1 active communication (both initiator and target) AM demodulator select (depend on Rx bit rate) 6 amd_sel 0: Peak detector → All Rx bit rates equal or below fc/16 (848 kb/s) 1: Mixer → All VHBR Rx bit rates (fc/8 and fc/4) 5 lp2 4 lp1 3 lp0 2 h200 1 h80 0 z12k Low pass control (depends on mode definition and Rx bit rate), see Table 3. Receiver filter selection and gain range First and third stage zero setting (depends on mode definition and Rx bit rate), see Table 3. Receiver filter selection and gain range Address 0Ch: Table 38. Receiver configuration register 3 Clips output of first and second stage 1 lim 0: All modes except NFCIP-1 active communication 1: NFCIP-1 active communication (both initiator and target) Forces gain reduction in second and third gain stage 0 rg_nfc 0: All modes except NFCIP-1 active communication 1: NFCIP-1 active communication (both initiator and target) DS11793 - Rev 7 page 31/116 ST25R3911B Application information Mask receive data and Unmask receive data After the direct command Mask receive data, the rx_on signal that enables the RSSI and AGC operation of the receiver (see Section 1.1.2 Receiver) is forced to low, the processing of the receiver output by the receive data framing block is disabled. This command is useful to mask receiver and receive framing from processing the data when there is actually no input and only a noise would be processed (for example in case where a transponder processing time after receiving a command from the reader is long). Masking of receive is also possible using Mask Receive timer. Actual masking is a logical or of the two mask receive processes. The direct command unmask receive data is enabling normal processing of the received data (signal rx_on is set high to enable the RSSI and AGC operation), the receive data framing block is enabled. A common use of this command is to enable again the receiver operation after it was masked by the command mask receive data. In case Mask Receive timer is running while command unmask receive data is received, reception is enabled, Mask Receive timer is reset. The commands mask receive data and unmask receive data are only accepted when the receiver is enabled (bit rx_en is set). Direct command chaining is possible. IRQ due to termination of direct command is not produced. Measure amplitude This command measures the amplitude on the RFI inputs and stores the result in the A/D converter output register. When this command is executed, the transmitter and Amplitude detector are enabled, the output of the Amplitude detector is multiplexed to the A/D converter input (the A/D converter is in absolute mode). The Amplitude detector conversion gain is 0.6 VINPP/ VOUT. One LSB of the A/D converter output represents 13.02 mVpp on the RFI inputs. A 3 Vpp signal (the maximum allowed level on each of the two RFI inputs), results in 1.8 V output DC voltage and produces a value of 1110 0110b on the A/D converter output. Duration time: 25 μs max. This command is accepted in case en (bit 7 of the Operation control register) is set and crystal oscillator frequency is stable. Direct command chaining is not possible. IRQ due to termination of direct command is produced after command execution is terminated. Squelch This direct command is intended to avoid demodulation problems of transponders that produce a lot of noise during data processing. It can also be used in a noisy environment. The operation of this command is explained in Squelch. Duration time: 500 μs max. This command is only accepted when the transmitter and the receiver are operating. Command is actually executed only in case signal rx_on is low. Direct command chaining is not possible. IRQ due to termination of direct command is not produced. Reset Rx gain This command initializes the AGC, Squelch and RSSI block. Sending this command stops a squelch process in case it is going on, clears the current Squelch setting and loads the manual gain reduction from Receiver configuration register 4. This command is accepted in case en (bit 7 of the Operation control register) is set and crystal oscillator frequency is stable. Direct command chaining is possible. IRQ due to termination of direct command is not produced. DS11793 - Rev 7 page 32/116 ST25R3911B Application information Adjust regulators When this command is sent the power supply level of VDD is measured in maximum load conditions and the regulated voltage reference is set 250 mV below this measured level to ensure maximum possible stable regulated supply (see Section 1.2.11 Power supply system). The use of this command increases the system PSSR. At the beginning of execution of the command, both the receiver and transmitter are switched on to have the maximum current consumption, and the regulators are set to their maximum regulated voltage (5.1 V in case of 5 V supply and 3.4 V in case of 3.3 V supply). After 300 μs VSP_RF is compared to VDD, if is not at least 250 mV lower the regulator setting is reduced by one step (120 mV in case of 5 V supply and 100 mV in case of 3.3 V supply) and measurement is done after another 300 μs. The procedure is repeated until VSP_RF drops at least 250 mV below VDD, or until the minimum regulated voltage (3.9 V in case of 5 V supply and 2.4 V in case of 3.3 V supply) is reached. Duration time: 5 ms max. This command is accepted if en (bit 7 of the Operation control register) is set and crystal oscillator frequency is stable. This command is not accepted when the external definition of the regulated voltage is selected in the Regulator voltage control register(bit reg_s is set to H). Direct command chaining is not possible. IRQ due to termination of direct command is produced after command execution is terminated. Calibrate modulation depth Starts a sequence that activates the transmission, measures the modulation depth and adapts it to comply with the modulation depth specified in the AM modulation depth control register. When calibration procedure is finished result is displayed in the same register. Refer to Section 1.2.20 AM modulation depth: definition and calibration for details about setting the AM modulation depth and running this command. Duration time: 275 μs max. This command is accepted when en (bit 7 of the Operation control register) is set and crystal oscillator frequency is stable. Direct command chaining is not possible. IRQ due to termination of direct command is produced after command execution is terminated. Calibrate antenna Sending this command starts a sequence that adjusts the parallel capacitances connected to TRIMx_y pins so that the antenna LC tank is in resonance. See Section 1.2.21 Antenna tuning for details. Duration time: 250 μs max. This command is accepted when en (bit 7 of the Operation control register) is set and crystal oscillator frequency is stable. Measure phase This command measures the phase difference between the signals on the RFO outputs and the signals on the RFI inputs and stores the result in the A/D converter output register. During execution of the direct command Measure phase the transmitter and Phase detector are enabled, the Phase detector output is multiplexed on the input of A/ D converter, which is set in relative mode. Since the A/D converter range is from 1/6 VSP_A to 5/6 VSP_A the actual phase detector range is from 30º to 150º. Values below 30º result in FFh, while values above 150º result in 00h. One LSB of the A/D conversion output represents 0.13% of carrier frequency period (0.468°). The result of A/D conversion is in case of 90º phase shift in the middle of range (1000 0000b or 0111 1111b). A value higher than 1000 0000b means that phase detector output voltage is higher than VSP_A/2, which corresponds to case with phase shift lower than 90º. In the opposite case, when the phase shift is higher than 90º, the result of A/D conversion is lower than 0111 1111b. For example, the phase difference of 135º shown in Figure 7 results in 0.75 VSP_A, result stored in A/D converter is 31d (1Fh). The phase measurement result can be calculating using the following formulas: DS11793 - Rev 7 page 33/116 ST25R3911B Application information • • • 0º ≤ φ ≤ 30º: result = 255 (decimal) 30º < φ < 150º: angle (in º) = 30 + [(255 - u_angle) / 255) * 120] 150º ≤ φ ≤ 180º: result = 0 (decimal) Duration time: 25 μs max. This command is accepted in case en (bit 7 of the Operation control register) is set and crystal oscillator frequency is stable. Direct command chaining is not possible. IRQ due to termination of direct command is produced after command execution is terminated. Clear RSSI The receiver automatically clears the RSSI bits in the RSSI display register and starts to measure the RSSI of the received signal when the signal rx_on is asserted. Since the RSSI bits store peak value (peak-hold type), the variations of the receiver input signal is not followed (this may happen in case of long messages or test procedures). The direct command Clear RSSI clears the RSSI bits in the RSSI display register, and the RSSI measurement is restarted (in case, of course, rx_on is still high). This command is accepted in case en (bit 7 of the Operation control register) is set and crystal oscillator frequency is stable. Direct command chaining is possible. IRQ due to termination of direct command is not produced. Transparent mode Enters in the Transparent mode. The Transparent mode is entered on the rising edge of signal /SS and is maintained as long as signal /SS is kept high. This command is accepted when en (bit 7 of the Operation control register) is set and crystal oscillator frequency is stable. Calibrate capacitive sensor This command calibrates the capacitive sensor. See Section 1.1.5 Capacitive sensor for more details. Duration time: 3 ms max. This command is executed in case capacitive sensor automatic calibration mode is set (all bits cs_mcal in the Capacitive sensor control register are set to 0). In order to avoid interference with crystal oscillator and reader magnetic field, it is strongly recommended to use this command in power-down mode only. Direct command chaining is not possible. IRQ due to termination of direct command is produced after command execution is terminated. Measure capacitance This command performs the capacitance measurement. See Section 1.1.5 Capacitive sensor for more details. Duration time: 250 μs max. To avoid interference with crystal oscillator and reader magnetic field, it is highly recommended to use this command only in power-down mode. Direct command chaining is not possible. IRQ due to termination of direct command is produced after command execution is terminated. Measure power supply This command performs the power supply measurement. Configuration bits mpsv1 and mpsv0 of the Regulator voltage control register define which power supply is measured (VDD,VSP_A, VSP_D and VSP_RF can be measured). Result of measurement is stored in the A/D converter output register. During the measurement the selected supply input is connected to a 1/3 resistive divider, whose output is multiplexed to A/D converter in absolute mode. Due to division by 3, one LSB represents 23.438 mV. Duration time: 25 μs max. This command is accepted in case en (bit 7 of the Operation control register) is set and crystal oscillator frequency is stable. DS11793 - Rev 7 page 34/116 ST25R3911B Application information Direct command chaining is not possible. IRQ due to termination of direct command is produced after command execution is terminated. 1.2.14 Start timers See Section 1.2.7 Timers. 1.2.15 Test access The ST25R3911B does not contain any dedicated test pins. A direct command Test access is used to enable RW access of test registers and entry in different test modes. Pins CSI and CSO are used as test pins. Test mode entry and access to test registers Test registers are not part of normal SPI register address space. After sending a direct command Test access, the test registers can be accessed using normal Read/Write register SPI command. Access to test registers is possible in a chained sequence of command, where first command Test access is sent followed by read/write access to test registers using auto increment feature. After SPI interface reset (SS toggle), the content of test registers is kept. Test register are set to default state at power-up and by sending the Clear test registers command. Table 12. Analog test and observation register Test address 01h: Analog test and observation register - Type: RW Bit Name Default Function Comments 7 tana_7 0 - Reserved 6 tana_6 0 - Reserved 5 tana_5 0 - Reserved 4 - 0 Not used - 3 tana_3 0 2 tana_2 0 1 tana_1 0 0 tana_0 0 DS11793 - Rev 7 See Table 13 These test modes are also intended for observation in normal mode. Other modes of this register are also available when analog test mode is not set. page 35/116 ST25R3911B Application information Table 13. Test access register - Tana signal selection of CSI and CSO pins Tana_ Pin CSI 3 2 1 0 Type Functionality Pin CSO Type Comments Functionality 0 0 0 1 AO Analog output of AM channel (before digitizer) DO Digital output of AM channel (after digitizer) Normal operation 0 0 1 0 AO Analog output of PM channel (before digitizer) DO Digital output of PM channel (after digitizer) Normal operation 0 0 1 1 AO Analog output of AM channel (before digitizer) AO Analog output of PM channel (before digitizer) Normal operation 0 1 0 0 DO Digital output of AM channel (after digitizer) DO Digital output of PM channel (after digitizer) Normal operation 0 1 0 1 AO Analog signal after first stage AO Analog signal after second stage Normal operation: • PM channel if enabled • AM if PM is not enabled 1 0 0 1 DO Channel selection from logic DO Collision avoidance detector output Collision avoidance detectors are enabled 1 0 1 0 DO Digital Tx modulation signal DO Select PM Analog part of channel selection AO Analog output of AM channel (before digitizer) DO Digital output of AM channel (after digitizer) Normal operation 0 0 0 1 1.2.16 Power-up sequence At power-up, the ST25R3911B enters the power-down mode. The content of all registers is set to the default state. 1. The microcontroller, after a power-up, must correctly configure the two IO configuration registers. The content of these two registers defines operation options related to hardware (power supply mode, crystal type, use of MCU_CLK clock, antenna operation mode). 2. Configure the regulators. It is recommended to use direct command Adjust regulators to improve the system PSRR. 3. When implementing the LC tank tuning, send the direct command Calibrate antenna. 4. When using the AM modulation (ISO-14443B for example), set the modulation depth in the AM modulation depth control register and send the command Calibrate modulation depth. 5. The ST25R3911B is now ready to operate. 1.2.17 Reader operation To begin with, the operation mode and data rate have to be configured by writing the Mode definition register and Bit rate definition register Bit rate definition register. Additionally, the receiver and transmitter operation options related to operation mode have to be defined. This is done automatically by sending the direct command Analog preset. If more options are required apart from those defined by Analog preset, then such options must be additionally set by writing the appropriate registers. Next, the Ready mode has to be entered by setting the bit en of the Operation control register. In this mode, the oscillator is started and the regulators are enabled. When the oscillator operation is stable, an interrupt is sent. Before sending any command to a transponder, the transmitter and receiver have to be enabled by setting the bits rx_en and tx_en. RFID protocols usually require that the reader field is turned on for a while before sending the first command (5 ms for ISO14443). General purpose timer can be used to measure this time interval. If it is necessary to send REQA or WUPA, this is done simply by sending the appropriate direct command, otherwise the following sequence has to be followed: 1. Send the direct command Clear 2. Define the number of transmitted bytes in the Number of transmitted bytes register 1 and Number of transmitted bytes register 2. 3. Write the bytes to be transmitted in the FIFO 4. Send the direct command Transmit with CRC or Transmit without CRC (whichever is appropriate) DS11793 - Rev 7 page 36/116 ST25R3911B Application information 5. When all the data is transmitted, an interrupt is sent to inform the microcontroller that the transmission is finished (IRQ due to end of transmission) After the transmission is executed, the ST25R3911B receiver automatically starts to observe the RFI inputs to detect a transponder response. The RSSI and AGC (when enabled) start. The framing block processes the sub-carrier signal from receiver and fills the FIFO with data. When the reception is finished and all the data is in the FIFO an interrupt is sent to the microcontroller (IRQ due to end of receive), additionally the FIFO status register 1 and FIFO status register 2 display the number of bytes in the FIFO so that the microcontroller can proceed with data download. In case of an error or bit collision detected during reception, an interrupt with appropriate flag is sent. Transmit and Receive when the data packet is longer than FIFO In case a data packet is longer than FIFO, the sequence explained above is modified. Before transmit, the FIFO is filled. During transmit an interrupt is sent when remaining number of bytes is lower than the water level (IRQ due to FIFO water level). The microcontroller in turn adds more data in the FIFO. When all the data is transmitted an interrupt is sent to inform the microcontroller that transmission is finished. During reception situation is similar. In case the FIFO is loaded with more data than the receive water level, an interrupt is sent and the microcontroller in turn reads the data from the FIFO. When reception is finished an interrupt is sent to the microcontroller (IRQ due to end of receive), additionally the FIFO status register 1 and FIFO status register 2 display the number of bytes in the FIFO that are still to be read out. Anticollision–ISO 14443A Note: DS11793 - Rev 7 For this section, it is assumed that there is more than one ISO/IEC 14443A PICC in the RF field of the reader, and all of them are compatible with ISO/IEC 14443 up to level 4. This section describes the anticollision procedure of ST25R3911B for ISO14443A tags. After an ISO14443 type A tag enters in the reader field, the reader has to perform a selection process that brings it into the PROTOCOL state in which the actual application implemented in the tag can be executed. This selection process is described in the ISO/IEC 14443-3. Figure 21 shows the states that a tag and a reader have to pass through to enter the protocol state. The selection procedure starts when a PICC enters the reader field and the PCD sends a REQA (or WUPA) command followed by an anticollision procedure (including SELECT, RATS, and PPS). page 37/116 ST25R3911B Application information Figure 21. ISO14443A states for PCD and PICC PICC states PCD states Power off (no field) Standby Idle (field ON) Poll for PICC with REQA Receive ATQA Ready Perform bit frame anticollision loop Active Check SAK Increase Cascade level UID not complete UID complete and PICC compliant with ISO 14443-4 ISO 14443-4 ISO 14443-4 Setting up the ST25R3911B for ISO 14443A anticollision To set up the ST25R3911B for the ISO14443A anticollision follow the steps indicated below. 1. The Initiator operation mode of ST25R3911B must be set up for ISO 14443A in the Mode definition register (default is already for ISO14443A). 2. The Tx and Rx bit rates must be set to default (106 kbps) in the Bit rate definition register. 3. Set the antcl bit in the ISO14443A and NFC 106kb/s settings register. This needs to be set before sending the REQA (or WUPA). As a result, if a collision occurs in the ATQA or during anticollision procedure, the ST25R3911B does not trigger a framing error. Note: This bit must be set to one for REQA, WUPA and ANTOCOLLISION commands, for other commands it has to be zero. 4. Review and set a value for Mask receive timer register lower than the Frame delay time, as required by the ISO14443A, and set the No-response timer register 1 and Section 1.3.17 No-response timer register 2 according to the requirements. This is typically larger than the FDT. Note: The ST25R3911B offers the resolution of n/2 (64/fc - half steps) compared to n (128/fc) as mentioned in ISO 14443A so that the receiver can be unmasked n/2 steps before the actual transmission from the PICC. DS11793 - Rev 7 page 38/116 ST25R3911B Application information 5. According to ISO 14443A the FDT must be 1236/fc if last transmitted bit is 1, or 1172/fc if last transmitted bit is 0. Figure 22 shows an example of how MRT and NRT timers are set for a given FDT. Figure 22. Selection of MRT and NRT for a given FDT FDT PCD to PICC PICC to PCD t MRT < FDT – 64/fc NRE > FDT + 64/fc 6. 7. 8. The receiver and transmitter operation options related to operation mode must be defined. This is done automatically by sending the direct command Analog preset. If different options are required apart from those defined by Analog preset, they must be additionally set by writing the appropriate registers. Set rx_en and tx_en in the Operation control register. RFID protocols usually require that the reader field is turned on for a while before sending the first command (5 ms for ISO14443). General purpose timer can be used to count this time. The reply from PICC for the REQA, WUPA, and replies within anticollision sequence before SAK do not contain CRC. In this case the no_CRC_rx bit in the Auxiliary definition register must be set to 1 (receive without CRC) before sending these commands. REQA and WUPA Sending these two commands is simple since they are implemented as direct commands (Transmit REQA and Transmit WUPA). The end of transmission of these commands is signaled to microcontroller by an interrupt - IRQ due to end of transmission). After the transmission is executed, the ST25R3911B receiver automatically starts to observe the RFI inputs to detect a transponder after the expiration of the Mask Receive timer. As a response to REQA (or WUPA) all the PICC in the field respond simultaneously with an ATQA. A collision can occur in this state if there are PICC with different UID size or has the bit frame anticollision bits set differently. Hence it is important to set the antcl bit to 1. If there is any IRQ (except I_nre) that ST25R3911B signals, the microcontroller must consider as a valid presence of tag and must proceed with the anticollision procedure. If more than one PICC is expected in the field, the following algorithm must be used to select multiple tags: 1. Send REQA, if there is any answer continue 2. Perform anticollision, and select one PICC 3. Send HLTA to move the selected PICC to the HALT state 4. Go to step 1, and repeat this procedure until all the PICCs are in HALT state and all the UIDs have been extracted. Anticollision procedure After receiving the ATQA from the tags in the field, the next step is to execute the anticollision procedure to resolve the IDs of the tags. The procedure mainly uses the ANTICOLLISION and SELECT commands, which consist of: • Select code SEL (1 byte) • Number of valid bits NVB (1 byte) • 0 to 40 data bits of UID CLn according to the value of NVB The ANTICOLLISION command uses bit oriented anticollision frame (it does not use CRC). In this case the transmit needs to be done with direct command Transmit without CRC and for the receive, the no_CRC_rx bit in the Auxiliary definition register must be set to 1. The final SELECT command and its response SAK contains a CRC, so the transmit needs to be done with command Transmit with CRC and before sending this command the configuration bit no_CRC_rx bit in the Auxiliary definition register must be set back to 0. DS11793 - Rev 7 page 39/116 ST25R3911B Application information If there is more than one PICC in the field, the collision will occur when the tags reply to the ANTICOLLISION command during anticollision, when the PICCs reply back with their UID. This collision can occur after a complete byte (Full byte scenario) or it can occur within a byte (Split byte scenario). The antcl bit in ISO14443A and NFC 106kb/s settings register must be set during this procedure too. As a result, the ST25R3911B will not trigger a Framing Error. This bit is also responsible for correct timing of anticollision and correct parity extraction. Note: It must only be set before sending an anticollision frame, REQA or WUPA. This bit must not be used in any other commands. Figure 23 shows how to implement the anticollision with ST25R3911B. Since SPI is byte oriented, in case of Split byte scenario, the invalid MSB bits must be ignored when reading out the FIFO for the received data. Similarly, 0s must be concatenated as MSB bits to complete a byte for the Transmit (which will then be ignored based on register 0x1E). Figure 23. Flowchart for ISO14443A anticollision with ST25R3911B SELn=0x93 for n=1 for 4 bytes UID Cascade level n (n =1) SELn=0x95 for n=2 for 7 bytes UID SELn=0x97 for n=3 for 10 bytes UID 1) Fill FIFO with SELn + NVB (0x20) 2) Set registers: Number of transmitted bytes register 1 = 0x00 Number of transmitted bytes register 2 = 0x10 1) Send command Transmit without CRC 2) Expected interrupts: I_txe I_col (if collision occurs) I_rxs I_rxe FIFO is filled in with PICC response Read FIFO for the valid data from the selected PICC No I_col occured? Yes PICC sends complete UID Set 1) Read Collision Display Register to identify the bit position where the collision occurred 2) Read FIFO for the response from PICC - no_CRC_rx = 0 - antcl = 0 Set - no_CRC_rx = 1 - antcl = 1 Send SELECT: fill FIFO with SELn + NVB(0x70) + UID CLn 1) Fill FIFO with part 1 of bit anticollision frame: SELn + NVB (available from valid tag response) + received valid data +1 or 0 for the bit where the collision occurred 1) Send command Transmit with CRC 2) Expected nterrupts: I_txe I_rxe FIFO is filled in with SAK Enter Cascade level n+1 DS11793 - Rev 7 No UID complete? 2) Set registers: mention the number of received full bytes and split bits + 1 in: Number of transmitted bytes register 1 Number of full bytes Number of transmitted bytes register 2 FIFO is filled in with PICC response Yes End anticollision with RATS page 40/116 ST25R3911B Application information 1.2.18 FeliCa™ reader mode The general recommendation from Section 1.2.17 Reader operation is valid for FeliCa™ reader mode as well. Both 212 and 424 kb/s bit rates are supported, they are same in both directions (reader to tag and tag to reader). Modulation reader to tag is AM. In FeliCa™ mode the FeliCa™ frame format (see Table 14) is supported. Table 14. FeliCa™ frame format Preamble Sync Length Payload 48 data bits, 2 bytes Length byte (value= payload length + 1), all logical 0 (B2h, 4Dh) the length range is from 2 to 255 Payload CRC 2 bytes FeliCa™ transmission In order to transmit FeliCa™ frame only the Payload data is put in the FIFO. The number of Payload bytes is defined in the Number of transmitted bytes register 1 and Number of transmitted bytes register 2. Preamble length is defined by bits f_p1 and f_p0 in the ISO14443B and FeliCa settings register, default value is 48 bits, but other options are possible. Transmission is triggered by sending direct command Transmit with CRC. The first preamble is sent, followed by the SYNC and Length bytes. Then Payload stored in FIFO is sent, and the transmission is terminated by two CRC bytes calculated by the ST25R3911B. The length byte is calculated from ‘number of transmitted bytes’. The following equation is used: length = payload length + 1 = number of transmitted bytes +1 FeliCa™ reception At the end of the transmission, the ST25R3911B logic starts analyzing the receiver output to detect the Preamble of FeliCa™ tag response. Once the Preamble (followed by the two SYNC bytes) is detected, the Length byte and Payload data are inserted in the FIFO. The CRC bytes are internally checked. 1.2.19 NFCIP-1 operation The ST25R3911B supports all NFCIP-1 initiator modes and active communication target modes. All NFCIP-1 bit rates (106, 212 and 424 kbit/s) are supported. For stable AP2P operation, the junction temperature must be kept below 75 °C to ensure reliable peer detection (trg threshold), and rfe threshold must be set to 800 mV. NFCIP-1 passive communication initiator NFCIP-1 passive communication is equivalent to reader (PCD) to tag (PICC) communication where initiator acts as a reader and the target acts as tag. The only difference is that: in the case of NFCIP-1 passive communication, the initiator performs the Initial RF collision avoidance procedure at the beginning of communication. In order to act as NFCIP-1 passive communication initiator, the ST25R3911B must be configured according to Table 15. Table 15. Operation mode/bit rate setting for NFCIP-1 passive communication NFCIP-1 bit rate (kb/s) 106 212 424 Operation mode setting ISO14443A FeliCa™ Bit rate Bit rate Comments for Tx (kb/s) for Rx (kb/s) fc/128 (~106) fc/128 (~106) fc/64 (~212) - fc/32 (~424) - In FeliCa mode, the data rate is the same in both directions. The initial set-up of the Operation control register before the start of communication is the same as in the case of reader to tag communication. The efd_o bit must be evaluated first to ensure no external field is present. DS11793 - Rev 7 page 41/116 ST25R3911B Application information After the guard time has elapsed, the communication is the same as the ISO14443A (for 106 kb/s) or FeliCa™ (for 242 and 424 kb/s) reader communication. If the presence of the external field is detected, the field cannot be turned on. Support of NFCIP-1 transport frame format Figure 24 shows the transport frame according to NFCIP-1. Figure 24. Transport frame format according to NFCIP-1 Transport data field 106 kbps SB LEN CMD0 CMD1 Byte 0 Byte 1 Byte 2 ... Byte n E1 ... Byte n E2 Transport data field 212 kbps 424 kbps PA SB LEN CMD0 CMD1 Byte 0 Byte 1 Byte 2 Transport frame for bit rate 212 and 424 kb/s bit rate has the same format as communication frame used during Initialization and SDD. This format is also used in the FeliCa™ protocol (see also Section 1.2.18 FeliCa™ reader mode). In the case of 106 kb/s the SB (Start byte at F0h) and LEN (length byte) are only used in the Transport frame. Transport frame support for NFCIP-1 communication at 106 kb/s is enabled by setting nfc_f0 bit in the ISO14443A and NFC 106kb/s settings register. Once this bit is set and ISO 14443A mode with bit rate 106 kb/s is configured, the ST25R3911B behaves as indicated in the next subsections. Transmission To transmit a Transport frame, only the Transport data must be inserted in FIFO. The number of Transport data bytes is defined in the Number of transmitted bytes register 1 and Number of transmitted bytes register 2. Transmission is triggered by sending direct command Transmit with CRC. First Start byte with value F0h followed by Length byte are sent. Then Transport data stored in FIFO is sent, and the transmission is terminated by two CRC bytes (E1 in Figure 24) that are calculated by the ST25R3911B. Length byte is calculated from ‘number of transmitted bytes’. The following equation is used: length = Transport data length + 1 = number of transmitted bytes +1 Reception After transmission is done, the ST25R3911B logic starts to parse the receiver output to detect the start of tag reply. Once the start of communication sequence is detected the first byte (Start byte with value F0h) is checked the Length byte and Transport data bytes are put in the FIFO. CRC bytes are internally checked. In case the Start byte is not equal to F0h the following data bytes are still put in FIFO, additionally a soft framing error IRQ is set to indicate the Start byte error. NFCIP-1 active communication Initiator During NFCIP-1 active communication, both initiator and target switch on its field during transmission and switch off its field during reception. In order to operate as NFCIP-1 active communication initiator the ST25R3911B has to be configured according to Table 16 (bit targ in Mode definition register has to be 0): DS11793 - Rev 7 page 42/116 ST25R3911B Application information Table 16. Operation mode/bit rate setting for NFCIP-1 active communication initiator NFCIP-1 bit rate (kb/s) Initiator operation mode setting 106 212 424 NFCIP-1 active communication Bit rate Bit rate for Tx (kb/s) for Rx (kb/s) fc/128 (~106) - fc/64 (~212) - fc/32 (~424) - Comments Data rate is the same in both directions for all NFCIP-1 communication. After selecting the NFCIP-1 active communication mode the receiver and transmitter have to be configured properly. This configuration can be done automatically by sending direct command Analog preset (see Analog preset). During NFCIP-1 active communication the RF collision avoidance and switching on the field is performed using NFC field ON commands (see NFC field ON commands), while the sending of message is performed using Transmit commands as in the case of reader communication. Alternatively the Response RF collision avoidance sequence is started automatically when the switching off of target field is detected in case the bit nfc_ar in the Mode definition register. When NFCIP-1 mode is activated the External field detector is automatically enabled by setting bit en_fd in the Auxiliary display register. The Peer detection threshold is used to detect target field. During execution of ‘NFC field ON’ commands, the collision avoidance threshold is used. Initial set-up of the Operation control register before the start of communication is the same as in case of reader to tag communication with the exception that the transmitter is not enabled by setting the tx_en bit. The tx_en bit and therefore switching on of the transmitter is controlled by NFC field ON commands. Switching off the field is performed automatically after a message has been sent. The General purpose and no-response timer control register is used to define the time during which the field stays switched on after a message has been transmitted. In order to receive the NFCIP-1 active reply only the AM demodulation channel is used. Due to this the receiver AM channel has to be enabled. The preset done by Analog preset command enables only the AM demodulation channel, while PM channel is disabled to save current. In NFCIP-1 active communication the NFCIP-1Transport frame format (see Figure 24) is always used. Due to this the ISO14443A and NFC 106kb/s settings register bit nfc_f0 is set by Analog preset command (see Support of NFCIP-1 transport frame format). NFCIP-1 active communication sequence when bit nfc_ar in the Mode definition register is set (automatic Response RF collision avoidance sequence). During this sequence bits nfc_n1 and nfc_n0 of the Auxiliary definition register have to be 0 to produce Response collision avoidance sequence with n=0: 1. The direct command NFC initial field ON is sent. If no collision was detected during RF collision avoidance the field is switched on and an IRQ with I_cat flag set is sent to controller after TIRFG. 2. 3. 4. 5. 6. 7. DS11793 - Rev 7 The message, prepared as in case of reader to tag communication, is transmitted using Transmit command. After the message is sent the field is switched off. The time between the end of the message and switching off the field is defined by the General purpose timer (the General purpose timer IRQ may be masked since controller does not need this information). After switching off its field the ST25R3911B starts the No-response timer and observes the External field detector output to detect the switching on of the target field. If the target field is not detected before No-response timer timeout, an IRQ due No-response timer expire is sent. When target field is detected an IRQ with I_eon flag set is sent to controller and Mask receive timer is started. After the Mask receive timer expires the receiver output starts to be observed to detect start of the target response. The reception process goes on as in case of reader to tag communication. When the External field detector detects that the target has switched off its field, it sends an IRQ with I_eof flag set to the controller, and in case bit nfc_ar is set automatically activates the sequence of direct command NFC Response field ON. In case no collision is detected during RF collision avoidance the field is switched on and an IRQ with I_cat flag set is sent to controller after TARFG. Sequence loops through point 2. In case the last initiator command is sent in next sequence (DLS_REQ in case of NFCIP-1 protocol) the bit nfc_ar in the Mode definition register has to be put to 0 to avoid switching on the initiator field after the target has switched of its field. page 43/116 ST25R3911B Application information NFCIP-1 active communication target The ST25R3911B target mode is activated by setting bit targ in the Mode definition register to 1. When target mode is activated the External field detector is automatically enabled by setting bit en_fd in the Auxiliary definition register. When bit targ is set and all bits of the Operation control register are set to 0, the ST25R3911B is in low power Initial NFC target mode. In this mode the External field detector with Peer detection threshold is enabled. There are two different NFC target modes implemented (defined by mode bits of the Mode definition register): the bit rate detection mode and normal mode. In the bit rate detection mode the framing logic performs automatic detection of the initiator data rate and writes it in the NFCIP bit rate detection display register. In the normal mode it is supposed that the data rate defined in the Bit rate definition register is used. After selecting the NFCIP-1 active target mode the receiver and transmitter have to be configured properly. Configuration is the same as in case of NFCIP-1 active initiator mode. This configuration can be done automatically by sending direct command Analog preset (see Analog preset). NFCIP-1 active communication sequence when bit nfc_ar in the Mode definition register is set (automatic Response RF collision avoidance sequence). During this sequence bits nfc_n1 and nfc_n0 of the Auxiliary definition register have to be 0 to produce Response collision avoidance with n=0. The following sequence assumes that the ST25R3911B is in the low power Initial NFC target mode with the bit rate detection mode selected. Bit nfc_ar in the Mode definition register is set (automatic Response RF collision avoidance sequence). When the initiator field is detected the following sequence is executed: 1. An IRQ with I_eon flag set is sent to the controller. 2. The controller turns on the oscillator, regulator and receiver. Mask receive timer is started by sending direct command Start mask receive timer. After the Mask receive timer expires the receiver output starts to be observed to detect start of the initiator message. 3. Once the start of initiator message is detected, an IRQ due to start of receive is sent, the framing logic switches on a module that automatically recognizes the bit rate of signal sent by the initiator. Once the bit rate is recognized, an IRQ with I_nfct flag set is sent, and the bit rate is automatically loaded in the NFCIP bit rate detection display register. Detection of bit rate is also a condition that automatic Response RF collision avoidance sequence is enabled). The received message is decoded and put into the FIFO, IRQ is sent as after any received message. 4. The controller sends direct command Go to normal NFC mode, to copy the content of the NFCIP bit rate detection display register to the Bit rate definition register and to change the NFCIP-1 target mode to normal (the command Go to normal mode and reading of received data can be chained). Since the Tx modulation type depends on bit rate, the Tx modulation type also has to be correctly set at this point. 5. When the External field detector detects that the target has switched off its field, it sends an IRQ with I_eof flag set to the controller, and in case bit nfc_ar is set automatically activates the sequence of direct command NFC Response field ON. Bits nfc_n1 and nfc_n0 of the Auxiliary definition register are used to define number n of Response RF collision avoidance sequence. In case no collision is detected during RF collision avoidance the field is switched on and an IRQ with I_cat flag set is sent to controller after TARFG. 6. 7. The reply, prepared as in case of reader to tag communication is transmitted using Transmit command. After the message is sent the field is switched off. The time between the end of the message and switching off the field is defined in the General purpose timer (the General purpose timer IRQ may be masked since the controller does not need this information). From this point on the communication with initiator loops through the following sequence (during this sequence bits nfc_n1 and nfc_n0 of the Auxiliary definition register have to be 0 to produce Response RF collision avoidance with n=0): 1. After switching off its field the ST25R3911B starts the No-Response timer and observes the External field detector output to detect the switching on of the initiator field. In case the initiator field is not detected before No-Response timer timeout, an IRQ due No-Response timer expire is sent. 2. When initiator field is detected an IRQ with I_eon flag set is sent to controller and Mask receive timer is started. After the Mask receive timer expires the receiver output starts to be observed to detect start of the initiator response. The reception process goes on as in case of reader to tag communication. DS11793 - Rev 7 page 44/116 ST25R3911B Application information 3. When the External field detector detects that the target has switched off its field, it sends an IRQ with I_eof flag set to the controller, and in case bit nfc_ar is set automatically activates the sequence of direct command NFC Response field ON. In case no collision is detected during RF collision avoidance the field is switched on and an IRQ with I_cat flag set is sent to controller after TARFG. 4. The reply that was prepared as in case of reader to tag communication is transmitted using the Transmit command After the message is sent the field is switched off. The time between the end of the message and switching off the field is defined in General purpose timer. In case a new command from the initiator is expected the General purpose timer IRQ may be masked as the controller does not need this information. In case a new command from Initiator is expected the sequence loops through point 1. In case the target reply was the last in a sequence (DLS_RES in case of NFCIP-1 protocol) a new command from initiator is not expected. At the moment the field is switched off, a General purpose timer IRQ is received and the ST25R3911B is put back in the low-power NFC target mode by deactivating the Operation control register. NFC mode is changed back to rate detection mode by writing the Mode definition register. 5. 6. 7. 1.2.20 AM modulation depth: definition and calibration The ST25R3911B transmitter supports OOK and AM modulation. The choice between OOK and AM modulation is done by writing bit tr_am in the Auxiliary definition register. AM modulation is preset by direct command Analog preset in case the following protocols are configured: • ISO14443B • • FeliCa™ NFCIP-1 212 and 424 kb/s The AM modulation depth can be automatically adjusted by setting the AM modulation depth control register and sending the direct command Calibrate modulation depth. There is also an alternative possibility where the command Calibrate modulation depth is not used and the modulated level is defined by writing the antenna driver RFO AM modulated level definition register. AM modulation depth definition using the direct command Calibrate modulation depth Before sending the direct command Calibrate modulation depth the AM modulation depth control register has to be configured in the following way: • Bit 7 (am_s) has to be set to 0 to choose definition by the command Calibrate modulation depth • Bits 6 to 1 (mod5 to mod0) define target AM modulation depth Definition of modulation depth using bits mod5 to mod0 The RFID standard documents usually define the AM modulation level in form of the modulation index. The modulation index is defined as (a - b) / (a + b), where a and b are, respectively, the amplitude of the non‑modulated carrier and of the modulated carrier. The modulation index specification is different for different standards. The ISO-14443B modulation index is typically 10% with allowed range from 8 to 14%, while range from 10 to 30% is defined in the ISO-15693, and 8 to 30% in the FeliCa™ and NFCIP-1 212 kb/s and 424 kb/s. The bits mod5 to mod0 are used to calculate the amplitude of the modulated level. The non‑modulated level that was before measured by the A/D converter and stored in an 8 bit register is divided by a binary number in the range from 1 to 1.98. Bits mod5 to mod0 define binary decimals of this number. DS11793 - Rev 7 page 45/116 ST25R3911B Application information Example In case of the modulation index 10% the ratio between the non‑modulated level (a) and the modulated level (b) is 1.2222, which, converted to binary and truncated to six decimals is 1.001110. So, in order to define the modulation index 10% the bits mod5 to mod0 have to be set to 001110. Table 17 shows the setting of the mod bits and the associated modulation indexes. Table 17. Setting mod bits Modulation Index (%) DS11793 - Rev 7 mod5 … mod0 Modulation Index (%) mod5 … mod0 0.0 000000 20.0 100000 0.8 000001 20.5 100001 1.5 000010 21.0 100010 2.3 000011 21.5 100011 3.0 000100 22.0 100100 3.8 000101 22.4 100101 4.5 000110 22.9 100110 5.2 000111 23.4 100111 5.9 001000 23.8 101000 6.6 001001 24.3 101001 7.2 001010 24.7 101010 7.9 001011 25.1 101011 8.6 001100 25.6 101100 9.2 001101 26.0 101101 9.9 001110 26.4 101110 10.5 001111 26.9 101111 11.1 010000 27.3 110000 11.7 010001 27.7 110001 12.3 010010 28.1 110010 12.9 010011 28.5 110011 13.5 010100 28.9 110100 14.1 010101 29.3 110101 14.7 010110 29.7 110110 15.2 010111 30.1 110111 15.8 011000 30.4 111000 16.3 011001 30.8 111001 16.9 011010 31.2 111010 17.4 011011 31.6 111011 17.9 011100 31.9 111100 18.5 011101 32.3 111101 19.0 011110 32.6 111110 19.5 011111 33.0 111111 page 46/116 ST25R3911B Application information Execution of direct command Calibrate modulation depth The modulation level is adjusted by increasing the RFO1 and RFO2 driver output resistance. The RFO drivers are composed of 8 binary weighted segments. Usually all these segments are turned on to define the normal, non‑modulated level, there is also a possibility to increase the output resistance of the non‑modulated state by writing the RFO normal level definition register. Before sending the direct command Calibrate modulation depth the oscillator and regulators have to be turned on. When the direct command Calibrate modulation depth is sent the following procedure is executed: 1. The transmitter is turned on, non‑modulated level is established. 2. The amplitude of the non‑modulated carrier level established on the inputs RFI1 and RFI2 is measured by the A/D converter and stored in the A/D converter output register. 3. Based on the measurement of the non‑modulated level and the target modulated level defined by the bits mod5 to mod0 the target modulated level is calculated. 4. The output driver strength is adjusted using a successive approximation algorithm until the field strength is as close as possible to the calculated target modulated level. 5. The result of the output driver strength adjustment is copied in the AM modulation depth display register. Content of this register is used to define the AM modulated level. Note: After the calibration procedure is finished, the content of the RFO normal level definition register must not be changed. The modifications of the content of this register change the non‑modulated amplitude and therefore the ratio between the modulated and non‑modulated level. In case the calibration of antenna resonant frequency in used, the command Calibrate antenna has to be run before AM modulation depth adjustment. AM modulation depth definition using the RFO AM Modulated Level Definition register When bit 7 (am_s) of the AM modulation depth control register is set to 1 the AM modulated level is controlled by writing the RFO normal level definition register. If the setting of the modulated level is already known it is not necessary to run the calibration procedure, the modulated level can be defined just by writing this register. It is also possible to implement calibration procedure through an external controller using the RFO normal level definition register and the direct command Measure amplitude. This procedure has to be used when the target modulation depth is deeper than 33%. The procedure is the following: 1. Write the non‑modulated level in the RFO normal level definition register (usually it is all 0 to have the lower possible output resistance). 2. Switch on the transmitter. 3. Send the direct command Measure amplitude. Read result from the A/D converter output register. 4. Calculate the target modulated level from the target modulation index and result of the previous point. 5. In the following iterations content of the RFO normal level definition register is modified, the command Measure amplitude executed and the result compared with the target modulated level as long as the result is not equal (or as close as possible) to the target modulated level. 6. At the end the content of the RFO normal level definition register that results in the target modulated level is written in the RFO AM modulated level definition register while the RFO normal level definition register is restored with the non‑modulated definition value. 1.2.21 Antenna tuning The ST25R3911B integrates the blocks needed to check and to adjust the antenna LC tank resonance frequency. The phase and amplitude detector block is used for resonance frequency checking and adjustment. In order to implement the antenna LC tank calibration tuning capacitors have to be connected between the two coil terminals to the pins TRIM1_3 to TRIM1_0 and TRIM2_3 to TRIM2_0. In case single driver is used only the pins TRIM1_3 to TRIM1_0 are used, pins TRIM2_3 to TRIM2_0 are left open. Figure 25 shows the connection of the trim capacitors for both single (left side) and differential (right side) driving for the simple case where the antenna LC tank is directly connected to RFO pins. The TRIMx_y pins contain the HVNMOS switching transistors to VSS. DS11793 - Rev 7 page 47/116 ST25R3911B Application information The on resistance of TRIM1_0 and TRIM2_0 switch transistors to be connected to LSB tuning capacitor is 50 Ω typ. at 3 V VSP_D, the on resistance of other pins is binary weighted (the on resistance of TRIM1_3 and TRIM2_3 is 6.25 Ω typ.) The breakdown voltage of the HVNMOS switch transistors is 25 V, putting a limit to the maximum peak to peak voltage on LC tank in case tuning is used. During tuning procedure the resonance frequency is adjusted by connecting some of the tuning capacitors to VSS and leaving others floating. The switches of the same binary weight are driven from the same source and are both on or off (the switches TRIM1_2 and TRIM2_2 are for example both either on or off). Antenna tuning can be automatically performed by sending direct command Calibrate antenna or by an algorithm implemented in external controller by performing phase and amplitude measurements and controlling the TRIM switches using Antenna calibration control register. Figure 25. Connection of tuning capacitors to the antenna LC tank TRIM1_0 TRIM1_0 TRIM1_1 TRIM1_1 TRIM1_2 TRIM1_2 TRIM1_3 TRIM1_3 RF01 RF01 RF02 RFI1 RF02 Antenna coil RFI1 RFI2 RFI2 TRIM2_3 TRIM2_3 TRIM2_2 TRIM2_2 TRIM2_1 TRIM2_1 TRIM2_0 TRIM2_0 Antenna coil Antenna tuning using calibrate antenna direct command In order to perform the antenna LC tank using direct command Calibrate antenna binary weighted tuning capacitors have to be connected between the two coil terminals to the pins TRIM1_3 to TRIM1_0 and TRIM2_3 to TRIM2_0. During automatic procedure, started by sending the direct command Calibrate antenna, the ST25R3911B finds the position of TRIM switches where the phase difference between the RFO output signal and RFI input signal is as close as possible to the target phase defined in the Antenna calibration target register. while achieving the highest possible amplitude. In case the antenna LC tank is directly connected to RFO pins (see Figure 25, where the cases of single and differential driving are reported, respectively on the left and on the right) there is 90° phase shift between signal on the RFO outputs and the voltage on the RFI inputs when antenna LC tank is in resonance. In case additional EMC filter is inserted between RFO outputs and antenna LC tank the phase shift in case of resonance depends on additional phase shift generated by EMC filter. During execution of the direct command Calibrate antenna the ST25R3911B runs several phase measurements and changes configuration of TRIMx_y pins in order to find the best possible setting. Due to this the format of the Antenna calibration target register is the same as the format of direct command Measure phase result. The TRIMx_y pin configuration that is the result of the direct command Calibrate antenna can be observed by reading the Antenna calibration target register. This register also contains an error flag that is set in case the tuning to target phase was not possible. After the execution of direct command Calibrate antenna the actual phase can be checked by sending direct command Measure phase. DS11793 - Rev 7 page 48/116 ST25R3911B Application information Antenna tuning using antenna calibration control register There is also a possibility to control the position of the TRIM switches by writing the Antenna calibration control register. When the bit trim_s of this register is set to 1 position of the trim switches is controlled by bits tre_3 to tre_0. Using this register and performing phase and amplitude measurements (using direct commands Measure phase and Measure amplitude) different tuning algorithms can be implemented in the external controller. 1.2.22 Stream mode and transparent mode Standard and custom 13.56 MHz RFID reader protocols not supported by the ST25R3911B framing can be implemented using the ST25R3911B AFE and framing implemented in the external microcontroller. Transparent mode After sending the direct command transparent mode the external microcontroller directly controls the transmission modulator and gets the receiver output (control logic becomes “transparent”). The transparent mode is entered on rising edge of signal /SS after sending the command transparent mode and is maintained as long as the signal /SS is kept high. Before sending the direct command transparent mode the transmitter and receiver have to be turned on, the AFE has to be configured properly. While the ST25R3911B is in the transparent mode, the AFE is controlled directly through the SPI: • Transmitter modulation is controlled by pin MOSI (high is modulator on) • Signal rx_on is controlled by pin SCLK (high enables RSSI and AGC) • Output of receiver AM demodulation chain (digitized sub‑carrier signal) is sent to pin MISO • Output of receiver PM demodulation chain (digitized sub‑carrier signal) is sent to pin IRQ By controlling the rx_on advanced receiver features like the RSSI and AGC can be used. The receiver channel selection bits are valid also in transparent mode, therefore it is possible to use only one of the two channel outputs. In case single channel is selected it is always multiplexed to MISO, while IRQ is kept low. Configuration bits related to the ISO mode, framing and FIFO are meaningless in transparent mode, while all other configuration bits are respected. Use of transparent mode to implement active peer to peer (NFC) communication The framing implemented in the ST25R3911B supports all active modes according to the NFCIP-1 specification (ISO/IEC 18092:2004). In case any amendments to this specification or some custom active NFC communication need to be implemented transparent mode can be used. There is no special NFC active communication transparent mode, controlling of the Tx modulation and the Rx is done as described above. The difference comparing to the reader transparent mode is that the emission of the carrier field must be enabled only during Tx. This is done by writing the Operation control register before and after Tx. Since with every SPI command the transparent mode is lost it has to be re-entered. In order to receive the reply in active NFC communication mode only the AM demodulation channel is used. Due to this the receiver AM channel has to be enabled, while PM can be disabled. Implementing active communication requires detection of external field. Setting the bit en_fd in the Auxiliary definition register enables the external field detector with peer detection hhreshold. When bit en_fd is selected and the ST25R3911B is in transparent mode, the external field detector output is multiplexed to pin IRQ. This enables detection of external target/initiator field and performing RF collision avoidance. In case timing of the NFC field ON command is correct for the NFC active protocol being implemented, these commands can be used in combination with the transparent mode. These commands are used to perform the RF collision avoidance, switching on the field and timing out the minimum time from switching on the field to start of transmitting the message. After getting the interrupt, the controller generates the message in the transparent mode. When bit en_fd is set and all bits of the Operation control register are set to 0 the ST25R3911B is in the low power NFC target mode (same as in case of setting of targ bit, (see NFCIP-1 active communication target). In this mode initiator field is detected. After getting an IRQ with I_eon flag set, the controller turns on the oscillator, regulator and receiver and performs reception in the transparent mode. DS11793 - Rev 7 page 49/116 ST25R3911B Application information MIFARE™ classic compatibility For communication with MIFARE™ classic compliant devices the bit6 and bit7 from the register 05h can be used to enable Type A custom frames. Alternatively, the stream mode of ST25R3911B can be used to send and receive MIFARE™ classic compliant or custom frames. Stream mode Stream mode can be used to implement protocols, where the low level framing needed for ISO14443 receive coding can be used and decoded information can be put in FIFO. The main advantage of this mode over the transparent mode is that timing is generated in the ST25R3911B therefore the external controller does not have to operate in real time. The stream mode is selected in the Mode definition register, the operating options are defined in the Stream mode definition register. Two different modes are supported for tag to reader communication (Sub‑carrier and BPSK Stream modes). General rule for Stream mode is that the first bit sent/received is put on the LSB position of the FIFO byte. After selecting the stream mode the receiver and transmitter have to be configured properly (Analog preset direct command does not apply for Stream mode). Sub-carrier stream mode This mode supports protocols where during the tag to reader communication the time periods with sub‑carrier signal are interchanged with time periods without modulation (like in the ISO14443A 106 kbit/s mode). In this mode the sub‑carrier frequency and number of sub‑carrier frequency periods in one reporting period is defined. Sub‑carrier frequency in the range from fc/64 (212 kHz) to fc/8 (1695 kHz) are supported. Supported number of sub‑carrier frequency periods in one reporting period range from two to eight. Start of receive interrupt is sent and the first data bit is put in FIFO after the first reporting time period with sub‑carrier is detected. One bit of FIFO data gives information about status of input signal during one reporting period. Logic 1 means that the sub‑carrier was detected during reporting period, while 0 means that no modulation was detected during reporting period. End of receive is reported when no sub‑carrier signal in more than eight reporting periods have been detected. Figure 26 shows an example for setting scf = 01b and scp = 10b. With this setting the sub‑carrier frequency is set to fc/32 (424 kHz) and the reporting period to four sub‑carrier periods (128/fc ~106 μs). Figure 26. Example of sub-carrier stream mode for scf = 01b and scp = 10b Data in FIFO Input signal 1 1 0 1 fc/32 fc/128 BPSK stream mode This mode supports protocols where during the tag to reader communication BPSK code is used (like in the ISO14443B mode). In this mode the sub‑carrier frequency and number of sub‑carrier frequency periods in one reporting period is defined. Sub‑carrier frequency in the range from fc/16 (848 kHz) to fc/4 (3390 kHz) are supported. Supported number of sub‑carrier frequency periods in one reporting period range from one to eight. Start of receive interrupt is sent and the first data bit is put in FIFO after the first reporting time period with sub‑carrier is detected. Logic 0 is used for the initially detected phase, while logic 1 indicates inverted phase comparing to the initial phase. DS11793 - Rev 7 page 50/116 ST25R3911B Registers End of receive is reported when the first reporting period without sub‑carrier is detected. Figure 27 shows an example for setting scf = 01b and scp = 01b. With this setting the sub‑carrier frequency is set to fc/8 (1695 kHz) and the reporting period to two sub‑carrier periods (16/fc ~1.18 μs). Figure 27. Example of BPSK stream mode for scf = 01b and scp = 10b Data in FIFO Input signal 0 0 1 0 fc/8 fc/16 Reader to tag communication in stream mode Reader to tag communication control is the same for both stream modes. Reader to tag coding is defined by data put in FIFO. The stx bits of Stream mode definition register define the Tx time period during which one bit of FIFO data define the status of transmitter. If the data bit is set to logic 0 there is no modulation, in case it is logic 1 the transmitted carrier signal is modulated according to current modulation type setting (AM or OOK). Transmission in stream mode is started by sending direct commands Transmit without CRC or Transmit with CRC. Figure 28 shows an example for setting stx = 000b. With this setting the Tx time period is defined to 128/fc (~9,44 μs). Figure 28. Example of Tx in stream mode for stx = 000b and OOK modulation Data in FIFO 0 0 1 0 Input signal fc/128 1.3 Registers The 6-bit register addresses below are defined in hexadecimal notation. The possible addresses range from 00h to 3Fh. There are two types of registers implemented in the ST25R3911B: • Configuration registers • Display registers The configuration registers are used to configure the ST25R3911B. They can be read and written (RW) through the SPI. The display registers are read only (R); they contain information about the ST25R3911B internal state. Registers are set to their default state at power-up and after sending direct command Set default. The exceptions are IO configuration register 1 , IO configuration register 2 and Operation control register. These registers are related to the hardware configuration and are reset to their default state only at power-up. DS11793 - Rev 7 page 51/116 ST25R3911B Registers Table 18. Registers map Address (hex) 00 01 Main function IO configuration IO configuration register 1 IO configuration register 2 Comment Set to default state only at power-up RW RW Set to default state only at power-up RW Mode definition register - RW 04 Bit rate definition register - RW 05 ISO14443A and NFC 106kb/s settings register - RW 06 ISO14443B settings register 1 - RW 07 ISO14443B and FeliCa settings register - RW 08 Stream mode definition register - RW Auxiliary definition register - RW 0A Receiver configuration register 1 - RW 0B Receiver configuration register 2 - RW 0C Receiver configuration register 3 - RW 0D Receiver configuration register 4 - RW 0E Mask receive timer register - RW 0F No-response timer register 1 - RW No-response timer register 2 - RW General purpose and no-response timer control register - RW 12 General purpose timer register 1 - RW 13 General purpose timer register 2 - RW 14 Main interrupt register - RW 15 Mask timer and NFC interrupt register - RW 16 Mask error and wake-up interrupt register - RW 17 Main interrupt register - R - R 02 03 09 Operation control and Mode definition Configuration 10 11 18 Timer definition Operation control register Interrupt and associated reporting Mask timer and NFC interrupt register 19 Error and wake-up interrupt register - R 1A FIFO status register 1 - R 1B FIFO status register 2 - R 1C Collision display register - R Number of transmitted bytes register 1 - RW Number of transmitted bytes register 2 - RW NFCIP bit rate detection display register - R A/D converter output register - R Antenna calibration control register - RW Antenna calibration target register - RW Antenna calibration display register - R 1D 1E Definition of transmitted bytes 1F NFCIP bit rate detection display 20 A/D converter output 21 22 Antenna calibration 23 DS11793 - Rev 7 Content 24 AM modulation depth and AM modulation depth control register - RW 25 Antenna driver AM modulation depth display register - R page 52/116 ST25R3911B Registers Address (hex) 26 AM modulation depth and 27 Antenna driver 29 External field detector threshold Content Comment RFO AM modulated level definition register - RW RFO normal level definition register - RW External field detector threshold register - RW Regulator voltage control register - RW Regulator and timer display register - R RSSI display register - R Gain reduction state register - R Capacitive sensor control register - RW Capacitive sensor display register - R Auxiliary display register - R 31 Wake-up timer control register - RW 32 Amplitude measurement configuration register - RW 33 Amplitude measurement reference register - RW 34 Amplitude measurement auto-averaging display register - R 35 Amplitude measurement display register - R 36 Phase measurement configuration register - RW Phase measurement reference register - RW 38 Phase measurement auto-averaging display register - R 39 Phase measurement display register - R 3A Capacitance measurement configuration register - RW 3B Capacitance measurement reference register - RW 3C Capacitance measurement auto-averaging display register - R 3D Capacitance measurement display register - R IC identity register - R 2A 2B 2C 2D 2E 2F 30 37 3F DS11793 - Rev 7 Main function Regulator Receiver State display Capacitive sensor Auxiliary display Wake-Up IC Identity page 53/116 ST25R3911B Registers 1.3.1 IO configuration register 1 Address: 00h Type: RW Table 19. IO configuration register 1 Bit Name Default 7 single 0 6 rfo2 0 5 fifo_lr 0 4 fifo_lt 0 3 osc 1 2 out_cl1 0 1 out_cl0 0 0 lf_clk_off 0 Comments(1) Function 1: Only one RFO driver will be used Choose between single and differential antenna driving 0: RFO1, RFI1 1: RFO2, RFI2 0: 64 Choose which output driver and which input will be used in case of single driving FIFO water level for receive 1: 80 0: 32 FIFO water level for transmit 1: 16 0: 13.56 MHz Xtal 1: 27.12 MHz Xtal out_cl1 out_cl0 MCU_CLK 0 0 3.39 MHz 0 1 6.78 MHz 1 0 13.56 MHz 1 1 disabled 1: No LF clock on MCU_CLK Selector for crystal oscillator Selection of clock frequency on MCU_CLK output in case Xtal oscillator is running. In case of “11” MCU_CLK output is permanently low. By default the 32 kHz LF clock is present on MCU_CLK output when Xtal oscillator is not running and the MCU_CLK output is not disabled. 1. Default setting takes place at power-up only. DS11793 - Rev 7 page 54/116 ST25R3911B Registers 1.3.2 IO configuration register 2 Address: 01h Type: RW Table 20. IO configuration register 2 Bit 7 Name sup3 V Default 0 Comments(1) Function 0: 5 V supply 1: 3.3 V supply 5 V supply, range: 4.1 V to 5.5 V 3.3 V supply, range: 2.4 V to 3.6 V min. 3.0 V for VHBR Used for low cost applications. When this bit is set: • At 3 V or 5 V supply VSP_D and VSP_A shall be shorted externally • At 3.3 V applications VSP_D can alternatively be supplied from VDD in case VSP_A is not more than 300 mV lower then VDD 6 vspd_off 0 1: Disable VSP_D regulator 5 - - Not used - 4 miso_pd2 0 1: Pull-down on MISO, when /SS is low and MISO is not driven by the ST25R3911B - 3 miso_pd1 0 1: Pull-down on MISO when /SS is high - 2 io_18 0 1: Increase MISO driving level in case of 1.8 V VDD_IO - 1 - - Not used - 0 slow_up 0 1: Slow ramp at Tx on ≥ 10 µs, 10% to 90%, for B 1. Default setting takes place at power-up only. DS11793 - Rev 7 page 55/116 ST25R3911B Registers 1.3.3 Operation control register Address: 02h Type: RW Table 21. Operation control register Bit Name Default Comments(1) Function 7 en 0 1: Enables oscillator and regulator (Ready mode) - 6 rx_en 0 1: Enables Rx operation - 5 rx_chn 0 0: Both, AM and PM, channels enabled In case only one Rx channel is enabled, selection is done by the Receiver Configuration register 1 bit ch_sel 4 rx_man 0 3 tx_en 0 1: Enables Tx operation This bit is automatically set by NFC Field ON commands and reset in NFC active communication modes after transmission is finished 2 wu 0 1: Enables Wake-up mode According to settings in Wake-Up Timer Control register 1 - - 0 - - 1: One channel enabled 0: Automatic channel selection 1: Manual channel selection Not used In case both Rx channels are enabled, it chooses the method of channel selection, manual selection is done by the Receiver Configuration register 1 bit ch_sel - 1. Default setting takes place at power-up only. DS11793 - Rev 7 page 56/116 ST25R3911B Registers 1.3.4 Mode definition register Address: 03h Type: RW Table 22. Mode definition register Bit Name Default 7 targ 0 6 om3 0 5 om2 0 4 om1 0 3 om0 1 2 - 0 1 - 0 0 nfc_ar 0 Comments(1) Function 0: Initiator - 1: Target Refer to Table 23 and Table 24 Selection of operation mode Different for initiator and target modes - Not used - 1: Automatic start Response RF Collision Avoidance sequence Automatically starts the Response RF Collision Avoidance if an external field off is detected 1. Default setting takes place at power-up and after set default command. Table 23. Initiator operation modes Comments(1) om3 om2 om1 om0 0 0 0 0 NFCIP-1 active communication 0 0 0 1 ISO14443A 0 0 1 0 ISO14443B 0 0 1 1 FeliCa™ 0 1 0 0 NFC Forum Type 1 Tag (Topaz) 1 1 1 0 Sub-carrier stream mode 1 1 1 1 BPSK stream mode Other combinations Not used 1. If a non supported operation mode is selected the Tx\Rx operation is disabled. Table 24. Target operation modes Comments(1) om3 om2 om1 om0 0 0 0 0 NFCIP-1 active communication, bit rate detection mode 0 0 0 1 NFCIP-1 active communication, normal mode Other combinations Not used 1. If a non supported operation mode is selected the Tx\Rx operation is disabled. DS11793 - Rev 7 page 57/116 ST25R3911B Registers 1.3.5 Bit rate definition register Address: 04h Type: RW Table 25. Bit rate definition register Bit Name Default 7 tx_rate3 0 6 tx_rate2 0 5 tx_rate1 0 4 tx_rate0 0 3 rx_rate3 0 2 rx_rate2 0 1 rx_rate1 0 0 rx_rate0 0 Comments(1)(2) Function Selects bit rate for Tx Refer to Table 26 Selects bit rate for Rx when the selected protocol allows different bit rates for Rx and Tx 1. Default setting takes place at power-up and after set default command. 2. Automatically loaded by direct command go to normal NFC mode. Table 26. Bit rate coding rate3 rate2 rate1 rate0 Bit rate (kbit/s) Comments(1) 0 0 0 0 fc/128 (~106) - 0 0 0 1 fc/64 (~212) - 0 0 1 0 fc/32 (~424) - 0 0 1 1 fc/16 (~848) - 0 1 0 0 fc/8 (~1695) 0 1 0 1 fc/4 (~3390) 0 1 1 0 fc/2 (~6780) Other combinations VHBR Tx is supported only for ISO14443B mode VHBR Rx is supported only for fc/4 - Not used 1. If a non supported bit rate is selected the Tx/Rx operation is disabled. DS11793 - Rev 7 page 58/116 ST25R3911B Registers 1.3.6 ISO14443A and NFC 106kb/s settings register Address: 05h Type: RW Table 27. ISO14443A and NFC 106kb/s settings register Bit Name Default Function Comments 7 no_tx_par (1) 0 1: No parity bit is generated during Tx Data stream is taken from FIFO, transmit has to be done using command Transmit Without CRC. 6 no_rx_par(1) 0 1: Receive without parity and CRC When set to 1 received bit stream is put in the FIFO, no parity and CRC detection is done, must be set to 0 when not in ISO14443A mode. 5 nfc_f0 0 1: Support of NFCIP-1 Transport frame format Add SB (F0) and LEN bytes during Tx and skip SB (F0) byte during Rx. 4 p_len3 0 3 p_len2 0 2 p_len1 0 Refer to Table 28 Modulation pulse width, defined in number of 13.56 MHz clock periods. 1 p_len0 0 0 antcl 0 1: ISO14443 anticollision frame Must be set to 1 when ISO14443A bit oriented anticollision frame is sent. 1. no_tx_par and no_rx_par are used to send and receive custom frames like Mifare™ Classic frames. Table 28. ISO14443A modulation pulse width p_len3 DS11793 - Rev 7 p_len2 p_len1 Pulse width in number of 1/fc for different bit rates p_len0 fc/128 fc/64 fc/32 fc/16 0 1 1 1 42 - - - 0 1 1 0 41 20 - - 0 1 0 1 40 21 - - 0 1 0 0 39 22 13 - 0 0 1 1 38 21 12 8 0 0 1 0 37 20 11 7 0 0 0 1 36 19 10 6 0 0 0 0 35 18 9 5 1 1 1 1 34 17 8 4 1 1 1 0 33 16 7 3 1 1 0 1 32 15 6 2 1 1 0 0 31 14 5 - 1 0 1 1 30 13 - - 1 0 1 0 29 12 - - 1 0 0 1 28 - - - 1 0 0 0 27 - - - page 59/116 ST25R3911B Registers 1.3.7 ISO14443B settings register 1 Address: 06h Type: RW Table 29. ISO14443B settings register 1 Bit Name Default 7 egt2 0 6 egt1 0 5 egt0 0 4 sof_0 0 3 sof_1 0 2 eof 0 1 half 0 0 rx_st_om 0 Comments(1) Function egt2 egt1 egt0 Number of etu 0 0 0 0 0 0 1 1 ... ... ... ... 1 1 0 6 1 1 1 6 0: 10 etu 1: 11 etu 0: 2 etu 1: 3 etu 0: 10 etu 1: 11 etu 0: SOF, and EOF defined by sof_0, sof_1, and eof bit 1: SOF 10.5, 2.5, EOF: 10.5 0: Start/stop bit must be present for Rx 1: Start/stop bit omission for Rx EGT defined in number of etu SOF, number of etu with logic 0 (10 or 11) SOF, number of etu with logic 1 (2 or 3) EOF, number of etu with logic 0 (10 or 11) Sets SOF and EOF settings in middle of specification SOF= fixed to 10 low - 2 high, EOF not defined, put in FIFO last full byte (2) 1. Default setting takes place at power-up and after set default command 2. Start/stop bit omission for Tx can be implemented by using Stream mode. DS11793 - Rev 7 page 60/116 ST25R3911B Registers 1.3.8 ISO14443B and FeliCa settings register Address: 07h Type: RW Table 30. ISO14443B and FeliCa settings register Bit Name Default Function Comments 7 tr1_1 0 6 tr1_0 0 5 no_sof 0 1: No SOF PICC to PCD 4 no_eof 0 1: No EOF PICC to PCD 3 eof_12 0 2 phc_th 0 1: Increased tolerance of phase change detection - 1 f_p1 00: 48 Refer to Table 31. Minimum TR1 codings According to ISO14443-3 chapter 7.10.3.3 Support of B’ According to ISO14443-3 chapter 7.10.3.3 0: PICC EOF 10 to 11 etu Support of B (1) 1: PICC EOF 10 to 12 etu 0 01: 64 0 f_p0 FeliCa preamble length (valid also for NFCIP-1 active communication bit rates 242 and 484 kb/s) 10: 80 0 - 11: 96 1. Detection of EOF requires larger tolerance range for bit rates with only one sub-carrier frequency period per bit (fc/16 and higher). Due to this it is not possible to distinguish between EOF with 11 and 12 etu and setting this bit has no impact on EOF detection. Table 31. Minimum TR1 codings tr1_1 DS11793 - Rev 7 Minimum TR1 for a PICC to PCD bit rate tr1_0 fc/128 >fc/128 0 0 80/fs 80/fs 0 1 64/fs 32/fs 1 0 Not used Not used 1 1 Not used Not used page 61/116 ST25R3911B Registers 1.3.9 Stream mode definition register Address: 08h Type: RW Table 32. Stream mode definition register Function Comments(1) - - Refer to Table 33 Sub-carrier frequency definition for Sub-carrier and BPSK stream mode Bit Name Default 7 0 6 scf1 0 5 scf0 0 scp1 scp0 4 scp1 0 3 scp0 0 2 stx2 0 1 stx1 0 0 stx0 Number of pulses 0 0 1 (BPSK only) 0 1 2 1 0 4 1 1 8 Number of sub-carrier pulses in report period for Sub-carrier and BPSK stream mode Definition of time period for Tx modulator control (for Sub-carrier and BPSK stream mode) Refer to Table 34 1. Default setting takes place at power-up only. Table 33. Sub-carrier frequency definition for Sub-Carrier and BPSK stream mode scf1 scf0 Sub-Carrier mode BPSK mode 0 0 fc/64 (212 kHz) fc/16 (848 kHz) 0 1 fc/32 (424 kHz) fc/8 (1695 kHz) 1 0 fc/16 (848 kHz) fc/4 (3390 kHz) 1 1 fc/8 (1695 kHz) Not used Table 34. Definition of time period for Stream Mode Tx modulator control DS11793 - Rev 7 stx2 stx1 stx0 Time period 0 0 0 fc/128 (106 kHz) 0 0 1 fc/64 (212 kHz) 0 1 0 fc/32 (424 kHz) 0 1 1 fc/16 (848 kHz) 1 0 0 fc/8 (1695 kHz) 1 0 1 fc/4 (3390 kHz) 1 1 0 fc/2 (6780 kHz) 1 1 1 Not used page 62/116 ST25R3911B Registers 1.3.10 Auxiliary definition register Address: 09h Type: RW Table 35. Auxiliary definition register Bit Name Default Comments(1) Function 7 no_crc_rx 0 1: Receive without CRC Valid for all protocols, for ISO14443A REQA, WUPA and anticollision receive without CRC is done automatically (2) 6 crc_2_fifo 0 1: Make CRC check, but put CRC bytes in FIFO and add them to number of receive bytes Needed for EMV compliance 5 tr_am 0 4 en_fd 0 1: Enable External Field Detector 3 ook_hr 0 1: Put RFO driver in tristate during OOK modulation Valid for all protocols using OOK modulation (also in transparent mode) 2 rx_tol 1 1: BPSK fc/32: more tolerant BPSK decoder for bit rate fc/32, ISO14443A fc/128, NFCIP-1 fc/128: more tolerant processing of first byte - 1 nfc_n1 0 0 nfc_n0 0 - Value of n for direct commands NFC Initial Field ON and NFC response field ON (0 ... 3) Set automatically by command Analog preset, can be modified by register write, has to be defined for transparent and bit stream mode Tx 0: OOK 1: AM External field detector with Peer detection threshold is activated. Preset for NFCIP-1 active communication mode 1. Default setting takes place at power-up and after set default command. 2. Receive without CRC is done automatically when REQA and WUPA commands are sent using direct commands Transmit REQA and Transmit WUPA, respectively, and in case anticollision is performed setting bit antcl. 1.3.11 Receiver configuration register 1 Address: 0Ah Type: RW Table 36. Receiver configuration register 1 Bit Name Default 0 Comments(1) Function 0: Enable AM channel 7 ch_sel 6 amd_sel 0 5 lp2 0 4 lp1 0 3 lp0 0 2 h200 0 First and third stage zero setting 1 h80 0 0 z12k 0 (see Table 1. First and third stage zero setting) In case only one Rx channel is enabled in the Operation Control register it defines which channel is enabled. 1: Enable PM channel In case both channels are enabled and manual channel selection is active, it defines which channel is used for receive framing. 0: Peak detector AM demodulator type select, 1: Mixer VHBR automatic preset to mixer Low pass control (see Table 2. Low pass control) For automatic and other recommended filter settings, refer to Table 3. Receiver filter selection and gain range. 1. Default setting takes place at power-up and after set default command. DS11793 - Rev 7 page 63/116 ST25R3911B Registers 1.3.12 Receiver configuration register 2 Address: 0Bh Type: RW Table 37. Receiver configuration register 2 Bit Name Default Comments(1) Function 7 rx_lp 0 6 lf_op 0 5 lf_en 0 1: LF signal on receiver input - 4 agc_en 1 1: AGC is enabled - 3 agc_m 1 2 agc_alg 0 1 sqm_dyn 1 0 pmix_cl 0 1: Low power receiver operation 0: Differential LF operation 1: LF input split (RFI1 to AM channel, RFI2 to PM channel) 0: AGC operates on first eight sub-carrier pulses 1: AGC operates during complete receive period 0: Algorithm with preset is used 1: Algorithm with reset is used 1: Automatic squelch activation after end of Tx 0: RFO 1: Internal signal - Algorithm with preset is recommended for protocols with short SOF (like ISO14443A fc/128) Squelch is started 18.88 s after end of Tx, and stopped when Mask Receive Timer expires PM demodulator mixer clock source, in single mode internal signal is always used 1. Default setting takes place at power-up and after set default command. DS11793 - Rev 7 page 64/116 ST25R3911B Registers 1.3.13 Receiver configuration register 3 Address: 0Ch (1st stage gain settings) Type: RW Table 38. Receiver configuration register 3 Bit 7 Name Default Comments(1) Function rg1_am2 1 6 rg1_am1 1 5 rg1_am0 0 4 rg1_pm2 1 0: Full gain Gain reduction/boost in first gain stage of AM channel. 1-6: Gain reduction 2.5 dB per step (15 dB total) 7: Boost +5.5 dB 0: Full gain Gain reduction/boost in first gain stage of PM channel. 1-6: Gain reduction 2.5 dB per step (15 dB total) 3 rg1_pm1 1 2 rg1_pm0 0 1 lim 0 1: Clip output of first and second stage 0 rg_nfc 0 Preset for NFCIP-1 active 1: Forces gain reduction in second and third gain stage to -6 dB and maximum comparator communication mode. After clearing this bit, receiver must be window restarted. 7: Boost +5.5 dB Signal clipped to 0.6 V, preset for NFCIP-1 active communication mode 1. Default setting takes place at power-up and after set default command. 1.3.14 Receiver configuration register 4 Address: 0Dh (second and third stage gain settings) Type: RW Table 39. Receiver configuration register 4 Bit Name Default 7 rg2_am3 0 6 rg2_am2 0 5 rg2_am1 0 4 rg2_am0 0 3 rg2_pm3 0 2 rg2_pm2 0 1 rg2_pm1 0 0 rg2_pm0 0 Comments(1)(2) Function AM channel: Gain reduction in second and third stage and digitizer PM channel: Gain reduction in second and third stage and digitizer Only values from 0h to Ah are used: • settings 1h to 4hreduce gain by increasing the digitizer window in 3dB steps • values from 5h to Ah additionally reduce the gain in second and third gain stage, always in 3 dB steps. Only values from 0h to Ah are used: • settings 1h to 4h reduce gain by increasing the digitizer window in 3dB steps • values from 5h to Ah additionally reduce the gain in second and third gain stage, always in 3 dB steps. 1. Default setting takes place at power-up and after set default command. 2. Sending of direct command reset Rx gain is necessary to load the value of this register into AGC, squelch, and RSSI. DS11793 - Rev 7 page 65/116 ST25R3911B Registers 1.3.15 Mask receive timer register Address: 0Eh Type: RW Table 40. Mask receive timer register Bit Name Default Function Comments(1)(2) 7 mrt7 0 6 mrt6 0 5 mrt5 0 4 mrt4 0 Timeout = mrt * 64/fc 3 mrt3 1 Timeout (0 ≤ mrt ≤ 4) = 4 * 64/fc (18.88 µs) For the case of ISO14443A 106 kbit/s the Mask Receive timer is defined according to PCD to PICC frame delay time definition, where bits mrt define the number of n/2 steps. 2 mrt2 0 1 mrt1 0 In NFCIP-1 bit rate detection mode one step is 512/fc (37.78 µs) Minimum mask receive time of 18.88 µs covers the transients in receiver after end of transmission. 0 mrt0 0 Defined in steps of 64/fc (4.72 µs). Range from 256/fc (~18.88 µs) to 16320/fc (~1.2 ms) Defines time after end of Tx during which receiver output is masked (ignored). 1. Default setting takes place at power-up and after set default command. 2. In NFCIP-1 bit rate detection mode, the clock of mask receive timer is additionally divided by eight (one count is 512/fc) to cover range ~9.6 ms. DS11793 - Rev 7 page 66/116 ST25R3911B Registers 1.3.16 No-response timer register 1 Address: 0Fh Type: RW Table 41. No-response timer register 1 Bit Name Default Comments(1) Function 7 nrt15 0 6 nrt14 0 5 nrt13 0 4 nrt12 0 Defined in steps of 64/fc (4.72 µs). 3 nrt11 0 Range from 0 to 309 ms 2 nrt10 0 1 nrt9 0 If bit nrt_step in Table 43 is set the step is changed to 4096/fc 0 nrt8 0 Defines timeout after end of Tx. If this timeout expires without detecting a response a No-response interrupt is sent. No-response timer definition In NFC mode the No-response timer is started only when external field is detected. In the NFCIP-1 active communication mode the MSB bits No-response timer is automatically started when the transmitter is turned off after the message has been sent All 0: No-response timer is not started. No-response timer is reset and restarted with Start No-response timer direct command. 1. Default setting takes place at power-up and after set default command. 1.3.17 No-response timer register 2 Address: 10h Type: RW Table 42. No-response timer register 2 Bit Name Default Function 7 nrt7 0 6 nrt6 0 5 nrt5 0 4 nrt4 0 No-Response timer definition 3 nrt3 0 LSB bits 2 nrt2 0 1 nrt1 0 0 nrt0 0 Comments(1) - 1. Default setting takes place at power-up and after set default command. DS11793 - Rev 7 page 67/116 ST25R3911B Registers 1.3.18 General purpose and no-response timer control register Address: 11h Type: RW Table 43. General purpose and no-response timer control register Bit Name Default Comments(1) Function 7 gptc2 0 6 gptc1 0 5 gptc0 0 4 - 0 - - 3 - 0 - - 2 - 0 - - 1 nrt_emv 0 1: EMV mode of No-Response timer - 0 nrt_step 0 - Defines the timer trigger source. - Refer to Table 44. - 0: 64/fc Selects the No-Response timer step. 1: 4096/fc 1. Default setting takes place at power-up and after set default command. Table 44. Timer trigger source DS11793 - Rev 7 gptc2 gptc1 gptc0 0 0 0 No trigger source, start only with direct command Start General Purpose Timer. 0 0 1 End of Rx (after EOF) 0 1 0 Start of Rx 0 1 1 End of Tx in NFC mode, when General Purpose Timer expires the field is switched off 1 0 0 1 0 1 1 1 0 1 1 1 Trigger source Not used page 68/116 ST25R3911B Registers 1.3.19 General purpose timer register 1 Address: 12h Type: RW Table 45. General purpose timer register 1 Bit Name Default 7 gpt15 - 6 gpt14 - 5 gpt13 - 4 gpt12 - 3 gpt11 - 2 gpt10 - 1 gpt9 - 0 gpt8 - Comments(1) Function General purpose timeout definition MSB bits Defined in steps of 8/fc (590 ns) - Range from 590 ns to 38,7 ms 1. Default setting takes place at power-up and after set default command. 1.3.20 General purpose timer register 2 Address: 13h Type: RW Table 46. General purpose timer register 2 Bit Name Default 7 gpt7 - 6 gpt6 - 5 gpt5 - 4 gpt4 - 3 gpt3 - 2 gpt2 - 1 gpt1 - 0 gpt0 - Comments(1) Function General purpose timeout definition LSB bits Defined in steps of 8/fc (590 ns) - Range from 590 ns to 38.7 ms 1. Default setting takes place at power-up and after set default command. DS11793 - Rev 7 page 69/116 ST25R3911B Registers 1.3.21 Mask main interrupt register Address: 14h Type: RW Table 47. Mask main interrupt register Bit Name Default Comments(1) Function 7 M_osc 0 1: Mask IRQ when oscillator frequency is stable - 6 M_wl 0 1: Mask IRQ due to FIFO water level - 5 M_rxs 0 1: Mask IRQ due to start of receive - 4 M_rxe 0 1: Mask IRQ due to end of receive - 3 M_txe 0 1: Mask IRQ due to end of transmission - 2 M_col 0 1: Mask IRQ due to bit collision - 1 - 0 0 - 0 - Not used - 1. Default setting takes place at power-up and after set default command. 1.3.22 Mask timer and NFC interrupt register Address: 15h Type: RW Table 48. Mask timer and NFC interrupt register Bit Name Default Comments(1) Function 7 M_dct 0 1: Mask IRQ due to termination of direct command - 6 M_nre 0 1: Mask IRQ due to No-Response Timer expire - 5 M_gpe 0 1: Mask IRQ due to general purpose timer expire - 4 M_eon 0 1: Mask IRQ due to detection of external field higher than Target activation level - 3 M_eof 0 1: Mask IRQ due to detection of external field drop below Target activation level - 2 M_cac 0 1: Mask IRQ due to detection of collision during RF Collision Avoidance - 1 M_cat 0 1: Mask IRQ after minimum guard time expire - 0 M_nfct 0 1: Mask IRQ when in target mode the initiator bit rate was recognized - 1. Default setting takes place at power-up and after set default command. DS11793 - Rev 7 page 70/116 ST25R3911B Registers 1.3.23 Mask error and wake-up interrupt register Address: 16h Type: RW Table 49. Mask error and wake-up interrupt register Bit Name Default Comments(1) Function 7 M_crc 0 1: Mask IRQ due to CRC error - 6 M_par 0 1: Mask IRQ due to parity error - 5 M_err2 0 1: Mask IRQ due to soft framing error - 4 M_err1 0 1: Mask IRQ due to hard framing error - 3 M_wt 0 1: Mask IRQ due to wake-up timer interrupt - 2 M_wam 0 1: Mask Wake-up IRQ due to amplitude measurement - 1 M_wph 0 1: Mask Wake-up IRQ due to phase measurement. - 0 M_wcap 0 1: Mask Wake-up IRQ due to capacitance measurement - 1. Default setting takes place at power-up and after set default command. 1.3.24 Main interrupt register Address: 17h Type: R Table 50. Main interrupt register Bit Name Default 7 I_osc - Comments(1)(2) Function IRQ when oscillator frequency is stable Set after oscillator is started by setting Operation Control register bit en. Set during receive, informing that FIFO is almost full and has to be read out. 6 I_wl - IRQ due to FIFO water level 5 I_rxs - IRQ due to start of receive - 4 I_rxe - IRQ due to end of receive - 3 I_txe - IRQ due to end of transmission - 2 I_col - IRQ due to bit collision - 1 I_tim - IRQ due to timer or NFC event Details in Timer and NFC Interrupt register 0 I_err - IRQ due to error and wake-up timer Details in Error and Wake-Up Interrupt register Set during transmit, informing that FIFO is almost empty and that additional data has to be sent. 1. Default setting takes place at power-up and after set default command. 2. After the reading of main interrupt register, the content is set to 0, except for bits 1 and 0, which are set to 0 after corresponding interrupt register is read. DS11793 - Rev 7 page 71/116 ST25R3911B Registers 1.3.25 Timer and NFC interrupt register Address: 18h Type: R Table 51. Timer and NFC Interrupt Register Bit Name Default Comments(1)(2) Function 7 I_dct - IRQ due to termination of direct command - 6 I_nre - IRQ due to No-Response Timer expire - 5 I_gpe - IRQ due to general purpose timer expire - 4 I_eon - IRQ due to detection of external field higher than Target activation level - 3 I_eof - IRQ due to detection of external field drop below Target activation level - 2 I_cac - IRQ due to detection of collision during RF Collision Avoidance An external field was detected during RF Collision Avoidance 1 I_cat - IRQ after minimum guard time expire An external field was not detected during RF Collision Avoidance, field was switched on, IRQ is sent after minimum guard time according to NFCIP-1 0 I_nfct - IRQ when in target mode the initiator bit rate was recognized - 1. Default setting takes place at power-up and after set default command. 2. After reading of main interrupt register, its content is set to 0. 1.3.26 Error and wake-up interrupt register Address: 19h Type: R Table 52. Error and wake-up interrupt register Comments(1)(2) Bit Name Default Function 7 I_crc - CRC error - 6 I_par - Parity error - 5 I_err2 - Soft framing error Framing error which does not result in corrupted Rx data 4 I_err1 - Hard framing error Framing error which results in corrupted Rx data 3 I_wt - Wake-up timer interrupt 2 I_wam - Wake-up interrupt due to amplitude measurement Result of amplitude measurement was Δam larger than reference 1 I_wph - Wake-up interrupt due to phase measurement. Result of phase measurement was Δpm larger than reference 0 I_wcap - Wake-up interrupt due to capacitance measurement Result of capacitance measurement was Δcm larger than reference Timeout after execution of Start wake-up timer command In case option with IRQ at every timeout is selected 1. Default setting takes place at power-up and after set default command. 2. After reading the main interrupt register, its content is set to 0. DS11793 - Rev 7 page 72/116 ST25R3911B Registers 1.3.27 FIFO status register 1 Address: 1Ah Type: R Table 53. FIFO status register 1 Bit Name Default 7 - - 6 fifo_b6 - 5 fifo_b5 - 4 fifo_b4 - 3 fifo_b3 - 2 fifo_b2 - 1 fifo_b1 - 0 fifo_b0 - Comments(1) Function - - Number of bytes (binary coded) in the FIFO which were not read out Valid range is from 0 (000 0000b) to 96 (110 0000b) 1. At power-up and after set default command content of this register is set to 0. 1.3.28 FIFO status register 2 Address: 1Bh Type: R Table 54. FIFO status register 2 Bit Name Default 7 - - 6 Comments(1)(2)(3) Function - - fifo_unf - 1: FIFO underflow Set when more bytes then actual content of FIFO were read 5 fifo_ovr - 1: FIFO overflow - 3 fifo_lb2 - 2 fifo_lb1 - Number of bits in the last FIFO byte if it was not complete (fifo_ncp=1) The received bits are stored in the LSB part of the last byte in the FIFO 1 fifo_lb0 - 0 np_lb 1: Parity bit is missing in last byte This is a framing error - 1. At power-up and after set default command content of this register is set to 0. 2. If FIFO is empty, the value of register FIFO status register 1 (0x1Ah) is 0x00, register bits fifo_ncp, fifo_lb2, fifo_lb1 and fifo_lb0 in register block 0x1Bh are cleared. 3. Correct procedure for FIFO read is to read both FIFO status register 1 and FIFO status register 1 and then read FIFO. Second register values need to be saved in MCU because bits fifo_ncp, fifo_lb, and np_lb are cleared automatically at readout. DS11793 - Rev 7 page 73/116 ST25R3911B Registers 1.3.29 Collision display register Address: 1Ch Type: R Table 55. Collision display register Bit Name Default 7 c_byte3 - 6 c_byte2 - 5 c_byte1 - 4 c_byte0 - 3 c_bit2 - 2 c_bit1 - 1 c_bit0 - 0 c_pb - Comments(1) Function Number of full bytes before the bit collision happened. The Collision Display register range covers ISO14443A anticollision command. In case collision (or framing error that is interpreted as collision) happens in a longer message, the Collision Display register is not set. Number of bits before the collision in the byte where the collision happened 1: Collision in parity bit This is an error, reported in case it is the first collision detected 1. At power-up and after Set Default command content of this register is set to 0. DS11793 - Rev 7 page 74/116 ST25R3911B Registers 1.3.30 Number of transmitted bytes register 1 Address: 1Dh Type: RW Table 56. Number of transmitted bytes register 1 Bit Name Function Comments(1) Number of full bytes to be transmitted in one command, MSB bits Maximum supported number of bytes is 8191 Default 7 ntx12 0 6 ntx11 0 5 ntx10 0 4 ntx9 0 3 ntx8 0 2 ntx7 0 1 ntx6 0 0 ntx5 0 1. Default setting takes place at power-up and after set default command. 1.3.31 Number of transmitted bytes register 2 Address: 1Eh Type: RW Table 57. Number of transmitted bytes register 2 Bit Name Default 7 ntx4 0 6 ntx3 0 5 ntx2 0 4 ntx1 0 3 ntx0 0 2 nbtx2 0 1 0 nbtx1 nbtx0 0 0 Comments(1)(2) Function Number of full bytes to be transmitted in one command, MSB Maximum supported number of bytes is 8191 bits Applicable for ISO14443A: Number of bits in the split byte 000 means that there is no split byte (all bytes all complete) Bit oriented anticollision frame in case last byte is split byte Tx is done without parity bit generation 1. Default setting takes place at power-up and after set default command. 2. If anctl bit is set while card is in idle state and nbtx is not 000, then i_par will be triggered during WUPA direct command is issued. DS11793 - Rev 7 page 75/116 ST25R3911B Registers 1.3.32 NFCIP bit rate detection display register Address: 1Fh Type: R Table 58. NFCIP bit rate detection display register Bit Name Default 7 nfc_rate3 - 6 nfc_rate2 - 5 nfc_rate1 - 4 nfc_rate0 - 3 - - 2 - - 1 - - 0 - - Comments(1) Function Refer to Table 26. Bit rate coding This register stores result of automatic bit rate detection in the NFCIP-1 active communication bit rate detection mode Not used - 1. At power-up and after Set Default command content of this register is set to 0. 1.3.33 A/D converter output register Address: 20h Type: R Table 59. A/D converter output register Bit Name Default 7 ad7 - 6 ad6 - 5 ad5 - 4 ad4 - 3 ad3 - 2 ad2 - 1 ad1 - 0 ad0 - Comments(1) Function Displays result of last A/D conversion. - 1. At power-up and after Set Default command content of this register is set to 0. DS11793 - Rev 7 page 76/116 ST25R3911B Registers 1.3.34 Antenna calibration control register Address: 21h Type: RW Table 60. Antenna calibration control register Bit Name Default 7 0: LC trim switches are defined by result of Calibrate antenna command, see Table 9 trim_s 0 Comments(1) Function Defines source of driving switches on TRIMx pins 1: LC trim switches are defined by bits tre_x written in this register 6 tre_3 0 MSB 5 tre_2 0 - 4 tre_1 0 - 3 tre_0 0 LSB 2 - 0 1 - 0 0 - 0 LC trim switches are defined by data written in this register in case trim_s=1. A bit set to 1 switch on transistor on TRIM1_x and TRIM2_x pin. - - 1. Default setting takes place at power-up and after Set Default command 1.3.35 Antenna calibration target register Address: 22h Type: RW Table 61. Antenna calibration target register Function Comments(1) Bit Name Default 7 act7 1 - 6 act6 0 - 5 act5 0 - 4 act4 0 3 act3 0 2 act2 0 - 1 act1 0 - 0 act0 0 - Define target phase for Calibrate antenna direct command, see Table 9 - 1. Default setting takes place at power-up and after Set Default command. DS11793 - Rev 7 page 77/116 ST25R3911B Registers 1.3.36 Antenna calibration display register Address: 23h Type: R Table 62. Antenna calibration display register Bit Name Default Comments(1) Function 7 tri_3 - MSB 6 tri_2 - - 5 tri_1 - - 4 tri_0 - LSB 3 tri_err - 2 - - 1 - - 0 - - This register stores result of Calibrate antenna command. LC trim switches are defined by data written in this register in case trim_s = 0. A bit set to 1 indicates that corresponding transistor on TRIM1_x and TRIM2_x pin is switched on. 1: Antenna calibration error Set when Calibrate antenna sequence has not been able to adjust resonance Not used - 1. At power-up and after Set Default command content of this register is set to 0. 1.3.37 AM modulation depth control register Address: 24h Type: RW Table 63. AM modulation depth control register Bit Name Default 7 am_s 0 Comments(1) Function 0: AM modulated level is defined by bits mod5 to mod0. Level is adjusted automatically by Calibrate modulation depth command, see Table 9. Direct commands - 1: AM modulated level is defined by bits dram7 to dram0. 6 mod5 0 MSB 5 mod4 0 - 4 mod3 0 - 3 mod2 0 - 2 mod1 0 - 1 mod0 0 LSB 0 - 0 - See Section 1.2.20 AM modulation depth: definition and calibration for details about AM modulation lavel definition. - 1. Default setting takes place at power-up and after Set Default command. DS11793 - Rev 7 page 78/116 ST25R3911B Registers 1.3.38 AM modulation depth display register Address: 25h Type: R Table 64. AM modulation depth display register Comments(1) Bit Name Default Function 7 md_7 - MSB 6 md_6 - - 5 md_5 - - 4 md_4 - - 3 md_3 - - 2 md_2 - - 1 md_1 - - 0 md_0 - LSB Displays the result of Calibrate modulation depth command. The antenna drivers are composed of 8 binary weighted segments. Bit md_x set to one indicates that this particular segment is disabled during AM modulated state. In case of error all 1 value is set. 1. At power-up and after Set default command content of this register is set to 0. DS11793 - Rev 7 page 79/116 ST25R3911B Registers 1.3.39 RFO AM modulated level definition register Address: 26h Type: RW Table 65. RFO AM modulated level definition register Comments(1) Bit Name Default Function 7 dram7 0 2 Ohm 6 dram6 0 4 Ohm 5 dram5 0 8 Ohm 4 dram4 0 16 Ohm 3 dram3 0 32 Ohm 2 dram2 0 64 Ohm 1 dram1 0 128 Ohm 0 dram0 0 256 Ohm Antenna drivers are composed of eight binary weighted segments. Setting a bit dram to 1 will disable corresponding segment during AM modulated state in case am_s bit is set to 1. 1. Default setting takes place at power-up and after Set default command. 1.3.40 RFO normal level definition register Address: 27h Type: RW Table 66. RFO normal level definition register Bit Name Default Function Comments(1) 7 droff7 0 2 Ohm 6 droff6 0 4 Ohm 5 droff5 0 8 Ohm 4 droff4 0 16 Ohm The antenna drivers are composed of eight binary weighted segments. Setting a droff bit to 1 disables the corresponding segment during normal unmodulated operation. 3 droff3 0 32 Ohm The TX drivers are made up of 8 segments, binary weighted from 2 to 256 Ohm (nominal). 2 droff2 0 64 Ohm 1 droff1 0 128 Ohm 0 droff0 0 256 Ohm As an example, setting this register to 0xC0 disables the 2 Ohm and 4 Ohm segments. 1. Default setting takes place at power-up and after Set default command. Applying the FFh value to the register 27h puts the drivers in tristate. DS11793 - Rev 7 page 80/116 ST25R3911B Registers 1.3.41 External field detector threshold register Address: 29h Type: RW Table 67. External field detector threshold register Default Comments(1) Bit Name Function 7 - 0 6 trg_l2 0 5 trg_l1 1 4 trg_l0 1 3 rfe_t3 0 2 rfe_t2 0 Collision avoidance threshold. 1 rfe_t1 1 Refer to Table 69. Collision avoidance threshold as seen on RFI1 input. 0 rfe_t0 1 Not used - Peer detection threshold. Refer to Table 68. Peer detection threshold as seen on RFI1 input. - - 1. Default setting takes place at power-up and after Set default command. Table 68. Peer detection threshold as seen on RFI1 input DS11793 - Rev 7 Target peer detection trg_I2 trg_I1 trg_I0 0 0 0 75 0 0 1 105 0 1 0 150 0 1 1 205 1 0 0 290 1 0 1 400 1 1 0 560 1 1 1 800 threshold voltage (mVpp on RFI1) page 81/116 ST25R3911B Registers Table 69. Collision avoidance threshold as seen on RFI1 input Typical Collision Avoidance rfe_3 rfe_2 rfe_1 rfe_0 0 0 0 0 75 0 0 0 1 105 0 0 1 0 150 0 0 1 1 205 0 1 0 0 290 0 1 0 1 400 0 1 1 0 560 0 1 1 1 800(1) 1 0 0 0 25 1 0 0 1 33 1 0 1 0 47 1 0 1 1 64 1 1 0 0 90 1 1 0 1 125 1 1 1 0 175 1 1 1 1 250 threshold voltage (mVpp on RFI1) 1. Recommended thresholds for NFCIP-1 active communication. 1.3.42 Regulator voltage control register Address: 2Ah Type: RW Table 70. Regulator voltage control register Bit Name Default 7 reg_s 0 6 rege_3 0 5 rege _2 0 4 rege _1 0 3 rege _0 0 2 mpsv1 0 0: Regulated voltages are defined by result of Adjust regulators command Defines mode of regulator voltage setting. 1: Regulated voltages are defined by rege_x bits written in this register External definition of regulated voltage. Refer to Table 72 for definition. mpsv0 0 - In 5 V mode VSP_D and VSP_A regulators are set to 3.4 V 00: VDD 01: VSP_A 1 Comments(1) Function 10: VSP_D Defines source of direct command Measure power supply. 11: VSP_RF 0 - 0 - - 1. Default setting takes place at power-up and after Set default command. DS11793 - Rev 7 page 82/116 ST25R3911B Registers 1.3.43 Regulator and timer display register Address: 2Bh Type: R Table 71. Regulator and timer display register Bit Name Default Comments(1) Function 7 reg_3 - 6 reg_2 - Actual regulated voltage setting. 5 reg_1 - Refer to Table 72. Regulated voltages for definition. 4 reg_0 - 3 - - - 2 gpt_on - 1: General purpose timer is running 1 nrt_on - 1: No-Response timer is running 0 mrt_on - 1: Mask receive timer is running - - 1. Default setting takes place at power-up and after Set default command. Table 72. Regulated voltages reg_3 reg_2 reg_1 reg_0 rege_3 rege_2 rege_1 rege_0 1 1 1 1 1 1 1 1 1 5 V mode 3.3 V mode 1 5.1 3.4 0 4.98 3.3 0 1 4.86 3.2 1 0 0 4.74 3.1 1 0 1 1 4.62 3.0 1 0 1 0 4.50 2.9 1 0 0 1 4.38 2.8 1 0 0 0 4.26 2.7 0 1 1 1 4.14 2.6 0 1 1 0 4.02 2.5 0 1 0 1 3.90 2.4 Other combinations DS11793 - Rev 7 Typical regulated voltage (V) Not used page 83/116 ST25R3911B Registers 1.3.44 RSSI display register Address: 2Ch Type: R Table 73. RSSI display register Bit Name Default 7 rssi_am_3 - 6 rssi_am_2 - 5 rssi_am_1 - 4 rssi_am_0 - 3 rssi_pm_3 - 2 rssi_pm_2 - 1 rssi_pm_1 - 0 rssi_pm_0 - Comments(1)(2) Function AM channel RSSI peak value. Refer to Table 74. RSSI for definition. Stores peak value of AM channel RSSI measurement. Automatically cleared at beginning of transponder message and with Clear RSSI command. PM channel RSSI peak value. Refer to Table 74. RSSI for definition. Stores peak value of PM channel RSSI measurement. Automatically cleared at beginning of transponder message and with Clear RSSI command. 1. At power-up and after Set default command content of this register is set to 0. 2. Bit 0x30[7] indicates which RSSI value is use in the logic for internal use. Table 74. RSSI DS11793 - Rev 7 rssi_3 rssi_2 rssi_1 rssi_0 Typical signal on RFI1 (mVrms) 0 0 0 0 ≤20 0 0 0 1 >20 0 0 1 0 >27 0 0 1 1 >37 0 1 0 0 >52 0 1 0 1 >72 0 1 1 0 >99 0 1 1 1 >136 1 0 0 0 >190 1 0 0 1 >262 1 0 1 0 >357 1 0 1 1 >500 1 1 0 0 >686 1 1 0 1 >950 1 1 1 0 1 1 1 1 >1150 page 84/116 ST25R3911B Registers 1.3.45 Gain reduction state register Address: 2Dh Type: R Table 75. Gain reduction state register Bit Name Comments(1) Default Function 7 gs_am_3 - MSB 6 gs_am_2 - - 5 gs_am_1 - - 4 gs_am_0 - LSB 3 gs_pm_3 - MSB 2 gs_pm_2 - - 1 gs_pm_1 - - 0 gs_pm_0 - LSB Actual gain reduction of second stage of AM channel (including register gain reduction, squelch and AGC) Actual gain reduction of second stage of PM channel (including register gain reduction, squelch and AGC) 1. At power-up and after Set default command content of this register is set to 0. 1.3.46 Capacitive sensor control register Address: 2Eh Type: RW Table 76. Capacitive sensor control register Bit Name Default Function 7 cs_mcal4 0 6 cs_mcal3 0 5 cs_mcal2 0 4 cs_mcal1 0 3 cs_mcal0 0 2 cs_g2 0 000: 2.8 V/pF 1 cs_g1 0 001: 6.5 V/pF Manual calibration value. All 0 value enables automatic calibration mode 010: 1.1 V/pF 0 cs_g0 0 100: 0.5 V/pF Comments(1) Binary weighted, step 0.1 pF, max 3.1 pF Capacitor sensor gain typical values 110: 0.35 V/pF Others: Not used 1. At power-up and after Set default command content of this register is set to 0. DS11793 - Rev 7 page 85/116 ST25R3911B Registers 1.3.47 Capacitive sensor display register Address: 2Fh Type: R Table 77. Capacitive sensor display register Bit Name Default 7 cs_cal4 - 6 cs_cal3 - 5 cs_cal2 - 4 cs_cal1 - 3 cs_cal0 - 2 cs_cal_end 1 0 Comments(1) Function Capacitive Sensor calibration value Binary weighted, step 0.1 pF, max 3.1 pF - 1: Calibration ended - cs_cal_err - 1: Calibration error - - - - - 1. At power-up and after Set default command content of this register is set to 0. 1.3.48 Auxiliary display register Address: 30h Type: R Table 78. Auxiliary display register Comments(1) Bit Name Default Function 7 a_cha - 6 efd_o - 1: External field detected External field detector output 5 tx_on - 1: Transmission is active - 4 osc_ok - 1: Xtal oscillation is stable Indication that Xtal oscillator is active and its output is stable 3 rx_on - 1: Receive coder is enabled - 2 rx_act - 1: Receive coder is receiving a message - 1 nfc_t - 0 en_ac - 0: AM 1: PM 1: External field detector is active in peer detection mode 1: External field detector is active in RF collision avoidance mode Currently selected channel - - 1. At power-up and after Set default command content of this register is set to 0. DS11793 - Rev 7 page 86/116 ST25R3911B Registers 1.3.49 Wake-up timer control register Address: 31h Type: RW Table 79. Wake-up timer control register Bit Name Default 7 wur 0 6 wut2 0 5 wut1 0 4 wut0 0 3 wto 2 1 Comments(1) Function 0: 100 ms Wake-up timer range 1: 10 ms Refer to Table 80. Typical wake-up time Wake-up timer timeout value 0 1: IRQ at every timeout - wam 0 1: At timeout perform amplitude measurement IRQ if difference larger than Δam wph 0 1: At timeout perform phase measurement IRQ if difference larger than Δpm 1. Default setting takes place at power-up and after Set default command. Table 80. Typical wake-up time DS11793 - Rev 7 wut2 wut1 wut0 100 ms range (wur=0) 10 ms range (wur=1) 0 0 0 100 ms 10 ms 0 0 1 200 ms 20 ms 0 1 0 300 ms 30 ms 0 1 1 400 ms 40 ms 1 0 0 500 ms 50 ms 1 0 1 600 ms 60 ms 1 1 0 700 ms 70 ms 1 1 1 800 ms 80 ms page 87/116 ST25R3911B Registers 1.3.50 Amplitude measurement configuration register Address: 32h Type: RW Table 81. Amplitude measurement configuration register Bit Name Default 7 am_d3 0 6 am_d2 0 5 am_d1 0 4 am_d0 0 3 am_aam 0 2 am_aew1 0 Comments(1) Function Definition of Δam (difference to reference that triggers interrupt) Include/exclude the measurement that causes IRQ (having difference > Δam to reference) in auto-averaging 0: Exclude the IRQ measurement 1: Include the IRQ measurement 00: 4 01: 8 1 am_aew2 0 - Define weight of last measurement result for auto-averaging 10: 16 11: 32 0: Use Amplitude measurement reference register 0 am_ae 0 1: Use amplitude measurement auto-averaging as reference Select reference value for amplitude measurement wake-up mode 1. Default setting takes place at power-up and after Set default command 1.3.51 Amplitude measurement reference register Address: 33h Type: RW Table 82. Amplitude measurement reference register Bit Name Default Comments(1) Function 7 am_ref7 0 - - 6 am_ref6 0 - - 5 am_ref5 0 - - 4 am_ref4 0 - - 3 am_ref3 0 - - 2 am_ref2 0 - - 1 am_ref1 0 - - 0 am_ref0 0 - - 1. Default setting takes place at power-up and after Set default command. DS11793 - Rev 7 page 88/116 ST25R3911B Registers 1.3.52 Amplitude measurement auto-averaging display register Address: 34h Type: R Table 83. Amplitude measurement auto-averaging display register Bit Name Default Function Comments(1) 7 amd_aad7 0 - - 6 amd_aad6 0 - - 5 amd_aad5 0 - - 4 amd_aad4 0 - - 3 amd_aad3 0 - - 2 amd_aad2 0 - - 1 amd_aad1 0 - - 0 amd_aad0 0 - - 1. At power-up and after Set default command content of this register is set to 0. 1.3.53 Amplitude measurement display register Address: 35h Type: R Table 84. Amplitude measurement display register Bit Name Default Function Comments(1) 7 am_amd7 0 - - 6 am_amd6 0 - - 5 am_amd5 0 - - 4 am_amd4 0 - - 3 am_amd3 0 - - 2 am_amd2 0 - - 1 am_amd1 0 - - 0 am_amd0 0 - - 1. At power-up and after Set default command content of this register is set to 0. DS11793 - Rev 7 page 89/116 ST25R3911B Registers 1.3.54 Phase measurement configuration register Address: 36h Type: RW Table 85. Phase measurement configuration register Bit Name Default 7 pm_d3 0 6 pm_d2 0 5 pm_d1 0 4 pm_d0 0 3 pm_aam 0 2 pm_aew1 0 Comments(1) Function Definition of Δpm (difference to reference that triggers interrupt) Include/exclude the measurement that causes IRQ (having difference > Δpm to reference) in auto-averaging 0: Exclude the IRQ measurement 1: Include the IRQ measurement 00: 4 01: 8 1 pm_aew0 0 - Define weight of last measurement result for auto-averaging 10: 16 11: 32 0: Use Phase measurement reference register 0 pm_ae 0 Select reference value for phase measurement Wake-up mode 1: Use phase measurement auto-averaging as reference 1. Default setting takes place at power-up and after Set default command 1.3.55 Phase measurement reference register Address: 37h Type: RW Table 86. Phase measurement reference register Bit Name Default Function Comments(1) 7 pm_ref7 0 - - 6 pm_ref6 0 - - 5 pm_ref5 0 - - 4 pm_ref4 0 - - 3 pm_ref3 0 - - 2 pm_ref2 0 - - 1 pm_ref1 0 - - 0 pm_ref0 0 - - 1. Default setting takes place at power-up and after Set default command. DS11793 - Rev 7 page 90/116 ST25R3911B Registers 1.3.56 Phase measurement auto-averaging display register Address: 38h Type: R Table 87. Phase measurement auto-averaging display register Bit Name Default Function Comments(1) 7 pm_aad7 0 - - 6 pm_aad6 0 - - 5 pm_aad5 0 - - 4 pm_aad4 0 - - 3 pm_aad3 0 - - 2 pm_aad2 0 - - 1 pm_aad1 0 - - 0 pm_aad0 0 - - 1. At power-up and after Set default command content of this register is set to 0. 1.3.57 Phase measurement display register Address: 39h Type: R Table 88. Phase measurement display register Bit Name Default Function Commentsx(1) 7 pm_amd7 0 0 - 6 pm_amd6 0 0 - 5 pm_amd5 0 0 - 4 pm_amd4 0 0 - 3 pm_amd3 0 0 - 2 pm_amd2 0 0 - 1 pm_amd1 0 0 - 0 pm_amd0 0 0 - 1. At power-up and after Set default command content of this register is set to 0. DS11793 - Rev 7 page 91/116 ST25R3911B Registers 1.3.58 Capacitance measurement configuration register Address: 3Ah Type: RW Table 89. Capacitance measurement configuration register Bit Name Default 7 cm_d3 0 6 cm_d2 0 5 cm_d1 0 4 cm_d0 0 3 cm_aam 0 2 cm_aew1 0 Comments(1) Function Definition of Δcm (difference to reference that triggers interrupt) Include/exclude the measurement that causes IRQ (having difference > Δcm to reference) in auto-averaging 0: Exclude the IRQ measurement 1: Include the IRQ measurement 00: 4 01: 8 1 cm_aew0 0 - Define weight of last measurement result for auto-averaging 10: 16 11: 32 0: Use Capacitance measurement reference register 0 cm_ae 0 1: Use capacitance measurement auto-averaging as reference Select reference value for capacitance measurement Wake-up mode 1. Default setting takes place at power-up and after Set default command. 1.3.59 Capacitance measurement reference register Address: 3Bh Type: RW Table 90. Capacitance measurement reference register Bit Name Default Function Comments(1) 7 cm_ref7 0 - - 6 cm_ref6 0 - - 5 cm_ref5 0 - - 4 cm_ref4 0 - - 3 cm_ref3 0 - - 2 cm_ref2 0 - - 1 cm_ref1 0 - - 0 cm_ref0 0 - - 1. Default setting takes place at power-up and after Set default command DS11793 - Rev 7 page 92/116 ST25R3911B Registers 1.3.60 Capacitance measurement auto-averaging display register Address: 3Ch Type: R Table 91. Capacitance measurement auto-averaging display register Bit Name Default Function Comments(1) 7 cm_aad7 0 - - 6 cm_aad6 0 - - 5 cm_aad5 0 - - 4 cm_aad4 0 - - 3 cm_aad3 0 - - 2 cm_aad2 0 - - 1 cm_aad1 0 - - 0 cm_aad0 0 - - 1. At power-up and after Set default command content of this register is set to 0. 1.3.61 Capacitance measurement display register Address: 3Dh Type: R Table 92. Capacitance measurement display register Bit Name Default Function Comments(1) 7 cm_amd7 0 - - 6 cm_amd6 0 - - 5 cm_amd_ 0 - - 4 cm_amd_ 0 - - 3 cm_amd3 0 - - 2 cm_amd2 0 - - 1 cm_amd1 0 - - 0 cm_amd0 0 - - 1. At power-up and after Set default command content of this register is set to 0. DS11793 - Rev 7 page 93/116 ST25R3911B Registers 1.3.62 IC identity register Address: 3Fh Type: R Table 93. IC identity register Bit Default Function 7 ic_type4 - 6 ic_type3 - 5 ic_type2 - 4 ic_type1 - 3 ic_type0 - 2 ic_rev2 - 010: silicon r3.1 1 ic_rev1 - 011: silicon r3.3 0 DS11793 - Rev 7 Name ic_rev0 - Code for ST25R3911B: 00001 100: silicon r4.0 Comments 5-bit IC type code 3-bit IC revision code 101: silicon r4.1 page 94/116 ST25R3911B Pinouts and pin description 2 Pinouts and pin description The ST25R3911B pin and pad assignments are described in Figure 29 . VDD_IO MOSI MISO MCU_CLK IRQ VSN_A CSI 32 1 SCLK /SS Figure 29. ST25R3911B QFN32 pinout 31 30 29 28 27 26 25 24 AGD CSO 2 23 RFI2 VSP_D 3 22 RFI1 XTO 4 21 VSS XTI 5 20 TRIM2_0 VSN_D 6 19 TRIM1_0 VSP_A 7 18 TRIM2_1 TRIM1_1 QFN32 33 Note: 9 10 11 12 13 14 15 17 16 RFO1 RFO2 VSN_RF TRIM1_3 TRIM2_3 TRIM1_2 TRIM2_2 8 VSP_RF VDD The above figure shows the package top view. Table 94. ST25R3911B pin definitions - QFN32 package Pin number Pin name Pin type 1 VDD_IO 2 CSO 3 VSP_D 4 XTO 5 XTI Analog input / Digital input Xtal oscillator input 6 VSN_D Supply pad Digital ground 7 VSP_A Analog output Analog supply regulator output 8 VDD Supply pad External positive supply 9 VSP_RF 10 RFO1 11 RFO2 12 VSN_RF 13 TRIM1_3 14 TRIM2_3 15 TRIM1_2 16 TRIM2_2 DS11793 - Rev 7 Supply pad Description Positive supply for peripheral communication Capacitor sensor output Analog output Digital supply regulator output Xtal oscillator output Supply regulator output for antenna drivers Analog output Antenna driver output Supply pad Ground of antenna drivers Analog I/O Input to trim antenna resonant circuit page 95/116 ST25R3911B Pinouts and pin description Pin number Pin name 17 TRIM1_1 18 TRIM2_1 19 TRIM1_0 20 TRIM2_0 21 VSS 22 RFI1 23 RFI2 24 Pin type Description Analog I/O Input to trim antenna resonant circuit Supply pad Ground, die substrate potential Analog input Receiver input AGD Analog I/O Analog reference voltage 25 CSI Analog input Capacitor sensor input 26 VSN_A Supply pad Analog ground 27 IRQ 28 MCU_CLK 29 MISO 30 MOSI 31 SCLK 32 /SS 33 VSS DS11793 - Rev 7 Digital output Digital output / tristate Interrupt request output Microcontroller clock output Serial Peripheral Interface data output Serial Peripheral Interface data input Digital input Serial Peripheral Interface clock Serial Peripheral Interface enable (active low) Supply Ground, die substrate potential, connected to VSS on PCB page 96/116 ST25R3911B Electrical characteristics 3 Electrical characteristics 3.1 Absolute maximum ratings Stresses beyond those listed Table 95, Table 96 and Table 97 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in Section 3.2 Operating conditions is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 95. Electrical parameters Symbol Parameter Min Max Unit Comments VDD DC supply voltage -0.5 6.0 V - VDD_IO DC_IO supply voltage -0.5 6.0 V - VINTRIM Input pin voltage TRIM pins -0.5 25.0 V - VIN Input pin voltage for peripheral communication pins -0.5 6.5 V - VINA Input voltage for analog pins -0.5 6.0 V - Iscr Input current (latch-up immunity) -100 100 mA Norm: JEDEC 78 Ioutmax Drive capability of output driver 0 600 mA - Table 96. Electrostatic discharge Symbol ESD Parameter Min Electrostatic discharge Max Unit ±2 kV ±500 V Comments Standard JS-001-2014 (Human body model) Standard JS-001-2014 (Human body model) Valid for TRIMx_x pins (pins 13 - 20) Table 97. Temperature ranges and storage conditions Symbol Parameter Tstrg Storage temperature Tbody Package body temperature Min Max Unit -55 125 - 260 °C °C Comments The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices.” The lead finish for Pb-free leaded packages is matte tin (100% Sn). RHNC MSL DS11793 - Rev 7 Relative Humidity non-condensing Moisture sensitivity level 5 85 3 % - - Represents a maximum floor life time of 168h. page 97/116 ST25R3911B Operating conditions 3.2 Operating conditions All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. All defined tolerances for external components in this specification need to be assured over the whole operating conditions range and over lifetime. Table 98. Operating conditions Symbol Parameter Min Max Unit VDD Positive supply voltage 2.4 5.5 V VDD_IO Peripheral communication supply voltage 1.65 5.5 V VSS Negative supply voltage 0 0 V - - 20 V - -40 125 °C - VINTRIM TJUN Input pin voltage TRIM pins Junction temperature VRFI_A RFI input amplitude 0.150 3 Vpp RFO Driver current 0 500 mA Comments In case power supply is lower than 2.6 V, PSSR cannot be improved using internal regulators VDD_IO (minimum regulated voltage is 2.4 V). Minimum RFI input signal definition is meant for NFC receive mode. In HF reader mode and NFC transmit mode the recommended signal level is 2.5 Vpp. - 3.3 DC/AC characteristics for digital inputs and outputs 3.3.1 CMOS inputs Valid for input pins \SS, MOSI, and SCLK. Table 99. CMOS inputs DS11793 - Rev 7 Symbol Parameter Min Max Unit VIH High level input voltage 0.7 * VDD_IO VDD_IO V VIL Low level input voltage VSS 0.3 * VDD_IO V ILEAK Input leakage current -1 1 µA page 98/116 ST25R3911B Electrical specifications 3.3.2 CMOS outputs Valid for output pins MISO, IRQ and MCU_CLK, io_18=0 (IO configuration register 2). Table 100. CMOS outputs 3.4 Symbol Parameter Conditions Min Typ Max Unit VOH High level output voltage 0.9 + VDD_IO - VDD_IO V VOL Low level output voltage 0 - 0.1 + VDD_IO V CL Capacitive load - 0 - 50 pF RO Output resistance - 0 250 550 Ω RPD Pull-down resistance pin MISO Pull-down can be enabled while MISO output is in tristate. The activation is controlled by register setting. 5 10 15 kΩ tSOURCE/SINK = 1mA, measured at VDDIO = 2.4V tSOURCE/SINK = 0.5mA, measured at VDDIO = 1.65V Electrical specifications VDD= 3.3 V, temperature 25 °C unless noted otherwise. 3.3 V supply mode, regulated voltages set to 3.4 V, 27.12 MHz Xtal connected to XTO and XTI. Table 101. Electrical specifications Symbol Parameter Min Typ Max Unit Comments Supply current in Power-down mode - 0.7 2 µA Register 00h set to 0Fh(no clock on MCU_CLK), register 01h set to 80h (3 V supply mode), register 02hset to 00h register 03hset to 08h, other registers in default state. INFCT Supply current in initial NFC Target mode - 3.5 7 µA Register 00hset to 0Fh (no clock on MCU_CLK), register 01h set to 80h (3 V supply mode), register 02hset to 00h register 03h set to 80h(enable NFC Target mode), other registers in default state. IWU Supply current in Wake-up mode - 3.6 8 µA Register 00h set to 0Fh (no clock on MCU_CLK), register 01h set to 80h (3 V supply mode), register 02h set to 04h (enable Wake-up mode), register 03hset to 08h, register 31h set to 08h (100 ms timeout, IRQ at every timeout), other registers in default state. IRD Supply current in Ready mode - 5.4 7.5 mA Register 00h set to 0Fh(no clock on MCU_CLK), register 01h set to C0h(3 V supply mode, disable VSP_D), register 02h set to 80h, register 03h set to 08h, other registers in default state, short VSP_A and VSP_D. mA Register 00h set to 0Fh, register 01h set to C0h (3 V supply mode, disable VSP_D), register 02h set to E8h (one channel Rx, enable Tx), register 03h set to 08h, register 0Bh set to 00h, register 27h set to FFh (all RFO segments disabled), other registers in default state, short VSP_A and VSP_D. mA Register 00h set to 0Fh, register 01h set to C0h (3 V supply mode, disable VSP_D), register 02h set to E8h(one channel Rx, enable Tx), register 03h set to 08, register 0Bh set to 80 (low power mode), register 27h set to FFh (all RFO segments disabled), other registers in default state, short VSP_A and VSP_D. IPD IAL Supply current, all active - 8.7 12.5 Supply current, ILP all active, - 6.8 10 low power receiver mode IRFO = 10 mA RRFO RFO1 and RFO2 driver output resistance DS11793 - Rev 7 The following measurement procedure that cancels resistance of measurement setup is used: 0.25 0.6 1.8 Ω • all driver segments are switched on, resistance is measured • all driver segments except the MSB segment are switched on, resistance is measured • difference between the two measurements is the resistance of MSB segment page 99/116 ST25R3911B Electrical specifications Symbol Parameter Min Typ Max Unit Comments • Zload Load impedance across 8 10 50 Ω RFO1 and RFO2 VRFI RFI input sensitivity - 0.5 - RRFI RFI input resistance 5 10 15 VPOR Power on Reset voltage VAGD VREG resistance of MSB segment multiplied by two is the value of RRFO. Using a load impedance lower than the minimum value can result in permanent damage to the device. mVrms fSUB = 848 kHz, AM channel with peak detector input stage selected. kΩ - 1.31 1.5 1.75 V - AGD voltage 1.4 1.6 V Register 00h set to 0Fh (no clock on MCU_CLK), register 01h set to C0h (3 V supply mode, disable VSP_D), register 02h set to 80h, register 03h set to 08h, other registers in default state, short VSP_A and VSP_D. Regulated voltage 2.80 3.0 3.32 V Manual regulator mode, regulated voltage set to 3.0 V, measured on pin VSP_RF: register 00h set to 0Fh, register 01h set to 80h (3 V supply mode), register 02h set to E8h (one channel Rx, enable Tx), register 2Ah set to D8h. 1.5 13.56 MHz or 27.12 MHz crystal TOSC Oscillator start-up time DS11793 - Rev 7 0.65 0.7 10 ms ESRMAX= 150 Ω max, load capacitance according to crystal specification, IRQ is issued once the oscillator frequency is stable. This parameter changes with ESRMAX parameter. page 100/116 ST25R3911B Typical operating characteristics 3.5 Typical operating characteristics 3.5.1 Thermal resistance and maximum power dissipation Figure 30. TCASE vs. power with different copper area at Tamb = 25°C 100 90 0x0mm 10x10mm 20x20mm 30x30mm 40x40mm 50x50mm 60x60mm 70x70mm Tcase (°C) 80 70 60 50 40 30 20 0 0.5 1 1.5 2 2.5 Power dissipation (W) Figure 31. RthCA vs. copper area 100 Rth_CA (K/W) 90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 2 Area (cm ) DS11793 - Rev 7 page 101/116 ST25R3911B Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK® is an ST trademark. 4.1 QFN32 package information The ST25R3911B is available in a 32-pin QFN (5 x 5 mm) package (see Figure 32). Dimensions are detailed in Table 102. Figure 32. QFN32 - Outline 1. DS11793 - Rev 7 Dimensioning and tolerances conform to ASME Y14.5M-1994. page 102/116 ST25R3911B QFN32 package information 2. 3. 4. 5. Coplanarity applies to the exposed heat slug as well as to the terminal. Radius on terminal is optional. N is the total number of terminals. This drawing is subject to change without notice. Table 102. QFN32 - Mechanical data Symbol Min. Typ. Max. A 0.80 0.90 1.00 A1 0 0.02 0.05 A2 - 0.65 1.00 A3 - 0.20 - L 0.35 0.40 0.45 q 0º - 14º b 0.18 0.25 0.30 D - 5.00 (with BSC) - E - 5.00 (with BSC) - e - 0.50 (with BSC) - D2 3.40 3.50 3.60 E2 3.40 3.50 3.60 D1 - 4.75 (with BSC) - E1 - 4.75 (with BSC) - aaa - 0.15 - bbb - 0.10 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - fff - 0.10 - (as specified in Figure 32) N (1) 32 1. Total number of terminals. Note: DS11793 - Rev 7 All dimensions are in mm. All angles are in degrees. page 103/116 ST25R3911B VFQFPN32 package information 4.2 VFQFPN32 package information VFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch, very thin fine pitch quad flat no lead package. Figure 33. VFQFPN32 - Outline B 32 24 A Pin #1 ID 1 Pin #1 ID Chamfer 0.35 E2 E D2 8 S1 L 16 e 32x bbb M C A B BOTTOM VIEW 0.10 Ref. A3 SIDE VIEW Detail A 32x eee C Terminal thickness 0.05 Ref. C Detail A SLP1 PLATED AREA A1 TOP VIEW ccc C Terminal length L D A b SIDE VIEW 1. 2. Drawing is not to scale. Coplanarity applies to the exposed heat slug as well as to the terminal. Table 103. VFQFPN32 - Mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.800 0.900 1.000 0.0315 0.0354 0.0394 A1 0 - 0.050 0 - 0.0020 A3 0.200 0.0079 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 b 0.180 0.250 0.300 0.0071 0.0098 0.0118 D D2 5.000 3.400 E E2 3.500 0.1969 3.600 0.1339 5.000 3.400 3.500 0.1378 0.1417 0.1969 3.600 0.1339 0.1378 e 0.500 0.0197 S1 0.350 0.0138 0.1417 bbb - 0.100 - - 0.0039 - ccc - 0.100 - - 0.0039 - eee - 0.080 - - 0.0031 - 1. Values in inches are converted from mm and rounded to four decimal digits. DS11793 - Rev 7 page 104/116 ST25R3911B VFQFPN32 package information Figure 34. VFQFPN32 - Recommended footprint 3.50 0.80 0.25 0.50 3.50 DS11793 - Rev 7 page 105/116 ST25R3911B Ordering information 5 Ordering information Table 104. Ordering information scheme Example: ST25 R 39 11B- A QF T Device type ST25 = NFC/RFID tag and reader Product type R = Reader Frequency range 39 = HF products Product features 11B = High performance HF reader / NFC initiator with 1.4 W supporting VHBR and AAT Temperature range A = - 40 to 125 °C Package/Packaging QF = 32-pin QFN (5x5 mm) QW = 32-pin VFQFPN (5x5mm) with wetable flank SW = Sorted wafer Tape and reel T = 4000 pcs/reel B = Wafer box Note: For a list of available options (speed, package, etc.) or for further information on any aspect of this device, contact your nearest ST sales office. Note: Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS11793 - Rev 7 page 106/116 ST25R3911B Revision history Table 105. Document revision history Date Revision 26-Sep-2016 1 Changes Initial release. Updated document title, and image on cover page Updated Features and Description. Updated Section 1 Functional overview, Section 1.1.1 Transmitter, Section 1.1.2 Receiver, Section 1.1.3 Phase and amplitude detector, Section 1.1.5 Capacitive sensor, Section 1.1.7 Quartz crystal oscillator, Section 1.1.8 Power supply regulators, Section 1.1.9 POR and Bias, Section 1.1.10 RC oscillator and Wake-Up timer, Section 1.2.2 Transmitter, Demodulation stage, Filtering and gain stages, Digitizing stage, Squelch, Receiver in NFCIP-1 active communication mode, Section 1.2.5 Wake-up mode, Auto-averaging, Section 1.2.8 A/D converter, Section 1.2.12 Communication with an external microcontroller and Section 4.1 QFN32 package information. Added Section 1.2.13 Direct commands. 16-Dec-2016 2 Updated Table 11. Register preset bits, Table 18. Registers map. Table 19. IO configuration register 1, Table 22. Mode definition register, Table 29. ISO14443B settings register 1, Table 35. Auxiliary definition register, Table 37. Receiver configuration register 2, Table 38. Receiver configuration register 3, Table 43. General purpose and no-response timer control register, Table 47. Mask main interrupt register, Table 48. Mask timer and NFC interrupt register, Table 49. Mask error and wake-up interrupt register, Table 52. Error and wake-up interrupt register, Table 54. FIFO status register 2, Table 55. Collision display register, Table 57. Number of transmitted bytes register 2, Table 60. Antenna calibration control register, Table 65. RFO AM modulated level definition register, Table 66. RFO normal level definition register, Table 67. External field detector threshold register, Table 70. Regulator voltage control register, Table 71. Regulator and timer display register, Table 73. RSSI display register, Table 78. Auxiliary display register, Table 81. Amplitude measurement configuration register, Table 85. Phase measurement configuration register, Table 93. IC identity register, Table 96. Electrostatic discharge, Table 101. Electrical specifications and Section 5 Ordering information. Removed footnote from Table 31. Minimum TR1 codings. Updated Figure 4. Receiver block diagramin Section 1.2.3 Receiver, figure Figure 8. ST25R3911B power supply, Section 1.2.12 Communication with an external microcontroller, Section 1.2.13 Direct commands, Section 1.2.21 Antenna tuning and Figure 32. QFN32 - Outline. Updated Features, Description, Clear, FIFO water level and FIFO status registers, and Section 1.2.15 Test access and Section 1.3.62 IC identity register. 19-Jul-2017 3 Updated , Table 6. SPI operation modes, Table 9. Direct commands, Table 17. Setting mod bits, Table 54. FIFO status register 2 and its footnotes, Table 74. RSSI and Table 93. IC identity register and Table 101. Electrical specifications. Updated Table 2. Low pass controlTable 6. SPI operation modes, Table 9. Direct commands and Table 27. ISO14443A and NFC 106kb/s settings register 26-Feb-2018 4 Updated Example and Table 93. IC identity register. Updated title and note of Section 5 Ordering information. Updated: 28-Jan-2019 5 • Table 4. Recommended blocking capacitor values Added: • Table 14. FeliCa™ frame format Updated: 16-Apr-2020 6 • Added: • DS11793 - Rev 7 Figure 2. Minimum configuration with single sided antenna driving (including EMC filter) Section 4.2 VFQFPN32 package information page 107/116 ST25R3911B Date Revision Changes Updated: 26-Apr-2022 DS11793 - Rev 7 7 • Figure 2. Minimum configuration with single sided antenna driving (including EMC filter) • Section 1.2.10 External field detector • Section 1.2.19 NFCIP-1 operation • Section 1.2.21 Antenna tuning • Table 26. Bit rate coding • Section 1.3.41 External field detector threshold register • Section 4.2 VFQFPN32 package information • Section 5 Ordering information page 108/116 ST25R3911B Contents Contents 1 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 1.2 DS11793 - Rev 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.3 Phase and amplitude detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.4 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.5 Capacitive sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.6 External field detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.7 Quartz crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.8 Power supply regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.9 POR and Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.10 RC oscillator and Wake-Up timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.11 ISO-14443 and NFCIP-1 framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.12 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.13 Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.14 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2.4 Capacitive sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.5 Wake-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2.6 Quartz crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.7 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.8 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2.9 Phase and amplitude detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2.10 External field detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.2.11 Power supply system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2.12 Communication with an external microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.2.13 Direct commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.2.14 Start timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 page 109/116 ST25R3911B Contents 1.3 DS11793 - Rev 7 1.2.15 Test access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.2.16 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.2.17 Reader operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.2.18 FeliCa™ reader mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.2.19 NFCIP-1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.2.20 AM modulation depth: definition and calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.2.21 Antenna tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1.2.22 Stream mode and transparent mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1.3.1 IO configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 1.3.2 IO configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.3.3 Operation control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 1.3.4 Mode definition register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 1.3.5 Bit rate definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 1.3.6 ISO14443A and NFC 106kb/s settings register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 1.3.7 ISO14443B settings register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.3.8 ISO14443B and FeliCa settings register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.3.9 Stream mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.3.10 Auxiliary definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1.3.11 Receiver configuration register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1.3.12 Receiver configuration register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.3.13 Receiver configuration register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1.3.14 Receiver configuration register 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1.3.15 Mask receive timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.3.16 No-response timer register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.3.17 No-response timer register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.3.18 General purpose and no-response timer control register. . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.3.19 General purpose timer register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.3.20 General purpose timer register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.3.21 Mask main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 1.3.22 Mask timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 1.3.23 Mask error and wake-up interrupt register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1.3.24 Main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 page 110/116 ST25R3911B Contents DS11793 - Rev 7 1.3.25 Timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.3.26 Error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.3.27 FIFO status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 1.3.28 FIFO status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 1.3.29 Collision display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.3.30 Number of transmitted bytes register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.3.31 Number of transmitted bytes register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.3.32 NFCIP bit rate detection display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.3.33 A/D converter output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.3.34 Antenna calibration control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.3.35 Antenna calibration target register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.3.36 Antenna calibration display register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 1.3.37 AM modulation depth control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 1.3.38 AM modulation depth display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 1.3.39 RFO AM modulated level definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1.3.40 RFO normal level definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1.3.41 External field detector threshold register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 1.3.42 Regulator voltage control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 1.3.43 Regulator and timer display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 1.3.44 RSSI display register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 1.3.45 Gain reduction state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 1.3.46 Capacitive sensor control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 1.3.47 Capacitive sensor display register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1.3.48 Auxiliary display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1.3.49 Wake-up timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.3.50 Amplitude measurement configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 1.3.51 Amplitude measurement reference register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 1.3.52 Amplitude measurement auto-averaging display register . . . . . . . . . . . . . . . . . . . . . . . . . 89 1.3.53 Amplitude measurement display register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 1.3.54 Phase measurement configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 1.3.55 Phase measurement reference register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 1.3.56 Phase measurement auto-averaging display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 1.3.57 Phase measurement display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 page 111/116 ST25R3911B Contents 1.3.58 Capacitance measurement configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 1.3.59 Capacitance measurement reference register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 1.3.60 Capacitance measurement auto-averaging display register . . . . . . . . . . . . . . . . . . . . . . . 93 1.3.61 Capacitance measurement display register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 1.3.62 IC identity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2 Pinouts and pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 3.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.3 DC/AC characteristics for digital inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.3.1 CMOS inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.3.2 CMOS outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.5.1 4 5 Thermal resistance and maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.1 QFN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.2 VFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 DS11793 - Rev 7 page 112/116 ST25R3911B List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. First and third stage zero setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low pass control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver filter selection and gain range. . . . . . . . . . . . . . . . . . . . . . . . . Recommended blocking capacitor values . . . . . . . . . . . . . . . . . . . . . . . Serial data interface (4-wire interface) signal lines . . . . . . . . . . . . . . . . . SPI operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing parameters of NFC field ON commands . . . . . . . . . . . . . . . . . . . Register preset bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog test and observation register. . . . . . . . . . . . . . . . . . . . . . . . . . . Test access register - Tana signal selection of CSI and CSO pins. . . . . . . FeliCa™ frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation mode/bit rate setting for NFCIP-1 passive communication . . . . Operation mode/bit rate setting for NFCIP-1 active communication initiator Setting mod bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IO configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IO configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initiator operation modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Target operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit rate definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit rate coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISO14443A and NFC 106kb/s settings register . . . . . . . . . . . . . . . . . . . ISO14443A modulation pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . ISO14443B settings register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISO14443B and FeliCa settings register . . . . . . . . . . . . . . . . . . . . . . . . Minimum TR1 codings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stream mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub-carrier frequency definition for Sub-Carrier and BPSK stream mode. . Definition of time period for Stream Mode Tx modulator control . . . . . . . . Auxiliary definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver configuration register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask receive timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No-response timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No-response timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General purpose and no-response timer control register . . . . . . . . . . . . . Timer trigger source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General purpose timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General purpose timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . Mask error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . Main interrupt register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer and NFC Interrupt Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . DS11793 - Rev 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 9 . 9 18 19 20 24 25 27 30 31 35 36 41 41 43 46 52 54 55 56 57 57 57 58 58 59 59 60 61 61 62 62 62 63 63 64 65 65 66 67 67 68 68 69 69 70 70 71 71 72 72 page 113/116 ST25R3911B List of tables Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. FIFO status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . FIFO status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . Collision display register . . . . . . . . . . . . . . . . . . . . . . . . . Number of transmitted bytes register 1 . . . . . . . . . . . . . . . Number of transmitted bytes register 2 . . . . . . . . . . . . . . . NFCIP bit rate detection display register . . . . . . . . . . . . . . A/D converter output register . . . . . . . . . . . . . . . . . . . . . . Antenna calibration control register . . . . . . . . . . . . . . . . . Antenna calibration target register . . . . . . . . . . . . . . . . . . Antenna calibration display register . . . . . . . . . . . . . . . . . AM modulation depth control register . . . . . . . . . . . . . . . . AM modulation depth display register . . . . . . . . . . . . . . . . RFO AM modulated level definition register . . . . . . . . . . . . RFO normal level definition register . . . . . . . . . . . . . . . . . External field detector threshold register . . . . . . . . . . . . . . Peer detection threshold as seen on RFI1 input . . . . . . . . . Collision avoidance threshold as seen on RFI1 input . . . . . Regulator voltage control register. . . . . . . . . . . . . . . . . . . Regulator and timer display register . . . . . . . . . . . . . . . . . Regulated voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . RSSI display register . . . . . . . . . . . . . . . . . . . . . . . . . . . RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain reduction state register . . . . . . . . . . . . . . . . . . . . . . Capacitive sensor control register . . . . . . . . . . . . . . . . . . Capacitive sensor display register . . . . . . . . . . . . . . . . . . Auxiliary display register . . . . . . . . . . . . . . . . . . . . . . . . . Wake-up timer control register . . . . . . . . . . . . . . . . . . . . . Typical wake-up time . . . . . . . . . . . . . . . . . . . . . . . . . . . Amplitude measurement configuration register. . . . . . . . . . Amplitude measurement reference register . . . . . . . . . . . . Amplitude measurement auto-averaging display register. . . Amplitude measurement display register . . . . . . . . . . . . . . Phase measurement configuration register . . . . . . . . . . . . Phase measurement reference register . . . . . . . . . . . . . . Phase measurement auto-averaging display register . . . . . Phase measurement display register . . . . . . . . . . . . . . . . Capacitance measurement configuration register . . . . . . . . Capacitance measurement reference register . . . . . . . . . . Capacitance measurement auto-averaging display register . Capacitance measurement display register . . . . . . . . . . . . IC identity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST25R3911B pin definitions - QFN32 package . . . . . . . . . Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature ranges and storage conditions . . . . . . . . . . . Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . CMOS inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMOS outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . QFN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . VFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . DS11793 - Rev 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 . 73 . 74 . 75 . 75 . 76 . 76 . 77 . 77 . 78 . 78 . 79 . 80 . 80 . 81 . 81 . 82 . 82 . 83 . 83 . 84 . 84 . 85 . 85 . 86 . 86 . 87 . 87 . 88 . 88 . 89 . 89 . 90 . 90 . 91 . 91 . 92 . 92 . 93 . 93 . 94 . 95 . 97 . 97 . 97 . 98 . 98 . 99 . 99 103 104 106 107 page 114/116 ST25R3911B List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. DS11793 - Rev 7 ST25R3911B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum configuration with single sided antenna driving (including EMC filter) Minimum configuration with differential antenna driving (including EMC filter) . Receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitive sensor block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase detector inputs and output in case of 90º phase shift . . . . . . . . . . . . . Phase detector inputs and output in case of 135º phase shift . . . . . . . . . . . . ST25R3911B power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exchange of signals with microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . SPI communication: writing a single byte . . . . . . . . . . . . . . . . . . . . . . . . . . SPI communication: writing multiple bytes . . . . . . . . . . . . . . . . . . . . . . . . . SPI communication: reading a single byte . . . . . . . . . . . . . . . . . . . . . . . . . SPI communication: loading of FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI communication: reading of FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI communication: direct command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI communication: direct command chaining . . . . . . . . . . . . . . . . . . . . . . SPI general timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct command NFC initial field ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct command NFC response field ON . . . . . . . . . . . . . . . . . . . . . . . . . . ISO14443A states for PCD and PICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selection of MRT and NRT for a given FDT . . . . . . . . . . . . . . . . . . . . . . . . Flowchart for ISO14443A anticollision with ST25R3911B . . . . . . . . . . . . . . . Transport frame format according to NFCIP-1. . . . . . . . . . . . . . . . . . . . . . . Connection of tuning capacitors to the antenna LC tank . . . . . . . . . . . . . . . . Example of sub-carrier stream mode for scf = 01b and scp = 10b . . . . . . . . . Example of BPSK stream mode for scf = 01b and scp = 10b . . . . . . . . . . . . Example of Tx in stream mode for stx = 000b and OOK modulation. . . . . . . . ST25R3911B QFN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCASE vs. power with different copper area at Tamb = 25°C. . . . . . . . . . . . . . RthCA vs. copper area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QFN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VFQFPN32 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2 .. 5 .. 5 .. 7 . 11 . 16 . 16 . 17 . 19 . 20 . 21 . 21 . 22 . 23 . 23 . 24 . 24 . 25 . 29 . 30 . 38 . 39 . 40 . 42 . 48 . 50 . 51 . 51 . 95 101 101 102 104 105 page 115/116 ST25R3911B IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS11793 - Rev 7 page 116/116