ST25R3920B-AQWT

ST25R3920B Automotive NFC reader for CCC digital key and car center console Datasheet - production data VFQFPN32 (5 x 5 mm) Features • AEC-Q100 qualified • Operating modes – Reader/writer – Card emulation – Active and passive peer to peer • RF communication – EMVCo® 3.1a analog and digital compliant – NFC-A / ISO14443A up to 848 kbit/s – NFC-B / ISO14443B up to 848 kbit/s – NFC-F / FeliCa™ up to 424 kbit/s – NFC-V / ISO15693 up to 53 kb/s – NFC-A / ISO14443A (106 kbit/s) and NFC-F / FeliCa™ (212/424 kbit/s) card emulation – Active and passive peer to peer initiator and target modes, up to 424 kbit/s – Low level modes to implement MIFARE Classic® compliant or other custom protocols • Key features – Dynamic power output (DPO) controls the field strength to stay within given limits – Active wave shaping (AWS) reduces overand under-shoots – Noise suppression receiver (NSR) allows reception in noisy environment – Automatic antenna tuning (AAT) via variable capacitor November 2022 This is information on a product in full production. – Integrated EMVCo® 3.1a compliant EMD handling – Automatic gain control and squelch feature to maximize SNR – Low power NFC active and passive target modes – Adjustable ASK modulation depth, from 0 to 82% – Integrated regulators to boost system PSRR – AM/PM and I/Q demodulator with baseband channel summation or automatic channel selection – Possibility to drive two independent single ended antennas – Measurement of antenna voltage amplitude and phase, RSSI, on-chip supply and regulated voltages • External communication interfaces – 512-byte FIFO – Serial peripheral interface (SPI) up to 5 Mbit/s – I2C with up to 400 kbit/s in Fast-mode, 1 Mbit/s in Fast-mode Plus, and 3.4 Mbit/s in High-speed mode • Electrical characteristics – Wide supply voltage and ambient temperature range (2.6 to 5.5 V from -40 °C to +105 °C, 2.4 to 5.5 V from -20 °C to +105 °C) – Wide peripheral communication supply range, from 1.65 to 5.5 V – Quartz oscillator capable of operating with 27.12 MHz crystal with fast start-up DS13890 Rev 4 1/158 www.st.com Contents ST25R3920B Contents 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 System diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.3 Phase and amplitude detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.4 Automatic antenna tuning (AAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.5 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.6 External field detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.7 Quartz crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.8 Power supply regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.9 POR and bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.10 RC oscillator and Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.11 TX encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.12 RX decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.13 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.14 Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.15 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.16 Passive target memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.17 P2RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 Pin and signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/158 4.1 Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.3 Antenna tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.4 Wake-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.5 Quartz crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2.6 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DS13890 Rev 4 ST25R3920B 4.3 4.4 4.5 Contents 4.2.7 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.8 Phase and amplitude detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.9 External field detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2.10 Power supply system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2.11 Overshoot / undershoot protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.2.12 Active wave shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2.13 Reader operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.14 Listen mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Communication with an external microcontroller . . . . . . . . . . . . . . . . . . . 47 4.3.1 Interrupt interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3.2 Communication interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3.4 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Direct commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.4.1 Set default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.4.2 Stop all activities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.4.3 Clear FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.4.4 Transmit commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.4.5 NFC field ON commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.4.6 Mask receive data and Unmask receive data . . . . . . . . . . . . . . . . . . . . 63 4.4.7 Change AM modulation state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.4.8 Measure amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.4.9 Reset RX gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.4.10 Adjust regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.4.11 Measure phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4.12 Clear RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4.13 Transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4.14 Measure power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4.15 Trigger RC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4.16 Test access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.5.1 IO configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5.2 IO configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.5.3 Operation control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.5.4 Mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.5.5 Bit rate definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.5.6 ISO14443A and NFC 106kb/s settings register . . . . . . . . . . . . . . . . . . . 76 DS13890 Rev 4 3/158 6 Contents 4/158 ST25R3920B 4.5.7 ISO14443B settings register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.5.8 ISO14443B and FeliCa settings register . . . . . . . . . . . . . . . . . . . . . . . . 78 4.5.9 NFCIP-1 passive target definition register . . . . . . . . . . . . . . . . . . . . . . . 79 4.5.10 Stream mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.5.11 Auxiliary definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.5.12 EMD suppression configuration register . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.13 Subcarrier start timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.5.14 Receiver configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.5.15 Receiver configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.5.16 Receiver configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.5.17 Receiver configuration register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.5.18 P2P receiver configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.5.19 Correlator configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.5.20 Correlator configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.5.21 Mask receive timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.5.22 No-response timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.5.23 No-response timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.5.24 Timer and EMV control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.5.25 General purpose timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.5.26 General purpose timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.5.27 PPON2 field waiting register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.5.28 Squelch timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.5.29 NFC field on guard timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.5.30 Mask main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.5.31 Mask timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.5.32 Mask error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . 97 4.5.33 Mask passive target interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.5.34 Main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.5.35 Timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.5.36 Error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.5.37 Passive target interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.5.38 FIFO status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.5.39 FIFO status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.5.40 Collision display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.5.41 Passive target display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.5.42 Number of transmitted bytes register 1 . . . . . . . . . . . . . . . . . . . . . . . . 105 4.5.43 Number of transmitted bytes register 2 . . . . . . . . . . . . . . . . . . . . . . . . 105 DS13890 Rev 4 ST25R3920B Contents 4.5.44 Bit rate detection display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.5.45 A/D converter output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.5.46 Antenna tuning control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.5.47 Antenna tuning control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.5.48 TX driver register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.5.49 Auxiliary modulation setting register . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.5.50 Passive target modulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.5.51 TX driver timing register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.5.52 External field detector activation threshold register . . . . . . . . . . . . . . . 114 4.5.53 Resistive AM modulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.5.54 External field detector deactivation threshold register . . . . . . . . . . . . . 117 4.5.55 TX driver timing display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.5.56 Regulator voltage control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.5.57 Regulator display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.5.58 RSSI display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.5.59 Gain reduction state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.5.60 AWS Config 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.5.61 AWS Config 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.5.62 Auxiliary display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.5.63 Overshoot protection configuration register 1 . . . . . . . . . . . . . . . . . . . 127 4.5.64 Overshoot protection configuration register 2 . . . . . . . . . . . . . . . . . . . 127 4.5.65 Undershoot protection configuration register 1 . . . . . . . . . . . . . . . . . . 128 4.5.66 Undershoot protection configuration register 2 . . . . . . . . . . . . . . . . . . 129 4.5.67 Wake-up timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4.5.68 Amplitude measurement configuration register . . . . . . . . . . . . . . . . . . 131 4.5.69 Amplitude measurement reference register . . . . . . . . . . . . . . . . . . . . . 131 4.5.70 AWS time 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.5.71 AWS time 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.5.72 AWS time 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.5.73 AWS time 4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.5.74 AWS time 5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.5.75 AWS time 6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.5.76 Amplitude measurement auto-averaging display register . . . . . . . . . . 135 4.5.77 Amplitude measurement display register . . . . . . . . . . . . . . . . . . . . . . . 135 4.5.78 Phase measurement configuration register . . . . . . . . . . . . . . . . . . . . . 136 4.5.79 Phase measurement reference register . . . . . . . . . . . . . . . . . . . . . . . 136 4.5.80 Phase measurement auto-averaging display register . . . . . . . . . . . . . 137 DS13890 Rev 4 5/158 6 Contents 5 6 ST25R3920B 4.5.81 Phase measurement display register . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.5.82 Measurement TX delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.5.83 IC identity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 5.3 DC/AC characteristics for digital inputs and outputs . . . . . . . . . . . . . . . 143 5.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.5 SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.6 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.1 VFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6/158 DS13890 Rev 4 ST25R3920B List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. ST25R3920B VFQFPN32 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 RX channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Low-pass control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 First and third zero setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Typical preset values for slow, medium and fast transients in OOK and ASK . . . . . . . . . . 40 PT_Memory address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 NFC-212/424k SENS_RES format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 IRQ output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Serial data interface (4-wire interface) signal lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SPI operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I2C interface and interrupt signal lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 List of direct commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Timing parameters of NFC field ON commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Analog test and observation register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Test access register - Signal selection of TAD1 and TAD2 pins . . . . . . . . . . . . . . . . . . . . 65 List of registers - Space A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 List of registers - Space B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 IO configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 IO configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Operation control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Initiator operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Target operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Bit rate definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Bit rate coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ISO14443A and NFC 106kb/s settings register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Modulation pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ISO14443B settings register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ISO14443B and FeliCa settings register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Minimum TR1 codings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 NFCIP-1 passive target definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Stream mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Sub-carrier frequency definition for Sub-Carrier stream mode . . . . . . . . . . . . . . . . . . . . . . 80 Definition of time period for Stream mode Tx modulator control. . . . . . . . . . . . . . . . . . . . . 80 Auxiliary definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 EMD suppression configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Subcarrier start timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Receiver configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Receiver configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Receiver configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Receiver configuration register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 P2P receiver configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 OOK threshold level settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Correlator configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Correlator configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Mask receive timer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 No-response timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 No-response timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 DS13890 Rev 4 7/158 9 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. 8/158 ST25R3920B Timer and EMV control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Trigger sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 General purpose timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 General purpose timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PPON2 field waiting register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Squelch timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 NFC field on guard timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Mask main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Mask timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Mask error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Mask passive target interrupt register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Passive target interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 FIFO status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 FIFO status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Collision display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Passive target display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Number of transmitted bytes register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Number of transmitted bytes register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Bit rate detection display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 A/D converter output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Antenna tuning control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Antenna tuning control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 TX driver register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 AM modulation index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 RFO driver resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Auxiliary modulation setting register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Passive target modulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Passive target modulated and unmodulated state driver output resistance . . . . . . . . . . . 112 TX driver timing register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 External field detector activation threshold register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Resistive AM modulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Resistive AM modulated state driver output resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 115 External field detector deactivation threshold register . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Peer detection threshold as seen on RFI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Collision avoidance threshold as seen on RFI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 TX driver timing display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Regulator voltage control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Regulator display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Regulated voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 RSSI display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Gain reduction state register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 AWS configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 AWS configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Auxiliary display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Overshoot protection configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Overshoot protection configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Undershoot protection configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Undershoot protection configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 DS13890 Rev 4 ST25R3920B Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. List of tables Wake-up timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Typical wake-up time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Amplitude measurement configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Amplitude measurement reference register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 AWS time 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 AWS time 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 AWS time 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 AWS time 4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 AWS time 5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 AWS time 6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Amplitude measurement auto-averaging display register. . . . . . . . . . . . . . . . . . . . . . . . . 135 Amplitude measurement display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Phase measurement configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Phase measurement reference register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Phase measurement auto-averaging display register . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Phase measurement display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Measurement TX delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Wake-up time and wake-up pulse prolongation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 IC identity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Characteristics of CMOS I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 ST25R3920B electrical characteristics (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 ST25R3920B electrical characteristics (VDD = 5.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 145 ST25R3920B electrical characteristics (VDD = 2.4 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 SPI characteristics (5 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 AC measurement conditions - I2C configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 100 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 400 kHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 3.4 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 VFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 DS13890 Rev 4 9/158 9 List of figures ST25R3920B List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. 10/158 Minimum system configuration - Single sided antenna driving . . . . . . . . . . . . . . . . . . . . . . 13 Minimum system configuration - Differential antenna driving . . . . . . . . . . . . . . . . . . . . . . . 14 ST25R3920B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ST25R3920B QFN32 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Phase detector inputs and output in case of 90º phase shift . . . . . . . . . . . . . . . . . . . . . . . 34 Phase detector inputs and output in case of 135º phase shift . . . . . . . . . . . . . . . . . . . . . . 34 ST25R3920B power supply system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AWS mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Bit and timing relation for OOK waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Bit and timing relation for ASK waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Exchange of signals with a microcontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SPI communication: writing a single byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SPI communication: writing multiple bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SPI communication: reading a single byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SPI communication: FIFO loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SPI communication: FIFO reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SPI communication: direct command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SPI communication: direct command chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Writing a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Writing register data with auto-incrementing address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Reading a single byte from a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 FIFO load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 FIFO read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Sending a direct command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Read and Write mode for register space-B access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 I2C master reads slave immediately after the first byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Direct command NFC initial field ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Direct command NFC response field ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SPI timing diagram - General operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 SPI timing diagram - Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 RPmin vs. VDD, fc = 3.4 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Maximum Rbus value vs. bus parasitic capacitance, fc = 3.4 MHz . . . . . . . . . . . . . . . . . 152 I2C AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 I2C AC measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 VFQFPN32 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 VFQFPN32 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 DS13890 Rev 4 ST25R3920B 1 Applications Applications The ST25R3920B device is suitable for a wide range of NFC and HF RFID applications, among them • NFC Forum compliant NFC universal device • EMVCo 3.1a compliant contactless payment terminal • ISO14443 and ISO15693 compliant general purpose NFC device • FeliCa™ reader / writer • Support all five NFC Forum Tag types in reader mode • Support all common proprietary protocols, such as Kovio, CTS, B’. DS13890 Rev 4 11/158 157 Description 2 ST25R3920B Description The ST25R3920B is an automotive grade high performance NFC universal device supporting NFC initiator, NFC target, NFC reader and NFC card emulation modes. Designed for CCC (car connectivity consortium) digital key applications, the ST25R3920B enables fast product development for car access/start applications in areas like door handle or center console, and enables additional functionality, like pairing or NFC card protection combined with a Qi charger. Being very robust and noise tolerant while at the same time reducing electromagnetic emission, the device works even under harsh conditions, enabling an easier certification. The device includes an advanced analog front end (AFE) and a highly integrated data framing system for ISO18092 passive and active initiator, ISO 18092 passive and active target, NFC-A/B (ISO14443A/B) reader including higher bit rates, NFC-F (FeliCa™) reader, NFC-V (ISO15693) reader up to 53 kbps, and NFC-A / NFC-F card emulation. Special stream and transparent modes of the AFE and framing system is used to implement other custom protocols in reader or card emulation modes. The ST25R3920B features high RF power with dynamic power output to directly drive antennas at high efficiency, achieving large interaction distance even with small antenna sizes common in door handles. The device include additional features, making it incomparable for low power applications. It offers low power card detection by performing a measurement of the amplitude or phase of the antenna signal while reducing power consumption to a minimum. The ST25R3920B is designed to operate from a wide power supply range (2.6 to 5.5 V from -40 °C to +105 °C, 2.4 to 5.5 V from -20 °C to +105 °C), and a wide peripheral IO voltage range (from 1.65 to 5.5 V). Due to this combination of high RF output power, low power modes, wide supply range and AEC-Q100 grade 2 qualification the device is perfectly suited for automotive applications. 12/158 DS13890 Rev 4 ST25R3920B 2.1 Description System diagram Figure 1 and Figure 2 show the minimum system configuration for, respectively, single ended and differential antenna configurations. Both include the EMC filter. Figure 1. Minimum system configuration - Single sided antenna driving +2.4 to +5.5 V +1.65 to +5.5 V VDD_IO VDD VDD_TX VDD_A BSS MISO MCU MOSI SCLK IRQ GND_A VDD_D GND_D 2.2 μFNOM for Regulator AM and 22 nFNOM for AWS AM MCU_CLK VDD_AM Connect to GND (SPI) or VDD_D (I2C) I2C_EN ST25R3920B XTI XTO VDD_RF VDD_DR AGD Antenna coil VSS TAD2 TAD1 AAT_A AAT_B RF01 RF02 RFI1 RFI2 EXT_LM GND_DR1 GND_DR2 MS69287V4 DS13890 Rev 4 13/158 157 Description ST25R3920B Figure 2. Minimum system configuration - Differential antenna driving 55 +1.65 to +5.5 V VDD_IO VDD VDD_TX VDD_A BSS GND_A MISO MCU MOSI VDD_D SCLK IRQ GND_D MCU_CLK VDD_AM Connect to GND (SPI) or VDD_D (I2C) I2C_EN 2.2 μFNOM for Regulator AM and 22 nFNOM for AWS AM ST25R3920B XTI VDD_RF VDD_DR XTO AGD Antenna coil VSS RF01 TAD2 TAD1 RF02 AAT_A RFI1 AAT_B RFI2 EXT_LM GND_DR1 GND_DR2 MS69288V3 14/158 DS13890 Rev 4 ST25R3920B 2.2 Description Block diagram The ST25R3920B block diagram is shown in Figure 3, the main functions are described in the following subsections. Figure 3. ST25R3920B block diagram XTO RC oscillator XTI XTAL oscillator VDD VDD_A VDD_D POR and Bias VDD_A, VDD_D reference regulator VDD_TX VDD_RF, VDD_AM regulator Transmitter Wake-up timer TX coding Level shifters Protocol timers I2C_EN RFO1 RFO2 EXT_LM /NC IRQ SPI VDD_AM VDD_DR Digital part VDD_IO VDD_RF A/D converter Phase and amplitude detector Control logic Passive target SDD logic MCU_CLK SPI/I2C interfaces External field detector RFI1 RX decoding FIFO 512 bytes P2RAM 6 bytes Receiver RFI2 Registers Passive target memory AAT D/A converter AAT_A /TO2 AAT_B /TO3 ST25R3920B MS69289V1 2.2.1 Transmitter In reader mode the transmitter drives an external antenna through pins RFO1 and RFO2 to generate the RF field. Single sided and differential antenna configurations are supported. The transmitter block also generates the OOK or AM modulation of the transmitted RF signal. The transmitter can either operate RFO1 and RFO2 independently to drive up to two antennas in single ended configuration or operate RFO1 and RFO2 combined to drive one antenna in differential configuration. The drivers are designed to directly drive antenna(s) integrated on the PCB as well as antennas connected with 50 Ω cables. Some of the advanced features (such as antenna diagnostics) are not fully usable if the antenna is connected with a 50 Ω cable. In card emulation mode the transmitter generates the load modulation signal by changing the resistance of the internal antenna driver connected to the antenna via RFO1 and RFO2. The transmitter can also drive an external MOS transistor via the EXT_LM pin to generate the load modulation signal. DS13890 Rev 4 15/158 157 Description 2.2.2 ST25R3920B Receiver The receiver detects card modulation superimposed on the 13.56 MHz carrier signal. The receiver consists of two receive chains that are built from a set of demodulators, followed by two gain and filtering stages and a final digitizer stage. The demodulators operate as AM/PM demodulator or as I/Q demodulator. The filter characteristics can be adjusted to match the selected RF mode and bit rate to optimize performance (subcarrier frequencies from 212 to 848 kHz are supported). Apart from the filter stage the receiver incorporates several other features (AGC, squelch) that enable reliable operation in noisy conditions. The receiver is connected to the antenna via the pins RFI1 and RFI2. The output of the receiver is connected to the framing block that decodes the demodulated and digitized subcarrier signal. 2.2.3 Phase and amplitude detector The phase detector measures the phase difference between the transmitter output signals (RFO1 and RFO2) and the receiver input signals (RFI1 and RFI2). The amplitude detector measures the amplitude of the differential RF carrier signal between the receiver inputs RFI1 and RFI2. This differential amplitude signal is directly proportional to the amplitude of the RF signal on the antenna LC tank. The phase- and amplitude detectors are used for several purposes: 2.2.4 • PM demodulation, by observing RFI1 and RFI2 phase variations (LF signal is fed to the receiver) • Average phase difference between RFOx pins and RFIx pins, to check antenna tuning • Measure amplitude of signal present on pins RFI1 and RFI2, proportional to the antenna voltage Automatic antenna tuning (AAT) The AAT block consists of two independent 8-bit D/A converters. These converters generate a programmable voltage (from 0 to 3.3 V) to control external variable capacitors. 2.2.5 A/D converter The ST25R3920B feature a built in A/D converter. Its input can be multiplexed from different sources and it is used for the diagnostic functions and the low power card detection. The result of the A/D conversion is stored in a register that can be read through the host interface. 2.2.6 External field detector This is a low power block used in the active or passive target mode to detect the presence of an external RF field. It supports two different external field detection thresholds, namely Peer detection and Collision avoidance threshold. The Peer detection threshold is used in the active and passive peer to peer modes to detect when the peer device turns on its RF field. The Collision avoidance threshold is used to detect the presence of an external RF field during the RF collision avoidance procedure. 16/158 DS13890 Rev 4 ST25R3920B 2.2.7 Description Quartz crystal oscillator The quartz crystal oscillator operates with 27.12 MHz crystals. At start-up the transconductance of the oscillator is increased to achieve a fast start-up. Since the start-up time varies with crystal type, temperature and other parameters, the oscillator amplitude is observed and an interrupt is generated when stable oscillator operation is reached. The oscillator block also provides a clock signal to the external microcontroller (MCU_CLK), according to the settings in the IO configuration register 1. 2.2.8 Power supply regulators The integrated power supply regulators ensures a high power supply rejection ratio (PSRR) for the complete system. Three voltage regulators, one for the analog block, one for the digital block, and one for the RF output drivers, are available to decouple noise sources from the ST25R3920B. A fourth voltage regulator generates the reference voltage for the analog receivers (AGDC, analog ground). The RF output driver voltage regulator is configured automatically by the ST25R3920B based on the systems power supply stability and RF output power (see Section 4.4.10: Adjust regulators for more details). 2.2.9 POR and bias This block provides bias currents and reference voltages to all other blocks. It also incorporates a Power on Reset (POR) circuit that provides a reset at power-up and at low supply levels. 2.2.10 RC oscillator and Wake-up timer The ST25R3920B includes several possibilities for low power detection of a card presence (phase measurement, amplitude measurement). The RC oscillator and the register configurable Wake-up timer are used to periodically trigger the card presence detection in the low power card detection modes. 2.2.11 TX encoding This block encodes the transmit frames according to the selected RF mode and bit rate. The SOF (start of frame), EOF (end of frame), CRC and parity bits are generated automatically. The data to transmit are taken from the FIFO. In Stream mode the framing is bypassed. The FIFO data directly defines the modulation data sent to the transmitter. In Transparent mode, the framing and FIFO are bypassed, and the MOSI pin directly drives the modulation of the transmitter. 2.2.12 RX decoding This block decodes received frames according to the selected RF mode and bitrate. The received data is written to the FIFO. In Stream mode the framing is bypassed. The digitized subcarrier signal is directly stored in the FIFO. DS13890 Rev 4 17/158 157 Description ST25R3920B In Transparent mode the framing and FIFO are bypassed. The digitized subcarrier signal directly drives the MISO pin. 2.2.13 FIFO The ST25R3920B contain a 512-byte FIFO. Depending on the direction of the data transfer, it contains either data which has been received or data which is to be transmitted. In reader mode the ST25R3920B can transmit frames of up to 8191 bytes length and receive frames of arbitrary length. 2.2.14 Control logic The control logic contains I/O registers that define the operation of device. 2.2.15 Host interface A 4-wire serial peripheral interface (SPI) and a 2-wire I2C interface are available to communicate with an external microcontroller. The pins for the SPI and the I2C interface are shared, and pin I2C_EN is used to select the active interface. 2.2.16 Passive target memory The device contains a 48-byte RAM to store configuration data for the passive target and card emulation mode. 2.2.17 P2RAM The P2RAM stores information on wafer number, die position, device subversion, and I2C address. The P2RAM is programmed during production. 18/158 DS13890 Rev 4 ST25R3920B Pin and signal description SCLK/SCL BSS MCU_CLK IRQ GND_A TAD1 32 1 VDD_IO MOSI MISO/SDA Figure 4. ST25R3920B QFN32 pinout (top view) 31 30 29 28 27 26 25 24 AGDC TAD2 2 23 RFI2 VDD_D 3 22 RFI1 XTO 4 21 VSS XTI 5 20 I2C_EN GND_D 6 19 AAT_B VDD_A 7 18 AAT_A VFQFPN32 33 9 10 11 12 13 14 15 VDD_TX VDD_AM GND_DR1 RFO1 VDD_DR RFO2 8 17 16 EXT_LM GND_DR2 VDD VDD_RF 3 Pin and signal description MS68598V2 Table 1. ST25R3920B VFQFPN32 pin assignment VFQFPN32 Name Type(1) 1 VDD_IO P 2 TAD2 AO/DO 3 VDD_D AO Digital supply regulator output 4 XTO AO Crystal oscillator output 5 XTI AI/DI 6 GND_D P 7 VDD_A AO 8 VDD P 9 VDD_RF AO 10 VDD_TX P 11 VDD_AM AO Regulated driver supply for AM modulation 12 GND_DR1 P Antenna driver ground, including driver VSS 13 RFO1 AO 14 VDD_DR P 15 RFO2 AO 16 GND_DR2 P 17 EXT_LM AO Description Positive supply for peripheral communication Test analog digital Crystal oscillator input, in test mode used as digital input (clock) Digital ground Analog supply regulator output External positive supply Regulated driver supply for antenna drivers External positive supply for the TX part Antenna driver output Antenna driver positive supply input Antenna driver output Antenna driver ground, including driver VSS External load modulation MOS gate driver DS13890 Rev 4 19/158 157 Pin and signal description ST25R3920B Table 1. ST25R3920B VFQFPN32 pin assignment (continued) VFQFPN32 Name Type(1) 18 AAT_A AO AAT tune voltage for variable capacitor AAT_A 19 AAT_B AO AAT tune voltage for variable capacitor AAT_B 20 I2C_EN DI I2C interface enable (VDD_D level) 21 VSS P Ground, die substrate potential 22 RFI1 AI Receiver input 23 RFI2 AI Receiver input 24 AGDC AIO 25 TAD1 AO/DO 26 GND_A P 27 IRQ DO Interrupt request output 28 MCU_CLK DO Clock output for MCU 29 BSS DI SPI enable (active low) 30 SCLK DI SPI clock / I2C clock 31 MOSI DI SPI data input 32 MISO DO_T 33 NA P Description Analog reference voltage Test analog digital Analog ground Serial peripheral interface data output / I2C data line Thermal pad 1. P: Power supply pin AIO: analog I/O, AI: analog input, AO: analog output, DI: digital input, DIPD: digital input with pull-down, DO: digital output, DO_T: digital output/tri-state, DIO: digital bidirectional. 20/158 DS13890 Rev 4 ST25R3920B Application information 4 Application information 4.1 Power-on sequence Once powered, the device enters the Power-down mode where the content of all registers is set to its default state. The next steps are basic configurations of the IC: 1. The IO configuration register 1 and IO configuration register 2 must be properly configured. 2. The internal voltage regulators have to be configured. It is recommended to use direct command Adjust regulators to improve the system PSRR. 3. If AAT is used the tuning procedure must be performed. 4. After device power-on and direct command set default, release the direct command Trigger RC calibration. After the sequence of events mentioned above the devices are ready to operate. 4.2 Operating modes The ST25R3920B operating mode is defined by the contents of the Operation control register. At power-on all its bits are set to 0, the ST25R3920B is in Power-down mode. In this mode, the AFE static power consumption is minimized, as only the POR and part of the bias are active. The regulator itself is disabled. The SPI/I2C is still functional in this mode and all required settings on the configuration registers can be done. The PT_memory and FIFO are not accessible in this mode. Bit en (bit 7 of the Operation control register) is controlling the quartz crystal oscillator, regulators and AAT control output pins. When this bit is set, the device enters in Ready mode and the quartz crystal oscillator and regulators are enabled. An interrupt is sent to inform the microcontroller when the oscillator amplitude and frequency is stable. The PT_memory and FIFO are accessible in this mode. The enable of the receiver and the transmitter block are separated, it is possible to operate one without switching on the other (control bits rx_en and tx_en). This feature is used when the reader field has to be maintained while no response from a tag is expected. Another example is NFCIP-1 active communication in receive mode configuration. The RF field is generated by the initiator on one side while the other side is only in receive operation. Asserting the Operation control register bit wu while the other bits are set to 0 puts the ST25R3920B into the Wake-up mode that is used to perform low power detection of card presence. In this mode the low power RC oscillator and register configurable wake-up timer are used to schedule periodic measurement(s). When a difference to the predefined reference is detected an interrupt is sent to wake-up the MCU. Phase and amplitude measurement are available to trigger the wake-up. DS13890 Rev 4 21/158 157 Application information 4.2.1 ST25R3920B Transmitter The transmitter contains two identical push-pull driver blocks connected to pins RFO1 and RFO2. These drivers are differentially driving the external antenna LC tank. It is also possible to operate only one of the two drivers by setting the IO configuration register 1 bit single and selecting which RFO/RFI to be use on bit rfo2. Output resistance Each driver is composed of eight segments having binary weighted output resistance. The MSB segment typical ON resistance is 4 Ω. When all segments are turned on, the output resistance is typically 2 Ω. Usually all segments are turned on to define the normal transmission (non-modulated) level. It is also possible to switch off certain MSB segments when driving the non-modulated level to drive the circuitry with a higher impedance driver. The bits d_res in the TX driver register define the resistance during the normal transmission. The default setting is minimum available resistance. When using the single driver mode, the number and therefore the cost of the antenna LC tank components is halved, but also the output power is reduced. In single mode it is possible to connect two antenna LC tanks to the two RFO outputs and multiplex between them by controlling the IO configuration register 1 bit rfo2. To transmit data, the transmitter output level needs to be modulated. AM and OOK modulation principles are supported. The type of modulation is defined by setting bit tr_am in the Mode definition register. Driver TX modulation During the OOK modulation (e.g. for ISO14443A) the transmitter drivers stop driving the carrier frequency. As a consequence the amplitude of the antenna LC tank oscillation decays, the time constant of the decay is defined with the LC tank Q factor. AM modulation (for example ISO14443B) is done via an additional regulator providing the supply voltage VDD_AM, used as the driver supply voltage during the modulation state. The AM modulation level is set by am_mod3:0 bits in the TX driver register. AM modulation has to be manually enabled and the level to be set correctly for the following protocols: • ISO14443B • FeliCa • ISO15693 (if not OOK) • NFCIP-1 212 and 424 kb/s initiator or active target. Depending on the applicable standard the modulation index is set in a range between 0 and 82% in the TX driver register. Passive load modulation The ST25R3920B enable passive load modulation using two different methods 22/158 • Internal driver load modulation • Load modulation with an external MOS transistor and a diode that directly loads the antenna circuit DS13890 Rev 4 ST25R3920B Application information The driver load modulation is selected by bit lm_dri and the external MOS modulation is selected by lm_ext option bits. Normally, the internal driver or the external load modulation should be used exclusively, but the device also allows simultaneous modulation. The driver load modulation is based on the change of driver impedance. Typically, a high impedance during non-modulated state and a lower impedance for the modulated state is used. This yields modulation phase equal to passive tag modulation. It is also possible to reverse the polarity of the driver load modulation by using low impedance during non-modulated state and higher impedance for the modulated state. During the non-modulated state the output impedance is defined by pt_res3:0 option bits. During modulation the output impedance is defined by ptm_res3:0 option bits. Load modulation through an external MOS transistor and a diode is selected by the lm_ext option bit. In this case the EXT_LM pin is driven by the digital representation of the load modulation signal (848 kHz subcarrier or 424 / 212 kHz modulation signal). The EXT_LM is used to drive a gate of the external modulation MOS. The bit lm_ext_pol sets inverse polarity for the external load modulation. The pt_res3:0 and ptm_res3:0 bits must be set prior entering passive target mode (reg 03h), because in passive target mode the resistance value propagates through the TX driver only when the extracted clock is available. Driver load modulation is based on change of the driver impedance. Typically high impedance is used during non-modulated state, and decreased for modulated state, resulting in modulation phase equal to Passive tag modulation. It is also possible to set inverse polarity driver load modulation by using low impedance during non-modulated state and higher impedance for the modulated state. During non-modulated / modulated state the output impedance is defined, respectively, by pt_res3:0 / ptm_res3:0 option bits. An external MOS transistor and a diode modulation is selected by lm_ext option bit. In this case the EXT_LM pin is driven by digital representation of the load modulation signal (848 kHz subcarrier or 424 / 212 kHz modulation signal). The EXT_LM is used to drive a gate of the external modulation MOS. Bit lm_ext_pol sets inverse polarity for the External load modulation. Bits pt_res and ptm_res must be set before entering Passive target mode (reg 03h), as in Passive target mode the resistance value propagates through the TX driver only when extracted clock is available (during PT data transmission, including FDT). 4.2.2 Receiver The receiver performs demodulation of the tag subcarrier modulation that is superimposed on the 13.56 MHz carrier frequency. It performs AM/PM or I/Q demodulation, amplification, band-pass filtering and digitalization of subcarrier signals. It also performs RSSI measurement, automatic gain control (AGC) and Squelch function. The reception chain has two separate channels for AM and PM demodulation. When both channels are active the selection for reception framing is done automatically by the receiver logic. The receiver is switched on when Operation control register bit rx_en is set to 1. DS13890 Rev 4 23/158 157 Application information ST25R3920B The Operation control register contains bits rx_chn and rx_man, which define whether only one or both demodulation channels are active: • bit rx_man defines the channel selection mode when both channels are active (automatic or manual) • bit ch_sel defines which channel is used for decoding. Table 2. RX channel selection rx_chn rx_man ch_sel Selected reception channel 0 0 x Automatic selection 0 1 0 AM or I channel 0 1 1 PM or Q channel 1 x 0 AM or I channel 1 x 1 PM or Q channel Figure 5. Receiver block diagram 24/158 DS13890 Rev 4 ST25R3920B Application information Demodulation stage The first stage performs demodulation of the tag subcarrier response signal, superimposed on the HF field carrier. Two different blocks are implemented for the AM demodulation: • peak detector • AM/I or PM/Q demodulator mixer. The choice of the used demodulator is made by the Receiver configuration register 2 bit amd_sel. The peak detector performs AM demodulation using a peak follower. Both the positive and negative peaks are tracked to suppress any common mode signals. Its demodulation gain is G = 0.7 and the input is taken from RFI1 demodulator input only. The AM demodulator mixer uses synchronous rectification of both receiver inputs (RFI1 and RFI2). Its gain is G = 0.55. The PM demodulation is also done by a mixer. The PM demodulator mixer has differential outputs with 60 mV differential signal for 1% phase change (16.67 mV / °). The I/Q demodulation is composed of two mixer circuits, driven with a 90° shifted local oscillator (LO) signals derived from the crystal oscillator. The outputs of the two mixers are connected to two equal base band reception chains and to the decoding logic. Filtering and gain stages The receiver chain has band pass filtering characteristics. The filtering is optimized to pass subcarrier frequencies while rejecting carrier frequency, low frequency noise and DC component. Filtering and gain is implemented in three stages, the first and the last stage have first order high pass characteristics while the mid stage has second order low-pass characteristic. The gain and filtering characteristics can be optimized depending on the application by writing the Receiver configuration register 1 (filtering), Receiver configuration register 3 (primarily gain in first stage) and Receiver configuration register 4 (gain in second and third stage). The gain of first stage is around 20 dB and can be reduced in six 2.5 dB steps. There is also a special boost mode available, which increases the max gain by additional 5.5 dB. The first stage gain can only be modified by writing Receiver configuration register 3. The default setting of this register is the minimum gain. Default first stage zero is located at 60 kHz, it can also be lowered to 40 or 12 kHz by writing option bits in the Receiver configuration register 1. The first stage can be reconfigured to second order high-pass at 600 kHz by option bit z600k. The control of the first and third stage zeros is done with common control bits (see Table 4). Table 3. Low-pass control rec1lp2 rec1lp1 rec1lp0 -1 dB point 0 0 0 1200 kHz 0 0 1 600 kHz 0 1 0 300 kHz 1 0 0 2 MHz DS13890 Rev 4 25/158 157 Application information ST25R3920B Table 3. Low-pass control (continued) rec1lp2 rec1lp1 rec1lp0 -1 dB point 1 0 1 7 MHz Others Not used Table 4. First and third zero setting rec1z600k rec1h200 rec1h80 rec1z12k 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 0 1 1 0 0 Others First stage zero Third stage zero 400 kHz 60 kHz 200 kHz 40 kHz 80 kHz 200 kHz 12 kHz 80 kHz 200 kHz 400 kHz 600 kHz 200 kHz Not used The gain in the second and third stage is 23 dB and can be reduced in six 3 dB steps. Gain of these two stages is included in AGC and Squelch loops or can be manually set in Receiver configuration register 4. Sending of direct command Reset RX Gain is necessary to initialize the AGC, Squelch and RSSI block. Sending this command clears the current Squelch setting and loads the manual gain reduction from Receiver configuration register 4. Second stage has a second order low-pass filtering characteristic, the pass band is adjusted according to subcarrier frequency using the bits lp2 to lp0 of the Receiver configuration register 1. See Table 3 for -1 dB cut-off frequency for different settings. Digitizing stage The digitizing stage produces a digital representation of the sub-carrier signal coming from the receiver. This digital signal is then processed by the receiver framing logic. The digitizing stage consists of a window comparator with adjustable digitizing window (five possible settings, 3 dB steps, adjustment range from ±33 to ±120 mV). The adjustment of the digitizing window is included in the AGC and Squelch loops. The digitizing window can also be set manually in the Receiver configuration register 4. AGC, Squelch and RSSI As mentioned above, the second and third gain stage gain and the digitizing stage window are included in the AGC and Squelch loops. Eleven settings are available. The default state features minimum digitizer window and maximum gain. The first four steps increase the digitizer window in 3 dB steps, the next six steps reduce the gain in the second and third gain stage, again in 3 dB steps. The initial start setting for Squelch and AGC is defined in Receiver configuration register 4. The Gain reduction state register displays the actual state of gain resulting from Squelch, AGC and initial settings in Receiver configuration register 4. 26/158 DS13890 Rev 4 ST25R3920B Application information Squelch This feature is designed for operation in noisy environments. The noise may be misinterpreted as the start of tag response, resulting in decoding errors. Automatic squelch is enabled by option bit sqm_dyn in the Receiver configuration register 2. It is activated automatically 18.88 µs after end of TX and is terminated at the moment the Mask receive timer (MRT) reaches the value defined in the Squelch timer register. This mode is primarily intended to suppress noise generated by tag processing during the time when the tag response is not expected (covered by MRT). Squelch can operate in two modes, namely with ratios 1 and 6, selectable by pulz_61 bit in the Receiver configuration register 2. Squelch ratio 1 means that system observes the subcarrier signal from the main digitizer and decrease the system gain to decrease the frequency of transitions. If there are more than two transitions on this output in a 50 μs time period, gain is reduced by 3 dB and output is observed during the following 50 μs. This procedure is repeated until number of transitions in 50 μs is lower or equal to 2 or until the maximum gain reduction is reached. This mode is intended for protocols where digitized subcarrier outputs are used. Squelch ratio 6 means the system similarly observes and decreases the frequency seen at the window comparator set to 6 times the digitizing window. This mode is intended for protocols where output from correlators are used (ISO-A, ISO-B correlated reception). The gain setting acquired by squelch is cleared by sending direct command Reset RX gain. AGC The AGC (automatic gain control) reduces the gain to keep the receiver chain and input to the digitizing stage out of saturation. The demodulation process is also less influenced by system noise when the gain is properly adjusted. The AGC logic starts operating when the signal rx_on is asserted to high and is reset when it is reset to low. The state of the receiver gain is stored in the Gain reduction state register during a high to low transition of bit rx_on. Reading this register later on gives information of the gain setting used during the last reception. The AGC system comprises a window comparator and an AGC ratio that can be set to 3 or to 6. As an example, when the AGC ratio is set to 6 the window is six times larger than the data digitalization window comparator. When the AGC function is enabled the gain is reduced until there are no transitions on its output. Such procedure assures that the input to digitalization window comparator is up to 6 times larger than its window. If the AGC ratio is set to three, the input to the digitalization window comparator is set to be up to 3 times larger than its window. The AGC operation is controlled by the control bits agc_en, agc_m, agc_alg, and agc6_3 in Receiver configuration register 2. The bit agc_m defines the AGC mode when two AGC modes are available. The AGC can operate during the complete RX process as long as the signal rx_on is high and it can be enabled only during first eight subcarrier pulses. There are two AGC algorithms to choose from bit agc_alg. The AGC can start either by pre-setting (maximum digitizer window and maximum gain) or by resetting (minimum digitizer window and maximum gain) it. The algorithm with preset is faster and therefore recommended for protocols with short SOF (like ISO14443A at 106 kbps). DS13890 Rev 4 27/158 157 Application information ST25R3920B Correlator The correlators correlate the incoming filtered subcarrier with 848 kHz. The aim of the correlation is to maximize the system sensitivity at 848 kHz, while rejecting other frequencies. There are two correlators in the system for AM (or I) channel and PM (or Q) channel. Correlator settings are defined in Correlator configuration register 1 and Correlator configuration register 2. RSSI The receiver also performs the RSSI (received signal strength indicator) measurement for both channels. The RSSI measurement is started after the rising edge of rx_on. It stays active while the signal rx_on is high and frozen while rx_on is low. It is a peak hold system where the value can only increase from initial 0 value. Every time the AGC reduces the gain the RSSI measurement is reset and starts from 0. The result of RSSI measurements is a 4-bit value that can be observed by reading the RSSI display register. The LSB step is 2.8 dB, the maximum value is Dh (13d). Since the RSSI measurement is of peak hold type, the result does not follow any variations in the signal strength (the highest value will be kept). To follow RSSI variation it is possible to reset RSSI bits and restart the measurement by sending direct command Clear RSSI. Clock extractor The clock extractor observes the RFI1 and RFI2 differential signal and provides a clock signal synchronous with the incoming RF field. The extracted clock is used for synchronous demodulation, for correct frame delay time and for correct data timing during passive transmission. The clock extractor is active down to 60 mVPP input signal. 4.2.3 Antenna tuning The ST25R3920B supports antenna tuning through external variable capacitors. The variable capacitor is connected on its position in the matching network, and the tuning control voltage is connected to one of the control output pins (AAT_A, AAT_B). The variable capacitors can be connected in series and parallel configurations in the matching network. Further information on the various configuration options can be found in the application note AN5322, available on www.st.com. The phase and amplitude detector block is used for resonance frequency checking. The algorithm in the MCU evaluates the result and adjusts the tuning voltages at AAT_A and AAT_B output pins via the Antenna tuning control register 1 and Antenna tuning control register 2 according to the procedure in the MCU firmware. The AAT_A/B pin voltages are actively set according to Antenna tuning control register 1 and Antenna tuning control register 2 when en and aat_en option bits are both set. If aat_en=1 and en=0, the AAT_A/B voltages are set to a fixed value between 1.5 and 2.2 V (typically 1.9 V). 28/158 DS13890 Rev 4 ST25R3920B 4.2.4 Application information Wake-up mode Asserting the Operation control register bit wu while the other bits are set to 0 puts the ST25R3920B into the Wake-up mode, used to perform low power detection of card presence. The ST25R3920B features two possibilities, namely phase and amplitude measurement. An integrated low power 32 kHz RC oscillator and register configurable Wake-up timer are used to schedule periodic detection. Usually the presence of a card is detected by a so-called polling. In this process the reader field is periodically turned on and the controller checks whether a card is present using RF commands. This procedure consumes a lot of energy since reader field has to be turned on for 5 ms before a command can be issued. Low power detection of card presence is performed by detecting a change in the reader environment, produced by a card. When a change is detected, an interrupt is sent to the controller. As a result, the controller performs a regular polling loop. In Wake-up mode the ST25R3920B periodically perform the configured reader environment measurements and sends an IRQ to the controller when a difference to the configured reference value is detected. Card detection The presence of a card close to the reader antenna coil produces a change of the antenna LC tank signal phase and amplitude. The reader field activation time needed to perform the phase or the amplitude measurement is extremely short (~20 μs) compared to the activation time needed to send a protocol activation command. The power level during the measurement can be lower than that during normal operation as the card does not have to be powered to produce a coupling effect. The emitted power can be reduced by changing the RFO driver resistance. Registers from 32h to 3Bh are dedicated to Wake-up configuration and display. The Wakeup timer control register is the main Wake-up mode configuration register. The timeout period between the successive detections and the measurements which are going to be used are selected in this register. Timeouts in the range from 10 to 800 ms are available, 100 ms being the default value. Registers from 33h to 3ADh configure the two possible detection measurements and store the results, four registers are used for each method. An IRQ is sent when the difference between a measured value and reference value is larger than configured threshold value. There are two possibilities how to define the reference value: • the ST25R3920B can calculate the reference based on previous measurements (auto-averaging) • the controller determines the reference and stores it in a register. The first register in the series of four is the Amplitude measurement configuration register. The difference to reference which triggers the IRQ, the method of reference value definition and the weight of last measurement result in case of auto-averaging are defined in this register. The next register is storing the reference value in case the reference is defined by the controller. The following two registers are display registers. The first one stores the auto-averaging reference, the second one stores the result of the last measurement. DS13890 Rev 4 29/158 157 Application information ST25R3920B Wake-up mode configuration registers have to be configured before Wake-up mode is actually entered. Any modification of Wake-up mode configuration while it is active may result in unpredictable behavior. Auto-averaging In case of auto-averaging the reference value is recalculated after every measurement. The last measurement value, the old reference value and the weight are used in this calculation. The following formula is used to calculate the new reference value: new_reference = old_reference - (old_reference - measured_value) / weight The calculation is done on 10 bits to have sufficient precision. The auto-averaging process is initialized when Wake-up mode is first time entered after initialization (power-up or using Set default command). The initial value is taken from the measurement reference register (for example Amplitude measurement reference register) if the content of this register is not 0. If content of this register is 0, the result of first measurement is taken as initial value. Every measurement configuration register contains a bit defining whether the measurement that causes an interrupt is taken in account for the average value calculation (for example bit am_aam of Amplitude measurement reference register). 4.2.5 Quartz crystal oscillator The quartz crystal oscillator operates with 27.12 MHz crystals; its operation is enabled when the Operation control register bit en is set to 1. An interrupt is sent to inform the microcontroller when the oscillator amplitude is sufficiently high, meaning the frequency is stable (see Main interrupt register). The status of oscillator can be observed by checking the Auxiliary display register bit osc_ok. This bit is set to 1 when oscillator frequency is stable. The oscillator is based on an inverter stage supplied by a controlled current source. A feedback loop is controlling the bias current in order to regulate amplitude on XTI pin to 1 VPP. To enable a fast reader start-up an interrupt is sent when oscillator amplitude exceeds 750 mVPP. Division by two assures that 13.56 MHz signal has a duty cycle of 50%, which is better for the transmitter performance (no PW distortion). The oscillator output is also used to drive a clock signal output pin MCU_CLK, which can be used by the external microcontroller. The MCU_CLK pin is configured in the IO configuration register 2. 4.2.6 Timers The ST25R3920B contain several timers, which eliminate the need to run counters in the controller, thus reducing the effort of the controller code implementation and improve portability of code to different controllers. Every timer has one or more associated configuration registers in which the timeout duration and different operating modes are defined. These configuration registers have to be set while the corresponding timer is not running. Any modification of timer configuration while the timer is active may result in unpredictable behavior. All timers are stopped by the direct command Stop all activities. 30/158 DS13890 Rev 4 ST25R3920B Application information Mask receive timer (MRT) In Reader mode this timer is blocking the receiver and reception process in framing logic by keeping the rx_on signal low after the end of TX during the time the tag reply is not expected. While Mask Receive timer is running the Squelch is automatically turned on when enabled. The MRT does not produce an IRQ. The MRT timeout is configured in the Mask receive timer register and is automatically started at the end of data transmission (at the end of EOF). The MRT can be triggered by direct command Start Mask-receive timer. In this case the squelch is enabled, according to the Squelch timer register. In the NFCIP-1 Active Initiator, Active and Passive Target communication modes the MRT is started when the other device turns on its field and the external field detector signals I_eon. MRT supports a longer timing needed for NFCIP1 by setting option bit mrt_step. The bit switches between fc/64 and fc/512 step size. The MRT starts also in the low power Initial NFC target mode. After the initiator field has been detected the controller turns on the 27 kHz RC oscillator, regulator, crystal oscillator, receiver and MRT. After the MRT expires the receiver output starts to be observed to detect start of the initiator message. For correct operation in the low power Initial NFC target mode the mrt_step = 1 must be used. The 27 kHz RC oscillator is used as a MRT clock source for the time before the crystal oscillator stabilises. This enables that the actual MRT time is a good approximation to the targeted time, also in case the crystal oscillator is not running yet. No-response timer (NRT) The purpose of this timer is intended to observe whether a response is detected during a configured time started by end of transmission. The I_nre flag in the Timer and NFC interrupt register is signaling interrupt events resulting from this timer timeout. The NRT is configured by writing No-response timer register 1 and No-response timer register 2). Operation options are defined by setting bits nrt_emv and nrt_step in the Timer and EMV control register. The NRT is automatically started at the end of transmission. Bit nrt_step configures the time step of the No-response timer. Two steps are available, 64/fc (4.72 μs) and 4096/fc, covering, respectively, the range up to 309 ms and up to 19.8 s. Bit nrt_emv controls the timer operation mode. • When this bit is set to 0 (default mode) the IRQ is produced if the NRT expires before a start of a response is detected. The rx_on is set low to disable the receiver. In the opposite case, when the start of a tag reply is detected before timeout, the timer is stopped, and no IRQ is produced. • When this bit is set to 1 the timer unconditionally produces an IRQ when it expires, it is also not stopped by direct command Stop all activities. This means that the IRQ is independent from whether or not a tag reply was detected. When a tag reply is being processed during a timeout, no other action is taken and the reply is normally received. In the opposite case, when no tag response is being processed, the receiver is disabled. The NRT can also be started using direct command Start No-response timer. The intention of this command is to extend the No-response timer timeout beyond the range defined in the DS13890 Rev 4 31/158 157 Application information ST25R3920B No-response timer control registers. If this command is sent while the timer is running, it is reset and restarted. The NRT can be terminated using direct command Stop No-response Timer or Stop all activities. The timer is terminated and no IRQ is sent. It is expected to be used in the nrt_emv mode, when the incoming reception does not stop the No-response timer. In the NFCIP-1 active communication mode the NRT role is similar to operation in the normal Reader mode. If the NRT expires before the start of a response is detected an IRQ is produced and the receiver is disabled. There are two modes available: • • nrt_nfc = 0 – The timer is started when the device TX field is switched off, using a general purpose timer. – The operation is valid for active initiator and target modes as well as for bit rate detection mode. nrt_nfc = 1 – The timer is started when the peer field is turned on. – Operation is valid for Active initiator and Active target modes. For Bit rate detection mode the timer is not started at peer field on as, in case of migration from Bit rate detection mode to Active target mode, the MCU has to reconfigure the device to Active target mode prior field on. In the NFCIP-1 Passive target the No-response timer has no task and is not automatically started. PPON2 timer This timer is not used in Reader mode. In NFCIP-1 mode this timer is automatically started when the transmitter is turned off after the message has been sent. If this timer expires before the peer NFC device (TFADT + n*TRFW) field-on is detected, an I_ppon2 IRQ is sent. I_txe is must be read before the I_gpe for PPON2 timer to be started. If the external RF field is detected on time, the timer is stopped and no IRQ is sent. Time is defined in the PPON2 field waiting register. General purpose (GP) timer The triggering of the this timer is configured by setting the Timer and EMV control register. It can be used to survey the duration of reception process (triggering by start of reception, after SOF) or to time out the PCD to PICC response time (triggered by end of reception, after EOF). In the NFCIP-1 active communication mode it is used to timeout the field switching off. In all cases an IRQ is sent when it expires. The GP timer can also be started by sending the direct command Start General purpose timer. If this command is sent while the timer is running, it is reset and restarted. 32/158 DS13890 Rev 4 ST25R3920B Application information Wake-up (WU) timer This timer is primarily used in the Wake-up mode, it can be used by sending the direct command Start Wake-up Timer. This command is accepted in any operation mode except Wake-up mode. When this command is sent the RC oscillator, which is used as clock source for wake-up timer is started, timeout is defined by setting the Wake-up timer control register. When the timer expires, an IRQ with the I_wt flag in the Error and wake-up interrupt register is sent. The WU timer is used in the Power-down mode, in which other timers cannot be used because the crystal oscillator, which is the clock source for the other timers, is not running. Note that the tolerance of wake-up timer timeout is defined by tolerance of the RC oscillator. In NFCIP-1 passive target mode the WU timer is used for time out the temporary device enable after the initial peer field on was detected. 4.2.7 A/D converter The ST25R3920B contains an 8-bit successive approximation A/D converter. Inputs can be multiplexed from different sources to be used in several direct commands and adjustment procedures. The result of the last conversion is stored in the A/D converter output register. Typical conversion time is 224/fc (16.5 µs). The A/D converter has two operating modes, absolute and relative. • In absolute mode the low reference is 0 V and the high reference is 2 V. This means that A/D converter input range is from 0 to 2V, 00h code means input is 0 V or lower, FFh means that input is 2 V - 1 LSB or higher, LSB being 7.8125 mV. • In relative mode low reference is 1/11 of VDD_A and high reference is 10/11 of VDD_A, so the input range is from 1/11 VDD_A to 10/11 VDD_A. Relative mode is only used in phase measurement (phase detector output is proportional to power supply). In all other cases absolute mode is used. 4.2.8 Phase and amplitude detector This block is used to provide inputs to the A/D converter to perform measurements of amplitude and phase, expected by direct commands Measure amplitude and Measure phase. Phase detector The phase detector observes phase difference between the transmitter output signals (RFO1 and RFO2) and the receiver input signals RFI1 and RFI2, proportional to the signal on the antenna LC tank. These signals are first passed by digitizing comparators. Digitized signals are processed by a phase detector with a strong low-pass filter characteristics to get the average phase difference. The phase detector output is inversely proportional to the phase difference between the two inputs. The 90° phase shift results in VDD_A/2 output voltage, if both inputs are in phase the output voltage is VDD_A, if they are in opposite phase the output voltage is 0 V. During execution of direct command Measure phase this output is multiplexed to the A/D converter input (A/D converter is in relative mode during the execution of this command). Since the A/D converter range is from 1/11 VDD_A to 10/11 VDD_A the actual phase detector range is from 17º to 163º. Figure 6 and Figure 7 show the two inputs and output of phase detector in case of 90º and 135º phase shift, respectively. DS13890 Rev 4 33/158 157 Application information ST25R3920B Figure 6. Phase detector inputs and output in case of 90º phase shift VSP_A Input 1 0 VSP_A Input 2 0 VSP_A Output VSP_A/2 0 MS42426V1 Figure 7. Phase detector inputs and output in case of 135º phase shift VSP_A Input 1 0 VSP_A Input 2 0 VSP_A Output VSP_A/2 0 MS42427V1 Amplitude detector Signals from pins RFI1 and RFI2 are used as inputs to the self-mixing stage. The output of this stage is a DC voltage proportional to the amplitude of signals on pins RFI1 and RFI2. During execution of direct command Measure amplitude this output is multiplexed to the A/D converter input. 4.2.9 External field detector This block is used to detect the presence of an external device generating an RF field. It is used in NFCIP-1 Active communication and Passive target modes. It is enabled by en_fd_c option bits. The external field detector supports two different detection thresholds, namely Peer detection and Collision avoidance. The two thresholds can be independently set by writing the External field detector activation threshold register. The actual state of the detector output can be checked by reading the Auxiliary display register. Input to this block is the signal from the RFI1 pin. For both thresholds there is a possibility to separately set the activation and deactivation levels. 34/158 DS13890 Rev 4 ST25R3920B Application information If the External field level is not detected yet, the Activation threshold is used. If the External field level is detected, the Deactivation threshold is used. The Activation threshold must be set higher than or equal to the Deactivation threshold. If the Activation is higher than the Deactivation, the hysteresis is given by the difference between the two levels. If the Activation and Deactivation levels are equal, there is no the hysteresis in the system and multiple field-on/off events can verify if the actual field level persists in proximity of the selected threshold. Peer detection threshold This threshold is used to detect the field emitted by peer NFC device with whom NFC communication is going on. It can be selected in the range from 75 to 800 mVPP. When this threshold is enabled the detector is in low power mode. An interrupt is generated when an external field is detected and also when it is switched off. With such implementation it can also be used to detect the moment when the external field disappears. This can be used to detect the moment when the peer NFC device (either an initiator or a target) has stopped emitting an RF field. The External Field Detector is enabled in low power Peer Detection mode by setting bits en_fd_c,1:0> in the Operation control register. Collision avoidance threshold This threshold is used during the RF collision avoidance sequence, which is executed by sending NFC Field ON commands (see Section 4.4.5: NFC field ON commands). It can be selected in the range from 25 to 800 mVPP. 4.2.10 Power supply system The ST25R3920B feature three positive supply pins, VDD, VDD_TX and VDD_IO: • VDD is the main power supply pin. It supplies the ST25R3920B blocks through two regulators (VDD_A, VDD_D) • VDD_TX is the transmitter supply pin. It supplies the transmitter via two regulators (VDD_RF, VDD_AM). VDD range from 2.4 to 5.5 V is supported. VDD and VDD_TX must be connected to the same power supply. • VDD_IO is used to define supply level for digital communication pins (BSS, MISO, MOSI, SCLK, IRQ, MCU_CLK). Digital communication pins interface to the ST25R3920B logic through level shifters, therefore the internal supply voltage can be either higher or lower than VDD_IO. VDD_IO range from 1.65 to 5.5 V is supported. Figure 8 details the building blocks of the ST25R3920B power supply system. It contains three regulators, a power-down support block, a block generating analogue reference voltage (AGDC) and a block performing automatic power supply adjustment procedure. The three regulators are providing supply to analogue blocks (VDD_A), logic (VDD_D) and transmitter (VDD_RF). The use of VDD_A and VDD_D regulators is mandatory at 5 V power supply to provide regulated voltage to analogue and logic blocks, which only use 3.3 V. The use of VDD_A and VDD_D regulators at 3 V supply and VDD_RF regulator at any supply voltage is recommended to improve system PSRR. Regulated voltage can be adjusted automatically to have maximum possible regulated voltage while still having good PSRR. All regulator pins also have corresponding negative supply pins externally connected to ground potential (VSS). Figure 1 and Figure 2 show DS13890 Rev 4 35/158 157 Application information ST25R3920B typical application schematics with all regulators used. For regulators recommended blocking capacitors are 2.2 μF in parallel with 10 nF, for pin AGDC 1 μF in parallel with 10 nF is suggested. Figure 8. ST25R3920B power supply system VDD_TX VDD EN sup3v VDD_D regulator VDD_A regulator VDD_RF regulator VDD_RF NŸ Power-down support NŸ VDD_DR VDD_AM regulator BGR and AGD AGDC VDD_D Ÿ Autoreg rege VDD_AM VDD_A reg Adjust regulators MS52437V1 Regulators have two basic operation modes depending on supply voltage, 3.3 V supply mode (max. 3.6 V) and 5 V supply mode (max 5.5 V). The supply mode is set by writing bit sup3V in theIO configuration register 2. Default setting is 5 V so this bit has to be set to 1 after power-up in case of 3.3 V supply. In 3.3 V mode all regulators are set to the same regulated voltage in range from 2.4 to 3.4 V, while in 5 V only the VDD_RF can be set in range from 3.6 to 5.1 V, while VDD_A and VDD_D are fixed to 3.4 V. Figure 8 also shows the signals controlling the power supply system. The regulators are operating when signal en is high (en is configuration bit in Operation control register). When signal en is low the ST25R3920B is in low power Power-down mode. In this mode consumption of the power supply system is also minimized. VDD_RF regulator The purpose of this regulator is to improve the PSRR of the transmitter (the noise of the transmitter power supply is emitted and fed back to the receiver). The VDD_RF regulator operation is controlled and observed by writing and reading two regulator registers: 36/158 • Regulator voltage control register controls the regulator mode and regulated voltage. Bit reg_s controls regulator mode. If it is set to 0 (default state) the regulated voltage is set using direct command Adjust regulators. When bit reg_s is asserted to 1 regulated voltage is defined by bits rege_3 to rege_0 of the same register. The regulated voltage adjustment range depends on the power supply mode. In case of 5 V supply mode the adjustment range is between 3.6 and 5.1 V in steps of 120 mV, in case of 3.3 V supply mode the adjustment range is from 2.4 to 3.6 V with 100 mV steps. • Regulator display register is a read only register that displays actual regulated voltage when regulator is operating. It is especially useful in case of automatic mode, since the DS13890 Rev 4 ST25R3920B Application information actual regulated voltage, which is result of direct command Adjust regulators, can be observed. The VDD_RF regulator includes a current limiter that limits the regulator current to 350 mArms in normal operation. The i_lim in the Regulator display register is set when the VDD_RF regulator is in current limiting mode. If a transmitter output current higher than 350 mArms is required the VDD_RF regulator cannot be used to supply the transmitter. VDD_RF and VDD_DR have to be externally connected to VDD_TX (connection of VDD_RF to supply voltage higher than VDD_TX is not allowed). The voltage drop of the transmitter current is the main source of the ST25R3920B power dissipation. This voltage drop is composed of a drop in the transmitter driver and of a drop in the VDD_RF regulator. Due to this it is recommended to set the regulated voltage using direct command Adjust Regulators. It results in good power supply rejection ratio with relatively low dissipated power due to regulator voltage drop. In Power-down mode the VDD_RF regulator is not operating. VDD_RF pin is connected to VDD_TX through a 1 kΩ resistor. Connection through resistors assures smooth power-up of the system and a smooth transition from Power-down mode to other operating modes. VDD_AM regulator This regulator is used to support the transmitter AM modulation. Its output voltage is used as transmitter supply during modulation phase. The output is internally connected to the transmitter. It requires decoupling capacitors (2.2µFNOM for Regulator AM and 22nFNOM for AWS AM) at VDD_AM pin. Additionally, 100pF to 2.2nF can be used to improve RF decoupling. VDD_DR is used as reference voltage, resulting in correct VDD_AM voltage and modulation index at supply voltage between 2.4 and 5.5 V. The output voltage and thus modulation setting is controlled by am_mod option bits from 0 to 82% in 16 steps. In Power-down mode the VDD_AM regulator is not operating. VDD_AM pin is connected to VDD_TX through 1 kΩ resistor, as in the VDD_RF regulator. VDD_A and VDD_D regulators VDD_A and VDD_D regulators are used to supply the ST25R3920B analog and digital blocks respectively. In 3.3 V mode VDD_A and VDD_D regulator are set to the same regulated voltage as the VDD_RF regulator, in 5 V mode VDD_A and VDD_D regulated voltage is fixed to 3.4 V. The use of VDD_A and VDD_D regulators is mandatory in 5 V mode since analog and digital blocks supplied with these two pins contain low voltage transistors which support maximum supply voltage of 3.6 V. In 3.3 V supply mode the use of regulators is strongly recommended to improve PSRR of analog processing. For low cost applications it is possible to disable the VDD_D regulator and to supply digital blocks through external short between VDD_A and VDD_D (configuration bit vspd_off in the IO configuration register 2). DS13890 Rev 4 37/158 157 Application information ST25R3920B Power-down support block In the Power-down mode the regulators are disabled to save current. In this mode a low power Power-down support block that keeps VDD_D and VDD_A below 3.6 V is enabled. Typical regulated voltage in this mode is 3.1 V at 5 V supply and 2.2 V at 3 V supply. When 3.3 V supply mode is set this block is disabled, its output is connected to VDD through a 1 kΩ resistor. Typical consumption of Power-down support block is 600 nA at 5 V supply. Measurement of supply voltages Using direct command Measure power supply it is possible to measure VDD and regulated voltages VDD_A, VDD_D and VDD_RF. 4.2.11 Overshoot / undershoot protection The overshoot / undershoot protection mechanism makes it possible to control the transmitting waveform during challenging test conditions. This is accomplished by setting bit patterns in the corresponding registers that produce additional signals during the transition phase from modulated to unmodulated state or vice versa. Note: ST25R3920 legacy overshoot / undershoot protection mode is only valid when rgs_am = 0, for this reason, specific drive levels must be set. For the ST25R3920B device, the overshoot / undershoot bits can be simply activated and used in conjunction with AWS registers. The operation of this protection is explained by using the overshoot registers. The overshoot mechanism is only effective when bits are written in ov_pattern. Setting ov_pattern to 0 implicitly disables the overshoot protection, as the configuration from Mode definition register and TX driver register is applied for all clock cycles after the transition. The overshoot mode has to be set in control bits ov_tx_mode and defines the drive level for the complete bit pattern. Three modes are available. • ov_tx_mode = 00b: the transmitter outputs are driven with VDD_DR when the respective ov_pattern bit is 1. • ov_tx_mode = 01b: the transmitter outputs are driven with VDD_AM when the respective ov_pattern bit is 1. • ov_tx_mode = 10b: the transmitter outputs are stopped (like Type A pause) when the respective ov_pattern bit is 1. The overshoot protection pattern ov_pattern is applied LSB first. For the first 14 clock cycles after the transition from modulated to unmodulated state, each of the 14 bits of the overshoot protection pattern specifies the driver configuration to apply. So ov_pattern defines which driver configuration to apply for the first clock cycle after the transition from modulated to unmodulated state, and ov_pattern defines which driver configuration to apply for the tenth clock cycle after the transition from modulated to unmodulated state. From the 15th clock cycle on the settings from TX driver register are used. The undershoot protection works in a similar manner for transitions from unmodulated state of the carrier to modulated state of the carrier. 38/158 DS13890 Rev 4 ST25R3920B 4.2.12 Application information Active wave shaping To use the specific wave shaping functionality of ST25R3920B, the logic must be enabled in the auxiliary modulation setting as well as the corresponding AWS registers. Additionally, the external VDD_AM capacitor must be selected in a range of 10-50 nF. Note: Contrary to the recommendations for the ST25R3920, do not insert a 2.2 μF capacitor on the VDD_AM pin when using AWS. To generally enable the ST25R3920B specific AWS: • set 0x28h in register SpaceB (Auxiliary modulation setting register) to 0x94h • set 0x2Eh in register SpaceB (AWS configuration) to 0x08h The following registers need to be adjusted depending on whether OOK (for instance NFC-A) or ASK (for instance NFC-B, NFC-F) modulation is transmitted. OOK: • set am_mod in TX driver register to 0xFXh, which is the lowest VDD_AM level during modulation (82 % modulation index) • clear am_sym and set en_modsink in AWS Config 2 register by writing 0x1Xh, which activates nonsymmetrical shape and strong en_modsink during OOK. ASK: • set am_mod in TX driver register to the required modulation index, which could be 0x4Xh or 12% for the usual case, for instance NFC-B. • set am_sym and clear en_modsink in AWS Config 2 register by writing 0x2Xh, which activates symmetrical shape and weak en_modsink during ASK. The shaping of the modulation pulse is done through am_filt speed and by setting the switching time of the clamp between VDD_RF and VDD_AM. The following picture gives a graphical representation of the wave shaping mechanism and involved register bits. Figure 9. AWS mechanism VDD_TX RF VDD_DR clamp modsw VDD_TX AM am_mod RFO VDD_AM r_trim am_filt am_sym en_modsink DS13890 Rev 4 mods d_res MS69269V2 39/158 157 Application information ST25R3920B The AM regulator, together with the am_filt bits, and circuitry behind, creates the reference for the filter curve. A larger value of am_filt results in a larger time constant of the VDD_AM regulator, and a slower signal transition. All timer names in AWS register that end with “1” (for instance, tmodsw1) represent the timer starts at falling edge. Similarly, all timer names that end with ‘2’ (for instance, tmodsw2) mean that the timer starts at rising edge (end of modulation). The typical preset values for slow, medium and fast transients in OOK and ASK can be applied by setting as showed in the below table: Table 5. Typical preset values for slow, medium and fast transients in OOK and ASK Note: 40/158 Slow transient Medium transient Fast transient AWS Config 2 = 0xXCh AWS Config 2 = 0xX8h AWS Config 2 = 0xX4h AWS time 1 = 0x01h AWS time 1 = 0x01h AWS time 1 = 0x01h AWS time 3 = 0x9Ch AWS time 3 = 0x79h AWS time 3 = 0x57h AWS time 4 = 0x0Ah AWS time 4 = 0x07h AWS time 4 = 0x06h The settings must be adjusted individually with the final antenna. DS13890 Rev 4 ST25R3920B Application information Timing related information when using OOK The following figure represents the interaction between bits and timings during active wave shaping in OOK modulation. Figure 10. Bit and timing relation for OOK waveform VDD_TX VDD_DR VDD_AM p_len modulation pulse width un_pattern tmods2 mods modswx2 modswx=11 am_mod=0000 d_res tmodswx1 ov_pattern 0: Driver to VDD_AM 1: Driver to VDD_DR 11: VDD_RF(DR)/AM Shorted tammod1 from register tdres2 tdres1 d_res md_res (if res_am=1) m en_tx tentx1 driver stop sinkx 0: strong sink 1: weak sink MS69283V1 DS13890 Rev 4 41/158 157 Application information ST25R3920B The following figure represents the interaction between bits and timings during active wave shaping in OOK modulation. Figure 11. Bit and timing relation for ASK waveform VDD_TX VDD_DR VDD_AM p_len modulation pulse width un_pattern tmods2 mods modsw2 modsw ov_pattern 0: Driver to VDD_AM 1: Driver to VDD_DR 1: VDD_RF/AM Shorted tmodsw1 tammod1 am_mod=0000 d_res tdres1 am_mod from register tdres2 d_res md_res (if res_am=1) m sinkx 0: strong sink 1: weak sink MS69285V1 Note: 42/158 The over- and undershoot patterns can be applied additionally to the AWS specific settings to further decrease over- and undershoot effects in the waveform signal. DS13890 Rev 4 ST25R3920B 4.2.13 Application information Reader operation The Ready mode has to be entered by setting the bit en of the Operation control register. In this mode the oscillator is started and the regulators are enabled. When the oscillator operation is stable an interrupt is sent and bit osc_ok indicates it. The operation mode and data rate must be then configured by writing the Mode definition register and Bit rate definition register. The receiver and transmitter operation options related to operation mode have to be defined too. If the selected operation mode uses AM modulation for communication reader to tag the modulation depth must be configured. Before sending any command to a transponder the transmitter and receiver have to be enabled by setting the bits rx_en and tx_en. Several NFC standards define a guard time (5 ms for ISO14443) requiring that the reader field must be turned on for some time before first command is sent. General purpose timer can be used to count this time or NFC Field On command with a defined time by the NFC field on guard timer register. Preparation and execution of a transceive sequence: • Execute the direct command Stop all activities • Execute the direct command Reset RX gain • Configure the timers accordingly • Define the number of transmitted bytes in the Number of transmitted bytes register 1 and Number of transmitted bytes register 2 • Write the bytes to be transmitted in the FIFO (not in the case of direct commands REQA and WUPA) • Send one of the commands Transmit with CRC, Transmit without CRC, Transmit REQA or Transmit WUPA • When all the data is transmitted an interrupt is sent to inform the microcontroller that the transmission is finished (IRQ due to end of transmission) After the transmission is executed, the ST25R3920B receiver automatically starts to observe the RFI inputs to detect a transponder response. The RSSI and AGC (in case it is enabled) are started. The framing block processes the subcarrier signal from receiver and fills the FIFO with data. When the reception is finished and all the data is in the FIFO an interrupt is sent to the microcontroller (IRQ due to end of receive), and the FIFO status register 1 and FIFO status register 1 display the number of bytes in the FIFO so the microcontroller can proceed with data download. If an error or bit collision are detected during reception, an interrupt with appropriate flag is sent, and the microcontroller must take appropriate action. When data packets longer than FIFO have to be transmitted the sequence detailed above changes. The FIFO is prepared with data before the transmission starts. An interrupt is sent during the transmission to signal when the remaining number of bytes is lower than the water level (IRQ due to FIFO water level). The microcontroller then adds more data in the FIFO. When all the data are transmitted an interrupt is sent to inform the microcontroller that the transmission is finished. The situation during reception time is similar. When the FIFO is loaded with more data than the receive water level, an interrupt is sent and the microcontroller reads the data from the FIFO. When the reception is finished an interrupt is sent to the microcontroller (IRQ due to end of receive) the FIFO status register 1 and FIFO status register 1 display the number of bytes in the FIFO still to be read. DS13890 Rev 4 43/158 157 Application information 4.2.14 ST25R3920B Listen mode The ST25R3920B listen/target mode is activated by setting to 1 bit targ in the Mode definition register. There are various target or listening modes implemented depending on setting of the om bits, refer to Table 23: Target operation modes. The main modes are • NFCIP-1 active target • Passive target used for Card mode and NFCIP-1 passive target Fixed listen communication mode Fixed communication mode is active when one of the target modes with om3=0 is selected. The other om bits control the type of communication. Passive target Communication can be performed by the host (through FIFO) or also by using automatic responses as referred in NFCIP-1 passive target definition register. These automatic responses include for NFC-A the complete anti-collision including SAK. Handling of RATS and HLTA is up to the host. For NFC-F only the SENSF_REQ is handled by sending SENSF_RES. States of NFC-A can be handled by observing Passive target display register and Passive target interrupt register bits I_wu_a, I_wu_a*. Direct commands Go to sense and Go to sleep let the host influence the passive target states. Responses to SENSF_REQ can be observed by thanks to bit I_wu_f. The content of the automatic responses is defined by content of PT_Memory. NFCIP-1 active target When operating in NFCIP-1 active target mode the following settings are relevant. • Enable external field detector by setting bit en_fd_c in the Operation control register. Using the field detector allows the ST25R3920B to turn on a response field depending on nfc_ar setting in the Mode definition register. Bits nfc_n of the Auxiliary definition register influence the timing of Response collision avoidance sequence. • The General purpose timer defines the time until RF field off after data transmission. Its trigger sourcehas to be set to the end of transmit, according to Table 50: Trigger sources (gptc = 011). • After TARFG either I_cat or I_cac is flagged. TARFG is defined by NFC field on guard timer register. • MRT starts at external field-on. NRT can be tailored by using nrt_nfc. • After switching off its field the ST25R3920B start the PPON2 timer and observe the External field detector output to detect the response field. If no external field is detected before PPON2 timer timeout, an IRQ with I_ppon2 flag is signaled. Bit rate detection mode The Listen mode can also be started from the so-called Bit rate detection mode. In this mode the communication mode is not fixed. This mode is activated in case of Target mode together with bit om3 set to 1. 44/158 DS13890 Rev 4 ST25R3920B Application information The other om bits define the technologies to be recognized. It is an extension of the Fixed listen communication mode. Once the reception of the first frame starts, the Bit rate detection mode signals an IRQ I_nfct indicating that the bit rate has been identified and the host can retrieve the related information by reading nfc_rate on Bit rate definition register. When the first frame has been fully received, the host can exit the Bit rate detection mode by setting the corresponding mode on om bits in the Mode definition register to the corresponding fixed listen communication mode. Bit d_ac_ap2p allows filtering of NFCIP-1 active frames. Low power field detection The Fixed listen communication and Bit rate detection modes can be enhanced in terms of power consumption by using the field detector in Low-power mode, putting the ST25R3920B in power-down mode (en = 0) while waiting for an external field from a peer/reader. For this mode the Bit rate detection mode or the Fixed listen communication mode have to be selected, and bits en, rx_en and tx_en in the Operation control register need to be cleared to 0. In this mode the field detector has to be configured to automatic or manual peer detection threshold. On detection of external field (I_eon) the ST25R3920B temporarily enable the oscillator and the receiver. The host needs to confirm it by setting en and rx_en option bits in the Operation control register within 10 ms. From this point on normal bit rate detection or normal target communication can be performed. PT memory The PT_Memory is used to store data for NFCIP-1 passive target and NFC-A card/listen mode. It is loaded via the host interface as described in Section 4.3. Table 6. PT_Memory address space Location Description Data usage NFCID1 (4/7/RFU bytes) 4 bytes: locations 0-3 7 bytes: locations 0-6 SENS_RES2:1 SENS_REQ response 12 SELR_L1 SEL Level 1 response. 13 SELR_L2 SEL Level 2 response 14 SELR_L3 RFU 15,16 NFCF_SC System code (SC) in SENSF_REQ(1) 17-35 212/424 polling response SENSF_RES format(2) TSN - Random numbers Slot selection, 24 4-bit random numbers are stored(3) (4) 0-9 10,11 36-47 NFC-A anticollision NFC-F anticollision 1. SENSF_RES is transmitted in case received SC=NFCF_SC or SC=0xFFFF. DS13890 Rev 4 45/158 157 Application information ST25R3920B 2. NFC-212/424k SENS_RES format, see Table 7. The last two bytes in SENSF_RES are transmitted based on the RC bytes in the SENSF_REQ. 3. The 4-bit slot numbers are sequentially used in the NFC212/424 Polling response. When only four TSN numbers remain unused, an IRQ with I_sl_wl bit is sent. 4. Depending on the number of slots in the Polling request, appropriate number of the MSB bits in the slot number is used. Table 7. NFC-212/424k SENS_RES format Byte 1 Bytes 2-9 Bytes 10-11 Bytes 12-14 Byte 15 Byte 16 Byte 17 Bytes 18-19 01h NFCID2 PAD0 PAD1 MRTICHECK MRTIUPDATE PAD2 [RD] 46/158 DS13890 Rev 4 ST25R3920B 4.3 Application information Communication with an external microcontroller The ST25R3920B communicate with a microcontroller either via an SPI interface or via an I2C interface. On both interfaces the ST25R3920B acts as a slave devices, relying on the microcontroller to initiate all communication. To notify the microcontroller of completed commands or external events (e.g. peer device field on) the ST25R3920B signal an interrupt on the IRQ pin. The ST25R3920B can also provide a configurable clock signal to the microcontroller on the MCU_CLK pin. 4.3.1 Interrupt interface There are four interrupt registers implemented in the ST25R3920B: • Main interrupt register • Timer and NFC interrupt register • Error and wake-up interrupt register • Passive target interrupt register When an interrupt condition is met the source of interrupt bit is set and the IRQ pin transitions to high. The microcontroller then reads the Main interrupt register to distinguish between different interrupt sources. After a particular interrupt register is read, its content is reset to 0. The IRQ pin transitions to low after the interrupt bit(s) that caused its transition to high has (have) been read. Note: There may be more than one interrupt bit set if the microcontroller does not immediately read the interrupt registers after the IRQ signal is set and another event causing an interrupt occurs. In this case the IRQ pin transitions to low after the last bit causing interrupt is read. When not using the INT pin, do not read the interrupt status before I_rxs while FIFO count is still zero (fifo_b equals 00). If an interrupt from a certain source is not required it can be disabled by setting the corresponding bit in the Mask interrupt registers. In case of masking a certain interrupt source the IRQ line is not set high, but the interrupt status bit is still set in IRQ status registers. Reading the IRQ status registers presents and clears also the masked interrupt bits. If some interrupts are masked, and set to 1 because of an IRQ event, and later on one of them unmasks the IRQ status bit that is already set, the IRQ line is immediately set to high. This notifies the host system that there are some interrupt events not yet read out. Note: It's recommended to implement a timeout on I_rxe to recover from corrupted frames when I_rxe is not signaled. Table 8. IRQ output Name Signal Level Description IRQ Digital output CMOS Interrupt output pin DS13890 Rev 4 47/158 157 Application information ST25R3920B IRQ line and IRQ status bits are cleared at: • Set default • Reading the IRQ status • Stop all activities • Clear FIFO. FIFO water level and FIFO status registers, FIFO reset The ST25R3920B feature a 512 byte FIFO. The control logic shifts the data during transmission, which was previously loaded by the external microcontroller to the framing block and further to the transmitter. During reception, the demodulated data is stored in the FIFO and the external microcontroller can receive data at a later moment. The FIFO status register 2 also contains two bits that indicate that the FIFO was not correctly served during TX/RX process (FIFO overflow and FIFO underflow). A FIFO overflow is set when too many data are written into the FIFO. When this bit is set during RX the external controller did not react on time on the water level IRQ and more than 512 bytes were written into the FIFO (including received CRC bytes). Consequently, the received data is corrupted. When an overflow happens during TX, it means that the controller has written more data than the FIFO size. The data to be transmitted is corrupted. A FIFO underflow is set when data were read from an empty FIFO. When this bit is set during RX the external controller read more data than was actually received. When an underflow happens during TX, it means that the controller has failed to provide the quantity of data defined in the number of transmitted bytes registers on time. FIFO pointers and FIFO status are reset at the start of each data reception (at I_rxs). They are also reset at Power-up and at commands Set Default and Clear FIFO. Reading out data from empty/cleared fifo shows data = 0. MCU_CLK The pin MCU_CLK may be used as clock source for the external microcontroller. Depending on the operation mode either a low frequency clock (32 kHz) from the RC oscillator or the clock signal derived from crystal oscillator is available on pin MCU_CLK. The MCU_CLK output pin is controlled by bits out_c and lf_clk_off in the IO configuration register 1. Bits out_c enable the use of pin MCU_CLK as clock source and define the division when the crystal oscillator is running (13.56, 6.78 and 3.39 MHz are available). Bit lf_clk_off controls the use of low frequency clock (32 kHz) when the crystal oscillator is not running. By default configuration, which is defined at power-up, the 3.39 MHz clock is selected and the low frequency clock is enabled. If the Transparent mode (see Section 4.4.13) is used the use of MCU_CLK is mandatory since a clock synchronous with the field carrier frequency is needed to implement receive and transmit framing in the external controller. The use of MCU_CLK is recommended also when the internal framing is used. Using MCU_CLK as the microcontroller clock source generates noise, synchronous with the reader carrier frequency and therefore filtered out by the receiver, while using some other incoherent clock source may produce noise that perturbs the reception. Use of MCU_CLK is also better for EMC compliance. 48/158 DS13890 Rev 4 ST25R3920B 4.3.2 Application information Communication interface selection The active communication interface is selected via the I2C_EN pin. If this pin is pulled to GND, the ST25R3920B operates in SPI mode. If this pin is pulled to VDD_D, the ST25R3920B operate in I2C mode. 4.3.3 Serial peripheral interface (SPI) The ST25R3920B hasve a standard serial peripheral interface with clock polarity of 0, a clock phase of 1, and an active low slave select signal. Communication starts with the MCU pulling BSS low. The MOSI pin is samples on the falling edge of SCLK, and the state of the MISO pin is updated on the rising edge of the SCLK signal. Data is transferred byte-wise, most significant bit first. Read and Write commands support an address auto increment to reduce communication time. Table 9 provides an overview of the SPI signals. Table 9. Serial data interface (4-wire interface) signal lines Name Signal Signal level I2C_EN Digital input Pull to GND for SPI operation BSS Digital input Active low - Slave select MOSI Digital input MISO Digital output with tristate SCLK Digital input IRQ Digital output CMOS Description Master out - Slave in (MCU → ST25R3920B) Master in - Slave out (ST25R3920B → MCU) Serial clock Active high - Interrupt output pin The MISO output is in tristate as long as no output data is available. Due to this the MOSI and the MISO can be externally shorted to create a three-wire SPI. During the time the MISO output is in tristate, it is also possible to switch on a 10 kΩ pull down by activating option bits miso_pd1 and miso_pd2 in the IO configuration register 2. Figure 12. Exchange of signals with a microcontroller MISO MISO MOSI I/O MCU MOSI ST25R3920B MOSI Bidirectional data IO signal to MCU MCU ST25R3920B Separate SPI input and output signals to MCU MISO MS69290V1 DS13890 Rev 4 49/158 157 Application information ST25R3920B The first two bits of the first byte transmitted after the BSS high to low transition define the SPI operation mode. All Read and Write modes support address auto incrementing, which means that if, after the address and first data byte some additional data bytes are sent (or read), they are written to (or read from) addresses incremented by 1. Table 10 shows available SPI operation modes. Register read and write operations are possible in all ST25R3920B operation modes. FIFO and PT_memory operations are possible in case en (bit 7 of the Operation control register) is set and the crystal oscillator is stable. Some direct commands are accepted in all operation modes, others require en (bit 7 of the Operation control register) to be set and the crystal oscillator to be stable (see Table 12). Table 10. SPI operation modes Pattern (communication bits) Mode Mode M1 M0 Trailer Related data C5 C4 C3 C2 C1 C0 A0 Data byte (or more bytes in case of A0 auto-incrementing). Register write 0 0 A5 A4 A3 A2 A1 Register read 0 1 A5 A4 A3 A2 A1 FIFO load 1 0 0 0 0 0 0 0 One or more bytes of FIFO data. PT_memory load A-config 1 0 1 0 0 0 0 0 Passive target memory, locations from 0 on. PT_memory load F-config 1 0 1 0 1 0 0 0 Passive target memory, locations from 15 on. PT_memory load TSN data 1 0 1 0 1 1 0 0 Passive target memory, locations from 36 on. The additional address allows reload of the TSN random numbers without rewriting the whole PT_memory. PT_memory read 1 0 1 1 1 1 1 1 Passive target memory, locations from 0 on. A 0 byte is presented to the passive target memory to support reading at all SPI speeds. FIFO read 1 0 0 1 1 1 1 1 One or more bytes of FIFO data Direct command 1 1 C5 C4 C3 C2 C1 C0 - Writing data to addressable registers (Write mode) Figure 13 and Figure 14 show cases of writing, respectively, a single byte and multiple bytes with auto-incrementing address. After the SPI operation mode bits, the address of register to be written is provided. Then one or more data bytes are transferred from the SPI, always MSB to LSB. The data byte is written in register on falling edge of its last clock. If the register on the defined address does not exist or it is a read only register no write is performed. 50/158 DS13890 Rev 4 ST25R3920B Application information Figure 13. SPI communication: writing a single byte BSS Raising edge indicates end of Write mode SCLK MOSI X 0 0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X Two leading bits indicate mode SCLK rising edge Data transferred from MCU SCLK falling edge Data is sampled Data is moved to address MS51644V1 Figure 14. SPI communication: writing multiple bytes BSS BSS raising edge indicates end of Write mode SCLK MOSI X 0 0 A A A A A A D D D D D D D D D D D D D D D D D D 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 D D D D D D D D D D 1 0 7 6 5 4 3 2 1 0 SCLK falling edge Data moved to address + 1 Two leading 0s indicate Write mode SCLK falling edge Data moved to address X SCLK falling edge Data moved to address + n SCLK falling edge Data moved to address + (n-1) MS51645V1 Reading data from addressable registers (Read register mode) The SPI operation mode bits are followed by the address of the register to be read. Then one or more data bytes are transferred to MISO output (MSB first) for as long as SCLK is present. This mode also supports address auto-incrementing. If there is no register at a certain address, then all 0 data is sent to MISO. Figure 15 is an example of reading a single byte. DS13890 Rev 4 51/158 157 Application information ST25R3920B Figure 15. SPI communication: reading a single byte BSS BSS raising edge indicates end of Read mode SCLK MOSI X 0 1 A5 MISO A4 A3 A2 A1 X A0 tristate D7 D6 SCLK rising edge Data moved from Address A5-A0 Two leading bits indicate Mode D5 D4 D3 D2 D1 D0 tristate SCLK falling edge Data transferred to MCU SCLK rising edge SCLK falling edge Data transferred from MCU Data is sampled MS51646V1 Read or write access to register space-B To access the register space-B the register read or write SPI sequence has to be prefixed with the byte FBh. Access to register space-B remains active until the rising edge of BSS. Loading transmitting data into FIFO Loading the transmitting data into the FIFO is similar to writing data into an addressable registers. The SPI sequence starts with SPI operation mode bits ‘10’ to indicate a FIFO operation followed by bits set to 000000b. After the FIFO mode byte at least one and up to 512 data bytes must be sent. Figure 16 shows how to load the transmitting data into the FIFO. Figure 16. SPI communication: FIFO loading BSS BSS raising edge indicates end of FIFO mode SCLK MOSI X 1 0 10 pattern indicates FIFO mode 0 0 0 0 0 0 1 to 512 bytes X Start of paylod data SCLK rising edge SCLK falling edge Data transferred from MCU Data is sampled MS51647V1 52/158 DS13890 Rev 4 ST25R3920B Application information Reading received data from FIFO Reading received data from the FIFO is similar to reading data from an addressable registers. The SPI sequence starts with SPI operation mode bits ‘10’ to indicate a FIFO operation followed by set to 011111b. After the mode byte the ST25R3920B output the data from the FIFO as long as SCLK is present and BSS is kept low. Figure 17. SPI communication: FIFO reading BSS BSS raising edge indicates end of FIFO mode SCLK MOSI X 1 0 MISO 0 1 1 1 1 1 X 1 to 512 bytes tristate 10 pattern indicates FIFO mode tristate SCLK rising edge Data moved from FIFO SCLK rising edge SCLK falling edge Data transferred from MCU Data is sampled SCLK falling edge Data transferred to MCU MS53128V1 Direct command mode Direct command mode has no arguments, so a single byte is sent. The byte starts with the SPI operation mode bits ‘11’ to indicate Direct Command Mode followed by the direct command code (see Table 12) in , MSB first. Execution of the direct command starts with the rising edge of BSS (see Figure 18). While the execution of some direct commands is immediate, there are others that start a process of certain duration (e.g. calibration, measurements). During the execution of such commands it is not allowed to start another activity over the SPI interface, an IRQ is sent. when the execution is terminated. DS13890 Rev 4 53/158 157 Application information ST25R3920B Figure 18. SPI communication: direct command /SS /SS raising edge indicates start of command execution SCLK MOSI X 1 1 Two leading 1s indicate Command Mode C5 C4 SCLK rising edge Data transferred from MCU C3 C2 C1 C0 SCLK falling edge Data is sampled X MS42466V1 Direct command chaining As shown in Figure 19, direct commands with immediate execution can be followed by another SPI mode (Read, Write or FIFO) without deactivating the BSS signal in between. Figure 19. SPI communication: direct command chaining BSS Direct command Read, Write or FIFO mode MS51649V1 Loading data in the PT_Memory (PT_Memory load) Loading data into the PT_Memory is similar to loading data into the FIFO. There are three mode patterns available to load data into three different parts of the PT_memory, as indicated in Table 10. The first byte following the mode/address pattern is stored in the location detailed in Table 10, for consecutive bytes the address is automatically incremented and data are stored to consecutive addresses. The user must take care that the number of loaded bytes fits the size of the selected PT_memory area, not to overwrite data in the following PT_memory areas. 4.3.4 I2C interface The I2C address is 50h.This interface supports: • Standard mode (100 kHz) • Fast mode (400 kHz) • Fast mode Plus (1 MHz) • High speed mode (3.4 MHz). Table 11 summarizes the I2C interface signals. 54/158 DS13890 Rev 4 ST25R3920B Application information Table 11. I2C interface and interrupt signal lines Name Signal Signal level I2C_EN Digital input MISO (SDA) Digital output SCLK (SCL) Digital input IRQ Digital output Description Pull to VDD_D for I2C operation CMOS I2C data line I2C clock Active high - Interrupt output pin Writing data to addressable registers (Register Write mode) After the I2C slave address the address of the register to be written is sent using the same Register Write mode byte as for SPI register write access. The Register Write mode byte is then followed by one or more data bytes. If more than one data byte is sent, the data is stored in subsequent registers starting form the initial register address by incrementing the target address by one for each new data byte. Figure 20 and Figure 21 show, respectively, how to write a single byte into a register and how to write multiple bytes into subsequent registers using address auto-incrementing. Figure 20. Writing a single register SCL SDA S A A A A A A 6 5 4 3 2 1 A 0 0 Slave address A C 0 K 0 A A R R R R R R D D D D D D D D C C 5 4 3 2 1 0 7 6 5 4 3 2 1 0 K K Register address P Data MS51653V2 Figure 21. Writing register data with auto-incrementing address SCL SDA S A A A A A A A A A A D D D D D D D D R R R R R R 0 C 0 0 C C 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 5 4 3 2 1 1 K K K Slave address Register address Data moved to address + 0 A D D D D D D D D C 7 6 5 4 3 2 1 0 K P Data moved to address + n MS51654V2 Reading data from addressable registers (Register Read mode) After the I2C slave address the address of the register to be read is sent using the same Register Read mode byte of the SPI register read access. After the Register Read mode byte the ST25R3920B sends data bytes to the SDA output as long as the MCU keeps SCL. The Register Read mode also supports address auto-incrementing. If the addressed register does not exist, all 0 data is sent to SDA. DS13890 Rev 4 55/158 157 Application information ST25R3920B Figure 22 shows how to read a single byte from a register. Figure 22. Reading a single byte from a register SCL SDA S A N A A D D D D D D D D A A A A A A A A A A A A A A R R R R R R 1 C A C S 0 C 0 1 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 5 4 3 2 1 0 K K K K Slave address Register address Slave address P Data MS51655V2 Loading data into FIFO or PT_Memory (FIFO/PT_Memory load) Loading data into FIFO or PT_Memory is similar to writing data into addressable registers. After the I2C slave address the mode byte to trigger a load of the FIFO or selected PT_Memory area is sent (see Table 10) followed by the data bytes to be loaded. Figure 23 shows how to load data into the FIFO. Figure 23. FIFO load SCL SDA S A A A A A A A A A A D D D D D D D D C 0 C 1 0 0 0 0 0 0 0 C 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 K K K Slave address FIFO load Data A D D D D D D D D C 7 6 5 4 3 2 1 0 K P Data MS51656V1 Reading data from the FIFO Reading data from the FIFO is similar to reading data from addressable registers. After the I2C slave address the mode byte to trigger a read of the FIFO is sent. After receiving the FIFO read mode byte the ST25R3920B send data bytes from the FIFO for as long as the MCU keeps reading the bus. 56/158 DS13890 Rev 4 ST25R3920B Application information Figure 24. FIFO read SCL SDA S A A A A A A A A A 0 C 1 0 0 1 1 1 1 1 C 6 5 4 3 2 1 0 K K Slave address S A N A A A A A A A D D D D D D D D 1 C A 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 K K FIFO read Slave address P Data MS51657V1 Direct command mode After the I2C slave address the mode byte to trigger a direct command is sent. As for SPI some direct commands take some time to execute and no I2C access to the ST25R3920B must be performed until the execution of the direct command is completed. All such direct commands send an interrupt upon completion to notify the MCU that the I2C bus can be used again. Figure 25. Sending a direct command SCL SDA S A A A A A A A 6 5 4 3 2 1 0 A C 1 1 K Slave address C C C C C C 5 4 3 2 1 0 A C P K Direct command byte MS51658V1 I2C access to register space-B To access the register space-B, byte FBh has to be inserted between the I2C slave address and the register read or write mode byte. Access to register space-B remains active until an I2C Stop Condition is received. Figure 26. Read and Write mode for register space-B access Write to register space B S Slave Register A FBh A Data 0 A Data 1 A address W address ... Data N A P Read from register space B S Slave Register A FBh A address W address Sr Slave A Data 0 address R A Data 1 A ... Data N N P Legend: S: Start, Sr: repeated Start, A: ACK, N: NAK, P: Stop. DS13890 Rev 4 57/158 157 Application information ST25R3920B I2C: transition to and termination of the Transparent mode When the transparent mode command is received via I2C, the chip interface lines are switched to the Analogue front end as described in Section 4.4.13: Transparent mode. Once in transparent mode the BSS signal is used to distinguish between I2C communication and transparent mode data as follows: 1. the BSS line must be set high before entering the transparent mode, and then kept high during the Transparent mode 2. the Transparent mode is terminated when the BSS line is set to low, followed by at least one SCL clock pulse 3. after the termination of the transparent mode the I2C interface can be used again. I2C: master reads slave immediately after the first byte If the I2C master omits the mode byte and reads the ST25R3920B immediately after the slave address, then, as shown in Figure 27, it will first output the byte FFh, followed by a register dump starting at addres 01h. Figure 27. I2C master reads slave immediately after the first byte S Slave address R A Data FFh A Data register 01h A ... Data register n N P Legend: S: Start, A: ACK, N: NAK, P: Stop. This mode is incorporated for an easier the detection of I2C devices, but is not intended to be used in normal operation. 4.4 Direct commands Table 12. List of direct commands Code (hex) Name Comments Chaining Interrupt after termination Operation mode(1) C0, C1 Set default Puts the ST25R3920B into powerup state No No All C2, C3 Stop all activities Stops all activities: transmission, reception, direct command execution, timers Yes No en C4 Transmit with CRC Starts a transmit sequence with automatic CRC generation Yes No en C5 Transmit without CRC Starts a transmit sequence without automatic CRC generation Yes No en C6 Transmit REQA Transmits REQA command (ISO14443A mode only) Yes No en, tx_en C7 Transmit WUPA Transmits WUPA command (ISO14443A mode only) Yes No en, tx_en C8 NFC initial field ON Performs Initial RF Collision avoidance and switches on the field Yes Yes en 58/158 DS13890 Rev 4 ST25R3920B Application information Table 12. List of direct commands (continued) Code (hex) Name Comments Chaining Interrupt after termination Operation mode(1) C9 NFC response field ON Performs Response RF Collision avoidance and switches on the field Yes Yes en CD Go to sense (Idle) Puts the passive target logic into Sense (Idle) state Yes No en, rx_en CE Go to sleep (Halt) Puts the passive target logic into Sleep (Halt) state Yes No en, rx_en D0 Mask receive data Stops receivers and RX decoders Yes No All D1 Unmask receive data Starts receivers and RX decoders Yes No All D2 Change AM modulation state Changes AM modulation state Yes No en, tx_en D3 Measure amplitude Measures the amplitude of the signal present on RFI inputs and stores the result in the A/D converter output register No Yes All(2) D5 Reset RX gain Resets receiver gain to the value in the Receiver configuration register 4 No No en D6 Adjust regulators Adjusts supply regulators according to the current supply voltage level No Yes en D8 Calibrate driver timing Starts the driver timing calibration according to the setting in the TX driver timing display register No No en D9 Measure phase Measures the phase difference between the signal on RFO and RFI No Yes All(2) DA Clear RSSI Clears the RSSI bits in the RSSI display register and restarts the measurement Yes No en DB Clear FIFO Clears FIFO Yes No en DC Enter Transparent mode Enters in Transparent mode No No en DF Measure power supply - No Yes en E0 Start General purpose timer - Yes No en E1 Start Wake-up timer - Yes No All except wu E2 Start Mask-receive timer Yes No en E3 Start No-response timer - Yes No en E4 Start PPON2 timer - Yes No en E8 Stop No-response timer - Yes No en EA Trigger RC calibration - No Yes en Starts the mask-receive timer and squelch operation DS13890 Rev 4 59/158 157 Application information ST25R3920B Table 12. List of direct commands (continued) Code (hex) Name Comments Chaining Interrupt after termination Operation mode(1) FB Register space-B access Enables R/W access to register Space-B Yes No all FC Test access Enable R/W access to Test register Yes No All - - - Other RFU codes Not used 1. Defines which Operation control register bits have to be set in order to accept a particular command. 2. Measure amplitude and Measure phase can be used directly from power down mode. In this case the command temporarily enables the oscillator. 4.4.1 Set default This direct command puts the ST25R3920B in the same state as power-up initialization: • performs Stop all activities command • resets all registers to their default state • clears all collision bits Results of previous calibration and adjust commands are lost. No IRQ due to termination of direct command is produced. 4.4.2 Stop all activities This direct command stops any ongoing activities: • performs Clear FIFO command • stops data transmission and reception • stops all timers, including FDT timer • clears IRQ line an IRQ status bits • stops Field ON commands If Stop All Activities is received during RF collision avoidance the field detection is terminated and field is not set, consequently no interrupts are sent • stops automatic field ON (same as above) • stops automatic field OFF If Stop All Activities is received during waiting for automatic field off via GPT, the field remains on • nfc_ar is set to 01b, then it clears the awareness that there was a previous reception • stops Temporary Enable This command does not update any register apart from the FIFO status registers. Therefore it does not disable the field detector in CE mode (if it was enabled), and it does not switch off the field (if it was enabled). 4.4.3 Clear FIFO This direct command clears the FIFO and the FIFO status registers. It does not clear the IRQ line or IRQ status bits. 60/158 DS13890 Rev 4 ST25R3920B Application information To prepare a transmission send this command first before writing data into the FIFO. If a Clear FIFO command is sent during an ongoing data transmission, then the data transmission is aborted and FIFO and FIFO status registers are cleared. 4.4.4 Transmit commands The transmit direct commands are used to start a data transmission from the ST25R3920B. They switch the device to reception mode after the transmission is completed. Before sending commands Transmit with CRC and Transmit without CRC, direct command Clear FIFO has to be sent, followed by the definition of the number of transmitted bytes and writing data to be transmitted in FIFO. Use the direct commands Transmit REQA and Transmit WUPA to transmit ISO14443A short frame commands REQA and WUPA respectively. It is not necessary to send the direct command Clear FIFO before these two commands. If the antcl bit is set, then the number of valid bits in the last byte must be set to 0 (nbtx in the Number of transmitted bytes register 2) prior to the direct command Transmit REQA or Transmit WUPA. The direct commands Transmit REQA and Transmit WUPA automatically disable the CRC check of the response frame. The CRC check is enabled again after any of the below conditions: • Transmit with CRC direct command • Mask receive data direct command • No Response timer expires If the direct command Transmit without CRC is used in Felica™ mode the Length and CRC bytes are skipped. After the preamble and Sync bytes the raw FIFO content is transmitted. A transmit length nbtx ≥1 must be used. 4.4.5 NFC field ON commands The NFC field ON direct commands are used to perform RF Collision Avoidance. The external field detector must be enabled for these commands to work correctly. Note: It is recommended that bits en_fd_c of the operation control register are set to 01b in Reader mode. In the NFCIP-1 active communication (AP2P), the bits en_fd must be set to 11b to enable an external field detector automatically. So that the external field detector automatically exchanges its threshold between collision avoidance and peer detection level, as needed, during operation. Collision avoidance and peer detection levels must be tuned (in accordance with environmental temperature) to ensure good working conditions. In AP2P mode, a minimum collision avoidance and peer detection activation threshold of 205 mVPP is recommended for bits rfe_t and trg_l of the external field detector activation threshold register. To determine whether an external field is present the ST25R3920B compares the RF voltage level on the RFI1 pin with the collision avoidance threshold defined in the External field detector activation threshold register. If no external field is detected, then the ST25R3920B transmitter is switched on automatically (bit tx_en in the Operation control register is set) and an I_apon IRQ is signaled. After the RF guard time defined in the NFC field on guard timer register has passed an I_cat IRQ is signaled. At this point the controller can initiate a data transmission using a transmit command. DS13890 Rev 4 61/158 157 Application information ST25R3920B If an external field is detected a I_cac IRQ is signaled, and the ST25R3920B transmitter stays off. The direct command NFC initial field ON performs an Initial collision avoidance according to NFCIP-1 standard, and the direct command NFC response field ON performs a Response collision avoidance according to NFCIP-1 standard. See Figure 28, Figure 29 and Table 13 for details on the timing of these commands. Figure 28. Direct command NFC initial field ON RF on TRFW Start TIDT n x TRFW TIRFG MS42450V1 Figure 29. Direct command NFC response field ON RF on TRFW Start TADT n x TRFW TARFG MS42451V1 Table 13. Timing parameters of NFC field ON commands Parameter Symbol Value Unit Initial delay time TIDT 4096 / fc NFC initial field ON RF waiting time TRFW 512 / fc n = 0…3 based on nfc_n Initial guard time TIRFG 75 µs + NFC field on guard time s Active delay time TADT 768 / fc NFC response field ON RF waiting time TRFW 512 / fc n = 0…3 based on nfc_n in Auxiliary definition register TARFG 75 µs + NFC field on guard time Active guard time 62/158 s DS13890 Rev 4 Notes NFC field on guard time defined in the NFC field on guard timer register. NFCIP-1 TIRFG requirement: 5 …35 ms NFC Field ON guard time defined in the NFC field on guard timer register. NFCPIP-1 TARFG requirement: > 75 µs + NFC field ON guard times (1024 / fc) ST25R3920B 4.4.6 Application information Mask receive data and Unmask receive data The direct command Mask receive data disables processing of the receiver output by the RX decoders, RSSI measurement, and AGC operation. The direct command Unmask receive data enables processing of the received data by the RX decoders, RSSI measurement and AGC operation. A common use of this command is to re-enable the receiver operation after it was masked by the command Mask receive data. If the Mask receive timer is still running while the direct command Unmask receive data is received, reception is enabled, and the Mask receive timer is reset. In passive target (card emulation) mode, the Unmask receive data command prepares the RX decoders for a new data reception and clears the internal FDT timer. In passive target mode, this direct command must be used only if no further transmissions from the ST25R3920B is planned and the devices have to wait for the next command to be received. 4.4.7 Change AM modulation state This command changes the AM modulation state from unmodulated to modulated, and vice versa. This can be used to measure the AM modulation index with the direct command Measure amplitude. 4.4.8 Measure amplitude This command measures the amplitude of the RF signal on the RFI inputs and stores the result in the A/D converter output register. This command enables the transmitter and amplitude detector. The transmitter drives the antenna, and the amplitude detector converts the differential RF signal received back between RFI1 and RFI2 into a proportional DC voltage. This DC voltage is converted with the A/D converter in absolute conversion mode into an 8-bit value and stored in the A/D converter output register. The amplitude detector conversion gain is 0.6 VinPP / Vout referenced to the RF signal on a single RFI pin. Thus, one LSB of the A/D converter output represents 13.02 mVPP on either of the RFI inputs. Note: The maximum allowed voltage level on an RFI pin is 3 VPP. This results in 1.8 V output DC voltage of the amplitude detector and produces a value of E6h after A/D conversion. Duration time: 25 μs max. 4.4.9 Reset RX gain This command initializes the AGC, Squelch and RSSI block and resets the gain reduction to the value set in Receiver configuration register 4. Sending this command also stops any ongoing squelch process. 4.4.10 Adjust regulators When this command is sent, then the transmitter and receiver are enabled to ensure a high current draw and the regulated voltage VDD_RF is set 250 mV below the power supply level of VDD_TX. Before sending the adjust regulator command it is required to toggle the bit reg_s by setting it first to 1 and then reset it to 0. After the adjustment is completed the state of the transmitter and receiver prior to the command execution is restored (either enabled or disabled). DS13890 Rev 4 63/158 157 Application information ST25R3920B Duration time: 5 ms max. This command is not accepted if external definition of the regulated voltage is selected in the Regulator voltage control register (bit reg_s is set to 1). 4.4.11 Measure phase This command measures the phase difference between the signals on the RFO outputs and the signals on the RFI inputs and stores the result in the A/D converter output register. This command enables the transmitter and phase detector, and performs an A/D conversion of the output of the phase detector with the A/D converter in relative mode. The phase measurement results can be calculated using the following formulas: • 0 ≤ Φ ≤ 17º: result = 255 • 17 < Φ < 163º: angle [º] = 17 + (1 -result / 255) * 146 • 163 ≥ Φ ≥ 180º: result = 0 Duration time: 25 μs max. 4.4.12 Clear RSSI The receiver automatically clears the RSSI bits in the RSSI display register and starts a new measurement of the RSSI when a new reception is started (e.g. after a Transmit direct command). Since the RSSI bits store the peak value (peak-hold type) eventual variation of the receiver input signal will not be followed (this may happen in case of a long message or test procedure). The direct command Clear RSSI clears the RSSI bits in the RSSI display register, and restarts the RSSI measurement. This allows to obtain multiple RSSI measurements during a single reception. 4.4.13 Transparent mode This command sets the receiver and transmitter into the transparent mode. The device enters the transparent mode on the rising edge of the BSS signal of the SPI frame used to send the direct command. The transparent mode is maintained as long as signal BSS is kept high, that is, the following SPI command sent from the microcontroller will automatically stop the transparent mode. 4.4.14 Measure power supply This command measures the power supply. The bits mpsv in the Regulator voltage control register select which signal is measured. The result of the measurement is stored in the A/D converter output register. For power supply measurements the selected supply input voltage is divided by three and measured with the A/D converter in absolute mode. This leads to a resolution of 23.4 mV per LSB for all power supply measurements. Duration time: 25 μs max. 4.4.15 Trigger RC calibration The command triggers the RC calibration cycle for the active waveshaping filter constant. The result can be read in AWS time 6 register and IRQ I_dct signals end of calibration. 64/158 DS13890 Rev 4 ST25R3920B Application information The Trigger RC calibration command should be triggered once after device power-on and set default direct command. The RC calibration should not be triggered during data transmission or reception. 4.4.16 Test access The devices do not have dedicated test pins. A direct command Test Access is used to enable RW access of test registers and entry in different test modes. Pins TAD1 and TAD2 are used as test pins. Test mode entry and access to test registers Test registers are not part of the normal register address space. After sending direct command Test Access, test registers can be accessed using normal Read/Write register command. Access to test registers is possible in a chained command sequence where command Test Access is sent first, followed by read/write access to test registers using auto increment feature. Test register are set to default state at power-up. Analog test and observation register 1 Address: 01h Type: RW Table 14. Analog test and observation register 1 Bit Name Default Function 7 tana7 0 - Reserved 6 tana6 1 - Reserved 5 tana5 0 - Reserved 4 - 0 - Reserved 5 tana3 0 4 tana2 0 3 tana1 0 0 tana0 0 See Table 15 Comments These test modes are also intended for observation in normal mode. Other modes of this register are also available when analog test mode is not set. Table 15. Test access register - Signal selection of TAD1 and TAD2 pins(1) tana3:0 (hex) Pin TAD1 Pin TAD2 Type Functionality Type 1 A0 Analog output of AM channel (before digitizer) D0 Digital output of AM channel (after digitizer) 2 A0 Analog output of PM channel (before digitizer) D0 Digital output of PM channel (after digitizer) 3 A0 Analog output of AM channel (before digitizer) A0 Analog output of PM channel (before digitizer) 4 A0 Analog output of AM correlation signal A0 Analog output of PM correlation signal DS13890 Rev 4 Functionality Comment Normal operation (reader) 65/158 157 Application information ST25R3920B Table 15. Test access register - Signal selection of TAD1 and TAD2 pins(1) (continued) tana3:0 (hex) 5 Pin TAD1 Type Pin TAD2 Functionality Type A0 D0 Tag demodulator OOK digital out D0 Tag demodulator ASK digital out Tag demodulator analog 6 A0 Functionality Comment Normal operation (tag) m_amp_ana and m_phase_ana in Rs-A, Reg 3Bh define which is active 7 A0 Analog voltage of amplitude measurement D0 Analog voltage of phase measurement B D0 Digital output of AM correlation data signal D0 Digital output of AM correlation collision/start detection signal - C D0 Digital output of PM correlation data signal D0 Digital output of PM correlation collision/start detection signal - D A0 Analog output of AM correlation signal A0 Correlation digitizing threshold for AM channel - E A0 Analog output of PM correlation signal A0 Correlation digitizing threshold for PM channel - 1. Set en=1 and rx_en=1 in Operation control register before enabling tana test modes. 4.5 Registers The ST25R3920B has two register spaces, each of them consists of up to 64 registers with address ranging from 00h to 3Fh: 1. register space A (Rs-A), see Table 16 2. register space B (Rs-B), see Table 17. There are two types of registers implemented in the ST25R3920B: 1. configuration registers: used to configure the device, can be written and read through the SPI or I2C interfaces 2. display registers: read only (RO), contain information about the state of the device. Registers are set to their default value at power-up and after sending the direct command Set default. Bits set as RFU must be kept at their reset values unless otherwise specified. Table 16. List of registers - Space A Type IO configuration 66/158 Address (hex) Register space A (Rs-A) 00 IO configuration register 1 01 IO configuration register 2 DS13890 Rev 4 ST25R3920B Application information Table 16. List of registers - Space A (continued) Type Operation control and mode definition Protocol configuration Receiver configuration Timer definition Interrupt and associated reporting Definition of number of transmitted bytes Address (hex) Register space A (Rs-A) 02 Operation control register 03 Mode definition register 04 Bit rate definition register 05 ISO14443A and NFC 106kb/s settings register 06 ISO14443B settings register 1 07 ISO14443B and FeliCa settings register 08 NFCIP-1 passive target definition register 09 Stream mode definition register 0A Auxiliary definition register 0B Receiver configuration register 1 0C Receiver configuration register 2 0D Receiver configuration register 3 0E Receiver configuration register 4 0F Mask receive timer register 10 No-response timer register 1 11 No-response timer register 2 12 Timer and EMV control register 13 General purpose timer register 1 14 General purpose timer register 2 15 PPON2 field waiting register 16 Mask main interrupt register 17 Mask timer and NFC interrupt register 18 Mask error and wake-up interrupt register 19 Mask passive target interrupt register 1A Main interrupt register 1B Timer and NFC interrupt register 1C Error and wake-up interrupt register 1D Passive target interrupt register 1E FIFO status register 1 1F FIFO status register 2 20 Collision display register 21 Passive target display register 22 Number of transmitted bytes register 1 23 Number of transmitted bytes register 2 24 Bit rate detection display register DS13890 Rev 4 67/158 157 Application information ST25R3920B Table 16. List of registers - Space A (continued) Type Address (hex) A/D converter output Register space A (Rs-A) 25 A/D converter output register 26 Antenna tuning control register 1 27 Antenna tuning control register 2 Antenna driver and modulation 28 TX driver register 29 Passive target modulation register External field detector threshold 2A External field detector activation threshold register 2B External field detector deactivation threshold register Regulator 2C Regulator voltage control register 2D RSSI display register 2E Gain reduction state register 31 Auxiliary display register 32 Wake-up timer control register 33 Amplitude measurement configuration register 34 Amplitude measurement reference register 35 Amplitude measurement auto-averaging display register 36 Amplitude measurement display register 37 Phase measurement configuration register 38 Phase measurement reference register 39 Phase measurement auto-averaging display register 3A Phase measurement display register 3F IC identity register Antenna calibration Receiver state display Auxiliary display Wake-up IC identity Table 17. List of registers - Space B Type Protocol configuration Receiver configuration Timer definition Antenna driver and modulation External field detector threshold 68/158 Address (hex) Register space B (Rs-B) 05 EMD suppression configuration register 06 Subcarrier start timer register 0B P2P receiver configuration register 1 0C Correlator configuration register 1 0D Correlator configuration register 2 0F Squelch timer register 15 NFC field on guard timer register 28 Auxiliary modulation setting register 29 TX driver timing register 2A Resistive AM modulation register 2B TX driver timing display register DS13890 Rev 4 ST25R3920B Application information Table 17. List of registers - Space B (continued) Type Regulator Active Waveshaping Address (hex) Register space B (Rs-B) 2C Regulator display register 30 Overshoot protection configuration register 1 31 Overshoot protection configuration register 2 32 Undershoot protection configuration register 1 33 Undershoot protection configuration register 2 2E AWS Config 1 register 2F AWS Config 2 register 34 AWS time 1 register 35 AWS time 2 register 36 AWS time 3 register 37 AWS time 4 register 38 AWS time 5 register 39 AWS time 6 register DS13890 Rev 4 69/158 157 Application information 4.5.1 ST25R3920B IO configuration register 1 Register space: A Address: 00h Type: RW Table 18. IO configuration register 1 Bit Name Default Function 7 single 0 0: Differential antenna driving 1: Only one RFO driver will be used Chooses between single and differential antenna driving. 6 rfo2 0 0: RFO1, RFI1 1: RFO2, RFI2 Chooses which output driver and which input will be used in case of single driving. 5 i2c_thd1 0 4 i2c_thd0 0 3 RFU 0 2 1 0 70/158 out_cl1 out_cl0 lf_clk_off 0 0 0 Comments I2C tHD: non hs-modes / hs-modes 00: 380 ns / 160 ns 01: 180 ns / 160 ns 10: 180 ns / 70 ns 11: 100 ns / 70 ns out_cl1 out_cl0 0 0 0 1 1 0 1 1 - - MCU_CLK Selection of clock frequency on MCU_CLK output in case Xtal 6.78 MHz oscillator is running. With “11” MCU_CLK output is permanently 13.56 MHz low. 3.39 MHz Disabled 0: LF clock on MCU_CLK 1: No LF clock on MCU_CLK DS13890 Rev 4 By default the 32 kHz LF clock is present on MCU_CLK output when Xtal oscillator is not running and the MCU_CLK output is not disabled. ST25R3920B 4.5.2 Application information IO configuration register 2 Register space: A Address: 01h Type: RW Table 19. IO configuration register 2 Bit Name Default 7 sup3V 0 0: 5 V supply 1: 3.3 V supply Set to 0 for 3.6 V < VDD ≤ 5.5 V Set to 1 for 2.4 V ≤ VDD ≤ 3.6 V 0 0: Enable VDD_D regulator 1: Disable VDD_D regulator Used for low cost applications. When this bit is set: – at 3 V or 5 V supply VDD_D and VDD_A must be shorted externally The AAT D/A converters are enabled if both aat_en and en are set. If only aat_en is set and en is cleared, then the AAT outputs are set to a fixed value. Note that for the fixed value to operate, en must have been set to 1 at least once, prior to having en = 0. 6 vspd_off Function 5 aat_en 0 0: Disable AAT D/A 1: Enable AAT D/A 4 miso_pd2 0 1: Pull-down on MISO, when BSS is low and MISO is not driven by the ST25R3920B. 0 1: Pull-down on MISO when BSS is high 3 2 miso_pd1 io_drv_lvl Comments Valid only in SPI mode. 0 0: Normal IO driver level 1: Increase IO driving level Increases IO driver strength of MISO, MCU_CLK an IRQ. Recommended to set to 1 for all I2C operation, and for SPI operation if VDD_IO < 3.3 V. Selects non modulated RF voltage level reference of the VDD_AM voltage regulator. Set to 1 when Regulator modulation is intended (reg_am=1) and big capacitor is connected to VDD_AM (2.2 uF) 1 am_ref_rf 0 0: VDD_AM regulator reference from VDD_DR 1: VDD_AM regulator reference from VDD_RF 0 act_amsink 0 0: active sink disabled 1: active sink enabled DS13890 Rev 4 71/158 157 Application information 4.5.3 ST25R3920B Operation control register Address: 02h Type: RW Table 20. Operation control register(1) Bit Name Default Function Comments 7 en 0 1: Enables oscillator and regulator (Ready mode) - 6 rx_en 0 1: Enables Rx operation - 5 rx_chn 0 0: Both, AM and PM, channels enabled 1: One channel enabled If only one Rx channel is enabled, selection is done by the Receiver configuration register 1 bit ch_sel. 0 0: Automatic channel selection 1: Manual channel selection If both Rx channels are enabled, chooses the method of channel selection, manual selection is done by the Receiver configuration register 1 bit ch_sel. 4 rx_man 3 tx_en 0 1: Enables Tx operation This bit is automatically set by NFC Field ON commands and reset in NFC active communication modes after transmission is finished. 2 wu 0 1: Enables Wake-up mode According to settings in Wake-up timer control register. 00: External field detector off. 01: Manually enable external field detector with collision avoidance detection threshold. 10: Manually enable external field detector with peer detection threshold. 11: Enable external field detector automatically. 01: External field detector with collision avoidance detection must be used in R/W mode when using NFC field on commands. 11: External field detector with peer detection/collision avoidance threshold activated automatically must be used in NFCIP-1 active communication (AP2P) and Passive target modes. en_fd_c ≠ 0 and other bits in Operation control register set to 0 put the device in Low power initial NFC mode. 1 en_fd_c1 0 0 en_fd_c0 0 1. Default setting takes place at power-up only. 72/158 DS13890 Rev 4 ST25R3920B 4.5.4 Application information Mode definition register Register space: A Address: 03h Type: RW Table 21. Mode definition register(1) Bit Name Default 7 targ 0 6 om3 0 5 om2 0 4 om1 0 3 om0 1 2 tr_am 0 1 nfc_ar1 0 0 nfc_ar0 0 Function Comments 0: Initiator 1: Target - Refer to Table 22 and Table 23 Selection of operation mode. Different for initiator and target modes. 0: OOK 1: AM Selects RF modulation mode. 00: Off 01: Automatic field on after any reception (including errors) 10: Always after peer field-off 11: RFU Automatically starts the Response RF collision avoidance(2). 1. Register can be written only in case crystal clock is present and stable (oscok = 1). 2. Refer to the note in Section 4.4.5: NFC field ON commands for handling these bits. Table 22. Initiator operation modes(1) om3 om2 om1 om0 0 0 0 0 NFCIP-1 active communication 0 0 0 1 ISO14443A 0 0 1 0 ISO14443B 0 0 1 1 FeliCa™ 0 1 0 0 NFC Forum Type 1 tag (Topaz) 1 1 1 0 Sub-carrier stream mode 1 1 1 1 BPSK stream mode Other combinations Comments RFU 1. If a non supported operation mode is selected the Tx/Rx operation is disabled. Table 23. Target operation modes(1)(2) om3 om2 om1 om0 Comments 0 0 0 1 ISO14443A passive target mode 0 1 0 0 FeliCa™ passive target mode DS13890 Rev 4 73/158 157 Application information ST25R3920B Table 23. Target operation modes(1)(2) (continued) om3 om2 om1 om0 0 1 1 1 NFCIP-1 active communication mode x Bit rate detection mode – om2: enable FeliCa™ bit rate detection mode – om1: RFU – om0: enable ISO14443A bit rate detection mode 1 x x Other combinations Comments Not allowed 1. The nfc_f0 = 1 must not be set in Bit rate detection mode (see Table 25). 2. When in Passive target and Bit rate detection modes, the pt_res setting is used to generate the RF field (high ohmic setting of pt_res can prevent RF field generation). 74/158 DS13890 Rev 4 ST25R3920B 4.5.5 Application information Bit rate definition register Register space: A Address: 04h Type: RW Table 24. Bit rate definition register Bit Name Default Function Comments 7 RFU 0 - 6 RFU 0 - 5 tx_rate1 0 4 tx_rate0 0 3 RFU 0 2 RFU 0 1 rx_rate1 0 0 rx_rate0 0 Selects bit rate for Tx. Refer to Table 25 Selects bit rate for Rx. Table 25. Bit rate coding(1) rate3 rate2 rate1 rate0 Bit rate (kbit/s) Comments 0 0 0 0 fc/128 (~106) - 0 0 0 1 fc/64 (~212) - 0 0 1 0 fc/32 (~424) - 0 0 1 1 fc/16 (~848) - Other combinations - Not used 1. If a non supported bit rate is selected the Tx/Rx operation is disabled. DS13890 Rev 4 75/158 157 Application information 4.5.6 ST25R3920B ISO14443A and NFC 106kb/s settings register Register space: A Address: 05h Type: RW Table 26. ISO14443A and NFC 106kb/s settings register Bit Name Default Function Comments 7 no_tx_par 0 1: No parity bit is generated during Tx 6 no_rx_par 0 When set to 1 received bit stream is put in the 1: Receive and put in FIFO also FIFO, no parity and CRC detection is done(1). the parity bit Supported only for 106 kbit/s data rate. 5 nfc_f0 0 Adds SB (F0) and LEN bytes during Tx and skip 1: Support of NFCIP-1 Transport SB (F0) byte during Rx. Frame format Must not be set in bit rate detection mode. 4 p_len3 0 3 p_len2 0 2 p_len1 0 1 p_len0 0 0 antcl 0 Data stream is taken from FIFO, transmit to be done using command Transmit Without CRC(1). Refer to Table 27 Modulation pulse width, defined in number of 13.56 MHz clock periods. 0: Standard frame 1: ISO14443 anticollision frame Must be set to 1 for reception of ISO14443A bit oriented anticollision frames in reader mode. Must be set to 0 for all other frames and modes. 1. Supported in reader modes only, not supported in card emulation modes. Table 27. Modulation pulse width p_len3 p_len2 p_len1 p_len0 Stream mode (ISO15693) ISO14443A modulation pulse width in number of 1 / fc for different bit rates (1) fc/128 fc/64 fc/32 fc/16 fc 0 1 1 1 42 - - - - 0 1 1 0 41 24 - - - 0 1 0 1 40 23 - - - 0 1 0 0 39 22 13 - - 0 0 1 1 38 21 12 8 - 0 0 1 0 37 20 11 7 - 0 0 0 1 36 19 10 6 - 0 0 0 0 35 18 9 5 128 1 1 1 1 34 17 8 4 120 1 1 1 0 33 16 7 3 112 76/158 DS13890 Rev 4 ST25R3920B Application information Table 27. Modulation pulse width (continued) p_len3 p_len2 p_len1 Stream mode (ISO15693) ISO14443A modulation pulse width in number of 1 / fc for different bit rates p_len0 (1) fc/128 fc/64 fc/32 fc/16 fc 1 1 0 1 32 15 6 2 104 1 1 0 0 31 14 5 - 96 1 0 1 1 30 13 - - 88 1 0 1 0 29 12 - - 80 1 0 0 1 28 - - - - 1 0 0 0 27 - - - - 1. It applies for stx=0 and om=14 only. 4.5.7 ISO14443B settings register 1 Register space: A Address: 06h Type: RW Table 28. ISO14443B settings register 1 Bit Name Default 7 egt2 0 6 egt1 0 5 egt0 0 4 sof_0 0 0: 10 etu 1: 11 etu SOF, number of etu with logic 0 3 sof_1 0 0: 2 etu 1: 3 etu SOF, number of etu with logic 1 2 eof 0 0: 10 etu 1: 11 etu EOF, number of etu with logic 0 0: SOF and EOF defined by sof_0, sof_1, and eof bit 1: SOF 10.5 etu logic 0, 2.5 etu logic 1, EOF: 10.5 etu logic 0 Sets SOF and EOF settings in middle of specification. 1 half 0 0 RFU - Function Comments egt2 egt1 egt0 Number of etu 0 0 0 0 0 0 1 1 ... ... ... ... EGT defined in number of etu 1 1 0 6 1 1 1 7 - DS13890 Rev 4 - 77/158 157 Application information 4.5.8 ST25R3920B ISO14443B and FeliCa settings register Register space: A Address: 07h Type: RW Table 29. ISO14443B and FeliCa settings register Bit Name Default Function Comments 7 tr1_1 0 6 tr1_0 0 5 no_sof 0 1: No SOF PICC to PCD Supports PCD capability for suppression of SOF from PICC to PCD according to ISO14443 4 no_eof 0 1: No EOF PICC to PCD Supports PCD capability for suppression of EOF from PICC to PCD according to ISO14443 3 RFU 0 - - 2 RFU 0 - - 1 f_p1 0 0 f_p0 0 Refer to Table 30 - 00: 48 01: 64 10: 80 11: 96 FeliCa™ preamble length (valid also for NFCIP-1 active communication bit rates 212 and 424 kb/s) Table 30. Minimum TR1 codings Minimum TR1 for a PICC to PCD bit rate tr1_1 tr1_0 fc/128 78/158 >fc/128 0 0 80 / fs 0 1 1 0 Not used 1 1 Not used 64 / fs DS13890 Rev 4 32 / fs ST25R3920B 4.5.9 Application information NFCIP-1 passive target definition register Register space: A Address: 08h Type: RW Table 31. NFCIP-1 passive target definition register Bit Name Default 7 fdel3 0 6 fdel2 0 5 fdel1 0 4 fdel0 0 3 d_ac_ap2p 2 1 0 Function Comments PCD to PICC FDT compensation. Frame compensation defined as fdel*1 / fc Valid for NFC-A CE mode – fdel = 0: Nominal FDT time in produced in logic. – fdel > 0: Shortens the FDT provided by logic. Due to signal processing delays fdel = 2 is expected to be a good setting (best value dependents also on filter and antenna). 0 0: Enable AP2P frame recognition 1: Disable AP2P frame recognition - d_212/424_1r 0 0: Enable automatic SENSF_RES 1: Disable automatic SENSF_RES RFU 0 RFU 0 0: Enable automatic anti-collision in NFC-A 1: Disable automatic anti-collision in NFC-A d_106_ac_a DS13890 Rev 4 Disables the automatic responses in passive target mode, and completely operates via FIFO. 79/158 157 Application information 4.5.10 ST25R3920B Stream mode definition register Register space: A Address: 09h Type: RW Table 32. Stream mode definition register Bit Name Default Function Comments 7 RFU 0 - - 6 scf1 0 5 scf0 0 4 scp1 0 3 scp0 0 2 stx2 0 1 stx1 0 0 stx0 0 Sub-carrier frequency definition for Sub-carrier stream mode. Refer to Table 33 scp1 scp0 Number of pulses 0 0 RFU 0 1 RFU 1 0 4 1 1 8 Number of sub-carrier pulses in report period for Sub-carrier stream mode. Definition of time period for Tx modulator control (for Sub-carrier and BPSK stream mode). Refer to Table 34 Table 33. Sub-carrier frequency definition for Sub-Carrier stream mode scf1 scf0 Sub-Carrier mode BPSK mode 0 0 - fc/16 (848 kHz) 0 1 fc/32 (424 kHz) 1 0 - 1 1 - RFU Table 34. Definition of time period for Stream mode Tx modulator control 80/158 stx2 stx1 stx0 Time period 0 0 0 fc/128 (106 kHz) 0 0 1 fc/64 (212 kHz) 0 1 0 fc/32 (424 kHz) 0 1 1 fc/16 (848 kHz) 1 X X RFU DS13890 Rev 4 ST25R3920B 4.5.11 Application information Auxiliary definition register Register space: A Address: 0Ah Type: RW Table 35. Auxiliary definition register Bit Name Default 7 no_crc_rx 0 6 RFU 0 5 nfc_id1 0 4 nfc_id0 0 Function 0: Receive with CRC check 1: Receive without CRC check Comments Valid for all protocols, for ISO14443A REQA, WUPA and anticollision receive without CRC is done automatically(1). - - 00: 4 bytes NFCID1 01: 7 bytes NFCID1 1x: RFU Selects NFCID1 size. Affects also PM demodulation. Should be set to 0 for PM demodulation. Selects RW receiver operation. 3 mfaz_cl90 0 0: 0° shifted clock for phase measurement 1: 90° shifted clock for phase measurement 2 dis_corr 0 0: Correlation operation 1: RFU 1 nfc_n1 0 0 nfc_n0 0 Value of n for direct commands NFC Initial Field ON and NFC Response Field ON (0...3) (2). - 1. Receive without CRC is done automatically when REQA and WUPA commands are sent using direct commands Transmit REQA and Transmit WUPA, respectively, and in case anticollision is performed setting bit antcl. 2. The value of nfc_n must be set prior to the NFC Initial Field ON and NFC Response Field ON operations. DS13890 Rev 4 81/158 157 Application information 4.5.12 ST25R3920B EMD suppression configuration register Register space: B Address: 05h Type: RW Table 36. EMD suppression configuration register Bit Name Default Function Comments 7 emd_emv 0 0: Disable EMD suppression 1: Enable EMD suppression according to EMVCo 0: Reception is enabled (I_rxs) only if the first 4 bits of the frame are error free Applies to ISO-A 106k only. 1: Reception is enabled (I_rxs) Must be set to 1 for EMVCo compliance. also if there is an error in the first four bits of the frame Bits no_rx_par and no_crc_rx must be set to 0, and bit nrt_emv must be set to 1 when emd_emv is enabled 6 rx_start_emv 0 5 RFU 0 - - 4 RFU 0 - - 3 emd_thld3 0 2 emd_thld2 0 1 emd_thld1 0 0 emd_thld0 0 82/158 If the received frame is less than emd_thld bytes long then EMD suppression will trigger on reception errors DS13890 Rev 4 Must be set to 4 for EMVCo compliance. ST25R3920B 4.5.13 Application information Subcarrier start timer register Register space: B Address: 06h Type: RW Table 37. Subcarrier start timer register Bit Name Default Function Comments 7:5 RFU 0 - - 4:0 sst 0 Subcarrier start time Step: 0.25 etu Range: 0 etu to 7.75 etu DS13890 Rev 4 Applies to ISO-B, 106 kb/s. If the time from the end of the MRT timer to the detection of a subcarrier is shorter than sst, then a soft error interrupt is generated. If emd_emv = 1 the frame will be suppressed as EMD and a restart interrupt will be generated. Note that corr_s3 defines the length of subcarrier start detection and affects the correct sst setting. 83/158 157 Application information 4.5.14 ST25R3920B Receiver configuration register 1 Register space: A Address: 0Bh Type: RW Table 38. Receiver configuration register 1 Bit Name Default 7 ch_sel 0 6 lp2 0 5 lp1 0 4 lp0 0 3 z600k 0 2 h200 0 1 h80 0 0 z12k 0 84/158 Function 0: Enable AM channel 1: Enable PM channel Comments If only one Rx channel is enabled in the Operation control register defines which channel is enabled. If both channels are enabled and manual channel selection is active defines which channel is used for receive framing. Low-pass control (see Table 3) First and third stage zero setting (see Table 4) DS13890 Rev 4 ST25R3920B 4.5.15 Application information Receiver configuration register 2 Register space: A Address: 0Ch Type: RW Table 39. Receiver configuration register 2 Bit Name Default Function Comments 7 demod_mode 0 0: AM/PM demodulation 1: I/Q demodulation Selects demodulator operation mode. I/Q demodulation requires amd_sel = 1. 6 amd_sel 0 0: peak detector 1: mixer Selects AM demodulator. 5 sqm_dyn 1 0: Squelch disabled 1: Automatic squelch activation after end of TX Squelch is activated 18.88 µs after end of TX, and stops when the Mask receive timer reaches the sqt setting. Select squelch trigger level. Squelch triggers on signals that are 1 or 6/3 times larger than the digitizing threshold. – Ratio 1: recommended for ISO-A 106k correlator, ISO-A HBR/ISO-B pulse decoder, ISO-15693, and FeliCa™ – Ratio 6/3: recommended for ISO-A HBR/ISO-B correlator 4 pulz_61 0 0: Squelch ratio 1 1: Squelch ratio 6/3 3 agc_en 1 0: AGC disabled 1: AGC enabled - - 2 agc_m 1 0: AGC operates on first eight sub-carrier pulses 1: AGC operates during complete receive period 1 agc_alg 0 0: Algorithm with preset is used 1: Algorithm with reset is used Algorithm with preset is recommended for protocols with short SOF (like ISO14443A fc / 128). 0 agc6_3 0 0: AGC ratio 3 1: AGC ratio 6 Select AGC trigger level. AGC triggers on signals 3 or 6 times above the minimum detectable signal level. DS13890 Rev 4 85/158 157 Application information 4.5.16 ST25R3920B Receiver configuration register 3 Register space: A Address: 0Dh Type: RW Table 40. Receiver configuration register 3 Bit Name Default 7 rg1_am2 1 6 rg1_am1 1 5 rg1_am0 0 4 rg1_pm2 1 3 rg1_pm1 1 2 rg1_pm0 0 1 lf_en 0 0: HF signal on receiver input 1: LF signal on receiver input - 0 lf_op 0 0: differential LF operation 1: LF input split (RFI1 to AM channel, RFI2 to PM channel) - 4.5.17 Function Comments 0: Full gain Gain reduction/boost in first gain 1-6: Gain reduction 2.5 dB per step (15 dB total) stage of AM channel. 7: Boost + 5.5 dB 0: Full gain Gain reduction/boost in first gain 1-6: Gain reduction 2.5 dB per step (15 dB total) stage of PM channel. 7: Boost + 5.5 dB Receiver configuration register 4 Register space: A Address: 0Eh Type: RW Table 41. Receiver configuration register 4(1) Bit Name Default 7 rg2_am3 0 6 rg2_am2 0 5 rg2_am1 0 4 rg2_am0 0 3 rg2_pm3 0 2 rg2_pm2 0 1 rg2_pm1 0 0 rg2_pm0 0 Function Comments AM channel: gain reduction in second and third stage and digitizer Only values from 0h to Ah are used: – settings 1h to 4h reduce gain by increasing the digitizer window in 3 dB steps – values from 5h to Ah additionally reduce the gain in second and third gain stage, always in 3 dB steps. PM channel: gain reduction in second and third stage and digitizer Only values from 0h to Ah are used: – settings 1h to 4h reduce gain by increasing the digitizer window in 3 dB steps – values from 5h to Ah additionally reduce the gain in second and third gain stage, always in 3 dB steps. 1. Direct command Reset RX gain is necessary to load the value of this register into AGC, Squelch, and RSSI block. 86/158 DS13890 Rev 4 ST25R3920B 4.5.18 Application information P2P receiver configuration register 1 Register space: B Address: 0Bh Type: RW Table 42. P2P receiver configuration register 1 Bit Name Default Function Comments 7 ook_fd 0 OOK fast decay 6 ook_rc1 0 5 ook_rc0 0 00 = 1.4 µs 01 = 1.0 µs 10 = 0.6 µs 11 = 0.2 µs OOK RC time constant 4 ook_thd1 0 3 ook_thd0 1 Refer to Table 43 OOK threshold level, depends on ook_rc configuration. 2 ask_rc1 1 1 ask_rc0 0 00 = 8.4 µs 01 = 6.8 µs 10 = 4.4 µs 11 = 2.4 µs ASK RC time constant 0 ask_thd 0 0: 97% 1: 95% ASK threshold level - Table 43. OOK threshold level settings ook_thd ook_rc = 0 ook_rc > 0 00 55% 80% 01 45% 75% 10 35% 70% 11 25% 65% DS13890 Rev 4 87/158 157 Application information 4.5.19 ST25R3920B Correlator configuration register 1 Register space: B Address: 0Ch Type: RW Table 44. Correlator configuration register 1 Bit 7 6 Name corr_s7 corr_s6 Default 1 0 Function Comments AGC = max |AM, PM| 1: Links the two AGC systems so that the gain in the AM(I) and PM(Q) channels are equal. To be used in summation mode. 0: The AM(I) and PM(Q) AGC channels are independent. To be used in non-summation mode. 0: Collision detection level defined by ISO-A corr_s 106k 1: Collision detection level equal to data slicer level Selecting the collision detection level with corr_s gives better detection of weak collisions. Setting the collision detection level equal to the data slicer gives better noise immunity. 0: Correlator phase correction applied No phase correction after start BPSK during the complete reception recommended for ISO-B 424 kb/s and (1) 1: No correlator phase correction after 848 kb/s operation. the first data bytes 5 4 3 2 corr_s5 corr_s4 corr_s3 corr_s2 88/158 0 0: Vref -50 mV setting, 1st squelch step -100 mV 1: Vref -100 mV setting, 1st squelch step -200 mV 1 0: AM and PM correlation signals digitized separately 1: AM and PM correlation signals summed before digitizing (summation mode) Summation mode is recommended for all correlator operations 0: RX bit rate 106kb/s = 17, RX bit rates 212 to 848 kb/s = 9 1: RX bit rate 106kb/s = 33, RX bit rates 212 to 848 kb/s = 17 BPSK start length setting (delay from the start of a tags subcarrier signal to the moment when a subcarrier start is detected). Then circuit starts observing for the first phase transition (9/17/33 ± 2 pilot pulses). At this moment the sst check for TR0 is done. 0 0 - ISO-A 0: Normal data slicer 106k 1: Fast data slicer BPSK 0: Normal ref. time constant (1) 1: Long ref. time const. (1.5x normal) DS13890 Rev 4 - ST25R3920B Application information Table 44. Correlator configuration register 1 (continued) Bit Name Default Function Comments ISO-A Collision level setting MSB 106k 1 corr_s1 1 BPSK (1) 0 corr_s0 1 Collision detection level, compared to data detection level: – 00: 16% – 01: 28% – 10: 41% – 11: 53% Subcarrier end detection level 0: 100% 1: 66% ISO-A Collision level setting LSB 106k BPSK 0: Subcarrier end detector disabled (1) 1: Subcarrier end detector enabled 1. BPSK options apply to ISO-A HBR and ISO-B (all bit rates). 4.5.20 Correlator configuration register 2 Register space: B Address: 0Dh Type: RW Table 45. Correlator configuration register 2 Bit Name Default 7 RFU 0 6 RFU 0 5 RFU 0 4 RFU 0 3 RFU 0 2 RFU 0 Function Comments - - Correlator sleep mode option. Sleep start: 18 µs no output pulse. Stop with timer: – takes 18 µs (ISO-A/B, F424) – takes 42 µs (stream 15693, F212) 1 corr_s9 0 0: Sleep mode disable set by timer 1: Sleep mode disable only on rx_on = 1 0 corr_s8 0 0: All other standards Must be set to 1 for 424 kHz subcarrier stream mode. 1: 424 kHz subcarrier stream mode DS13890 Rev 4 89/158 157 Application information 4.5.21 ST25R3920B Mask receive timer register Register space: A Address: 0Fh Type: RW Table 46. Mask receive timer register Bit Name Default 7 mrt7 0 6 mrt6 0 5 mrt5 0 4 mrt4 0 3 mrt3 1 2 mrt2 0 1 mrt1 0 0 mrt0 0 90/158 Function mrt_step = 0: Step: 64 / fc (4.72 μs) Range: 256 / fc (~18.88 μs) to 16320 / fc (~1.2 ms) mrt_step = 1: Step: 512 / fc (37.78 μs) Range: 2048 / fc (151 μs) to 130560 / fc (9.62 ms) DS13890 Rev 4 Comments Set time after end of TX during which the receiver output is ignored (masked). The minimum mask receive time of 18.88 μs covers the transients in receiver after end of transmission. ST25R3920B 4.5.22 Application information No-response timer register 1 Register space: A Address: 10h Type: RW Table 47. No-response timer register 1 Bit Name Default 7 nrt15 0 6 nrt14 0 5 nrt13 0 4 nrt12 0 3 nrt11 0 2 nrt10 0 1 nrt9 0 0 nrt8 0 4.5.23 Function No-response timer definition MSB bits nrt_step = 0: Step: 64 / fc (4.72 μs), Range: 309 ms nrt_step = 1: Step: 4096 / fc (302 µs) Range: 19.8 s. Comments Defines timeout after end of Tx. If this timeout expires without detecting a response a Noresponse interrupt is sent. In NFC mode the No-response timer is started only when external field is detected. In the NFCIP-1 active communication mode the No-response timer is automatically started when the transmitter is turned off after the message has been sent. All 0: No-response timer is not started. No-response timer is reset and restarted with Start No-response timer direct command. No-response timer register 2 Register space: A Address: 11h Type: RW Table 48. No-response timer register 2 Bit Name Default 7 nrt7 0 6 nrt6 0 5 nrt5 0 4 nrt4 0 3 nrt3 0 2 nrt2 0 1 nrt1 0 0 nrt0 0 Function No-response timer definition LSB bits DS13890 Rev 4 Comments - 91/158 157 Application information 4.5.24 ST25R3920B Timer and EMV control register Register space: A Address: 12h Type: RW Table 49. Timer and EMV control register Bit Name Default Function Comments 7 gptc2 0 6 gptc1 0 5 gptc0 0 4 RFU 0 3 mrt_step 0 0: 64 / fc 1: 512 / fc 2 nrt_nfc 0 0: NRT starts at end of TX (own field off) No-response timer start condition in AP2P initiator and target mode. 1: NRT starts at peer field-on event 1 nrt_emv 0 1: No-response timer EMV mode 0 nrt_step 0 0: 64 / fc 1: 4096 / fc General purpose timer trigger source. Refer to Table 50 - - Mask receive timer step size No-response timer step size. Table 50. Trigger sources gptc2 gptc1 gptc0 92/158 Trigger source X X X The timer starts always with direct command Start General purpose timer. 0 0 0 No additional trigger source. 0 0 1 Additionally starts at End of RX (after EOF). 0 1 0 Additionally starts at Start of RX. 0 1 1 Additionally starts at End of TX. In AP2P modes the timer is used to switch the field off. In AP2P modes enables NRT start according to nrt_nfc description. 1 0 0 1 0 1 1 1 0 1 1 1 RFU DS13890 Rev 4 ST25R3920B 4.5.25 Application information General purpose timer register 1 Register space: A Address: 13h Type: RW Table 51. General purpose timer register 1 Bit Name Default 7 gpt15 - 6 gpt14 - 5 gpt13 - 4 gpt12 - 3 gpt11 - 2 gpt10 - 1 gpt9 - 0 gpt8 - 4.5.26 Function Comments General purpose timeout definition MSB bits Defined in steps of 8 / fc (590 ns) Range from 590 ns to 38,7 ms - General purpose timer register 2 Register space: A Address: 14h Type: RW Table 52. General purpose timer register 2 Bit Name Default 7 gpt7 - 6 gpt6 - 5 gpt5 - 4 gpt4 - 3 gpt3 - 2 gpt2 - 1 gpt1 - 0 gpt0 - Function Comments General purpose timeout definition LSB bits Defined in steps of 8 / fc (590 ns) Range from 590 ns to 38,7 ms - DS13890 Rev 4 93/158 157 Application information 4.5.27 ST25R3920B PPON2 field waiting register Register space: A Address: 15h Type: RW Table 53. PPON2 field waiting register Bit Name Default 7 ppt7 1 6 ppt6 0 5 ppt5 0 4 ppt4 0 3 ppt3 0 2 ppt2 0 1 ppt1 0 0 ppt0 0 94/158 Function PPON2 timer Step: 64 / fc (4.72 µs) Range: 1.204 ms DS13890 Rev 4 Comments Maximum time the system waits for the peer device field on in AP2P mode. ST25R3920B 4.5.28 Application information Squelch timer register Register space: B Address: 0Fh Type: RW Table 54. Squelch timer register Bit Name Default 7 sqt7 0 6 sqt6 0 5 sqt5 0 4 sqt4 0 3 sqt3 0 2 sqt2 0 1 sqt1 0 0 sqt0 0 4.5.29 Function Squelch Timer Step, Range: same as Mask receive timer register, including mrt_step selection Comments Squelch is enabled ~20 μs after the end of reader data transmission – sqt > 5: Squelch stops after the time defined by sqt. Gain reduction due to squelch is locked and used as a starting point for AGC. – Sqt ≤ 5 or sqt ≥ mrt: Squelch is enabled until the MRT expires. NFC field on guard timer register Register space: B Address: 15h Type: RW Table 55. NFC field on guard timer register Bit Name Default 7 nfc_gt7 0 6 nfc_gt6 0 5 nfc_gt5 1 4 nfc_gt4 1 3 nfc_gt3 0 2 nfc_gt2 0 1 nfc_gt1 1 0 nfc_gt0 1 Function NFC field on guard timer Step: 2048 / fc (151 μs) Range: 38.66 ms DS13890 Rev 4 Comments Used by NFC field on commands. The value nfc_gt is added to the initial 75 μs in TIRFG and TARFG. Set to 33 for TIRFG (75 μs + 4.984 ms= 5.06 ms) Set to 0 for TARFG (75 μs + 0 ms = 75 μs) 95/158 157 Application information 4.5.30 ST25R3920B Mask main interrupt register Register space: A Address: 16h Type: RW Table 56. Mask main interrupt register Bit Name Default 7 M_osc 0 1: Mask IRQ when oscillator frequency is stable - 6 M_wl 0 1: Mask IRQ due to FIFO water level - 5 M_rxs 0 1: Mask IRQ due to start of receive - 4 M_rxe 0 1: Mask IRQ due to end of receive - 3 M_txe 0 1: Mask IRQ due to end of transmission - 2 M_col 0 1: Mask IRQ due to bit collision - 1 M_rx_rest 0 1: Mask IRQ due to automatic reception restart - 0 RFU 0 Not used - 4.5.31 Function Comments Mask timer and NFC interrupt register Register space: A Address: 17h Type: RW Table 57. Mask timer and NFC interrupt register Bit Name Default Function Comments 7 M_dct 0 1: Mask IRQ due to termination of direct command - 6 M_nre 0 1: Mask IRQ due to No-response timer expire - 5 M_gpe 0 1: Mask IRQ due to general purpose timer expire - 4 M_eon 0 1: Mask IRQ due to detection of external field higher than Target activation level - 3 M_eof 0 1: Mask IRQ due to detection of external field drop below Target activation level - 2 M_cac 0 1: Mask IRQ due to detection of collision during RF Collision Avoidance - 1 M_cat 0 1: Mask IRQ after minimum guard time expire - 0 M_nfct 0 1: Mask IRQ when in target mode the initiator bit rate has been recognized - 96/158 DS13890 Rev 4 ST25R3920B 4.5.32 Application information Mask error and wake-up interrupt register Register space: A Address: 18h Type: RW Table 58. Mask error and wake-up interrupt register Bit Name Default 7 M_crc 0 1: Mask IRQ due to CRC error - 6 M_par 0 1: Mask IRQ due to parity error - 5 M_err2 0 1: Mask IRQ due to soft framing error - 4 M_err1 0 1: Mask IRQ due to hard framing error - 3 M_wt 0 1: Mask IRQ due to wake-up timer interrupt - 2 M_wam 0 1: Mask Wake-up IRQ due to amplitude measurement - 1 M_wph 0 1: Mask Wake-up IRQ due to phase measurement. - 0 RFU 0 - - 4.5.33 Function Comments Mask passive target interrupt register Register space: A Address: 19h Type: RW Table 59. Mask passive target interrupt register Bit Name Default Function 7 M_ppon2 0 1: Mask IRQ from PPON2 field on waiting timer - 6 M_sl_wl 0 1: Mask IRQ for Passive target slot number water level - 5 M_apon 0 1: Mask IRQ due to Active PP Field on event - 4 M_rxe_pta 0 1: Mask IRQ due to end of receive when the device is handling the response - 3 M_wu_f 0 1: Mask IRQ NFC 212/424 kb/s passive target active - 2 RFU 0 1 M_wu_a* 0 1: Mask IRQ NFC 106 kb/s passive target Active* - 0 M_wu_a 0 1: Mask IRQ NFC 106 kb/s passive target Active - - DS13890 Rev 4 Comments - 97/158 157 Application information 4.5.34 ST25R3920B Main interrupt register Register space: A Address: 1Ah Type: R Table 60. Main interrupt register Bit Name Default 7 I_osc - Function Comments IRQ when oscillator frequency is stable Set after oscillator is started by setting Operation control register bit en. Set during receive, if more than 300 bytes are in the FIFO. Set during transmit, if less than 200 bytes are in the FIFO. 6 I_wl - IRQ due to FIFO water level 5 I_rxs - IRQ due to start of receive - 4 I_rxe - IRQ due to end of receive - 3 I_txe - IRQ due to end of transmission - 2 I_col - IRQ due to bit collision - 1 I_rx_rest - IRQ due to automatic reception restart 0 RFU - 98/158 - Set when a frame is suppressed as EMD - DS13890 Rev 4 ST25R3920B 4.5.35 Application information Timer and NFC interrupt register Register space: A Address: 1Bh Type: R Table 61. Timer and NFC interrupt register(1) Bit Name Default Function 7 I_dct - IRQ due to termination of direct command - 6 I_nre - IRQ due to No-response timer expire - 5 I_gpe - IRQ due to general purpose timer expire - 4 I_eon - IRQ due to detection of external field higher than Target activation level - 3 I_eof - IRQ due to detection of external field drop below Target activation level - 2 I_cac - IRQ due to detection of collision during RF Collision Avoidance I_cac must be cleared before collision avoidance is performed. An external field was not detected during RF collision avoidance, field was switched on, IRQ sent after minimum guard time according to NFCIP-1. 1 I_cat - IRQ after minimum guard time expire 0 I_nfct - IRQ when in target mode the initiator bit rate was recognized Comments - 1. After register has been read, its content is set to 0. DS13890 Rev 4 99/158 157 Application information 4.5.36 ST25R3920B Error and wake-up interrupt register Register space: A Address: 1Ch Type: R Table 62. Error and wake-up interrupt register(1) Bit Name Default Function 7 I_crc - CRC error Avoid delayed reading of interrupt status register to not fall into potential signaling of I_crc. 6 I_par - Parity error - 5 I_err2 - Soft framing error Framing error that does not result in corrupted Rx data. 4 I_err1 - Hard framing error Framing error that results in corrupted Rx data. 3 I_wt - Wake-up timer interrupt Timeout after execution of Start Wake-Up Timer command in case option with IRQ at every timeout is selected. 2 I_wam - Wake-up interrupt due to amplitude measurement Result of amplitude measurement ∆am larger than reference. 1 I_wph - Wake-up interrupt due to phase measurement. Result of phase measurement ∆pm larger than reference. 0 RFU - - - 1. After Main Interrupt Register has been read, its content is set to 0. 100/158 DS13890 Rev 4 Comments ST25R3920B 4.5.37 Application information Passive target interrupt register Register space: A Address: 1Dh Type: R Table 63. Passive target interrupt register(1) Bit Name Default Function Comments 7 I_ppon2 - PPON2 field on waiting timer interrupt 6 I_sl_wl - IRQ for passive target slot number water level Sent if four unused slot numbers (TSN) remain in PT_memory. 5 I_apon - IRQ due to active P2P field on event Sent after RF collision avoidance, if there was no collision and field was turned on. 4 I_rxe_pta - IRQ due to end of receive, 3920B is handling the response Sent in passive target mode when NFC-A anti-collision or NFC-F SENSF_RES is automatically sent (MCU action required). 3 I_wu_f - NFC 212/424kb/s Passive target Sent after NFC 212/424 kb/s automatic response ‘Active’ interrupt to SENSF_REQ was sent. 2 RFU - RFU 1 I_wu_a* - Passive target Active* interrupt Sent when Active* state is reached. 0 I_wu_a - Passive target Active interrupt Sent when Active state is reached. - - 1. After register has been read, its content is set to 0. DS13890 Rev 4 101/158 157 Application information 4.5.38 ST25R3920B FIFO status register 1 Register space: A Address: 1Eh Type: R Table 64. FIFO status register 1 Bit Name Default 7 fifo_b7 - 6 fifo_b6 - 5 fifo_b5 - 4 fifo_b4 - 3 fifo_b3 - 2 fifo_b2 - 1 fifo_b1 - 0 fifo_b0 - 4.5.39 Function Number of bytes in the FIFO (LSB) Comments Valid range is from 0 to 512. FIFO status register 2 Register space: A Address: 1Fh Type: R Table 65. FIFO status register 2 Bit Name Default 7 fifo_b9 - 6 fifo_b8 5 Function Comments - - Number of bytes in the FIFO (MSB) - fifo_unf - 1: FIFO underflow - 4 fifo_ovr - 1: FIFO overflow - 3 fifo_lb2 - 2 fifo_lb1 - 1 fifo_lb0 - 0 102/158 np_lb - Number of bits in the last FIFO byte if it was not complete The received bits are stored in the LSB part of the last byte in the FIFO. If I_err1 is set then fifo_lb dos not contain valid data. The bit is set if the last received byte is complete 1: Parity bit is missing in the last with 8 data bits but he parity bit is missing. byte If I_err1 is set then np_lb does not contain valid data. DS13890 Rev 4 ST25R3920B 4.5.40 Application information Collision display register Register space: A Address: 20h Type: R Table 66. Collision display register Bit Name Default 7 c_byte3 - 6 c_byte2 - 5 c_byte1 - 4 c_byte0 - 3 c_bit2 - 2 c_bit1 - 1 c_bit0 - 0 c_pb - Function Number of full bytes before the bit collision happened. Number of bits before the collision in the byte where the collision happened 1: Collision in parity bit 0: no collision DS13890 Rev 4 Comments The Collision display register range covers ISO14443A anticollision command. If collision (or framing error interpreted as collision) happens in a longer message, the Collision display register is not set. If I_err1 is set then c_byte and c_bit do not contain valid data. This error is reported if the first detected collision is in a parity bit. If I_err1 is set then c_pb dos not contain valid data. 103/158 157 Application information 4.5.41 ST25R3920B Passive target display register Register space: A Address: 21h Type: R Table 67. Passive target display register Bit Name Default Function Comments 7 RFU - - - 6 RFU - - - 5 RFU - - - 4 RFU - - - 3 pta_state3 - 2 pta_state2 - 1 pta_state1 - 0 pta_state0 - 104/158 0000: POWER OFF 0001: IDLE 0010: READY_L1 0011: READY_L2 0100: RFU 0101:ACTIVE 0110: RFU 1001: HALT 1010: READY_L1* 1011: READY_L2* 1100: RFU 1101: ACTIVE* DS13890 Rev 4 ISO-A passive target states. In ACTIVE or ACTIVE* state, the MCU must handle all commands, including SENSE/IDLE and SLEEP/HALT. ST25R3920B 4.5.42 Application information Number of transmitted bytes register 1 Register space: A Address: 22h Type: RW Table 68. Number of transmitted bytes register 1 Bit Name Default 7 ntx12 0 6 ntx11 0 5 ntx10 0 4 ntx9 0 3 ntx8 0 2 ntx7 0 1 ntx6 0 0 ntx5 0 4.5.43 Function Number of full bytes to be transmitted, MSB bits Comments Maximum supported number of bytes is 8191. Number of transmitted bytes register 2 Register space: A Address: 23h Type: RW Table 69. Number of transmitted bytes register 2(1) (2) Bit Name Default 7 ntx4 0 6 ntx3 0 5 ntx2 0 4 ntx1 0 3 ntx0 0 2 nbtx2 0 1 nbtx1 0 0 nbtx0 0 Function Comments Number of full bytes to be transmitted, MSB bits Maximum supported number of bytes is 8191. Number of bits to transmit after the last full byte. Set to 000 to transmit only full bytes. Bit transmission starts from LSB. Applicable for ISO14443A: – bit oriented anticollision frame in case last byte is a split byte – Tx is done without parity bit generation 1. If anctl bit is set while card is in idle state and nbtx is not 000, then i_par will be triggered during REQA and WUPA direct command is issued. 2. Transmission of short or incomplete messages only works for ISO-A/B using the command Transmit without CRC. DS13890 Rev 4 105/158 157 Application information 4.5.44 ST25R3920B Bit rate detection display register Register space: A Address: 24h Type: R Table 70. Bit rate detection display register Bit Name Default Function Comments 7 RFU - - - 6 RFU - - - 5 nfc_rate1 - 4 nfc_rate0 - 3 ppt2_on - 1: PPON2 timer is running 2 gpt_on - 1: General purpose timer is running 1 nrt_on - 1: No-response timer is running 0 mrt_on - 1: Mask receive timer is running 106/158 Refer to Table 25 DS13890 Rev 4 Result of automatic bit rate detection in the bit rate detection target mode. State of internal timers. ST25R3920B 4.5.45 Application information A/D converter output register Register space: A Address: 25h Type: R Table 71. A/D converter output register Bit Name Default 7 ad7 - 6 ad6 - 5 ad5 - 4 ad4 - 3 ad3 - 2 ad2 - 1 ad1 - 0 ad0 - Function Displays the result of the last A/D conversion. DS13890 Rev 4 Comments - 107/158 157 Application information 4.5.46 ST25R3920B Antenna tuning control register 1 Register space: A Address: 26h Type: RW Table 72. Antenna tuning control register 1 Bit Name Default 7 aat_A_7 1 6 aat_A_6 0 5 aat_A_5 0 4 aat_A_4 0 3 aat_A_3 0 2 aat_A_2 0 1 aat_A_1 0 0 aat_A_0 0 4.5.47 Function Comments AAT-A D/A converter input. AAT-A voltage (in V) = (0.044 + 0.868 * aat_A / 255) * VDD_A Antenna tuning control register 2 Register space: A Address: 27h Type: RW Table 73. Antenna tuning control register 2 Bit Name Default 7 aat_B_7 1 6 aat_B_6 0 5 aat_B_5 0 4 aat_B_4 0 3 aat_B_3 0 2 aat_B_2 0 1 aat_B_1 0 0 aat_B_0 0 108/158 Function Comments AAT-B D/A converter input. AAT-B voltage (in V) = (0.044 + 0.868 * aat_B / 255) * VDD_A DS13890 Rev 4 ST25R3920B 4.5.48 Application information TX driver register Register space: A Address: 28h Type: RW Table 74. TX driver register Bit Name Default 7 am_mod3 0 6 am_mod2 1 5 am_mod1 1 4 am_mod0 1 3 d_res3 0 2 d_res2 0 1 d_res1 0 0 d_res0 0 Function Comments AM modulation index (see Table 75) - RFO driver resistance (see Table 76) - Table 75. AM modulation index am_mod Modulation (%) 0 0 1 8 2 10 3 11 4 12 5 13 6 14 7 15 8 20 9 25 10 30 11 40 12 50 13 60 14 70 15 82 DS13890 Rev 4 109/158 157 Application information ST25R3920B Table 76. RFO driver resistance d_res Driver output resistance (normalized)(1) 0 1.00 1 1.19 2 1.40 3 1.61 4 1.79 5 2.02 6 2.49 7 2.94 8 3.41 9 4.06 10 5.95 11 8.26 12 17.1 13 36.6 14 51.2 15 High Z 1. The value has to be multiplied with the RFO resistance from Section 5.4: Electrical specifications to obtain the driver output resistance for the corresponding d_res setting. 110/158 DS13890 Rev 4 ST25R3920B 4.5.49 Application information Auxiliary modulation setting register Register space: B Address: 28h Type: RW Table 77. Auxiliary modulation setting register Bit 7 Name dis_reg_am Default Function Comments 0 0: Regulator AM enabled 1: Regulator AM disabled Uses am_mod to set the modulation index for regulator based AM modulation. Logic of this bit is inverted. Set to 0 to enable regulator AM. 0: To be used with act_amsink=1 and big VDD_AM capacitor (2.2uF) 1: To be used with act_amsink=0 and small VDD_AM capacitor (10-50nF, depending on RF load) Normal polarity: LM_EXT pin load modulation signal is active high. Inverse polarity: LM_EXT pin load modulation signal is active low. 6 lm_ext_pol 0 0: Normal polarity 1: Inverse polarity 5 lm_ext 0 0: External load modulation disabled Enables output of load modulation signal on 1: External load modulation enabled LM_EXT pin. 4 lm_dri 1 0: Driver load modulation disabled 1: Driver load modulation enabled Uses Passive target modulation register to set driver load modulation resistance. 3 res_am 0 0: Resistive AM modulation disabled 1: Resistive AM modulation enabled Uses md_res to configure resistive AM modulated driver resistance. Set to: 1: When it is used with act_amsink=0 and small VDD_AM capacitor (10-50 nF, depending on RF load) 0: In card mode, wake-up mode and measure amplitude/phase from tx_en=0 2 rgs_am 0 1: Regulator shaped AM modulation for AWS enabled 0: Regulator shaped AM modulation for AWS disabled 1 RFU 0 - - 0 RFU 0 - - DS13890 Rev 4 111/158 157 Application information 4.5.50 ST25R3920B Passive target modulation register Register space: A Address: 29h Type: RW Table 78. Passive target modulation register Bit Name Default 7 ptm_res3 0 6 ptm_res2 1 5 ptm_res1 1 4 ptm_res0 1 3 pt_res3 0 2 pt_res2 0 1 pt_res1 0 0 pt_res0 0 Function Comments RFO resistance during passive load modulation, modulated state. ptm_res must be set before the Mode definition register is set to passive target mode. Refer to Table 79 RFO resistance during passive load modulation, unmodulated state. pt_res must be set before the Mode definition register is set to passive target mode. Table 79. Passive target modulated and unmodulated state driver output resistance ptm_res pt_res Driver output resistance RRFO (normalized)(1) 0 1.0 1 2.0 2 4.1 3 8.3 4 12.2 5 17.1 6 25.6 7 32.0 8 36.6 9 42.7 10 51.2 11 64.0 12 85.3 13 128.0 14 256.0 15 High Z 1. The value must be multiplied by the RFO resistance from Section 5.4: Electrical specifications to obtain the driver output resistance for the corresponding ptm_res/pt_res setting. 112/158 DS13890 Rev 4 ST25R3920B 4.5.51 Application information TX driver timing register Register space: B Address: 29h Type: RW Table 80. TX driver timing register Bit Name Default 7 d_rat_t3 0 6 d_rat_t2 1 5 d_rat_t1 1 4 d_rat_t0 1 3 d_tim_man 1 2 d_tim_m2 1 1 d_tim_m1 0 0 d_tim_m0 0 Function Comments The value presents the target ratio between one RF period and whole non-overlap time (both sides L to H and H to L). The system starts with the slowest available Driver transient ratio target transient and measures the ratio. If this is lower (in number of non-overlap times than targeted the system switches to faster in one RF period) transient. The procedure is repeated until the target ratio is reached (or exceeded for the first time). There are five steps available, procedure can take up to ten RF periods. 0: Use automatically acquired timing setting 1: Use manual timing setting 000: Slow 001: Medium slow 010: Nominal 011: Medium fast 1xx: Fast - Manual driver timing, used if d_tim_man is set to 1. DS13890 Rev 4 113/158 157 Application information 4.5.52 ST25R3920B External field detector activation threshold register Register space: A Address: 2Ah Type: RW Table 81. External field detector activation threshold register(1) Bit Name Default 7 RFU 0 6 trg_l2 0 5 trg_l1 1 4 trg_l0 1 3 rfe_t3 0 2 rfe_t2 0 1 rfe_t1 1 0 rfe_t0 1 Function Not used - Peer detection threshold. Refer to Table 85. - Collision avoidance threshold. Refer to Table 86. - 1. The value of rfe_3 must be equal for both activation and deactivation threshold. 114/158 Comments DS13890 Rev 4 ST25R3920B 4.5.53 Application information Resistive AM modulation register Register space: B Address: 2Ah Type: RW Table 82. Resistive AM modulation register Bit Name Default Function Comments 7 fa3_f 0 0: Use normal non-overlap 1: Use minimum non-overlap - 6 md_res6 0 5 md_res5 0 4 md_res4 0 3 md_res3 0 2 md_res2 0 1 md_res1 0 0 md_res0 0 Refer to Table 83. Resistive AM modulated state driver output resistance. Table 83. Resistive AM modulated state driver output resistance md_res Driver output resistance RRFO (normalized)(1) md_res Driver output resistance RRFO (normalized) 0 1.004 64 4.063 1 1.020 65 4.129 2 1.036 66 4.197 3 1.053 67 4.267 4 1.071 68 4.339 5 1.089 69 4.414 6 1.108 70 4.491 7 1.128 71 4.571 8 1.148 72 4.655 9 1.169 73 4.741 10 1.191 74 4.830 11 1.213 75 4.923 12 1.237 76 5.020 13 1.261 77 5.120 14 1.286 78 5.224 15 1.313 79 5.333 16 1.340 80 5.447 DS13890 Rev 4 115/158 157 Application information ST25R3920B Table 83. Resistive AM modulated state driver output resistance (continued) md_res Driver output resistance RRFO (normalized)(1) md_res Driver output resistance RRFO (normalized) 17 1.369 81 5.565 18 1.399 82 5.689 19 1.430 83 5.818 20 1.463 84 5.953 21 1.497 85 6.095 22 1.533 86 6.244 23 1.571 87 6.400 24 1.610 88 6.564 25 1.652 89 6.737 26 1.695 90 6.919 27 1.741 91 7.111 28 1.790 92 7.314 29 1.842 93 7.529 30 1.896 94 7.758 31 1.954 95 8.000 32 2.016 96 8.258 33 2.081 97 8.533 34 2.151 98 8.828 35 2.226 99 9.143 36 2.306 100 9.481 37 2.349 101 9.846 38 2.393 102 10.24 39 2.438 103 10.67 40 2.485 104 11.13 41 2.535 105 11.64 42 2.586 106 12.19 43 2.639 107 12.80 44 2.695 108 13.47 45 2.753 109 14.22 46 2.813 110 15.06 47 2.876 111 16.00 48 2.943 112 17.07 49 3.012 113 18.29 50 3.084 114 19.69 116/158 DS13890 Rev 4 ST25R3920B Application information Table 83. Resistive AM modulated state driver output resistance (continued) md_res Driver output resistance RRFO (normalized)(1) md_res Driver output resistance RRFO (normalized) 51 3.160 115 21.3 52 3.241 116 23.3 53 3.325 117 25.6 54 3.413 118 28.4 55 3.507 119 32.0 56 3.606 120 36.6 57 3.657 121 42.7 58 3.710 122 51.2 59 3.765 123 64.0 60 3.821 124 85.3 61 3.879 125 128 62 3.938 126 256 63 4.000 127 High Z 1. The value must be multiplied by the RFO resistance from Section 5.4: Electrical specifications to obtain the driver output resistance for the corresponding md_res setting. 4.5.54 External field detector deactivation threshold register Register space: A Address: 2Bh Type: RW Table 84. External field detector deactivation threshold register(1) Bit Name Default 7 RFU 0 6 trg_ld2 0 5 trg_ld1 1 4 trg_ld0 1 3 rfe_td3 0 2 rfe_td2 0 1 rfe_td1 1 0 rfe_td0 1 Function Comments Not used - Deactivation peer detection threshold (see Table 85). - Deactivation collision avoidance threshold (see Table 86). - 1. The value of rfe_3 must be equal for both activation and deactivation threshold. DS13890 Rev 4 117/158 157 Application information ST25R3920B Table 85. Peer detection threshold as seen on RFI1 input trg_I2 trg_I1 trg_I0 Peer detection threshold voltage (mVpp) on RFI1 0 0 0 75 0 0 1 105 0 1 0 150 0 1 1 205 1 0 0 290 1 0 1 400 1 1 0 560 1 1 1 800 Table 86. Collision avoidance threshold as seen on RFI1 input 118/158 rfe_3 rfe_2 rfe_1 rfe_0 Collision avoidance threshold voltage (mVpp) on RFI1 0 0 0 0 75 0 0 0 1 105 0 0 1 0 150 0 0 1 1 205 0 1 0 0 290 0 1 0 1 400 0 1 1 0 560 0 1 1 1 800 1 0 0 0 25 1 0 0 1 33 1 0 1 0 47 1 0 1 1 64 1 1 0 0 90 1 1 0 1 125 1 1 1 0 175 1 1 1 1 250 DS13890 Rev 4 ST25R3920B 4.5.55 Application information TX driver timing display register Register space: B Address: 2Bh Type: R Table 87. TX driver timing display register Bit Name Default 7 d_rat_r3 - 6 d_rat_r2 - 5 d_rat_r1 - 4 d_rat_r0 - 3 RFU - 2 d_tim_r2 - 1 d_tim_1 - 0 d_tim_0 - Function Comments Driver Transient ratio readout (in number of non-overlap Driver transient ratio readout times in one RF period) 000: Slow 001: Medium slow 010: Nominal 011: Medium fast 1xx: Fast - Driver timing readout DS13890 Rev 4 119/158 157 Application information 4.5.56 ST25R3920B Regulator voltage control register Register space: A Address: 2Ch Type: RW Table 88. Regulator voltage control register Bit Name Default 7 reg_s 0 6 rege_3 0 5 rege_2 0 4 rege_1 0 3 rege_0 0 2 mpsv2 0 1 mpsv1 0 0 mpsv0 0 120/158 Function Comments 0: Regulated voltages are defined by result of Adjust Regulators command 1: Regulated voltages are defined by rege_x bits written in this register Defines mode of regulator voltage setting. External definition of regulated voltage (see Table 90). In 5 V mode VDD_D and VDD_A regulators are set to 3.4 V In 5 V mode VDD_D and VDD_A regulators are set to 3.4 V. In 3.3 V mode VDD_D and VDD_A regulators are set to the same value as VDD_RF. 000: VDD 001: VDD_A 010: VDD_D 011: VDD_RF 100: VDD_AM 101: VDD_TX 110: RFU 111: RFU Defines source of direct command Measure power supply. DS13890 Rev 4 ST25R3920B 4.5.57 Application information Regulator display register Register space: B Address: 2Ch Type: R Table 89. Regulator display register Bit Name Default Function Comments 7 reg_3 - 6 reg_2 - 5 reg_1 - 4 reg_0 - 3 RFU - - - 2 RFU - - - 1 RFU - - - 0 i_lim - Voltage regulator setting after Adjust regulators command. Refer to Table 90 for definition. - 1: VDD_RF regulator in current limit mode - Table 90. Regulated voltages reg_3 reg_2 reg_1 reg_0 Typical regulated voltage (V) rege_3 rege_2 rege_1 rege_0 5 V mode 3.3 V mode 1 1 1 1 5.1 3.4 1 1 1 0 5.0 3.3 1 1 0 1 4.9 3.2 1 1 0 0 4.8 3.1 1 0 1 1 4.7 3.0 1 0 1 0 4.6 2.9 1 0 0 1 4.5 2.8 1 0 0 0 4.4 2.7 0 1 1 1 4.3 2.6 0 1 1 0 4.2 2.5 0 1 0 1 4.1 2.4 0 1 0 0 4.0 - 0 0 1 1 3.9 - 0 0 1 0 3.8 - 0 0 0 1 3.7 - 0 0 0 0 3.6 - DS13890 Rev 4 121/158 157 Application information 4.5.58 ST25R3920B RSSI display register Register space: A Address: 2Dh Type: R Table 91. RSSI display register Bit Name Default 7 rssi_am_3 - 6 rssi_am_2 - 5 rssi_am_1 - 4 rssi_am_0 - 3 rssi_pm_3 - 2 rssi_pm_2 - 1 rssi_pm_1 - 0 rssi_pm_0 - Function Comments AM channel RSSI peak value. Refer to Table 92 for definition. Stores the AM channel RSSI peak value until the start of the next reception, or until the Clear RSSI command is sent. PM channel RSSI peak value. Refer to Table 92 for definition. Stores the PM channel RSSI peak value until the start of the next reception, or until the Clear RSSI command is sent. Table 92. RSSI 122/158 rssi_3 rssi_2 rssi_1 rssi_0 Typical signal on RFI1 (mVrms) 0 0 0 0 ≤20 0 0 0 1 >20 0 0 1 0 >27 0 0 1 1 >37 0 1 0 0 >52 0 1 0 1 >72 0 1 1 0 >99 0 1 1 1 >136 1 0 0 0 >190 1 0 0 1 >262 1 0 1 0 >357 1 0 1 1 >500 1 1 0 0 >686 1 1 0 1 >950 1 1 1 0 1 1 1 1 DS13890 Rev 4 >1150 ST25R3920B 4.5.59 Application information Gain reduction state register Register space: A Address: 2Eh Type: R Table 93. Gain reduction state register Bit Name Default 7 gs_am_3 - 6 gs_am_2 - 5 gs_am_1 - 4 gs_am_0 - 3 gs_pm_3 - 2 gs_pm_2 - 1 gs_pm_1 - 0 gs_pm_0 - Function Comments Refer to rg2_am for value explanation. Overall AM channel second and third stage gain reduction (includes register gain reduction, squelch and AGC). Refer to rg2_pm for value explanation. Overall PM channel second and third stage gain reduction (includes register gain reduction, squelch and AGC). DS13890 Rev 4 123/158 157 Application information 4.5.60 ST25R3920B AWS Config 1 register(a) Register Space: B Address: 2Eh Type: RW Table 94. AWS configuration 1 Bit Name Default Function Comments 7:4 RFU - - - 3 vddrf_cont 0 2 RFU - 1: VDD_RF regulator continuous operation - - 1 vddrf_rx_only 0 0: Use VDD_RF after each modulation gap 1: Use VDD_RF for RX only 0 rgs_txonoff 0 1: Enables regulator shape for TX field on/off a. Settings for this register are only applicable when bit rgs_am=1 124/158 It must be set to 1 DS13890 Rev 4 0: at the end of each modulation pause, the driver switches to VDD_RF 1: The driver switches to VDD_RF only during RX period. To set vddrf_rx_only to 1 is only allowed when internal LDO is bypassed. Must be set to 1 to shape TX field on/off ST25R3920B 4.5.61 Application information AWS Config 2 register(a) Register Space: B Address: 2Fh Type: RW Table 95. AWS configuration 2 Bit Name Default Function Comments 7:6 RFU - - - 5 am_sym 0 0: Nonsymmetrical shape 1: Symmetrical shape For OOK modulation typically different signal fall and rise times are required and a non-symmetrical shape is preferred. For ASK modulation a symmetrical shape during signal fall and rise time is preferred. 0: weak sink during AWS modulation 1: strong sink during AWS modulation Selection between strong and weak sink for discharging VDD_AM Filter for AM reference in AWS Sets the time constant of the first order filter for the AM reference A higher am_filt value increases the signal rise and fall time in combination with AWS time register settings 4 en_modsink 0 3 am_filt3 0 2 am_filt2 0 1 am_filt1 0 0 am_filt0 0 a. Settings for this register are only applicable when bit rgs_am=1. DS13890 Rev 4 125/158 157 Application information 4.5.62 ST25R3920B Auxiliary display register Register space: A Address: 31h Type: R Table 96. Auxiliary display register Bit Name Default 7 a_cha - 0: AM 1: PM Receiver channel used in ongoing/last reception. 6 efd_o - 1: External field detected External field detector output. 5 tx_on - 1: Transmission is active Data transmission due to automatic handling of CE mode collision avoidance are not indicated. 4 osc_ok - 1: Xtal oscillation is stable Indication that Xtal oscillator is active and its output is stable. 3 rx_on - 1: Receive decoder is enabled - 2 rx_act - 1: Receive decoder is receiving a message - 1 en_peer - 1: External field detector is active in Peer detection mode - 0 en_ac - 1: External field detector is active in RF collision avoidance mode - 126/158 Function DS13890 Rev 4 Comments ST25R3920B 4.5.63 Application information Overshoot protection configuration register 1 Register space: B Address: 30h Type: RW Table 97. Overshoot protection configuration register 1 Bit Name Default 7 ov_tx_mode1 0 6 ov_tx_mode0 0 Function Comments 00: Drive with VDD_DR 01: Drive with VDD_AM 10: Driver stop (at GND / VDD_DR) 11: RFU Selects RF drive level to apply when ov_patternX is set to 1. ov_tx_mode is only effective when bit rgs_am=0 Applicable for all ov_pattern cells: Pulse drive in modulation period Applicable for all ov_pattern cells: rgs_am=0: – Drive level as defined in ov_tx_mode is applied rgs_am=1: – 0: Drive with VDD_DR – 1: Drive with VDD_AM 5 ov_pattern13 0 4 ov_pattern12 0 - - 3 ov_pattern11 0 - - 2 ov_pattern10 0 - - 1 ov_pattern9 0 - - 0 ov_pattern8 0 - - 4.5.64 Overshoot protection configuration register 2 Register space: B Address: 31h Type: RW Table 98. Overshoot protection configuration register 2 Bit Name Default Function Applicable for all ov_pattern cells: Pulse drive in modulation period Comments Applicable for all ov_pattern cells: rgs_am=0: – Drive level as defined in ov_tx_mode is applied rgs_am=1: – 0: Drive with VDD_DR – 1: Drive with VDD_AM 7 ov_pattern7 0 6 ov_pattern6 0 - - 5 ov_pattern5 0 - - DS13890 Rev 4 127/158 157 Application information ST25R3920B Table 98. Overshoot protection configuration register 2 (continued) Bit Name Default Function Comments 4 ov_pattern4 0 - - 3 ov_pattern3 0 - - 2 ov_pattern2 0 - - 1 ov_pattern1 0 - - 0 ov_pattern0 0 - - 4.5.65 Undershoot protection configuration register 1 Register space: B Address: 32h Type: RW Table 99. Undershoot protection configuration register 1 Bit Name Default 7 un_tx_mode1 0 6 un_tx_mode0 0 Function Comments 00: Drive with VDD_DR 01: Drive with VDD_AM 10: Driver stop (at GND / VDD_DR) 11: RFU Selects RF drive level to apply when un_patternX is set to 1. un_tx_mode is only effective when bit rgs_am=0 Applicable for all un_pattern cells: Pulse drive after modulation period Applicable for all un_pattern cells: rgs_am=0: – Drive level as defined in un_tx_mode is applied rgs_am=1: – 0: Drive with VDD_DR – 1: Drive with VDD_AM 5 un_pattern13 0 4 un_pattern12 0 - - 3 un_pattern11 0 - - 2 un_pattern10 0 - - 1 un_pattern9 0 - - 0 un_pattern8 0 - - 128/158 DS13890 Rev 4 ST25R3920B 4.5.66 Application information Undershoot protection configuration register 2 Register space: B Address: 33h Type: RW Table 100. Undershoot protection configuration register 2 Bit Name Default Function Applicable for all un_pattern cells: Pulse drive after modulation period Comments Applicable for all un_pattern cells: rgs_am=0: – Drive level as defined in un_tx_mode is applied rgs_am=1: – 0: Drive with VDD_DR – 1: Drive with VDD_AM 7 un_pattern7 0 6 un_pattern6 0 - - 5 un_pattern5 0 - - 4 un_pattern4 0 - - 3 un_pattern3 0 - - 2 un_pattern2 0 - - 1 un_pattern1 0 - - 0 un_pattern0 0 - - DS13890 Rev 4 129/158 157 Application information 4.5.67 ST25R3920B Wake-up timer control register Register space: A Address: 32h Type: RW Table 101. Wake-up timer control register Bit Name Default Function Comments 7 wur 0 6 wut2 0 5 wut1 0 4 wut0 0 3 wto 0 1: IRQ at every timeout 2 wam 0 1: At timeout perform amplitude measurement Generates I_wam interrupt if amplitude difference is larger than ∆am. 1 wph 0 1: At timeout perform phase measurement Generates I_wph interrupt if phase difference islarger than ∆pm. 0 RFU 0 0: 100 ms 1: 10 ms Wake-up timer range Refer to Table 102 Wake-up timer timeout value - - - Table 102. Typical wake-up time 130/158 wut2 wut1 wut0 100 ms range (wur = 0) 10 ms range (wur = 1) 0 0 0 100 ms 10 ms 0 0 1 200 ms 20 ms 0 1 0 300 ms 30 ms 0 1 1 400 ms 40 ms 1 0 0 500 ms 50 ms 1 0 1 600 ms 60 ms 1 1 0 700 ms 70 ms 1 1 1 800 ms 80 ms DS13890 Rev 4 ST25R3920B 4.5.68 Application information Amplitude measurement configuration register Register space: A Address: 33h Type: RW Table 103. Amplitude measurement configuration register Bit Name Default 7 am_d3 0 6 am_d2 0 5 am_d1 0 4 am_d0 0 3 am_aam 0 2 am_aew1 0 1 am_aew2 0 0 am_ae 0 4.5.69 Function Comments Definition of ∆am (difference vs. reference that triggers interrupt) - 0: Exclude the IRQ measurement Includes/excludes the measurement that causes IRQ (having difference > ∆am to 1: Include the IRQ measurement reference) in auto-averaging. 00: 4 01: 8 10: 16 11: 32 Weight of last measurement result for auto-averaging. 0: Use Amplitude measurement reference register Selects reference value for amplitude measurement Wake-up mode. Amplitude measurement reference register Register space: A Address: 34h Type: RW Table 104. Amplitude measurement reference register Bit Name Default Function Comments 7 am_ref7 0 - - 6 am_ref6 0 - - 5 am_ref5 0 - - 4 am_ref4 0 - - 3 am_ref3 0 - - 2 am_ref2 0 - - 1 am_ref1 0 - - 0 am_ref0 0 - - DS13890 Rev 4 131/158 157 Application information 4.5.70 ST25R3920B AWS time 1 register Register Space: B Address: 34h Type: RW Table 105. AWS time 1 register Bit Name Default Function 7 RFU 0 - 6 RFU 0 - - 5 RFU 0 - - 4 RFU 0 - - 3 tmodsw1_3 0 2 tmodsw1_2 0 1 tmodsw1_1 0 time Set the time in fc periods when clamp between VDD_RF and VDD_AM is released. 0 tmodsw1_0 0 4.5.71 Comments It must be set to 0 for bit 4 to 7 AWS time 2 register Register Space: B Address: 35h Type: RW Table 106. AWS time 2 register Bit Name Default 7 tammod1_3 0 6 tammod1_2 0 5 tammod1_1 0 4 tammod1_0 0 3 tdres1_3 0 2 tdres1_2 0 1 tdres1_1 0 0 tdres1_0 0 132/158 Function Comments time Sets the time in fc periods when the VDD_AM modulation starts changing and the driver switches to VDD_AM. The value should be smaller or equal to tmodsw1, it is recommended 0 time Set the time in fc periods when the driver resistance changes to modulation resistance. The recommended setting for bits tdres1 is 0 when using AWS. DS13890 Rev 4 ST25R3920B 4.5.72 Application information AWS time 3 register Register Space: B Address: 36h Type: RW Table 107. AWS time 3 register Bit Name Default 7 tentx1_3 0 6 tentx1_2 0 5 tentx1_1 0 4 tentx1_0 0 3 tmods2_3 0 2 tmods2_2 0 1 tmods2_1 0 0 tmods2_0 0 4.5.73 Function Comments Set the time in fc periods when the driver stops driving. The value depends on setting of am_filt. time It is the time in fc periods when the driver switches to VDD_RF. The value depends on setting of am_filt. AWS time 4 register Register Space: B Address: 37h Type: RW Table 108. AWS time 4 register Bit Name Default Function 7 RFU 0 - 6 RFU 0 - - 5 RFU 0 - - 4 RFU 0 - - 3 tmodsw2_3 0 2 tmodsw2_2 0 1 tmodsw2_1 0 0 tmodsw2_0 0 time DS13890 Rev 4 Comments It must be set to 0 for bit 4 to 7 Set the time in fc periods when clamp between VDD_RF and VDD_AM is connected. The value depends on am_filt. 133/158 157 Application information 4.5.74 ST25R3920B AWS time 5 register Register Space: B Address: 38h Type: RW Table 109. AWS time 5 register Bit Name Default 7 tdres2_3 0 6 tdres2_2 0 5 tdres2_1 0 4 tdres2_0 0 3 RFU 0 - 2 RFU 0 - - 1 RFU 0 - - 0 RFU 0 - - 4.5.75 Function Comments time Set the time in fc periods when the driver resistance changes to driving resistance. The recommended setting for bits tdres2 is 0 when using AWS. It must be set to 0 for bit 0 to 3. AWS time 6 register Register Space: B Address: 39h Type: R Table 110. AWS time 6 register Bit Name Default Function Comments 7:3 RFU 0 - - 2 rc_cal_ro_2 0 1 rc_cal_ro_1 0 0 rc_cal_ro_0 0 134/158 RC calibration readout DS13890 Rev 4 Center 011b, 8 steps available, the step size is 12 % ST25R3920B 4.5.76 Application information Amplitude measurement auto-averaging display register Register space: A Address: 35h Type: R Table 111. Amplitude measurement auto-averaging display register Bit Name Default Function Comments 7 amd_aad7 0 - - 6 amd_aad6 0 - - 5 amd_aad5 0 - - 4 amd_aad4 0 - - 3 amd_aad3 0 - - 2 amd_aad2 0 - - 1 amd_aad1 0 - - 0 amd_aad0 0 - - 4.5.77 Amplitude measurement display register Register space: A Address: 36h Type: R Table 112. Amplitude measurement display register Bit Name Default Function Comments 7 am_amd7 0 - - 6 am_amd6 0 - - 5 am_amd5 0 - - 4 am_amd4 0 - - 3 am_amd3 0 - - 2 am_amd2 0 - - 1 am_amd1 0 - - 0 am_amd0 0 - - DS13890 Rev 4 135/158 157 Application information 4.5.78 ST25R3920B Phase measurement configuration register Register space: A Address: 37h Type: RW Table 113. Phase measurement configuration register Bit Name Default 7 pm_d3 0 6 pm_d2 0 5 pm_d1 0 4 pm_d0 0 3 pm_aam 0 2 pm_aew1 0 1 0 4.5.79 pm_aew0 Comments Definition of ∆pm (difference to reference that triggers interrupt) 0 pm_ae Function 0 - 0: Exclude the IRQ measurement 1: Include the IRQ measurement Includes/excludes the measurement value that triggered the I_wph interrupt in the auto-averaging. 00: 4 01: 8 10: 16 11: 32 Weight of last measurement result for auto-averaging. 0: Use Phase measurement reference register 1: Use phase measurement auto-averaging as reference Selects reference value for phase measurement Wake-up mode. Phase measurement reference register Register space: A Address: 38h Type: RW Table 114. Phase measurement reference register Bit Name Default Function Comments 7 pm_ref7 0 - - 6 pm_ref6 0 - - 5 pm_ref5 0 - - 4 pm_ref4 0 - - 3 pm_ref3 0 - - 2 pm_ref2 0 - - 1 pm_ref1 0 - - 0 pm_ref0 0 - - 136/158 DS13890 Rev 4 ST25R3920B 4.5.80 Application information Phase measurement auto-averaging display register Register space: A Address: 39h Type: R Table 115. Phase measurement auto-averaging display register Bit Name Default Function Comments 7 pm_aad7 0 - - 6 pm_aad6 0 - - 5 pm_aad5 0 - - 4 pm_aad4 0 - - 3 pm_aad3 0 - - 2 pm_aad2 0 - - 1 pm_aad1 0 - - 0 pm_aad0 0 - - 4.5.81 Phase measurement display register Register space: A Address: 3Ah Type: R Table 116. Phase measurement display register Bit Name Default Function Comments 7 pm_amd7 0 0 - 6 pm_amd6 0 0 - 5 pm_amd5 0 0 - 4 pm_amd4 0 0 - 3 pm_amd3 0 0 - 2 pm_amd2 0 0 - 1 pm_amd1 0 0 - 0 pm_amd0 0 0 - DS13890 Rev 4 137/158 157 Application information 4.5.82 ST25R3920B Measurement TX delay Register space: A Address: 3Bh Type: RW Table 117. Measurement TX delay Bit Name Default 7 m_phase_ana 0 6 m_amp_ana 0 5 RFU 0 - - 4 RFU 0 - - 3 meas_tx_del3 0 2 meas_tx_del2 0 1 meas_tx_del1 0 0 meas_tx_del0 0 138/158 Function Comments Connects analog phase measurement signal to TAD2 (set tanato 07h) When m_amp_ana = 1 or m_phase_ana = 1, field gets enabled; not to be used during NFC communication: 00: disabled 01: Amplitude measurement signal to TAD2 Connects analog amplitude 10: Phase measurement signal to TAD2 measurement signal to 11: Amplitude measurement signal to TAD1, TAD1/TAD2 (set tanato 07h) The phase measurement signal to TAD2, to be used in Ready mode only. 0: Disabled >0: Delay enable according to Table 118 DS13890 Rev 4 meas_tx_del bits set the time to prolong the time before TX field is enabled and the measure amplitude and/or phase measurement is performed. ST25R3920B Application information Table 118. Wake-up time and wake-up pulse prolongation(1) wur wut Wake-up time meas_tx_del 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 10 ms 0 0.7 1.3 1.9 2.5 3.1 3.7 4.3 4.9 5.5 6.1 7.3 8.5 9.7 10.9 12.2 0 1 20 ms 0 0.4 1.0 1.6 2.3 2.9 3.5 4.1 4.7 5.3 5.9 7.1 8.3 9.5 10.7 11.9 0 2 30 ms 0 0 3 40 ms 0 NA 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.6 7.8 9.0 10.2 11.4 0 4 50 ms 0 NA NA 0.9 1.5 2.1 2.8 3.4 4.0 4.6 5.2 6.4 7.6 8.8 10.0 11.2 0 5 60 ms 0 NA NA 0.7 1.3 1.9 2.5 3.1 3.7 4.3 4.9 6.1 7.3 8.6 9.8 11.0 0 6 70 ms 0 NA NA NA 1.1 1.7 2.3 2.9 3.5 4.1 5.0 5.9 7.1 8.3 9.5 10.7 0 7 80 ms 0 NA NA NA 0.8 1.4 3.9 2.6 3.3 3.9 4.5 5.7 6.9 8.1 9.3 10.5 1 0 100 ms 0 0.9 1.5 2.1 2.7 3.3 3.9 4.5 5.1 5.7 6.3 7.5 8.7 9.9 11.2 12.4 1 1 200 ms 0 0.9 1.5 2.1 2.7 3.3 3.9 4.5 5.1 5.7 6.3 7.5 8.7 9.9 11.1 12.3 1 2 300 ms 0 0.8 1.4 2.0 2.7 3.3 3.9 4.5 5.1 5.7 6.3 7.5 8.7 9.9 11.1 12.3 1 3 400 ms 0 0.8 1.4 2.0 2.6 3.2 3.8 4.4 5.0 5.6 6.3 7.5 8.7 9.9 11.1 12.3 1 4 500 ms 0 0.8 1.4 2.0 2.6 3.2 3.8 4.4 5.0 5.6 6.2 7.4 8.6 9.9 11.1 12.3 1 5 600 ms 0 0.8 1.4 2.0 2.6 3.2 3.8 4.4 5.0 5.6 6.2 7.4 8.6 9.8 11.0 12.2 1 6 700 ms 0 0.8 1.4 2.0 2.6 3.2 3.8 4.4 5.0 5.6 6.2 7.4 8.6 9.8 11.0 12.2 1 7 800 ms 0 0.7 1.3 1.9 2.5 3.1 3.7 4.3 5.0 5.6 6.2 7.4 8.6 9.8 11.0 12.2 NA (2) Unit 0.8 1.4 2.0 2.6 3.2 3.8 4.4 5.0 5.6 6.8 8.1 9.3 10.5 11.7 ms 1. An additional +/- 20% tolerance must be considered for the meas_tx_del values. 2. Not applicable. DS13890 Rev 4 139/158 157 Application information 4.5.83 ST25R3920B IC identity register Register space: A Address: 3Fh Type: R Table 119. IC identity register Bit Name Default 7 ic_type4 0 6 ic_type3 0 5 ic_type2 1 4 ic_type1 1 3 ic_type0 0 2 ic_rev2 0 1 ic_rev1 0 0 ic_rev0 1 140/158 Function Comments IC type code 00110: ST25R3920B 5-bit IC type code IC revision code 001: rev 4.1 3-bit IC revision code DS13890 Rev 4 ST25R3920B Electrical characteristics 5 Electrical characteristics 5.1 Absolute maximum ratings Stresses beyond the limits listed in Table 120 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in Table 120 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 120. Absolute maximum ratings Symbol Parameter Min Max Positive supply voltage -0.3 6.0 Positive supply voltage when option bit sup3V is set -0.3 5 Difference between VDD and VDD_TX -0.3 0.3 Peripheral communication supply voltage -0.3 6 VGND(1) Negative supply voltage -0.3 0.3 VpIO(1) Voltage for peripheral IO communication pins (27 to 32) -0.3 6 Vp5V(1) Voltage for other pins (9, 11, 13, 14, 15, 17 and 20) in the 5 V domain -0.3 6 Vp3V(1) Voltage for other pins (2 to 5, 7, 18, 19 and 22 to 25) in the 3 V domain -0.3 5 Input current (latch-up immunity) according to JESD78 -100 100 - 350(3) VDD, VDD_TX(1) (1)(2) VDD, VDD_TX ∆VDD-VDD_TX(1) VDD_IO(1) Iscr IVDD_LDO Maximum driver current using internal voltage regulator IVDD_EXT(4) Peak current supplied from an external source, internal voltage regulator bypassed VESD Electrostatic pulse (human body model)(6) Tstrg Storage temperature Tbody Package body temperature according to IPC/JEDEC J-STD-020(7) TJun Junction temperature - Humidity non-condensing Unit V mA 500(5) - 2000 -65 150 - 260 -40 125 5 85 mA V °C % 1. Referenced to VSS. 2. Bit sup3V set to 1 in IO configuration register 2. 3. Provide good thermal management to ensure that junction temperature remains below the specified value. 4. VDD_RF is connected to VDD_TX to bypass the internal voltage regulator. 5. Peak current with RF driver externally supplied. Provide good thermal management to ensure that junction temperature remains below the specified value. 6. Positive and negative pulses applied on different combinations of pin connections, according to AEC-Q100-002 (compliant with ANSI/ESDA/JEDEC JS-001 standard, C1=100 pF, R1=1500 Ω). 7. Reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices”. DS13890 Rev 4 141/158 157 Electrical characteristics 5.2 ST25R3920B Operating conditions All defined tolerances for external components in this specification need to be ensured over the whole operation conditions range and also over lifetime. Table 121. Operating conditions Symbol VDD, VDD_TX(1) (2) ∆VDD-VDD_TX(1) Parameter Min Max Positive supply voltage (pins 8 and 10), Tamb = -40 to 105 °C, rege ≥ 07h 2.6 5.5 Positive supply voltage (pins 8 and 10), Tamb = -20 to 105 °C 2.4 5.5 Positive supply voltage when option bit sup3V is set(3), Tamb = -40 to 105 °C, rege ≥ 07h 2.6 3.6 Positive supply voltage when option bit sup3V is set(3), Tamb = -20 to 105 °C 2.4 3.6 V Difference between VDD and VDD_TX -0.2 0.2 VDD_IO(1) Peripheral communication supply voltage (pin 1) 1.65 5.5 VGND(1) Negative supply voltage (pins 6, 12, 16 and 26) 0 0 VpIO(1) Voltage for peripheral IO communication pins (27 to 32) 0 5.5 Vp5V(1) Voltage for other pins (9, 11, 13, 14, 15, 17, and 20) in the 5 V domain 0 5.5 Vp3V(1) Voltage for other pins (2 to 5, 7, 18, 19 and 22 to 25) in the 3 V domain 0 3.6 -40 105 °C 0.15 3 VPP T(amb, VFQFPN32)(4) VRFI_A Ambient temperature range for VFQFPN32 package RFI input amplitude(5) 1. Referenced to VSS. 2. If power supply is lower than 2.6 V, PSSR cannot be improved using internal regulators (minimum regulated voltage is 2.4 V). 3. Bit sup3V set to 1 in IO configuration register 2. 4. The device must be mounted on a PCB with sufficient heat dissipation. 5. The minimum RFI input signal definition is meant for NFC active P2P reception and NFC passive target reception. In HF reader mode and NFC transmit mode recommended signal level is 2.5 VPP. 142/158 Unit DS13890 Rev 4 V ST25R3920B 5.3 Electrical characteristics DC/AC characteristics for digital inputs and outputs Table 122. Characteristics of CMOS I/Os(1) Type Inputs(2) Symbol Parameter Conditions Min Typ Max Unit VIH High level input voltage - 0.8 * VDD_IO - - VIL Low level input voltage - - - 0.2 * VDD_IO VDD_IO = 5.5 V -1 - 1 - - - - ILEAK VOH Input leakage current High level output voltage Output VOL Low level output voltage Isource = 1 mA VDD_IO = 3.3 to 5.5 V, io_drv_lvl=0(3) Isource = 0.5 mA VDD_IO = 1.65 to 3.3 V(4) io_drv_lvl = 1 V µA 0.9 * VDD_IO V Isource = 1 mA VDD_IO = 3.3 to 5.5 V(3), io_drv_lvl=0 - - 0.1 * VDD_IO Isource = 0.5 mA VDD_IO = 1.65 to 3.3 V(4) io_drv_lvl = 1 - - 0.1 * VDD_IO - - - 50 pF CL Capacitive load RO Output resistance VDD_IO = 3.3 V - 250 500 Ω RPD Pull-down resistance pin MISO(5) VDD_IO = 3.3 V - 10 - kΩ 1. Min and Max values tested in production at 25 °C and 125 °C, other temperature values evaluated by characterization. 2. Pins BSS, MOSI and SCLK. 3. Tested in production at 3.3 V at 25 °C, other temperature and VDD_IO values evaluated by characterization. 4. Tested in production at 1.8 V at 25 °C, other temperature and VDD_IO values evaluated by characterization. 5. Use bits miso_pd1 and miso_pd2 in the IO configuration register 2 to control the optional pull down on the MISO pin. DS13890 Rev 4 143/158 157 Electrical characteristics 5.4 ST25R3920B Electrical specifications Table 123. ST25R3920B electrical characteristics (VDD = 3.3 V) (1)(2) Symbol Parameter Conditions TJun = -40 °C to 25 °C IPD TJun = 85 °C (3) Supply current in Power-down mode TJun = 125 °C (3) TJun = -40 °C to 25 °C INFCT (3) Supply current in Initial NFC target mode TJun = 85 °C (4) (4) TJun = 125 °C (4) IWU TJun = -40 °C to 25 °C Supply current in Wake-up mode (logic and RC oscillator) TJun = 85 °C (5) Min Typ Max - 0.8 2.5 - 2 20 - 12 60 - 3.5 7.0 - 4.25 20 - 14 60 - 3.0 6.3 3.8 20 15 60 (5) TJun = 125 °C (5) Unit µA µA µA Supply current in Ready mode (6) - 4.5 7.5 mA Supply current all active (7) - 16 23 mA IAWS Supply current all active, AWS (8) - 17 26 mA RRFO RFO1 and RFO2 driver output resistance VRFO = 150 mV - 1.7 4 Ω RRFI RFI input resistance - - 12 16 kΩ VPOR Power on reset voltage IRD IAL - 1.0 1.45 2.0 AGDC voltage (6) 1.4 1.5 1.6 VREG Regulated voltage (9) 2.65 3.00 3.20 RTAD Testpin output resistance - - 0.5 1.5 VAGDC V kΩ 1. 3.3 V supply mode with VDD = 3.3 V, unless noted otherwise. Regulated voltages are set at 3.0 V, 27.12 MHz Xtal connected to XTO and XTI. 2. Min and Max values tested in production at 25 °C and 125 °C, other temperature values evaluated by characterization. 3. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), other registers in default state. 4. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), 02h to 03h (external field detector enable), 03h to E8h (enable NFC Target mode), other registers in default state. 5. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), 02h to 04h (enable Wake-up mode), 32h to 08h (100 ms timeout, IRQ at every timeout), other registers in default state. 6. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to 80h (en = 1), 2Ch to D8h (3.0 V regulator), other registers in default state, short VDD_A and VDD_D. 7. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to C8h (enable RX, enable TX), 28h to 7Fh (RFO segments disabled), 2Ch to D8h (3.0 V regulator), other registers in default state, short VDD_A and VDD_D. 8. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to C8h (enable RX, enable TX), 03h to 14h (AM modulation), 28h to 7Fh (RFO segments disabled), 2Ch to D8h (3.0 V regulator), other registers in default state, short VDD_A and VDD_D. 9. Manual regulator mode, regulated voltage set to 3.0 V, measured on pin VDD_RF: register 00h set to 0Fh, register 01h set to 80h (3 V supply mode), register 02h set to E8h (one channel RX, enable TX), 2Ch to D8h (3.0 V regulator), other registers in default state. 144/158 DS13890 Rev 4 ST25R3920B Electrical characteristics Table 124. ST25R3920B electrical characteristics (VDD = 5.5 V) (1) (2) Symbol IPD Parameter Supply current in Power-down mode Conditions TJun = -40 to 25 °C (3) TJun = 125 °C (3) TJun = 85 °C INFCT Supply current in initial NFC target mode TJun = -40 to 25 °C (4) TJun = 125 °C (4) TJun = 85 °C IWU Supply current in Wake-up mode (logic and RC oscillator) TJun = -40 to 25 °C (5) TJun = 125 °C (5) Min Typ Max - 1 3 - - 90 - 2.5 25 - 3.4 8 - 35 90 - 5 25 - 3 8 - 15 90 5 25 TJun = 85 °C Unit µA Supply current in Ready mode (6) - 5.6 7.5 mA Supply current all active (7) - 16.0 23.0 mA IAWS Supply current all active, AWS (8) - 19.0 26.0 mA RRFO RFO1 and RFO2 driver output resistance - 1.7 4 Ω RRFI RFI input resistance - 12.5 16 kΩ VPOR Power on reset voltage IRD IAL VRFO = 150 mV(9) (9)(10) - 1.00 1.45 2.00 1.40 1.50 1.60 VAGDC AGDC voltage (7) VREG Regulated voltage (7) 4.3 5.0 5.3 Testpin output resistance (9) - 0.6 1.5 RTAD V kΩ 1. Min and Max values tested in production at 25 °C and 125 °C, other temperature values evaluated by characterization. 2. 5.0 V supply mode with VDD = 5.5 V unless noted otherwise. Regulated voltages set to 5.1 V, 27.12 MHz crystal connected to XTO and XTI. 3. Registers 00h to 07h (no clock on MCU_CLK), 01h to 00h (5 V supply mode), other registers in default state. 4. Registers 00h to 07h (no clock on MCU_CLK), 01h to 00h (5 V supply mode), 02h to 03h (external field detector enable), 03h to E8h (enable NFC Target mode), other registers in default state. 5. Registers 00h to 07h (no clock on MCU_CLK), 01h to 00h (5 V supply mode), 02h to 04h (enable Wake-up mode), 32h to 08h (100 ms timeout, IRQ at every timeout), other registers in default state. 6. Registers 00h to 07h (no clock on MCU_CLK), 01h to 40h (5 V supply mode, disable VDD_D), 02h to 80h (en = 1), 2Ch to F8h (5.1 V regulator), other registers in default state, short VDD_A and VDD_D. 7. Registers 00h to 07h (no clock on MCU_CLK), 01h to 40h (5 V supply mode, disable VDD_D), 02h to C8h (enable RX, enable TX), 28h to 7Fh (RFO segments disabled), 2Ch to F8h (5.1 V regulator), other registers in default state, short VDD_A and VDD_D. 8. Registers 00h to 07h (no clock on MCU_CLK), 01h to 40h (5 V supply mode, disable VDD_D), 02h to C8h (enable RX, enable TX), 03h to 14h (AM modulation), 28h to 7Fh (RFO segments disabled), 2Ch to F8h (5.1 V regulator), other registers in default state, short VDD_A and VDD_D. 9. Evaluated by characterization - not tested in production. 10. fSUB = 848 kHz, AM channel with peak detector input stage selected. DS13890 Rev 4 145/158 157 Electrical characteristics ST25R3920B Table 125. ST25R3920B electrical characteristics (VDD = 2.4 V)(1) (2) Symbol IPD Parameter Supply current in Power-down mode Conditions TJun = -40 to 25 °C (3) TJun = 85 °C (3) TJun = 125 °C INFCT Supply current in initial NFC target mode (4) TJun = 125 °C IWU Supply current in Wake-up mode (logic and RC oscillator) Max - 0.5 2.2 - 1.5 15 7.0 50 - 1.5 5 - 2 15 8 50 - 1.8 5 - 2.7 15 9 50 (4) TJun = -40 to 25 °C (5) TJun = 85 °C (5) TJun = 125 °C Typ (3) TJun = -40 to 25 °C (4) TJun = 85 °C Min (5) Unit µA Supply current in Ready mode (6) - 3.4 7.5 mA Supply current all active (7) - 14 23 mA IAWS Supply current all active, AWS (8) - 15 26 mA RRFO RFO1 and RFO2 driver output resistance - 1.7 4 Ω RRFI RFI input resistance - 12 16 kΩ VPOR Power on reset voltage IRD IAL VRFO = 150 mV(9) (9)(10) - 1.00 1.45 2.00 1.40 1.50 1.60 VAGDC AGDC voltage (7) VREG Regulated voltage (7) 2.20 2.40 2.45 Testpin output resistance (9) - 0.5 1.5 RTAD V kΩ 1. Min and Max values tested in production at 25 °C and 125 °C, other values evaluated by characterization. 2. 3.3 V supply mode with VDD = 2.4 V unless noted otherwise. Regulated voltages set to 2.4 V, 27.12 MHz crystal connected to XTO and XTI. 3. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), other registers in default state. 4. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), 02h to 03h (external field detector enable), 03h to E8h (enable NFC Target mode), other registers in default state. 5. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), 02h to 04h (enable Wake-up mode), 32h to 08h (100 ms timeout, IRQ at every timeout), other registers in default state. 6. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to 80h (en = 1), 2Ch to A8h (2.4 V regulator), other registers in default state, short VDD_A and VDD_D. 7. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to C8h (enable RX, enable TX), 28h to 7Fh (RFO segments disabled), 2Ch to A8h (2.4 V regulator), other registers in default state, short VDD_A and VDD_D. 8. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to C8h (enable RX, enable TX), 03h to 14h (AM modulation), 28h to 7Fh (RFO segments disabled), 2Ch to A8h (2.4 V regulator), other registers in default state, short VDD_A and VDD_D. 9. Evaluated by characterization - not tested in production. 10. fSUB = 848 kHz, AM channel with peak detector input stage selected. 146/158 DS13890 Rev 4 ST25R3920B 5.5 Electrical characteristics SPI interface characteristics Table 126. SPI characteristics (5 MHz) (1) Operation General Symbol Parameter Conditions Min Typ Max TSCLK = TSCLKL + TSCLKH - 200 - TSCLK SCLK period TSCLKL SCLK low - 95 - - TSCLKH SCLK high - 95 - - TSSH SPI reset (BSS high) - 100 - - TNCSL BSS falling to SCLK rising First SCLK pulse 25 - - TNCSH SCLK falling to BSS rising Last SCLK pulse 25 - - TDIS Data in setup time - 10 - - TDIH Data in hold time - 10 - - Cload ≤ 50 pF, VDD_IO = 1.65 to 3.0 V - 80 95 Cload ≤ 50 pF, VDD_IO = 3.0 to 5.5 V - - 70 Cload ≤ 50 pF - 20 - TDOD Data out delay Read TDOHZ Data out to high impedance delay Unit ns 1. Evaluated by characterization - not tested in production. Figure 30. SPI timing diagram - General operation BSS tNCSL tSCLKH ... tSCLKL SCLK ... tDIS MOSI tNCSH tDIH DATAI DATAI ... DATAI ... MISO MS49945V1 DS13890 Rev 4 147/158 157 Electrical characteristics ST25R3920B Figure 31. SPI timing diagram - Read operation BSS ... ... SCLK MOSI ... DATAI DATAO MISO tDOD ... DATAO tDOHZ MS49946V1 148/158 DS13890 Rev 4 ST25R3920B 5.6 Electrical characteristics I2C interface characteristics Timing according to I2C protocol. Drivers for up to 3.4 MHz operation. Transition from 100 kHz / 400 kHz / 1 MHz mode to 3.4 MHz mode (High speed mode) is done via Master code 00001XXX, as described in the I2C specification. Table 127. AC measurement conditions Symbol CBUS Parameter Min Max Load capacitance - Unit 100 SCL input rise/fall time, SDA input fall time - pF 50 ns Table 128. AC measurement conditions - I2C configuration Mode Rate Setting S 100 kHz i2c_thd = 00b, io_drv_lvl = 1b F 400 kHz i2c_thd = 01b, io_drvl_lvl = 1b F+ 1000 kHz i2c_thd = 11b, Io_drv_lvl = 1b HS 3400 kHz i2c_thd = 11b, io_drv_lvl = 1b Table 129. Input parameters(1) Symbol CIN Parameter Conditions Min Max Input capacitance (SDA) - - 15 Input capacitance (SCL) - - 15 Unit pF 1. Evaluated by characterization - not tested in production. Table 130. DC characteristics(1) Symbol Parameter Conditions (in addition to those in Table 127 and Table 128) Min Max ILI Input leakage VIN = VSS or VCC, device in current (SCL, SDA) Standby mode - ± 10 ILO Output leakage current - ± 10 VIL Input low voltage (SCL, SDA) - -0.4 0.2 VDD_IO VIH Input high voltage (SCL, SDA) - VOL Output low voltage SDA in Hi-Z, external voltage applied on SDA: VSS or VCC Unit µA 0.8 VDD_IO VDD_IO + 0.4 VDD_IO = 1.65 V, IOL = 2.5 mA - 0.1 VDD_IO VDD_IO = 2.4 V, IOL = 3.0 mA - 0.1 VDD_IO VDD_IO = 3.3 V, IOL = 8 mA - 0.1 VDD_IO VDD_IO = 5.5 V, IOL = 8 mA - 0.1 VDD_IO V 1. Evaluated by characterization - not tested in production. DS13890 Rev 4 149/158 157 Electrical characteristics ST25R3920B Table 131. 100 kHz AC characteristics(1) Symbol Alt. Parameter Min Max Unit fC fSCL Clock frequency - 100 kHz tCHCL tHIGH Clock pulse width high 4000 - tCLCH tLOW Clock pulse width low 4700 - tQL1QL2 tF SDA (out) fall time - 300 tDXCH tSU:DAT Data in set up time 250 - tCLDXX tHD:DAT Data in hold time 5000 - tCLQX tDH Data out hold time 50 - tCLQV tAA Clock low to next data valid (access time) - 3450 tCHDL tSU:STA Start condition setup time 4700 - tDLCL tHD:STA Start condition hold time 4000 - tCHDH tSU:STO Stop condition set up time 4000 - tDHDL tBUF Time between Stop condition and next Start condition 4700 - tNS(2) - Pulse width ignored (input filter on SCL and SDA), single glitch - 40 Min Max Unit - 400 kHz ns 1. Conditions in addition to those specified in Table 127 and Table 128. 2. Evaluated by characterization - not tested in production. Table 132. 400 kHz AC characteristics(1) (2) Symbol Alt. Parameter fC fSCL Clock frequency tCHCL tHIGH Clock pulse width high 600 - tCLCH tLOW Clock pulse width low 1300 - tQL1QL2 tF SDA (out) fall time - 300 tDXCH tSU:DAT Data in set up time 100 - tCLDXX tHD:DAT Data in hold time 0 - tCLQX tDH Data out hold time 50 - tCLQV tAA Clock low to next data valid (access time) - 900 tCHDL tSU:STA Start condition setup time 600 - tDLCL tHD:STA Start condition hold time 600 - tCHDH tSU:STO Stop condition set up time 600 - tDHDL tBUF Time between Stop condition and next Start condition 1300 - tNS - Pulse width ignored (input filter on SCL and SDA), single glitch - 40 1. Conditions in addition to those specified in Table 127 and Table 128. 2. Evaluated by characterization - not tested in production. 150/158 DS13890 Rev 4 ns ST25R3920B Electrical characteristics Table 133. 1 MHz AC characteristics(1)(2) Symbol Alt. Parameter Min Max Unit fC fSCL Clock frequency - 1 MHz tCHCL tHIGH Clock pulse width high 260 - tCLCH tLOW Clock pulse width low 500 - tQL1QL2 tF SDA (out) fall time - 120 tDXCH tSU:DAT Data in set up time 50 - tCLDXX tHD:DAT Data in hold time 0 - tCLQX tDH Data out hold time 50 - tCLQV tAA Clock low to next data valid (access time) - 450 tCHDL tSU:STA Start condition setup time 250 - tDLCL tHD:STA Start condition hold time 250 - tCHDH tSU:STO Stop condition set up time 250 - tDHDL tBUF Time between Stop condition and next Start condition 500 - tNS - Pulse width ignored (input filter on SCL and SDA), single glitch - 40 ns 1. Conditions in addition to those specified in Table 127 and Table 128. 2. Evaluated by characterization - not tested in production. Table 134. 3.4 MHz AC characteristics(1)(2)(3) Symbol Alt. Parameter Min Max Unit fC fSCL Clock frequency - 3.4 MHz tCHCL tHIGH Clock pulse width high 80 - tCLCH tLOW Clock pulse width low 160 - tQL1QL2 tF - 41 tDXCH tSU:DAT Data in set up time 25 - tCLDXX tHD:DAT Data in hold time 0 - tCLQX tDH Data out hold time 20 - tCLQV tAA Clock low to next data valid - 150 tCHDL tSU:STA Start condition setup time 160 - tDLCL tHD:STA Start condition hold time 160 - tCHDH tSU:STO Stop condition set up time 160 - tNS - - 10 SDA (out) fall time (10-100 pF) Pulse width ignored (input filter on SCL and SDA), single glitch ns 1. Conditions in addition to those specified in Table 127 and Table 128. 2. Evaluated by characterization - not tested in production. 3. VDD_IO supply must not exceed VDD. DS13890 Rev 4 151/158 157 Electrical characteristics ST25R3920B Figure 32. RPmin vs. VDD, fc = 3.4 MHz Figure 33. Maximum Rbus value vs. bus parasitic capacitance, fc = 3.4 MHz VDD 8000 7000 Rbus Ÿ 6000 Rbus 5000 SCL I2C bus master 4000 ST25R39xx SDA 3000 Cbus 2000 1000 10 20 30 Bus parasitic capacitance (pF) 152/158 DS13890 Rev 4 40 50 MS53555V3 ST25R3920B Electrical characteristics Figure 34. I2C AC waveforms Start condition tXH1XH2 Stop Start condition condition tXL1XL2 tCHCL tCLCH SCLK/SCL tCHDL tXL1XL2 MISO/SDA in tCHDL tXH1XH2 SDA input tCLDX SDA tDHCX change tCHDH Stop condition tDHDL Start condition SCLK/SCL MISO/SDA in tCHDH tW tCHDL Write cycle tCHCL SCLK/SCL tCHQV MISO/SDA out Data valid tCLQX tQL1QL2 Data valid MS51627V1 Figure 35. I2C AC measurements Input voltage levels 0.8VCC Input and output Timing reference levels 0.7VCC 0.3VCC 0.2VCC MS19774V1 DS13890 Rev 4 153/158 157 Package information 6 ST25R3920B Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com. ECOPACK is an ST trademark. 6.1 VFQFPN32 package information VFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch, very thin fine pitch quad flat no lead package. Figure 36. VFQFPN32 - Outline B A 32 Pin #1 ID 1 24 Pin #1 ID Chamfer 0.35 E2 E D2 8 S1 L 16 e A1 32x bbb M C A B BOTTOM VIEW 0.10 Ref. A3 SIDE VIEW TOP VIEW Detail A ccc C Terminal length L D A b 32x eee C Terminal thickness 0.05 Ref. C Detail A SLP1 PLATED AREA SIDE VIEW B04R_ME_V1 1. Drawing is not to scale. 2. Coplanarity applies to the exposed pad as well as the terminal. Table 135. VFQFPN32 - Mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.800 0.900 1.000 0.0315 0.0354 0.0394 A1 0 - 0.050 0 - 0.0020 A3 L 154/158 0.200 0.300 0.400 0.0079 0.500 DS13890 Rev 4 0.0118 0.0157 0.0197 ST25R3920B Package information Table 135. VFQFPN32 - Mechanical data (continued) inches(1) millimeters Symbol b Min Typ Max Min Typ Max 0.180 0.250 0.300 0.0071 0.0098 0.0118 D D2 5.000 3.400 E E2 3.500 0.1969 3.600 0.1339 0.1378 5.000 3.400 3.500 0.1417 0.1969 3.600 0.1339 0.1378 e 0.500 0.0197 S1 0.350 0.0138 0.1417 bbb - 0.100 - - 0.0039 - ccc - 0.100 - - 0.0039 - eee - 0.080 - - 0.0031 - 1. Values in inches are converted from mm and rounded to four decimal digits. Figure 37. VFQFPN32 - Footprint example 3.50 0.80 0.25 0.50 3.50 B04R_FP_V1 1. Dimensions are expressed in millimeters. DS13890 Rev 4 155/158 157 Ordering information 7 ST25R3920B Ordering information Table 136. Ordering information scheme Example: ST25 R 3920B -A QW T Device type ST25 = NFC/RFID tags and readers Product type R = NFC/HF reader Product feature 3920B = Automotive NFC reader for CCC digital key and car center console Ambient temperature range A = -40 °C to 105 °C Package/Packaging QW = 32-pin VFQFPN (5 x 5 mm) with wettable flanks Tape and reel T = 4000 pcs/reel (VFQFPN) Note: For a list of available options (speed, package, etc.) or for further information on any aspect of this device, contact your nearest ST sales office. Note: Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 156/158 DS13890 Rev 4 ST25R3920B 8 Revision history Revision history Table 137. Document revision history Date Revision 14-Apr-2022 1 Initial release 22-Apr-2022 2 Updated: – Features – Table 69: Number of transmitted bytes register 2 06-Jun-2022 3 Updated: – Table 119: IC identity register 4 Updated: – Figure 1: Minimum system configuration - Single sided antenna driving – Figure 2: Minimum system configuration - Differential antenna driving – Figure 4: ST25R3920B QFN32 pinout (top view) – Table 1: ST25R3920B VFQFPN32 pin assignment – Section 4.2.12: Active wave shaping – Table 1: ST25R3920B VFQFPN32 pin assignment – Table 9: Serial data interface (4-wire interface) signal lines 16-Nov-2022 Changes DS13890 Rev 4 157/158 157 ST25R3920B IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved 158/158 DS13890 Rev 4