ST25RU3992-BQFT

austriamicrosystems AG is now ams AG The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30 8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 e-Mail: ams_sales@ams.com Please visit our website at www.ams.com D atas hee t AS3992 UHF RFID Single Chip Reader EPC Class1 Gen2 Compatible The AS3992 is pin to pin and firmware compatible with the previous AS3990/91 IC's. It offers improved receive sensitivity to -86dB, programmable Rx Dense Reader Mode (DRM) filters on chip and pre-distortion. Fully scalable, the AS3992 is ideal for longer range and higher power applications. Filters dedicated to 250kHz and 320kHz M4 and M8 DRM operation. Available RX modes: - LF40kHz, 160kHz: FM0, M2, M4, M8 - LF 250kHz, 320kHz, 640kHz: M4, M8 ISO18000-6C (EPC Gen2) full protocol support ISO18000-6A,B compatibility in direct mode Programmable Dense Reader Mode filters on chip allowing a true World Wide Shippable device Improved receive sensitivity to -86dBm On chip pre-distortion meaning improved external PA efficiency am lc s on A te G nt st il Offering DRM filtering on chip, combined with improved sensitivity and pre-distortion allows the AS3992 to be the only true world wide shippable IC. The reader configuration is achieved through setting control registers allowing fine tuning of different reader parameters. Supply voltage range 4.1V to 5.5V al id The AS3992 UHF Reader chip is an integrated analog front-end and provides protocol handling for ISO180006c/b 900MHz RFID reader systems. Equipped with multiple built-in programming options, the device is suitable for a wide range of UHF RFID applications. 2 Key Features lv 1 General Description The AS3992 complies with EPC Class 1 Generation 2 protocol (ISO 18000-6C) and ISO 18000-6A/B (in direct mode). Integrated low level transmission coding, Integrated low level decoders Parallel or serial interface can be selected for communication between the host system (MCU) and the reader IC. When hardware coders and decoders are used for transmission and reception, data is transferred via 24 bytes FIFO register. In case of direct transmission or reception, coders and decoders are bypassed and the host system can service the analog front end in real time. Integrated data framing, Integrated CRC checking The transmitter generates 20dBm output power into 50Ω load and is capable of ASK or PR-ASK modulation. The integrated supply voltage regulators ensure supply rejection of the complete reader system. Can be powered by USB with no need for step conversion from 4.1V to 5.5V The transmission system comprises low level data coding. Automatic generation of FrameSync, Preamble, and CRC is supported. ni ca The receiver system allows AM and PM demodulation. The receiver also comprises automatic gain control option (patent pending) and selectable gain and signal bandwidth to cover a range of input link frequency and bit rate options. The signal strength of AM and PM modulation is measured and can be accessed in RSSI register. The receiver output is selectable between digitized sub-carrier signal and any of integrated sub-carrier decoders. Selected decoders deliver bit stream and data clock as outputs. ch The receiver system also comprises framing system. This system performs the CRC check and organizes the data in bytes. Framed data is accessible to the host system through a 24 byte FIFO register. Te To support external MCU and other circuitry a 3.3V regulated supply and clock outputs are available. The regulated supply has 20mA current capability. The AS3992 is available in a 64-pin QFN (9mm x 9mm), ensuring the smallest possible footprint. Parallel 8-bit or serial 4-pin SPI interface to MCU using 24 bytes FIFO Voltage range for communication to MCU between 1.8V and 5.5V Selectable clock output for MCU Integrated supply voltage regulator (20mA), which can be used to supply MCU and other external circuitry Integrated supply voltage regulator for the RF output stage, providing rejection to supply noise Internal power amplifier (20dBm) for short range applications Antenna driver using ASK or PR-ASK modulation Adjustable ASK modulation index AM & PM demodulation ensuring no “communication holes” with automatic I/Q selection Selectable reception gain, Reception automatic gain control AD converter for measuring TX power using external RF power detector DA converter for controlling external power amplifier Frequency hopping support On-board VCO and PLL covering complete RFID frequency range 840MHz to 960MHz Oscillator using 20MHz crystal Power down, standby and active mode available 3 Applications The device is an ideal solution for UHF RFID reader systems and hand-held UHF RFID readers. www.austriamicrosystems.com/AS3992 Revision 1.1 1 - 53 AS3992 Datasheet - A p p l i c a t i o n s 2xC VEXT VEXT2 16 17 AS3992 lv 13 15 18 VDD_D VDD_RF 19 VDD_B 54 AGD VDD_A 38 Supply Regulators & References 53 52 5 VDD_MIX VDD_TXPAB CD1 CD2 VDD_5LFI 3 31 30 ADC 58 DAC 4 7 MIX_INN 9 MIXS_IN 10 RFOUTN_1 27 RFOUTN_2 28 RFOUTP_1 20 RFOUTP_2 21 RFONX 32 RFOPX 33 EXT_IN 56 OSCI 37 DRM Filter Oscillator & Timing System VDDLF 61 VOSC VDD_RFP 41 VDD_IO IO0 42 IO1 43 44 IO2 IO3 45 IO4 46 IO5 47 IO6 48 IO7 51 Analog Front-end RSSI EPC Gen 2 Protocol Handling GEN-2 Frame Gen CRC 24 Byte FIFO 60 65 EXP_PAD 50 CLK 39 EN 40 IRQ 49 CLSYS Micro controller Te ch ni 8 11 12 14 22 23 24 25 26 29 35 55 57 VSS VSS VSN_MIX CBIB CBV5 VSN_1 VSN_2 VSN_3 VSN_4 VSN_5 VSN_D VSN_RFP VSN_A VSN_CP 62 6 63 7xC Digitizer Digitizer RF Out 59 34 Gain Filter ca OSCO VCO CP 36 IQ DownConversion Mixer MCU Interface OAD_2 MIX_INP Directional unit 1 am lc s on A te G nt st il OAD COMN_A COMN_B COMP_A COMP_B 4xC 64 2 al id Figure 1. AS3992 Block Diagram www.austriamicrosystems.com/AS3992 Revision 1.1 2 - 53 AS3992 Datasheet - C o n t e n t s Contents 1 2 Key Features............................................................................................................................................................................. 1 3 Applications............................................................................................................................................................................... 1 4 Pin Assignments ....................................................................................................................................................................... 5 4.1 Pin Descriptions.................................................................................................................................................................................... 5 al id 1 General Description .................................................................................................................................................................. 5 Absolute Maximum Ratings ...................................................................................................................................................... 8 6 Electrical Characteristics........................................................................................................................................................... 9 7 Detailed Description................................................................................................................................................................ 11 7.1 Supply................................................................................................................................................................................................. 11 lv 7.1.1 Power Modes............................................................................................................................................................................. 12 7.2 Host Communication .......................................................................................................................................................................... 13 7.3 VCO and PLL ..................................................................................................................................................................................... 13 am lc s on A te G nt st il 7.3.1 VCO and External RF Source.................................................................................................................................................... 13 7.3.2 PLL ............................................................................................................................................................................................ 13 7.4 Chip Status Control ............................................................................................................................................................................ 14 7.5 Protocol Control.................................................................................................................................................................................. 14 7.6 Option Registers Preset ..................................................................................................................................................................... 14 7.7 Transmitter.......................................................................................................................................................................................... 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 Normal Mode ............................................................................................................................................................................. Direct Mode ............................................................................................................................................................................... Modulator................................................................................................................................................................................... Amplifier..................................................................................................................................................................................... TX Pre-Distortion ....................................................................................................................................................................... 7.8 Receiver ............................................................................................................................................................................................. ni ca 7.8.1 Input Mixer ................................................................................................................................................................................. 7.8.2 DRM RX Filter............................................................................................................................................................................ 7.8.3 RX Filter Calibration................................................................................................................................................................... 7.8.4 Fast AC Coupling....................................................................................................................................................................... 7.8.5 RX Gain ..................................................................................................................................................................................... 7.8.6 Received Signal Strength Indicator (RSSI)................................................................................................................................ 7.8.7 Reflected RF Level Indicator ..................................................................................................................................................... 7.8.8 Normal Mode ............................................................................................................................................................................. 7.8.9 Direct Mode ............................................................................................................................................................................... 7.8.10 Normal Mode With Mixer DC Level Output and Enable RX Output Available ......................................................................... 7.9 ADC / DAC ......................................................................................................................................................................................... 14 14 16 16 17 17 17 17 18 19 19 19 20 20 20 21 21 22 ch 7.9.1 DA Converter ............................................................................................................................................................................. 22 7.9.2 AD Converter ............................................................................................................................................................................. 22 7.10 Reference Oscillator ......................................................................................................................................................................... 23 Te 8 Application Information ........................................................................................................................................................... 22 8.1 Configuration Registers Address Space............................................................................................................................................. 23 8.2 Main Configuration Registers ............................................................................................................................................................. 25 8.3 Control Registers - Low Level Configuration Registers...................................................................................................................... 26 8.4 Status Registers ................................................................................................................................................................................. 30 8.5 Test Registers..................................................................................................................................................................................... 33 8.6 PLL, Modulator, DAC, and ADC Registers ......................................................................................................................................... 35 www.austriamicrosystems.com/AS3992 Revision 1.1 3 - 53 AS3992 Datasheet - C o n t e n t s 8.7 RX Length Registers .......................................................................................................................................................................... 38 8.8 FIFO Control Registers....................................................................................................................................................................... 39 8.9 Direct Commands............................................................................................................................................................................... 40 41 41 41 41 41 41 41 41 42 42 42 42 42 42 42 am lc s on A te G nt st il lv al id 8.9.1 Idle (80)...................................................................................................................................................................................... 8.9.2 Hop to Main Frequency (84) ...................................................................................................................................................... 8.9.3 Hop to Auxiliary Frequency (85) ................................................................................................................................................ 8.9.4 Trigger AD Conversion (87)....................................................................................................................................................... 8.9.5 Trigger RX Filter Calibration (88)............................................................................................................................................... 8.9.6 Decrease RX Filter Calibration Data (89) .................................................................................................................................. 8.9.7 Increase RX Filter Calibration Data (8A) ................................................................................................................................... 8.9.8 Reset FIFO (8F)......................................................................................................................................................................... 8.9.9 Transmission With CRC (90) ..................................................................................................................................................... 8.9.10 Transmission With CRC Expecting Header Bit (91) ................................................................................................................ 8.9.11 Transmission Without CRC (92) .............................................................................................................................................. 8.9.12 Delayed Transmission With CRC (93)..................................................................................................................................... 8.9.13 Delayed Transmission Without CRC (94)................................................................................................................................ 8.9.14 Block RX (96)........................................................................................................................................................................... 8.9.15 Enable RX (97) ........................................................................................................................................................................ 8.10 EPC GEN2 Specific Commands ...................................................................................................................................................... 8.10.1 8.10.2 8.10.3 8.10.4 8.10.5 8.10.6 8.10.7 8.10.8 Query (98)................................................................................................................................................................................ QueryRep (99) ......................................................................................................................................................................... QueryAdjustUp (9A)................................................................................................................................................................. QueryAdjustNic (9B) ................................................................................................................................................................ QueryAdjustDown (9C)............................................................................................................................................................ ACK (9D) ................................................................................................................................................................................. NAK (9E).................................................................................................................................................................................. ReqRN (9F) ............................................................................................................................................................................. 8.11 Reader Communication Interface ..................................................................................................................................................... 42 42 42 42 43 43 43 43 43 43 8.12 Parallel Interface Communication..................................................................................................................................................... 45 8.13 Serial Interface Communication ....................................................................................................................................................... 47 8.13.1 Timing Diagrams...................................................................................................................................................................... 48 8.13.2 Timing Parameters .................................................................................................................................................................. 49 ca 8.14 FIFO ................................................................................................................................................................................................. 49 50 10 Ordering Information............................................................................................................................................................. 52 Te ch ni 9 Package Drawings and Markings ........................................................................................................................................... www.austriamicrosystems.com/AS3992 Revision 1.1 4 - 53 AS3992 Datasheet - P i n A s s i g n m e n t s 4 Pin Assignments CLSYS 49 al id VDD_IO CLK CD2 50 CD1 53 52 51 VSN_A AGD 55 56 54 VSN_CP EXT_IN 57 VDD_A ADC 59 58 VOSC VCO 62 60 CP 63 61 COMP_A VDDLF 64 Figure 2. Pin Assignments (Top View) 1 48 IO7 COMP_B 2 47 IO6 COMN_B 3 46 IO5 DAC 4 45 IO4 VDD_5LFI 5 44 IO3 VSS 6 43 IO2 MIX_INP VSS 7 8 42 IO1 41 IO0 MIX_INN 9 40 IRQ MIXS_IN 10 39 EN VSN_MIX 11 38 VDD_D CBIB 12 37 OSCO VDD_MIX 13 36 OSCI CBV5 14 35 VSN_RFP VDD_TXPAB 15 34 VDD_RFP VEXT 16 33 RFOPX am lc s on A te G nt st il lv COMN_A 28 29 30 31 32 RFOUTN_2 VSN_D OAD2 OAD RFONX 26 27 VSN_5 25 RFOUTN_1 24 VSN_3 VSN_4 21 RFOUTP_2 22 20 23 19 VDD_B RFOUTP_1 VSN_2 18 VSN_1 17 VEXT2 ca VDD_RF AS3992 4.1 Pin Descriptions Pin Number Pin Name Pin Type COMN_A Bidirectional ch 1 ni Table 1. Pin Descriptions Description Connect de-coupling capacitor to VDD_5LFI COMP_B Bidirectional 3 COMN_B Bidirectional 4 DAC Output 5 VDD_5LFI Supply Input Positive supply for LF input stage, connect to VDD_MIX 6 VSS Supply Input Substrate 7 MIX_INP Input 8 VSS Supply Input 9 MIX_INN Input Te 2 www.austriamicrosystems.com/AS3992 DAC output for external amplifier support, Output Resistance of DAC pin is 1kΩ Differential mixer positive input Substrate Differential mixer negative input Revision 1.1 5 - 53 AS3992 Datasheet - P i n A s s i g n m e n t s Table 1. Pin Descriptions Pin Number Pin Name Pin Type 10 MIXS_IN Input 11 VSN_MIX Supply Input Mixer negative supply 12 CBIB Bidirectional Internal node de-coupling capacitor to GND 13 VDD_MIX Supply Output Mixer positive supply, internally regulated to 4.8V 14 CBV5 Bidirectional Internal node de-coupling capacitor to VDD_MIX 15 VDD_TXPAB Supply Input Power Amplifier Bias positive supply. Connect to VDD_MIX 16 VEXT Supply Input Main positive supply input (5V to 5.5V) 17 VEXT2 Supply Input PA positive supply regulator input (2.5V to 5.5V) 18 VDD_RF Supply Output PA positive supply regulator output, internally regulated to 2V-3.5V 19 VDD_B Supply Output PA buffer positive supply. Internally regulated to 3.4V 20 RFOUTP_1 Output 21 RFOUTP_2 Output 22 VSN_1 Supply Input 23 VSN_2 Supply Input 24 VSN_3 Supply Input 25 VSN_4 Supply Input 26 VSN_5 Supply Input 27 RFOUTN_1 Output 28 RFOUTN_2 Output 29 VSN_D Supply Output 30 OAD2 Bidirectional Analog or digital received signal output and MCU support mode sense input 31 OAD Bidirectional Analog or digital received signal output 32 RFONX Output Low power linear negative RF output (~0dBm) 33 RFOPX Output Low power linear positive RF output (~0dBm) 34 VDD_RFP Supply Output 35 VSN_RFP Supply Input 36 OSCI Input OSCO Bidirectional Crystal oscillator output or external 20MHz clock input VDD_D Supply Output Digital part positive supply, internally regulated to 3.4V EN Input 40 IRQ Output 41 IO0 Bidirectional 42 IO1 Bidirectional 43 IO2 Bidirectional I/O pin for parallel communication EnableRX input in case of direct mode 44 IO3 Bidirectional I/O pin for parallel communication Modulation input in case of direct mode 45 IO4 Bidirectional I/O pin for parallel communication Slave select in case of serial communication (SPI) 38 lv al id Single ended mixer input PA positive RF output RFOUT1 and RFOUT2 must be tied together am lc s on A te G nt st il ca Te ch 39 ni 37 Description www.austriamicrosystems.com/AS3992 PA negative supply PA negative RF output or used in single ended mode. RFOUT1 and RFOUT2 must be tied together Digital negative supply RF path positive supply, internally regulated to 3.4V RF path negative supply Crystal oscillator input Enable input Interrupt output I/O pin for parallel communication Revision 1.1 6 - 53 AS3992 Datasheet - P i n A s s i g n m e n t s Table 1. Pin Descriptions Pin Number Pin Name Pin Type Description 46 IO5 Bidirectional I/O pin for parallel communication Sub-carrier output in case of direct mode IO6 Bidirectional 48 IO7 Bidirectional I/O pin for parallel communication. MOSI in case of serial communication (SPI) 49 CLSYS Output 50 CLK Input 51 VDD_IO Supply Input 52 CD2 Bidirectional 53 CD1 Bidirectional 54 AGD Bidirectional Analog reference voltage 55 VSN_A Supply Input Analog part negative supply 56 EXT_IN Input 57 VSN_CP Supply Input 58 ADC Input 59 VDD_A Supply Output 60 VCO Input 61 VOSC Bidirectional 62 CP Output 63 VDDLF Supply Input Positive supply for LF processing, internally regulated to 3.4 64 COMP_A Bidirectional Internal node, connect de-coupling capacitor to VDD_5LFI 65 EXP_PAD Supply Input Exposed paddle, must be tied to GND Clock output for MCU operation al id 47 I/O pin for parallel communication. MISO in case of serial communication (SPI) Sub-carrier output in case of direct mode Clock input for MCU communication (parallel and serial) am lc s on A te G nt st il Internal node de-coupling capacitor lv Positive supply for peripheral communication, connect to host positive supply RF input in case external VCO is used Charge pump negative supply ADC input for external power detector support Analog part positive supply, internally regulated to 3.4V VCO input Internal node de-coupling capacitor Te ch ni ca Charge pump output www.austriamicrosystems.com/AS3992 Revision 1.1 7 - 53 AS3992 Datasheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 9 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Min Max Units Comments -0.3 6 V All voltage values are with respect to substrate ground terminal VSS VEXT+0.3 V For pins EN, I07..IO0, CLK, IRQ, CLSYS, VDDIO, VDD_MIX, VDD_5LFI, VDD_TXPAB, CBV5, DAC, OAD, OAD2 4.5 V For other pins -0.3 V For other pins ±100 mA According to JEDEC 78 kV According to MIL 883 E method 3015 120 ºC The maximum junction temperature for continuous operation is limited by package constraints. +150 ºC Positive Voltage Negative voltage 1 Electrostatic Discharge ESD rating 2 am lc s on A te G nt st il Latchup immunity , IO lv Supply voltage, VEXT, VEXT2 al id Electrical Parameters Other pins, HBM 2 RF pins, HBM 1 Temperature Ranges and Storage Conditions Maximum junction temperature, TJ Storage temperature range, Tstg -55 Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260 ºC The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/ JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for non-hermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn) 1. The AGD (Pin 54) is excluded from Latch-up immunity test at EN (Pin 39) high. AGD is a reference voltage pin and must be kept at the reference voltage level for proper chip operation. AGD must be connected to an external stabilization capacitor. Te ch ni ca 2. This integrated circuit can be damaged by ESD. We recommend that all integrated circuits are handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet the published specifications. RF integrated circuits are also more susceptible to damage due to use of smaller protection devices on the RF pins, which are needed for low capacitive load on these pins. www.austriamicrosystems.com/AS3992 Revision 1.1 8 - 53 AS3992 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics VEXT = 5.3V, typical values at 25ºC, unless otherwise noted. Note: The difference between the external supply and the regulated voltage is higher than 250mV. Table 3. Electrical Characteristics Symbol Parameter Conditions Typ IVEXT Supply current without PA driver current VEXT Consumption 80 IVEXT2 Supply Current for internal PA VEXT2 Consumption, VDD_RF = 2.5V 140 ISTBY Standby current IPD Supply current in power-down mode VAGD AGD voltage 1.5 VPOR Power on reset voltage (POR) 1.4 VVDD Regulated supply for internal circuitry and for external MCU 3.2 3.4 3.6 V VDD_RF Regulated supply for internal PA 1.9 2 2.1 V VVDD MIX1 Regulated supply for mixers, bit vext_low=L 4.5 4.8 5.1 V VVDD MIX2 Regulated supply for mixers, bit vext_low=H 3.5 3.7 3.9 V PPSSR Rejection of external supply noise on the supply regulators 26 dB PRFAUX Auxiliary output power 0 dBm PRFOUT Internal PA output power 20 dBm RRFIN RFIN input resistance 100 Ω Nominal mixer setting, PER = 0.1% -66 dBm Increased mixer gain, PER = 0.1% -76 dBm Maximum LBT sensitivity -86 dBm 10 dBm 21 dBm 3 All system disabled including supply voltage regulators mA mA mA 10 µA 1.6 1.7 V 2.0 2.5 V am lc s on A te G nt st il VSENS-NOM Input sensitivity VSENS-GAIN VSENS-LBT LBT sensitivity The difference between the external supply and the regulated voltage is higher than 250mV Units lv 2 Max al id Min Input 1dB compression point IP3 Third order intercept point PN200 VCO Phase noise @ 200 kHz -118 dBc/Hz PN400 VCO Phase noise @ 400 kHz -125 dBc/Hz 18 µs ni TREC ca 1dBCP Recovery time after modulation Nominal mixer setting Maximum LF selected ch Logic Input/Output 2 MHz VLOW Input logic low 0.2 VDD_IO VHIGH Input logic high Te Maximum CLK frequency RIO Output resistance IO0…IO7 RCL SYS Output resistance CL SYS www.austriamicrosystems.com/AS3992 VDD_IO 0.8 low_io = H for VDD_IO < 2.7V Revision 1.1 400 200 800 Ω Ω 9 - 53 AS3992 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 4. Recommended Operating Conditions Symbol Parameter Conditions Positive Supply Voltage VEXT Bit vext_low = 1 Min Typ Max Units 5.0 5.3 5.5 V 4.1 5.5 V Operating virtual junction temperature range -40 110 ºC TAMB Ambient temperature -40 110 ºC - Rth junction to exposed die pad 19 º/W Te ch ni ca am lc s on A te G nt st il lv - al id TJ www.austriamicrosystems.com/AS3992 Revision 1.1 10 - 53 AS3992 Datasheet - D e t a i l e d D e s c r i p t i o n 7 Detailed Description The RFID reader IC comprises complete analog and digital functionality for reader operation including transmitter and receiver section with complete EPC Gen2 or ISO18000-6C digital protocol support. To integrate as many components as possible, the device also comprises an onboard PLL section with integrated VCO, supply section, DAC and ADC section, and host interface section. In order to cover a wide range of possibilities, there is also Configuration registers section that configures operation of all blocks. al id For operation, the device needs to be correctly supplied via. VEXT and VEXT2 pins and enabled via. EN pin (Refer Supply on page 11 for connecting to supply and Power Modes on page 12 about operation of the EN pin). At power-up, the configuration registers are preset to a default operation mode. The preset values are described in the Configuration Registers Address Space on page 23 below each register description table. It is possible to access and change registers to choose other options. The communication between the reader and the transponder follows the reader talk first method. After power-up and configuring IC, the host system starts communication by turning on the RF field by setting option bit rf_on in the ‘Chip status control register’ (00) (see Table 13) and transmitting the first protocol command (Select in EPC Gen2). Transmitting and receiving is possible in the following two modes: am lc s on A te G nt st il 7.1 Supply lv 1. Normal Data Mode: In this mode, the TX and RX data is transferred through the FIFO register and all protocol data processing is done internally. 2. Direct Data Mode: In this mode, the data processing is done by the host system. COMN_B COMP_B COMN_A COMP_A VDD_TXPAB LDO ni VEXT Mixer On receive Te ch CBV5 ca VDD_MIX Figure 3. Mixer Supply VDD_5LFI The effective supply system of the chip decreases the influence of the supply noise and interference and thus improves de-coupling between different building blocks. A set of 3.4V regulators is used for supplying the reference block, AD and DA converters, low frequency receiver cells, the RF part, and digital part. It is possible to use the digital part supply VDD_D for supplying the external MCU with a current consumption up to 20mA. The input pin for the regulators is VEXT. The output pins for regulators are VDD_A, VDD_LF, VDD_D, VDD_RFP and VDD_B. Each of the pins require stabilizing capacitors to connected ground (2.2…10µF and 10…100nF) in parallel. Depending on quality of the capacitors, 100pF could be required. An additional 4.8V regulator is used for the input RF mixers supply. The input of this regulator is VEXT, output is VDD_MIX pin. For correct operation of the 4.8V regulator, the VEXT voltage needs to be between 5.3V and 5.5V. VDD_MIX needs de-coupling capacitors to VDD_MIX like other VDD pins. www.austriamicrosystems.com/AS3992 Revision 1.1 11 - 53 AS3992 Datasheet - D e t a i l e d D e s c r i p t i o n In case lower VEXT supply voltage is used (down to 4.1V), the vext_low option bit needs to be set to optimize the chip performance to the lower supply. The vext_low in the ‘TRcal high and misc register’ (05) bit decreases VDD_MIX voltage to 3.7V to maintain the regulators PSSR and the ir bit in the ‘RX special setting 2’ (0A) adapts mixer’s internal operating point to lower supply. Adaptation to low supply is implemented in differential mixer only. The consequence of the decreased supply is lower mixer’s input range. VDD_5LFI and VDD_TXPAB pins are supply input pins and should be connected to VDD_MIX. The internal 20dBm power amplifier has an internal regulator from 2…3.5V. The output voltage selection is done by reg2v1:0 option bits in the ‘Regulator and IO control register’ (0B) (see Table 24). al id The input pin is VEXT2 and output is VDD_RF. For optimum noise rejection performance, the input voltage at VEXT2 pin needs to be at least 0.5V above the regulated supply output. Connecting VEXT2 directly to VEXT is possible only at the expense of increasing IC’s power dissipation and decreasing the maximum operating temperature. 7.1.1 lv A separate I/O supply pin (VDD_IO) is used to supply the internal level shifters for communication interface to the host system (MCU). VDD_IO should be connected to MCU supply to ensure proper communication between the chip and MCU. In case the MCU is supplied by VDD_D from the reader IC also VDD_IO should be connected to VDD_D. Power Modes The chip has five power modes. am lc s on A te G nt st il Power Down Mode. The power down mode is activated by EN pin low (EN=L). For correct operation, the OAD2 pin should not be connected. Normal Mode. The normal mode is entered by setting EN=H. In this case all supply regulators, reference voltage and bias system, crystal oscillator, RF oscillator and PLL are enabled. After the crystal oscillator stabilizes, the CLSYS clock becomes active (default frequency is 5MHz) and the chip is ready to work with internal registers. In case the crystal oscillator is used the time that the crystal stabilizes dependent on the crystal used. Typical time is 1.5-3ms. By reading the register 0E, the firmware can check the crystal status: register 0E:x1 (osc_ok=1, pll_ok=0, rf_ok=0) shows that crystal oscillator is stable and that device is ready to operate. In case the continuously running TCXO is used, only the OSCO pin DC level needs to be set before the internal clock is ready. The same test with reg0E as above can be used. The bias and reference voltages after EN=H stabilize in 12ms typically. Then the chip is ready to switch on the RF field and start data transmission. Standby Mode. The standby mode is entered from normal mode by option bit stby=H. In the standby mode the regulators, reference voltage system, and crystal oscillator are operating in low power mode; but the PLL, transmitter output stages and receiver are switched off. All the register settings are kept while switching between standby and normal mode. The bias and reference voltages after stby=0 stabilize in 12ms typically. Then the chip is ready to switch on the RF field and start data transmission. MCU Support Mode. Power down with MCU support mode intends to support the MCU if the majority of the reader IC is in power down. This ca mode is enabled by connecting 10kΩ resistor between OAD2 pin and ground. During EN=L period, the VDD_D regulator is enabled in low power mode and the CLSYS frequency is 60kHz typically. Temporary Normal Mode. It is also possible to trigger temporary normal mode from power down mode (EN=L) by pulling shortly the OAD2 ni pin low via 10kΩ or less. After the crystal oscillator is stable and the CLSYS clock output is active, the chip waits for approximately 200µs and then changes back to the power down mode. Using this function, the superior system can wake up the reader IC and MCU that are both in the power down mode. If the MCU during 200µs period finds out that the RFID system must react, it confirms the normal mode by setting EN high. Power Mode EN OAD2 Std by Power down L - X Power down SYSCLK of 60kHz L 10k to GND X Normal power H X X X H 10k and falling edge X Te ch Table 5. AS3992 Power Modes Standby Listen mode www.austriamicrosystems.com/AS3992 L Revision 1.1 12 - 53 AS3992 Datasheet - D e t a i l e d D e s c r i p t i o n 7.2 Host Communication An 8-bit parallel interface (pins IO0 to IO7) with two control signals (CLK, IRQ) forms the main communication system. It can also be changed (by hardwiring some of the 8 I/O pins) to a serial interface. The data handling is done by a 24 byte FIFO register used in both directions, transmission and reception. For more details, refer Reader Communication Interface on page 43. al id The signal level for communication between the host system (MCU) is defined by the supply voltage connected to VDD_IO pin. Communication is possible in wide range between 1.8V and 5.5V. In case the pull-up output resistance at VDD_IO below 2.7V is to high, it can be decreased by setting option bit vdd_io_low in the ‘TRcal High and Misc register’ (05). In case the MCU is supplied from the reader IC, then both the MCU supply and VDD_IO pin need to be connected to VDD_D. CLSYS output level is defined by the VDD_IO voltage. It is also possible to configure CLSYS to open drain N-MOS output by setting the option bit open_dr in the in the ‘TRcal high and misc register’ (05), (see Table 18). This function can be used to decrease amplitude and harmonic content of the CLSYS signal and decrease the cross-talk effects that could corrupt operation of other parts of the circuit. lv 7.3 VCO and PLL The PLL section is composed of a voltage control oscillator (VCO), prescaler, main and reference divider, phase-frequency detector, charge pump, and loop filter. All building blocks excluding the loop filter are completely integrated. Operating range is 840MHz to 960MHz. VCO and External RF Source am lc s on A te G nt st il 7.3.1 Instead of the internal PLL signal, an external RF source can be used. The external source needs to be connected to EXT_IN pin and option bit eext_in in the ‘PLL A/B divider auxiliary register’ (17) (see Table 39) needs to be set high. The EXT_IN input optimum level is 0dBm with a DC level between 0V and 2V. It is also possible to use external VCO and internal PLL circuitry. In this case, the output of the external VCO (0dBm) needs to be connected to EXT_IN, option bits eext_in and epresc in the ‘PLL A/B divider auxiliary register’ (17) both need to be set high. The charge pump output pin CP needs to be connected to the external loop filter input and loop filter output to the external VCO input. This configuration is useful in case the application demands better phase noise performance than the completely integrated oscillator offers. The internal on-board VCO is completely integrated including the variable capacitor and inductor. The control input is pin VCO; input range is between 0 and 3.3V. The option bits eosc in the ‘CLSYS, analog out and CP control’ (14) (Table 36) can be used for oscillator noise and current consumption optimization. Option bit lev_vco in the ‘PLL A/B divider auxiliary register’ (17) (see Table 39) is used to optimize the internal VCO output level to other RF circuitry demands. VCO and CP pin valid range is between 0.5V and 2.9V. AS3992 has internal VCO set to a frequency range around 1800MHz, later internally divided by two for decreasing the VCO pulling effect. The tuning curve of 1800MHz VCO is divided into 16 segments to decrease VCO gain and attain lowest possible phase noise. Configuration of the 1800MHz VCO tuning range can be manual using option bits vco_r in the ‘CL_SYS, analog out and CP control’ register (14) or automatic using L-H transition on option bit auto in the same register. The device allows measurement of the VCO voltage using option bit mvco and reading out the 4 bits result of the automatic segment selection procedure, both in the ‘AGL/VCO/F_CAL status’ register (10). PLL ca 7.3.2 ni The divide by 32/33 prescaler is controlled by the main divider. The main divider ratio is defined by the ‘PLL A/B divider main register’ (16). The low ten bits in the three bytes deep register define A value and the next ten bits define B value. The A and B values define the main divider division ratio to N=B*32+A*33. The reference clock is selectable by RefFreq bits in the ‘PLL R, A/B divider main register’ (16) (see Table 38). The available values are 500 kHz, 250 kHz, 200 kHz, 100 kHz, 50 kHz and 25 kHz. Charge pump current is selectable between 150µA and 1200µA using option bits cp1:0 in the ‘CL_SYS, analog out and CP control register’ (14) (see Table 36). The cp is used to change the polarity (direction) of the charge pump output. Te ch The frequency hopping is supported by direct commands ‘Hop to main frequency’ (84) and ‘Hop to auxiliary frequency’ (85). The hopping is controlled by host system (MCU) using two configuration registers for two frequencies. Before enabling the RF field, the host system needs to configure the PLL by writing the ‘CL_SYS, analog out and PLL register’ (09) and the ‘PLL R, A/B divider main’ (16) registers. Any time during operating at the first selected frequency, the external system can configure the three bytes deep ‘PLL A/B divider auxiliary (17)’ register. Hopping to the second frequency is triggered, if direct command ‘Hop to auxiliary frequency’ is sent. Hop to the third frequency is similar: the register ‘PLL A/B divider main (16)’ can be written any time the external system has free resources and actual hop is triggered by direct command ‘Hop to main frequency’. www.austriamicrosystems.com/AS3992 Revision 1.1 13 - 53 AS3992 Datasheet - D e t a i l e d D e s c r i p t i o n 7.4 Chip Status Control In the ‘Chip status control register’ (00) (see Table 13), main functionality of the chip is defined. By setting the rf_on bit in the ‘Chip control register’ (00), the transmit and receive part are enabled. The initial RF field ramp-up is defined with the Tari1:0 option bits in the ‘Protocol control register’ (01) (see Table 14). It is also possible to slow down the initial RF field ramp by option bits trfon1:0 in the ‘Modulator control register’ (15) (see Table 37). The available values are 100µs, 200µs, and 400µs. al id The host system can check whether the field ramp-up is finished via the rf_ok bit in the ‘AGC and internal status register’ (0E) (see Table 27), which is set high when ramp-up is finished. By setting the rf_on bit low, the field will ramp-down similarly to the ramp-up transient. It is also possible to enable receiver operation by setting rec_on bit. The agc_on and agl_on bits enables the (Automatic Gain Control) AGC and (Automatic Gain Leveling) AGL functionality, dac_on enables DA converter, bit direct enables the direct data mode, and stby bit moves chip to the stand-by power mode. 7.5 Protocol Control lv In the ‘Protocol control register’ (01) (see Table 14), the main protocol parameters are selected (Tari value and RX coding for EPC Gen2 protocol). The Gen2 Protocol is configured by setting Prot bits to low. The dir_mode bit defines type of output signals in case the direct mode is used. The rx_crc_n bit high defines reception in case the user does not want to check CRC internally. In this case, the CRC is not checked but is just passed to the FIFO like other data bytes. In the EPC Gen2, this function is useful in case of truncated EPC reply where the ‘CRC’ transponder transmits is not valid CRC calculated over actual transmitted data. am lc s on A te G nt st il 7.6 Option Registers Preset After power up (EN low to high transition), the option registers are preset to values that allow default reader operation. Default transmission uses Tari 25µs, PW length is 0.5Tari, TX one length is 2 Tari, and RTcal is 133µs. Default reception uses FM0 coding with long preamble, link frequency 160kHz. Default operation is set to internal PLL with internal VCO, differential input mixers, low power output (RFOPX, RFONX), and DSB-ASK transmit modulation. 7.7 Transmitter Transmitter section comprises of protocol processing digital part, shaping, modulator and amplifier circuitry. The RF carrier is modulated with the transmit data and amplified for transmission. 7.7.1 Normal Mode In normal mode, all signal processing (protocol coding, adding preamble or frame-sync and CRC, signal shaping, and modulation) is done internally. The external system (MCU) triggers the transmission and loads the transmit data into the FIFO register. The transmission is started by sending the transmit command followed by information on the number of bytes that should be transmitted and the data. The number of bytes needs to be written in the ‘TX length’ registers and the data to the FIFO register. Both can be done by a single continuous write. The transmission actually starts when the first data byte is written into the FIFO. ca The second possibility is to start transmission with one of the direct Gen2 commands (Query, QueryRep, QueryAdjust, ACK, NAK, ReqRN). In this case, the transmission is started after receiving the command. ch ni In case the transmission data length is longer than the size of the FIFO, the host system (MCU) should initially fill the FIFO register with up to 24 bytes. The reader chip starts transmission and sends an interrupt request when only 3 bytes are left in the FIFO. When interrupt is received, the host system needs to read the ‘IRQ status register’ (0C) (see Table 25). By reading this register, the host system is notified by the cause of the interrupt and the same reading also clears the interrupt. In case the cause of the interrupt is low FIFO level and the host system did not put all data to the FIFO, the remaining data needs to be sent to FIFO, again according to the available FIFO size. In case all transmission data was already sent to the FIFO, the host system waits until the transmission runs out. At the end of the transmit operation, the external system is notified by another interrupt request with a flag in the IRQ register that signals the end of transmission. Te The two ‘TX length’ registers support in-complete bytes transmission. The high two nibbles in register 1D and the nibble composed of bits B4 ~ B7 in ‘TX length byte 2’ (1E) register (see Table 46) store the number of complete bytes that should be transmitted. Bit B0 (in register 1E) is a flag that signals the presence of additional bits that do not form a complete byte. The number of bits are stored in bits B1~B3 of the same register (1E). The protocol selection is done by the ‘Protocol control register’ (01) (see Table 14). As defined by selected protocol, the reader automatically adds all the special signals like Preamble, Frame-Sync, and CRC bytes. The data is then coded to the modulation pulse level and sent to the modulator. This means that the external system only has to load the FIFO with data and all the micro-coding is done automatically. The EPC Gen 2 protocol allows some adjustment in transmission parameters. The reader IC supports three Tari values (25µs, 12.5µs, 6.25µs) by changing Tari option bits in the ‘Protocol control register’ (01). PW length and length of the logical one in the transmission protocol can be adjusted by TxPW and TxOne option bits in the ‘TX options’ (02) register. Session that should be used in direct commands is defined in the S1and S0 bits in the same register. The back scatter link frequency is defined by TRcal in the Query command transmission. The TRcal is defined by option bits TRcal in the ‘TRcal registers’ (04, 05). www.austriamicrosystems.com/AS3992 Revision 1.1 14 - 53 AS3992 Datasheet - D e t a i l e d D e s c r i p t i o n Table 6. Register Bits Settings Protocol Setting Register Bits Individual Settings TARI Protocol control 6.25µs (00) PW length control TX option 0.27TARI (00) 0.35TARI(01) 0.44TARI(10) 0.5TARI(11) Data1 Tx TX option 1.5TARI(00) 1.66TARI(01) 1.83TARI(10) 2TARI(11) Coding Protocol control FMO(00) M2(01) M4(10) M8(11) Link frequency RX option 40 kHz (0000) 25µs 256 kHz (1001) 320 kHz (1100) 640 kHz (1111) lv 160 kHz (0110) al id 12.5µs (01) am lc s on A te G nt st il The software designer needs to take care that actual TRcal (reg. 04, 05) and RxLF (reg. 03) bits and DR bit in the transmission of the Query command are matched. Precise description is in the EPC Gen2 or ISO18000-6C protocol description. The Transmit section contains a timer. The timer is used to issue a command in a specified time window after a transponder’s response. The timer’s time is defined in ‘TX reply in slot’ (06) register. The timer is enabled by using the command ‘Delayed transmission without CRC’ (92) or ‘Delayed transmission with CRC’ (93) and is actually started at the end of the reception. Forward Link Table 7. EPC_gen2 - Tari Combinations TARI Settings 12.5µs 2.5 3 6.25µs 2.5 3 2.6667 2.2222 2.1333 1.7778 2.5 3 2.1333 1.7778 Zero and one length (RT CAL) Division Ratio TR cal (microseconds) 40 8 200.00 3.2 2.6667 64/3 133.33 2.1333 1.7778 64/3 83.33 1.3333 1.1111 64/3 66.67 256 320 640 64/3 33.33 8 200.00 ni 40 ca LF (kHz) 160 160 8 50.00 256 8 31.25 2 1.6667 1.6 1.3333 2.1333 1.7778 ch Backscatter Link 25µs 1.6 8 25.00 640 8 12.50 40 64/3 533.33 160 64/3 133.33 2.1333 1.7778 256 64/3 83.33 1.3333 1.1111 320 64/3 66.67 640 64/3 33.33 Te 320 www.austriamicrosystems.com/AS3992 Revision 1.1 1.3333 2.6667 2.2222 2.1333 1.7778 15 - 53 AS3992 Datasheet - D e t a i l e d D e s c r i p t i o n 7.7.2 Direct Mode Direct mode is applied if the user wants to use analog functions only and bypass the protocol handling supported in the reader IC. Direct Mode Using Parallel Interface. The reader IC enters the direct mode when option bit ‘direct’ is set to high in the ‘Chip status control register’ (00). As the direct mode starts immediately, all the register settings that help to configure the operation of the chip needs to be done prior to entering the direct mode. The ‘write’ command for direct mode should not be terminated by stop condition since the stop condition terminates the direct mode. This is necessary as direct mode uses four IO pins (IO2, IO3, IO5, IO6) and normal parallel or serial communication is not possible in direct mode. To terminate the direct mode, the user needs to send the stop condition. After stop condition, normal communication via. interface and access to the registers are possible. al id Direct Mode Using Serial Interface (SPI). To enter direct mode via SPI, bit direct should be set to high in the ‘Chip status control register’ For more information on transmit modulation input signal possibilities, refer to Modulator on page 16. For more information on the receive output signal possibilities, refer to TX Pre-Distortion on page 17. lv (00) and stop condition (IO4 L-to-H transition) has to be sent. As the direct mode starts immediately, all the register settings that help to configure the operation of the chip needs to be done prior to entering the direct mode. The direct mode persists till writing bit direct to low (IO4 H-to-L, SPI write to reg00). Since the direct mode uses four IO pins (IO2, IO3, IO5, IO6), it is not possible to read registers during the direct mode (IO6 which is MISO in SPI mode is used as direct mode data or subcarrier output). It is possible to write register 00 to terminate the direct mode. After direct mode termination, normal communication via SPI interface and access to the registers are possible. 1. 2. 3. 4. 5. 6. 7.7.3 am lc s on A te G nt st il The digital modulation input in direct mode is IO3. RF field is set to high level if IO3 is high, and to low level if IO3 is low. IO2 is used as RX enable. For correct operation, follow the instructions given below: Configuration registers should be defined, starting from reg01 Direct command Enable RX (97) should be sent Bit direct should be written to reg00 IO2 should be low during data transmission via IO3 IO2 should be changed to high level just before the reception is expected IO3 should be maintained high during reception Modulator For the modulation signal source, there are three possibilities: Normal data mode – Internally coded and internally shaped. Externally coded and internally shaped modulation enabled by entering direct mode. For more information on entering and terminating the direct mode, refer to Direct Mode on page 16. Externally coded and externally shaped modulation is enabled by setting option bit e_amod in the ‘Modulator control register’ (15) and entering direct mode. For more information on entering and terminating the direct mode, refer to Direct Mode on page 16. In this case, ADC and DAC pins are differential modulator input. The DC level should be 2.2V, amplitude 600mVp. It is also possible to use CD1 and CD2 pins as high and low reference for the external modulation shape circuitry. ni ca The internal modulator is capable of DSB-ASK and PR-ASK modulation. Modulation shape is controlled with a double D/A converter. The first one defines the upper (un-modulated) signal level while the second one generates the modulation transient. The level defined by the first converter is filtered by capacitors on CD1 and CD2 pins to decrease the noise level. The two levels are used as a reference for the shaping circuitry that transforms the digital modulation signal to shaped analog modulation signal. Sinusoidal and linear shapes are available. The output of the shaping circuit is interpolated and connected to the modulator input. ch The output level and modulation shape properties are controlled by the ‘Modulator control register’ (15). The level of the output signal is adjusted by option bits tx_lev. Modulation depth for ASK is adjusted by mod_dep bits. Valid values for DSB-ASK are 01 to 3F. PR-ASK modulation is selected by pr-ask bit high. In case of PR-ASK, the mod_dep bits are used to adjust the delimiter/first zero timing. Linear modulation shape is selected by lin_mod bit. The rate of the modulation transient is automatically adjusted to selected Tari and can be adjusted by ask_rate bits. For smoother transition of the modulation signal, an additional low pass filter can be used. The Filter will be enabled by e_lpf bit. The adjustment step is 1.6%, 3F gives 100% ASK modulation depth. Te PR-ASK modulation is selected by pr-ask bit high. In case of PR-ASK the mod_dep bits are used to adjust the delimiter/first zero timing in a range 9.6µs to 15.9µs. Linear modulation shape is selected by lin_mod bit. The rate of the modulation transient is automatically adjusted to selected Tari and can be adjusted by ask_rate bits. For smoother transition of the modulation signal, additional low pas filter can be used by e_lpf bit. In ASK modulation it is possible to adjust delimiter length by setting option bit ook_ask in the ‘Modulator control register’ (15). In this case, ook_ask defines 100% ask modulation and the mod_dep bits are used for delimiter length setting similar to the PR-ASK mode. Bits aux_mod and main_mod define whether the modulation signal will be connected to the auxiliary low power output or to the main PA output. In case one of the outputs are enabled by the etxp bits and appropriate aux_mod or main_mod bit is low, the output is enabled but not modulated. www.austriamicrosystems.com/AS3992 Revision 1.1 16 - 53 AS3992 Datasheet - D e t a i l e d D e s c r i p t i o n 7.7.4 Amplifier The following two outputs are available: Low power high linear output (~0dBm) can be used for driving an external amplifier. This output uses RFOPX and RFONX pins and it has nominal output impedance of 50Ω. It needs an external RF choke and de-coupling capacitor for operation. It is also possible to use differential output for driving balanced loads. The output is enabled by etx bits in the ‘Regulator an IO control’ (0B) register (see Table 24). With the help of these bits, it is also possible to adjust current capability of the output. 7.7.5 lv al id Higher output power output (~20dBm) can be used for antenna driving in case of short range applications. Internal higher power amplifier is enabled by etx bits in the ‘Regulator an IO control’ (0B) register (see Table 24). For operation it needs external RF choke and correct impedance matching for operation in 50Ω system. It is also possible to use differential output by setting etx. Bias current in the PA stage can be increased by a factor of two or four using option bits ai2x and ai4x in registers 16 and 17. The differential outputs are RFOUT_1 and RFOUT_2. Single ended output is RFOUT_1. UHF - power amplifiers (PAs) are generally sensitive to parasitics (layout, placement, routing, PCB material etc) and load conditions. We recommend to carefully investigate the specific system implementation on inherent parasitic and load variations to avoid instabilities over production. TX Pre-Distortion am lc s on A te G nt st il Transmission signal is modulated with the cosine shaped representation of the digital modulation signal. It is possible to tune the initial shape by writing the correction data in the register 13 and setting option bit use_corr in register 15. Register 13 is 252 bytes deep register accessible in continuous write mode. Bytes on positions 1 to 251 are used for pre-distortion. Byte on position 0 is not used for pre-distortion. The value on position 1 should be set to 0 and the value on position 251 should be set to 250 for smooth continuous transition. The values between positions 1 and 251 form the pre-distortion curve. In case the ramp with values 0-250 is written, the initial cosine shape is maintained. The pre-distortion data can be written and read during use_corr=0 period. 7.8 Receiver Receiver section comprises two input mixers followed by gain and filtering stages. The two receiving signals are fed to decision circuitry, bit decoder and framer where preamble is removed and CRC is checked. The clean framed data is accessible to the host system (MCU) via. 24 byte FIFO. 7.8.1 Input Mixer The two input mixer pairs are driven with 90º shifted LO signals and form IQ demodulator circuit. Using IQ architecture, the amplitude modulated input signals are demodulated in the in-phase channel (I) while the phase modulated input signals are demodulated in the quadrature phase (Q) channel. Mixed input modulation is demodulated in both receiving channels. This configuration allows reliable operation regardless the transponders. Modulation presents amplitude or phase modulation at receiver’s input and suppresses communication holes that are caused by modulation alternation. One can use differential input mixer or single ended input mixer. The differential input is formed by pins MIX_INP and MIX_INN. Input should be AC coupled. By default, differential mixers input is chosen. If the inputs are not used, then they should be unconnected. ca The mixer with single ended mixers input is selected by s_mix bit in the ‘Rx special setting register’ (0A). The single ended mixers input is the MIXS_IN pin. Input should be AC coupled. If the input is not used, then it should be unconnected. ni To optimize the receiver’s noise level and dynamic input range, the mixers have adjustable input range. Depending on expected level of the reflected power the one can adapt mixer performance by internal attenuator or increasing mixer gain. Depending on the reflectivity of the environment or antenna, the receiver’s input RF voltage can increase to a level that corrupts mixer operation. In such a case, the input range can be widened by internal input attenuator by setting option bit ir. This is valid for both differential and single ended input mixer. ch In case of low reflected power, the host system can increase the differential input mixer’s conversion gain and improve the overall sensitivity of the receiver by setting option bit ir. The drawback of this setting is decreased mixer’s input dynamic range. The single ended input mixer does not support the gain increase feature. The ir bits are in the ‘RX special setting’ (0A) register. Te In case lower supply voltage is used (low_vext=1, refer to Supply on page 11), the low_vext option bit adapts mixer’s operation point to decreased supply. The consequence of low supply voltage is up to 1dB decreased performance in terms of sensitivity and input dynamic range. The ir bits are in the ‘RX special setting2 register’ (0A) (see Table 23). www.austriamicrosystems.com/AS3992 Revision 1.1 17 - 53 AS3992 Datasheet - D e t a i l e d D e s c r i p t i o n 7.8.2 DRM RX Filter The analog filtering is composed of four filter stages: th 4 -order elliptic low-pass with notch characteristic to suppress neighboring channel (500kHz or 600kHz). The filter can be set to have -1dB point at 360kHz and 280kHz for ETSI and FCC channel spacing in DRM operation. It allows one non-DRM setting: 800kHz upper frequency for 640kHz LF. nd 2 -order high-pass Chebyshev filter with adjustable -1dB from 72kHz to 200kHz. The filter can also be switched off (only gain stage) for lower LF frequencies. nd lv al id 2 -order low-pass Chebyshev filter with -1dB frequencies at 360kHz and 280kHz for European and US channel spacing in DRM operation. It allows three non-DRM settings: - 800kHz upper frequency for 640kHz LF, - 180kHz upper frequency for 160kHz LF and, - 72kHz upper frequency for 40kHz LF. nd st 2 -order high-pass Chebyshev filter with adjustable -1dB from 72kHz to 200kHz. The filter can also be reconfigured to 1 -order with -3dB frequency at 5.5kHz or 12kHz for lower LF and FM0 coding. Filter setting is done via option bits setting in ‘RX Filter register’ 09. Available bit combinations are: Filter Setting reg09:00 reg09:07 am lc s on A te G nt st il 640kHz LF– (reg09:00…reg09:07) -3dB high-pass frequency -3dB low-pass frequency Atten. at 40kHz Atten. at 1.2MHz 220kHz 770kHz -55dB -35dB 80kHz 770kHz -18dB -35dB 320kHz LF – DRM ETSI range filter (reg09:20…reg09:27) Filter Setting -3dB high-pass frequency -3dB low-pass frequency Atten. at 40kHz Atten. at 600kHz Atten. at 1.2MHz reg09:20 200kHz 380kHz -50dB -40dB -54dB 75kHz 380kHz -18dB -40dB -54dB reg09:27 250kHz LF – DRM FCC range filter (reg09:30…reg09:37) Filter Setting -3dB high-pass frequency -3dB low-pass frequency Atten. at 40kHz Atten. at 600kHz Atten. at 1.2MHz reg09:30 200kHz 320kHz -50dB -45dB -55dB 75kHz 320kHz -18dB -45dB -55dB ca reg09:37 160kHz – (reg09:3B…reg09:3F) -3dB high-pass frequency -3dB low-pass frequency Atten. at 40kHz Atten. at 600kHz Atten. at 1.2MHz reg09:3B 110kHz 245kHz NA -52dB -56dB 56kHz 255kHz NA -52dB -56dB Filter Setting -3dB high-pass frequency -3dB low-pass frequency Atten. at 40kHz Atten. at 600kHz Atten. at 1.2MHz reg09:FF 7kHz 80kHz NA -60dB -55dB ch ni Filter Setting reg09:3F Te 40kHz LF – (reg09:FF) www.austriamicrosystems.com/AS3992 Revision 1.1 18 - 53 AS3992 Datasheet - D e t a i l e d D e s c r i p t i o n Following filter settings for different link frequency and RX coding are proposed: DRM modes: Link frequency and RX coding Proposed reg09 setting 320kHz, M4, M8 24 250kHz, M4, M8 34 40kHz, FM0, M2, M4, M8 FF 160kHz, FM0 BF 160kHz, M2, M4, M8 3F 640kHz, M4, M8 04 RX Filter Calibration lv Proposed reg09 setting am lc s on A te G nt st il 7.8.3 Link frequency and RX coding al id Other supported modes: The calibration procedure implemented in the chip helps to compensate the resistor and capacitor process and temperature variations. Calibration procedure is triggered by ‘Trigger RX filter calibration’ (88) direct command. Calibration is finished in 5ms maximum. Calibration should be triggered prior to first reception after power down and from time to time, especially in cases wherein significant temperature changes are expected. The result of calibration is seen in the ‘AGL/VCO/F_CAL/PilotFreq status register’ (10) in case option bits r10page in ‘Test setting’ register (12) are set to 2. Typical calibration result values are 88. The calibrated values can be changed automatically by using ‘Decrease RX filter calibration data’ (89) and ‘Increase RX filter calibration data’ (8A) direct command, together with f_cal_hp_cgh option bit in ‘Test setting’ register (12). Note: hp_cal affects the high pass part of the filter characteristic and lp_cal affects the low pass part of the filter characteristic, both in 4% steps. 7.8.4 Fast AC Coupling The internal (patent pending) feedback AC coupling system prior to start of transmit modulation stores the DC operating points, and after data transmission progressively adjusts the high pass time constant to allow very fast settling time prior to beginning of reception. Such a system is needed to accommodate the short TX to RX time used at the highest bit rates in the EPC Gen 2 protocol. It is possible to additionally speed up the first AC coupling time constant by setting option bit lf4_ac_su in the ‘Test register’ (12). 7.8.5 RX Gain ca Gain in the receiving chain can be adjusted to optimize the signal to noise and interference ratio. There are three ways of adjusting: manual adjustment, AGC, and AGL. ni Manual Adjustment is gain adjustable by setting option bits gain in the ‘RX special setting 2 register’ (0A) (see Table 23) and ‘TRcal high and misc register’ (05) (see Table 18). The low three bits decrease digitizer hysteresis by 3dB (7 steps), the high two bits change the amplifier gain by 3dB (3 steps). Gain direction (increase or decrease) is defined by gd. ch AGC is automatic gain control. It can be enabled by option bit agc_on in the ‘Chip status control’ register (00) (see Table 13). AGC comprises of a system that decreases gain during the first periods of the incoming preamble. Gain is decreased equally for both channels to a level that results the stronger signal is just in the range. In this case, the ratio between I and Q channel amplitude is maintained. The resulted status of the AGC can be seen in the ‘AGC and internal status’ register (0E) (see Table 27). Te AGL is another possibility for adjusting the gain. AGL bit needs to be set high at the moment when there is no actual transponder response at receiver input. It automatically decreases gain for each channel to the level that is just below the noise and interference level. The gain of the two channels is independent. The resulted status of the AGL for both channels can be seen in the ‘AGL status ‘register (10) (see Table 29). Difference between the AGC and AGL functionality is that AGC is done each time at beginning of the receive telegram; while AGL is done only at the moment when agl_on bit is set high, stored, and is valid till the agl_on bit is set low. The two receiving signals are digitized and evaluated. The decision circuit selects the in-phase signal or quadrature signal for further processing, whichever presents the better received signal. Which of the signals is chosen can be seen in the in_select bit in the ‘AGC and internal status’ register (0E). Bit is valid from preamble end till start of the next transmission. www.austriamicrosystems.com/AS3992 Revision 1.1 19 - 53 AS3992 Datasheet - D e t a i l e d D e s c r i p t i o n 7.8.6 Received Signal Strength Indicator (RSSI) The receiver section includes a double RSSI meter. The RSSI meters are connected to the outputs of both receiver chains to measure in real time the peak to peak demodulated voltage of each receiving channel during the reception of each transponder response (from the end of RX wait timer till the end of reception). The peak value of each RSSI meter is stored and presented in the ‘RSSI levels’ (0F) register (see Table 28). The RSSI register is valid till start of next transmission. 7.8.7 Reflected RF Level Indicator al id The receiver also comprises the input RF level indicator. It is used for diagnostic of circuitry or environment difficulties. The reflection of poor antenna, reflection of reflective antenna’s environment, or directional device leakage (circulator) can cause that input mixers are overdriven with the transmitting signal. Normal Mode am lc s on A te G nt st il 7.8.8 lv Overloading of the input mixers by reflected transmitting carrier can be notified by the host system (MCU) by measuring the RF input level via internal AD converter. The reflected carrier that is seen on the two mixers input is down converted to zero frequency. The two DC levels on the mixers outputs are proportional to the input RF level and dependant on the input phase and can be used for measuring the level of the reflected carrier. They can be connected to the on-board ADC converter by setting option bits msel in the ‘Test setting and measurement selection register’ (11). The appropriate settings for connecting two mixers’ DC levels to AD converter are 001 and 002. Conversion is started by direct command ‘Trigger ADC conversion’ (87). Result in register 19 is valid 20µs after triggering. In the normal mode, the digitized output after decision circuit is connected to the input of the digital portion of the receiver. This input signal is the sub-carrier coded signal, which is a digital representation of modulation signal on the RF carrier. The digital part of the receiver consists of two sections, which partly overlap. The first section comprises the bit decoders for the various protocols. The bit decoders convert the sub-carrier coded signal to a bit stream and the data’s clock according to the protocol defined by option bits Rx-cod in the ‘Protocol control’ (01) register (see Table 14) and Rx_LF option bits in the ‘RX options’ (03) register. Preamble is truncated. The decoder logic is designed for maximum error tolerance. This enables the decoders to successfully decode even partly corrupted sub-carrier signals due to noise or interference. The receiver also supports transfer of incomplete bytes. The number of valid bits in the last received byte is reported by Bb bits in the ‘TX length byte 2’ (1E) register (see Table 46). The second section comprises the framing logic for the protocols supported by the bit decoder section. In the framing section, the serial bit stream data is formatted in bytes. The preamble, FrameSync, and CRC bytes are checked and removed. The result is ‘clean’ data, which is sent to the 24-byte FIFO register where it can be read out by the host system (MCU). In the EPC Gen2 protocol, the decoder supports long RX preamble (TRext=1) for FM0, and all Miller coded signals and short RX preamble (Trext=0) for Miller4 and Miller8 coded signals. In the EPC Gen2 protocol, the timing between transponders response and the subsequent reader’s command is quite short. To relieve the host system (MCU) of reading RN16 (or handle) out of the FIFO and then writing it back into the FIFO, there is a special register for storing last received RN16 during the Query, QueryRep, QueryAdjust or RegRN commands. The last stored RN16 is automatically used in ACK command. The start of the receive operation (successfully received preamble) sets the flags in the ‘IRQ and status’ register. The end of the receive operation is signalled to the host system (MCU) by sending an interrupt request (pin IRQ). If the receive data packet is longer than 8 bytes, an th ca interrupt is sent to the MCU when the 18 byte is received to signal that the data should be removed from the FIFO. In case an error in data format or in CRC is detected, the external system is made aware of the error by an interrupt request pulse. The nature of the interrupt request pulse is available in the ‘IRQ and status register’ (0C) (see Table 25). ni The receive part comprises two timers. ch The RX wait time timer setting is controlled by the value in the ‘RX wait time’ (08) (see Table 21). This timer defines the time after the end of transmit operation in which the receive decoders are not active (held in reset state). This prevents any incorrect detection that could be caused as a result of transients that are caused by transmit operation or transients that are caused by noise or interference. The value of the ‘RX wait time register’ defines this time with increments of 6.4µs. This register is preset at every write to the ‘Protocol control’ register (01) according to the minimum tag response time defined by default register definition. Te The RX no response timer setting is controlled by the ‘RX no response wait time’ (07) (see Table 20). This timer measures the time from the start of slot in the anti-collision sequence until the start of tag response. If there is no tag response in the defined time, an interrupt request is sent and a flag is set in ‘IRQ status control’ register. This enables the external controller to be aware of empty slots. The wait time is stored in the register with increments of 25.6µs. This register is automatically preset for every new protocol selection. www.austriamicrosystems.com/AS3992 Revision 1.1 20 - 53 AS3992 Datasheet - D e t a i l e d D e s c r i p t i o n ‘RX length register’ (1A, 1B) defines the number of bits that the receiver should receive. The number of bits is taken into account only in case the value is different than 0 00, otherwise receiver stops on pause at the end of reception. Since in noisy environment, the end of transponders transmission is not precisely defined using the RX length registers improves the probability for successful receiving. For direct commands 98 to 9C, the RX length is internally set to 16 to receive RN16. For direct command 9F, the RX length is internally set to 32 to receive RN16 and CRC. For other commands when the host system knows the expected RX length, it is recommended to write it in the RX length register. The only case when RX length is not known in advance is reception of the PC+EPC. al id AS3992 handles the issue mentioned above by using special RX mode. The idea is that reader chip generates an additional interrupt after two bytes (PC part of the PC+EPC field) are received. MCU reads out the two bytes that define the length of the on going telegram and writes it in the RX length register. To use IRQ after the two received bytes, the fifo_dir_irq2 bit in the reg1A should be set and non-zero length (typical PC+EPC length) should be written in the 1B register before start of reception. The fifo_dir_irq2 performs the following changes in the behavior of the logic: lv All received bytes are directly transferred to FIFO. Normally the receiving data is pipelined, causing that the two CRC bytes are not seen in the FIFO. If dir_fifo=1, then all bytes including CRC are seen in the FIFO. am lc s on A te G nt st il Additional interrupt is generated after two bytes are received. In the IRQ status register, the ‘header/2byte’ (B3) bit is set. If the reception is still in progress, IRQ status value is 48. At this moment, the MCU needs to read out the first two bytes (PC part of the PC+EPC field) and set RX length accordingly. The fifo_dir_irq2 bit should be maintained high. At the end of reception, another IRQ is generated. Additional IRQ status bit ‘Irq_err3 – preamble/end’ (B1) is set. IRQ status is 42 if the intermediate 2nd_byte interrupt was read out and cleared, or 4A if the reception was over before the intermediate interrupt was read out and cleared. 7.8.9 Direct Mode The direct mode is applied in case the user wants to use analog functions only and bypass the protocol handling supported in the reader IC. (Refer to Transmitter on page 14 for information on entering direct mode.) Regarding receiving tag data in direct data mode, there are three possibilities depending on setting of option bits: Internally decoded bit stream and bit clock according to the protocol defined by option bits Rx-cod in the ‘Protocol control’ (01) register and Rx_LF option bits in the ‘RX options’ (03) register is enabled by low level of option bit dir_mode in the ‘Protocol control’ (01) register. Outputs are IO5 and IO6. Digitized sub-carrier signals of both receiving channels are enabled by high level of option bit dir_mode in the ‘Protocol control’ (01) register. Outputs are IO5 and IO6. Analog sub-carrier signals of both receiving channels are enabled by high level of option bit e_anasupc in the ‘CLSYS, analog out, and CP control’ (14) register. Outputs are OAD and OAD2. ca In case MCU support mode is used, the OAD2 resistor to ground (the one that is needed for entering this mode) can be removed during reception not to load the analog OAD2 output. Resistor is necessary only during EN=L, EN L-to-H transition and EN H-to-L transition. It is not necessary during reception. 7.8.10 Normal Mode With Mixer DC Level Output and Enable RX Output Available Te ch ni One of the possibilities for achieving low reflected TX power is active tuning of the antenna or the directivity device. For correct tuning, the data on the amplitude and phase of the incoming reflected power is available in the output DC level of the two mixers. The two voltages are available on the OAD and OAD2 inputs. For correct operation, the tuning circuitry needs to know when receiver is enabled and the two mixer output DC levels are correct. This signal is available on ADC in case ‘Test setting’ low register (12l) is set to 1A, or on DAC pin in case ‘Test setting’ low register (12l) is set to 1B. Tuning can be done on CW and also during telegram reception. In the first case, the receiver is enabled by ‘Enable RX’ direct command. In the second case, the receiver is automatically enabled after data transmission. www.austriamicrosystems.com/AS3992 Revision 1.1 21 - 53 AS3992 Datasheet - D e t a i l e d D e s c r i p t i o n 7.9 ADC / DAC ADC MCU Power detector Interface am lc s on A te G nt st il lv RSSI al id Figure 4. ADC / DAC Section AS3992 7.9.1 DA Converter DA converter intends to support the TX power control function in cases that the external PA supports this function (typically named ramp input or gain control input). The output level is stored in the DAC control register (18) (see Table 40) and the output pin is DAC. Output range is 0V to two times AGD voltage (3.2V). Input code 00 gives output level equal to AGD. The 7 LSB gives absolute output level and the MSB Bit is the sign. DA converter is enabled by dac_on bit in the ‘Chip status control’ register (00). Output resistance on DAC pin is 1kΩ typically. For applications that require current, a voltage follower needs to be included. 7.9.2 AD Converter ni ca AD converter intends to support the external power detector placed before or after the circulator to measure actual output power. The analog voltage from the power detector is connected to the ADC pin. AD conversion is triggered by the ‘Trigger AD conversion’ (87) command, and the resulted value is available in the ‘ADC readout register’ (19) (see Table 41). AD converter can also be used for measuring the mixers DC output levels. The source for the conversion is selected by msel bits in the ‘Test setting 1 and measurement selection’ register (11) (see Table 33). Input range is 0V to two times AGD voltage (3.2V). Input level equal to AGD gives output code 00. The 7 LSB bits give absolute output level, the MSB bit is a sign, H means positive, L means negative value. Result is valid 20µs after triggering. AD converter can be used to measure VEXT voltage, and according to the result, the MCU can decide to use adaptation to low supply voltage (low_vext=1 and ir=1 option bits) or inform the superior system that supply needs to be fixed or just disable transmission. The value in ‘ADC readout register’ (19) is calculated accordingly to the equation: ADCreg = [(VEXT-1.6)*0.8-1.6] / 0.0126 (EQ 1) ch Where: ADCreg is the value, sign should be considered as above VEXT is in volts Te 7.10 Reference Oscillator Reference frequency of 20MHz is needed for the chip. It is possible to use quartz crystal or external reference source (TCXO). In case the crystal is used it should be connected between OSCI and OSCO pin with appropriate load capacitors between each oscillating pin and ground. Load capacitance 15-20pF is proposed. Maximum series resistance in resonance is 30Ω. In case external reference source is used, it should be connected to OSCO pin. The signal should be sinusoidal shape, 1Vpp, DC level 1.6V or AC coupled. www.austriamicrosystems.com/AS3992 Revision 1.1 22 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8 Application Information Figure 5. Application Example LAN Interface device microcontroller 8 I/O IRQ CLK CLSYS VCC Tx Optional PA Rx am lc s on A te G nt st il UHF Reader AS3992 lv USB al id Display Optional VCO 8.1 Configuration Registers Address Space At power up, the configuration registers are preset to a value that allows default operation. The preset values are given after each register description table. Table 8. Main Control Registers Adr (hex) 00 01 Register Length Chip status control R/W 1 Protocol control R/W 1 Adr (hex) ca Table 9. Protocol Sub-setting Registers Register Length TX options Gen2 R/W 1 RX options Gen2 R/W 1 04 TRcal L register Gen2 R/W 1 05 TRcal H and misc R/W 1 06 TX reply in slot R/W 1 07 RX no response wait R/W 1 08 RX wait time R/W 1 09 RX filter R/W 1 0A RX special setting2 R/W 1 0B Regulator and IO control R/W 1 13 TX pre-distortion (deep register) R/W 14 CL_SYS, analog out, and CP R/W 3 15 Modulator control (3 bytes deep) R/W 3 02 Te ch ni 03 www.austriamicrosystems.com/AS3992 Revision 1.1 23 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Table 9. Protocol Sub-setting Registers Adr (hex) Register Length PLL main (3 bytes deep) R/W 3 17 PLL auxiliary (3 bytes deep) R/W 3 18 DAC register R/W 1 19 ADC register R 1 Table 10. Status Registers Register Length 0C IRQ and status 0D Interrupt mask register 0E AGC and internal status register R 0F RSSI levels R 10 AGL / VCO / F_CAL / PilotFreq status register R Adr (hex) 11 12 Table 12. FIFO Registers Adr (hex) 1A 1B 1C 1D 1E 1 1 1 1 Register Length Measurement selection R/W 1 Test setting R/W 1 Register Length RX length R/W 1 RX length R/W 1 FIFO status R 1 TX length byte1 R/W 1 TX length byte2 R for RX W for TX 1 FIFO I/O register R/W 1 Te ch ni ca 1F R/W 1 am lc s on A te G nt st il Table 11. Test Registers R lv Adr (hex) al id 16 www.austriamicrosystems.com/AS3992 Revision 1.1 24 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.2 Main Configuration Registers Chip Status Control (00) – Controls of the operation mode Table 13. Chip Status Control (00) 1 Signal Name Comments B7 stby Stand-by power mode 0: normal mode 1: stby power mode B6 direct Direct data mode External modulation control for transmission and IQ or bit stream output for reception B5 dac_on DA converter enable 0: DAC off 1: DAC on B3 agl_on AGL mode enable 0: AGL off 1: AGL on B2 agc_on AGC select 0: AGC off 1: AGC on rec_on Receiver enable Receiver is enabled TX and RX enable TX RF field and receiver are enabled am lc s on A te G nt st il B4 lv Function al id Bit B1 B0 rf_on 1. Reset to 00 at EN=L or POR=H Protocol Control (01) – Controls the RFID protocol selection, operation of Tari10 bits is defined with Prot10 bits. Table 14. Protocol Control (01) 1 Bit Signal Name B7 rx_crc_n Receiving without CRC 0: RX CRC (generate interrupt) 1: No RX CRC (interrupt and no CRC truncation) dir_mode Direct mode type 0: Output is bit stream and clock from the selected decoder 1: Output is sub-carrier data. Protocol selection 00: EPC Gen2 / ISO18000-6C: Tari 6.26/12.5/25us, FM0, M2, M4, M8 01: 10: ISO18000-6A/B:, A/B FM0 decoder in direct mode B6 B5 Prot1 Prot0 ca B4 ch B1 RX_cod0 B0 RX decoding select (Gen2) Tari (Gen2) 00: Tari=6.25µs (Gen2, ISO-C) 01: Tari=12.5µs (Gen2, ISO-C) 10: Tari=25µs (Gen2, ISO-C) Tari1 Tari0 Comments 00: FM0 01: Miller 2 10: Miller 4 11: Miller 8 RX_cod1 ni B3 B2 Function Te 1. Preset to 06 (Gen2, Miller2, Tari=25µs) at EN=L or POR=H www.austriamicrosystems.com/AS3992 Revision 1.1 25 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.3 Control Registers - Low Level Configuration Registers TX Options (02) – Gen2 1 B7 TxPw1 B6 TxPw0 B5 TxOne1 B4 TxOne0 B3 Tx-CRC B2 Force_TRcal B1 S1 B0 Function Comments PW length control 00: 0.27Tari 01: 0.35Tari 10: 0.44Tari 11: 0.50Tari TX one length control 00: 1.50Tari 01: 1.66Tari 10: 1.83Tari 11: 2.00Tari TX CRC type 0: CRC-16 1: CRC-5 al id Signal Name TRcal period in normal transmission Normally TRcal is automatically transmitted when Query (98) direct command is issued, according to EPC Gen2 and ISO18000-6C. In case Force_TRcal=1 the TRcal period is transmitted also in normal data transmission (direct commands 90, 91) Session bits Used for Gen 2 direct commands am lc s on A te G nt st il Bit lv Table 15. TX Options (02) S0 1. Preset at POR=H or EN=L Gen2: F0 (TxPW=0.5 Tari, TxOne=2 Tari) RX Options (03) - Gen 2 Table 16. RX Options (03) 1 Bit Signal Name B7 Rx_LF3 Rx_LF2 B5 Rx_LF1 B4 ni pil_meas_sh ch B2 Link frequency selection Shorter pilot measurement Shorten pilot measurement interval to 1/2, 1/4, 1/8. Available intervals are 80, 40, 20, 10, 5 LF periods. RX preamble length 0: Short preamble 1: Long preamble Short preamble is supported for Miller 4 and Miller 8 coding. don’t care Set to 0 Rx_LF0 B3 B1 TRext Te B0 Comments 0000: 40kHz 0110: 160kHz 1001: 256kHz 1100: 320kHz 1111: 640kHz ca B6 Function 1. Preset at POR=H or EN=L Gen2: 60 (160kHz) www.austriamicrosystems.com/AS3992 Revision 1.1 26 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n TRcal Low Register (04) – Gen2 1 Signal Name B7 TRcal7 B6 TRcal6 B5 TRcal5 B4 TRcal4 B3 TRcal3 B2 TRcal2 B1 TRcal1 B0 TRcal0 Function Comments Gen2: 17.2µs…225µs al id Bit TRcal range 0.1µs…409µs (1…4096 steps) step size 0.1µs worst case relative resolution (0.1µs/ 17.2µs=0.6%) am lc s on A te G nt st il 1. Preset at POR=H or EN=L Gen2: 35 (1333 steps: 133.3µs, DR=64/3(bit DR=1) => LF=160µs) lv Table 17. TRcal Low Register (04) TRcal High and Miscellaneous Register (05) – Gen 2 Table 18. TRcal High and Miscellaneous Register (05) 1 Bit Signal Name B7 gain RX gain direction 0: Decrease 1: Increase gain by option bits gain in reg0A vext_low Decrease VDD_MIX 0: 4.8V 1: 3.7V, also differential mixer adaptation to low supply Supports low peripheral communication voltage When high decreases output resistance of logic outputs. Should be set high when VDD_IO voltage is below 2.7V. Open drain N-MOS outputs Valid for CLSYS, OAD, OAD2 pins B6 B5 vdd_io_low B4 open_dr B3 Function Comments TRcal11 B2 TRcal10 (see Table 17 on page 27) TRcal9 ca B1 B0 TRcal8 Te ch ni 1. Preset at POR=H or EN=L Gen2: 05 www.austriamicrosystems.com/AS3992 Revision 1.1 27 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Delayed Transmission Wait Time (06) Bit Signal Name B7 Txdel7 B6 Txdel6 B5 Txdel5 B4 Txdel4 B3 Txdel3 B2 Txdel2 B1 Txdel1 B0 Txdel0 1 Function Delayed transmission wait time Comments TX reply range 6.4µs to 1632µs (1…255), Start at end of RX. 00: Delayed transmission is disabled. al id Table 19. Delayed Transmission Wait Time (06) lv Gen2: T2=4.68µs…500µs after end of RX, Select T4>31.2…150µs after end of TX am lc s on A te G nt st il 1. Preset at POR=H or EN=L Gen2: 00 RX No Response Wait Time (07) – Defines the time when ‘No Response’ interrupt is sent. Table 20. RX No Response Wait Time (07) 1 Bit Signal Name B7 NoResp7 B6 Function Defines the time when ‘no response’ interrupt is sent. It starts from the end of TX. NoResp6 B5 NoResp5 B4 NoResp4 B3 NoResp3 B2 No response wait time RX no response wait range is 25.6µs to 6528µs (1…255), Step size 25.6µs Interrupt is sent in case the time runs out before 6-10 periods of link frequency is detected. NoResp2 B1 Comments NoResp1 B0 Gen2: T1max=23.6µs…262µs NoResp0 ca 1. Preset at POR=H or EN=L Gen2: 07 (179.2µs > 54.25µs…84.5µs + 10 periods – LF:160kHz) RX Wait Time (08) – Defines the time after TX when the RX input is disregarded. Bit Signal Name ch B7 1 ni Table 21. RX Wait Time (08) Rxw7 B6 Rxw6 B5 Rxw5 B4 Rxw4 B3 Rxw3 B2 Rxw2 B1 Rxw1 B0 Rxw0 Te Function Comments Defines the time during which the RX input is ignored. It starts from the end of TX. RX wait time RX wait range is 6.4µs to 1632µs (1…255), Step size 6.4µs, 00: receiver enabled immediately after TX. ISO 1800-6C(Gen2) Gen2: T1min=11.28µs…262us, ISO 1800 - 6A: 150…1150µs ISO 1800 - 6B: 85…460µs 1. Preset at POR=H or EN=L Gen2: 07(44.8µs < 54.25µs…84.5µs – LF:160kHz) www.austriamicrosystems.com/AS3992 Revision 1.1 28 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n RX Filter (09) 1 Bit Signal Name B7 byp160 Bypass for 160kHz LF B6 byp40 Bypass for 40kHz LF B5 lp3 B4 lp2 B3 lp1 B2 hp3 B1 hp2 B0 hp1 RX Special Setting2 (0A) Table 23. RX Special Setting2 (0A) Signal Name B7 gain lv High pass setting Function Comments RX gain setting Gain change, 3 steps by 3dB, Increase/decrease defined by gain option bit in reg05 Digitizer hysteresis setting Hysteresis increase, 7 steps by 3dB s_mix Mixer input selection 0: differential input mixer 1: single ended input mixer ir Differential mixer gain increase 10dB gain increase ir Mixer input attenuation 8dB attenuation using differential mixer, 5dB attenuation using single ended input mixer gain B5 see DRM RX Filter on page 18 1 Bit B6 Low pass setting Comments am lc s on A te G nt st il 1. Preset at POR=H or EN=L Gen 2:41 Function al id Table 22. RX Filter (09) gain B4 gain B3 gain B2 B1 ca B0 Te ch ni 1. Preset to 01 (Max gain, mixer range) at POR=H or EN=L www.austriamicrosystems.com/AS3992 Revision 1.1 29 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Regulator and I/O Control (0B) Table 24. Regulator and I/O Control (0B) 1 Bit Signal Name B7 reg B6 reg2v etx B3 etx etx PA2 enable 0: RFOUT1 only 1: differential RFOUT1 and RFOUT2 Enable for main PA and current for main PA pre-driver 00: disabled 01:7mA 10: 14mA 11: 22mA 00: disabled 01:7mA 10: 14mA 11: 22mA am lc s on A te G nt st il B1 00: 2V 01: 2.5V 10: 3V 11: 3.5V al id B4 Internal power amplifier regulator setting lv reg2v etx Comments for VDD_RF current source B5 B2 Function B0 Enable for low power output and current for auxiliary driver low power output etx 1. Preset to 02 (Medium driver current) at POR=H or EN=L 8.4 Status Registers IRQ and status register (0C) displays the cause of IRQ and TX / RX status. Table 25. IRQ and Status Register (0C) 1 Bit Signal Name B7 Irq_tx IRQ set due to end of TX Signals the TX is in progress. Interrupt when TX is finished. Irg_srx IRQ set due to RX start Signals the RX was received and RX is in progress. Interrupt when RX is finished. Irq_fifo Signals the FIFO is 3/4910MHz) DAC Control Register (18) Bit Signal Name Function Comments dac ch B7 1 ni Table 40. DAC Control Register (18) dac B5 dac B4 dac B3 dac B2 dac B1 dac B0 dac Te B6 DAC control value 1. Default: reset to 00 at POR=H and EN=L www.austriamicrosystems.com/AS3992 Revision 1.1 37 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n ADC Readout Register (19) Table 41. ADC Readout Register (19) B7 adc B6 adc B5 adc B4 adc B3 adc B2 adc B1 adc B0 adc Function Comments ADC readout Via ADC the two mixers output DC levels can be measured showing the reflectivity of the antenna or the environment. Also DC level on ADC pin can be measured. The later case can be used for checking the RF output power via external power detector. The measurement is selected using msel bits. The measurement is triggered by the ‘Trigger ADC conversion’ command (87). Result is valid 20µs after triggering. Table 42. RX Length 1 (1A) 1 Bit am lc s on A te G nt st il 8.7 RX Length Registers RX Length 1 (1A) Signal Name B7 al id Signal Name lv Bit rx_crc_n2 Function Receiving without CRC Comments Temporary receiving without CRC. Valid for a single reception. All bytes including CRC are transferred to FIFO, B6 fifo_dir_irq2 B5 B4 B3 B2 B1 Direct FIFO and 2 byte IRQ rxl B0 nd rxl nd irq_header is changed to irq_2 byte, irq_err3 is changed to irq_RX_finished. For PC+EPC reception RX length RX Length 2 (1B) ca 1. Default: reset to 00 at POR=H, EN=L, at the end of reception. Bit Signal Name ch B7 1 ni Table 43. RX Length 2 (1B) Comments rxl B6 rxl B5 rxl B4 rxl B3 rxl B2 rxl B1 rxl B0 rxl Te Function RX length 1. Default: reset to 00 at POR=H, EN=L, at the end of reception. www.austriamicrosystems.com/AS3992 Revision 1.1 38 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.8 FIFO Control Registers FIFO status – adr 1C hex number of received bytes and FIFO flags. 1 Table 44. FIFO Status- adr 1C hex Signal Name Function Comments B7 Fhil High FIFO level Indicates that 18 bytes are in FIFO already (for RX) B6 Flol Low FIFO level Indicates that only 6 bytes are left in FIFO (for TX) B5 Fove FIFO overflow error Several data is written to FIFO B4 Fb4 FIFO bytes fb[4] B3 Fb3 FIFO bytes fb[3] B2 Fb2 FIFO bytes fb[2] B1 Fb1 FIFO bytes fb[1] B0 Fb0 FIFO bytes fb[0] al id Bit am lc s on A te G nt st il lv How many bytes loaded in FIFO were not read out yet 1. Default: reset to 00 at POR=H and EN=L TX length byte1 – adr 1D hex high 2 nibbles of complete bytes, which will be transferred through FIFO. 1 Table 45. TX Length Byte1 - adr 1D hex Bit Signal Name B7 Txl11 Number of complete byte– bn[11] Txl10 Number of complete byte– bn[10] Txl9 Number of complete byte– bn[9] Txl8 Number of complete byte– bn[8] Txl7 Number of complete byte– bn[7] Txl6 Number of complete byte– bn[6] Txl5 Number of complete byte– bn[5] Txl4 Number of complete byte– bn[4] B6 B5 B4 B3 B2 B1 B0 Function Comments High nibble of complete bytes to be transmitted or received. Middle nibble of complete bytes to be transmitted or received. Te ch ni ca 1. Default: reset to 00 at POR=H and EN=L. It is also automatically reset at TX EOF www.austriamicrosystems.com/AS3992 Revision 1.1 39 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n TX Length Byte2 – adr 1E hex low nibbles of complete bytes, which will be transferred through FIFO and information if there is broken byte and how many bits from it should be transferred. 1 Table 46. TX Length Byte2 - adr 1E hex Function B7 Txl3 Number of complete byte– bn[3] B6 Txl2 Number of complete byte– bn[2] B5 Txl1 Number of complete byte– bn[1] B4 Txl0 Number of complete byte– bn[0] B3 Bb2 Broken byte number of bits bb[2] B2 Bb1 Broken byte number of bits bb[1] B1 Bb0 Broken byte number of bits bb[0] B0 Bbf Broken byte flag Comments Low nibble of complete bytes to be transmitted or received. al id Signal Name Number of bits in the last (broken) byte to be transmitted or number of bits that is valid in the last (broken) received byte. It is taken into account only when broken byte flag is set. lv Bit am lc s on A te G nt st il 1: indicates that last byte is not complete 8 bit wide. 1. Default: reset to 00 at pro=H and EN=L Note: For transmission, the register 1E is write only. The written value is used for the transmission but can not be read out by the micro controller. For reception bits B0 to B4 are read only. The value read out is the number of valid bits in the last received byte. Bits B0 to B4 are updated at the end of the last successful reception. In case the last received byte is not complete, the valid bits are on the LSB side. FIFO I/O Register – adr 1F hex 24 bytes FIFO register filled and read in cyclical way. 8.9 Direct Commands Table 47 lists out the direct commands that are supported in the UHF reader IC. Table 47. Command Codes Cmd (hex) 1 Command Idle 84 Hop to main frequency 85 Hop to auxiliary frequency 87 Trigger AD conversion 88 Trigger RX filter calibration 89 Decrease RX filter calibration data 8A Increase RX filter calibration data Reset FIFO Transmission with CRC ch 90 ni 8F ca 80 Comments Transmission with CRC expecting header bit (Gen2 RX) 92 Transmission without CRC 93 Delayed transmission without CRC (not used in EPC Gen2) 94 Delayed transmission with CRC (not used in EPC Gen2) 96 Block RX 97 Enable RX 98 Query (=TX with TX CRC5, no RX CRC) 99 QueryRep (=TX no TX CRC, no RX CRC) Te 91 www.austriamicrosystems.com/AS3992 Revision 1.1 40 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Table 47. Command Codes Cmd (hex) 1 Command Comments QueryAdjustUp (=TX no TX CRC, no RX CRC) 9B QueryAdjustNic (=TX no TX CRC, no RX CRC) 9C QueryAdjustDown (=TX no TX CRC, no RX CRC) 9D ACK (repeat) RN 16 9E NAK 9F ReqRN al id 9A 8.9.1 lv 1. Value in this column includes the command bit (MSB) high. Idle (80) Command Hop to Main Frequency (84) am lc s on A te G nt st il 8.9.2 This command forces the PLL to use frequency setting in ‘PLL A/B divider main register’ (see Table 38). This is also the default setting. 8.9.3 Hop to Auxiliary Frequency (85) This command forces the PLL to use frequency setting in ‘PLL A/B divider auxiliary register’ (see Table 39). 8.9.4 Trigger AD Conversion (87) This command triggers the analog to digital conversion with the internal 8-bit AD converter. Conversion result is available in the ‘ADC readout register’ (19) (see Table 41). The source for the AD conversion is defined with msel bits in the ‘Test setting 1 register’ (11) (see Table 33). With this command it is possible to measure the both mixers output DC levels (msel=001 and 010) and DC value on the pin ADC (msel=011). The first two possibilities are used for diagnostic purposes. Reflectivity of the antenna or antenna environment, or leakage of the directional device causes reflection of the transmitted carrier towards receivers input. The mixers DC levels are defined with the amplitude and phase of the incoming carrier. The ADC pin is direct input to the AD converter. The input can be used to connect the external power detector for measuring the actual transmitted power. Other msel combinations are used for test purposes. 8.9.5 Trigger RX Filter Calibration (88) The command triggers the RX filter calibration cycle. The calibration cycle is finished after t.b.d. Result is available in reg10. 8.9.6 Decrease RX Filter Calibration Data (89) Increase RX Filter Calibration Data (8A) ni 8.9.7 ca After RX filter calibration (88), the host system (MCU) can decrease the automatically selected time constant by sending direct command 89 to fine adjust the filters. The option bit f_cal_hp_chg in reg12 defines whether the calibration data change triggered by command 89 will affect the lp or hp part of the filter. Sending one command 89 decreases calibration data for one step. There are 16 steps available, step size is 4%. Result is available in reg10. ch After RX filter calibration (8A), the host system (MCU) can increase the automatically selected time constant by sending direct command 8A to fine adjust the filters. The option bit f_cal_hp_chg in reg12 defines whether the calibration data change triggered by command 89 will affect the lp or hp part of the filter. Sending one command 8A increases calibration data for one step. There are 16 steps available, step size is 4%. Result is available in reg10. Reset FIFO (8F) Te 8.9.8 The reset command clears the FIFO pointers and all IRQ flags. It also clears the register storing the error (collision) location. www.austriamicrosystems.com/AS3992 Revision 1.1 41 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.9.9 Transmission With CRC (90) The transmission commands are used to transmit data from the reader to the transponders. First the registers ‘Tx length’ (1D, 1E) need to be set with the number of bytes for transmission, including data on broken bytes. Then transmission data can be loaded to FIFO register (1F). Transmission starts when the third byte is written in the FIFO. Transmission of short messages (less than three bytes) is started when complete data is in the FIFO. When the command is received the reader starts transmitting. CRC-16 is included in the transmitted sequence. In this mode the micro controller has control on precise timing. al id Optimal way to load transmission data is use of Continuous Write mode, starting from address 1D. Example 90 3D 00 30 AA BB CC operates as follows: Transmit with CRC, write 00 to 1D and 30 to 1E (three bytes are going to be transmitted), and write AA, BB, CC to address 1F (FIFO, data that will be transmitted). Continuous write command must be terminated by ‘Continuous stop condition’. Transmission starts when the data is in the FIFO. 8.9.10 Transmission With CRC Expecting Header Bit (91) 8.9.11 Transmission Without CRC (92) am lc s on A te G nt st il This command functions similar to Transmission with CRC (90), but CRC is excluded. lv This command functions similar to Transmission with CRC (90), but also informs RX decoding logic that header bit is expected in the response (Gen 2). 8.9.12 Delayed Transmission With CRC (93) Delayed transmission is used in case the transmission needs to be started in a quite narrow time window after end of reception. The time between end of reception and start of transmission is set in register ‘Delayed transmission wait time’ (06) (see Table 19). The register 06 needs to be set prior to the reception after which the delayed transmit should be done. After sending the ‘Delayed transmission with CRC’ the TX length bytes must be set and transmission data needs to be loaded in the FIFO. The reader transmitting is triggered by the TX timer. Example: 93 3D 00 40 AA BB CC DD will transmit AA BB CC DD and CRC. Transmission will start after delayed defined in reg 06. The delay time will start at the end of previous reception - despite the command is sent during the delay is already running out. 8.9.13 Delayed Transmission Without CRC (94) This command functions similar to Delayed transmission with CRC, but CRC is excluded. 8.9.14 Block RX (96) 8.9.15 Enable RX (97) ca The block RF command puts the digital part of receiver (bit decoder and framer) in reset. The reset of the receiver is useful in case the system operates in an extremely noisy environment, causing a constant switching of the sub-carrier input of the digital part of the receiver. The receiver (if not in reset) would try to ‘catch’ a Preamble and in case the noise pattern matches the expected signal pattern, an interrupt is sent. A constant flow of interrupt requests can be a problem for the external system (MCU), so the external system can stop this by putting the receive decoders in reset mode. The reset mode can be terminated in two ways. One possibility is that the external system sends the ‘Enable RX’ command. The reset mode is also automatically terminated at the end of TX operation. The receiver can stay in reset also after end of TX if the ‘RX wait time’ registers (address 08) is set. In this case, the receiver is enabled at the end of the wait time following the transmit operation. This command clears the reset mode in the digital part of the receiver, if the reset mode was entered on the request by the ‘Block RX’ command. ni 8.10 EPC GEN2 Specific Commands ch 8.10.1 Query (98) The Query command must be followed by 3F (continuous FIFO write) and two bytes of query data (00, DR, M, TRext, Sel, Session, Target, Q). Since this gives 15 applicable bits the last LSB bit is disregarded. Transmitter issues preamble, command, TX data and CRC-5. The received RN16 is stored in an internal register for further communication (ACK…). RN 16 is also achievable from the FIFO. Te 8.10.2 QueryRep (99) The QueryRep command issues the command followed by two session bits. The session bits are taken from ‘TX options’ (02) register. The received RN16 is stored in an internal register for further communication (ACK). RN 16 is also achievable from the FIFO. 8.10.3 QueryAdjustUp (9A) The QueryAdjustUp command issues the command QueryAdjust followed by two session bits and ‘up’ parameter (increase number of slots Q). The session bits are taken from ‘TX options’ (02) register. The received RN16 is stored in an internal register for further communication (ACK…). RN 16 is also achievable from the FIFO. www.austriamicrosystems.com/AS3992 Revision 1.1 42 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.10.4 QueryAdjustNic (9B) The QueryAdjustNic command issues the command QueryAdjust followed by two session bits and ‘no change’ parameter. The session bits are taken from ‘TX options’ (02) register. The received RN16 is stored in an internal register for further communication (ACK). RN 16 is also achievable from the FIFO. 8.10.5 QueryAdjustDown (9C) al id The QueryAdjustUp command issues the command QueryAdjust followed by two session bits and ‘down’ parameter (decrease number of slots Q). The session bits are taken from ‘TX options’ (02) register. The received RN16 is stored in an internal register for further communication (ACK, ReqRN). RN 16 is also achievable from the FIFO. 8.10.6 ACK (9D) The ACK command issues the command followed by RN16 (or handle) that was stored in the internal register. The stored RN16 was acquired in last successful Query command. 8.10.7 NAK (9E) lv The direct NAK command issues the NAK command to tags. 8.10.8 ReqRN (9F) am lc s on A te G nt st il The direct ReqRN command issues the ReqRN command to the tag. The last received RN is used as a parameter and the received new RN16 (handle) is stored in an internal register for further communication (ACK, ReqRN…). New RN 16 is also achievable from the FIFO. 8.11 Reader Communication Interface The basic interface is a parallel 10-pin bus, which can be also configured and used as a serial peripheral interface (SPI) also. Both modes are exclusive and one can not switch between them in a single application. The parallel mode is selected if all IO pins are low during low to high transition of the EN pin (enable). When the serial interface is selected in an application, the unused IO1 and IO0 pins should be hard wired according to Table 48. Upon power-up (EN low to high transition), the reader looks for the status of these three pins and as given in Table 48, it enters parallel or serial mode. The reader will always behave as the “slave” connected to the host system (MCU), which behaves as the “master” device. The host system initiates all communications with the reader and is used for communication to the higher levels towards the host station, which can typically be a personal computer. The reader has an IRQ pin to ask for host system attention. Table 48. Pin Assignment in Parallel and Serial Interface Connection and in Case of Direct Mode Pin 1 Parallel normal mode, Direct mode SPI with SS , Direct mode CLK SCLK from master A/D[7] MOSI (data in) A/D[6], Direct mode out (sub-carrier) MISO (data out), Direct mode out (sub-carrier) A/D[5], Direct mode out (sub-carrier) Direct mode out (sub-carrier) IO4 A/D[4] SS – Slave Select IO3 A/D[3] Direct mode modulation input Direct mode modulation input IO2 A/D[2] Direct mode enable RX input Direct mode enable RX input IO1 A/D[1] Hard wire to VDD_IO IO0 A/D[0] Hard wire to ground IRQ IRQ interrupt IRQ interrupt IO7 IO6 3 Te ch ni IO5 2 ca CLK 1. SS – Slave Select pin active low 2. MOSI – Master Output, Slave Input 3. MISO – Master Input, Slave Output www.austriamicrosystems.com/AS3992 Revision 1.1 43 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Communication is initialized by a Start condition, which should be followed by an Address or Command word. The Address and Command words are 8-bits long. Their format is shown in Table 49. Communication is closed by an appropriate stop condition. Three different communication modes are available – Continuous address mode, non-continuous address mode, and command mode. Continuous address mode needs to be closed by StopCont condition, while the other two modes need to be terminated by StopSgl condition. Table 49. Address / Command Word Bit Distribution Description Bit Function Address Command 7 Command control bit 0=Address, 1=Command 0 1 6 Read/Write 1=Read, 0=Write R/W 5 Continuous address mode 1=Cont., 0=Non-cont mode Cont 4 Address/Command bit 4 Adr 4 3 Address/Command bit 3 Adr 3 2 Address/Command bit 2 Adr 2 Cmd 2 1 Address/Command bit 1 Adr 1 Cmd 1 0 Address/Command bit 0 Adr 0 Cmd 0 al id Bit Not used Not used Cmd 4 am lc s on A te G nt st il lv Cmd 3 The MSB (Bit 7) determines if the word is to be used as a command or address. The last two columns in Table 49 show the function of the separate bits in the event that either address or command is written. Data is expected once the address word is sent. In the event of continuous address mode (Cont mode=1), the first data that follows the address is written (or read) to (from) the given address. For each additional data, the address is incremented by one. This continuous mode can be used to write part of the control registers in a single stream without changing the address: for instance, set-up of the pre-defined standard control registers from the MCU’s non-volatile memory to the reader. In the case of noncontinuous address, only one data word is expected after the address. The two address modes are used to write or read the configuration registers or the FIFO. When writing or reading more than one byte the Continuous address mode should be used. The Command mode is used to enter a command resulting in reader action (initialize transmission, frequency hop…). Examples of expected communication between MCU and reader chip are shown below: Continuous Address Mode Start Adrc x Data (x) Data (x+1) Data (x+2) Data (x+3) Data (x+4) … Data (x+n) StopCont Non-continuous Address Mode (Single Address Mode) Start Adr x Adr y Data (y) … ca Command Mode Data (x) Start Cmd x Cmd y Adr z Data (z) … StopSgl StopSgl Te ch ni Where: Start = start condition Adr = address with Cont bit low Adrc = address with the Cont bit high Cmd = command byte Data = data byte StopSgl = stop condition for termination of the command or non-continuous address mode StopCont = stop condition for termination of the continuous address mode There are also combinations of different communication modes allowed in a single stream between the start and stop condition. Some examples of combined communication are presented below: Non-continuous Address Mode and Command Mode Start Adr x Data (x) www.austriamicrosystems.com/AS3992 Adr y Data (y) … Revision 1.1 Cmd z Cmd w StopSgl 44 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Command and Continuous Address Mode Start Cmd x Cmd y … Adrc z Data (z) Data (z+1) Data (z) Data (z+1) … Data (z+n) StopCont Non-continuous, Command, and Continuous Address Mode Adr x Data (x) … Cmd y … Adrc z … Data (z+n) … StopSgl al id Start Non-continuous address mode and Command mode can be continued by any mode including the Continuous address mode. The Continuous address mode should be terminated by StopCont condition. Changing from Continuous address mode to the other two modes can be done only by StopCont condition followed by start condition. Majority of the registers in the reader IC are 8-bit long. They can be accessed by continuous or non-continuous address mode. Adrc x 1. Least significant byte 2. Middle byte 3. Most significant byte Data0 (x) 1 Data1 (x) 2 Data2 (x) 3 StopCont am lc s on A te G nt st il Start lv Registers 12, 14, 15, 16, and 17 are three bytes deep. They can be accessed by Continuous address mode only. The least significant byte is accessed first. It is possible to access only deep register in a single communication stream, more of them, or combination of normal and deep registers. Example is presented below: Continuous access is possible for registers 00 to the end of the register 12. Register 13 is deep register and prevents continuous access over it to register 14. Continuous access is again possible from register 14 to the end of FIFO (address 1F). The 24 bytes deep FIFO register can be accessed by Continuous address mode only. It is allowed to use communication stream combined of command mode and address mode. Example is combination needed for transmission composed of Reset FIFO, Transmit, write to 1D, 1E for transmission length, and continuously to 1F for filling FIFO with transmission data. Start ResetFIFO Transmit Write Cont. to 1D 8F 90 3D Data (1D) Data (1E) Data FIFO (0) TX length Data FIFO (1) … StopCont TX data 8.12 Parallel Interface Communication ca In parallel mode, the Start condition is triggered by rising edge of the IO7 pin while the CLK pin is high and IO6-IO0 are low. This is used to reset the interface logic. Communication is terminated by StopSgl condition or StopCont condition. StopSgl condition is triggered by falling edge on IO7 pin while CLK pin is high and IO6-IO0 are low. StopCont condition is triggered by successive rising and falling edge on IO7 pin while CLK and IO6-IO0 are low. The ‘StopSgl’ condition is used to terminate the direct mode. ni Figure 6. Parallel Interface Communication with Single Stop Condition “StopSgl” ch Start condition StopSgl Te CLK IO7 a1[7] d1[7] a2[7] d2[7] IO[6:0] a1[6:0] d1[6:0] a2[6:0] d2[6:0] www.austriamicrosystems.com/AS3992 Revision 1.1 aN[7] aN[6:0] dN[7] dN[6:0] 45 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 7. Parallel Interface Communication with Continuous Stop Condition “StopCont” Stop Cont Start condition continuous mode IO7 d0[7] d1[7] d2[7] d3[7] dN[7] a0[6:0] d0[6:0] d1[6:0] d2[6:0] d3[6:0] dN[6:0] am lc s on A te G nt st il lv IO[6:0] a0[7] al id CLK Figure 8. Data Output Only when CLK is High Stop Cont continuous mode Start condition CLK IO7 IO[6:0] internal OE d0[7] d1[7] d2[7] d3[7] dN[7] a0[6:0] d0[6:0] d1[6:0] d2[6:0] d3[6:0] dN[6:0] valid Output data ch ni ca Output Data a0[7] Timing Requirements for Parallel Interface. While using parallel interface, there must always be a separation between CLK transitions and IO0…IO7 transitions. Minimum time interval between transition on CLK and data lines is 100ns. Te Minimum CLK high time interval is 300ns in periods when IO0…IO7 pins are used as data outputs (see Figure 8) or 100ns in periods when IO0…IO7 pins are used as inputs (address, command, or register write). To decrease interferences between MCU communication and RF part of the chip, the output resistance of IO0…IO7 lines is 400Ω typical and 800Ω maximum. The firmware designer should be aware of the fact that in case higher capacitance are connected to these pins, then possibly longer CLK high intervals are needed to allow settling of the output level. www.austriamicrosystems.com/AS3992 Revision 1.1 46 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.13 Serial Interface Communication In serial interface IO4 pin enables the communication, CLK pin is serial data clock, IO7 is serial data input, and IO6 is serial data output. The interface is in reset as long the IO4 pin is high. Communication is started by falling edge on the IO4 pin. Data coming from the host system is sampled on the falling of the CLK pin. When reading out the data from the UHF chip, the data is set on the rising edge of the CLK pin. Host system (MCU) should sample the data on the falling edge on the CLK pin. Communication is terminated by rising edge on the IO4 pin. All words are 8-bits long with the MSB transmitted first. al id Figure 9. Serial Interface Communication Stop condition lv Start condition IO7 x b7 IO4 IO6 b6 am lc s on A te G nt st il CLK b5 b4 b3 b2 b1 b0 x z7 z6 z5 z4 z3 z2 z1 z0 x In this mode the serial interface is in reset while the IO4 signal is high. CLK pin is serial data clock, IO7 is serial data in, and IO6 is serial data output. Communication is terminated when IO4 signal goes high again. Timing Requirements for Serial Interface. Minimum time interval between IO4 falling edge and first CLK change is 100ns. ca Minimum CLK high time interval is 300ns in periods IO6 pin is used as data output (like register reading – data from UHF chip to MCU) or 100ns in periods when IO7 pin is used as input (address, command, or register write – data from MCU to UHF chip). Minimum CLK low interval is 100ns. To decrease interferences between MCU communication and RF part of the chip the output resistance of IO6 line is 400Ω typical and 800Ω maximum. The firmware designer should be aware that in case of higher capacitance is connected to this pin possibly longer CLK high interval is needed to allow settling of the output level. ni Minimum hold time (time in which IO6 output data is valid after the CLK fall edge) is 130ns. Minimum time interval between bytes is 200ns. ch Minimum time interval between last CLK falling edge and IO4 rising edge is 200ns. Te Minimum IO4 high time interval is 200ns. www.austriamicrosystems.com/AS3992 Revision 1.1 47 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.13.1 Timing Diagrams Figure 10. Write Data tCHD tCH tEH tCL CLK tDIS Figure 11. Read Data ENABLE - IO4 DATAI DATAI tDOH DATAO (D7N) tDOD DATAO (D00) Te ch ni MISO - IO6 tDOD ca MOSI - IO7 DATAI tCL tCH CLK DATAI am lc s on A te G nt st il DATAO DATAI lv MOSI - IO7 tDIH al id ENABLE - IO4 www.austriamicrosystems.com/AS3992 Revision 1.1 48 - 53 AS3992 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.13.2 Timing Parameters Table 50. Timing Parameters Symbol Parameter Condition Min Typ Max Units 2 Mbps General tCH Clock high time 250 tCL Clock low time 250 tDIS Data in setup time 20 tDIH Data in hold time 10 tEH Enable hold time 300 tDOH Data out hold time 150 tDOD Data out delay Write timing ns ns ns ns am lc s on A te G nt st il Read timing ns al id Bit rate lv BRSDI 8.14 FIFO 150 ns ns The FIFO is loaded in a cyclical manner. The FIFO and its pointers should be cleared by the Reset FIFO command (0F) prior each FIFO write for transmission. Data coming from the MCU is stored in the FIFO at address 1F hex from location 0 to 23. When the bytes are loaded in the reader, the input FIFO counter is counting the number of bytes loaded into the FIFO. When data is read from the FIFO, an output FIFO counter is incremented and it follows the status of the bytes read. The input and output counters are 12 bits each. They are used to control the data flow in and out of the FIFO. This control sends an interrupt request if the number of bytes in the FIFO is less than 6 and if number of bytes increases to above 18 so that MCU can send new data or remove the data as necessary. It additionally checks that the number of data bytes to be sent does not surpass the value defined in ‘TX length’ bytes. It also signals the transmit logic when the last data to be sent was moved from FIFO to the transmit logic. The number of bytes in the FIFO is available in the FIFO status register. This register also contains three status flags: Fove bit is set in case of FIFO overflow Flol bit is set in case of low FIFO level during transmission Te ch ni ca Fhil bit is set in case of high FIFO level during reception www.austriamicrosystems.com/AS3992 Revision 1.1 49 - 53 AS3992 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 9 Package Drawings and Markings The device is available in a 64-pin QFN (9mm x 9mm) package. al id Figure 12. Drawings and Dimensions am lc s on A te G nt st il lv AS3992 YYWWXZZ Min 0.80 0 0.35 0 0.18 5.90 5.90 - Nom 0.90 0.02 0.20 REF 0.40 0.25 9.00 BSC 9.00 BSC 0.50 BSC 6.00 6.00 0.15 0.10 0.10 0.05 0.08 0.10 64 Max 1.00 0.05 0.45 0.15 0.30 6.10 6.10 - - REF: Reference Dimension, usually without tolerance, for information purposes only. - BSC: Basic Dimension. Theoretically exact value shown without tolerances. ch Notes: ni ca Symbol A A1 A3 L L1 b D E e D2 E2 aaa bbb ccc ddd eee fff N Te 1. Dimensions and Tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. Angles are in degrees. 3. Dimension b applies to metalized terminal and is measured between 0.25mm and 0.30mm from terminal tip. Dimension L1 represents terminal full back from package edge up to 0.15mm is acceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional. 6. N is the total number of terminals Marking: YYWWXZZ. YY WW X ZZ Year (i.e. 10 for 2010) Manufacturing Week Assembly plant identifier Assembly traceability code www.austriamicrosystems.com/AS3992 Revision 1.1 50 - 53 AS3992 Datasheet - R e v i s i o n H i s t o r y Revision History Date 1.0 Dec 21, 2009 1.1 Nov 24, 2010 Owner Description Initial revision tlu Updated current consumption, Key Features, Package Drawings and Markings, Ordering Information Te ch ni ca am lc s on A te G nt st il lv Note: Typos may not be explicitly mentioned under revision history. al id Revision www.austriamicrosystems.com/AS3992 Revision 1.1 51 - 53 AS3992 Datasheet - O r d e r i n g I n f o r m a t i o n 10 Ordering Information The devices are available as the standard products shown in Table 51. Table 51. Ordering Information 1 Description Delivery Form Package AS3992-BQFP Internal DRM compatible VCO, pre-distortion Tape and Reel in dry pack 64-pin QFN (9mm x 9mm) Note: All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect Technical Support is availableat http://www.austriamicrosystems.com/Technical-Support Te ch ni ca am lc s on A te G nt st il For further information and requests, please contact us mailto: sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor lv 1. Dry Pack Sensitivity Level =3 according to IPC/JEDEC J-STD-033A for full reels. al id Ordering Code www.austriamicrosystems.com/AS3992 Revision 1.1 52 - 53 AS3992 Datasheet - C o p y r i g h t s Copyrights Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. 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No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. ni austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria ch Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: Te http://www.austriamicrosystems.com/contact www.austriamicrosystems.com/AS3992 Revision 1.1 53 - 53 AS3992 (V6) Errata Sheet Known issues in the digital section: No. P1 Issue description clsys=000b enables 60kHz on the CLSYS output Comment As a consequence a -62dBc TX spur at 60kHz can be seen. This problem can be considered as noncritical. By using the proposed workaround, the spur disappears. Workaround Set the bit open_dr in register 0x05 to high. No. P2 Issue description In case exactly two bytes are received in the FIFO and both bytes are read out during reception, the subsequent ReqRN command is corrupted. Comment The data length information is contained in the first received byte – therefore it is sufficient to read only one byte. Workaround Read out only the first FIFO byte which contains the EPC length information upon receiving Irq_2nd_byte The case happens when 2byte_irq is used. Any other number of bytes (1, 3, 4, …) can be read out without any problems. No. P5 Issue description In case BlockRX is used after receiving the RN16 the IRQstatus register (0x0C) reports 0x00 instead of 0x4x. (Select, NAK) Comment An alternative to the Block RX command, reg03:0A can be used as well. Workaround Skip the direct command BlockRX. In case the issue still happen act as in case of a collision. No. P6 Issue description In case BlockRX is used after receiving the RN16 the IRQstatus register (0x0C) reports 0xC0 instead of 0x4x. (Select, NAK) Comment An alternative to the Block RX command, reg03:0A can be used as well. Workaround Skip the direct command BlockRX. In case the issue still happen act as in case of a collision. No. P7 Issue description After corrupted reception of RN16 with IRQstatus register (0x0C) = 0x40 the reception remains enabled, TX is blocked and consequently the TX IRQ is missing. Comment There are two possibilities to identify this condition: (1) Read IRQstatus just after subsequent TX command (IRQstatus=0x80 is expected) (2) Watch dog timer action when waiting on the missing IRQ pulse at the end of transmission. Workaround EN H-L-H transition is needed. STRICTLY CONFIDENTIAL 1/3 20 Sept. 12 No. P8 Issue description After EPC reception the IRQstatus register contains 0X00. Comment This case does not indicate that a collision has happened. There is no need to increase the number of slots in the subsequent inventory. Workaround Continue inventory round as if a corrupted EPC was received. No. P9 Issue description After any reception the IRQstatus register contains 0x41. Comment Workaround Continue inventory round as if a corrupted reception has happened (collision on RN, error EPC…) No. P10 Issue description SPI: Direct command Reset FIFO (0x8F) should not be sent before the direct command ReqRN (0x9F). Comment Workaround Send the direct command Reset FIFO after the TX IRQ, before the receiving the HANDLE. No. G5d Issue description SPI: Reading the FIFO register 0x1F should not be done right after an IO4 H-L transition. Comment Workaround Read the FIFO status register in single byte mode before reading the contents of the FIFO register. Known issues in the analogue section: No. A4b Issue description MCU support current not stable and higher than expected (400uA1000uA). Should be 400-500uA typ. Comment Issue is less critical since MCU current in operation is typically much higher than the unwanted 500uA. Workaround No. H3 Issue description The internal PA cannot be used in majority of the applications due to insufficient linearity and stability. Comment Use low power RF output. Workaround STRICTLY CONFIDENTIAL 2/3 20 Sept. 12 Important Notes & Hints No. P3 Issue description QueryRep and QueryAdj need a Reset FIFO (0x8F) direct command for correct operation. Comment Not critical in a normal inventory round in case an access operation (read/write) is done in the same round. The issue decreases tag inventory rate in case only the EPCs are read and no read or write operation is planned. Recommendation Use Reset FIFO command before QueryRep and QueryAdj. No. P3A Issue description Direct commands for transmission (0x90, 0x91, 0x92) require a Reset FIFO direct command for correct operation. Comment Recommendation Use Reset FIFO before transmission commands. No. P4 Issue description To meet a StopSgl condition a IO7 transition at CLK=H is needed. IO6:0 should be stable during StopSgl. Comment Previously also the stop condition met by a transition of all IO lines at CLK=H was allowed. Recommendation Use correct StopSgl. No. G8 Issue description A FIFO read operation requires the continuous read mode for correct status of the pointers. Comment Recommendation Read FIFO contents in the continuous read mode. STRICTLY CONFIDENTIAL 3/3 20 Sept. 12