ST2S06BPQR

ST2S06 Dual synchronous rectification with reset or inhibit, 0.5 A, 1.5 MHz adjustable step-down switching regulator Datasheet - production data Description The ST2S06A33 and ST2S06B are dual stepdown DC-DC converters optimized for powering low-voltage digital cores in ODD applications and, generally, to replace high current linear solutions when the power dissipation may cause high heating of the application environment. It provides up to 0.5 A over an input voltage range of 2.5 V to 5.5 V. QFN12L (4 x 4 mm) Features  Step-down current mode PWM (1.5 MHz) DCDC converter  Fixed or adjustable output voltage from 0.8 V  2% DC output voltage tolerance A high switching frequency of 1.5 MHz allows the use of tiny surface-mount components as well as a resistor divider to set the output voltage value. Only an inductor and two capacitors are required. A low output ripple is guaranteed by the current mode PWM topology and the utilization of low ESR SMD ceramic capacitors. The devices are thermally protected and current-limited to prevent damage due to accidental short-circuit. The ST2S06A33 and ST2S06B are available in the QFN12L (4x4 mm) package.  Synchronous rectification  Reset function for A version  Inhibit function for B version  Internal soft start for startup current limitation and power ON delay of 50-100 µs  Typical efficiency: > 90%  0.5 A output current capability  Non-switching quiescent current: max 1.2 mA over temperature range  RDS(ON) 150 m (typ.)  Uses tiny capacitors and inductors  Available in QFN12L (4x4 mm) Table 1. Device summary Order codes Package Packaging QFN12L (4 x 4 mm) Tape and reel ST2S06A33PQR ST2S06BPQR May 2013 This is information on a product in full production. DocID13866 Rev 6 1/18 www.st.com Contents ST2S06 Contents 1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 DocID13866 Rev 6 ST2S06 1 Schematic diagram Schematic diagram Figure 1. Schematic diagram RESET_OUT * VI_SW VI_A Delay Ref SW HV Trimming FB1 VI_SW SW2 FB2 CONTROL LOGIC Ref Soft Start GND INH** GND * ST2S06A33 ** ST2S06B DocID13866 Rev 6 3/18 18 Pin configuration 2 ST2S06 Pin configuration Figure 2. Pin connections (top view) Table 2. Pin description 4/18 Pin n° ST2S06A33 ST2S06B Name and function 1 HV HV Programing pin. It must be floating or connected to GND. 2 FB2 FB2 Feedback voltage 3 GND2 GND2 Power ground 4 SW2 SW2 Switching pin 5 VIN_SW VIN_SW 6 SW1 SW1 Switching pin 7 GND1 GND1 Power ground 8 FB1/OUT1 FB1 Feedback voltage / output voltage 9 Reset_out NC Reset out pin 10 NC INH Inhibit pin 11 VIN_A VIN_A Supply for analog circuit 12 GND_A GND_A System ground Power input voltage pin DocID13866 Rev 6 ST2S06 3 Maximum ratings Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VIN_SW Positive power supply voltage -0.3 to 7 V VIN_A Positive power supply voltage -0.3 to 7 V VINH Inhibit voltage -0.3 to 7 V -0.3 to 7 V -0.3 to 2.5 V -0.3 to 5 V +1 to -1 mA 150 °C -65 to +150 °C 300 °C SWITCH voltage Max. voltage of output pin VFB1,2/VO1 Feedback voltage/output voltage Output voltage (for VO > 1.6 V) VO1 Current into VFB Common mode input voltage pin Max junction temperature TJ Note: TSTG Storage temperature range TLEAD Lead temperature (soldering) 10 sec. Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 4. Thermal data Symbol Parameter Value Unit RthJC Thermal resistance junction-case 10 °C/W RthJA Thermal resistance junction-ambient 60 °C/W Table 5. ESD performance Symbol ESD Parameter ESD protection voltage Test conditions HBM-DH11C DocID13866 Rev 6 Value Unit 4 kV 5/18 18 Electrical characteristics 4 ST2S06 Electrical characteristics VIN_SW = VIN_A = 5 V, V01 = 3.3 V, VO2 = 1.2 V, C1 = 4.7 µF, C2 = C3 = 22 µF, L1 = L2 = 3.3 µH, TJ = - 30 to 125 °C unless otherwise specified. Typical values are referred to 25 °C. Table 6. Electrical characteristics for the ST2S06A33 Symbol Min. Typ. Max. Unit Output feedback pin 3.23 3.3 3.37 V FB2 Feedback voltage 784 800 816 mV IO1 IO1 pin bias current VO = 3.5 V 15 20 µA IFB2 VFB pin bias current VFB = 1 V 600 nA Quiescent current VFB = 1 V 1.2 mA IO1,2 Output current VIN = 4 to 5.5 V (1) IMIN Minimum output current OUT1 IQ %VO1,2/VI Parameter Test conditions A 1 Reference line regulation 4V < VIN < 5.5 V VO1,2 Reference load regulation 10mA < IO < 0.5 A PWM fS PWM switching frequency(1) VFB = 0.7 V, TA = 25°C DMAX Maximum duty cycle VFB = 0.7 V, TA = 25°C ISWL Switching current limitation ILKN NMOS leakage current ILKP PMOS leakage current N 0.8 mA %VO/ VIN 0.032 5.5 15 mV 1.2 1.5 1.8 MHz 85 94 % 1 1.2 A VFB = 0.9 V, TA = 25°C 0.1 µA VFB = 0.9 V, TA = 25°C 0.1 µA RDSon-N NMOS switch on resistance ISW = 250 mA 0.15 0.3 W RDSon-P PMOS switch on resistance ISW = 250 mA 0.2 0.4 W  Efficiency TSHDN Thermal shut down THYS Thermal shut down hysteresis (2) IO = 20 mA to 100 mA 75 % IO = 100 mA to 0.5 A 90 % 150 °C 15 °C (2) VO1,2/IO Load transient response (2) 130 100 mA < IO < 500 mA tR = tF => 100 ns, TA = 25°C -5 +5 %VO Reset section tDEL Delay time TA = 25°C 80 85 Reset in threshold measured on input pin VIN_A Rising 4.5 4.6 4.75 VRES VIN_A Falling 4.12 4.2 4.28 1. VO = 90% of nominal value. 2. Guaranteed by design, but not tested in production. 6/18 DocID13866 Rev 6 ms V ST2S06 Electrical characteristics VIN_SW = VIN_A = 5 V, VO1,2 =1.2 V, C1= 4.7 µF, C2 = C3 = 22 µF, L1 = L2 = 3.3 µH, TJ = -30 to 125 °C unless otherwise specified. Typical values are referred to 25 °C. Table 7. Electrical characteristics for the ST2S06B Symbol Parameter Test conditions FB1,2 Feedback voltage IFB1,2 VFB pin bias current IQ Quiescent current IO1,2 Output current IMIN Minimum output current VINH Min. Typ. Max. Unit 784 800 816 mV 600 nA VINH > 1.2 V, VFB = 1 V 1 mA VINH < 0.4 V 1 µA VFB = 1 V VIN = 2.5 to 5.5 V Inhibit threshold (1) 0.8 1 2.5V < VIN < 5 V 1.2 2.5V < VIN < 5.5 V 1.3 mA V Device OFF IINH1,2 A 0.4 Inhibit pin current 2 µA %VO1,2/ VIN Reference line regulation 2.5V < VIN < 5.5 V 0.032 %VO/ VIN VO1,2 Reference load regulation 10 mA < IO < 0.5 A 5.5 15 mV PWM fS PWM switching frequency(1) VFB = 0.7 V, TA = 25°C 1.2 1.5 1.8 MHz DMAX Maximum duty cycle VFB = 0.7 V, TA = 25°C 85 94 % ISWL Switching current limitation 1 1.2 A ILKN NMOS leakage current VFB = 0.9 V, TA = 25°C 0.1 µA ILKP PMOS leakage current VFB = 0.9 V, TA = 25°C 0.1 µA RDSon-N NMOS switch on resistance ISW = 250 mA 0.15 0.3 W RDSon-P PMOS switch on resistance ISW = 250 mA 0.2 0.4 W  Efficiency TSHDN Thermal shut down THYS Thermal shut down hysteresis (1) IO = 20 mA to 100 mA 75 % IO = 100 mA to 0.5 A 90 % 150 °C 15 °C (2) VO1,2/IO Load transient response (1) 130 100 mA < IO < 500 mA, tR = tF1 => 100 ns, TA = 25°C -5 +5 %VO 1. VO= 90% of nominal value. 2. Guaranteed by design, but not tested in production. DocID13866 Rev 6 7/18 18 Typical performance characteristics 5 ST2S06 Typical performance characteristics Figure 3. Feedback voltage 1 vs. temperature (ST2S06B) Figure 4. Feedback voltage 2 vs. temperature (ST2S06B) 0.82 0.82 VI=5V, VFB1 connected to VO1 IO1=IO2=NO LOAD VI=5V, VFB2 connected to VO2 IO1=IO2 =NO LOAD 0.81 VFB2 [V] VFB1 [V] 0.81 0.8 0.79 0.8 0.79 0.78 0.78 -50 -25 0 25 50 75 100 125 -50 -25 0 TEMPERATURE [°C] VI=5V, VO1=3.3V, IO2 NO LOAD 0 0.1 0.2 0.3 0.4 0.5 100 95 90 85 80 75 70 65 60 55 50 45 40 0.6 0 Frequency [MHz] Duty Cycle [%] 0 25 50 75 100 125 100 99 98 97 96 95 94 93 92 91 90 0.1 0.2 0.3 0.4 0.5 0.6 VI=5V, VFB1=3.2V, VFB2=0.7V -50 Temperature [°C] 8/18 125 Figure 8. Duty cycle vs. temperature (ST2S06A33) VI=5V, VFB1=3.2V, VFB2=0.7V -25 100 Output Current 2 [A] Figure 7. Switching frequency vs. temperature (ST2S06A33) -50 75 VI=5V, VO2=1.2V, IO1 NO LOAD Output Current 1 [A] 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 50 Figure 6. Efficiency vs. output current 2 EFFICIENCY [%] EFFICIENCY [%] Figure 5. Efficiency vs. output current 1 100 95 90 85 80 75 70 65 60 25 TEMPERATURE [°C] -25 0 25 50 Temperature [°C] DocID13866 Rev 6 75 100 125 ST2S06 Typical performance characteristics 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 Figure 10. Inhibit threshold vs. temperature (ST2S06B) 1.4 VI=5V, IO1= IO2=100mA 1.2 ON 1 VINH (V) Frequency [MHz] Figure 9. Switching frequency vs. temperature (ST2S06B) 0.8 OFF 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 -50 125 -25 0 25 Figure 11. Switching current limitation vs. input voltage (ST2S06A33) 75 100 125 Figure 12. PMOS switch on resistance vs. temperature 2 240 VI from 2.5V to 5.5V, Output2 Maximum load Current RDSON -P[mOhm] 1.8 ISW2 [A] 50 T [C°] Temperature [°C] 1.6 1.4 1.2 VCC=5V, ISW=250mA 220 200 180 160 140 120 1 100 2.5 3 3.5 4 4.5 5 5.5 -50 -25 0 25 50 75 100 125 T [°C] VI [V] Figure 13. NMOS switch on resistance vs. temperature Figure 14. Delay time vs. temperature (ST2S06A33) RDSON -N[mOhm] 170 150 130 VI 110 VCC=5V, ISW=250mA 90 VRES 70 50 -50 -25 0 25 50 75 100 125 T [°C] VI Rising from 0V to 5V, Delay from VRES threshold and reset pin below 0V. DocID13866 Rev 6 9/18 18 Typical performance characteristics ST2S06 100 95 90 85 80 75 70 65 60 55 50 Figure 16. Reset in threshold vs. temperature (ST2S06A33) VRES (V) TDEL (ms) Figure 15. Delay time vs. temperature (ST2S06A33) VI Rising from 0V to 5V -50 -25 0 25 50 75 100 5 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4 Rising Falling -50 125 -25 0 25 50 75 100 T [C°] T [C°] Figure 17. Load transient response (ST2S06A33) Figure 18. Startup transient (ST2S06A33) VI VO1 VO1 IO1 VI= from 0V to 5V, IO1=500mA, Output Voltage=3.3V VI= 5V, IO1 from 100mA to 500mA Figure 19. Startup transient (ST2S06B) Figure 20. Inhibit transient (ST2S06B) VINH IO1 VI VO1 VO1 VO2 VI= from 0V to 5V, IO1 =1A, Output Voltage=1.2V 10/18 VINH= from 0V to 2V, VI=5V, IO1=IO2=1A DocID13866 Rev 6 125 ST2S06 Typical application 6 Typical application Figure 21. Application circuit for the ST2S06A33 V IN 3.3 µH L2 VIN_A SW2 VIN_SW VFB2 R3 V O2 L1 3.3 µH ST2S06A33 SW1 NC R1 V O1 VFB1 Reset_Out GND1 GND2 HV GND_A C1 4.7 µF C2 22 µF R2 C3 R4 22 µF R3 VO2 Figure 22. Application circuit for ST2S06B L2 VIN VIN_A SW2 VIN_SW VFB2 L1 3.3µH ST2S06B INH C1 4.7µF NC GND1 GND2 HV 3.3µH SW1 R1 VFB1 VO1 GND_A R2 DocID13866 Rev 6 C2 22µF R4 C3 22µF 11/18 18 Application information 7 ST2S06 Application information The ST2S06A33 and ST2S06B represent a series of dual adjustable current mode PWM step-down DC-DC converters with an internal 0.5 A power switch, packaged in a QFN12L (4x4 mm). It is a complete 0.5 A switching regulator with internal compensation that eliminates the need for additional components. The constant frequency, current mode, PWM architecture and stable operation with ceramic capacitors results in low, predictable output ripple. To clamp the error amplifier reference voltage a soft start control block generating a voltage ramp has been implemented. Other circuits fitted to the device protection are the thermal shut-down block, which turns off the regulator when the junction temperature exceeds 150 °C (typ.), and the cycle-by-cycle current limiting that provides protection against shorted outputs. The output voltage is determined by an external resistor divider, as the ST2S06A33 and ST2S06B are adjustable regulators. The desired value is given by the following equation: VO = VFB [1+R1/R2] Operation of the device requires few components: 2 inductors, 3 capacitors and a resistor divider. The chosen inductor must be capable of not saturating at the peak current level. Its value should be selected keeping in mind that a large inductor value increases the efficiency at low output current and reduces output voltage ripple, while a smaller inductor can be chosen when it is important to reduce package size and total application cost. Finally, the ST2S06A33 and ST2S06B have been designed to work properly with X5R or X7R SMD ceramic capacitors both at the input and at the output. These types of capacitors, due to their very low series resistance (ESR), minimize the output voltage ripple. Other low ESR capacitors can be used according to the need of the application without compromising the correct functionality of the device. Due to the high switching frequency and peak current, it is important to optimize the application environment by reducing the length of the PCB traces and placing all the external components near the device. Figure 23. Reset function VIN VTH VTL tDEL Reset 12/18 DocID13866 Rev 6 ST2S06 8 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID13866 Rev 6 13/18 18 Package mechanical data ST2S06 QFN12L (4x4) mechanical data mm. inch. Dim. Min. Typ. Max. Min. Typ. Max. 0.80 0.90 1.00 0.031 0.035 0.039 A1 0.02 0.05 0.001 0.002 A3 0.20 A 0.008 b 0.25 0.30 0.35 0.010 0.012 0.014 D 3.90 4.00 4.10 0.154 0.157 0.161 D2 2.00 2.15 2.25 0.079 0.085 0.089 E 3.90 4.00 4.10 0.154 0.157 0.161 E2 2.00 2.15 2.25 0.079 0.085 0.089 e L 0.80 0.45 0.55 0.031 0.65 0.018 0.022 0.026 7936361B 14/18 DocID13866 Rev 6 ST2S06 Package mechanical data Tape & reel QFNxx/DFNxx (4x4) mechanical data mm. inch. Dim. Min. Typ. A Max. Min. Typ. 330 C 12.8 D 20.2 N 99 13.2 Max. 12.992 0.504 0.519 0.795 101 T 3.898 3.976 14.4 0.567 Ao 4.35 0.171 Bo 4.35 0.171 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 DocID13866 Rev 6 15/18 18 Package mechanical data ST2S06 Figure 24. QFN12L (4x4 mm) footprint recommended data 16/18 DocID13866 Rev 6 ST2S06 9 Revision history Revision history Table 8. Document revision history Date Revision Changes 3-Sep-2007 1 Initial release. 21-Jan-2008 2 Added root part number ST2S06D33. 18-Mar-2008 3 Modified: Table 2 on page 4. 28-Jul-2009 4 Modified: Table 1 on page 1. 24-May-2012 5 – Changed max value for Non-switching quiescent current to 1.2 mA in Features on page 1. – Updated part number in Figure 21 on page 11 – Minor text changes throughout the document 22-May-2013 6 – Changed title in cover page DocID13866 Rev 6 17/18 18 ST2S06 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 18/18 DocID13866 Rev 6