ST62T01CB3

ST6200C ST6201C ST6203C 8-bit MCUs with A/D converter, two timers, oscillator safeguard & safe reset ■ ■ ■ ■ ■ ■ ■ Memories – 1K or 2K bytes Program memory (OTP, EPROM, FASTROM or ROM) with read-out protection – 64 bytes RAM Clock, Reset and Supply Management – Enhanced reset system – Low voltage detector (LVD) for safe Reset – Clock sources: crystal/ceramic resonator or RC network, external clock, backup oscillator (LFAO) – Oscillator safeguard (OSG) – 2 Power saving modes: Wait and Stop Interrupt Management – 4 interrupt vectors plus NMI and RESET – 9 external interrupt lines (on 2 vectors) 9 I/O Ports – 9 multifunctional bidirectional I/O lines – 4 alternate function lines – 3 high sink outputs (20mA) 2 Timers – Configurable watchdog timer – 8-bit timer/counter with a 7-bit prescaler Analog Peripheral – 8-bit ADC with 4 input channels (except on ST6203C) Instruction Set – 8-bit data manipulation – 40 basic instructions – 9 addressing modes – Bit manipulation PDIP16 SO16 SSOP16 CDIP16W (See Section 11.5 for Ordering Information) ■ Development Tools – Full hardware/software development package Device Summary Features ST6200C ST6201C ST6203C Program memory - bytes 1K 2K 1K RAM - bytes Operating Supply Analog Inputs Clock Frequency Operating Temperature Packages October 2009 64 3.0V to 6V 4 8MHz Max -40°C to +125°C PDIP16 / SO16 / SSOP16 Doc ID 4563 Rev 5 1/100 1 Table of Contents ST6200C ST6201C ST6203C . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . 8 3.1 MEMORY AND REGISTER MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.3 Readout Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.4 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.5 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.6 Data ROM Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.2 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 CLOCKS, SUPPLY AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Oscillator Safeguard (OSG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 19 20 21 21 22 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 RESET Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 24 25 25 26 5.5 INTERRUPT RULES AND PRIORITY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.6 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.7 NON MASKABLE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.8 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.9 EXTERNAL INTERRUPTS (I/O PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.9.1 Notes on using External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 . . . . 28 5.10 INTERRUPT HANDLING PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.10.1Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/100 2 Doc ID 4563 Rev 5 Table of Contents 5.11 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4 NOTES RELATED TO WAIT AND STOP MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4.1 Exit from Wait and Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4.2 Recommended MCU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.1 Digital Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.2 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.3 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.4 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.5 Instructions NOT to be used to access Port Data registers (SET, RES, INC and DEC) 38 7.2.6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.5 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.4 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 8-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 41 42 42 43 43 44 45 8.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3 Counter/Prescaler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 45 46 46 46 47 48 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 48 49 50 51 51 51 9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Doc ID 4563 Rev 5 3/100 3 Table of Contents 9.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.1.1Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.3Typical Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.4Loading Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.5Pin Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 58 58 58 58 59 10.2.1Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 59 59 60 10.3.1General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.3.2Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . 61 10.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.4.1RUN Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.3STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.4Supply and Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.5On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 63 66 67 67 68 10.5.1General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.2External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.3Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.4RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.5Oscillator Safeguard (OSG) and Low Frequency Auxiliary Oscillator (LFAO) . . . . . 10.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 68 69 70 71 72 10.6.1RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.6.2EPROM Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.7.1Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.2Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.3ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 74 76 77 10.8.1General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.8.2Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.9.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.9.2NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 . . . . 83 10.10.28-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4/100 1 Doc ID 4563 Rev 5 Table of Contents 11 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.3 ECOPACK INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.6 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.6.1FASTROM version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.6.2ROM VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13 ST6 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 15 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Doc ID 4563 Rev 5 5/100 1 ST6200C ST6201C ST6203C 1 INTRODUCTION The ST6200C, 01C and 03C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip peripherals. The ST62E01C is the erasable EPROM version of the ST62T00C, T01 and T03C devices, which may be used during the development phase for the ST62T00C, T01 and T03C target devices, as well as the respective ST6200C, 01C and 03C ROM devices. OTP and EPROM devices are functionally identical. OTP devices offer all the advantages of user programmability at low cost, which make them the ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programmability are required. The ROM based versions offer the same functionality, selecting the options defined in the program- mable option bytes of the OTP/EPROM versions in the ROM option list (See Section 11.6 on page 92). The ST62P00C, P01C and P03C are the Factory Advanced Service Technique ROM (FASTROM) versions of ST62T00C, T01 and T03C OTP devices. They offer the same functionality as OTP devices, but they do not have to be programmed by the customer (See Section 11 on page 86). These compact low-cost devices feature a Timer comprising an 8-bit counter with a 7-bit programmable prescaler, an 8-bit A/D Converter with 4 analog inputs (depending on device, see device summary on page 1) and a Digital Watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications. For easy reference, all parametric data are located in Section 10 on page 58. Figure 1. Block Diagram 8-BIT * A/D CONVERTER VPP PORT A NMI INTERRUPTS PORT B PROGRAM : MEMORY DATA ROM USER SELECTABLE (1K or 2K Bytes) TIMER DATA RAM 64 Bytes WATCHDOG TIMER PC STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER SUPPLY VDD VSS 8-BIT CORE OSCILLATOR RESET OSCin OSCout RESET * Depending on device. Please refer to I/O Port section. 6/100 4 PA1..PA3 (20mA Sink) Doc ID 4563 Rev 5 PB0..PB1 PB3, PB5..PB7 / Ain* ST6200C ST6201C ST6203C 2 PIN DESCRIPTION Figure 2. 16-Pin Package Pinout VDD 1 16 VSS OSCin 2 15 PA1/20mA Sink OSCout 3 14 PA2/20mA Sink NMI VPP RESET 4 13 PA3/20mA Sink 5 12 6 11 PB0 PB1 Ain*/PB7 Ain*/PB6 7 8 it1 it2 10 it2 9 PB3/Ain* PB5/Ain* itX associated interrupt vector * Depending on device. Please refer to I/O Port section. Pin n° Pin Name Type Table 1. Device Pin Description Main Function (after Reset) Alternate Function 1 VDD S Main power supply 2 OSCin I External clock input or resonator oscillator inverter input 3 OSCout O Resonator oscillator inverter output or resistor input for RC oscillator 4 NMI I Non maskable interrupt (falling edge sensitive) 5 VPP 6 RESET I/O Top priority non maskable interrupt (active low) 7 PB7/Ain* I/O Pin B7 (IPU) Analog input 8 PB6/Ain* I/O Pin B6 (IPU) Analog input Must be held at Vss for normal operation, if a 12.5V level is applied to the pin during the reset phase, the device enters EPROM programming mode. 9 PB5/Ain* I/O Pin B5 (IPU) Analog input 10 PB3/Ain* I/O Pin B3 (IPU) Analog input 11 PB1 I/O Pin B1 (IPU) 12 PB0 I/O Pin B0 (IPU) 13 PA3/ 20mA Sink I/O Pin A3 (IPU) 14 PA2/ 20mA Sink I/O Pin A2 (IPU) 15 PA1/ 20mA Sink I/O Pin A1 (IPU) 16 VSS S Ground Legend / Abbreviations for Table 1: * Depending on device. Please refer to I/O Port section. I = input, O = output, S = supply, IPU = input pull-up The input with pull-up configuration (reset state) is valid as long as the user software does not change it. Refer to Section 7 "I/O PORTS" on page 36 for more details on the software configuration of the I/O ports. Doc ID 4563 Rev 5 7/100 ST6200C ST6201C ST6203C 3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES 3.1 MEMORY AND REGISTER MAPS 3.1.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Briefly, Program space contains user program code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack space accommodates six levels of stack for subroutine and interrupt service routine nesting. Figure 3. Memory Addressing Diagram PROGRAM SPACE DATA SPACE 000h 000h RESERVED 03Fh 040h DATA ROM WINDOW PROGRAM MEMORY 07Fh 080h 081h 082h 083h 084h (see Figure 4) X REGISTER Y REGISTER V REGISTER W REGISTER RAM 0BFh 0C0h 0FF0h INTERRUPT & RESET VECTORS 0FFFh 8/100 1 0FFh Doc ID 4563 Rev 5 HARDWARE CONTROL REGISTERS (see Table 2) ACCUMULATOR ST6200C ST6201C ST6203C MEMORY MAP (Cont’d) Figure 4. Program Memory Map ST62T03C,T00C ST62T01C, E01C 0000h 0000h NOT IMPLEMENTED NOT IMPLEMENTED 07FFh 0800h RESERVED* 087Fh 0880h 0AFFh 0B00h 0B9Fh RESERVED* USER PROGRAM MEMORY 0BA0h USER PROGRAM MEMORY 1824 BYTES 1024 BYTES 0F9Fh 0FA0h 0FEFh 0FF0h 0FF7h 0FF8h 0FFBh 0FFCh 0FFDh 0FFEh 0FFFh 0F9Fh 0FA0h 0FEFh 0FF0h 0FF7h 0FF8h 0FFBh 0FFCh 0FFDh 0FFEh 0FFFh RESERVED* INTERRUPT VECTORS RESERVED* NMI VECTOR USER RESET VECTOR RESERVED* INTERRUPT VECTORS RESERVED* NMI VECTOR USER RESET VECTOR (*) Reserved areas should be filled with 0FFh Doc ID 4563 Rev 5 9/100 1 ST6200C ST6201C ST6203C MEMORY MAP (Cont’d) 3.1.2 Program Space Program Space comprises the instructions to be executed, the data required for immediate addressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register (PC register). Thus, the MCU is capable of addressing 4K bytes of memory directly. 3.1.3 Readout Protection The Program Memory in in OTP, EPROM or ROM devices can be protected against external readout of memory by setting the Readout Protection bit in the option byte (Section 3.3 on page 15). In the EPROM parts, Readout Protection option can be desactivated only by U.V. erasure that also results in the whole EPROM context being erased. Note: Once the Readout Protection is activated, it is no longer possible, even for STMicroelectronics, to gain access to the OTP or ROM contents. Returned parts can therefore not be accepted if the Readout Protection bit is set. 3.1.4 Data Space Data Space accommodates all the data necessary for processing the user program. This space comprises the RAM resource, the processor core and peripheral registers, as well as read-only data 10/100 1 such as constants and look-up tables in OTP/ EPROM. 3.1.4.1 Data ROM All read-only data is physically stored in program memory, which also accommodates the Program Space. The program memory consequently contains the program code to be executed, as well as the constants and look-up tables required by the application. The Data Space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in OTP/EPROM. 3.1.4.2 Data RAM The data space includes the user RAM area, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the peripheral data and control registers, the interrupt option register and the Data ROM Window register (DRWR register). 3.1.5 Stack Space Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents. Doc ID 4563 Rev 5 ST6200C ST6201C ST6203C MEMORY MAP (Cont’d) Table 2. Hardware Register Map Address Block 080h to 083h CPU 0C0h 0C1h I/O Ports Register Label Reset Status Remarks X,Y,V,W X,Y index registers V,W short direct registers xxh R/W DRA 1) 2) 3) DRB 1) 2) 3) Port A Data Register Port B Data Register 00h 00h R/W R/W 00h 00h R/W R/W 0C2h 0C3h 0C4h 0C5h Register Name Reserved (2 Bytes) I/O Ports DDRA 2) DDRB 2) 0C6h 0C7h Port A Direction Register Port B Direction Register Reserved (2 Bytes) 0C8h CPU IOR Interrupt Option Register xxh Write-only 0C9h ROM DRWR Data ROM Window register xxh Write-only 00h 00h R/W R/W Read-only Ro/Wo 0CAh 0CBh 0CCh 0CDh Reserved (2 Bytes) I/O Ports ORA 2) ORB 2) 0CEh 0CFh Port A Option Register Port B Option Register Reserved (2 bytes) 0D0h 0D1h ADC ADR ADCR A/D Converter Data Register A/D Converter Control Register xxh 40h 0D2h 0D3h 0D4h Timer 1 PSCR TCR TSCR Timer 1 Prescaler Register Timer 1 Downcounter Register Timer 1 Status Control Register 7Fh 0FFh 0D5h to 0D7h 0D8h 0FEh R/W xxh R/W Reserved (3 Bytes) Watchdog Timer WDGR 0D9h to 0FEh 0FFh 00h R/W R/W R/W Watchdog Register Reserved (38 Bytes) CPU A Accumulator Legend: x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s) in the register. Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always be kept at their reset value. 3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured in input mode (refer to Section 7 "I/O PORTS" on page 36 for more details). 4. Depending on device. See device summary on page 1. Doc ID 4563 Rev 5 11/100 1 ST6200C ST6201C ST6203C MEMORY MAP (Cont’d) 3.1.6 Data ROM Window The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes located anywhere in program memory, between address 0000h and 0FFFh. There are 64 blocks of 64 bytes in a 4K device: – Block 0 is related to the address range 0000h to 003Fh. – Block 1 is related to the address range 0040h to 007Fh. and so on... All the program memory can therefore be used to store either instructions or read-only data. The Data ROM window can be moved in steps of 64 bytes along the program memory by writing the appropriate code in the Data ROM Window Register (DRWR). Figure 5. Data ROM Window PROGRAM 0000h SPACE 12/100 1 Address: 0C9h — Write Only Reset Value = xxh (undefined) 7 - 0 - DRWR5 DRWR4 DRWR3 DRWR2 DRWR1 DRWR0 Bits 7:6 = Reserved, must be cleared. 000h DATA SPACE 040h DATA ROM 64-BYTE ROM 07Fh WINDOW 0FFFh 3.1.6.1 Data ROM Window Register (DRWR) The DRWR can be addressed like any RAM location in the Data Space. This register is used to select the 64-byte block of program memory to be read in the Data ROM window (from address 40h to address 7Fh in Data space). The DRWR register is not cleared on reset, therefore it must be written to before accessing the Data read-only memory window area for the first time. Bit 5:0 = DRWR[5:0] Data read-only memory Window Register Bits. These are the Data read-only memory Window bits that correspond to the upper bits of the data read-only memory space. Caution: This register is undefined on reset, it is write-only, therefore do not read it nor access it using Read-Modify-Write instructions (SET, RES, INC and DEC). 0FFh Doc ID 4563 Rev 5 ST6200C ST6201C ST6203C MEMORY MAP (Cont’d) 3.1.6.2 Data ROM Window memory addressing In cases where some data (look-up tables for example) are stored in program memory, reading these data requires the use of the Data ROM window mechanism. To do this: 1. The DRWR register has to be loaded with the 64-byte block number where the data are located (in program memory). This number also gives the start address of the block. 2. Then, the offset address of the byte in the Data ROM Window (corresponding to the offset in the 64-byte block in program memory) has to be loaded in a register (A, X,...). When the above two steps are completed, the data can be read. To understand how to determine the DRWR and the content of the register, please refer to the example shown in Figure 6. In any case the calcula- tion is automatically handled by the ST6 development tools. Please refer to the user manual of the correspoding tool. 3.1.6.3 Recommendations Care is required when handling the DRWR register as it is write only. For this reason, the DRWR contents should not be changed while executing an interrupt service routine, as the service routine cannot save and then restore the register’s previous contents. If it is impossible to avoid writing to the DRWR during the interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to the DRWR, it must also write to the image register. The image register must be written first so that, if an interrupt occurs between the two instructions, the DRWR is not affected. Figure 6. Data ROM Window Memory Addressing DATA SPACE 000h PROGRAM SPACE 0000h 040h DATA 061h OFFSET 21h 07Fh 0400h OFFSET 0421h 64 bytes DATA 10h DRWR 0FFh 07FFh DATA address in Program memory : 421h DRWR content : 421h / 3Fh (64) = 10H data is located in 64-bytes window number 10h 64-byte window start address : 10h x 3Fh = 400h Register (A, X,...)content : Offset = (421h - 400h) + 40h ( Data ROM Window start address in data space) = 61h Doc ID 4563 Rev 5 13/100 1 ST6200C ST6201C ST6203C 3.2 PROGRAMMING MODES 3.2.1 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/VPP pin. The programming flow of the ST62T00C, T01/E01C and T03C is described in the User Manual of the EPROM Programming Board. Table 3. ST6200C/03C Program Memory Map Device Address Description 0000h-0B9Fh 0BA0h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh Reserved User ROM Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector Table 4. ST6201C Program Memory Map Device Address Description 0000h-087Fh 0880h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh Reserved User ROM Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector 14/100 1 Note: OTP/EPROM devices can be programmed with the development tools available from STMicroelectronics (please refer to Section 12 on page 95). 3.2.2 EPROM Erasing The EPROM devices can be erased by exposure to Ultra Violet light. The characteristics of the MCU are such that erasure begins when the memory is exposed to light with a wave lengths shorter than approximately 4000Å. It should be noted that sunlight and some types of fluorescent lamps have wavelengths in the range 3000-4000Å. It is thus recommended that the window of the MCU packages be covered by an opaque label to prevent unintentional erasure problems when testing the application in such an environment. The recommended erasure procedure is exposure to short wave ultraviolet light which have a wavelength 2537Å. The integrated dose (i.e. U.V. intensity x exposure time) for erasure should be a minimum of 30W-sec/cm2. The erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet lamp with 12000µW/cm2 power rating. The EPROM device should be placed within 2.5cm (1inch) of the lamp tubes during erasure. Doc ID 4563 Rev 5 ST6200C ST6201C ST6203C 3.3 OPTION BYTES Each device is available for production in user programmable versions (OTP) as well as in factory coded versions (ROM). OTP devices are shipped to customers with a default content (00h), while ROM factory coded parts contain the code supplied by the customer. This implies that OTP devices have to be configured by the customer using the Option Bytes while the ROM devices are factory-configured. The two option bytes allow the hardware configuration of the microcontroller to be selected. The option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard ST6 programming tool). In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see Section 11.6.2 "ROM VERSION" on page 93). It is therefore impossible to read the option bytes. The option bytes can be only programmed once. It is not possible to change the selected options after they have been programmed. In order to reach the power consumption value indicated in Section 10.4, the option byte must be programmed to its default value. Otherwise, an over-consumption will occur. 0: Low Voltage Detector disabled 1: Low Voltage Detector enabled. MSB OPTION BYTE Bits 15:11 = Reserved, must be always cleared. Bit 2 = Reserved, must be always set. LSB OPTION BYTE Bit 7 = PROTECT Readout Protection. This option bit enables or disables external access to the internal program memory. 0: Program memory not read-out protected 1: Program memory read-out protected Bit 6 = OSC Oscillator selection. This option bit selects the main oscillator type. 0: Quartz crystal, ceramic resonator or external clock 1: RC network Bit 5 = Reserved, must be always cleared. Bit 4 = Reserved, must be always set. Bit 3 = NMI PULL NMI Pull-Up on/off. This option bit enables or disables the internal pullup on the NMI pin. 0: Pull-up disabled 1: Pull-up enabled Bit 1 = WDACT Hardware or software watchdog. This option bit selects the watchdog type. 0: Software (watchdog to be enabled by software) 1: Hardware (watchdog always enabled) Bit 10 = Reserved, must be always set. Bit 9 = EXTCNTL External STOP MODE control. 0: EXTCNTL mode not available. STOP mode is not available with the watchdog active. 1: EXTCNTL mode available. STOP mode is available with the watchdog active by setting NMI pin to one. Bit 0 = OSGEN Oscillator Safeguard on/off. This option bit enables or disables the oscillator Safeguard (OSG) feature. 0: Oscillator Safeguard disabled 1: Oscillator Safeguard enabled Bit 8 = LVD Low Voltage Detector on/off. This option bit enable or disable the Low Voltage Detector (LVD) feature. MSB OPTION BYTE LSB OPTION BYTE 15 8 EXT CTL Reserved Default Value X X X X X X X 7 0 PRONMI LVD OSC Res. Res. TECT PULL X X Doc ID 4563 Rev 5 X X X X Res. WD ACT OSG EN X X X 15/100 1 ST6200C ST6201C ST6203C 4 CENTRAL PROCESSING UNIT 4.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses. 4.2 MAIN FEATURES ■ ■ ■ ■ ■ ■ ■ 40 basic instructions 9 main addressing modes Two 8-bit index registers Two 8-bit short direct registers Low power modes Maskable hardware interrupts 6-level hardware stack 4.3 CPU REGISTERS The ST6 Family CPU core features six registers and three pairs of flags available to the programmer. These are described in the following paragraphs. Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipula- tions. The accumulator can be addressed in Data Space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data Space. Index Registers (X, Y). These two registers are used in Indirect addressing mode as pointers to memory locations in Data Space. They can also be accessed in Direct, Short Direct, or Bit Direct addressing modes. They are mapped in Data Space at addresses 80h (X) and 81h (Y) and can be accessed like any other memory location. Short Direct Registers (V, W). These two registers are used in Short Direct addressing mode. This means that the data stored in V or W can be accessed with a one-byte instruction (four CPU cycles). V and W can also be accessed using Direct and Bit Direct addressing modes. They are mapped in Data Space at addresses 82h (V) and 83h (W) and can be accessed like any other memory location. Note: The X and Y registers can also be used as Short Direct registers in the same way as V and W. Program Counter (PC). The program counter is a 12-bit register which contains the address of the next instruction to be executed by the core. This ROM location may be an opcode, an operand, or the address of an operand. Figure 7. CPU Registers 7 0 ACCUMULATOR SIX LEVEL STACK RESET VALUE = xxh 7 0 X INDEX REGISTER RESET VALUE = xxh 7 0 NORMAL FLAGS CN ZN INTERRUPT FLAGS CI ZI Y INDEX REGISTER RESET VALUE = xxh 7 0 V SHORT INDIRECT REGISTER NMI FLAGS CNMI ZNMI RESET VALUE = xxh 7 0 W SHORT INDIRECT REGISTER RESET VALUE = xxh 11 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ 0FFEh-0FFFh 16/100 1 Doc ID 4563 Rev 5 x = Undefined value ST6200C ST6201C ST6203C CPU REGISTERS (Cont’d) The 12-bit length allows the direct addressing of 4096 bytes in Program Space. However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program ROM Page register. The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC. The program counter can be changed in the following ways: – JP (Jump) instruction PC = Jump address – CALL instruction PC = Call address – Relative Branch InstructionPC = PC +/- offset – Interrupt PC = Interrupt vector – Reset PC = Reset vector – RET & RETI instructions PC = Pop (stack) – Normal instruction PC = PC + 1 Flags (C, Z). The ST6 CPU includes three pairs of flags (Carry and Zero), each pair being associated with one of the three normal modes of operation: Normal mode, Interrupt mode and Non Maskable Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used in the Non Maskable Interrupt mode (CNMI, ZNMI). The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6 CPU uses the Interrupt flags (or the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context switching and thus retain their status. C : Carry flag. This bit is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction; it also participates in the rotate left instruction. 0: No carry has occured 1: A carry has occured Z : Zero flag This flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared. 0: The result of the last operation is different from zero 1: The result of the last operation is zero Switching between the three sets of flags is performed automatically when an NMI, an interrupt or a RETI instruction occurs. As NMI mode is automatically selected after the reset of the MCU, the ST6 core uses the NMI flags first. Stack. The ST6 CPU includes a true LIFO (Last In First Out) hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are shifted into the next level down, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level. Figure 8. Stack manipulation PROGRAM COUNTER ON RETURN FROM INTERRUPT, OR SUBROUTINE LEVEL 1 LEVEL 2 ON INTERRUPT, OR SUBROUTINE CALL LEVEL 3 LEVEL 4 LEVEL 5 LEVEL 6 Since the accumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. Caution: The stack will remain in its “deepest” position if more than 6 nested calls or interrupts are executed, and consequently the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed. Doc ID 4563 Rev 5 17/100 1 ST6200C ST6201C ST6203C 5 CLOCKS, SUPPLY AND RESET 5.1 CLOCK SYSTEM The main oscillator of the MCU can be driven by any of these clock sources: – external clock signal – external AT-cut parallel-resonant crystal – external ceramic resonator – external RC network (RNET). In addition, an on-chip Low Frequency Auxiliary Oscillator (LFAO) is available as a back-up clock system or to reduce power consumption. An optional Oscillator Safeguard (OSG) filters spikes from the oscillator lines, and switches to the LFAO backup oscillator in the event of main oscillator failure. It also automatically limits the internal clock frequency (fINT) as a function of VDD, in order to guarantee correct operation. These functions are illustrated in Figure 10, and Figure 11. Table 5 illustrates various possible oscillator configurations using an external crystal or ceramic resonator, an external clock input, an external resistor (RNET), or the lowest cost solution using only the LFAO. For more details on configuring the clock options, refer to the Option Bytes section of this document. The internal MCU clock frequency (fINT) is divided by 12 to drive the Timer, the Watchdog timer and the A/D converter, by 13 to drive the CPU core and the SPI and by 1 or 3 to drive the ARTIMER, as shown in Figure 9. With an 8 MHz oscillator, the fastest CPU cycle is therefore 1.625µs. A CPU cycle is the smallest unit of time needed to execute any operation (for instance, to increment the Program Counter). An instruction may require two, four, or five CPU cycles for execution. Figure 9. Clock Circuit Block Diagram OSCILLATOR SAFEGUARD (OSG) SPI fOSC : 13 OSG filtering CORE 8-BIT TIMER 0 Oscillator MAIN OSCILLATOR Divider fINT : 12 WATCHDOG 1 ADC * LFAO OSCOFF BIT * (ADCR REGISTER) :1 8-BIT ARTIMER :3 8-BIT ARTIMER OSG ENABLE OPTION BIT (See OPTION BYTE SECTION) * Depending on device. See device summary on page 1. 18/100 1 Doc ID 4563 Rev 5 ST6200C ST6201C ST6203C Table 5. Oscillator Configurations Crystal/Resonator Option1) Crystal/Resonator Option1) Hardware Configuration External Clock ST6 OSCin OSCout NC EXTERNAL CLOCK Crystal/Resonator Clock 2) ST6 OSCin CL1 OSCout LOAD CAPACITORS 3) CL2 RC Network Option1) RC Network OSG Enabled Option1) CLOCK SYSTEM (Cont’d) 5.1.1 Main Oscillator The oscillator configuration is specified by selecting the appropriate option in the option bytes (refer to the Option Bytes section of this document). When the CRYSTAL/RESONATOR option is selected, it must be used with a quartz crystal, a ceramic resonator or an external signal provided on the OSCin pin. When the RC NETWORK option is selected, the system clock is generated by an external resistor (the capacitor is implemented internally). The main oscillator can be turned off (when the OSG ENABLED option is selected) by setting the OSCOFF bit of the ADC Control Register (not available on some devices). This will automatically start the Low Frequency Auxiliary Oscillator (LFAO). The main oscillator can be turned off by resetting the OSCOFF bit of the A/D Converter Control Register or by resetting the MCU. When the main oscillator starts there is a delay made up of the oscillator start-up delay period plus the duration of the software instruction at a clock frequency fLFAO. Caution: It should be noted that when the RC network option is selected, the accuracy of the frequency is about 20% so it may not be suitable for some applications (For more details, please refer to the Electrical Characteristics Section). ST6 OSCin OSCout NC RNET LFAO ST6 OSCin OSCout NC Notes: 1. To select the options shown in column 1 of the above table, refer to the Option Byte section. 2.This schematic are given for guidance only and are subject to the schematics given by the crystal or ceramic resonator manufacturer. 3. For more details, please refer to the Electrical Characteristics Section. Doc ID 4563 Rev 5 19/100 1 ST6200C ST6201C ST6203C CLOCK SYSTEM (Cont’d) 5.1.2 Oscillator Safeguard (OSG) The Oscillator Safeguard (OSG) feature is a means of dramatically improving the operational integrity of the MCU. It is available when the OSG ENABLED option is selected in the option byte (refer to the Option Bytes section of this document). The OSG acts as a filter whose cross-over frequency is device dependent and provides three basic functions: – Filtering spikes on the oscillator lines which would result in driving the CPU at excessive frequencies – Management of the Low Frequency Auxiliary Oscillator (LFAO), (useable as low cost internal clock source, backup clock in case of main oscillator failure or for low power consumption) – Automatically limiting the fINT clock frequency as a function of supply voltage, to ensure correct operation even if the power supply drops. 5.1.2.1 Spike Filtering Spikes on the oscillator lines result in an effectively increased internal clock frequency. In the absence of an OSG circuit, this may lead to an over frequency for a given power supply voltage. The OSG filters out such spikes (as illustrated in Figure 10). In all cases, when the OSG is active, the max- imum internal clock frequency, fINT, is limited to fOSG, which is supply voltage dependent. 5.1.2.2 Management of Supply Voltage Variations Over-frequency, at a given power supply level, is seen by the OSG as spikes; it therefore filters out some cycles in order that the internal clock frequency of the device is kept within the range the particular device can stand (depending on VDD), and below fOSG: the maximum authorised frequency with OSG enabled. 5.1.2.3 LFAO Management When the OSG is enabled, the Low Frequency Auxiliary Oscillator can be used (see Section 5.1.3). Note: The OSG should be used wherever possible as it provides maximum security for the application. It should be noted however, that it can increase power consumption and reduce the maximum operating frequency to fOSG (see Electrical Characteristics section). Caution: Care has to be taken when using the OSG, as the internal frequency is defined between a minimum and a maximum value and may vary depending on both VDD and temperature. For precise timing measurements, it is not recommended to use the OSG. Figure 10. OSG Filtering Function fOSC>fOSG fOSCVDD while a negative injection is induced by VIN