ST6215C ST6225C
8-bit MCUs with A/D converter,
two timers, oscillator safeguard & safe reset
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Memories
– 2K or 4K bytes Program memory (OTP,
EPROM, FASTROM or ROM) with read-out
protection
– 64 bytes RAM
Clock, Reset and Supply Management
– Enhanced reset system
– Low Voltage Detector (LVD) for Safe Reset
– Clock sources: crystal/ceramic resonator or
RC network, external clock, backup oscillator
(LFAO)
– Oscillator Safeguard (OSG)
– 2 Power Saving Modes: Wait and Stop
Interrupt Management
– 4 interrupt vectors plus NMI and RESET
– 20 external interrupt lines (on 2 vectors)
– 1 external non-interrupt line
20 I/O Ports
– 20 multifunctional bidirectional I/O lines
– 16 alternate function lines
– 4 high sink outputs (20mA)
2 Timers
– Configurable watchdog timer
– 8-bit timer/counter with a 7-bit prescaler
Analog Peripheral
– 8-bit ADC with 16 input channels
Instruction Set
– 8-bit data manipulation
– 40 basic instructions
– 9 addressing modes
– Bit manipulation
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SS0P28
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CDIP28W
(See Section 12.5 for Ordering Information)
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Development Tools
– Full hardware/software development package
Device Summary
Features
Program memory - bytes
RAM - bytes
Operating Supply
Clock Frequency
Operating Temperature
Packages
January 2009
ST6215C
ST6225C
2K
4K
64
3.0V to 6V
8MHz Max
-40°C to +125°C
PDIP28 / SO28 / SSOP28
Rev 4
1/105
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Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . 9
3.1 MEMORY AND REGISTER MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.3 Readout Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.4 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.5 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.6 Data ROM Window Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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3.2.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3
CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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5 CLOCKS, SUPPLY AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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5.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Oscillator Safeguard (OSG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 INTERRUPT RULES AND PRIORITY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2
INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3
NON MASKABLE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4
PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.5
EXTERNAL INTERRUPTS (I/O PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.5.1 Notes on using External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.6 INTERRUPT HANDLING PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.6.1 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7
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7.2
WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.3
STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4
NOTES RELATED TO WAIT AND STOP MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.4.1 Exit from Wait and Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.4.2 Recommended MCU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2.1 Digital Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2.2 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2.3 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2.4 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2.5 Instructions NOT to be used to access Port Data registers (SET, RES, INC and DEC) 40
8.2.6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.3 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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8.4
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.5
REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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9 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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9.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.4 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2 8-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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9.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.3 Counter/Prescaler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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10 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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10.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.1.1Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.2Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.3Typical Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.4Loading Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.5Pin Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11.2.1Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.2Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.3Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11.3.1General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.3.2Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . 66
11.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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11.4.1RUN Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.2WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.3STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.4Supply and Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.5On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11.5.1General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5.2External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5.3Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5.4RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5.5Oscillator Safeguard (OSG) and Low Frequency Auxiliary Oscillator (LFAO) . . . . .
11.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11.6.1RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
11.6.2EPROM Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
11.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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11.7.1Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.7.2Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.7.3ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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79
81
82
11.8.1General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.8.2Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.9.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.9.2NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.10.28-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
12 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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88
89
91
91
Table of Contents
12.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.3 ECOPACK INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.6 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.6.1FASTROM Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.6.2ROM Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
13 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
14 ST6 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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15 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
16 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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ST6215C ST6225C
1 INTRODUCTION
The ST6215C, 25C devices are low cost members
of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity
applications. All ST62xx devices are based on a
building block approach: a common core is surrounded by a number of on-chip peripherals.
The ST62E25C is the erasable EPROM version of
the ST62T15C, T25C devices, which may be used
during the development phase for the ST62T15C,
T25C target devices, as well as the respective
ST6215C, 25C ROM devices.
OTP and EPROM devices are functionally identical. OTP devices offer all the advantages of user
programmability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
The ROM based versions offer the same functionality, selecting the options defined in the programFigure 1. Block Diagram
8-BIT
A/D CONVERTER
)
(s
VPP
NMI
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INTERRUPTS
od
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PROGRAM
:
MEMORY
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e
For easy reference, all parametric data is located
in Section 11 on page 63.
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PORT A
PA0..PA3 (20mA Sink)
PA4..PA7 / Ain
PORT B
PB0..PB7 / Ain
PORT C
PC4..PC7 / Ain
TIMER
WATCHDOG
TIMER
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
POWER
SUPPLY
VDD VSS
4
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DATA RAM
64 Bytes
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These compact low-cost devices feature a Timer
comprising an 8-bit counter with a 7-bit programmable prescaler, an 8-bit A/D Converter with 16
analog inputs and a Digital Watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications.
DATA ROM
USER
SELECTABLE
(2K or 4K Bytes)
O
mable option bytes of the OTP/EPROM versions
in the ROM option list (See Section 12.6 on page
97).
The ST62P15C/P25C are the Factory Advanced
Service Technique ROM (FASTROM) versions of
ST62T15C,T25C OTP devices.
They offer the same functionality as OTP devices,
but they do not have to be programmed by the
customer (See Section 12 on page 91).
8-BIT CORE
OSCILLATOR
RESET
OSCin OSCout
RESET
TIMER
ST6215C ST6225C
2 PIN DESCRIPTION
Figure 2. 28-Pin Package Pinout
VDD
1
28
VSS
TIMER
OSCin
2
27
3
26
PA0/20mA Sink
PA1/20mA Sink
OSCout
4
25
PA2/20mA Sink
NMI
5
24
PA3/20mA Sink
Ain/PC7
6
23
PA4/Ain
Ain/PC6
7
22
PA5/Ain
8
21
PA6/Ain
Ain/PC4
9
20
PA7/Ain
VPP
RESET
10
19
PB0/Ain
PB1/Ain
Ain/PB7
Ain/PB6
12
Ain/PB5
14
1
VDD
2
TIMER
let
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S
I/O
18
11
13
it2
17
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PB2/Ain
PB3/Ain
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it2
15
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Type
Pin Name
it2
Ain/PC5
Table 1. Device Pin Description
Pin n°
it1
PB4/Ain
itX associated interrupt vector
Main Function
(after Reset)
Alternate Function
Main power supply
Timer input or output
OSCin
I
External clock input or resonator oscillator inverter input
4
OSCout
O
Resonator oscillator inverter output or resistor input for RC oscillator
5
NMI
I
Non maskable interrupt (falling edge sensitive)
6
PC7/Ain
I/O
Pin C7 (IPU)
Analog input
7
PC6/Ain
I/O
Pin C6 (IPU)
Analog input
8
PC5/Ain
I/O
Pin C5 (IPU)
Analog input
9
PC4/Ain
I/O
Pin C4 (IPU)
Analog input
10
VPP
11
RESET
I/O
Top priority non maskable interrupt (active low)
12
PB7/Ain
I/O
Pin B7 (IPU)
Analog input
13
PB6/Ain
I/O
Pin B6 (IPU)
Analog input
b
O
Must be held at Vss for normal operation, if a 12.5V level is applied to the pin
during the reset phase, the device enters EPROM programming mode.
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5
Pin n°
Pin Name
Type
ST6215C ST6225C
Main Function
(after Reset)
Alternate Function
14
PB5/Ain
I/O
Pin B5 (IPU)
Analog input
15
PB4/Ain
I/O
Pin B4 (IPU)
Analog input
16
PB3/Ain
I/O
Pin B3 (IPU)
Analog input
17
PB2/Ain
I/O
Pin B2 (IPU)
Analog input
18
PB1/Ain
I/O
Pin B1 (IPU)
Analog input
19
PB0/Ain
I/O
Pin B0 (IPU)
Analog input
20
PA7/Ain
I/O
Pin A7 (IPU)
Analog input
21
PA6/Ain
I/O
Pin A6 (IPU)
Analog input
22
PA5/Ain
I/O
Pin A5 (IPU)
23
PA4/Ain
I/O
Pin A4 (IPU)
24
PA3/ 20mA Sink
I/O
Pin A3 (IPU)
25
PA2/ 20mA Sink
I/O
Pin A2 (IPU)
26
PA1/ 20mA Sink
I/O
Pin A1 (IPU)
27
PA0/ 20mA Sink
I/O
Pin A0 (IPU)
28
VSS
S
)
(s
Ground
)
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Analog input
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Pr
Analog input
s
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O
Legend / Abbreviations for Table 1:
I = input, O = output, S = supply, IPU = input pull-up
The input with pull-up configuration (reset state) is valid as long as the user software does not change it.
Refer to Section 8 "I/O PORTS" on page 38 for more details on the software configuration of the I/O ports.
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ST6215C ST6225C
3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES
3.1 MEMORY AND REGISTER MAPS
3.1.1 Introduction
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.
Briefly, Program space contains user program
code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack
space accommodates six levels of stack for subroutine and interrupt service routine nesting.
Figure 3. Memory Addressing Diagram
PROGRAM SPACE
DATA SPACE
000h
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RESERVED
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PROGRAM
MEMORY
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(see Figure 4
on page 10)
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03Fh
040h
07Fh
080h
081h
082h
083h
084h
b
O
so
0FFFh
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
RAM
0BFh
0C0h
0FF0h
let
DATA READ-ONLY
MEMORY WINDOW
INTERRUPT &
RESET VECTORS
0FFh
HARDWARE
CONTROL
REGISTERS
(see Table 2)
ACCUMULATOR
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ST6215C ST6225C
MEMORY MAP (Cont’d)
Figure 4. Program Memory Map
ST6215C
ST6225C
0000h
0000h
RESERVED*
07Fh
080h
NOT IMPLEMENTED
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07FFh
0800h
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RESERVED*
087Fh
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0880h
USER
PROGRAM MEMORY
1824 BYTES
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
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RESERVED*
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INTERRUPT VECTORS
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)
(s
RESERVED*
NMI VECTOR
USER RESET VECTOR
(*) Reserved areas should be filled with 0FFh
10/105
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0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
USER
PROGRAM MEMORY
3872 BYTES
RESERVED*
INTERRUPT VECTORS
RESERVED*
NMI VECTOR
USER RESET VECTOR
ST6215C ST6225C
MEMORY MAP (Cont’d)
3.1.2 Program Space
Program Space comprises the instructions to be
executed, the data required for immediate addressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register). Thus, the MCU is capable of addressing 4K bytes of memory directly.
3.1.3 Readout Protection
The Program Memory in OTP or EPROM devices
can be protected against external readout of memory by setting the Readout Protection bit in the option byte (Section 3.3 on page 16).
In the EPROM parts, Readout Protection option
can be desactivated only by U.V. erasure that also
results in the whole EPROM context being erased.
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the OTP contents. Returned
parts can therefore not be accepted if the Readout
Protection bit is set.
3.1.4 Data Space
Data Space accommodates all the data necessary
for processing the user program. This space comprises the RAM resource, the processor core and
peripheral registers, as well as read-only data
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(s
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such as constants and look-up tables in OTP/
EPROM.
3.1.4.1 Data ROM
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently contains the program code to be executed, as well as
the constants and look-up tables required by the
application.
The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in OTP/EPROM.
3.1.4.2 Data RAM
The data space includes the user RAM area, the
accumulator (A), the indirect registers (X), (Y), the
short direct registers (V), (W), the I/O port registers, the peripheral data and control registers, the
interrupt option register and the Data ROM Window register (DRWR register).
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3.1.5 Stack Space
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
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ST6215C ST6225C
MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Address
Block
080h
to 083h
CPU
0C0h
0C1h
0C2h
Register
Label
I/O Ports
X,Y index registers
V,W short direct registers
xxh
R/W
DRA 1) 2) 3)
DRB 1) 2) 3)
DRC 1) 2) 3)
Port A Data Register
Port B Data Register
Port C Data Register
00h
00h
00h
R/W
R/W
R/W
00h
00h
00h
)
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ct
xxh
Write-only
xxh
Write-only
00h
00h
00h
R/W
R/W
R/W
A/D Converter Data Register
A/D Converter Control Register
xxh
40h
Read-only
Ro/Wo
Timer 1 Prescaler Register
Timer 1 Counter Register
Timer 1 Status Control Register
7Fh
0FFh
Reserved (1 Byte)
0C4h
0C5h
0C6h
I/O Ports
DDRA 2)
DDRB 2)
DDRC 2)
Port A Direction Register
Port B Direction Register
Port C Direction Register
0C7h
CPU
IOR
Interrupt Option Register
0C9h
ROM
DRWR
Data ROM Window register
I/O Ports
ORA 2)
ORB 2)
ORC 2)
Port A Option Register
Port B Option Register
Port C Option Register
0D0h
0D1h
ADC
0D2h
0D3h
0D4h
Timer1
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ADR
ADCR
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Watchdog
Timer
PSCR
TCR
TSCR
O
)
s
(
t
c
0CFh
Reserved (1 byte)
00h
R/W
R/W
R/W
0FEh
R/W
xxh
R/W
Reserved (3 Bytes)
WDGR
0D9h
to 0FEh
0FFh
R/W
R/W
R/W
Reserved (2 Bytes)
0CCh
0CDh
0CEh
0D8h
let
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b
0CAh
0CBh
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Reserved (1 Byte)
0C8h
b
O
Remarks
X,Y,V,W
0C3h
0D5h
to 0D7h
Reset
Status
Register Name
Watchdog Register
Reserved (38 Bytes)
CPU
A
Accumulator
Legend:
x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s)
in the register.
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured
in input mode (refer to Section 8 "I/O PORTS" on page 38 for more details).
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ST6215C ST6225C
MEMORY MAP (Cont’d)
3.1.6 Data ROM Window Mechanism
The Data read-only memory window is located
from address 0040h to address 007Fh in Data
space. It allows direct reading of 64 consecutive
bytes located anywhere in program memory, between address 0000h and 0FFFh.
There are 64 blocks of 64 bytes in a 4K device:
– Block 0 is related to the address range 0000h to
003Fh.
– Block 1 is related to the address range 0040h to
007Fh.
and so on...
All the program memory can therefore be used to
store either instructions or read-only data. The
Data ROM window can be moved in steps of 64
bytes along the program memory by writing the
appropriate code in the Data ROM Window Register (DRWR).
Address: 0C9h — Write Only
Reset Value = xxh (undefined)
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DRWR5 DRWR4 DRWR3 DRWR2 DRWR1 DRWR0
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Bits 7:6 = Reserved, must be cleared.
Figure 5. Data ROM Window
PROGRAM
0000h SPACE
3.1.6.1 Data ROM Window Register (DRWR)
The DRWR can be addressed like any RAM location in the Data Space.
This register is used to select the 64-byte block of
program memory to be read in the Data ROM window (from address 40h to address 7Fh in Data
space). The DRWR register is not cleared on reset, therefore it must be written to before accessing the Data read-only memory window area for
the first time.
000h DATA SPACE
)
(s
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c
u
040h
DATA ROM
64-BYTE
ROM 07Fh WINDOW
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Bits 5:0 = DRWR[5:0] Data read-only memory
Window Register Bits. These are the Data readonly memory Window bits that correspond to the
upper bits of the data read-only memory space.
Caution: This register is undefined on reset, it is
write-only, therefore do not read it nor access it using Read-Modify-Write instructions (SET, RES,
INC and DEC).
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0FFFh
0FFh
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ST6215C ST6225C
MEMORY MAP (Cont’d)
3.1.6.2 Data ROM Window memory addressing
In cases where some data (look-up tables for example) are stored in program memory, reading
these data requires the use of the Data ROM window mechanism. To do this:
1. The DRWR register has to be loaded with the
64-byte block number where the data are located
(in program memory). This number also gives the
start address of the block.
2. Then, the offset address of the byte in the Data
ROM Window (corresponding to the offset in the
64-byte block in program memory) has to be loaded in a register (A, X,...).
When the above two steps are completed, the
data can be read.
To understand how to determine the DRWR and
the content of the register, please refer to the example shown in Figure 6. In any case the calcula-
tion is automatically handled by the ST6 development tools.
Please refer to the user manual of the correspoding tool.
3.1.6.3 Recommendations
Care is required when handling the DRWR register as it is write only. For this reason, the DRWR
contents should not be changed while executing
an interrupt service routine, as the service routine
cannot save and then restore the register’s previous contents. If it is impossible to avoid writing to
the DRWR during the interrupt service routine, an
image of the register must be saved in a RAM location, and each time the program writes to the
DRWR, it must also write to the image register.
The image register must be written first so that, if
an interrupt occurs between the two instructions,
the DRWR is not affected.
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Figure 6. Data read-only memory Window Memory Addressing
bs
PROGRAM SPACE
r
P
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DATA SPACE
000h
O
)
0000h
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040h
DATA
061h
OFFSET
21h
07Fh
0400h
bs
OFFSET
O
0421h
64 bytes
DATA
10h
DRWR
0FFh
07FFh
DATA address in Program memory : 421h
DRWR content : 421h / 3Fh (64) = 10H data is located in 64-bytes window number 10h
64-byte window start address : 10h x 3Fh = 400h
Register (A, X,...)content : Offset = (421h - 400h) + 40h ( Data ROM Window start address in data space) = 61h
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ST6215C ST6225C
3.2 PROGRAMMING MODES
3.2.1 Program Memory
EPROM/OTP programming mode is set by a
+12.5V voltage applied to the TEST/VPP pin. The
programming flow of the ST62T15C,T25C/E25C is
described in the User Manual of the EPROM Programming Board.
Table 3. ST6215C Program Memory Map
Device Address
Description
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Table 4. ST6225C Program Memory Map
Device Address
Description
0000h-007Fh
0080h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
)
(s
Note: OTP/EPROM devices can be programmed
with the development tools available from
STMicroelectronics (please refer to Section 13 on
page 100).
3.2.2 EPROM Erasing
The EPROM devices can be erased by exposure
to Ultra Violet light. The characteristics of the MCU
are such that erasure begins when the memory is
exposed to light with a wave lengths shorter than
approximately 4000Å. It should be noted that sunlight and some types of fluorescent lamps have
wavelengths in the range 3000-4000Å.
It is thus recommended that the window of the
MCU packages be covered by an opaque label to
prevent unintentional erasure problems when testing the application in such an environment.
The recommended erasure procedure is exposure
to short wave ultraviolet light which have a wavelength 2537Å. The integrated dose (i.e. U.V. intensity x exposure time) for erasure should be a minimum of 30W-sec/cm2. The erasure time with this
dosage is approximately 30 to 40 minutes using an
ultraviolet lamp with 12000µW/cm2 power rating.
The EPROM device should be placed within
2.5cm (1inch) of the lamp tubes during erasure.
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ST6215C ST6225C
3.3 OPTION BYTES
Each device is available for production in user programmable versions (OTP) as well as in factory
coded versions (ROM). OTP devices are shipped
to customers with a default content (00h), while
ROM factory coded parts contain the code supplied by the customer. This implies that OTP devices have to be configured by the customer using
the Option Bytes while the ROM devices are factory-configured.
The two option bytes allow the hardware configuration of the microcontroller to be selected.
The option bytes have no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST6 programming tool).
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see Section
12.6.2 "ROM Version" on page 98). It is therefore
impossible to read the option bytes.
The option bytes can be only programmed once. It
is not possible to change the selected options after
they have been programmed.
In order to reach the power consumption value indicated in Section 11.4, the option byte must be
programmed to its default value. Otherwise, an
over-consumption will occur.
)
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0: Low Voltage Detector disabled
1: Low Voltage Detector enabled.
LSB OPTION BYTE
Bit 7 = PROTECT Readout Protection.
This option bit enables or disables external access
to the internal program memory.
0: Program memory not read-out protected
1: Program memory read-out protected
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Bit 6 = OSC Oscillator selection.
This option bit selects the main oscillator type.
0: Quartz crystal, ceramic resonator or external
clock
1: RC network
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Bits 5:4 = Reserved, must be always cleared.
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Bit 3 = NMI PULL NMI Pull-Up on/off.
This option bit enables or disables the internal pullup on the NMI pin.
0: Pull-up disabled
1: Pull-up enabled
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Bit 2 = TIM PULL TIMER Pull-Up on/off.
This option bit enables or disables the internal pullup on the TIMER pin.
0: Pull-up disabled
1: Pull-up enabled
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MSB OPTION BYTE
Bits 15:10 = Reserved, must be always cleared.
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Bit 9 = EXTCNTL External STOP MODE control.
0: EXTCNTL mode not available. STOP mode is
not available with the watchdog active.
1: EXTCNTL mode available. STOP mode is available with the watchdog active by setting NMI pin
to one.
P
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Bit 1 = WDACT Hardware or software watchdog.
This option bit selects the watchdog type.
0: Software (watchdog to be enabled by software)
1: Hardware (watchdog always enabled)
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Bit 0 = OSGEN Oscillator Safeguard on/off.
This option bit enables or disables the oscillator
Safeguard (OSG) feature.
0: Oscillator Safeguard disabled
1: Oscillator Safeguard enabled
Bit 8 = LVD Low Voltage Detector on/off.
This option bit enable or disable the Low Voltage
Detector (LVD) feature.
MSB OPTION BYTE
LSB OPTION BYTE
15
8
EXT
CTL
Reserved
Default
Value
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X
X
X
X
X
X
X
7
0
PRONMI
TIM
LVD
OSC Res. Res.
TECT
PULL PULL
X
X
X
X
X
X
X
WD
ACT
OSG
EN
X
X
ST6215C ST6225C
4 CENTRAL PROCESSING UNIT
4.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control
buses.
4.2 MAIN FEATURES
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40 basic instructions
9 main addressing modes
Two 8-bit index registers
Two 8-bit short direct registers
Low power modes
Maskable hardware interrupts
6-level hardware stack
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4.3 CPU REGISTERS
The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic calculations, logical operations, and data manipula-
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Figure 7. CPU Registers
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7
tions. The accumulator can be addressed in Data
Space as a RAM location at address FFh. Thus
the ST6 can manipulate the accumulator just like
any other register in Data Space.
Index Registers (X, Y). These two registers are
used in Indirect addressing mode as pointers to
memory locations in Data Space. They can also
be accessed in Direct, Short Direct, or Bit Direct
addressing modes. They are mapped in Data
Space at addresses 80h (X) and 81h (Y) and can
be accessed like any other memory location.
Short Direct Registers (V, W). These two registers are used in Short Direct addressing mode.
This means that the data stored in V or W can be
accessed with a one-byte instruction (four CPU cycles). V and W can also be accessed using Direct
and Bit Direct addressing modes. They are
mapped in Data Space at addresses 82h (V) and
83h (W) and can be accessed like any other memory location.
Note: The X and Y registers can also be used as
Short Direct registers in the same way as V and W.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next instruction to be executed by the core. This
ROM location may be an opcode, an operand, or
the address of an operand.
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0
ACCUMULATOR
SIX LEVEL
STACK
RESET VALUE = xxh
7
0
X INDEX REGISTER
RESET VALUE = xxh
7
0
NORMAL FLAGS
CN
ZN
INTERRUPT FLAGS
CI
ZI
Y INDEX REGISTER
RESET VALUE = xxh
7
0
V SHORT INDIRECT
REGISTER
NMI FLAGS
CNMI ZNMI
RESET VALUE = xxh
7
0
W SHORT INDIRECT
REGISTER
RESET VALUE = xxh
11
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ 0FFEh-0FFFh
x = Undefined value
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ST6215C ST6225C
CPU REGISTERS (Cont’d)
The 12-bit length allows the direct addressing of
4096 bytes in Program Space.
However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
ROM Page register.
The PC value is incremented after reading the address of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted back into the PC. The program counter can
be changed in the following ways:
– JP (Jump) instruction
PC = Jump address
– CALL instruction
PC = Call address
– Relative Branch InstructionPC = PC +/- offset
– Interrupt
PC = Interrupt vector
– Reset
PC = Reset vector
– RET & RETI instructions PC = Pop (stack)
– Normal instruction
PC = PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNMI, ZNMI).
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (or the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is
restored. It should be noted that each flag set can
only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main routine).
The flags are not cleared during context switching
and thus retain their status.
C : Carry flag.
This bit is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared.
The Carry flag is also set to the value of the bit
tested in a bit test instruction; it also participates in
the rotate left instruction.
0: No carry has occured
1: A carry has occured
)-
Z : Zero flag
This flag is set if the result of the last arithmetic or
logical operation was equal to zero; otherwise it is
cleared.
0: The result of the last operation is different from
zero
1: The result of the last operation is zero
Switching between the three sets of flags is performed automatically when an NMI, an interrupt or
a RETI instruction occurs. As NMI mode is automatically selected after the reset of the MCU, the
ST6 core uses the NMI flags first.
Stack. The ST6 CPU includes a true LIFO (Last In
First Out) hardware stack which eliminates the
need for a stack pointer. The stack consists of six
separate 12-bit RAM locations that do not belong
to the data space RAM area. When a subroutine
call (or interrupt request) occurs, the contents of
each level are shifted into the next level down,
while the content of the PC is shifted into the first
level (the original contents of the sixth stack level
are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of
each level is popped back into the previous level.
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Figure 8. Stack manipulation
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PROGRAM
COUNTER
ON RETURN
FROM
INTERRUPT,
OR
SUBROUTINE
LEVEL 1
LEVEL 2
ON
INTERRUPT,
OR
SUBROUTINE
CALL
LEVEL 3
LEVEL 4
LEVEL 5
LEVEL 6
Since the accumulator, in common with all other
data space registers, is not stored in this stack,
management of these registers should be performed within the subroutine.
Caution: The stack will remain in its “deepest” position if more than 6 nested calls or interrupts are
executed, and consequently the last return address will be lost.
It will also remain in its highest position if the stack
is empty and a RET or RETI is executed. In this
case the next instruction will be executed.
ST6215C ST6225C
5 CLOCKS, SUPPLY AND RESET
5.1 CLOCK SYSTEM
The main oscillator of the MCU can be driven by
any of these clock sources:
– external clock signal
– external AT-cut parallel-resonant crystal
– external ceramic resonator
– external RC network (RNET).
In addition, an on-chip Low Frequency Auxiliary
Oscillator (LFAO) is available as a back-up clock
system or to reduce power consumption.
An optional Oscillator Safeguard (OSG) filters
spikes from the oscillator lines, and switches to the
LFAO backup oscillator in the event of main oscillator failure. It also automatically limits the internal
clock frequency (fINT) as a function of VDD, in order
to guarantee correct operation. These functions
are illustrated in Figure 10, and Figure 11.
Figure 9. Clock Circuit Block Diagram
)
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Table 5 illustrates various possible oscillator configurations using an external crystal or ceramic
resonator, an external clock input, an external resistor (RNET), or the lowest cost solution using only
the LFAO.
For more details on configuring the clock options,
refer to the Option Bytes section of this document.
The internal MCU clock frequency (fINT) is divided
by 12 to drive the Timer, the Watchdog timer and
the A/D converter, by 13 to drive the CPU core and
the SPI and by 1 or 3 to drive the ARTIMER, as
shown in Figure 9.
With an 8 MHz oscillator, the fastest CPU cycle is
therefore 1.625µs.
A CPU cycle is the smallest unit of time needed to
execute any operation (for instance, to increment
the Program Counter). An instruction may require
two, four, or five CPU cycles for execution.
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OSCILLATOR SAFEGUARD (OSG)
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OSG
filtering
od
Pr
MAIN
OSCILLATOR
SPI
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fOSC
: 13
CORE
8-BIT TIMER
0
Oscillator
Divider
fINT
: 12
WATCHDOG
1
ADC
LFAO
OSCOFF BIT
(ADCR REGISTER)
:1
8-BIT ARTIMER
:3
8-BIT ARTIMER
OSG ENABLE OPTION BIT (See OPTION BYTE SECTION)
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ST6215C ST6225C
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Crystal/Resonator Option1)
Crystal/Resonator Option1)
Hardware Configuration
External Clock
ST6
OSCin
OSCout
NC
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EXTERNAL
CLOCK
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Crystal/Resonator Clock 2)
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Pr
OSCin
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RC Network Option1)
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)-
Table 5. Oscillator Configurations
OSG Enabled Option1)
CLOCK SYSTEM (Cont’d)
5.1.1 Main Oscillator
The oscillator configuration is specified by selecting the appropriate option in the option bytes (refer
to the Option Bytes section of this document).
When the CRYSTAL/RESONATOR option is selected, it must be used with a quartz crystal, a ceramic resonator or an external signal provided on
the OSCin pin. When the RC NETWORK option is
selected, the system clock is generated by an external resistor (the capacitor is implemented internally).
The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register (not
available on some devices). This will automatically
start the Low Frequency Auxiliary Oscillator
(LFAO).
The main oscillator can be turned off by resetting
the OSCOFF bit of the A/D Converter Control Register or by resetting the MCU. When the main oscillator starts there is a delay made up of the oscillator start-up delay period plus the duration of the
software instruction at a clock frequency fLFAO.
Caution: It should be noted that when the RC network option is selected, the accuracy of the frequency is about 20% so it may not be suitable for
some applications (For more details, please refer
to the Electrical Characteristics Section).
CL1
OSCout
LOAD
CAPACITORS 3)
CL2
RC Network
ST6
OSCin
OSCout
NC
RNET
LFAO
ST6
OSCin
OSCout
NC
Notes:
1. To select the options shown in column 1 of the above
table, refer to the Option Byte section.
2.This schematic are given for guidance only and are subject to the schematics given by the crystal or ceramic resonator manufacturer.
3. For more details, please refer to the Electrical Characteristics Section.
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ST6215C ST6225C
CLOCK SYSTEM (Cont’d)
5.1.2 Oscillator Safeguard (OSG)
The Oscillator Safeguard (OSG) feature is a
means of dramatically improving the operational
integrity of the MCU. It is available when the OSG
ENABLED option is selected in the option byte (refer to the Option Bytes section of this document).
The OSG acts as a filter whose cross-over frequency is device dependent and provides three
basic functions:
– Filtering spikes on the oscillator lines which
would result in driving the CPU at excessive frequencies
– Management of the Low Frequency Auxiliary
Oscillator (LFAO), (useable as low cost internal
clock source, backup clock in case of main oscillator failure or for low power consumption)
– Automatically limiting the fINT clock frequency as
a function of supply voltage, to ensure correct
operation even if the power supply drops.
5.1.2.1 Spike Filtering
Spikes on the oscillator lines result in an effectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over frequency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure
10). In all cases, when the OSG is active, the max-
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imum internal clock frequency, fINT, is limited to
fOSG, which is supply voltage dependent.
5.1.2.2 Management of Supply Voltage
Variations
Over-frequency, at a given power supply level, is
seen by the OSG as spikes; it therefore filters out
some cycles in order that the internal clock frequency of the device is kept within the range the
particular device can stand (depending on VDD),
and below fOSG: the maximum authorised frequency with OSG enabled.
5.1.2.3 LFAO Management
When the OSG is enabled, the Low Frequency
Auxiliary Oscillator can be used (see Section
5.1.3).
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Note: The OSG should be used wherever possible
as it provides maximum security for the application. It should be noted however, that it can increase power consumption and reduce the maximum operating frequency to fOSG (see Electrical
Characteristics section).
Caution: Care has to be taken when using the
OSG, as the internal frequency is defined between
a minimum and a maximum value and may vary
depending on both VDD and temperature. For precise timing measurements, it is not recommended
to use the OSG.
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Figure 10. OSG Filtering Function
fOSC>fOSG
fOSC
fOSCVDD while a negative injection is induced by VIN
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