ST72324Bxx-Auto
8-bit MCU for automotive, 3.8 to 5.5V operating range with
8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
Features
Memories
■
8 to 32 Kbyte dual voltage High Density Flash
(HDFlash) or ROM with readout protection
capability. In-application programming and Incircuit programming for HDFlash devices
■ 384 bytes to 1 Kbyte RAM
■ HDFlash endurance: 100 cycles, data retention
20 years
Clock, reset and supply management
■
Enhanced low voltage supervisor (LVD) with
programmable reset thresholds and auxiliary
voltage detector (AVD) with interrupt capability
■ Clock sources: crystal/ceramic resonator
oscillators, internal RC oscillator and external
clock input
■ PLL for 2x frequency multiplication
■ 4 power saving modes: Slow, Wait, Active Halt,
and Halt
LQFP44
10 x 10
LQFP32
7x7
4 timers
■
Main clock controller with Real-time base,
Beep and Clock-out capabilities
■ Configurable watchdog timer
■ 16-bit Timer A with 1 input capture, 1 output
compare, external clock input, PWM and pulse
generator modes
■ 16-bit Timer B with 2 input captures, 2 output
compares, PWM and pulse generator modes
2 communication interfaces
■
SPI synchronous serial interface
■ SCI asynchronous serial interface
Interrupt management
1 analog peripheral (low current coupling)
■
Nested interrupt controller
■ 10 interrupt vectors plus TRAP and RESET
■ 9/6 external interrupt lines (on 4 vectors)
■
Up to 32 I/O ports
■
■
32/24 multifunctional bidirectional I/O lines
22/17 alternate function lines
■ 12/10 high sink outputs
■
Instruction set
■
8-bit data manipulation
63 basic instructions
■ 17 main addressing modes
■ 8 x 8 Unsigned Multiply Instruction
Development tools
■
Table 1.
Device
In-circuit testing capability
Device summary
Memory
RAM (stack)
ST72324BK2-Auto Flash/ROM 8 Kbytes
384 (256) bytes
ST72324BK4-Auto Flash/ROM 16 Kbytes
512 (256) bytes
ST72324BK6-Auto Flash/ROM 32 Kbytes
1024 (256) bytes
ST72324BJ2-Auto Flash/ROM 8 Kbytes
384 (256) bytes
ST72324BJ4-Auto Flash/ROM 16 Kbytes
512 (256) bytes
ST72324BJ6-Auto Flash/ROM 32 Kbytes
1024 (256) bytes
July 2010
10-bit ADC with up to 12 input ports
Voltage range
Doc ID13466 Rev 4
Temp. range
Package
LQFP32
7x7
3.8 to 5.5V
up to
-40 to 125°C
LQFP44
10x10
1/198
www.st.com
1
Contents
ST72324B-Auto
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3.1
4.4
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5
ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.6
IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7.1
5
6
2/198
Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Flash Control/Status Register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.1
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.2
Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.3
Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.4
Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.5
Stack Pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2
PLL (phase locked loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3
Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.1
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.2
Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Doc ID13466 Rev 4
ST72324B-Auto
Contents
6.3.3
6.4
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.1
6.5
6.6
6.5.1
LVD (low voltage detector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.5.2
AVD (auxiliary voltage detector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.5.3
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5.4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9
System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 39
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.2
Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.2.1
Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.2
Different interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.2.3
Non-maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.2.4
Maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3
Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.4
Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.5
Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.6
8
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.6.1
7
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.5.1
CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.5.2
Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 46
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.6.1
I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.6.2
External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 49
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.2
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.3
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.4
Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.4.1
Active Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.4.2
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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Contents
ST72324B-Auto
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.2.1
Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.2.2
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2.3
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.3
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.5.1
10
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1
10.2
10.3
4/198
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1.4
How to program the Watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.1.5
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.1.6
Hardware Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.1.7
Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 68
10.1.8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.1.9
Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 69
10.2.1
Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.2.2
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2.3
Real-time clock (RTC) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2.4
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2.5
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.2.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.2.7
MCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.3.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.3.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.3.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.3.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.3.6
Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Doc ID13466 Rev 4
ST72324B-Auto
Contents
10.3.7
10.4
10.5
10.6
11
16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.4.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.4.4
Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
10.4.5
Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.6
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
10.4.7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
10.4.8
SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.5.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.5.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
10.5.4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
10.5.5
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.5.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.5.7
SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.6.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.6.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
10.6.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.6.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.6.6
ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
11.1
11.2
CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
11.1.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
11.1.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
11.1.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
11.1.4
Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
11.1.5
Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
11.1.6
Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
11.1.7
Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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Contents
12
ST72324B-Auto
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.1
12.2
12.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.2.1
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.2.2
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.2.3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.4
LVD/AVD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.5
12.6
12.7
12.8
12.9
6/198
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.4.1
Operating conditions with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.4.2
Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 149
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.5.1
ROM current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.5.2
Flash current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.5.3
Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
12.5.4
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.6.1
General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.6.2
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.6.3
Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 154
12.6.4
RC oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.6.5
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.7.1
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.7.2
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.8.1
Functional electromagnetic susceptibility (EMS) . . . . . . . . . . . . . . . . . 158
12.8.2
Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.8.3
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 160
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.9.1
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.9.2
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Doc ID13466 Rev 4
ST72324B-Auto
Contents
12.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.10.2 ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.11 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.11.1 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.12 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 169
12.12.1 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.13 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
12.13.1 Analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 173
12.13.2 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.13.3 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
13
14
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
13.1
LQFP44 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
13.2
LQFP32 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
13.3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.4
Ecopack information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.5
Packaging for automatic handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Device configuration and ordering information . . . . . . . . . . . . . . . . . 179
14.1
14.1.1
Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
14.1.2
Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
14.2
ROM device ordering information and transfer of customer code . . . . . 183
14.3
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.4
15
Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
14.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3.2
Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3.3
Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3.4
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3.5
Socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 188
ST7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.1
All Flash and ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.1.1
Safe connection of OSC1/OSC2 pins . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.1.2
External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Doc ID13466 Rev 4
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Contents
ST72324B-Auto
15.2
15.3
16
8/198
15.1.3
Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
15.1.4
Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 191
15.1.5
16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.1.6
TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 192
15.1.7
SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
8/16 Kbyte Flash devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
15.2.1
39-pulse ICC entry mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
15.2.2
Negative current injection on pin PB0 . . . . . . . . . . . . . . . . . . . . . . . . . 193
8/16 Kbyte ROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
15.3.1
Readout protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
15.3.2
I/O Port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Doc ID13466 Rev 4
ST72324B-Auto
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Arithmetic management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Software interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Interrupt software priority selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Effect of low power modes on SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AVD interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reset source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
CPU CC register interrupt bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
ISPRx interrupt vector correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
EICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interrupt sensitivity - ei2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interrupt sensitivity - ei3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupt sensitivity - ei0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupt sensitivity - ei1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
MCC/RTC low power mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DR register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
I/O port interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Effect of lower power modes on Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
WDGCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Effect of low power modes on MCC/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
MCC/RTC interrupt control/wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
MCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Time base selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
MCCBCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Beep frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Input capture byte distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Output compare byte distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
16-bit timer interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Doc ID13466 Rev 4
9/198
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
10/198
ST72324B-Auto
CR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
CR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
CSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SPI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SPICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
SPI master mode SCK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SPICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SCI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SCISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SCICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SCIBRR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SCIERPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SCIETPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Effect of low power modes on ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
ADCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
ADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
ADCDRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 139
Relative direct and indirect instructions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Operating conditions with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
AVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
ROM current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Flash current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Oscillators, PLL and LVD current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
OSCRANGE selection for typical resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RC oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Dual voltage HDFlash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Doc ID13466 Rev 4
ST72324B-Auto
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
List of tables
EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Option byte 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Option byte 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Package selection (OPT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Doc ID13466 Rev 4
11/198
List of figures
ST72324B-Auto
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
12/198
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
44-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
32-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
RESET sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Priority decision process flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Active Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Active Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HALT timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Exact timeout duration (tmin and tmax). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Output compare timing diagram, fTIMER = fCPU/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
One pulse mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
One Pulse mode timing example(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Pulse width modulation mode timing example with two output compare functions(1)(2) . . 86
Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Doc ID13466 Rev 4
ST72324B-Auto
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
List of figures
Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Generic SS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Data clock timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Clearing the WCOL bit (Write Collision flag) software sequence . . . . . . . . . . . . . . . . . . . 104
Single master/multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Bit sampling in Reception mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
fCPU max versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Typical application with a crystal or ceramic resonator (8/16 Kbyte Flash
and ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Typical application with a crystal or ceramic resonator (32 Kbyte Flash
and ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Typical fOSC(RCINT) vs TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Integrated PLL jitter vs signal frequency(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Unused I/O pins configured as input(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Typical IPU vs. VDD with VIN = VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Typical VOL at VDD = 5V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Typical VOL at VDD = 5V (high-sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Typical VOH at VDD = 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Typical VOL vs. VDD (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Typical VOL vs. VDD (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Typical VOH vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
RESET pin protection when LVD is enabled(1)(2)(3)(4)(5)(6) . . . . . . . . . . . . . . . . . . . . . 167
RESET pin protection when LVD is disabled(1)(2)(3)(4) . . . . . . . . . . . . . . . . . . . . . . . . . 167
Two typical applications with ICCSEL/VPP pin(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
SPI slave timing diagram with CPHA = 0(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
SPI slave timing diagram with CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
SPI master timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
RAIN max. vs fADC with CAIN = 0pF(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Recommended CAIN and RAIN values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
44-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
pin 1 orientation in tape and reel conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
ST72F324Bxx-Auto Flash commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . 182
ST72P324Bxx-Auto FastROM commercial product structure. . . . . . . . . . . . . . . . . . . . . . 184
ST72324Bxx-Auto ROM commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Doc ID13466 Rev 4
13/198
Description
1
ST72324B-Auto
Description
The ST72324B-Auto devices are members of the ST7 microcontroller family designed for
mid-range automotive applications running from 3.8 to 5.5V. Different package options offer
up to 32 I/O pins.
All devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set and are available with Flash or ROM program memory. The ST7 family
architecture offers both power and flexibility to software developers, enabling the design of
highly efficient and compact application code.
The on-chip peripherals include an A/D converter, two general purpose timers, an SPI
interface and an SCI interface. For power economy, the microcontroller can switch
dynamically into, Slow, Wait, Active Halt or Halt mode when the application is in idle or
stand-by state.
Figure 1.
Device block diagram
8-bit CORE
ALU
RESET
VPP
Program
memory
(8 - 32 Kbytes)
CONTROL
RAM
(384 - 1024 bytes)
VSS
VDD
LVD
OSC1
OSC2
OSC
WATCHDOG
PORT F
PF7:6, 4, 2:0
(6 bits on J devices)
(5 bits on K devices)
TIMER A
BEEP
ADDRESS AND DATA BUS
MCC/RTC/BEEP
PORT A
PORT B
PA7:3
(5 bits on J devices)
(4 bits on K devices)
PB4:0
(5 bits on J devices)
(3 bits on K devices)
PORT E
PE1:0
(2 bits)
PORT C
SCI
TIMER B
PORT D
PD5:0
(6 bits on J devices)
(2 bits on K devices)
VAREF
VSSA
PC7:0
(8 bits)
SPI
10-bit ADC
Typical applications include
14/198
●
all types of car body applications such as window lift, DC motor control, rain sensors
●
safety microcontroller in airbag and engine management applications
●
auxiliary functions in car radios
Doc ID13466 Rev 4
ST72324B-Auto
Pin description
44-pin LQFP package pinout
PE0/TDO
VDD_2
OSC1
OSC2
VSS_2
RESET
VPP/ICCSEL
PA7 (HS)
PA6 (HS)
PA5 (HS)
PA4 (HS)
Figure 2.
RDI / PE1
PB0
PB1
PB2
PB3
(HS) PB4
AIN0/PD0
AIN1/PD1
AIN2/PD2
AIN3/PD3
AIN4/PD4
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
ei0 31
ei2
4
30
5
29
ei3
6
28
7
27
8
26
9
25
ei1
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
VSS_1
VDD_1
PA3 (HS)
PC7/SS/AIN15
PC6/SCK/ICCCLK
PC5/MOSI/AIN14
PC4 / MISO/ICCDATA
PC3 (HS)/ICAP1_B
PC2 (HS)/ICAP2_B
PC1/OCMP1_B/AIN13
PC0/OCMP2_B/AIN12
AIN5/PD5
VAREF
VSSA
MCO/AIN8/PF0
BEEP/(HS) PF1
(HS) PF2
OCMP1_A/AIN10/PF4
ICAP1_A/(HS) PF6
EXTCLK_A/(HS) PF7
VDD_0
VSS_0
(HS) 20mA high sink capability
eix associated external interrupt vector
32-pin LQFP package pinout
PD1/AIN1
PD0/AIN0
PB4 (HS)
PB3
PB0
PE1/RDI
PE0/TDO
VDD_2
Figure 3.
VAREF
VSSA
MCO/AIN8/PF0
BEEP/(HS) PF1
OCMP1_A/AIN10/PF4
ICAP1_A/(HS) PF6
EXTCLK_A/(HS) PF7
AIN12/OCMP2_B/PC0
32 31 30 29 28 27 26 25
24
1
ei3 ei2
23
2
22
3
ei1
21
4
20
5
19
6
18
7
ei0 17
8
9 10 11 12 13 14 15 16
AIN13/OCMP1_B/PC1
ICAP2_B/(HS) PC2
ICAP1_B/(HS) PC3
ICCDATA/MISO/PC4
AIN14/MOSI/PC5
ICCCLK/SCK/PC6
AIN15/SS/PC7
(HS) PA3
2
Pin description
OSC1
OSC2
VSS_2
RESET
VPP/ICCSEL
PA7 (HS)
PA6 (HS)
PA4 (HS)
(HS) 20mA high sink capability
eix associated external interrupt vector
See Section 12: Electrical characteristics on page 145 for external pin connection
guidelines.
Doc ID13466 Rev 4
15/198
Pin description
ST72324B-Auto
Refer to Section 9: I/O ports on page 58 for more details on the software configuration of the
I/O ports.
The reset configuration of each pin is shown in bold. This configuration is valid as long as
the device is in reset state.
Device pin description
Port
I/O
CT
HS
7
31 PD0/AIN0
I/O
CT
X
X
8
32 PD1/AIN1
I/O
CT
X
Output
Alternate function
PP
Main
function
(after
reset)
OD
ana
Output
30 PB4 (HS)
wpu
Input
6
Name
float
LQFP32
Input
LQFP44
No.
Level
Type
Pin
X
X
Port B4
X
X
X
Port D0
ADC analog input 0
X
X
X
X
Port D1
ADC analog input 1
X
int
Table 2.
ei3
9
-
PD2/AIN2
I/O
CT
X
X
X
X
X
Port D2
ADC analog input 2
10
-
PD3/AIN3
I/O
CT
X
X
X
X
X
Port D3
ADC analog input 3
11
-
PD4/AIN4
I/O
CT
X
X
X
X
X
Port D4
ADC analog input 4
12
-
PD5/AIN5
I/O
CT
X
X
X
X
X
Port D5
ADC analog input 5
13
(1)
1
VAREF
14
2
VSSA(1)
15
3
PF0/MCO/AIN8
I/O
CT
16
4
PF1 (HS)/BEEP
I/O
CT
17
-
PF2 (HS)
I/O
CT
18
5
PF4/OCMP1_A
/AIN10
I/O
CT
19
6
PF6
(HS)/ICAP1_A
I/O
CT
20
7
PF7
(HS)/EXTCLK_A
I/O
CT
21
-
VDD_0(1)
S
Digital main supply voltage
22
-
VSS_0(1)
S
Digital ground voltage
23
8
PC0/OCMP2_B
/AIN12
I/O
CT
X
X
X
X
X
Port C0
Timer B
output
compare 2
ADC analog
input 12
24
9
PC1/OCMP1_B
/AIN13
I/O
CT
X
X
X
X
X
Port C1
Timer B
output
compare 1
ADC analog
input 13
PC2
(HS)/ICAP2_B
I/O
CT
X
X
X
X
Port C2
Timer B input capture 2
25 10
16/198
S
Analog reference voltage for ADC
S
Analog ground voltage
ADC analog
input 8
X
X
Port F0
Main clock
out (fCPU)
ei1
X
X
Port F1
Beep signal output
ei1
X
X
Port F2
X
X
Port F4
Timer A
output
compare 1
X
ei1
HS
X
HS
X
X
X
HS
X
X
X
X
Port F6
Timer A input capture 1
HS
X
X
X
X
Port F7
Timer A external clock
source
HS
X
ADC analog
Input 10
X
Doc ID13466 Rev 4
ST72324B-Auto
Table 2.
Pin description
Device pin description (continued)
Output
I/O
CT
HS
27 12
PC4/MISO/ICCD
ATA
I/O
28 13
PC5/MOSI
/AIN14
29 14
PC6/SCK
/ICCCLK
X
X
X
Port C3
Timer B input capture 1
CT
X
X
X
X
Port C4
SPI master
ICC data
in/slave out
input
data
I/O
CT
X
X
X
X
Port C5
SPI master
ADC analog
out/slave in
input 14
data
I/O
CT
X
X
X
X
Port C6
SPI serial
clock
30 15 PC7/SS/AIN15
I/O
CT
X
X
X
X
Port C7
SPI slave
ADC analog
select
input 15
(active low)
31 16 PA3 (HS)
I/O
CT
X
X
Port A3
32
33
HS
X
ana
X
int
PP
Alternate function
OD
Main
function
(after
reset)
wpu
Output
float
LQFP32
PC3
(HS)/ICAP1_B
LQFP44
26 11
Name
Port
Input
Input
No.
Level
Type
Pin
X
X
ei0
ICC clock
output
-
VDD_1(1)
S
Digital main supply voltage
-
VSS_1(1)
S
Digital ground voltage
34 17 PA4 (HS)
I/O
CT
HS
X
X
X
X
Port A4
35
PA5 (HS)
I/O
CT
HS
X
X
X
X
Port A5
36 18 PA6 (HS)
I/O
CT
HS
X
T
Port A6(2)
37 19 PA7 (HS)
I/O
CT
HS
X
T
Port A7(2)
-
38 20 VPP /ICCSEL
39 21 RESET
Must be tied low. In the Flash
programming mode, this pin acts as
the programming voltage input VPP.
See Section 12.10.2 for more details.
High voltage must not be applied to
ROM devices.
I
I/O
CT
Top priority non-maskable interrupt
40 22
VSS_2(1)
S
Digital ground voltage
41 23
OSC2(3)
O
Resonator oscillator inverter output
42 24 OSC1(3)
I
External clock input or resonator
oscillator inverter input
43 25 VDD_2(1)
S
Digital main supply voltage
44 26 PE0/TDO
I/O
CT
X
X
X
X
Port E0
SCI transmit data out
1
I/O
CT
X
X
X
X
Port E1
SCI receive data in
27 PE1/RDI
Doc ID13466 Rev 4
17/198
Pin description
Device pin description (continued)
2
28 PB0
PP
Output
ana
int
wpu
float
Name
Input
Output
LQFP32
LQFP44
No.
Port
OD
Level
Type
Pin
Input
Table 2.
ST72324B-Auto
Main
function
(after
reset)
I/O
CT
X
ei2
X
X
Port B0
3
-
PB1
I/O
CT
X
ei2
X
X
Port B1
4
-
PB2
I/O
CT
X
ei2
X
X
Port B2
29 PB3
I/O
CT
X
X
X
Port B3
5
ei2
Alternate function
Caution: Negative
current injection not
allowed on this pin on
8/16 Kbyte Flash
devices.(4)
1. It is mandatory to connect all available VDD and VREF pins to the supply voltage and all VSS and VSSA pins to ground.
2. On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration after
reset. The configuration of these pads must be kept at reset state to avoid added current consumption..
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1:
Description and Section 12.6: Clock and timing characteristics or more details.
4. For details refer to Section 12.9.1 on page 162
Legend / Abbreviations for Table 2:
Type:I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7DD
CT = CMOS 0.3VDD/0.7DD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
Input:float = floating, wpu = weak pull-up, int = interrupt(a), ana = analog ports
Output:OD = open drain(b), PP = push-pull
a. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column
(wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the
configuration is floating interrupt input.
b. In the open drain output column, ‘T’ defines a true open drain I/O (P-Buffer and protection diode to VDD are not
implemented). See Section 9: I/O ports and Section 12.9: I/O port pin characteristics for more details.
18/198
Doc ID13466 Rev 4
ST72324B-Auto
3
Register and memory map
Register and memory map
As shown in Figure 4 the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, up to 1024 bytes
of RAM and up to 32 Kbytes of user program memory. The RAM space includes up to 256
bytes for the stack from 0100h to 01FFh.
The highest address bytes contain the user reset and interrupt vectors.
Caution:
Never access memory locations marked as ‘Reserved’. Accessing a reserved area can
have unpredictable effects on the device.
Figure 4.
Memory map
0000h
0080h
HW registers
(see Table 3)
007Fh
0080h
00FFh
0100h
RAM
(1024, 512 or 384 bytes)
047Fh
0480h
Short addressing
RAM (zero page)
256 bytes stack
01FFh
0200h
Reserved
16-bit addressing
RAM
027Fh
or 047Fh
7FFFh
8000h
Program memory
(32, 16 or 8 Kbytes)
C000h
FFDFh
FFE0h Interrupt and reset vectors
(see Table 25)
FFFFh
Table 3.
8000h
32 Kbytes
16 Kbytes
E000h
8 Kbytes
FFFFh
Hardware register map
Register name
Remarks(1)
Block
0000h
0001h
0002h
Port A(2)
PADR
PADDR
PAOR
Port A data register
Port A data direction register
Port A option register
00h(3)
00h
00h
R/W
R/W
R/W
0003h
0004h
0005h
(1)
PBDR
PBDDR
PBOR
Port B data register
Port B data direction register
Port B option register
00h(2)
00h
00h
R/W
R/W
R/W
Port C data register
Port C data direction register
Port C option register
00h(2)
00h
00h
R/W
R/W
R/W
Port B
Register label
Reset
status(1)
Address
0006h
0007h
0008h
Port C
PCDR
PCDDR
PCOR
0009h
000Ah
000Bh
Port D(1)
PDADR
PDDDR
PDOR
Port D data register
Port D data direction register
Port D option register
00h(2)
00h
00h
R/W
R/W
R/W
000Ch
000Dh
000Eh
Port E(1)
PEDR
PEDDR
PEOR
Port E data register
Port E data direction register
Port E option register
00h(2)
00h
00h
R/W
R/W(1)
R/W(1)
Doc ID13466 Rev 4
19/198
Register and memory map
Table 3.
Address
000Fh
0010h
0011h
Hardware register map (continued)
Block
(1)
Port F
Register label
PFDR
PFDDR
PFOR
0012h to
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
SPI
ITC
0029h
Flash
002Ah
Watchdog
002Bh
SI
002Ch
002Dh
MCC
20/198
Port F data register
Port F data direction register
Port F option register
Reset
status(1)
Remarks(1)
00h(2)
00h
00h
R/W
R/W
R/W
SPIDR
SPICR
SPICSR
SPI data I/O register
SPI control register
SPI control/status register
xxh
0xh
00h
R/W
R/W
R/W
ISPR0
ISPR1
ISPR2
ISPR3
Interrupt software priority register 0
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
EICR
External interrupt control register
00h
R/W
FCSR
Flash control/status register
00h
R/W
WDGCR
Watchdog control register
7Fh
R/W
SICSR
System integrity control/status register
000x 000xb
R/W
MCCSR
MCCBCR
Main clock control/status register
Main clock controller: beep control register
00h
00h
R/W
R/W
002Eh to
0030h
0040h
Register name
Reserved area (15 bytes)
0028h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
ST72324B-Auto
Reserved area (3 bytes)
Timer A
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A control register 2
Timer A control register 1
Timer A control/status register
Timer A input capture 1 high register
Timer A input capture 1 low register
Timer A output compare 1 high register
Timer A output compare 1 low register
Timer A counter high register
Timer A counter low register
Timer A alternate counter high register
Timer A alternate counter low register
Timer A input capture 2 high register
Timer A input capture 2 low register
Timer A output compare 2 high register
Timer A output compare 2 low register
Reserved area (1 byte)
Doc ID13466 Rev 4
00h
00h
xxxx x0xxb
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W
ST72324B-Auto
Table 3.
Address
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
Register and memory map
Hardware register map (continued)
Block
Register label
Reset
status(1)
Remarks(1)
Timer B
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B control register 2
Timer B control register 1
Timer B control/status register
Timer B input capture 1 high register
Timer B input capture 1 low register
Timer B output compare 1 high register
Timer B output compare 1 low register
Timer B counter high register
Timer B counter low register
Timer B alternate counter high register
Timer B alternate counter low register
Timer B input capture 2 high register
Timer B input capture 2 low register
Timer B output compare 2 high register
Timer B output compare 2 low register
00h
00h
xxxx x0xxb
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W
SCI
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
SCI status register
SCI data register
SCI baud rate register
SCI control register 1
SCI control register 2
SCI extended receive prescaler register
Reserved area
SCI extended transmit prescaler register
C0h
xxh
00h
x000 0000b
00h
00h
--00h
Read only
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
R/W
Read only
Read only
0058h to
006Fh
0070h
0071h
0072h
Register name
Reserved area (24 bytes)
ADC
ADCCSR
ADCDRH
ADCDRL
0073h
007Fh
Control/status register
Data high register
Data low register
Reserved area (13 bytes)
1. Legend: x = undefined, R/W = read/write.
2. The bits associated with unavailable pins must always keep their reset value.
3. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
Doc ID13466 Rev 4
21/198
Flash program memory
ST72324B-Auto
4
Flash program memory
4.1
Introduction
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external VPP supply.
The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
Main features
●
4.3
3 Flash programming modes:
–
Insertion in a programming tool. In this mode, all sectors including option bytes
can be programmed or erased.
–
ICP (in-circuit programming). In this mode, all sectors including option bytes can
be programmed or erased without removing the device from the application board.
–
IAP (in-application programming). In this mode, all sectors, except Sector 0, can
be programmed or erased without removing the device from the application board
and while the application is running.
●
ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
●
Readout protection
●
Register Access Security System (RASS) to prevent accidental programming or
erasing
Structure
The Flash memory is organized in sectors and can be used for both code and data storage.
Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (seeTable 4). Each of these sectors can be erased independently to avoid
unnecessary erasing of the whole Flash memory when only a partial erasing is required.
The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
Sector 0 (F000h-FFFFh).
Table 4.
22/198
Sectors available in Flash devices
Flash size (bytes)
Available sectors
4K
Sector 0
8K
Sectors 0, 1
>8K
Sectors 0, 1, 2
Doc ID13466 Rev 4
ST72324B-Auto
4.3.1
Flash program memory
Readout protection
Readout protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the
entire program memory is first automatically erased.
Readout protection selection depends on the device type:
●
In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
●
In ROM devices it is enabled by mask option specified in the option list.
Figure 5.
Memory map and sector address
8K
16K
32K
Flash
memory size
7FFFh
Sector 2
BFFFh
8 Kbytes
DFFFh
EFFFh
FFFFh
4.4
24 Kbytes
4 Kbytes
Sector 1
4 Kbytes
Sector 0
ICC interface
ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see
Figure 6). These pins are:
●
RESET: device reset
●
VSS: device power supply ground
●
ICCCLK: ICC output serial clock pin
●
ICCDATA: ICC input/output serial data pin
●
ICCSEL/VPP: programming voltage
●
OSC1 (or OSCIN): main clock input for external source (optional)
●
VDD: application board power supply (optional, see Figure 6, Note 3).
Doc ID13466 Rev 4
23/198
Flash program memory
Figure 6.
ST72324B-Auto
Typical ICC interface
Programming tool
ICC connector
Mandatory for
8/16 Kbyte Flash devices
(see note 4)
ICC cable
(See note 3)
9
7
5
3
1
10
8
6
4
2
Application board
ICC connector
HE10 connector type
Application
reset source
See note 2
10k
Application
power supply
ICCDATA
RESET
ICCCLK
ST7
ICCSEL/VPP
VSS
OSC1
OSC2
VDD
See note 1
Application
I/O
1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is
necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in
progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by
the application, isolation such as a serial resistor has to be implemented in case another device forces the
signal. Refer to the Programming Tool documentation for recommended resistor values.
2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts
between the programming tool and the application reset circuit if it drives more than 5mA at high level
(PUSH-pull output or pull-up resistor 1K or a reset management IC with open
drain output and pull-up resistor >1K, no additional components are needed. In all cases the user must
ensure that no external reset is generated by the application during the ICC session.
3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be
connected when using most ST programming tools (it is used to monitor the application power supply).
Please refer to the programming tool manual.
4. Pin 9 has to be connected to the OSC1 (OSCIN) pin of the ST7 when the clock is not available in the
application or if the selected clock option is not programmed in the option byte. ST7 devices with multioscillator capability need to have OSC2 grounded in this case.
Caution:
External clock ICC entry mode is mandatory in ST72F324B 8/16 Kbyte Flash devices. In
this case pin 9 must be connected to the OSC1 (OSCIN) pin of the ST7 and OSC2 must be
grounded. 32 Kbyte Flash devices may use external clock or application clock ICC entry
mode.
4.5
ICP (in-circuit programming)
To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM, Flash memory programming can be fully
customized (number of bytes to program, program locations, or selection serial
communication interface for downloading).
When using an STMicroelectronics or third-party programming tool that supports ICP and
the specific microcontroller device, the user needs only to implement the ICP hardware
interface on the application board (see Figure 6). For more details on the pin locations, refer
to the device pinout description.
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4.6
Flash program memory
IAP (in-application programming)
This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP
mode or by plugging the device in a programming tool).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (such as user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored). For example, it is possible to
download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash sectors except Sector 0, which is write/erase
protected to allow recovery in case errors occur during the programming operation.
4.7
Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual.
4.7.1
Flash Control/Status Register (FCSR)
This register is reserved for use by programming tool software. It controls the Flash
programming and erasing operations.
Reset value:0000 0000 (00h)
FCSR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 5.
Flash control/status register address and reset value
Address (Hex)
0029h
Register label
7
6
5
4
3
2
1
0
FCSR reset value
0
0
0
0
0
0
0
0
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Central processing unit (CPU)
ST72324B-Auto
5
Central processing unit (CPU)
5.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.
5.2
5.3
Main features
●
Enable executing 63 basic instructions
●
Fast 8-bit by 8-bit multiply
●
17 main addressing modes (with indirect addressing mode)
●
Two 8-bit index registers
●
16-bit stack pointer
●
Low power Halt and Wait modes
●
Priority maskable hardware interrupts
●
Non-maskable software/hardware interrupts
CPU registers
The six CPU registers shown in Figure 7 are not present in the memory mapping and are
accessed by specific instructions.
Figure 7.
CPU registers
7
0
Accumulator
Reset value = XXh
7
0
X index register
Reset value = XXh
7
0
Y index register
Reset value = XXh
15
PCH
8 7
PCL
0
Program counter
Reset value = reset vector @ FFFEh-FFFFh
7
0
1 1 I1 H I0 N Z C
Reset value = 1 1 1 X 1 X X X
15
8 7
Condition code register
0
Stack pointer
Reset value = stack higher address
X = undefined value
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5.3.1
Central processing unit (CPU)
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
5.3.2
Index registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas
for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to
indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
5.3.3
Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is
the LSB) and PCH (Program Counter High which is the MSB).
5.3.4
Condition Code register (CC)
The 8-bit Condition Code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions. These bits can be individually tested and/or controlled by specific
instructions.
CC
Reset value: 111x1xxx
7
6
5
4
3
2
1
0
1
1
I1
H
I0
N
Z
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 6.
Arithmetic management bits
BIt Name
Function
Half carry
4
2
H
N
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instructions. It is reset by hardware during the same
instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
Negative
This bit is set and cleared by hardware. It is representative of the result sign of the last
arithmetic, logical or data manipulation. It is a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1.
This bit is accessed by the JRMI and JRPL instructions.
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Central processing unit (CPU)
Table 6.
ST72324B-Auto
Arithmetic management bits (continued)
BIt Name
1
0
Function
Z
Zero (Arithmetic Management bit)
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
C
Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the ‘bit test and branch’, shift and rotate instructions.
Table 7.
Software interrupt bits
BIt Name
Function
5
I1
Software Interrupt Priority 1
The combination of the I1 and I0 bits determines the current interrupt software priority
(see Table 8).
3
I0
Software Interrupt Priority 0
The combination of the I1 and I0 bits determines the current interrupt software priority
(see Table 8).
Table 8.
Interrupt software priority selection
Interrupt software priority
Level 0 (main)
Level
I1
I0
Low
1
0
0
1
0
0
1
1
Level 1
Level 2
High
Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (ISPRx). They can
be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP
instructions.
See Section 7: Interrupts on page 41 for more details.
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5.3.5
Central processing unit (CPU)
Stack Pointer register (SP)
SP
Reset value: 01 FFh
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 8).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by an LD
instruction.
Note:
When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 8.
●
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
●
On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
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Central processing unit (CPU)
Figure 8.
ST72324B-Auto
Stack manipulation example
Call
subroutine
Push Y
Interrupt
event
Pop Y
RET
or RSP
IRET
@ 0100h
SP
SP
Y
CC
A
CC
A
SP
@ 01FFh
SP
X
X
X
PCH
PCH
PCH
SP
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
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CC
A
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SP
ST72324B-Auto
Supply, reset and clock management
6
Supply, reset and clock management
6.1
Introduction
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. An overview is shown in Figure 10.
For more details, refer to dedicated parametric section.
Main features
6.2
●
Optional Phase Locked Loop (PLL) for multiplying the frequency by 2 (not to be used
with internal RC oscillator in order to respect the max. operating frequency)
●
Multi-Oscillator clock management (MO)
–
5 crystal/ceramic resonator oscillators
–
1 Internal RC oscillator
●
Reset Sequence Manager (RSM)
●
System Integrity management (SI)
–
Main supply low voltage detection (LVD)
–
Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main
supply
PLL (phase locked loop)
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to
multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option
byte. If the PLL is disabled, then fOSC2 = fOSC/2.
Caution:
The PLL is not recommended for applications where timing accuracy is required.
Furthermore, it must not be used with the internal RC oscillator.
Figure 9.
PLL block diagram
fOSC
PLL x 2
0
/2
1
fOSC2
PLL option bit
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Figure 10. Clock, reset and supply block diagram
MultiOscillator
(MO)
OSC2
OSC1
fOSC
fOSC2
PLL
(option)
Main Clock
fCPU
Controller
with Real-time
Clock (MCC/RTC)
System Integrity Management
Reset Sequence
Manager
(RSM)
RESET
AVD Interrupt Request
SICSR
0
AVD AVD LVD
F RF
IE
0
0
0
Watchdog
timer (WDG)
WDG
RF
Low Voltage
Detector
(LVD)
VSS
VDD
Auxiliary Voltage
Detector
(AVD)
6.3
Multi-oscillator (MO)
The main clock of the ST7 can be generated by three different source types coming from the
multi-oscillator block:
●
an external source
●
4 crystal or ceramic resonator oscillators
●
an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Table 9. Refer to the electrical characteristics section for more details.
Caution:
The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left
unconnected, the ST7 main oscillator may start and, in this configuration, could generate an
fOSC clock frequency in excess of the allowed maximum (> 16 MHz.), putting the ST7 in an
unsafe/undefined state. The product behavior must therefore be considered undefined when
the OSC pins are left unconnected.
6.3.1
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
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6.3.2
Supply, reset and clock management
Crystal/ceramic oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main
clock of the ST7. The selection within a list of four oscillators with different frequency ranges
has to be done by option byte in order to reduce consumption (refer to Section 14.1 on page
179 for more details on the frequency ranges). In this mode of the multi-oscillator, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and start-up stabilization time. The loading
capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the reset phase to avoid losing time in the oscillator
start-up phase.
Internal RC oscillator
This oscillator allows a low cost solution for the main clock of the ST7 using only an internal
resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency
accuracy and should not be used in applications that require accurate timing.
In this mode, the two oscillator pins have to be tied to ground.
In order not to exceed the maximum operating frequency, the internal RC oscillator must not
be used with the PLL.
Table 9.
ST7 clock sources
Crystal/ceramic resonators
External clock
Hardware configuration
Internal RC oscillator
6.3.3
OSC1
ST7
OSC2
External
source
OSC1
CL1
ST7
OSC2
Load
capacitors
CL2
ST7
OSC1
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Supply, reset and clock management
6.4
ST72324B-Auto
Reset sequence manager (RSM)
The reset sequence manager includes three reset sources as shown in Figure 12:
●
External reset source pulse
●
Internal LVD reset
●
Internal Watchdog reset
These sources act on the RESET pin and it is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of three phases as shown in Figure 11:
Caution:
●
Active Phase depending on the reset source
●
256 or 4096 CPU clock cycle delay (selected by option byte)
●
Reset vector fetch
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application.
The reset vector fetch phase duration is two clock cycles.
Figure 11. Reset sequence phases
RESET
ACTIVE PHASE
6.4.1
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See the Electrical characteristics
section for more details.
A reset signal originating from an external source must have a duration of at least th(RSTL)in
in order to be recognized (see Figure 13). This detection is asynchronous and therefore the
MCU can enter reset state even in Halt mode.
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Supply, reset and clock management
Figure 12. Reset block diagram
VDD
RON
RESET
Internal
reset
Filter
Pulse
generator
Watchdog reset
LVD reset
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
External power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until VDD is over
the minimum level specified for the selected fOSC frequency.
A proper reset signal for a slow rising VDD supply can generally be provided by an external
RC network connected to the RESET pin.
Internal LVD reset
Two different reset sequences caused by the internal LVD circuitry can be distinguished:
●
Power-On reset
●
Voltage Drop reset
The device RESET pin acts as an output that is pulled low when VDD < VIT+ (rising edge) or
VDD < VIT- (falling edge) as shown in Figure 13.
The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.
Internal Watchdog reset
The reset sequence generated by a internal Watchdog counter overflow is shown in
Figure 13.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
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ST72324B-Auto
Figure 13. RESET sequences
VDD
VIT+(LVD)
VIT-(LVD)
LVD
reset
External
reset
Run
Run
Active phase
Active
phase
Watchdog
reset
Run
Active
phase
Run
tw(RSTL)out
th(RSTL)in
External
RESET
source
RESET pin
Watchdog
reset
Watchdog underflow
Internal reset (256 or 4096 TCPU)
Vector fetch
6.5
System integrity management (SI)
The system integrity management block contains the LVD and auxiliary voltage detector
(AVD) functions. It is managed by the SICSR register.
6.5.1
LVD (low voltage detector)
The LVD function generates a static reset when the VDD supply voltage is below a VITreference value. This means that it secures the power-up as well as the power-down
keeping the ST7 in reset.
The VIT- reference value for a voltage drop is lower than the VIT+ reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the
supply (hysteresis).
The LVD reset circuitry generates a reset when VDD is below:
●
VIT+ when VDD is rising
●
VIT- when VDD is falling
The LVD function is illustrated in Figure 13.
The voltage threshold can be configured by option byte to be low, medium or high.
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Supply, reset and clock management
Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the
MCU can only be in two modes:
●
under full software control
●
in static safe reset
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During an LVD reset, the RESET pin is held low, thus permitting the MCU to reset other
devices.
Note:
1
The LVD allows the device to be used without any external reset circuitry.
2
If the medium or low thresholds are selected, the detection may occur outside the specified
operating voltage range. Below 3.8V, device operation is not guaranteed.
3
The LVD is an optional function which can be selected by option byte.
4
It is recommended to make sure that the VDD supply voltage rises monotonously when the
device is exiting from reset, to ensure the application functions properly.
Figure 14. Low voltage detector vs reset
VDD
Vhys
VIT+
VIT-
RESET
6.5.2
AVD (auxiliary voltage detector)
The AVD is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference
value and the VDD main supply. The VIT- reference value for falling voltage is lower than the
VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis).
The output of the AVD comparator is directly readable by the application software through a
real-time status bit (AVDF) in the SICSR register. This bit is read only.
Caution:
The AVD function is active only if the LVD is enabled through the option byte (see
Section 14.1 on page 179).
Monitoring the VDD main supply
The AVD voltage threshold value is relative to the selected LVD threshold configured by
option byte (see Section 14.1 on page 179).
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the
VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles).
In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing
software to shut down safely before the LVD resets the microcontroller. See Figure 15.
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The interrupt on the rising edge is used to inform the application that the VDD warning state
is over.
If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay
selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached.
If trv is greater than 256 or 4096 cycles then:
●
If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then 2 AVD
interrupts will be received: the first when the AVDIE bit is set, and the second when the
threshold is reached.
●
If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one
AVD interrupt will occur.
Figure 15. Using the AVD to monitor VDD
VDD
Early warning interrupt
(power has dropped, MCU not
not yet in reset)
Vhyst
VIT+(AVD)
VIT-(AVD)
VIT+(LVD)
VIT-(LVD)
AVDF bit
trv Voltage rise time
0
1
Reset value
1
0
AVD Interrupt
Request
if AVDIE bit = 1
Interrupt process
Interrupt process
LVD RESET
6.5.3
Low power modes
Table 10.
Effect of low power modes on SI
Mode
6.5.4
Description
Wait
No effect on SI. AVD interrupt causes the device to exit from Wait mode.
Halt
The CRSR register is frozen.
Interrupts
The AVD interrupt event generates an interrupt if the AVDIE bit is set and the interrupt mask
in the CC register is reset (RIM instruction).
M
Table 11.
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AVD interrupt control/wake-up capability
Interrupt event
Event flag
AVD event
AVDF
Enable Control bit Exit from WAIT
AVDIE
Doc ID13466 Rev 4
Yes
Exit from HALT
No
ST72324B-Auto
Supply, reset and clock management
6.6
SI registers
6.6.1
System integrity (SI) control/status register (SICSR)
SICSR
Reset value: 000x 000x (00h)
7
6
5
4
Res
AVDIE
AVDF
LVDRF
Reserved
WDGRF
-
R/W
RO
R/W
-
R/W
Table 12.
Bit
Name
7
-
3
2
1
0
SICSR register description
Function
Reserved, must be kept cleared
AVDIE
Voltage Detector Interrupt Enable
This bit is set and cleared by software. It enables an interrupt to be generated
when the AVDF flag changes (toggles). The pending interrupt information is
automatically cleared when software enters the AVD interrupt routine
0: AVD interrupt disabled
1: AVD interrupt enabled
5
AVDF
Voltage Detector Flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an
interrupt request is generated when the AVDF bit changes value. Refer to
Figure 15 and to Section 6.5.2: AVD (auxiliary voltage detector) for additional
details.
0: VDD over VIT+(AVD) threshold
1: VDD under VIT-(AVD) threshold
4
LVD Reset Flag
This bit indicates that the last reset was generated by the LVD block. It is set by
LVDRF
hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag
description for more details. When the LVD is disabled by option byte, the LVDRF
bit value is undefined.
6
3:1
0
-
Reserved, must be kept cleared
Watchdog Reset Flag
This bit indicates that the last reset was generated by the Watchdog peripheral. It is
WDGRF
set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD
reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF information, the flag description is given in Table 13.
Table 13.
Reset source flags
Reset sources
LVDRF
WDGRF
External RESET pin
0
0
Watchdog
0
1
LVD
1
X
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Application notes
The LVDRF flag is not cleared when another reset type occurs (external or watchdog); the
LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset
can be detected by software while an external reset cannot.
Caution:
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When the LVD is not activated with the associated option byte, the WDGRF flag can not be
used in the application.
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Interrupts
7
Interrupts
7.1
Introduction
The ST7 enhanced interrupt management provides the following features:
●
Hardware interrupts
●
Software interrupt (TRAP)
●
Nested or concurrent interrupt management with flexible interrupt priority and level
management:
–
up to 4 software programmable nesting levels
–
up to 16 interrupt vectors fixed by hardware
–
2 non-maskable events: reset, TRAP
This interrupt management is based on:
●
Bit 5 and bit 3 of the CPU CC register (I1:0)
●
Interrupt software priority registers (ISPRx)
●
Fixed interrupt vector addresses located at the high addresses of the memory map
(FFE0h to FFFFh) sorted by hardware priority order
This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.
7.2
Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx
registers which give the interrupt software priority level of each interrupt vector (see
Table 14). The processing flow is shown in Figure 16.
When an interrupt request has to be serviced:
●
Normal processing is suspended at the end of the current instruction execution.
●
The PC, X, A and CC registers are saved onto the stack.
●
I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx
registers of the serviced interrupt vector.
●
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to Table 25: Interrupt
mapping for vector addresses).
The interrupt service routine should end with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note:
As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
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Table 14.
Interrupt software priority levels
Interrupt software priority
Level
I1
I0
Low
1
0
Level 1
0
1
Level 2
0
0
1
1
Level 0 (main)
Level 3 (= interrupt disable)
High
Figure 16. Interrupt processing flowchart
Pending
Reset
Y
TRAP
Interrupt
Fetch next
Instruction
Y
The interrupt
stays pending
“IRET”
N
RESTORE PC, X, A, CC
from stack
7.2.1
Execute
instruction
N
I1:0
Interrupt has a higher
software priority
than current one
Interrupt has the same or a
lower software priority
than current one
N
Y
Stack PC, X, A, CC
load I1:0 from interrupt SW reg.
load PC from interrupt vector
Servicing pending interrupts
As several interrupts can be pending at the same time, the interrupt to be taken into account
is determined by the following two-step process:
●
the highest software priority interrupt is serviced,
●
if several interrupts have the same software priority then the interrupt with the highest
hardware priority is serviced first.
Figure 17 describes this decision process.
Figure 17. Priority decision process flowchart
PENDING
INTERRUPTS
Same
SOFTWARE
PRIORITY
Different
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
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Interrupts
When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.
Note:
7.2.2
1
The hardware priority is exclusive while the software one is not. This allows the previous
process to succeed with only one interrupt.
2
Reset and TRAP can be considered as having the highest software priority in the decision
process.
Different interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (reset, TRAP) and the maskable type (external or from internal peripherals).
7.2.3
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see Figure 16). After stacking the PC, X, A and CC registers (except for reset), the
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit Halt mode.
TRAP (non-maskable software interrupt)
This software interrupt is serviced when the TRAP instruction is executed. It will be serviced
according to the flowchart in Figure 16.
Reset
The reset source has the highest priority in the ST7. This means that the first current routine
has the highest software priority (level 3) and the highest hardware priority.
See the reset chapter for more details.
7.2.4
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
External interrupts
External interrupts allow the processor to Exit from Halt low power mode. External interrupt
sensitivity is software selectable through the External Interrupt Control register (EICR).
External interrupt triggered on edge will be latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these will be logically ORed.
Peripheral interrupts
Usually the peripheral interrupts cause the MCU to Exit from Halt mode except those
mentioned in Table 25: Interrupt mapping. A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the corresponding enable bit is set in the
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peripheral control register. The general sequence for clearing an interrupt is based on an
access to the status register followed by a read or write to an associated register.
Note:
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be
serviced) is therefore lost if the clear sequence is executed.
7.3
Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column Exit from HALT in Table 25: Interrupt mapping). When several pending interrupts are
present while exiting Halt mode, the first one serviced can only be an interrupt with Exit from
Halt mode capability and it is selected through the same decision process shown in
Figure 17.
Note:
If an interrupt, that is not able to exit from Halt mode, is pending with the highest priority
when exiting Halt mode, this interrupt is serviced after the first one serviced.
7.4
Concurrent and nested management
Figure 18 and Figure 19 show two different interrupt management modes. The first is called
concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode
in Figure 19. The interrupt hardware priority is given in order from the lowest to the highest
as follows: MAIN, IT4, IT3, IT2, IT1, IT0. Software priority is given for each interrupt.
Warning:
A stack overflow may occur without notifying the software of
the failure.
Hardware priority
TRAP
3
IT0
IT1
IT1
IT2
IT3
RIM
IT4
Main
Main
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I1
10
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I0
1 1
3
1 1
3
1 1
3
1 1
3
1 1
3
1 1
3/0
Used stack = 10 bytes
Software
priority
level
IT0
TRAP
IT3
IT4
IT1
IT2
Figure 18. Concurrent interrupt management
ST72324B-Auto
Interrupts
I1
Hardware priority
TRAP
IT0
IT1
IT1
IT2
IT2
IT3
RIM
IT4
IT4
Main
11 / 10
Main
I0
3
1 1
3
1 1
2
0 0
1
0 1
3
1 1
3
1 1
Used stack = 20 bytes
Software
priority
level
IT0
TRAP
IT3
IT4
IT1
IT2
Figure 19. Nested interrupt management
3/0
10
7.5
Interrupt registers
7.5.1
CPU CC register interrupt bits
CPU CC
Reset value: 111x 1010(xAh)
7
6
5
4
3
2
1
0
1
1
I1
H
I0
N
Z
C
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
Table 15.
CPU CC register interrupt bits description
Bit Name
Function
5
I1
Software Interrupt Priority 1
3
I0
Software Interrupt Priority 0
Table 16.
Interrupt software priority levels
Interrupt software priority
Level 0 (main)
Level
I1
I0
Low
1
0
0
1
0
0
1
1
Level 1
Level 2
Level 3 (= interrupt
disable)(1)
High
1. TRAP and RESET events can interrupt a level 3 program.
These two bits indicate the current interrupt software priority (see Table 16) and are
set/cleared by hardware when entering in interrupt. The loaded value is given by the
corresponding bits in the interrupt software priority registers (ISPRx).
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They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see Table 18: Dedicated interrupt instruction set).
7.5.2
Interrupt software priority registers (ISPRx)
ISPRx
Reset value: 1111 1111 (FFh)
7
6
5
4
3
2
1
0
ISPR0
I1_3
I0_3
I1_2
I0_2
I1_1
I0_1
I1_0
I0_0
ISPR1
I1_7
I0_7
I1_6
I0_6
I1_5
I0_5
I1_4
I0_4
ISPR2
I1_11
I0_11
I1_10
I0_10
I1_9
I0_9
I1_8
I0_8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
I1_13
I0_13
I1_12
I0_12
RO
RO
RO
RO
R/W
R/W
R/W
R/W
ISPR3
These four registers contain the interrupt software priority of each interrupt vector.
●
Each interrupt vector (except reset and TRAP) has corresponding bits in these
registers where its own software priority is stored. This correspondence is shown in the
following Table 17.
Table 17.
ISPRx interrupt vector correspondence
Vector address
ISPRx bits
FFFBh-FFFAh
I1_0 and I0_0 bits
FFF9h-FFF8h
I1_1 and I0_1 bits
...
...
FFE1h-FFE0h
I1_13 and I0_13 bits
●
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1
and I0 bits in the CC register.
●
Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value
is kept (for example, previous value = CFh, write = 64h, result = 44h).
The reset, and TRAP vectors have no software priorities. When one is serviced, the I1 and
I0 bits of the CC register are both set.
Caution:
If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior
has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
Table 18.
Instruction
HALT
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Dedicated interrupt instruction set(1)
New description
Function/example
Entering HALT mode
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I1
1
H
I0
0
N
Z
C
ST72324B-Auto
Table 18.
Instruction
Interrupts
Dedicated interrupt instruction set(1) (continued)
New description
Function/example
I1
H
I0
N
Z
C
I1
H
I0
N
Z
C
I1
H
I0
N
Z
C
IRET
Interrupt routine return
POP CC, A, X, PC
JRM
Jump if I1:0=11 (level 3)
I1:0=11 ?
JRNM
Jump if I1:011
I1:011 ?
POP CC
POP CC from the Stack
Mem => CC
RIM
Enable interrupt (level 0 set) Load 10 in I1:0 of CC
1
0
SIM
Disable interrupt (level 3 set) Load 11 in I1:0 of CC
1
1
TRAP
Software TRAP
1
1
WFI
WAIT for interrupt
1
0
Software NMI
1. During the execution of an interrupt routine, the HALT, POP CC, RIM, SIM and WFI instructions change
the current software priority up to the next IRET instruction or one of the previously mentioned instructions.
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7.6
External interrupts
7.6.1
I/O port interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register (Figure 20). This control allows up to four fully independent external interrupt source
sensitivities.
Each external interrupt source can be generated on four (or five) different events on the pin:
●
Falling edge
●
Rising edge
●
Falling and rising edge
●
Falling edge and low level
●
Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that
interrupts must be disabled before changing sensitivity.
The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits
of the EICR.
Figure 20. External interrupt control bits
Port A3 interrupt
PAOR.3
PADDR.3
EICR
IS20
IS21
ei0 interrupt source
Sensitivity
control
PA3
IPA BIT
Port F [2:0] interrupts
PFOR.2
PFDDR.2
PF2
Port B [3:0] interrupts
PBOR.3
PBDDR.3
EICR
IS20
IS21
Sensitivity
control
IS10
IS11
IPB BIT
Port B4 interrupt
PBOR.4
PBDDR.4
PB4
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ei1 interrupt source
EICR
Sensitivity
control
PB3
PF2
PF1
PF0
PB3
PB2
PB1
PB0
ei2 interrupt source
EICR
IS10
IS11
Sensitivity
control
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ei3 interrupt source
ST72324B-Auto
7.6.2
Interrupts
External interrupt control register (EICR)
EICR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
IS11
IS10
IPB
IS21
IS20
IPA
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
-
Table 19.
Bit
1
0
EICR register description
Name
Function
ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following
external interrupts:
7:6 IS1[1:0]
- ei2 for port B [3:0] (see Table 20)
- ei3 for port B4 (see Table 21
Bits 7 and 6 can only be written when I1 and I0 of the CC register are both set to 1
(level 3).
5
IPB
Interrupt Polarity (for port B)
This bit is used to invert the sensitivity of port B [3:0] external interrupts. It can be
set and cleared by software only when I1 and I0 of the CC register are both set to 1
(level 3).
0: No sensitivity inversion
1: Sensitivity inversion
ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following
external interrupts:
4:3 IS2[1:0]
- ei0 for port A[3:0] (see Table 22)
- ei1 for port F[2:0] (see Table 23)
Bits 4 and 3 can only be written when I1 and I0 of the CC register are both set to 1
(level 3).
2
IPA
1:0
-
Table 20.
Interrupt Polarity (for port A)
This bit is used to invert the sensitivity of port A [3:0] external interrupts. It can be
set and cleared by software only when I1 and I0 of the CC register are both set to 1
(level 3).
0: No sensitivity inversion.
1: Sensitivity inversion.
Reserved, must always be kept cleared
Interrupt sensitivity - ei2
External interrupt sensitivity
IS11
IS10
IPB bit = 0
IPB bit = 1
0
0
Falling edge and low level
Rising edge and high level
0
1
Rising edge only
Falling edge only
1
0
Falling edge only
Rising edge only
1
1
Rising and falling edge
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Table 21.
Interrupt sensitivity - ei3
IS11
IS10
External interrupt sensitivity
0
0
Falling edge and low level
0
1
Rising edge only
1
0
Falling edge only
1
1
Rising and falling edge
Table 22.
Interrupt sensitivity - ei0
External interrupt sensitivity
IS21
IS20
IPA bit = 0
IPA bit = 1
0
0
Falling edge and low level
Rising edge and high level
0
1
Rising edge only
Falling edge only
1
0
Falling edge only
Rising edge only
1
1
Table 23.
Rising and falling edge
Interrupt sensitivity - ei1
IS21
IS20
External interrupt sensitivity
0
0
Falling edge and low level
0
1
Rising edge only
1
0
Falling edge only
1
1
Rising and falling edge
Table 24.
Nested interrupts register map and reset values
Address (Hex.)
Register label
7
6
5
4
ei1
0024h
ISPR0
reset value
I1_3
1
ei0
I0_3
1
I1_2
1
3
1
0
1
1
MCC + SI
I0_2
1
I1_1
1
SPI
I0_1
1
ei3
ei2
0025h
ISPR1
reset value
0026h
ISPR2
reset value
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
0027h
ISPR3
reset value
1
1
1
1
I1_13
1
I0_13
1
I1_12
1
I0_12
1
0028h
EICR
reset value
IS11
0
IS10
0
IPB
0
IS21
0
IS20
0
IPA
0
0
0
I1_7
1
I0_7
1
I1_6
1
AVD
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2
I0_6
1
SCI
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I1_5
1
I0_5
1
Timer B
I1_4
1
I0_4
1
Timer A
ST72324B-Auto
Table 25.
No.
Interrupts
Interrupt mapping
Source
block
Reset
Register Priority
Exit from
label
order Halt/Active Halt
Description
Reset
Address vector
yes
FFFEh-FFFFh
no
FFFCh-FFFDh
N/A
TRAP
Software interrupt
0
Not used
Main clock controller time base
interrupt
1
MCC/RTC
2
ei0
External interrupt port A3..0
3
ei1
External interrupt port F2..0
FFFAh-FFFBh
MCCSR
Higher
priority
yes
FFF8h-FFF9h
yes
FFF6h-FFF7h
yes
FFF4h-FFF5h
N/A
4
ei2
External interrupt port B3..0
yes
FFF2h-FFF3h
5
ei3
External interrupt port B7..4
yes
FFF0h-FFF1h
6
Not used
7
SPI
8
Timer A
9
Timer B
10
11
FFEEh-FFEFh
SPI peripheral interrupts
SPICSR
yes
FFECh-FFEDh
Timer A peripheral interrupts
TASR
no
FFEAh-FFEBh
Timer B peripheral interrupts
TBSR
no
FFE8h-FFE9h
SCI
SCI peripheral interrupts
SCISR
no
FFE6h-FFE7h
AVD
Auxiliary voltage detector interrupt
SICSR
no
FFE4h-FFE5h
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8
Power saving modes
8.1
Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 21): Slow, Wait (Slow
Wait), Active Halt and Halt.
After a reset the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided or multiplied by 2 (fOSC2).
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 21. Power saving mode transitions
High
Run
Slow
Wait
Slow Wait
Active Halt
Halt
Low
Power consumption
8.2
Slow mode
This mode has two targets:
●
To reduce power consumption by decreasing the internal clock in the device,
●
To adapt the internal clock frequency (fCPU) to the available supply voltage.
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select the internal slow frequency (fCPU).
In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU
and peripherals are clocked at this lower frequency (fCPU).
Note:
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Slow-Wait mode is activated when entering the Wait mode while the device is already in
Slow mode.
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Figure 22. Slow mode clock transitions
fOSC2/2
fOSC2/4
fOSC2
fCPU
MCCSR
fOSC2
CP1:0
00
01
SMS
Normal Run mode request
New Slow
frequency
request
8.3
Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced
to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU
remains in Wait mode until an interrupt or reset occurs, whereupon the Program Counter
branches to the starting address of the interrupt or reset service routine. The MCU will
remain in Wait mode until a reset or an interrupt occurs, causing it to wake up. Refer to
Figure 23.
Figure 23. Wait mode flowchart
WFI instruction
Oscillator
Peripherals
CPU
I[1:0] bits
on
on
off
10
N
Reset
Y
N
Interrupt
Y
Oscillator
Peripherals
CPU
I[1:0] bits
on
off
on
10
256 or 4096 CPU clock
cycle delay
Oscillator
Peripherals
CPU
I[1:0] bits
on
on
on
XX(1)
Fetch reset vector
or service interrupt
1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
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Power saving modes
8.4
ST72324B-Auto
Active Halt and Halt modes
Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active
Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in the MCCSR
register).
Table 26.
MCC/RTC low power mode selection
MCCSR OIE bit
8.4.1
Power saving mode entered when HALT instruction is executed
0
Halt mode
1
Active Halt mode
Active Halt mode
Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock
Controller Status register (MCCSR) is set (see Section 10.2: Main clock controller with realtime clock and beeper (MCC/RTC) on page 69 for more details on the MCCSR register).
The MCU can exit Active Halt mode on reception of either an MCC/RTC interrupt, a specific
interrupt (see Table 25: Interrupt mapping) or a reset. When exiting Active Halt mode by
means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation
by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 25).
When entering Active Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in Active Halt mode is provided by the oscillator
interrupt.
Note:
As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),
entering Active Halt mode while the Watchdog is active does not generate a reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Caution:
When exiting Active Halt mode following an interrupt, OIE bit of MCCSR register must not be
cleared before tDELAY after the interrupt occurs (tDELAY = 256 or 4096 tCPU delay depending
on option byte). Otherwise, the ST7 enters Halt mode for the remaining tDELAY period.
Figure 24. Active Halt timing overview
Run
Active
Halt
Halt
instruction
[MCCSR.OIE = 1]
256 or 4096 CPU
cycle delay(1)
Reset
or
interrupt
Run
Fetch
vector
1. This delay occurs only if the MCU exits Active Halt mode by means of a reset.
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Figure 25. Active Halt mode flowchart
Halt instruction
(MCCSR.OIE = 1)
Oscillator
Peripherals(1)
CPU
I[1:0] bits
N
N
Reset
Y
Interrupt(2)
Y
on
off
off
10
Oscillator
Peripherals
CPU
I[1:0] bits
on
off
on
XX(3)
256 or 4096 CPU clock
cycle delay
Oscillator
Peripherals
CPU
I[1:0] bits
on
on
on
XX(3)
Fetch reset vector
or service interrupt
1. Peripheral clocked with an external clock source can still be active.
2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from Active Halt mode (such as
external interrupt). Refer to Table 25: Interrupt mapping on page 51 for more details.
3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and restored when the CC register is
popped.
8.4.2
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status
register (MCCSR) is cleared (see Section 10.2: Main clock controller with real-time clock
and beeper (MCC/RTC) on page 69for more details on the MCCSR register).
The MCU can exit Halt mode on reception of either a specific interrupt (see Table 25:
Interrupt mapping) or a reset. When exiting Halt mode by means of a reset or an interrupt,
the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to
stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the
interrupt or by fetching the reset vector which woke it up (see Figure 27).
When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog reset (see Section 14.1 on page 179) for more
details.
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Power saving modes
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Figure 26. HALT timing overview
Run
256 or 4096 CPU
cycle delay
Halt
Run
Reset
or
interrupt
Halt
instruction
[MCCSR.OIE = 0]
Fetch
vector
Figure 27. Halt mode flowchart
Halt instruction
(MCCSR.OIE = 0)
Enable
WDGHALT(1)
Watchdog
Disable
0
1
Watchdog
reset
Oscillator
Peripherals(2)
CPU
I[1:0] bits
off
off
off
10
N
Reset
N
Y
Interrupt(3)
Y
Oscillator
Peripherals
CPU
I[1:0] bits
on
off
on
XX(4)
256 or 4096 CPU clock
cycle delay
Oscillator
Peripherals
CPU
I[1:0] bits
on
on
on
XX(4)
Fetch reset vector
or service interrupt
1. WDGHALT is an option bit. See Section 14.1 on page 179 for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
Table 25: Interrupt mappingfor more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
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Power saving modes
Halt mode recommendations
●
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
●
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
●
For the same reason, reinitialize the sensitivity level of each external interrupt as a
precautionary measure.
●
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
●
As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,
the user may choose to clear all pending interrupt bits before executing the HALT
instruction. This avoids entering other peripheral interrupt routines after executing the
external interrupt routine corresponding to the wake-up event (reset or external
interrupt).
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I/O ports
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9
I/O ports
9.1
Introduction
The I/O ports offer different functional modes:
●
transfer of data through digital inputs and outputs,
and for specific pins:
●
external interrupt generation,
●
alternate signal input/output for the on-chip peripherals.
An I/O port contains up to 8 pins. Each pin can be programmed independently as digital
input (with or without interrupt generation) or digital output.
9.2
Functional description
Each port has two main registers:
●
Data Register (DR)
●
Data Direction Register (DDR)
and one optional register:
●
Option Register (OR)
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers: bit X corresponding to pin X of the port. The same correspondence is used for the
DR register.
The following description takes into account the OR register, (for specific ports which do not
provide this register refer to Section 9.3: I/O port implementation on page 62). The generic
I/O block diagram is shown in Figure 28.
9.2.1
Input modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Note:
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1
Writing the DR register modifies the latch value but does not affect the pin status.
2
When switching from input to output mode, the DR register has to be written first to drive the
correct level on the pin as soon as the port is configured as an output.
3
Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this
might corrupt the DR content for I/Os configured as input.
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I/O ports
External interrupt function
When an I/O is configured as ‘Input with Interrupt’, an event on this I/O can generate an
external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the EICR register.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout
description and interrupt section). If several input pins are selected simultaneously as
interrupt sources, these are first detected according to the sensitivity bits in the EICR
register and then logically ORed.
The external interrupts are hardware interrupts, which means that the request latch (not
accessible directly by the application) is automatically cleared when the corresponding
interrupt vector is fetched. To clear an unwanted pending interrupt by software, the
sensitivity bits in the EICR register must be modified.
9.2.2
Output modes
The output configuration is selected by setting the corresponding DDR register bit. In this
case, writing the DR register applies this digital value to the I/O pin through the latch. Then
reading the DR register returns the previously stored value.
Two different output modes can be selected by software through the OR register: Output
push-pull and open-drain.
Table 27.
9.2.3
DR register value and output pin status
DR
Push-pull
Open-drain
0
VSS
VSS
1
VDD
Floating
Alternate functions
When an on-chip peripheral is configured to use a pin, the alternate function is automatically
selected. This alternate function takes priority over the standard I/O programming.
When the signal is coming from an on-chip peripheral, the I/O pin is automatically
configured in output mode (push-pull or open drain according to the peripheral).
When the signal is going to an on-chip peripheral, the I/O pin must be configured in input
mode. In this case, the pin state is also digitally readable by addressing the DR register.
Note:
Input pull-up configuration can cause unexpected value at the input of the alternate
peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to
be configured in input floating mode.
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Figure 28. I/O port general block diagram
Alternate
output
Register
access
1
VDD
0
Alternate
enable
P-buffer
(see table 24 below)
Pull-up
(see table 24 below)
DR
VDD
DDR
Pull-up
condition
Data bus
OR
Pad
If implemented
OR SEL
N-buffer
Diodes
(see table 24 below)
DDR SEL
DR SEL
Analog
input
CMOS
Schmitt
trigger
1
0
Alternate
input
External
interrupt
source (eix)
Table 28.
I/O port mode options
Diodes
Configuration mode
Pull-up
Floating with/without Interrupt
Off(3)
Pull-up with/without Interrupt
On(4)
Input
P-buffer
to VDD(1)
to VSS(2)
Off
On
Push-pull
On
On
Off
Output
Open drain (logic level)
True open drain
Off
NI
NI
NI(5)
1. The diode to VDD is not implemented in the true open drain pads.
2. A local protection between the pad and VSS is implemented to protect the device against positive stress.
3. Off = implemented not activated.
4. On = implemented and activated.
5. NI = not implemented
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I/O ports
Table 29.
I/O port configurations
Hardware configuration
Not implemented in
true open drain
I/O ports
DR register access
VDD
RPU
Pull-up
condition
DR
register
W
Data bus
Pad
R
Alternate input
External interrupt
source (eix)
Input(1)
Interrupt
condition
Analog input
Open-drain output(2)
Not implemented in
true open drain
I/O ports
RPU
DR
register
Pad
Alternate
enable
Not implemented in
true open drain
I/O ports
PUSH-pull output(2)
DR register access
VDD
R/W
Data bus
Alternate
output
DR register access
VDD
RPU
DR
R/W
register
Pad
Alternate
enable
Data bus
Alternate
output
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
Caution:
The alternate function must not be activated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious interrupts.
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Analog alternate function
When the pin is used as an ADC input, the I/O must be configured as floating input. The
analog multiplexer (controlled by the ADC registers) switches the analog voltage present on
the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level or loading on any port pin while
conversion is in progress. Furthermore it is recommended not to have clocking pins located
close to a selected analog pin.
Warning:
9.3
The analog input voltage level must be within the limits
stated in the absolute maximum ratings.
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 29.
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation.
Figure 29. Interrupt I/O port state transitions
01
00
Input
Input
floating
floating/pull-up
(reset state)
interrupt
10
11
Output
open-drain
Output
push-pull
XX
9.4
Low power modes
Table 30.
Effect of low power modes on I/O ports
Mode
9.5
= DDR, OR
Description
Wait
No effect on I/O ports. External interrupts cause the device to exit from Wait mode.
Halt
No effect on I/O ports. External interrupts cause the device to exit from Halt mode.
Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and the interrupt mask in the CC register is not active
(RIM instruction).
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I/O ports
Table 31.
9.5.1
I/O port interrupt control/wake-up capability
Interrupt event
Event flag
External interrupt on selected
external event
-
Enable Control bit Exit from WAIT Exit from HALT
DDRx, ORx
Yes
Yes
I/O port implementation
The I/O port register configurations are summarized Table 32.
Table 32.
Port configuration
Input (DDR = 0)
Port
OR = 0
PA7:6
Port A
Output (DDR = 1)
Pin name
OR = 1
OR = 0
Floating
OR = 1
True open-drain (high sink)
PA5:4
Floating
Pull-up
Open drain
Push-pull
PA3
Floating
Floating interrupt
Open drain
Push-pull
PB3
Floating
Floating interrupt
Open drain
Push-pull
PB4, PB2:0
Floating
Pull-up
Open drain
Push-pull
Port C
PC7:0
Floating
Pull-up
Open drain
Push-pull
Port D
PD5:0
Floating
Pull-up
Open drain
Push-pull
Port E
PE1:0
Floating
Pull-up
Open drain
Push-pull
PF7:6, 4
Floating
Pull-up
Open drain
Push-pull
PF2:0
Floating
Pull-up
Open drain
Push-pull
Port B
Port F
Table 33.
I/O port register map and reset values
Address (Hex.)
Register label
7
6
5
4
3
2
1
0
Reset value of all I/O port registers
0
0
0
0
0
0
0
0
0000h
PADR
0001h
PADDR
0002h
PAOR
0003h
PBDR
0004h
PBDDR
0005h
PBOR
0006h
PCDR
0007h
PCDDR
0008h
PCOR
0009h
PDDR
000Ah
PDDDR
000Bh
PDOR
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
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I/O ports
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Table 33.
I/O port register map and reset values (continued)
Address (Hex.)
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Register label
000Ch
PEDR
000Dh
PEDDR
000Eh
PEOR
000Fh
PFDR
0010h
PFDDR
0011h
PFOR
7
6
5
4
3
2
1
0
MSB
LSB
MSB
LSB
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On-chip peripherals
10
On-chip peripherals
10.1
Watchdog timer (WDG)
10.1.1
Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before the T6 bit becomes cleared.
10.1.2
10.1.3
Main features
●
Programmable free-running downcounter
●
Programmable reset
●
Reset (if Watchdog activated) when the T6 bit reaches zero
●
Optional reset on HALT instruction (configurable by option byte)
●
Hardware Watchdog selectable by option byte
Functional description
The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is
decremented every 16384 fOSC2 cycles (approx.), and the length of the timeout period can
be programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin
for typically 30µs.
The application program must write in the WDGCR register at regular intervals during
normal operation to prevent an MCU reset. This downcounter is free-running: it counts down
even if the watchdog is disabled. The value to be stored in the WDGCR register must be
between FFh and C0h:
●
The WDGA bit is set (Watchdog enabled)
●
The T6 bit is set to prevent generating an immediate reset
●
The T[5:0] bits contain the number of increments which represents the time delay
before the Watchdog produces a reset (see Figure 31: Approximate timeout duration).
The timing varies between a minimum and a maximum value due to the unknown
status of the prescaler when writing to the WDGCR register (see Figure 32).
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the Watchdog is activated, the HALT instruction generates a reset.
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Figure 30. Watchdog block diagram
Reset
fOSC2
MCC/RTC
Watchdog Control register (WDGCR)
Div 64
T6
WDGA
T5
T4
T2
T3
T1
T0
6-bit downcounter (CNT)
12-bit MCC
RTC counter
LSB
MSB
11
10.1.4
6 5
0
WDG prescaler
div 4
TB[1:0] bits
(MCCSR
register)
How to program the Watchdog timeout
Figure 31 shows the linear relationship between the 6-bit value to be loaded in the
Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be
used for a quick calculation without taking the timing variations into account. If more
precision is needed, use the formulae in Figure 32.
Caution:
When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 31. Approximate timeout duration
3F
38
30
CNT value (Hex.)
28
20
18
10
08
00
1.5
18
34
50
65
82
Watchdog timeout (ms) @ 8 MHz. fOSC2
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128
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On-chip peripherals
Figure 32. Exact timeout duration (tmin and tmax)
WHERE:
tmin0 = (LSB + 128) x 64 x tOSC2
tmax0 = 16384 x tOSC2
tOSC2 = 125ns if fOSC2 = 8 MHz
CNT = value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR
register
TB1 bit
(MCCSR reg.)
TB0 bit
(MCCSR reg.)
Selected MCCSR timebase
MSB
LSB
0
0
2ms
4
59
0
1
4ms
8
53
1
0
10ms
20
35
1
1
25ms
49
54
To calculate the minimum Watchdog timeout (tmin):
MSB
IF CNT < ------------4
ELSE t
min
= t
THEN
min0
t min = t min0 + 16384 CNT t osc2
4CNT
4CNT
+ 16384 CNT – ----------------- + 192 + LSB 64 ----------------
MSB
MSB
t
osc2
To calculate the maximum Watchdog timeout (tmax):
MSB
IF CNT ------------4
THEN
t max = t max0 + 16384 CNT t osc2
4CNT
4CNT
ELSE t
--------------------------------max = t max0 + 16384 CNT – MSB + 192 + LSB 64 MSB
t osc2
NOTE: In the above formulae, division results must be rounded down to the next integer value.
EXAMPLE: With 2ms timeout selected in MCCSR register
Value of T[5:0] bits in WDGCR register
(Hex.)
Min. Watchdog timeout (ms)
tmin
Max. Watchdog timeout (ms)
tmax
00
1.496
2.048
3F
128
128.552
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On-chip peripherals
10.1.5
ST72324B-Auto
Low power modes
Table 34.
Effect of lower power modes on Watchdog
Mode
Description
Slow
No effect on Watchdog
Wait
OIE bit in
WDGHALT bit in
MCCSR register
option byte
0
0
No Watchdog reset is generated. The MCU enters
Halt mode. The Watchdog counter is decremented
once and then stops counting and is no longer able to
generate a watchdog reset until the MCU receives an
external interrupt or a reset.
If an external interrupt is received, the Watchdog
restarts counting after 256 or 4096 CPU clocks. If a
reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by
option byte. For application recommendations, see
Section 10.1.7 below.
0
1
A reset is generated.
x
No reset is generated. The MCU enters Active Halt
mode. The Watchdog counter is not decremented. It
stop counting. When the MCU receives an oscillator
interrupt or external interrupt, the Watchdog restarts
counting immediately. When the MCU receives a
reset the Watchdog restarts counting after 256 or
4096 CPU clocks.
Halt
1
10.1.6
Hardware Watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to the option byte description in Section 14.1:
Flash devices.
10.1.7
Using Halt mode with the WDG (WDGHALT option)
The following recommendation applies if Halt mode is used when the watchdog is enabled:
Before executing the HALT instruction, refresh the WDG counter to avoid an unexpected
WDG reset immediately after waking up the microcontroller.
10.1.8
Interrupts
None.
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10.1.9
On-chip peripherals
Control register (WDGCR)
WDGCR
7
Reset value: 0111 1111 (7F h)
6
5
3
WDGA
T[6:0]
R/W
R/W
Table 35.
Bit
2
1
0
WDGCR register description
Name
Function
7
Activation bit
This bit is set by software and only cleared by hardware after a reset. When
WDGA = 1, the watchdog can generate a reset.
WDGA
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
6:0
7-bit counter (MSB to LSB)
These bits contain the value of the Watchdog counter, which is decremented every
T[6:0]
16384 fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh
(T6 is cleared).
Table 36.
Watchdog timer register map and reset values
Address (Hex.) Register label
002Ah
10.2
4
WDGCR
reset value
7
6
5
4
3
2
1
0
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
Main clock controller with real-time clock and beeper
(MCC/RTC)
The main clock controller consists of three different functions:
●
a programmable CPU clock prescaler
●
a clock-out signal to supply external devices
●
a real-time clock timer with interrupt capability
Each function can be used independently and simultaneously.
10.2.1
Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal
peripherals. It manages Slow power saving mode (see Section 8.2: Slow mode on page 52
for more details).
The prescaler selects the fCPU main clock frequency and is controlled by three bits in the
MCCSR register: CP[1:0] and SMS.
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On-chip peripherals
10.2.2
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Clock-out capability
The clock-out capability is an alternate function of an I/O port pin that outputs the fCPU clock
to drive external devices. It is controlled by the MCO bit in the MCCSR register.
Caution:
When selected, the clock out pin suspends the clock during Active Halt mode.
10.2.3
Real-time clock (RTC) timer
The counter of the real-time clock timer allows an interrupt to be generated based on an
accurate real-time clock. Four different time bases depending directly on fOSC2 are available.
The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and
OIF.
When the RTC interrupt is enabled (OIE bit set), the ST7 enters Active Halt mode when the
HALT instruction is executed. See Section 8.4: Active Halt and Halt modes on page 54for
more details.
10.2.4
Beeper
The beep function is controlled by the MCCBCR register. It can output three selectable
frequencies on the Beep pin (I/O port alternate function).
Figure 33. Main clock controller (MCC/RTC) block diagram
BC1 BC0
MCCBCR
Beep
Beep signal
selection
MCO
12-bit MCC RTC
counter
Div 64
To
Watchdog
timer
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
MCCSR
fOSC2
Div 2, 4, 8, 16
MCC/RTC interrupt
1
0
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CPU clock
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10.2.5
On-chip peripherals
Low power modes
Table 37.
Effect of low power modes on MCC/RTC
Mode
Description
Wait
No effect on MCC/RTC peripheral. MCC/RTC interrupt causes the device to exit
from Wait mode.
No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.
MCC/RTC interrupt causes the device to exit from Active Halt mode.
Active Halt
MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when
the MCU is woken up by an interrupt with Exit from Halt capability.
Halt
10.2.6
Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is
set and the interrupt mask in the CC register is not active (RIM instruction).
Table 38.
MCC/RTC interrupt control/wake-up capability
Interrupt event
Event flag
Time base overflow event
OIF
Enable control bit Exit from WAIT Exit from HALT
OIE
No(1)
Yes
1. The MCC/RTC interrupt wakes up the MCU from Active Halt mode, not from Halt mode.
10.2.7
MCC registers
MCC control/status register (MCCSR)
)
MCCSR
7
6
5
4
3
2
1
0
MCO
CP[1:0]
SMS
TB[1:0]
OIE
OIF
R/W
R/W
R/W
R/W
R/W
R/W
Table 39.
Bit
7
Reset value: 0000 0000 (00h)
MCCSR register description
Name
Function
MCO
Main Clock Out selection
This bit enables the MCO alternate function on the PF0 I/O port. It is set and
cleared by software.
0: MCO alternate function disabled (I/O pin free for general-purpose I/O).
1: MCO alternate function enabled (fCPU on I/O port).
Note: To reduce power consumption, the MCO function is not active in Active Halt
mode.
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Table 39.
Bit
MCCSR register description (continued)
Name
Function
CPU Clock Prescaler
These bits select the CPU clock prescaler which is applied in different slow modes.
Their action is conditioned by the setting of the SMS bit. These two bits are set and
cleared by software:
6:5 CP[1:0]
00: fCPU in Slow mode = fOSC2/2
01: fCPU in Slow mode = fOSC2/4
10: fCPU in Slow mode = fOSC2/8
11: fCPU in Slow mode = fOSC2/16
4
3:2
1
SMS
Slow Mode Select
This bit is set and cleared by software.
0: Normal mode. fCPU = fOSC2.
1: Slow mode. fCPU is given by CP1, CP0.
See Section 8.2: Slow mode and Section 10.2: Main clock controller with real-time
clock and beeper (MCC/RTC) for more details.
Time Base control
These bits select the programmable divider time base. They are set and cleared by
TB[1:0]
software (see Table 40). A modification of the time base is taken into account at the
end of the current period (previously set) to avoid an unwanted time shift. This
allows to use this time base as a real-time clock.
OIE
Oscillator interrupt Enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from Active Halt mode. When this bit is set, calling
the ST7 software HALT instruction enters the Active Halt power saving mode
.
0
.
OIF
Table 40.
Oscillator interrupt Flag
This bit is set by hardware and cleared by software reading the MCCSR register. It
indicates when set that the main oscillator has reached the selected elapsed time
(TB1:0).
0: Timeout not reached
1: Timeout reached
Caution: The BRES and BSET instructions must not be used on the MCCSR
register to avoid unintentionally clearing the OIF bit.
Time base selection
Time base
Counter prescaler
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TB1
TB0
2ms
0
0
8ms
4ms
0
1
80000
20ms
10ms
1
0
200000
50ms
25ms
1
1
fOSC2 = 4 MHz
fOSC2 = 8 MHz
16000
4ms
32000
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On-chip peripherals
MCC beep control register (MCCBCR)
MCCBCR
Reset value: 0000 0000 (00h)
7
6
Table 41.
5
4
3
2
1
0
Reserved
BC[1:0]
-
R/W
MCCBCR register description
Bit
Name
7:2
-
Function
Reserved, must be kept cleared
Beep Control
These 2 bits select the PF1 pin beep capability (see Table 42). The beep output
1:0 BC[1:0]
signal is available in Active Halt mode but has to be disabled to reduce the
consumption.
Table 42.
Beep frequency selection
BC1
BC0
Beep mode with fOSC2 = 8 MHz
0
0
Off
0
1
~2 kHz
1
0
~1 kHz
1
1
~500 Hz
Table 43.
Output
Beep signal
~50% duty cycle
Main clock controller register map and reset values
Address
Register label
(Hex.)
7
6
5
4
3
2
1
0
002Bh
SICSR
Reset value
0
AVDIE
0
AVDF
0
LVDRF
x
0
0
0
WDGRF
x
002Ch
MCCSR
Reset value
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
002Dh
MCCBCR
Reset value
0
0
0
0
0
0
BC1
0
BC0
0
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10.3
16-bit timer
10.3.1
Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.
Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and
do not share any resources. They are synchronized after a MCU reset as long as the timer
clock frequencies are not modified.
This description covers one or two 16-bit timers. In ST7 devices with two timers, register
names are prefixed with TA (Timer A) or TB (Timer B).
10.3.2
Main features
●
Programmable prescaler: fCPU divided by 2, 4 or 8
●
Overflow status flag and maskable interrupt
●
External clock input (must be at least four times slower than the CPU clock speed) with
the choice of active edge
●
1 or 2 output compare functions each with:
●
–
2 dedicated 16-bit registers
–
2 dedicated programmable signals
–
2 dedicated status flags
–
1 dedicated maskable interrupt
1 or 2 input capture functions each with:
–
2 dedicated 16-bit registers
–
2 dedicated active edge selection signals
–
2 dedicated status flags
–
1 dedicated maskable interrupt
●
Pulse width modulation mode (PWM)
●
One pulse mode
●
Reduced power mode
●
5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)(c)
The timer block diagram is shown in Figure 34.
c.
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Some timer pins may not be available (not bonded) in some ST7 devices. Refer to Section 2: Pin description.
When reading an input signal on a non-bonded pin, the value will always be ‘1’.
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10.3.3
On-chip peripherals
Functional description
Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
●
●
Counter Register (CR)
–
Counter High Register (CHR) is the most significant byte (MSB)
–
Counter Low Register (CLR) is the least significant byte (LSB)
Alternate Counter Register (ACR)
–
Alternate Counter High Register (ACHR) is the most significant byte (MSB)
–
Alternate Counter Low Register (ACLR) is the least significant byte (LSB)
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the
Status register (SR) (see note at the end of paragraph entitled 16-bit read sequence).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in
the 16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and
PWM mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table 50. The value in the counter register repeats every 131072, 262144 or 524288 CPU
clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4,
fCPU/8 or an external frequency.
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Figure 34. Timer block diagram
ST7 internal bus
fCPU
MCU-peripheral interface
8 low
8
8
low
8
low
8
high
8
high
EXEDG
8
low
8
high
8
high
8-bit
buffer
low
8 high
16
1/2
1/4
1/8
EXTCLK
pin
Output
Compare
register
2
Output
Compare
register
1
Counter
register
Alternate
Counter
register
Input
Capture
register
1
Input
Capture
register
2
16
16
16
CC[1:0]
Timer internal bus
16
Overflow
Detect
circuit
Output Compare
circuit
6
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
16
Edge Detect
circuit 1
ICAP1
pin
Edge Detect
circuit 2
ICAP2
pin
Latch 1
OCMP1
pin
Latch 2
OCMP2
0
(Control/Status register) CSR
pin
ICIE OCIE TOIE FOLV2FOLV1OLVL2 IEDG1OLVL1 OC1E OC2E OPM PWM CC1
(Control register 1) CR1
CC0 IEDG2EXEDG
(Control register 2) CR2
(See note 1)
Timer interrupt
1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table 25:
Interrupt mapping on page 51).
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On-chip peripherals
16-bit read sequence
The 16-bit read sequence (from either the Counter register or the Alternate Counter
register) is illustrated in the followingFigure 35.
Figure 35. 16-bit read sequence
Beginning of the sequence
At t0
LSB is buffered
Read MSB
Other
instructions
At t0 +t
Read LSB
Returns the buffered
LSB value at t0
Sequence completed
The user must first read the MSB, afterwhich the LSB value is automatically buffered.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MSB several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LSB of the count value at the time of the read.
Whatever the timer mode used (input capture, output compare, one pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:
●
The TOF bit of the SR register is set.
●
A timer interrupt is generated if:
–
TOIE bit of the CR1 register is set and
–
I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
Note:
1.
Reading the SR register while the TOF bit is set.
2.
An access (read or write) to the CLR register.
The TOF bit is not cleared by access to the ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a reset).
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External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 36. Counter timing diagram, internal clock divided by 2
CPU clock
Internal reset
Timer clock
Counter register
FFFD FFFE FFFF 0000
0001
0002
0003
Timer Overflow Flag (TOF)
Figure 37. Counter timing diagram, internal clock divided by 4
CPU clock
Internal reset
Timer clock
Counter register
FFFC
FFFD
0000
0001
Timer Overflow Flag (TOF)
Figure 38. Counter timing diagram, internal clock divided by 8
CPU clock
Internal reset
Timer clock
Counter register
FFFC
FFFD
0000
Timer Overflow Flag (TOF)
Note:
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The MCU is in reset state when the internal reset signal is high, when it is low the MCU is
running.
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On-chip peripherals
Input capture
In this section, the index, i, may be 1 or 2 because there are two input capture functions in
the 16-bit timer.
The two 16-bit input capture registers (IC1R/IC2R) are used to latch the value of the free
running counter after a transition is detected on the ICAPi pin (see Figure 40).
Table 44.
Input capture byte distribution
Register
MS byte
LS byte
ICiR
ICiHR
ICiLR
The ICiR registers are read-only registers.
The active transition is software programmable through the IEDGi bit of Control Registers
(CRi).
Timing resolution is one count of the free running counter: (fCPU/CC[1:0]).
Procedure
To use the input capture function select the following in the CR2 register:
●
Select the timer clock (CC[1:0]) (see Table 50).
●
Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2
pin must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
Select the following in the CR1 register:
●
Set the ICIE bit to generate an interrupt after an input capture coming from either the
ICAP1 pin or the ICAP2 pin
●
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input or input with pull-up without interrupt if
this configuration is available).
When an input capture occurs:
●
ICFi bit is set.
●
The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see Figure 40).
●
A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1.
Reading the SR register while the ICFi bit is set
2.
An access (read or write) to the ICiLR register
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On-chip peripherals
Note:
ST72324B-Auto
1
After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never
be set until the ICiLR register is also read.
2
The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
3
The two input capture functions can be used together even if the timer also uses the two
output compare functions.
4
In One pulse mode and PWM mode only Input Capture 2 can be used.
5
The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any
transitions on these pins activates the input capture function.
Moreover if one of the ICAPi pins is configured as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR (see
note 1).
6
The TOF bit can be used with interrupt generation in order to measure events that go
beyond the timer range (FFFFh).
Figure 39. Input capture block diagram
ICAP1
pin
ICAP2
pin
(Control register 1) CR1
Edge Detect
circuit 2
Edge Detect
circuit 1
ICIE
IEDG1
(Status register) SR
IC2R register
IC1R register
ICF1
0
ICF2
CC1
16-bit free running counter
Figure 40. Input capture timing diagram
Timer clock
FF01
FF02
FF03
ICAPi pin
ICAPi flag
FF03
ICAPi register
Note: The rising edge is the active edge.
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0
(Control register 2) CR2
16-bit
Counter register
0
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On-chip peripherals
Output compare
In this section, the index, i, may be 1 or 2 because there are two output compare functions in
the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time
has elapsed.
When a match is found between the Output Compare register and the free running counter,
the output compare function:
●
Assigns pins with a programmable value if the OCiE bit is set
●
Sets a flag in the status register
●
Generates an interrupt if enabled
Two 16-bit registers Output Compare register 1 (OC1R) and Output Compare register 2
(OC2R) contain the value to be compared to the counter register each timer clock cycle.
Table 45.
Output compare byte distribution
Register
MS byte
LS byte
OCiR
OCiHR
OCiLR
These registers are readable and witable and are not affected by the timer hardware. A
reset event changes the OCiR value to 8000h.
Timing resolution is one count of the free running counter: (fCPU/CC[1:0]).
Procedure
To use the Output Compare function, select the following in the CR2 register:
●
Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
●
Select the timer clock (CC[1:0]) (see Table 50).
And select the following in the CR1 register:
●
Select the OLVLi bit to applied to the OCMPi pins after the match occurs.
●
Set the OCIE bit to generate an interrupt if it is needed.
When a match is found between OCRi register and CR register:
●
OCFi bit is set
●
The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset)
●
A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is
cleared in the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using
the following formula:
OCiR =
t * fCPU
PRESC
Where:
t
= Output compare period (in seconds)
fCPU
= CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Table 50)
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If the timer clock is an external clock, the formula is:
OCiR = t * fEXT
Where:
t
fEXT
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:
1.
Reading the SR register while the OCFi bit is set.
2.
An access (read or write) to the OCiLR register.
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OCiR register:
Note:
●
Write to the OCiHR register (further compares are inhibited).
●
Read the SR register (first step of the clearance of the OCFi bit, which may be already
set).
●
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit).
1
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
2
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
3
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see Figure 42 on page 83 for an example with fCPU/2 and
Figure 43 on page 83 for an example with fCPU/4). This behavior is the same in OPM or
PWM mode.
4
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
5
The value in the 16-bit OCiR register and the OLVi bit should be changed after each
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
Forced output compare capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
The FOLVLi bits have no effect in both one pulse mode and PWM mode.
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On-chip peripherals
Figure 41. Output compare block diagram
16-bit free running counter
OC1E OC2E
CC1
CC0
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
Output compare
16-bit
circuit
OCIE
FOLV2FOLV1 OLVL2
OLVL1
16-bit
Latch
1
Latch
2
OC1R register
OCF1
OCF2
OC2R register
0
0
OCMP1
Pin
OCMP2
Pin
0
(Status register) SR
Figure 42. Output compare timing diagram, fTIMER = fCPU/2
Internal CPU clock
Timer clock
Counter register
2ECF 2ED0
Output Compare register i (OCRi)
2ED1 2ED2 2ED3 2ED4
2ED3
Output Compare flag i (OCFi)
OCMPi pin (OLVLi = 1)
Figure 43. Output compare timing diagram, fTIMER = fCPU/4
Internal CPU clock
Timer clock
Counter register
2ECF 2ED0
Output Compare register i (OCRi)
2ED1 2ED2 2ED3 2ED4
2ED3
Output Compare flag i (OCFi)
OCMPi pin (OLVLi = 1)
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On-chip peripherals
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One Pulse mode
One Pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure
To use One Pulse mode:
1.
Load the OC1R register with the value corresponding to the length of the pulse (see the
formula below).
2.
Select the following in the CR1 register:
3.
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
–
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
–
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
Select the following in the CR2 register:
–
Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1
function.
–
Set the OPM bit.
–
Select the timer clock CC[1:0] (see Table 50).
Figure 44. One pulse mode cycle
When
event occurs
on ICAP1
ICR1 = Counter
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
When
counter =
OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
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1.
Reading the SR register while the ICFi bit is set.
2.
An access (read or write) to the ICiLR register.
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On-chip peripherals
The OC1R register value required for a specific timing application can be calculated using
the following formula:
t f
OCiR value = * CPU
-5
PRESC
Where:
t
= Pulse period (in seconds)
fCPU
= CPU clock frequnency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 50)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT - 5
Where:
t
fEXT
= Pulse period (in seconds)
= External timer clock frequency (in hertz)
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin (see Figure 45).
Note:
1
The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
2
When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
3
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
4
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
5
When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the one pulse mode.
Figure 45. One Pulse mode timing example(1)
Counter
2ED3
01F8
IC1R
01F8
FFFC FFFD FFFE
2ED0 2ED1 2ED2
FFFC FFFD
2ED3
ICAP1
OCMP1
OLVL2
OLVL1
OLVL2
Compare1
1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
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Figure 46. Pulse width modulation mode timing example with two output compare
functions(1)(2)
Counter 34E2 FFFC FFFD FFFE
2ED0 2ED1 2ED2
OLVL2
OCMP1
compare2
OLVL1
compare1
34E2
FFFC
OLVL2
compare2
1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
2. On timers with only one Output Compare register, a fixed frequency PWM signal can be generated using
the output compare and the counter overflow to define the pulse length.
Pulse Width Modulation mode
Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse Width Modulation mode uses the complete Output Compare 1 function plus the
OC2R register, and so this functionality can not be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are taken into account only at the end of the
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
Procedure
To use Pulse Width Modulation mode:
1.
Load the OC2R register with the value corresponding to the period of the signal using
the formula below.
2.
Load the OC1R register with the value corresponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column.
3.
Select the following in the CR1 register:
4.
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–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register.
–
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC2R register.
Select the following in the CR2 register:
–
Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
–
Set the PWM bit.
–
Select the timer clock (CC[1:0]) (see Table 50).
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On-chip peripherals
Figure 47. Pulse width modulation cycle
When
counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
When
counter
= OC2R
counter is reset
to FFFCh
ICF1 bit is set
If OLVL1 = 1 and OLVL2 = 0, the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2, a continuous signal will be seen on the OCMP1 pin.
The OC1R register value required for a specific timing application can be calculated using
the following formula:
t f
OCiR value = * CPU
-5
PRESC
Where:
t
= Signal or pulse period (in seconds)
fCPU
= CPU clock frequnency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 50)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT - 5
Where:
t
fEXT
= Signal or pulse period (in seconds)
= External timer clock frequency (in hertz)
The Output Compare 2 event causes the counter to be initialized to FFFCh (see Table 46).
Note:
1
After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
2
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
3
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
4
In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
5
When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
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On-chip peripherals
10.3.4
ST72324B-Auto
Low power modes
Table 46.
Effect of low power modes on 16-bit timer
Mode
10.3.5
Description
Wait
No effect on 16-bit timer.
Timer interrupts cause the device to exit from Wait mode.
Halt
16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes
from the previous count when the MCU is woken up by an interrupt with Exit from Halt
mode capability or from the counter reset value when the MCU is woken up by a reset.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the MCU is woken up by an interrupt with Exit from Halt
mode capability, the ICFi bit is set, and the counter value present when exiting from Halt
mode is captured into the ICiR register.
Interrupts
Table 47.
16-bit timer interrupt control/wake-up capability(1)
Interrupt event
Event flag Enable Control bit Exit from WAIT Exit from HALT
Input Capture 1 event/counter
reset in PWM mode
ICF1
Input Capture 2 event
ICF2
Output Compare 1 event
(not available in PWM mode)
OCF1
Output Compare 2 event
(not available in PWM mode)
OCF2
Timer Overflow event
ICIE
Yes
No
OCIE
TOF
TOIE
1. The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 7: Interrupts).
These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
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10.3.6
On-chip peripherals
Summary of timer modes
Table 48.
Summary of timer modes
Timer resources
Mode
Input
Capture 1
Input
Capture 2
Output
Compare 1
Output
Compare 2
Yes
Yes
Yes
Yes
Input Capture
(1 and/or 2)
Output Compare
(1 and/or 2)
Not recommended(1)
One Pulse mode
No
Not recommended(3)
PWM mode
Partially(2)
No
No
1. See note 4 in One Pulse mode on page 84.
2. See note 5 in One Pulse mode on page 84.
3. See note 4 in Pulse Width Modulation mode on page 86.
10.3.7
16-bit timer registers
Each timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) relating to the two input captures, the two output compares, the
counter and the alternate counter.
Control Register 1 (CR1)
CR1
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
M
Table 49.
Bit
CR1 register description
Name
Function
ICIE
Input Capture Interrupt Enable
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is
set.
6
OCIE
Output Compare Interrupt Enable
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register
is set.
5
TOIE
Timer Overflow Interrupt Enable
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
7
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On-chip peripherals
Table 49.
Bit
ST72324B-Auto
CR1 register description (continued)
Name
Function
4
Forced Output compare 2
This bit is set and cleared by software.
FOLV2
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and
even if there is no successful comparison.
3
Forced Output compare 1
This bit is set and cleared by software.
FOLV1
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if
there is no successful comparison.
2
Output Level 2
This bit is copied to the OCMP2 pin whenever a successful comparison occurs with
OLVL2
the OC2R register and OCxE is set in the CR2 register. This value is copied to the
OCMP1 pin in One Pulse mode and Pulse Width modulation mode.
1
IEDG1
Input Edge 1
This bit determines which type of level transition on the ICAP1 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
0
OLVL1
Output Level 1
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison
occurs with the OC1R register and the OC1E bit is set in the CR2 register.
Control Register 2 (CR2)
CR2
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Reset value: 0000 0000 (00h)
7
6
5
4
OC1E
OC2E
OPM
PWM
R/W
R/W
R/W
R/W
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3
2
1
0
CC[1:0]
IEDG2
EXEDG
R/W
R/W
R/W
ST72324B-Auto
On-chip peripherals
M
Table 50.
Bit
7
6
5
4
3:2
CR2 register description
Name
Function
OCIE
Output Compare 1 Pin Enable
This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in
Output Compare mode, both OLV1 and OLV2 in PWM and One-Pulse mode).
Whatever the value of the OC1E bit, the Output Compare 1 function of the timer
remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
OC2E
Output Compare 2 Pin Enable
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in
Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2
function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
OPM
One Pulse Mode
0: One Pulse mode is not active.
1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the
OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the
generated pulse depends on the contents of the OC1R register.
PWM
Pulse Width Modulation
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the
length of the pulse depends on the value of OC1R register; the period depends on
the value of OC2R register.
Clock Control
The timer clock mode depends on these bits.
00: Timer clock = fCPU/4
01: Timer clock = fCPU/2
CC[1:0]
10: Timer clock = fCPU/8
11: Timer clock = external clock (where available)
Note: If the external clock pin is not available, programming the external clock
configuration stops the counter.
1
Input Edge 2
This bit determines which type of level transition on the ICAP2 pin will trigger the
IEDG2
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
0
External Clock Edge
This bit determines which type of level transition on the external clock pin EXTCLK
EXEDG
will trigger the counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
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Control/Status Register (CSR)
CSR
Reset value: xxxx x0xx (xxh)
7
6
5
4
3
2
ICF1
OCF1
TOF
ICF2
OCF2
TIMD
Reserved
RO
RO
RO
RO
RO
R/W
-
M
Table 51.
0
CSR register description
Bit Name
Function
7
Input Capture Flag 1
0: No Input Capture (reset value).
ICF1
1: An Input Capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) register.
6
Output Compare Flag 1
0: No match (reset value).
OCF1
1: The content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC1R (OC1LR) register.
Timer Overflow Flag
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first
read the SR register, then read or write the low byte of the CR (CLR) register.
Note: Reading or writing the ACLR register does not clear TOF.
5
TOF
4
Input Capture Flag 2
0: No input capture (reset value).
ICF2
1: An Input Capture has occurred on the ICAP2 pin. To clear this bit, first read the SR
register, then read or write the low byte of the IC2R (IC2LR) register.
3
Output Compare Flag 2
0: No match (reset value).
OCF2
1: The content of the free running counter has matched the content of the OC2R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC2R (OC2LR) register.
2
Timer Disable
This bit is set and cleared by software. When set, it freezes the timer prescaler and
counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce
TIMD
power consumption. Access to the timer registers is still available, allowing the timer
configuration to be changed, or the counter reset, while it is disabled.
0: Timer enabled.
1: Timer prescaler, counter and outputs disabled.
1:0
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1
-
Reserved, must be kept cleared.
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On-chip peripherals
Input Capture 1 High Register (IC1HR)
This is an 8-bit register that contains the high part of the counter value (transferred by the
input capture 1 event).
IC1HR
7
Reset value: undefined
6
5
4
3
2
1
MSB
RO
0
LSB
RO
RO
RO
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RO
RO
RO
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Input Capture 1 Low Register (IC1LR)
This is an 8-bit register that contains the low part of the counter value (transferred by the
input capture 1 event).
IC1LR
7
Reset value: undefined
6
5
4
3
2
1
MSB
RO
0
LSB
RO
RO
RO
RO
RO
RO
RO
Output Compare 1 High Register (OC1HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
OC1HR
7
Reset value: 1000 0000 (80h)
6
5
4
3
2
1
MSB
R/W
0
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Compare 1 Low Register (OC1LR)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
OC1LR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
MSB
R/W
0
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Compare 2 High Register (OC2HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
OC2HR
7
Reset value: 1000 0000 (80h)
6
5
4
3
2
1
MSB
R/W
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0
LSB
R/W
R/W
R/W
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R/W
R/W
R/W
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On-chip peripherals
Output Compare 2 Low Register (OC2LR)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
OC2LR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
MSB
R/W
0
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Counter High Register (CHR)
This is an 8-bit register that contains the high part of the counter value.
CHR
Reset value: 1111 1111 (FFh)
7
6
5
4
3
2
1
MSB
RO
0
LSB
RO
RO
RO
RO
RO
RO
RO
Counter Low Register (CLR)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after accessing the CSR register clears the
TOF bit.
CLR
Reset value: 1111 1100 (FCh)
7
6
5
4
3
2
1
MSB
RO
0
LSB
RO
RO
RO
RO
RO
RO
RO
Alternate Counter High Register (ACHR)
This is an 8-bit register that contains the high part of the counter value.
ACHR
7
Reset value: 1111 1111 (FFh)
6
5
4
3
2
1
MSB
RO
0
LSB
RO
RO
RO
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RO
RO
RO
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Alternate Counter Low Register (ACLR)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after an access to CSR register does not clear
the TOF bit in the CSR register.
ACLR
7
Reset value: 1111 1100 (FCh)
6
5
4
3
2
1
0
MSB
RO
LSB
RO
RO
RO
RO
RO
RO
RO
Input Capture 2 High Register (IC2HR)
This is an 8-bit register that contains the high part of the counter value (transferred by the
Input Capture 2 event).
1C2HR
7
Reset value: undefined
6
5
4
3
2
1
0
MSB
RO
LSB
RO
RO
RO
RO
RO
RO
RO
Input Capture 2 Low Register (IC2LR)
This is an 8-bit register that contains the low part of the counter value (transferred by the
Input Capture 2 event).
1C2LR
7
Reset value: undefined
6
5
4
3
2
1
0
MSB
RO
Table 52.
Address
(Hex.)
LSB
RO
RO
RO
RO
RO
RO
RO
16-bit timer register map and reset values
Register
label
7
6
5
4
3
2
1
0
Timer A: 32
Timer B: 42
CR1
Reset value
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
Timer A: 31
Timer B: 41
CR2
Reset value
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
Timer A: 33
Timer B: 43
CSR
Reset value
ICF1
x
OCF1
x
TOF
x
ICF2
x
OCF2
x
TIMD
0
x
x
Timer A: 34
Timer B: 44
IC1HR
Reset value
MSB
x
x
x
x
x
x
x
LSB
x
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Table 52.
On-chip peripherals
16-bit timer register map and reset values (continued)
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
Timer A: 35
Timer B: 45
IC1LR
Reset value
MSB
x
x
x
x
x
x
x
LSB
x
Timer A: 36
Timer B: 46
OC1HR
Reset value
MSB
1
0
0
0
0
0
0
LSB
0
Timer A: 37
Timer B: 47
OC1LR
Reset value
MSB
0
0
0
0
0
0
0
LSB
0
Timer A: 3E
Timer B: 4E
OC2HR
Reset value
MSB
1
0
0
0
0
0
0
LSB
0
Timer A: 3F
Timer B: 4F
OC2LR
Reset value
MSB
0
0
0
0
0
0
0
LSB
0
Timer A: 38
Timer B: 48
CHR
Reset value
MSB
1
1
1
1
1
1
1
LSB
1
Timer A: 39
Timer B: 49
CLR
Reset value
MSB
1
1
1
1
1
1
0
LSB
0
Timer A: 3A
Timer B: 4A
ACHR
Reset value
MSB
1
1
1
1
1
1
1
LSB
1
Timer A: 3B
Timer B: 4B
ACLR
Reset value
MSB
1
1
1
1
1
1
0
LSB
0
Timer A: 3C
Timer B: 4C
IC2HR
Reset value
MSB
x
x
x
x
x
x
x
LSB
x
Timer A: 3D
Timer B: 4D
IC2LR
Reset value
MSB
x
x
x
x
x
x
x
LSB
x
10.4
Serial peripheral interface (SPI)
10.4.1
Introduction
The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves.
However, the SPI interface can not be a master in a multi-master system.
10.4.2
Main features
●
Full duplex synchronous transfers (on 3 lines)
●
Simplex synchronous transfers (on 2 lines)
●
Master or slave operation
●
6 master mode frequencies (fCPU/4 max.)
●
fCPU/2 max. slave mode frequency (see note)
●
SS Management by software or hardware
●
Programmable clock polarity and phase
●
End of transfer interrupt flag
●
Write collision, Master mode fault and Overrun flags
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Note:
In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
10.4.3
General description
Figure 49 shows the serial peripheral interface (SPI) block diagram. The SPI has three
registers:
●
SPI Control Register (SPICR)
●
SPI Control/Status Register (SPICSR)
●
SPI Data Register (SPIDR)
The SPI is connected to external devices through four pins:
●
MISO: Master In / Slave Out data
●
MOSI: Master Out / Slave In data
●
SCK: Serial Clock out by SPI masters and input by SPI slaves
●
SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master
communicate with slaves individually and to avoid contention on the data lines. Slave
SS inputs can be driven by standard I/O ports on the master MCU.
Figure 48. Serial peripheral interface block diagram
Data/Address bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
0
SPICSR
7
MISO
8-bit Shift Register
SPIF WCOL OVR MODF
SOD
bit
0
SOD SSM
SSI
Write
SS
SPI
state
control
SCK
7
1
0
SPICR
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Master
control
Serial clock
generator
SS
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 49.
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On-chip peripherals
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see Figure 52) but master and
slave must be programmed with the same timing mode.
Figure 49. Single master/single slave application
Master
MSB
Slave
LSB
MSB
8-bit Shift Register
SPI
clock
generator
MISO
MISO
MOSI
MOSI
SCK
SS
LSB
8-bit Shift Register
SCK
+5V
SS
Not used if SS is managed
by software
Slave Select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see Figure 51).
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In Master mode:
●
SS internal must be held high continuously
Depending on the data/clock timing relationship, there are two cases in Slave mode (see
Figure 50):
If CPHA = 1 (data latched on second clock edge):
●
SS internal must be held low during the entire transmission. This implies that in single
slave applications the SS pin either can be tied to VSS, or made free for standard I/O by
managing the SS function by software (SSM = 1 and SSI = 0 in the in the SPICSR
register)
If CPHA = 0 (data latched on first clock edge):
●
SS internal must be held low during byte transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a Write
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Collision error will occur when the slave writes to the shift register (seeWrite collision
error (WCOL) on page 103).
Figure 50. Generic SS timing diagram
Byte 1
MOSI/MISO
Byte 2
Byte 3
Master SS
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Figure 51. Hardware/software slave select management
SSM bit
SSI bit
SS external pin
1
SS internal
0
Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order:
1.
2.
Write to the SPICR register:
–
Select the clock frequency by configuring the SPR[2:0] bits.
–
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 52 shows the four possible configurations.
Note: The slave must have the same CPOL and CPHA settings as the master.
Write to the SPICSR register:
–
3.
Write to the SPICR register:
–
Caution:
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin
high for the complete byte transmit sequence.
Set the MSTR and SPE bits.
Note: MSTR and SPE bits remain set only if SS is high.
If the SPICSR register is not written first, the SPICR register setting (MSTR bit) might not be
taken into account.
The transmit sequence begins when software writes a byte in the SPIDR register.
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Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
–
The SPIF bit is set by hardware
–
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
Note:
1.
An access to the SPICSR register while the SPIF bit is set.
2.
A read to the SPIDR register.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1.
2.
Write to the SPICSR register to perform the following actions:
–
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see Figure 52). The slave must have the same CPOL and CPHA settings as the
master.
–
Manage the SS pin as described in Slave Select management on page 99 and
Figure 50. If CPHA = 1, SS must be held low continuously. If CPHA = 0, SS must
be held low during byte transmission and pulled up between each byte to let the
slave write in the shift register.
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
–
The SPIF bit is set by hardware
–
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
Note:
1.
An access to the SPICSR register while the SPIF bit is set.
2.
A write or a read to the SPIDR register.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
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On-chip peripherals
ST72324B-Auto
The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an Overrun condition (see Overrun condition
(OVR) on page 103).
10.4.4
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (see Figure 52).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge
Figure 52 shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
The diagram may be interpreted as a master or slave timing diagram where the SCK, MISO
and MOSI pins are directly connected between the master and the slave device.
Note:
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Figure 52. Data clock timing diagram(1)
CPHA = 1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MSB
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
MOSI
(from slave)
MSB
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSB
LSB
SS
(to slave)
Capture strobe
CPHA = 0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSB
MSB
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSB
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSB
SS
(to slave)
Capture strobe
1. This figure should not be used as a replacement for parametric information. Refer to the Electrical
Characteristics chapter.
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10.4.5
On-chip peripherals
Error flags
Master mode fault (MODF)
Master mode fault occurs when the master device has its SS pin pulled low.
When a Master mode fault occurs:
●
The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
●
The SPE bit is reset. This blocks all output from the device and disables the SPI
peripheral.
●
The MSTR bit is reset, thus forcing the device into slave mode.
Clearing the MODF bit is done through a software sequence:
Note:
1.
A read access to the SPICSR register while the MODF bit is set.
2.
A write to the SPICR register.
To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high
during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their
original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set
except in the MODF bit clearing sequence.
Overrun condition (OVR)
An overrun condition occurs, when the master device has sent a data byte and the slave
device has not cleared the SPIF bit issued from the previously transmitted byte.
When an Overrun occurs the OVR bit is set and an interrupt request is generated if the SPIE
bit is set.
In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A
read to the SPIDR register returns this byte. All other bytes are lost.
The OVR bit is cleared by reading the SPICSR register.
Write collision error (WCOL)
A write collision occurs when the software tries to write to the SPIDR register while a data
transfer is taking place with an external device. When this happens, the transfer continues
uninterrupted and the software write is unsuccessful.
Write collisions can occur both in master and slave mode. See also Slave Select
management on page 99.
Note:
A read collision will never occur since the received data byte is placed in a buffer in which
access is always synchronous with the MCU operation.
The WCOL bit in the SPICSR register is set if a write collision occurs.
No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).
A software sequence clears the WCOL bit (see Figure 53).
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Figure 53. Clearing the WCOL bit (Write Collision flag) software sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
Read SPICSR
Result
2nd Step
Read SPIDR
SPIF = 0
WCOL = 0
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
Read SPICSR
Result
2nd Step
Read SPIDR
Note: Writing to the SPIDR register
instead of reading it does not reset
the WCOL bit.
WCOL = 0
Single master systems
A typical single master system may be configured, using an MCU as the master and four
MCUs as slaves (see Figure 54).
The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports will be forced to be
inputs at that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line the master allows only one active slave
device during a transmission.
For more security, the slave device may respond to the master with the received data byte.
Then the master will receive the previous byte back from the slave device if all MISO and
MOSI pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
Figure 54. Single master/multiple slave configuration
SS
SS
SCK
SCK
MOSI
MISO
MOSI
MISO
MOSI
MISO
5V
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Ports
SCK
Master
MCU
SCK
SS
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Slave
MCU
Slave
MCU
Slave
MCU
Slave
MCU
SS
SS
SCK
MOSI
MISO
MOSI
MISO
ST72324B-Auto
10.4.6
On-chip peripherals
Low power modes
Table 53.
Effect of low power modes on SPI
Mode
Description
Wait
No effect on SPI.
SPI interrupt events cause the device to exit from Wait mode.
Halt
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an
interrupt with Exit from Halt mode capability. The data received is subsequently read from
the SPIDR register when the software is running (interrupt vector fetching). If several data
are received before the wake-up event, then an overrun error is generated. This error can
be detected after the fetch of the interrupt routine that woke up the device.
Using the SPI to wake up the MCU from Halt mode
In slave configuration, the SPI is able to wake up the ST7 device from Halt mode through a
SPIF interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
Note:
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from Halt mode state to normal
state. If the SPI exits from Slave mode, it returns to normal state immediately.
Caution:
The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. Therefore,
if Slave selection is configured as external (see Slave Select management on page 99),
make sure the master drives a low level on the SS pin when the slave enters Halt mode.
10.4.7
Interrupts
Table 54.
SPI interrupt control/wake-up capability(1)
Interrupt event
Event flag
SPI end of transfer event
SPIF
Master mode fault event
MODF
Enable control bit
Exit from WAIT Exit from HALT
Yes
SPIE
Yes
No
Overrun error
OVR
1. The SPI interrupt events are connected to the same interrupt vector (see Section 7: Interrupts). They
generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC
register is reset (RIM instruction).
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On-chip peripherals
10.4.8
ST72324B-Auto
SPI registers
SPI Control Register (SPICR)
SPICR
Reset value: 0000 xxxx (0xh)
7
6
5
4
3
2
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 55.
Bit
7
6
5
4
3
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1
0
SPICR register description
Name
Function
SPIE
Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited.
1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or OVR = 1 in the
SPICSR register.
SPE
Serial Peripheral Output Enable
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see Master mode fault (MODF) on page 103). The SPE bit
is cleared by reset, so the SPI peripheral is not initially connected to the external
pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
SPR2
Divider Enable
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to Table 56: SPI master mode SCK
frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
MSTR
Master mode
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see Master mode fault (MODF) on page 103).
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output
and the functions of the MISO and MOSI pins are reversed.
CPOL
Clock Polarity
This bit is set and cleared by software. This bit determines the idle state of the
serial Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication byte boundaries, the SPI must be
disabled by resetting the SPE bit.
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On-chip peripherals
Table 55.
Bit
SPICR register description (continued)
Name
2
CPHA
Function
Clock Phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
Note: The slave must have the same CPOL and CPHA settings as the master.
Serial clock frequency
These bits are set and cleared by software. Used with the SPR2 bit, they select
1:0 SPR[1:0]
the baud rate of the SPI serial clock SCK output by the SPI in master mode
(seeTable 56).
Note: These 2 bits have no effect in slave mode.
Table 56.
SPI master mode SCK frequency
Serial clock
SPR2
SPR1
SPR0
fCPU/4
1
0
0
fCPU/8
0
0
0
fCPU/16
0
0
1
fCPU/32
1
1
0
fCPU/64
0
1
0
fCPU/128
0
1
1
SPI Control/Status Register (SPICSR)
SPICSR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
SPIF
WCOL
OVR
MODF
Reserved
SOD
SSM
SSI
RO
RO
RO
RO
-
R/W
R/W
R/W
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Table 57.
Bit
7
6
5
4
3
2
1
0
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SPICSR register description
Name
Function
SPIF
Serial Peripheral data transfer flag
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared
1: Data transfer between the device and an external device has been completed.
Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the
SPICSR register is read.
Write Collision status
This bit is set by hardware when a write to the SPIDR register is done during a
WCOL
transmit sequence. It is cleared by a software sequence (see Figure 53).
0: No write collision occurred
1: A write collision has been detected.
OVR
SPI Overrun error
This bit is set by hardware when the byte currently being received in the shift register
is ready to be transferred into the SPIDR register while SPIF = 1 (see Overrun
condition (OVR) on page 103). An interrupt is generated if SPIE = 1 in SPICR
register. The OVR bit is cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
Mode Fault flag
This bit is set by hardware when the SS pin is pulled low in master mode (see
Master mode fault (MODF) on page 103). An SPI interrupt can be generated if
SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An
MODF
access to the SPICR register while MODF = 1 followed by a write to the SPICR
register).
0: No master mode fault detected
1: A fault in master mode has been detected.
-
Reserved, must be kept cleared.
SOD
SPI Output Disable
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode).
0: SPI output enabled (if SPE = 1).
1: SPI output disabled.
SSM
SS Management
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See Slave Select management
on page 99.
0: Hardware management (SS managed by external pin).
1: Software management (internal SS signal controlled by SSI bit. External SS pin
free for general-purpose I/O).
SSI
SS Internal mode
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the
level of the SS slave select signal when the SSM bit is set.
0: Slave selected.
1: Slave deselected.
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On-chip peripherals
SPI Data I/O Register (SPIDR)
SPIDR
Reset value: undefined
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
Note:
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Warning:
A write to the SPIDR register places data directly into the
shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see Figure 48).
Table 58.
SPI register map and reset values
Address (Hex.) Register label
7
6
5
4
3
2
1
0
x
x
x
x
LSB
x
0021h
SPIDR
Reset value
MSB
x
x
x
0022h
SPICR
Reset value
SPIE
0
SPE
0
SPR2
0
MSTR CPOL CPHA SPR1 SPR0
0
x
x
x
x
0023h
SPICSR
Reset value
SPIF
0
WCOL
0
OVR
0
MODF
0
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0
SOD
0
SSM
0
SSI
0
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10.5
Serial communications interface (SCI)
10.5.1
Introduction
The serial communications interface (SCI) offers a flexible means of full-duplex data
exchange with external equipment requiring an industry standard NRZ asynchronous serial
data format. The SCI offers a very wide range of baud rates using two baud rate generator
systems.
10.5.2
Main features
●
Full duplex, asynchronous communications
●
NRZ standard format (mark/space)
●
Dual baud rate generator systems
●
Independently programmable transmit and receive baud rates up to 500K baud.
●
Programmable data word length (8 or 9 bits)
●
Receive buffer full, Transmit buffer empty and End of Transmission flags
●
2 receiver wake-up modes
Address bit (MSB)
–
Idle line
●
Muting function for multiprocessor configurations
●
Separate enable bits for Transmitter and Receiver
●
4 error detection flags
●
●
●
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–
–
Overrun error
–
Noise error
–
Frame error
–
Parity error
5 interrupt sources with flags
–
Transmit data register empty
–
Transmission complete
–
Receive data register full
–
Idle line received
–
Overrun error detected
Parity control
–
Transmits parity bit
–
Checks parity of received data byte
Reduced power consumption mode
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10.5.3
On-chip peripherals
General description
The interface is externally connected to another device by two pins (see Figure 56):
●
TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the
output pin returns to its I/O port configuration. When the transmitter and/or the receiver
are enabled and nothing is to be transmitted, the TDO pin is at high level.
●
RDI: Receive Data Input is the serial data input. Oversampling techniques are used for
data recovery by discriminating between valid incoming data and noise.
Through these pins, serial data is transmitted and received as frames comprising:
●
an Idle Line prior to transmission or reception
●
a start bit
●
a data word (8 or 9 bits) least significant bit first
●
a Stop bit indicating that the frame is complete
This interface uses two types of baud rate generator:
●
a conventional type for commonly-used baud rates
●
an extended type with a prescaler offering a very wide range of baud rates even with
non-standard oscillator frequencies
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On-chip peripherals
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Figure 55. SCI block diagram
Write
Read
(Data Register) DR
Received Data Register (RDR)
Transmit Data Register (TDR)
TDO
Received Shift Register
Transmit Shift Register
RDI
CR1
R8
T8
SCID
Wake
up
unit
Transmit
control
M WAKE PCE PS
PIE
Receiver
clock
Receiver
control
CR2
SR
TIE TCIE RIE
ILIE
TE
RE RWU SBK
TDRE TC RDRF IDLE OR
NF
FE
SCI
Interrupt
control
Transmitter
clock
fCPU
Transmitter rate
control
/16
/PR
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
Receiver rate
control
Conventional baud rate generator
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10.5.4
On-chip peripherals
Functional description
The block diagram of the serial control interface is shown in Figure 55. It contains six
dedicated registers:
●
2 control registers (SCICR1 and SCICR2)
●
a status register (SCISR)
●
a baud rate register (SCIBRR)
●
an extended prescaler receiver register (SCIERPR)
●
an extended prescaler transmitter register (SCIETPR)
Refer to the register descriptions in Section 10.5.7 for the definitions of each bit.
Serial data format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see Figure 55).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame of ‘1’s followed by the start bit of the next
frame which contains data.
A Break character is interpreted on receiving ‘0’s for some multiple of the frame period. At
the end of the last break frame the transmitter inserts an extra ‘1’ bit to acknowledge the
start bit.
Transmission and reception are driven by their own baud rate generator.
Figure 56. Word length programming
9-bit word length (M bit is set)
Possible
Parity
bit
Data frame
Start
bit
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
Next data frame
Next
Stop Start
bit
bit
Start
bit
Idle frame
Break frame
Extra
’1’
Start
bit
8-bit word length (M bit is reset)
Possible
Parity
bit
Data frame
Start
bit
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
Stop
bit 7 Bit
Next data frame
Next
Start
bit
Idle frame
Start
bit
Break frame
Extra Start
bit
’1’
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On-chip peripherals
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Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.
Character transmission
During an SCI transmission, data shifts out LSB first on the TDO pin. In this mode, the
SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift
register (see Figure 55).
Procedure
1.
Select the M bit to define the word length.
2.
Select the desired baud rate using the SCIBRR and the SCIETPR registers.
3.
Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame
as first transmission.
4.
Access the SCISR register and write the data to send in the SCIDR register (this
sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
1.
An access to the SCISR register
2.
A write to the SCIDR register
The TDRE bit is set by hardware and it indicates:
●
The TDR register is empty.
●
The data transfer is beginning.
●
The next data can be written in the SCIDR register without overwriting the previous
data.
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR
register.
When a transmission is taking place, a write instruction to the SCIDR register stores the
data in the TDR register and which is copied in the shift register at the end of the current
transmission.
When no transmission is taking place, a write instruction to the SCIDR register places the
data directly in the shift register, the data transmission starts, and the TDRE bit is
immediately set.
When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt
is generated if the TCIE is set and the I bit is cleared in the CCR register.
Clearing the TC bit is performed by the following software sequence:
Note:
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1.
An access to the SCISR register
2.
A write to the SCIDR register
The TDRE and TC bits are cleared by the same software sequence.
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On-chip peripherals
Break characters
Setting the SBK bit loads the shift register with a break character. The break frame length
depends on the M bit (see Figure 56).
As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this
bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the
recognition of the start bit of the next frame.
Idle characters
Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the
current word.
Note:
Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore,
the best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next
byte in the SCIDR.
Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9
bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this
mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the
received shift register (see Figure 55).
Procedure
1.
Select the M bit to define the word length.
2.
Select the desired baud rate using the SCIBRR and the SCIERPR registers.
3.
Set the RE bit, this enables the receiver which begins searching for a start bit.
When a character is received:
●
The RDRF bit is set. It indicates that the content of the shift register is transferred to the
RDR.
●
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
●
The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
Clearing the RDRF bit is performed by the following software sequence done by:
1. An access to the SCISR register
2. A read to the SCIDR register.
The RDRF bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
Break character
When a break character is received, the SCI handles it as a framing error.
Idle character
When a idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.
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Overrun error
An overrun error occurs when a character is received when RDRF has not been reset. Data
can not be transferred from the shift register to the RDR register as long as the RDRF bit is
not cleared.
When a overrun error occurs:
●
The OR bit is set.
●
The RDR content will not be lost.
●
The shift register will be overwritten.
●
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read
operation.
Noise error
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise. Normal data bits are considered valid if three consecutive samples
(8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit
detection, the NF flag is set on the basis of an algorithm combining both valid edge
detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag from being
set during start bit reception, there should be a valid edge detection as well as three valid
samples.
When noise is detected in a frame:
●
The NF flag is set at the rising edge of the RDRF bit.
●
Data is transferred from the Shift register to the SCIDR register.
●
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The NF flag is reset by a SCISR register read operation followed by a SCIDR register read
operation.
During reception, if a false start bit is detected (for example, 8th, 9th, 10th samples are
011,101,110), the frame is discarded and the receiving sequence is not started for this
frame. There is no RDRF bit set for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid
frame is received.
Note:
If the application Start bit is not long enough to match the above requirements, then the NF
Flag may get set due to the short Start bit. In this case, the NF flag may be ignored by the
application software when the first valid byte is received.
See also Noise error causes on page 121.
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On-chip peripherals
Figure 57. SCI baud rate and extended prescaler block diagram
Extended prescaler transmitter rate control
Transmitter
clock
SCIETPR
Extended transmitter prescaler register
SCIERPR
Extended receiver prescaler register
Receiver
clock
Extended prescaler receiver rate control
Extended prescaler
fCPU
Transmitter rate
control
/16
/PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
Receiver rate
control
Conventional baud rate generator
Framing error
A framing error is detected when:
●
The stop bit is not recognized on reception at the expected time, following either a desynchronization or excessive noise.
●
A break is received.
When the framing error is detected:
●
the FE bit is set by hardware
●
Data is transferred from the Shift register to the SCIDR register.
●
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read
operation.
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On-chip peripherals
ST72324B-Auto
Conventional baud rate generation
The baud rate for the receiver and transmitter (Rx and Tx) are set independently and
calculated as follows:
Tx =
fCPU
Rx =
(16*PR)*TR
fCPU
(16*PR)*RR
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCI Baud Rate Register (SCIBRR) on page 127.
Example: If fCPU is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and
receive baud rates are 38400 baud.
Note:
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
Extended baud rate generation
The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value
prescaler, whereas the conventional baud rate generator retains industry standard software
compatibility.
The extended baud rate generator block diagram is described in Figure 57.
The output clock rate sent to the transmitter or to the receiver will be the output from the 16
divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR
register.
The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as follows:
fCPU
fCPU
Rx =
Tx =
16*ERPR*(PR*RR)
16*ETPR*(PR*TR)
with:
ETPR = 1,..,255, see SCI Extended Transmit Prescaler Division Register (SCIETPR) on
page 128.
ERPR = 1,.. 255, see SCI Extended Receive Prescaler Division Register (SCIERPR) on
page 128
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On-chip peripherals
Receiver muting and wake-up feature
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant SCI
service overhead for all non-addressed receivers.
The non-addressed devices may be placed in sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in sleep mode:
All the reception status bits cannot be set.
All the receive interrupts are inhibited.
A muted receiver may be awakened by one of the following two ways:
●
by Idle Line detection if the Wake bit is reset,
●
by Address Mark detection if the Wake bit is set.
A receiver wakes up by Idle Line detection when the Receive line has recognized an Idle
Frame. Then the RWU bit is reset by hardware but the Idle bit is not set.
A receiver wakes up by Address Mark detection when it received a ‘1’ as the most significant
bit of a word, thus indicating that the message is an address. The reception of this particular
word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the
receiver to receive this word normally and to use it as an address word.
Caution:
In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the
read operation (RWU = 1) and an address mark wake-up event occurs (RWU is reset)
before the write operation, the RWU bit will be set again by this write operation.
Consequently the address byte is lost and the SCI is not woken up from Mute mode.
Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in Table 59.
Table 59.
Frame formats(1)(2)
M bit
PCE bit
SCI frame
0
0
| SB | 8 bit data | STB |
0
1
| SB | 7-bit data | PB | STB |
1
0
| SB | 9-bit data | STB |
1
1
| SB | 8-bit data PB | STB |
1. SB = Start bit, STB = Stop bit, and PB = Parity bit.
2. In case of wake-up by an address mark, the MSB bit of the data is taken into account and not the Parity bit.
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On-chip peripherals
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Even parity
The parity bit is calculated to obtain an even number of ‘1’s inside the frame made of the 7 or
8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit, for example,
data = 00110101; 4 bits set => Parity bit will be 0 if Even parity is selected (PS bit = 0).
Odd parity
The parity bit is calculated to obtain an odd number of ‘1’s inside the frame made of the 7 or
8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit, for example,
data = 00110101; 4 bits set => Parity bit will be 1 if Odd parity is selected (PS bit = 1).
Transmission mode
If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted
but is changed by the parity bit.
Reception mode
If the PCE bit is set then the interface checks if the received data byte has an even number
of ‘1’s if even parity is selected (PS = 0) or an odd number of ‘1’s if odd parity is selected
(PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is
generated if PIE is set in the SCICR1 register.
SCI clock tolerance
During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th
samples is considered as the bit value. For a valid bit detection, all the three samples should
have the same value otherwise the noise flag (NF) is set. For example: If the 8th, 9th and
10th samples are 0, 1 and 1 respectively, then the bit value will be ‘1’, but the Noise flag bit
is set because the three samples values are not the same.
Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples
have the desired bit value. This means the clock frequency should not vary more than 6/16
(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when
receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed
3.75%.
Note:
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The internal sampling clock of the microcontroller samples the pin value on every falling
edge. Therefore, the internal sampling clock and the time the application expects the
sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit
length is 64µs), then the 8th, 9th and 10th samples will be at 28µs, 32µs and 36µs
respectively (the first sample starting ideally at 0µs). But if the falling edge of the internal
clock occurs just before the pin value changes, the samples would then be out of sync by
~4µs. This means the entire bit length must be at least 40µs (36µs for the 10th sample + 4µs
for synchronization with the internal sampling clock).
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On-chip peripherals
Clock deviation causes
The causes which contribute to the total deviation are:
●
DTRA: Deviation due to transmitter error (local oscillator error of the transmitter or the
transmitter is transmitting at a different baud rate).
●
DQUANT: Error due to the baud rate quantization of the receiver.
●
DREC: Deviation of the local oscillator of the receiver: This deviation can occur during
the reception of one complete SCI message assuming that the deviation has been
compensated at the beginning of the message.
●
DTCL: Deviation due to the transmission line (generally due to the transceivers)
All the deviations of the system should be added and compared to the SCI clock tolerance:
DTRA + DQUANT + DREC + DTCL < 3.75%
Noise error causes
See also the description of Noise error in Receiver on page 115.
Start bit
The Noise Flag (NF) is set during start bit reception if one of the following conditions occurs:
1.
A valid falling edge is not detected. A falling edge is considered to be valid if the three
consecutive samples before the falling edge occurs are detected as ‘1’ and, after the
falling edge occurs, during the sampling of the 16 samples, if one of the samples
numbered 3, 5 or 7 is detected as a ‘1’.
2.
During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is
detected as a ‘1’.
Therefore, a valid Start bit must satisfy both the above conditions to prevent the Noise Flag
from being set.
Data bits
The Noise Flag (NF) is set during normal data bit reception if the following condition occurs:
During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the
same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
Therefore, a valid Data bit must have samples 8, 9 and 10 at the same value to prevent the
Noise Flag from being set.
Figure 58. Bit sampling in Reception mode
RDI line
sampled values
Sample
clock
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6/16
7/16
7/16
One bit time
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On-chip peripherals
10.5.5
ST72324B-Auto
Low power modes
Table 60.
Effect of low power modes on SCI
Mode
10.5.6
Description
Wait
No effect on SCI.
SCI interrupts cause the device to exit from Wait mode.
Halt
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
Interrupts
The SCI interrupt events are connected to the same interrupt vector.
These events generate an interrupt if the corresponding Enable Control bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
Table 61.
SCI interrupt control/wake-up capability
Interrupt event
Event flag Enable control bit Exit from WAIT Exit from HALT
Transmit data register empty
TDRE
TIE
Yes
No
TC
TCIE
Yes
No
Yes
No
Yes
No
Transmission complete
Received data ready to be read
RDRF
RIE
Overrun error detected
OR
Idle line detected
IDLE
ILIE
Yes
No
PE
PIE
Yes
No
Parity error
10.5.7
SCI registers
SCI Status Register (SCISR)
SCISR
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Reset value: 1100 0000 (C0h)
7
6
5
4
3
2
1
0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PE
RO
RO
RO
RO
RO
RO
RO
RO
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On-chip peripherals
Table 62.
Bit
Name
SCISR register description
Function
7
Transmit Data Register Empty
This bit is set by hardware when the content of the TDR register has been transferred
into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the SCISR register
TDRE
followed by a write to the SCIDR register).
0: Data is not transferred to the shift register.
1: Data is transferred to the shift register.
Note: Data will not be transferred to the shift register unless the TDRE bit is cleared.
6
Transmission Complete
This bit is set by hardware when transmission of a frame containing data is complete.
An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a
software sequence (an access to the SCISR register followed by a write to the
SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note: TC is not set after the transmission of a Preamble or a Break.
TC
5
Received Data Ready Flag
This bit is set by hardware when the content of the RDR register has been
transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2
RDRF
register. It is cleared by a software sequence (an access to the SCISR register
followed by a read to the SCIDR register).
0: Data is not received
1: Received data is ready to be read
4
Idle line detect
This bit is set by hardware when a Idle Line is detected. An interrupt is generated if
the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access
to the SCISR register followed by a read to the SCIDR register).
IDLE
0: No idle line is detected
1: Idle line is detected
Note: The IDLE bit is not reset until the RDRF bit has itself been set (that is, a new
idle line occurs).
3
OR
Overrun error
This bit is set by hardware when the word currently being received in the shift register
is ready to be transferred into the RDR register while RDRF = 1. An interrupt is
generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an
access to the SCISR register followed by a read to the SCIDR register).
0: No overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content is not lost but the shift register is
overwritten.
NF
Noise Flag
This bit is set by hardware when noise is detected on a received frame. It is cleared
by a software sequence (an access to the SCISR register followed by a read to the
SCIDR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt.
2
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On-chip peripherals
Table 62.
Bit
ST72324B-Auto
SCISR register description (continued)
Name
Function
FE
Framing Error
This bit is set by hardware when a desynchronization, excessive noise or a break
character is detected. It is cleared by a software sequence (an access to the SCISR
register followed by a read to the SCIDR register).
0: No framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt. If the word currently being transferred
causes both Frame Error and Overrun error, it is transferred and only the OR bit will
be set.
PE
Parity Error
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared
by a software sequence (a read to the status register followed by an access to the
SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
1: Parity error
1
0
SCI Control Register 1 (SCICR1)
SCICR1
7
6
5
4
3
2
1
0
R8
T8
SCID
M
WAKE
PCE
PS
PIE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 63.
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Reset value: x000 0000 (x0h)
SCICR1 register description
Bit
Name
Function
7
R8
Receive data bit 8
This bit is used to store the 9th bit of the received word when M = 1.
6
T8
Transmit data bit 8
This bit is used to store the 9th bit of the transmitted word when M = 1.
5
Disabled for low power consumption
When this bit is set the SCI prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption.This bit is set and
SCID
cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
4
Word length
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 data bits, 1 Stop bit
1: 1 Start bit, 9 data bits, 1 Stop bit
Note: The M bit must not be modified during a data transfer (both transmission and
reception).
M
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On-chip peripherals
Table 63.
Bit
SCICR1 register description (continued)
Name
Function
Wake-Up method
This bit determines the SCI Wake-Up method, it is set or cleared by software.
WAKE
0: Idle line
1: Address mark
3
2
PCE
PS
Parity Selection
This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity will be selected
after the current byte.
0: Even parity
1: Odd parity
PIE
Parity Interrupt Enable
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
1
0
Parity Control Enable
This bit selects the hardware parity control (generation and detection). When the
parity control is enabled, the computed parity is inserted at the MSB position (9th bit
if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set
and cleared by software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
0: Parity control disabled
1: Parity control enabled
SCI Control Register 2 (SCICR2)
SCICR2
7
6
5
4
3
2
1
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 64.
Bit
7
6
Reset value: 0000 0000 (00h)
Name
TIE
TCIE
SCICR2 register description
Function
Transmitter Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.
Transmission Complete Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.
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On-chip peripherals
Table 64.
Bit
5
4
3
2
1
0
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Name
ST72324B-Auto
SCICR2 register description (continued)
Function
RIE
Receiver interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR
register.
ILIE
Idle Line Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.
TE
Transmitter Enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
- During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble
(Idle line) after the current word.
- When TE is set there is a 1 bit-time delay before the transmission starts.
Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits
are both cleared (or if TE is never set).
RE
Receiver Enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Note: Before selecting Mute mode (setting the RWU bit), the SCI must first receive
some data, otherwise it cannot function in Mute mode with Wake-Up by Idle line
detection.
RWU
Receiver Wake-Up
This bit determines if the SCI is in mute mode or not. It is set and cleared by
software and can be cleared by hardware when a wake-up sequence is recognized.
0: Receiver in Active mode
1: Receiver in Mute mode
SBK
Send Break
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted.
1: Break characters are transmitted.
Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter will send a Break word
at the end of the current word.
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On-chip peripherals
SCI Data Register (SCIDR)
This register contains the received or transmitted data character, depending on whether it is
read from or written to.
SCIDR
Reset value: undefined
7
6
5
4
3
2
1
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 55). The RDR register provides the parallel interface between the
input shift register and the internal bus (see Figure 55).
SCI Baud Rate Register (SCIBRR)
SCIBRR
Reset value: 0000 0000 (00h)
7
6
4
3
2
1
SCP[1:0]
SCT[2:0]
SCR[2:0]
R/W
R/W
R/W
Table 65.
Bit
5
0
SCIBRR register description
Name
Function
First SCI Prescaler
These 2 prescaling bits allow several standard clock division ranges.
00: PR prescaling factor = 1
7:6 SCP[1:0]
01: PR prescaling factor = 3
10: PR prescaling factor = 4
11: PR prescaling factor = 13
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On-chip peripherals
Table 65.
Bit
ST72324B-Auto
SCIBRR register description (continued)
Name
Function
SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division
applied to the bus clock to yield the transmit rate clock in conventional baud rate
generator mode.
000: TR dividing factor = 1
001: TR dividing factor = 2
5:3 SCT[2:0]
010: TR dividing factor = 4
011: TR dividing factor = 8
100: TR dividing factor = 16
101: TR dividing factor = 32
110: TR dividing factor = 64
111: TR dividing factor = 128
SCI Receiver rate divisor
These 3 bits, in conjunction with the SCP[1:0] bits, define the total division applied
to the bus clock to yield the receive rate clock in conventional baud rate generator
mode.
000: RR dividing factor = 1
001:
RR dividing factor = 2
2:0 SCR[2:0]
010: RR dividing factor = 4
011: RR dividing factor = 8
100: RR dividing factor = 16
101: RR dividing factor = 32
110: RR dividing factor = 64
111: RR dividing factor = 128
SCI Extended Receive Prescaler Division Register (SCIERPR)
This register is used to set the Extended Prescaler rate division factor for the receive circuit.
SCIERPR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
ERPR[7:0]
R/W
Table 66.
Bit
7:0
SCIERPR register description
Name
Function
8-bit Extended Receive Prescaler Register
The extended baud rate generator is activated when a value different from 00h
is stored in this register. Therefore the clock frequency issued from the 16
ERPR[7:0]
divider (see Figure 57) is divided by the binary factor set in the SCIERPR
register (in the range 1 to 255).
The extended baud rate generator is not used after a reset.
SCI Extended Transmit Prescaler Division Register (SCIETPR)
This register is used to set the External Prescaler rate division factor for the transmit circuit.
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On-chip peripherals
SCIETPR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
ETPR[7:0]
R/W
Table 67.
Bit
7:0
Table 68.
SCIETPR register description
Name
Function
ETPR[7:0]
8-bit Extended Transmit Prescaler Register
The extended baud rate generator is activated when a value different from 00h
is stored in this register. Therefore the clock frequency issued from the 16
divider (see Figure 57) is divided by the binary factor set in the SCIETPR
register (in the range 1 to 255).
The extended baud rate generator is not used after a reset.
Baud rate selection
Conditions
Symbol
Parameter
fCPU
fTx
fRx
Communication
frequency
Accuracy vs.
Standard
Prescaler
~0.16%
Conventional mode
TR (or RR) = 128, PR = 13
TR (or RR) = 32, PR = 13
TR (or RR) = 16, PR = 13
TR (or RR) = 8, PR = 13
TR (or RR) = 4, PR = 13
TR (or RR) = 16, PR = 3
TR (or RR) = 2, PR =13
TR (or RR) = 1, PR = 13
8 MHz
~0.79%
Extended mode
ETPR (or ERPR) = 35,
TR (or RR)= 1, PR = 1
Doc ID13466 Rev 4
Standard
Baud rate
300
1200
2400
4800
9600
10400
19200
38400
~300.48
~1201.92
~2403.84
~4807.69
~9615.38
~10416.67
~19230.77
~38461.54
14400
~14285.71
Unit
Hz
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On-chip peripherals
Table 69.
ST72324B-Auto
SCI register map and reset values
Address (Hex.)
Register label
7
6
5
4
3
2
1
0
0050h
SCISR
Reset value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
0051h
SCIDR
Reset value
MSB
x
x
x
x
x
x
x
LSB
x
0052h
SCIBRR
Reset value
SCP1
0
SCP0
0
SCT2
0
SCT1
0
SCT0
0
SCR2
0
SCR1
0
SCR0
0
0053h
SCICR1
Reset value
R8
x
T8
0
SCID
0
M
0
WAKE
0
PCE
0
PS
0
PIE
0
0054h
SCICR2
Reset value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
0055h
SCIERPR
Reset value
MSB
0
0
0
0
0
0
0
LSB
0
0057h
SCIPETPR
Reset value
MSB
0
0
0
0
0
0
0
LSB
0
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On-chip peripherals
10.6
10-bit A/D converter (ADC)
10.6.1
Introduction
The on-chip analog-to-digital converter (ADC) peripheral is a 10-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 16
multiplexed analog input channels (refer to device pin out description) that allow the
peripheral to convert the analog voltage levels from up to 16 different sources.
The result of the conversion is stored in a 10-bit Data Register. The A/D converter is
controlled through a Control/Status Register.
10.6.2
Main features
●
10-bit conversion
●
Up to 16 channels with multiplexed input
●
Linear successive approximation
●
Data register (DR) which contains the results
●
Conversion complete status flag
●
On/off bit (to reduce consumption)
The block diagram is shown in Figure 59.
Figure 59. ADC block diagram
fCPU
Div 4
0
fADC
1
Div 2
EOC SPEED ADON
0
CH3
CH2
CH1
ADCCSR
CH0
4
AIN0
AIN1
Analog to Digital
Analog
MUX
Converter
AINx
ADCDRH
D9
D8
ADCDRL
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D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
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On-chip peripherals
10.6.3
ST72324B-Auto
Functional description
The conversion is monotonic, meaning that the result never decreases if the analog input
does not increase.
If the input voltage (VAIN) is greater than VAREF (high-level voltage reference) then the
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in the Electrical
Characteristics Section.
RAIN is the maximum recommended impedance for an analog input signal. If the impedance
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the allotted time.
A/D converter configuration
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to
Section 9: I/O ports. Using these pins as analog inputs does not affect the ability of the port
to be read as a logic input.
In the ADCCSR register:
Select the CS[3:0] bits to assign the analog channel to convert.
Starting the conversion
In the ADCCSR register:
Set the ADON bit to enable the A/D converter and to start the conversion. From this
time on, the ADC performs a continuous conversion of the selected channel.
When a conversion is complete:
●
the EOC bit is set by hardware
●
the result is in the ADCDR registers
A read to the ADCDRH resets the EOC bit.
To read the 10 bits, perform the following steps:
Note:
1.
Poll the EOC bit.
2.
Read the ADCDRL register
3.
Read the ADCDRH register. This clears EOC automatically.
The data is not latched, so both the low and the high data register must be read before the
next conversion is complete. Therefore, it is recommended to disable interrupts while
reading the conversion result.
To read only 8 bits, perform the following steps:
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1.
Poll the EOC bit.
2.
Read the ADCDRH register. This clears EOC automatically.
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On-chip peripherals
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
10.6.4
Low power modes
Note:
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed.
.
Table 70.
Effect of low power modes on ADC
Mode
10.6.5
Description
Wait
No effect on A/D converter
Halt
A/D converter disabled.
After wake-up from Halt mode, the A/D converter requires a stabilization time tSTAB
(see Section 12: Electrical characteristics) before accurate conversions can be
performed.
Interrupts
None.
10.6.6
ADC registers
ADC Control/Status Register (ADCCSR)
ADCCSR
7
6
5
4
EOC
SPEED
ADON
Reserved
CH[3:0]
RO
R/W
RW
-
RW
Table 71.
Bit
7
6
Reset value: 0000 0000 (00h)
2
1
0
ADCCSR register description
Name
EOC
3
Function
End of Conversion
This bit is set by hardware. It is cleared by hardware when software reads the
ADCDRH register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
ADC clock selection
This bit is set and cleared by software.
SPEED
0: fADC = fCPU/4
1: fADC = fCPU/2
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On-chip peripherals
ST72324B-Auto
Table 71.
Bit
Name
5
ADON
4
-
3:0
ADCCSR register description
Function
A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Reserved, must be kept cleared.
Channel selection
These bits are set and cleared by software. They select the analog input to convert.
0000: Channel pin = AIN0
0001: Channel pin = AIN1
0010: Channel pin = AIN2
0011: Channel pin = AIN3
0100: Channel pin = AIN4
0101: Channel pin = AIN5
0110: Channel pin = AIN6
0111: Channel pin = AIN7
CH[3:0]
1000: Channel pin = AIN8
1001: Channel pin = AIN9
1010: Channel pin = AIN10
1011: Channel pin = AIN11
1100: Channel pin = AIN12
1101: Channel pin = AIN13
1110: Channel pin = AIN14
1111: Channel pin = AIN15
Note: The number of channels is device dependent. Refer to Section 2: Pin
description.
ADC Data Register High (ADCDRH)
ADCDRH
7
Reset value: 0000 0000 (00h)
6
5
4
3
D[9:2]
RO
Table 72.
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Bit
Name
7:0
D[9:2]
ADCDRH register description
Function
MSB of Converted Analog Value
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1
0
ST72324B-Auto
On-chip peripherals
ADC Data Register Low (ADCDRL)
ADCDRL
7
Reset value: 0000 0000 (00h)
6
Table 73.
Bit
Name
7:2
-
1:0
D[1:0]
Table 74.
5
4
3
2
1
0
Reserved
D[1:0]
-
RO
ADCDRL register description
Function
Reserved. Forced by hardware to 0.
LSB of Converted Analog Value
ADC register map and reset values
Address (Hex.) Register label
7
6
5
4
3
2
1
0
0070h
ADCCSR
Reset value
EOC
0
SPEED
0
ADON
0
0
CH3
0
CH2
0
CH1
0
CH0
0
0071h
ADCDRH
Reset value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
0072h
ADCDRL
Reset value
0
0
0
0
0
0
D1
0
D0
0
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Instruction set
ST72324B-Auto
11
Instruction set
11.1
CPU addressing modes
The CPU features 17 different addressing modes which can be classified in 7 main groups
(see Table 75).
:
Table 75.
Addressing mode groups
Addressing mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset byte,#5
The CPU Instruction Set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be divided in two submodes called
long and short:
●
Long addressing mode is more powerful because it can use the full 64 Kbyte address
space, however it uses more bytes and more CPU cycles.
●
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 76.
CPU addressing mode overview
Mode
Syntax
Destination
Pointer address
(Hex.)
Pointer size
(Hex.)
Length
(bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No offset
Direct
Indexed
ld A,(X)
00..FF
+0
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed
ld A,($1000,X)
0000..FFFF
+2
Short
Indirect
ld A,[$10]
00..FF
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect
ld A,([$10],X)
00..1FE
00..FF
byte
+2
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Indexed
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ST72324B-Auto
Table 76.
Instruction set
CPU addressing mode overview (continued)
Long
Indirect
Relative
ld A,([$10.w],X)
0000..FFFF
Direct
jrne loop
PC+/-127
Relative
Indirect
jrne [$10]
PC+/-127
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
Relative
btjt $10,#7,skip
00..FF
Bit
Indirect
Relative
btjt [$10],#7,skip
00..FF
11.1.1
Indexed
00..FF
word
+2
+1
00..FF
byte
+2
+1
00..FF
byte
+2
+2
00..FF
byte
+3
Inherent
All Inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Table 77.
Inherent instructions
Instruction
Function
NOP
No Operation
TRAP
S/W Interrupt
WFI
Wait for Interrupt (low power mode)
HALT
Halt oscillator (lowest power mode)
RET
Sub-routine Return
IRET
Interrupt sub-routine Return
SIM
Set Interrupt Mask (level 3)
RIM
Reset Interrupt Mask (level 0)
SCF
Set Carry Flag
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
LD
Load
CLR
Clear
PUSH/POP
Push/Pop to/from the stack
INC/DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
MUL
Byte Multiplication
SLL, SRL, SRA, RLC, RRC
Shift and Rotate operations
SWAP
Swap nibbles
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Instruction set
11.1.2
ST72324B-Auto
Immediate
Immediate instructions have two bytes: The first byte contains the opcode and the second
byte contains the operand value.
.
Table 78.
Immediate instructions
Instruction
11.1.3
Function
LD
Load
CP
Compare
BCP
Bit Compare
AND, OR, XOR
Logical operations
ADC, ADD, SUB, SBC
Arithmetic operations
Direct
In Direct instructions, the operands are referenced by their memory address. The direct
addressing mode consists of two submodes:
Direct (short)
The address is a byte, thus requiring only one byte after the opcode, but only allows
00 - FF addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after
the opcode.
11.1.4
Indexed (no offset, short, long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indexed addressing mode consists of three submodes:
Indexed (no offset)
There is no offset, (no extra byte after the opcode), and it allows 00 - FF addressing space.
Indexed (short)
The offset is a byte, thus requiring only one byte after the opcode and allows 00 - 1FE
addressing space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the
opcode.
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11.1.5
Instruction set
Indirect (short, long)
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two
submodes:
Indirect (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing
space, and requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
11.1.6
Indirect indexed (short, long)
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
The indirect indexed addressing mode consists of two submodes:
Indirect indexed (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing
space, and requires 1 byte after the opcode.
Indirect indexed (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
I
Table 79.
Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes
Instructions
Long and short
Function
LD
Load
CP
Compare
AND, OR, XOR
Logical operations
ADC, ADD, SUB, SBC
Arithmetic Additions/Subtractions operations
BCP
Bit Compare
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Instruction set
ST72324B-Auto
Table 79.
Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes
Instructions
Short only
11.1.7
Function
CLR
Clear
INC, DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
BSET, BRES
Bit operations
BTJT, BTJF
Bit Test and Jump operations
SLL, SRL, SRA, RLC, RRC
Shift and Rotate operations
SWAP
Swap nibbles
CALL, JP
Call or Jump sub-routine
Relative mode (direct, indirect)
This addressing mode is used to modify the PC register value, by adding an 8-bit signed
offset to it.
.
Table 80.
Relative direct and indirect instructions and functions
Available relative direct/indirect instructions
Function
JRxx
Conditional Jump
CALLR
Call Relative
The relative addressing mode consists of two submodes:
Relative (direct)
The offset follows the opcode.
Relative (indirect)
The offset is defined in the memory, the address of which follows the opcode.
11.2
Instruction groups
The ST 7 family devices use an Instruction Set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Table 81.
Instruction groups
Group
Instructions
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
Increment/Decrement INC
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RSP
DEC
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Instruction set
Table 81.
Instruction groups (continued)
Group
Instructions
Compare and Tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit operation
BSET
BRES
Conditional Bit Test
and Branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and Rotates
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional Jump
or Call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Conditional Branch
JRxx
Interruption
management
TRAP
WFI
HALT
IRET
Condition Code Flag
modification
SIM
RIM
SCF
RCF
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RET
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Instruction set
ST72324B-Auto
Using a prebyte
The instructions are described with one to four opcodes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:
PC-2
End of previous instruction
PC-1
Prebyte
PC
Opcode
PC+1
Additional word (0 to 2) according to the number of bytes required to compute the
effective address
These prebytes enable the instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
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PDY 90
Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92
Replace an instruction using direct, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction
using indirect X indexed addressing mode.
PIY 91
Replace an instruction using X indirect indexed addressing mode by a Y one.
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Table 82.
Instruction set
Instruction set overview
Mnemo
Description
Function/example
Dst
Src
I1
H
I0
N
Z
C
ADC
Add with Carry
A=A+M+C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A, memory
tst (A . M)
A
M
N
Z
BRES
Bit reset
bres Byte, #3
M
BSET
Bit set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1
M
C
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1
M
C
CALL
Call sub-routine
CALLR
Call sub-routine relative
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
CPL
One Complement
A = FFH-A
DEC
Decrement
dec Y
HALT
Halt
IRET
Interrupt routine return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
jrf *
JRIH
Jump if ext. INT pin = 1
(ext. INT pin high)
JRIL
Jump if ext. INT pin = 0
(ext. INT pin low)
JRH
Jump if H = 1
H=1?
JRNH
Jump if H = 0
H=0?
JRM
Jump if I1:0 = 11
I1:0 = 11 ?
JRNM
Jump if I1:0 11
I1:0 11 ?
JRMI
Jump if N = 1 (minus)
N=1?
JRPL
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned
reg, M
0
1
N
Z
C
reg, M
N
Z
1
reg, M
N
Z
N
Z
N
Z
M
1
I1
reg, M
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H
I0
C
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Instruction set
Table 82.
ST72324B-Auto
Instruction set overview (continued)
Mnemo
Description
Function/example
Dst
Src
JRUGT
Jump if (C + Z = 0)
Unsigned >
JRULE
Jump if (C + Z = 1)
Unsigned
LD
Load
dst src
reg, M
M, reg
MUL
Multiply
X,A = X * A
A, X, Y
X, Y, A
NEG
Negate (2's compl)
neg $10
reg, M
NOP
No Operation
OR
OR operation
A=A+M
A
M
pop reg
reg
M
POP
Pop from the Stack
pop CC
CC
M
M
reg, CC
I1
H
I0
N
Z
N
Z
0
I1
H
C
0
I0
N
Z
N
Z
N
Z
C
C
PUSH
Push onto the Stack
push Y
RCF
Reset carry flag
C=0
RIM
Enable Interrupts
I1:0 = 10 (level 0)
RLC
Rotate Left true C
C A C
reg, M
N
Z
C
RRC
Rotate Right true C
C A C
reg, M
N
Z
C
RSP
Reset Stack Pointer
S = Max allowed
SBC
Subtract with Carry
A=A-M-C
N
Z
C
SCF
Set CARRY FLAG
C=1
SIM
Disable Interrupts
I1:0 = 11 (level 3)
SLA
Shift Left Arithmetic
C A 0
reg, M
N
Z
C
SLL
Shift Left Logic
C A 0
reg, M
N
Z
C
SRL
Shift Right Logic
0 A C
reg, M
0
Z
C
SRA
Shift Right Arithmetic
A7 A C
reg, M
N
Z
C
SUB
Subtraction
A=A-M
A
N
Z
C
SWAP
SWAP nibbles
A7-A4 A3-A0
reg, M
N
Z
TNZ
Test for Neg and Zero
tnz lbl1
N
Z
TRAP
S/W TRAP
S/W interrupt
WFI
WAIT for Interrupt
XOR
Exclusive OR
N
Z
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0
1
A
0
M
1
A = A XOR M
1
A
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M
M
1
1
1
0
ST72324B-Auto
Electrical characteristics
12
Electrical characteristics
12.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
12.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25°C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3).
12.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25°C, VDD = 5V. They are given
only as design guidelines and are not tested.
12.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
12.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 60.
Figure 60. Pin loading conditions
ST7 pin
CL
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Electrical characteristics
12.1.5
ST72324B-Auto
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 61.
Figure 61. Pin input voltage
ST7 pin
VIN
12.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
12.2.1
Voltage characteristics
Table 83.
Voltage characteristics
Symbol
Ratings
Maximum value Unit
VDD - VSS
Supply voltage
6.5
VPP - VSS
Programming voltage
13
Input voltage on true open drain pin
VIN(1)(2)
Input voltage on any other pin
|VDDx| and |VSSx| Variations between different digital power pins
|VSSA - VSSx|
Variations between digital and analog ground pins
VESD(HBM)
Electrostatic discharge voltage (human body model)
VESD(MM)
Electrostatic discharge voltage (machine model)
V
VSS - 0.3 to 6.5
VSS - 0.3 to
VDD + 0.3
50
mV
50
see Section 12.8.3 on
page 160
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up
or pull-down resistor (typical: 4.7k for RESET, 10k for I/Os). For the same reason, unused I/O pins
must not be directly tied to VDD or VSS.
2. IINJ(PIN) must never be exceeded. This is implicitly ensured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be
respected.
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12.2.2
Electrical characteristics
Current characteristics
Table 84.
Current characteristics
Symbol
Ratings
IVDD
Total current into VDD power lines (source)(1)
IVSS
Total current out of VSS ground lines (sink)(1)
IIO
Max value Unit
32-pin devices
75
44-pin devices
150
32-pin devices
75
44-pin devices
150
Output current sunk by any standard I/O and control pin
20
Output current sunk by any high sink I/O pin
40
Output current source by any I/Os and control pin
- 25
Injected current on VPP pin
±5
Injected current on RESET pin
±5
Injected current on OSC1 and OSC2 pins
±5
Injected current on ROM and 32 Kbyte Flash devices PB0 pin
±5
Injected current on 8/16 Kbyte Flash devices PB0 pin
+5
mA
IINJ(PIN)(2)(3)
Injected current on any other
IINJ(PIN)
(2)
pin(4)(5)
Total injected current (sum of all I/O and control
±5
pins)(4)
± 25
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected.
3. Negative injection degrades the analog performance of the device. See note in Section 12.13.3: ADC
accuracy on page 174. If the current injection limits given in Section Table 105.: General characteristics on
page 162 are exceeded, general device malfunction may result.
4. When several inputs are submitted to a current injection, the maximum SIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with SIINJ(PIN) maximum current injection on four I/O port pins of the device.
5. True open drain I/O port pins do not accept positive injection.
12.2.3
Thermal characteristics
Table 85.
Symbol
TSTG
TJ
Thermal characteristics
Ratings
Storage temperature range
Value
Unit
-65 to +150
°C
Maximum junction temperature (see Section 13.3: Thermal characteristics)
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Electrical characteristics
12.3
ST72324B-Auto
Operating conditions
Table 86.
Operating conditions
Symbol
fCPU
Parameter
Conditions
Internal clock frequency
Operating voltage (except Flash Write/Erase)
VDD
Min
Max
Unit
0
8
MHz
3.8
5.5
4.5
5.5
V
Operating Voltage for Flash Write/Erase
VPP = 11.4 to 12.6V
A-suffix versions
85
B-suffix versions
TA
Ambient temperature range
105
-40
°C
C-suffix version
125
D-suffix version
150
Figure 62. fCPU max versus VDD
fCPU [MHz]
Functionality
guaranteed
in this area
(unless
otherwise
specified
in the tables
of parametric
data)
8
Functionality
not guaranteed
in this area
6
4
2
1
0
3.5
3.8 4.0
4.5
5.5
Supply voltage [V]
Note:
Some temperature ranges are only available with a specific package and memory size.
Refer to Section 14: Device configuration and ordering information.
Warning:
148/198
Do not connect 12V to VPP before VDD is powered on, as this
may damage the device.
Doc ID13466 Rev 4
ST72324B-Auto
Electrical characteristics
12.4
LVD/AVD characteristics
12.4.1
Operating conditions with LVD
Subject to general operating conditions for TA.
Table 87.
Operating conditions with LVD
Symbol
Parameter
Conditions
Typ
Max
4.0(1)
4.2
4.5
VD level = med. in option byte
3.55
3.75
4.0(1)
VD level = low in option byte(2)
2.95(1)
3.15
3.35(1)
VD level = high in option byte
3.8
4.0
4.25(1)
3.55
3.75(1)
2.8(1)
3.0
3.15(1)
150
200
250
(2)
VIT-(LVD) Reset generation threshold (VDD fall) VD level = med. in option byte(2) 3.35(1)
VD level = low in option byte(2)
Vhys(LVD) LVD voltage threshold hysteresis(1)
VIT+(LVD)-VIT-(LVD)
Flash devices
VtPOR
VDD rise
time(1)
8/16K ROM devices
Filtered glitch delay on VDD(1)
V
mV
100ms/V
6µs/V
20ms/V
ms/V
32K ROM devices
tg(VDD)
Unit
(1)
VD level = high in option byte
VIT+(LVD) Reset release threshold (VDD rise)
Min
Not detected by the LVD
40
ns
1. Data based on characterization results, tested in production for ROM devices only.
2. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range.
12.4.2
Auxiliary voltage detector (AVD) thresholds
Subject to general operating conditions for TA.
Table 88.
Symbol
AVD thresholds
Parameter
Conditions
VD level = high in option byte
1 0 AVDF flag toggle threshold
VIT+(AVD)
(VDD rise)
VIT-(AVD)
0 1 AVDF flag toggle threshold
(VDD fall)
Vhys(AVD) AVD voltage threshold hysteresis
VIT-
Voltage drop between AVD flag set and
LVD reset activated
Min
Typ
Max
4.4(1)
4.6
4.9
(1)
VD level = med. in option byte
3.95
4.15
4.4(1)
VD level = low in option byte
3.4(1)
3.6
3.8(1)
VD level = high in option byte
4.2
4.4
4.65(1)
VD level = med. in option byte
3.75(1)
4.0
4.2(1)
VD level = low in option byte
3.2(1)
3.4
3.6(1)
VIT+(AVD)-VIT-(AVD)
200
VIT-(AVD)-VIT-(LVD)
450
Unit
V
mV
1. Data based on characterization results, tested in production for ROM devices only.
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Electrical characteristics
12.5
ST72324B-Auto
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To
obtain the total device consumption, the two current values must be added (except for Halt
mode for which the clock is stopped).
12.5.1
ROM current consumption
Table 89.
ROM current consumption
Symbol
Parameter
Conditions
32K ROM
devices
16K/8K ROM
devices
Unit
Typ
Max(1)
Typ
Max(1)
fOSC = 2 MHz, fCPU = 1 MHz
fOSC = 4 MHz, fCPU = 2 MHz
fOSC = 8 MHz, fCPU = 4 MHz
fOSC = 16 MHz, fCPU = 8 MHz
0.55
1.10
2.20
4.38
0.87
1.75
3.5
7.0
0.46
0.93
1.9
3.7
0.69
1.4
2.7
5.5
mA
fOSC = 2 MHz, fCPU = 62.5 kHz
fOSC = 4 MHz, fCPU = 125 kHz
fOSC = 8 MHz, fCPU = 250 kHz
fOSC = 16 MHz, fCPU = 500 kHz
53
100
194
380
87
175
350
700
30
70
150
310
60
120
250
500
µA
Supply current in Wait mode
fOSC = 2 MHz, fCPU = 1 MHz
fOSC = 4 MHz, fCPU = 2 MHz
fOSC = 8 MHz, fCPU = 4 MHz
fOSC = 16 MHz, fCPU = 8 MHz
0.31
0.61
1.22
2.44
0.5
1.0
2.0
4.0
0.22
0.45
0.91
1.82
0.37
0.75
1.5
3
mA
Supply current in Slow Wait
mode(2)
fOSC = 2 MHz, fCPU = 62.5 kHz
fOSC = 4 MHz, fCPU = 125 kHz
fOSC = 8 MHz, fCPU = 250 kHz
fOSC = 16 MHz, fCPU = 500 kHz
36
69
133
260
63
125
250
500
20
40
90
190
40
90
180
350
-40°C < TA < +85°C
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