ST7262xxx
Low speed USB 8-bit MCU with 3 endpoints, Flash or
ROM memory, LVD, WDG, 10-bit ADC, 2 timers, SCI, SPI
Features
Memories
– 8 or 16 Kbyte Program memory
(ROM or Dual voltage FLASH)
with read-write protection
– In-Application and In-Circuit Programming for
FLASH versions
– 384 to 768 bytes RAM (128-byte stack)
■ Clock, Reset and Supply Management
– Enhanced Reset System (Power On Reset)
– Low Voltage Detector (LVD)
– Clock-out capability
– 6 or 12 MHz Oscillator (8, 4, 2, 1 MHz internal
frequencies)
– 3 Power saving modes
■ USB (Universal Serial Bus) Interface
– DMA for low speed applications compliant
with USB specification (version 2.0):
– Integrated 3.3V voltage regulator and transceivers
– Suspend and Resume operations
– 3 Endpoints
■ Up to 31 I/O Ports
– Up to 31 multifunctional bidirectional I/O lines
– Up to 12 External interrupts (3 vectors)
– 13 alternate function lines
– 8 high sink outputs
(8 mA@0.4 V/20 mA@1.3 V)
– 2 true open drain pins (N buffer 8 mA@0.4 V)
■ 3 Timers
– Configurable watchdog timer (8 to 500 ms
timeout)
– 8-bit Auto Reload Timer (ART) with 2 Input
Captures, 2 PWM outputs and External Clock
– 8-bit Time Base Unit (TBU) for generating periodic interrupts cascadable with ART
Device Summary
■
SO34 shrink
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■
■
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Features
June 2009
ST72623F2
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Program memory - Kbytes
RAM (stack) - bytes
Peripherals
Serial I/O
I/Os
Operating Supply
Operating Temperature
Packages
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PDIP20
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SO20
ST72621K4
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LQFP44
PDIP32 shrink
PDIP42 shrink
Analog Peripheral
– 10-bit A/D Converter with up to 8 input pins.
2 Communications Interfaces
– Asynchronous Serial Communication interface
– Synchronous Serial Peripheral Interface
Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
Nested interrupts
Development Tools
– Full hardware/software development package
ST72622L2
ST72621L4
ST72621J4
8
16
8
16
16
384 (128)
768 (128)
384 (128)
768 (128)
768 (128)
USB, Watchdog, Low Voltage Detector, 8-bit Auto-Reload timer, Timebase unit, A/D Converter
SPI + SCI
SPI
SPI + SCI
11
21
23
31
4.0V to 5.5V (Low voltage 3.0V to 5.5V ROM versions available)
0°C to +70°C
PDIP20/SO20
PDIP32
SO34
PDIP42/LQFP44
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1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 PCB LAYOUT RECOMMENDATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 CLOCKS AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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6.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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8.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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8.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.3 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.3 TIMEBASE UNIT (TBU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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10.6 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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10.7 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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12.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 117
12.1210-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
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14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 128
14.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 128
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14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
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15 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
15.1 A/ D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . . 135
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15.2 A/D CONVERTER CONVERSION SPEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
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15.3 SCI WRONG BREAK DURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
15.4 UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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15.5 HALT MODE POWER CONSUMPTION WITH ADC ON . . . . . . . . . . . . . . . . . . . . . . . . . 136
16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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ST7262xxx
1 INTRODUCTION
The ST7262 and ST72F62 devices are members
of the ST7 microcontroller family designed for USB
applications.
All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set.
The ST7262 devices are ROM versions.
The ST72F62 versions feature dual-voltage
FLASH memory with FLASH Programming capability.
consumption when the application is in idle or
standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes.
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Under software control, all devices can be placed
in WAIT, SLOW, or HALT mode, reducing power
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Figure 1. General Block Diagram
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Internal
CLOCK
OSCIN
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LVD
VDD
POWER
SUPPLY
VSS
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VPP
CONTROL
8-BIT CORE
ALU
USB DMA
PROGRAM
MEMORY
(8 or 16K Bytes)
1
10-BIT ADC
PORT A
PA7:0
(8 bits)
SCI
PB7:0
(8 bits)
PWM ART
TIME BASE UNIT
USB SIE
USBDP
USBDM
USBVCC
PORT C
PC7:0
(8 bits)
SPI
RAM
(384,
or 768 Bytes)
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PORT B
ADDRESS AND DATA BUS
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RESET
VSSA
)-
OSCILLATOR
OSCOUT
VDDA
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PORT D
WATCHDOG
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PD6:0
(7 bits)
ST7262xxx
2 PIN DESCRIPTION
Reserved*
VDDA
USBVCC
USBDP
USBDM
VSSA
N.C.
ICCDATA /IT7 / PWM0 / PB6 (HS)
ICCCLK / IT6 / ARTIC2 / PB5 (HS)
IT5 / ARTIC1 / PB4 (HS)
ARTCLK / PB3 (HS)
TDO / PB2 (HS)
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
VSS
VDD
PC1
PC0
IT8 / PWM1 / PB7
VPP
PD1
PD0
PC7
MOSI / PC6
IT12 / MISO / PC5
IT11 / SS / PC4
IT10 / SCK / PC3
IT9 / PC2
OSCIN
OSCOUT
PD5
PD6
PD2
PD3
PD4
Figure 2. 44-pin LQFP and 42-Pin SDIP Package Pinouts
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PD5
PD4
PD3
PD2
VPP
PD1
PD0
PC7
MOSI / PC6
IT12 / MISO / PC5
IT11 / SS / PC4
IT10 / SCK / PC3
IT9 / PC2
OSCIN
OSCOUT
VSS
VDD
PC1
PC0
IT8 / PWM1 / PB7 (HS)
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PD6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
RESET
PA0 / AIN0 / IT1 / USBOE
PA1 / AIN1 / IT2
PA2 / AIN2 / IT3
PA3 / AIN3 / IT4
PA4 / AIN4
PA5 / AIN5
PA6 / AIN6
PA7 / AIN7
PB0 (HS) / MCO
PB1 (HS) / RDI
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* Pin 39 of the LQFP44 package
must be left unconnected.
VDDA
USBVCC
USBDP
USBDM
VSSA
RESET
PA0 / AIN0 / IT1 / USBOE
PA1 / AIN1 / IT2
PA2 / AIN2 / IT3
PA3 / AIN3 / IT4
PA4 / AIN4
PA5 / AIN5
PA6 / AIN6
PA7 / AIN7
PB0 (HS) / MCO
PB1 (HS) / RDI
PB2 (HS) / TDO
PB3 (HS) / ARTCLK
PB4 (HS) / ARTIC1 / IT5
PB5 (HS) / ARTIC2 / IT6 / ICCCLK
PB6 (HS) / PWM0 / IT7 / ICCDATA
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ST7262xxx
PIN DESCRIPTION (Cont’d)
Figure 3. 34-Pin SO and 32-Pin SDIP Package Pinouts
IT10 / SCK / PC3
1
34
PC4 / SS / INT11
IT9 / PC2
OSCIN
2
33
PC5 / MISO / IT12
3
32
PC6 / MOSI
OSCOUT
4
31
PC7
VSS
5
30
VDD
6
29
PC1
IT8 / PWM1 / PB7 (HS)
ICCDATA / IT7 / PWM0 / PB6 (HS)
7
28
8
27
RESET
VPP
VDDA
USBVCC
9
26
ICCCLK / IT6 /ARTIC2 / PB5 (HS)
IT5 / ARTIC1 / PB4 (HS)
10
25
USBDP
USBDM
11
24
VSSA
ARTCLK / PB3 (HS)
12
23
TDO / PB2 (HS)
13
22
RDI / PB1 (HS)
MCO / PB0 (HS)
14
21
15
20
PA0 / AIN0 / IT1 / USBOE
PA1 / AIN1 / IT2
PA2 / AIN2 / IT3
PA3 / AIN3 / IT4
AIN7 / PA7
16
19
PA4 / AIN4
AIN6 / PA6
17
IT10 / SCK / PC3
IT9 / PC2
OSCIN
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OSCOUT
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PA5 / AIN5
32
PC4 / SS / INT11
31
PC5 / MISO / IT12
3
30
4
29
PC6 / MOSI
RESET
VPP
2
VSS
5
28
VDD
IT8 / PWM1 / PB7 (HS)
ICCDATA / IT7 / PWM0 / PB6 (HS)
6
27
7
26
VDDA
USBVCC
8
25
USBDP
ICCCLK / IT6 / ARTIC2 / PB5 (HS)
IT5 / ARTIC1 / PB4 (HS)
9
24
10
23
USBDM
VSSA
ARTCLK / PB3 (HS)
11
22
TDO / PB2 (HS)
12
21
RDI / PB1 (HS)
MCO / PB0 (HS)
13
20
14
19
AIN7 / PA7
15
18
PA4 / AIN4
AIN6 / PA6
16
17
PA5 / AIN5
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PA0 / AIN0 / IT1 / USBOE
PA1 / AIN1 / IT2
PA2 / AIN2 / IT3
PA3 / AIN3 / IT4
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ST7262xxx
Figure 4. 20-pin SO20 Package Pinout
PB0 (HS) / MCO
PB1 (HS)
IT3 / AIN2 / PA2
1
20
IT2 / AIN1 / PA1
USBOE/ IT1 / AIN0/ PA0
VSS
2
19
3
18
4
17
USBDM
5
16
PB4 (HS) / ARTIC1 / IT5
PB2 (HS)
PB3 (HS) / ARTCLK
USBDP
USBVCC
VDD
6
15
PB5 (HS) / ARTIC2 / IT6 / ICCCLK
7
14
8
13
VPP
9
12
PB6 (HS) / PWM0 / IT7/ ICCDATA
PB7 (HS) / PWM1 / IT8
OSCOUT
RESET
10
11
OSCIN
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e
Figure 5. 20-pin DIP20 Package Pinout
t
e
l
o
IT5 / ARTIC1 / PB4 (HS)
ARTCLK / PB3 (HS)
PB2 (HS)
1
20
PB5 (HS) / ARTIC2 / IT6 / ICCCLK
2
19
3
18
PB1 (HS)
MCO / PB0 (HS)
IT3 / AIN2 / PA2
4
17
5
16
PB6 (HS) / PWM0 / IT7/ICCDATA
PB7 (HS) / PWM1 / IT8
OSCOUT
OSCIN
RESET
IT2 / AIN1/ PA1
7
USBDM
)
(s
6
USBOE / IT1 / AIN0 / PA0
VSS
t
c
u
d
o
r
)
s
(
ct
8
9
10
15
s
b
O
14
VPP
13
12
VDD
USBVCC
11
USBDP
P
e
t
e
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o
s
b
O
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ST7262xxx
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations:
Type:
I = Input, O = Output, S = Supply
Input level:
A = Dedicated analog input
Input level:
C = CMOS 0.3VDD/0.7VDD,
CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level:
HS = High Sink (on N-buffer only)
Port configuration capabilities:
– Input:float = floating, wpu = weak pull-up, int = interrupt (\ =falling edge, / =rising edge),
ana = analog
– Output: OD = open drain, T = true open drain (N buffer 8mA@0.4 V), PP = push-pull
)
s
(
ct
Table 1. Device Pin Description
6 29 28 9 14 VPP
2
7
-
-
-
-
PD1
I/O CT
x
3
8
-
-
-
-
PD0
I/O CT
4
9 31
-
-
-
PC7
5 10 32 30
-
-
PC6/MOSI
6 11 33 31
-
-
PC5/MISO/IT12
7 12 34 32
-
-
PC4/SS/IT11
13 1
O
2
-
-
-
-
PP
OD
ana
int
Main
Output Function Alternate Function
(after
reset)
r
P
e
t
e
l
o
x
s
b
O
FLASH programming voltage
(12V), must be tied low in user
mode.
x
Port D1
x
x
Port D0
I/O CT
x
x
Port C7
I/O CT
t
c
u
x
x
Port C6
I/O CT
x
x
x
Port C5
I/O CT
x
x
x
Port C4
PC3/SCK/IT10
I/O CT
x
x
x
Port C3
PC2/IT9
I/O CT
x
x
x
Port C2
)
(s
od
r
P
e
t
e
l
o
1
bs
9 14 2
S
wpu
Input
1
8
u
d
o
Port / Control
float
Output
Input
DIP20
SO20
Pin Name
Type
Level
DIP32
SO34
DIP42
LQFP44
Pin n°
SPI Master Out /
Slave In 1)
SPI Master In /
Slave Out 1) /
Interrupt 12 input
SPI Slave Select
(active low) 1)/
Interrupt 11 input
SPI Serial Clock 1)/
Interrupt 10 input
Interrupt 9 input
These pins are used connect an
external clock source to the onchip main oscillator.
10 15 3
3 11 16 OSCIN
11 16 4
4 12 17 OSCOUT
12 17 5
5
4
9 VSS
S
Digital Ground Voltage
13 18 6
6
8 13 VDD
S
Digital Main Power Supply Voltage
14 19 7
-
-
-
PC1
I/O CT
x
T
Port C1
15 20
-
-
-
PC0
I/O CT
x
T
Port C0
I/O CT HS
x
-
16 21 8
17
8/139
-
-
PB7/PWM1/IT8/
7 13 18 RX_SEZ/DATAOUT/DA9
\
N.C.
x
Port B7
ART PWM output 1/
Interrupt 8 input
Not Connected
Doc ID 6996 Rev 5
ST7262xxx
PB6/PWM0/IT7/
8 14 19
ICCDATA
Port / Control
PP
Main
Output Function Alternate Function
(after
reset)
OD
ana
int
wpu
Input
float
Input
Type
DIP20
SO20
DIP32
SO34
DIP42
LQFP44
18 22 9
Pin Name
Output
Level
Pin n°
ART PWM output 0/
Interrupt 7 input/InCircuit Communication Data
ART Input Capture 2/
Interrupt 6 input/
In-Circuit Communication Clock
ART Input Capture
1/Interrupt 5 input
I/O CT HS
x
\
x
Port B6
PB5/ARTIC2/IT6/
ICCCLK
I/O CT HS
x
/
x
Port B5
20 24 11 10 16 1 PB4/ARTIC1/IT5
I/O CT HS
x
/
x
Port B4
21 25 12 11 17 2 PB3/ARTCLK
I/O CT HS
x
x
Port B3
22 26 13 12 18 3 PB2/TDO
I/O CT HS
x
x
Port B2
23 27 14 13 19 4 PB1/RDI
I/O CT HS
x
x
Port B1
24 28 15 14 20 5 PB0/MCO
I/O CT HS
x
x
Port B0
CPU clock output
25 29 16 15
-
-
PA7/AIN7
I/O CT
x
x
Port A7
ADC Analog Input 7
26 30 17 16
-
-
PA6/AIN6
I/O CT
x
x
Port A6
ADC Analog Input 6
27 31 18 17
-
-
PA5/AIN5
I/O CT
x
x
x
Port A5
ADC Analog Input 5
28 32 19 18
-
-
PA4/AIN4
I/O CT
x
x
x
Port A4
ADC Analog Input 4
29 33 20 19
-
-
PA3/AIN3/IT4
19 23 10 9 15 20
6 PA2/AIN2/IT3
31 35 22 21 2
7 PA1/AIN1/IT2
e
t
e
l
32 36 23 22 3
o
s
b
8
Pr
PA0/AIN0/IT1/
USBOE
33 37 30 29 10 15 RESET
O
34 38 24 23
-
t
c
u
od
30 34 21 20 1
-
VSSA
)
(s
x
x
I/O CT
x
\
x
x
I/O CT
x
\
x
x
I/O CT
x
\
x
x
I/O CT
x
\
x
x
I/O
C
S
u
d
o
ART Clock input
SCI Transmit Data
Output 1)
SCI Receive Data
Input 1)
r
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ct
ADC Analog Input 3/
Interrupt 4 input
ADC Analog Input 2/
Port A2
Interrupt 3 input
ADC Analog Input 1/
Port A1
Interrupt 2 input
ADC Analog Input 0/
Port A0
Interrupt 1 input/
USB Output Enable
Top priority non maskable interrupt (active low)
Analog Ground Voltage, must
be connected externally to VSS.
Port A3
35 39 25 24 5 10 USBDM
I/O
USB bidirectional data (data -)
36 40 26 25 6 11 USBDP
I/O
USB bidirectional data (data +)
37 41 27 26 7 12 USBVCC
S
USB power supply 3.3V output
38 42 28 27
-
-
VDDA
S
Analog Power Supply Voltage,
must be connected externally to
VDD.
39
-
-
-
-
-
Reserved
Must be left unconnected.
40 1
-
-
-
-
PD6
I/O CT
x
x
Port D6
41 2
-
-
-
-
PD5
I/O CT
x
x
Port D5
42 3
-
-
-
-
PD4
I/O CT
x
x
Port D4
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ST7262xxx
Port / Control
PD3
I/O CT
x
x
Port D3
44 5
-
-
-
-
PD2
I/O CT
x
x
Port D2
PP
OD
-
ana
-
int
-
wpu
-
float
DIP20
43 4
Input
SO20
Main
Output Function Alternate Function
(after
reset)
DIP32
Input
SO34
Pin Name
Output
Type
Level
DIP42
LQFP44
Pin n°
Note 1: Peripheral not present on all devices. Refer to “Device Summary” on page 1.
2.1 PCB LAYOUT RECOMMENDATION
)
s
(
ct
In the case of DIP20 devices the user should layout the PCB so that the DIP20 ST7262 device and
the USB connector are centered on the same axis
ensuring that the D- and D+ lines are of equal
length. Refer to Figure 6
r
P
e
Figure 6. Recommended PCB Layout for USB Interface with DIP20 package
1
20
2
19
3
18
4
17
5
7
ct
8
du
USBDM
e
t
e
ol
bs
o
r
P
9
10
ST7262
)
(s
6
16
15
t
e
l
o
s
b
O
14
13
12
USBVCC
11
USBDP
1.5KOhm pull-up resistor
Ground
Ground
USB Connector
O
10/139
u
d
o
Doc ID 6996 Rev 5
ST7262xxx
3 REGISTER & MEMORY MAP
As shown in the Figure 7, the MCU is capable of
addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 64
bytes of register locations, 768 bytes of RAM and
up to 16 Kbytes of user program memory. The
RAM space includes up to 128 bytes for the stack
from 0100h to 017Fh.
The highest address bytes contain the user reset
and interrupt vectors.
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the
device.
)
s
(
ct
Figure 7. Memory Map
0040h
0000h
HW Registers
(see Table 2)
003Fh
0040h
00FFh
017Fh
768 Bytes RAM
)
(s
033Fh
0340h
Reserved
t
c
u
s
b
O
00FFh
017Fh
P
e
t
e
l
o
FFDFh
FFE0h
0040h
d
o
r
16 KBytes
E000h
s
b
O
01BFh
Program Memory
8 KBytes
u
d
o
r
P
e
16-bit Addressing
RAM
or Stack
(128 Bytes)
t
e
l
o
384 Bytes RAM
BFFFh
C000h
Short Addressing
RAM (zero page)
192 Bytes
033Fh
16-bit Addressing
RAM
64 Bytes
Short Addressing
RAM (zero page)
192 Bytes
16-bit Addressing
RAM
or Stack
(128 Bytes)
16-bit Addressing
RAM
448 Bytes
Interrupt & Reset Vectors
(see Table 6)
FFFFh
Doc ID 6996 Rev 5
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ST7262xxx
Table 2. Hardware Register Map
Register
Label
Reset
Status
Address
Block
Register Name
0000h
0001h
Port A
PADR
PADDR
Port A Data Register
Port A Data Direction Register
00h1)
00h
R/W2)
R/W2)
0002h
0003h
Port B
PBDR
PBDDR
Port B Data Register
Port B Data Direction Register
00h1)
00h
R/W2)
R/W2)
0004h
0005h
Port C
PCDR
PCDDR
Port C Data Register
Port C Data Direction Register
00h1)
00h
R/W2)
R/W2)
0006h
0007h
Port D
PDDR
PDDDR
Port D Data Register
Port D Data Direction Register
00h1)
00h
R/W2)
R/W2)
0008h
ITRFRE1
Interrupt Register 1
00h
0009h
MISC
Miscellaneous Register
00h
000Ah
000Bh
000Ch
ADC
ADCDRMSB ADC Data Register (bit 9:2)
ADCDRLSB ADC Data Register (bit 1:0)
ADCCSR
ADC Control Status Register
000Dh
WDG
WDGCR
Watchdog Control Register
000Eh
0010h
SPI
PWM ART
12/139
PWMDCR1
PWMDCR0
PWMCR
ARTCSR
ARTCAR
ARTARR
ARTICCSR
ARTICR1
ARTICR2
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
s
(
t
c
du
o
r
P
SCIERPR
SCIETPR
SCI
)-
SPIDR
SPICR
SPICSR
e
t
e
ol
s
b
O
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
R/W
R/W
Read Only
Read Only
R/W
7Fh
R/W
xxh
0xh
00h
R/W
R/W
Read Only
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
Reserved Area (3 Bytes)
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
00h
00h
00h
)
s
(
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u
d
o
r
P
e
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o
s
b
O
Remarks
PWM AR Timer Duty Cycle Register 1
PWM AR Timer Duty Cycle Register 0
PWM AR Timer Control Register
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
ART Input Capture Control/Status Register
ART Input Capture Register 1
ART Input Capture Register 2
SCI Extended Receive Prescaler register
SCI Extended Transmit Prescaler Register
Reserved Area
SCI Status register
SCI Data register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
Doc ID 6996 Rev 5
00h
00h
-C0h
xxh
00h
x000 0000b
00h
R/W
R/W
Read Only
R/W
R/W
R/W
R/W
ST7262xxx
Address
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
Block
Register
Label
USB
USBPIDR
USBDMAR
USBIDR
USBISTR
USBIMR
USBCTLR
USBDADDR
USBEP0RA
USBEP0RB
USBEP1RA
USBEP1RB
USBEP2RA
USBEP2RB
Reset
Status
Register Name
USB PID Register
USB DMA Address register
USB Interrupt/DMA Register
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
USB Device Address Register
USB Endpoint 0 Register A
USB Endpoint 0 Register B
USB Endpoint 1 Register A
USB Endpoint 1 Register B
USB Endpoint 2 Register A
USB Endpoint 2 Register B
0032h
to
0035h
x0h
xxh
x0h
00h
00h
06h
00h
0000 xxxxb
80h
0000 xxxxb
0000 xxxxb
0000 xxxxb
0000 xxxxb
TBU
0038h
FLASH
0039h
TBUCV
TBUCSR
TBU Counter Value Register
TBU Control/Status Register
FCSR
Flash Control/Status Register
ITRFRE2
Interrupt Register 2
r
P
e
)
(s
003Ah
to
003Fh
let
so
b
O
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
)
s
(
ct
u
d
o
Reserved Area (4 Bytes)
0036h
0037h
Remarks
00h
00h
R/W
R/W
00h
R/W
00h
R/W
Reserved Area (6 Bytes)
t
c
u
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
d
o
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ST7262xxx
4 FLASH PROGRAM MEMORY
4.1 INTRODUCTION
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 3). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
The first two sectors have a fixed size of 4 Kbytes
(see Figure 8). They are mapped in the upper part
of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).
The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply.
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
■
■
Available Sectors
r
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4K
Sector 0
8K
3 Flash programming modes:
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be programmed or erased.
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be programmed or erased without removing the device from the application board.
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the
application is running.
ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
Read-out protection
Register Access Security System (RASS) to
prevent accidental programming or erasing
Sectors 0,1
t
e
l
o
> 8K
Sectors 0,1, 2
4.3.1 Read-out Protection
Read-out protection, when selected, provides a
protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the entire
program memory is first automatically erased and
the device can be reprogrammed.
Read-out protection selection depends on the device type:
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
– In ROM devices it is enabled by mask option
specified in the Option List.
)
(s
■
u
d
o
Flash Size (bytes)
4.2 MAIN FEATURES
■
)
s
(
ct
Table 3. Sectors available in Flash devices
t
c
u
d
o
r
P
e
t
e
l
o
4.3 STRUCTURE
s
b
O
The Flash memory is organised in sectors and can
be used for both code and data storage.
s
b
O
Figure 8. Memory Map and Sector Address
4K
8K
10K
16K
24K
32K
48K
60K
1000h
FLASH
MEMORY SIZE
3FFFh
7FFFh
9FFFh
SECTOR 2
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
14/139
2 Kbytes
8 Kbytes
16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes
4 Kbytes
4 Kbytes
Doc ID 6996 Rev 5
SECTOR 1
SECTOR 0
ST7262xxx
FLASH PROGRAM MEMORY (Cont’d)
–
–
–
–
ICCCLK: ICC output serial clock pin
ICCDATA: ICC input/output serial data pin
ICCSEL/VPP: programming voltage
OSC1(or OSCIN): main clock input for external source (optional)
– VDD: application board power supply (see Figure 9, Note 3)
4.4 ICC INTERFACE
ICC (In-Circuit Communication) needs a minimum
of four and up to six pins to be connected to the
programming tool (see Figure 9). These pins are:
– RESET: device reset
– VSS: device power supply ground
Figure 9. Typical ICC Interface
PROGRAMMING TOOL
)
s
(
ct
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
9
7
5
3
1
10
8
6
4
2
ST7
u
d
o
r
P
e
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
2. During the ICC session, the programming tool
must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor 1K or a reset man-
s
b
O
t
e
l
o
s
b
O
ICCDATA
VSS
s
(
t
c
)ICCSEL/VPP
OSC1
VDD
OSC2
CL1
ICCCLK
CL2
r
P
e
t
e
l
o
10kΩ
APPLICATION
POWER SUPPLY
u
d
o
ICC CONNECTOR
HE10 CONNECTOR TYPE
OPTIONAL
(See Note 4)
RESET
(See Note 3)
APPLICATION
RESET SOURCE
See Note 2
See Note 1
APPLICATION
I/O
agement IC with open drain output and pull-up
resistor > 1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Programming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multioscillator capability need to have OSC2
grounded in this case.
Doc ID 6996 Rev 5
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ST7262xxx
FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (IN-CIRCUIT PROGRAMMING)
4.7 RELATED DOCUMENTATION
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface
for downloading).
When using an STMicroelectronics or third-party
programming tool that supports ICP and the specific microcontroller device, the user needs only to
implement the ICP hardware interface on the application board (see Figure 9). For more details on
the pin locations, refer to the device pinout description.
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.
4.6 IAP (IN-APPLICATION PROGRAMMING)
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (user-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI or
other type of serial interface and program it in the
Flash. IAP mode can be used to program any of
the Flash sectors except Sector 0, which is write/
erase protected to allow recovery in case errors
occur during the programming operation.
4.8 REGISTER DESCRIPTION
FLASH CONTROL/STATUS REGISTER (FCSR)
du
7
0
)
(s
0
0
d
o
r
P
e
t
e
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o
s
b
O
Doc ID 6996 Rev 5
0
e
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u
16/139
)
s
(
ct
Read/Write
Reset Value: 0000 0000 (00h)
0
o
r
P
0
0
0
0
ST7262xxx
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
5.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The 6 CPU registers shown in Figure 10 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
5.2 MAIN FEATURES
■
■
■
■
■
■
■
■
Enable executing 63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes (with indirect
addressing mode)
Two 8-bit index registers
16-bit stack pointer
Low power HALT and WAIT modes
Priority maskable hardware interrupts
Non-maskable software/hardware interrupts
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Figure 10. CPU Registers
7
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0
ACCUMULATOR
RESET VALUE = XXh
7
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15
PCH
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
8 7
PCL
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
0
1 1 I1 H I0 N Z C
CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8 7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
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ST7262xxx
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Reset Value: 111x1xxx
7
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
0
1
1
I1
H
I0
N
Z
This bit is accessed by the JREQ and JRNE test
instructions.
C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
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Arithmetic Management Bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
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Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the current interrupt software priority.
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Pr
This bit is accessed by the JRMI and JRPL instructions.
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Interrupt Software Priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
I0
0
1
0
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
See the interrupt management chapter for more
details.
Bit 1 = Z Zero.
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I1
1
0
0
1
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ST7262xxx
CPU REGISTERS (Cont’d)
STACK POINTER (SP)
Read/Write
Reset Value: 017Fh
15
8
0
0
0
0
0
0
0
7
1
0
1
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 11).
Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
@ 0100h
od
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PUSH Y
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POP Y
RET
or RSP
IRET
SP
SP
CC
A
Y
CC
A
SP
CC
A
X
X
X
PCH
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
SP
@ 017Fh
Interrupt
Event
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Figure 11. Stack Manipulation Example
CALL
Subroutine
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 11.
– When an interrupt is received, the SP is decremented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
SP
SP
Stack Higher Address = 017Fh
Stack Lower Address = 0100h
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ST7262xxx
6 CLOCKS AND RESET
6.1 CLOCK SYSTEM
6.1.1 General Description
The MCU accepts either a Crystal or Ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the external oscillator frequency (fOSC),
by dividing by 3 and multiplying by 2. By setting the
OSC12/6 bit in the option byte, a 12 MHz external
clock can be used giving an internal frequency of 8
MHz while maintaining a 6 MHz clock for USB (refer to Figure 14).
The internal clock signal (fCPU) consists of a
square wave with a duty cycle of 50%.
It is further divided by 1, 2, 4 or 8 depending on the
Slow Mode Selection bits in the Miscellaneous
register (SMS[1:0])
The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz or ceramic resonator in the frequency range specified for fosc.
The circuit shown in Figure 13 is recommended
when using a crystal, and Table 4 lists the recommended capacitors. The crystal and associated
components should be mounted as close as possible to the input pins in order to minimize output
distortion and start-up stabilization time.
6.1.2 External Clock input
An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as
shown on Figure 12. The tOXOV specifications
does not apply when using an external clock input.
The equivalent specification of the external clock
source should be used instead of tOXOV (see Electrical Characteristics).
6.1.3 Clock Output Pin (MCO)
The internal clock (fCPU) can be output on Port B0
by setting the MCO bit in the Miscellaneous register.
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Figure 12. External Clock Source Connections
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EXTERNAL
CLOCK
Table 4. Recommended Values for 12 MHz
Crystal Resonator
RSMAX
20 Ω
COSCIN
56pF
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COSCOUT
RP
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56pF
1-10 MΩ
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25 Ω
47pF
70 Ω
Figure 13. Crystal/Ceramic Resonator
22pF
47pF
22pF
1-10 MΩ
1-10 MΩ
OSCIN
Note: RSMAX is the equivalent serial resistor of the
crystal (see crystal specification).
Note: When a crystal is used, and to not overstress the crystal, ST recommends to add a serial
resistor on the OSCOUT pin to limit the drive level
in accordance with the crystal manufacturer’s
specification. Please also refer to Section 12.5.4.
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OSCOUT
OSCIN
COSCIN
Doc ID 6996 Rev 5
OSCOUT
COSCOUT
ST7262xxx
Figure 14. Clock block diagram
fCPU 8/4/2/1 MHz
(or 4/2/1/0.5 MHz)
Slow
Mode
%
1/2/4/8
x2
to CPU and
peripherals
SMS[1:0]
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%3
MCO pin
OSC12/6
0
12 or
6 MHz
Crystal
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6 MHz (USB)
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6.2 RESET
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The Reset procedure is used to provide an orderly
software start-up or to exit low power modes.
Three reset modes are provided: a low voltage reset, a watchdog reset and an external reset at the
RESET pin.
A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution starting
from this point.
An internal circuitry provides a 514 CPU clock cycle delay from the time that the oscillator becomes
active.
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recommended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behaviour.
It is recommended to make sure that the VDD supply
voltage rises monotonously when the device is exiting from Reset, to ensure the application functions
properly.
6.2.1 Low Voltage Reset
Low voltage reset circuitry generates a reset when
VDD is:
■ below VIT+ when VDD is rising,
■ below VIT- when VDD is falling.
During low voltage reset, the RESET pin is held low,
thus permitting the MCU to reset other devices.
Notes:
The Low Voltage Detector can be disabled by setting the LVD bit of the Option byte.
Figure 15. Low Voltage Reset functional Diagram
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6.2.2 Watchdog Reset
When a watchdog reset occurs, the RESET pin is
pulled low permitting the MCU to reset other devices as when low voltage reset (Figure 15).
6.2.3 External Reset
The external reset is an active low input signal applied to the RESET pin of the MCU.
As shown in Figure 18, the RESET signal must
stay low for a minimum of one and a half CPU
clock cycles.
An internal Schmitt trigger at the RESET pin is provided to improve noise immunity.
RESET
VDD
LOW VOLTAGE
RESET
INTERNAL
RESET
FROM
WATCHDOG
RESET
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ST7262xxx
Figure 16. Low Voltage Reset Signal Output
VIT+
VITVDD
RESET
Note: Typical hysteresis (VIT+-VIT-) of 250 mV is expected.
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Figure 17. Temporization Timing Diagram after an internal Reset
VIT+
VDD
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Temporization
(514 CPU clock cycles)
$FFFE
Addresses
Figure 18. Reset Timing Diagram
tDDR
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VDD
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OSCIN
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fCPU
)
(s
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PC
RESET
tOXOV
FFFE
FFFF
514 CPU
CLOCK
CYCLES
DELAY
Note: Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+ and VIT-.
22/139
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ST7262xxx
Figure 19. Reset Block Diagram
VDD
RON
200ns
Filter
RESET
tw(RSTL)out + 128 fOSC
delay
INTERNAL
RESET
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WATCHDOG RESET
PULSE
GENERATOR
LVD RESET
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Note: The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
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ST7262xxx
7 INTERRUPTS
7.1 INTRODUCTION
The CPU enhanced interrupt management provides the following features:
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 3 non maskable events: RESET, TRAP, TLI
This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nested) CPU interrupt controller.
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
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Interrupt software priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
)
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7.2 MASKING AND PROCESSING FLOW
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 5). The processing flow is shown in Figure 20.
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Table 5. Interrupt Software Priority Levels
Level
Low
I1
1
0
0
1
High
I0
0
1
0
1
Figure 20. Interrupt Processing Flowchart
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PENDING
INTERRUPT
Y
Interrupt has the same or a
lower software priority
than current one
N
FETCH NEXT
INSTRUCTION
Y
TLI
THE INTERRUPT
STAYS PENDING
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
N
I1:0
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
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Y
Interrupt has a higher
software priority
than current one
let
RESET
Doc ID 6996 Rev 5
ST7262xxx
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
As several interrupts can be pending at the same
time, the interrupt to be taken into account is determined by the following two-step process:
– the highest software priority interrupt is serviced,
– if several interrupts have the same software priority then the interrupt with the highest hardware
priority is serviced first.
Figure 21 describes this decision process.
PENDING
INTERRUPTS
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Different
SOFTWARE
PRIORITY
TRAP (Non Maskable Software Interrupt)
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced according to the flowchart in Figure 20 as a TLI.
Caution: TRAP can be interrupted by a TLI.
■ RESET
The RESET source has the highest priority in the
CPU. This means that the first current routine has
the highest software priority (level 3) and the highest hardware priority.
See the RESET chapter for more details.
■
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Figure 21. Priority Decision Process
Same
TLI (Top Level Hardware Interrupt)
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin.
Caution: A TRAP instruction must not be used in a
TLI service routine.
■
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HIGHEST SOFTWARE
PRIORITY SERVICED
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.
■ External Interrupts
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the ITRFRE2 register.
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically NANDed.
■ Peripheral Interrupts
Usually the peripheral interrupts cause the Device
to exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear sequence is executed.
)
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HIGHEST HARDWARE
PRIORITY SERVICED
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When an interrupt request is not serviced immediately, it is latched and then processed when its
software priority combined with the hardware priority becomes the highest one.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI can be considered
as having the highest software priority in the decision process.
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Different Interrupt Vector Sources
Two interrupt source types are managed by the
CPU interrupt controller: the non-maskable type
(RESET, TLI, TRAP) and the maskable type (external or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 20). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
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ST7262xxx
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exiting HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision process shown in Figure 21.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
The following Figure 22 and Figure 23 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in
Figure 23. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without notifying the software of the failure.
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IT0
TLI
IT3
IT4
IT1
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SOFTWARE
PRIORITY
LEVEL
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TLI
IT0
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IT2
du
RIM
MAIN
11 / 10
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IT1
IT1
-O
IT3
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IT4
MAIN
I1
I0
3
1 1
3
1 1
3
1 1
3
1 1
3
1 1
3
1 1
USED STACK = 10 BYTES
HARDWARE PRIORITY
IT2
Figure 22. Concurrent Interrupt Management
3/0
10
IT0
TLI
IT3
IT4
IT1
SOFTWARE
PRIORITY
LEVEL
TLI
IT0
IT1
IT1
IT2
IT2
IT3
RIM
IT4
IT4
MAIN
MAIN
11 / 10
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I1
I0
3
1 1
3
1 1
2
0 0
1
0 1
3
1 1
3
1 1
3/0
USED STACK = 20 BYTES
HARDWARE PRIORITY
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IT2
Figure 23. Nested Interrupt Management
ST7262xxx
INTERRUPTS (Cont’d)
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
7.5 INTERRUPT REGISTER DESCRIPTION
CPU CC REGISTER INTERRUPT BITS
Read/Write
Reset Value: 111x 1010 (xAh)
7
7
1
0
1
I1
H
I0
N
Z
Level
Low
I1
1
0
0
1
High
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I0_3
I1_2
I0_2
I1_1
I0_1
I1_0
I0_0
ISPR1
I1_7
I0_7
I1_6
I0_6
I1_5
I0_5
I1_4
I0_4
ISPR2
I1_11 I0_11 I1_10 I0_10 I1_9
I0_9
I1_8
I0_8
1
1
1
1
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I1_13 I0_13 I1_12 I0_12
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These four registers contain the interrupt software
priority of each interrupt vector.
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This correspondence is shown in the following table.
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I1_3
ISPR3
I0
0
1
0
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see “Interrupt Dedicated Instruction
Set” table).
*Note: TLI, TRAP and RESET events can interrupt
a level 3 program.
r
P
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ISPR0
C
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt software priority.
Interrupt Software Priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable*)
0
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Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
FFE1h-FFE0h
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
I1_13 and I0_13 bits
– Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h)
The RESET, TRAP and TLI vectors have no software priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they
are not significant in the interrupt process management.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the interrupt x).
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ST7262xxx
INTERRUPTS (Cont’d)
INTERRUPT REGISTER 1 (ITRFRE1)
Address: 0008h - Read/Write
Reset Value: 0000 0000 (00h)
7
Bit 5:4 = CTL[1:0] IT[10:9]1nterrupt Sensitivity
These bits are set and cleared by software. They
are used to configure the edge and level sensitivity
of the IT10 and IT9 external interrupt pins (this
means that both must have the same sensitivity).
0
IT8E
IT7E
IT6E
IT5E
IT4E
IT3E
IT2E
IT1E
Bit 7:0 = ITiE Interrupt Enable
0: I/O pin free for general purpose I/O
1: ITi external interrupt enabled.
Note: The corresponding interrupt is generated
when:
– a rising edge occurs on the IT5/IT6 pins
– a falling edge occurs on the IT1, 2, 3, 4, 7 and 8
pins
CTL1
0
0
1
1
CTL0
0
1
0
1
Bit 3:0 = ITiE Interrupt Enable
0: I/O pin free for general purpose I/O
1: ITi external interrupt enabled.
7
)
(s
0
r
P
e
s
b
O
t
c
u
CTL3 CTL2 CTL1 CTL0 IT12E IT11E IT10E IT9E
d
o
r
Bit 7:6 = CTL[3:2] IT[12:11] Interrupt Sensitivity
These bits are set and cleared by software. They
are used to configure the edge and level sensitivity
of the IT12 and IT11 external interrupt pins (this
means that both must have the same sensitivity).
P
e
CTL2
0
1
0
1
t
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)
s
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ct
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e
l
o
INTERRUPT REGISTER 2 (ITRFRE2)
Address: 0039h - Read/Write
Reset Value: 0000 0000 (00h)
CTL3
0
0
1
1
IT[10:9] Sensitivity
Falling edge and low level
Rising edge only
Falling edge only
Rising and falling edge
IT[12:11] Sensitivity
Falling edge and low level
Rising edge only
Falling edge only
Rising and falling edge
Doc ID 6996 Rev 5
ST7262xxx
INTERRUPTS (Cont’d)
Table 6. Interrupt Mapping
Source
Block
N°
Register
Label
Description
Priority
Order
Reset
TRAP software interrupt
ICP
FLASH Start programming NMI interrupt
1
USB
USB End Suspend interrupt
3
I/O Ports
4
Address
Vector
Yes
FFFEh-FFFFh
Highest
Priority
0
2
Exit
from
HALT
USBISTR
No
FFFCh-FFFDh
Yes
FFFAh-FFFBh
Yes
FFF8h-FFF9h
)
s
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Port A external interrupts IT[4:1]
ITRFRE1
Yes
FFF6h-FFF7h
Port B external interrupts IT[8:5]
ITRFRE1
Yes
FFF4h-FFF5h
Port C external interrupts IT[12:9]
ITRFRE2
Yes
5
TBU
Timebase Unit interrupt
TBUCSR
No
6
ART
ART/PWM Timer interrupt
ICCSR
Yes
SPI
SPI interrupt vector
SPISR
Yes
8
SCI
SCI interrupt vector
SCISR
No
9
USB
USB interrupt vector
USBISTR
10
ADC
A/D End of conversion interrupt
ADCCSR
e
t
e
l
o
s
b
Reserved area
u
d
o
Pr
7
Lowest
Priority
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
No
FFE8h-FFE9h
No
FFE6h-FFE7h
FFE0h-FFE5h
O
)
Table 7. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
u
d
o
Ext. Interrupt Port B
0032h
0033h
ISPR0
Reset Value
o
s
b
O
0034h
e
t
e
l
ISPR1
Reset Value
ISPR2
Reset Value
Pr
I1_3
1
s
(
t
c
I0_3
1
5
Ext. Interrupt Port A
I1_2
1
SPI
I1_7
1
I0_2
1
3
2
I0_7
1
I1_6
1
I1_1
1
I1_5
1
ADC
I0_11
1
I1_10
1
I0_1
1
TBU
I0_6
1
ISPR3
Reset Value
1
1
1
0
Not Used
1
1
Ext. Interrupt Port C
I0_5
1
I1_4
1
USB
I0_10
1
I1_9
1
1
Doc ID 6996 Rev 5
I1_13
1
I0_4
1
SCI
I0_9
1
Not Used
0035h
1
USB END SUSP
ART
Not Used
I1_11
1
4
I0_13
1
I1_8
1
I0_8
1
Not Used
I1_12
1
I0_12
1
29/139
ST7262xxx
8 POWER SAVING MODES
8.1 INTRODUCTION
There are three Power Saving modes. Slow Mode
is selected by setting the SMS bits in the Miscellaneous register. Wait and Halt modes may be entered using the WFI and HALT instructions.
After a RESET the normal operating mode is selected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 3 and multiplied by 2 (fCPU).
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
8.1.1 Slow Mode
In Slow mode, the oscillator frequency can be divided by a value defined in the Miscellaneous
Register. The CPU and peripherals are clocked at
this lower frequency. Slow mode is used to reduce
power consumption, and enables the user to adapt
clock frequency to available supply voltage.
Figure 24. WAIT Mode Flow Chart
WFI INSTRUCTION
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
N
u
d
o
RESET
s
b
O
ct
8.2 WAIT MODE
r
P
e
Y
INTERRUPT
)
(s
WAIT mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register is forced to 0, to enable
all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting
address of the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to Figure 24.
Y
)
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u
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t
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l
o
N
ON
ON
OFF
CLEARED
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
r
P
e
ON
ON
ON
SET
IF RESET
514 CPU CLOCK
t
e
l
o
CYCLES DELAY
s
b
O
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is
popped.
30/139
Doc ID 6996 Rev 5
ST7262xxx
POWER SAVING MODES (Cont’d)
Figure 25. HALT Mode Flow Chart
8.3 HALT MODE
HALT INSTRUCTION
The HALT mode is the MCU lowest power consumption mode. The HALT mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the
on-chip peripherals.
When entering HALT mode, the I bit in the Condition Code Register is cleared. Thus, any of the external interrupts (ITi or USB end suspend mode),
are allowed and if an interrupt occurs, the CPU
clock becomes active.
The MCU can exit HALT mode on reception of either an external interrupt on ITi, an end suspend
mode interrupt coming from USB peripheral, or a
reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 514 CPU clock cycles.
After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
)
s
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u
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N
RESET
r
P
e
N
EXTERNAL
INTERRUPT*
t
e
l
o
)
(s
s
b
O
t
c
u
od
r
P
e
OFF
OFF
OFF
CLEARED
Y
Y
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
ON
ON
SET
514 CPU CLOCK
CYCLES DELAY
t
e
l
o
FETCH RESET VECTOR
s
b
O
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is
popped.
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ST7262xxx
9 I/O PORTS
9.1 INTRODUCTION
The I/O ports offer different functional modes:
transfer of data through digital inputs and outputs
and for specific pins:
– Analog signal input (ADC)
– Alternate signal input/output for the on-chip peripherals.
– External interrupt generation
An I/O port is composed of up to 8 pins. Each pin
can be programmed independently as digital input
or digital output.
9.2 FUNCTIONAL DESCRIPTION
Each port is associated with 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
Each I/O pin may be programmed using the corresponding register bits in DDR register: bit x corresponding to pin x of the port. The same correspondence is used for the DR register.
)
(s
Table 8. I/O Pin Functions
DDR
t
c
u
MODE
0
Input
d
o
r
1
Output
P
e
9.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Notes:
1. All the inputs are triggered by a Schmitt trigger.
2. When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port is
configured as an output.
Interrupt function
When an external interrupt function of an I/O pin, is
enabled using the ITFRE registers, an event on
this I/O can generate an external Interrupt request
to the CPU. The interrupt sensitivity is programma-
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ble, the options are given in the description of the
ITRFRE interrupt registers.
Each pin can independently generate an Interrupt
request.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as interrupt source, this is logically ANDed and inverted. For this reason, if an event occurs on one of the interrupt pins, it masks the other
ones.
9.2.2 Output Mode
The pin is configured in output mode by setting the
corresponding DDR register bit (see Table 7).
In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.
Note: In this mode, the interrupt function is disabled.
9.2.3 Alternate Functions
Digital Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically selected. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).
When the signal is going to an on-chip peripheral,
the I/O pin has to be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
Notes:
1. Input pull-up configuration can cause an unexpected value at the alternate peripheral input.
2. When the on-chip peripheral uses a pin as input
and output, this pin must be configured as an
input (DDR = 0).
Warning: Alternate functions of peripherals must
must not be activated when the external interrupts
are enabled on the same pin, in order to avoid
generating spurious interrupts.
)
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Doc ID 6996 Rev 5
ST7262xxx
I/O PORTS (Cont’d)
Analog Alternate Functions
When the pin is used as an ADC input, the I/O
must be configured as input. The analog multiplexer (controlled by the ADC registers) switches the
analog voltage present on the selected pin to the
common analog rail which is connected to the
ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected analog pin.
Warning: The analog input voltage level must be
within the limits stated in the Absolute Maximum
Ratings.
9.2.4 I/O Port Implementation
The hardware implementation on each I/O port depends on the settings in the DDR register and specific features of the I/O port such as ADC Input or
true open drain.
)
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(s
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P
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ST7262xxx
I/O PORTS (Cont’d)
9.2.5 Port A
Table 9. Port A Description
I/O
PORT A
Alternate Function
Input*
Output
Signal
Condition
USBOE
PA0
floating
push-pull
PA1
floating
push-pull
PA2
floating
push-pull
USBOE = 1 (MISC)
IT1 Schmitt triggered input
IT1E = 1 (ITRFRE1)
AIN0 (ADC)
CS[2:0] = 000 (ADCCSR)
IT2 Schmitt triggered input
IT2E = 1 (ITRFRE1)
AIN1 (ADC)
CS[2:0] = 001 (ADCCSR)
IT3 Schmitt triggered input
IT3E = 1 (ITRFRE1)
AIN2 (ADC)
CS[2:0] = 010 (ADCCSR)
IT4 Schmitt triggered input
IT4E = 1 (ITRFRE1)
AIN3 (ADC)
CS[2:0] = 011 (ADCCSR)
CS[2:0] = 100 (ADCCSR)
PA3
floating
push-pull
PA4
floating
push-pull
AIN4 (ADC)
PA5
floating
push-pull
AIN5 (ADC)
PA6
floating
push-pull
AIN6 (ADC)
PA7
floating
push-pull
AIN7 (ADC)
*Reset State
)
(s
u
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P
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t
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l
o
CS[2:0] = 101 (ADCCSR)
s
b
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c
u
Figure 26. PA[7:0] Configuration
)
s
(
ct
CS[2:0] = 110 (ADCCSR)
CS[2:0] = 111 (ADCCSR)
ALTERNATE ENABLE
od
ALTERNATE
OUTPUT
DR
LATCH
e
t
e
ol
Pr
1
VDD
0
P-BUFFER
ALTERNATE ENABLE
DDR
DATA BUS
COMMON ANALOG RAIL
s
b
O
PAD
LATCH
ANALOG ENABLE
(ADC)
DDR SEL
ANALOG
SWITCH
DIODES
N-BUFFER
DR SEL
1
ALTERNATE ENABLE
0
DIGITAL ENABLE
ALTERNATE INPUT
34/139
VDD
Doc ID 6996 Rev 5
VSS
ST7262xxx
I/O PORTS (Cont’d)
9.2.6 Port B
Table 10. Port B Description
I/O
Alternate Function
PORT B
Input*
Output
Signal
Condition
PB0
floating
push-pull (high sink)
MCO (Main Clock Output)
MCO = 1 (MISCR)
PB1
floating
push-pull (high sink)
RDI
SCI enabled
PB2
floating
push-pull (high sink)
TDO
TE = 1 (SCICR2)
PB3
floating
push-pull (high sink)
ARTCLK
EXCL = 1 (ARTCSR)
ARTIC1
ART Timer enabled
PB4
floating
push-pull (high sink)
IT5 Schmitt triggered input
IT5E = 1 (ITRFRE1)
floating
ART Timer enabled
push-pull (high sink)
IT6 Schmitt triggered input
let
PWM1
PB6
floating
push-pull (high sink)
so
IT7 Schmitt triggered input
b
O
PWM2
PB7
floating
push-pull (high sink)
)
(s
t
c
u
IT6E = 1 (ITRFRE1)
OE0 = 1 (PWMCR)
IT7E = 1 (ITRFRE1)
OE1 = 1 (PWMCR)
IT8 Schmitt triggered input
*Reset State
u
d
o
r
P
e
ARTIC2
PB5
)
s
(
ct
IT8E = 1 (ITRFRE1)
Figure 27. Port B and Port C [7:2] Configuration
od
ALTERNATE 1
OUTPUT
r
P
e
t
e
l
o
O
DATA BUS
bs
ALTERNATE ENABLE
VDD
0
P-BUFFER
VDD
DR
PULL-UP*
LATCH
ALTERNATE ENABLE
DDR
LATCH
PAD
DDR SEL
N-BUFFER
DR SEL
ALTERNATE INPUT
1
0
DIODES
ALTERNATE ENABLE
VSS
CMOS SCHMITT TRIGGER
* PULL-UP ON PORT C [7:2] ONLY
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ST7262xxx
I/O PORTS (Cont’d)
9.2.7 Port C
Table 11. Port C Description
I/O
Alternate Function
PORT C
Input*
Output
PC0
floating
true open drain
PC1
floating
true open drain
PC2
with pull-up
push-pull
PC3
with pull-up
push-pull
PC4
with pull-up
PC5
Signal
Condition
IT9 Schmitt triggered input
IT9E = 1 (ITRFRE2)
SCK
SPI enabled
IT10 Schmitt triggered input
IT10E = 1 (ITRFRE2)
SS
SPI enabled
push-pull
with pull-up
with pull-up
push-pull
PC7
with pull-up
push-pull
Figure 28. Port C[1:0] Configuration
r
P
e
IT11E = 1 (ITRFRE2)
MISO
SPI enabled
t
e
l
o
IT12 Schmitt triggered input
IT12E = 1 (ITRFRE2)
MOSI
SPI enabled
)
(s
*Reset State
u
d
o
IT11 Schmitt triggered input
push-pull
PC6
s
b
O
t
c
u
ALTERNATE ENABLE
ALTERNATE 1
OUTPUT
d
o
r
P
e
bs
O
DATA BUS
t
e
l
o
0
DR
LATCH
DDR
LATCH
PAD
DDR SEL
N-BUFFER
DR SEL
1
ALTERNATE ENABLE
VSS
0
CMOS SCHMITT TRIGGER
36/139
)
s
(
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Doc ID 6996 Rev 5
DIODES
ST7262xxx
I/O PORTS (Cont’d)
9.2.8 Port D
Table 12. Port D Description
I/O
Alternate Function
PORT D
Input*
Output
PD0
with pull-up
push-pull
PD1
with pull-up
push-pull
PD2
with pull-up
push-pull
PD3
with pull-up
push-pull
PD4
with pull-up
push-pull
PD5
with pull-up
push-pull
PD6
with pull-up
push-pull
Signal
Condition
)
s
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ct
u
d
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r
P
e
*Reset State
t
e
l
o
Figure 29. Port D Configuration
s
b
O
ALTERNATE ENABLE
ALTERNATE 1
OUTPUT
u
d
o
r
P
e
LATCH
VDD
s
(
t
c
0
DR
)-
P-BUFFER
PULL-UP
ALTERNATE ENABLE
DATA BUS
t
e
l
o
bs
VDD
DDR
PAD
LATCH
DDR SEL
O
N-BUFFER
DR SEL
1
DIODES
ALTERNATE ENABLE
VSS
0
ALTERNATE INPUT
CMOS SCHMITT TRIGGER
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ST7262xxx
I/O PORTS (Cont’d)
9.2.9 Register Description
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B, C or D.
Read/Write
Reset Value: 0000 0000 (00h)
DATA REGISTER (DR)
Port x Data Register
PxDR with x = A, B, C or D.
Read/Write
Reset Value: 0000 0000 (00h)
7
7
0
D7
D6
D5
D4
D3
D2
D1
DD7
0
DD6
DD4
DD3
DD2
DD1
DD0
)
s
(
ct
D0
Bits 7:0 = D[7:0] Data register 8 bits.
The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account
even if the pin is configured as an input; this allows
to always have the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
Bits 7:0 = DD[7:0] Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
)
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DD5
Doc ID 6996 Rev 5
ST7262xxx
I/O PORTS (Cont’d)
Table 13. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
Reset Value
of all I/O port registers
0000h
PADR
0001h
PADDR
0002h
PBDR
0003h
PBDDR
0004h
PCDR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
MSB
LSB
MSB
LSB
)
s
(
ct
u
d
o
MSB
0005h
PCDDR
0006h
PDDR
0007h
PDDDR
let
r
P
e
MSB
o
s
b
LSB
LSB
O
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ST7262xxx
9.3 MISCELLANEOUS REGISTER
MISCELLANEOUS REGISTER
Read Write
Reset Value - 0000 0000 (00h)
7
Bit 1 = USBOE USB Output Enable
0: PA0 port free for general purpose I/O
1: USBOE alternate function enabled. The USB
output enable signal is output on the PA0 port
(at “1” when the ST7 USB is transmitting data).
0
-
-
-
-
SMS1 SMS0
USBOE
MCO
Bit 0 = MCO Main Clock Out
0: PB0 port free for general purpose I/O
1: MCO alternate function enabled (fCPU output on
PB0 I/O port)
Bits 7:4 = Reserved
)
s
(
ct
Bits 3:2 = SMS[1:0] Slow Mode Selection
These bits select the Slow Mode frequency (depending on the oscillator frequency configured by
option byte).
Slow Mode Frequency
OSC12/6
SMS1 SMS0
(MHz.)
0
0
4
0
1
2
fOSC= 6 MHz.
1
0
1
1
1
0.5
0
0
8
0
1
4
fOSC= 12 MHz.
1
0
2
1
1
1
)
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ST7262xxx
10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG)
10.1.1 Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to
abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.
10.1.2 Main Features
■ Programmable free-running downcounter (64
increments of 65536 CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) when the T6 bit
reaches zero
■ Hardware Watchdog selectable by option byte
10.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 65,536 machine cycles, and the length of the timeout period can be
programmed by the user in 64 increments.
Figure 30. Watchdog Block Diagram
)
s
(
ct
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle by driving low the reset pin for 30µs.
The application program must write in the CR register at regular intervals during normal operation to
prevent an MCU reset. This downcounter is freerunning: it counts down even if the watchdog is diabled The value to be stored in the CR register
must be between FFh and C0h (see Table 14):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an immediate reset
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
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Table 14.Watchdog Timing (fCPU = 8 MHz)
bs
-O
Max
Min
CR Register
initial value
WDG timeout period
(ms)
FFh
524.288
C0h
8.192
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RESET
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fCPU
WDGA
WATCHDOG CONTROL REGISTER (CR)
T6
T5
T4
T3
T2
T1
T0
7-BIT DOWNCOUNTER
CLOCK DIVIDER
÷65536
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ST7262xxx
WATCHDOG TIMER (Cont’d)
10.1.4 Software Watchdog Option
If Software Watchdog is selected by option byte,
the watchdog is disabled following a reset. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).
10.1.5 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
10.1.6 Low Power Modes
WAIT Instruction
No effect on Watchdog.
HALT Instruction
Halt mode can be used when the watchdog is enabled. When the oscillator is stopped, the WDG
stops counting and is no longer able to generate a
reset until the microcontroller receives an external
interrupt or a reset.
If an external interrupt is received, the WDG restarts counting after 514 CPU clocks. In the case
of the Software Watchdog option, if a reset is generated, the WDG is disabled (reset state).
Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcontroller.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as Input before executing the HALT instruction.
The main reason for this is that the I/O may be
wrongly configured due to external interference
or by an unforeseen logical condition.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memory. For example, avoid defining a constant in
ROM with the value 0x8E.
– As the HALT instruction clears the I bit in the CC
register to allow interrupts, the user may choose
to clear all pending interrupt bits before executing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
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10.1.7 Interrupts
None.
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10.1.8 Register Desc4ription
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
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WDGA
T6
0
T5
T4
T3
T2
T1
T0
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
Table 15. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
0Dh
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Register
Label
WDGCR
Reset Value
7
6
5
4
3
2
1
0
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
Doc ID 6996 Rev 5
ST7262xxx
10.2 PWM AUTO-RELOAD TIMER (ART)
10.2.1 Introduction
The Pulse Width Modulated Auto-Reload Timer
on-chip peripheral consists of an 8-bit auto reload
counter with compare/capture capabilities and of a
7-bit prescaler clock source.
These resources allow five possible operating
modes:
– Generation of up to 2 independent PWM signals
– Output compare and Time base interrupt
– Up to two input capture functions
– External event detector
– Up to two external interrupt sources
The three first modes can be used together with a
single counter frequency.
The timer can be used to wake up the MCU from
WAIT and HALT modes.
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Figure 31. PWM Auto-Reload Timer Block Diagram
OEx
PWMCR
OCRx
REGISTER
OPx
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LOAD
PORT
ALTERNATE
FUNCTION
PWMx
POLARITY
CONTROL
COMPARE
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INPUT CAPTURE
CONTROL
ICSx
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ICIEx
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(s
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ARTICRx
REGISTER
LOAD
ICFx
ARTICCSR
ICx INTERRUPT
fEXT
ARTCLK
O
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LOAD
(ARTCAR REGISTER)
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ARTICx
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8-BIT COUNTER
ARTARR
REGISTER
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PWMDCRx
REGISTER
fCOUNTER
fCPU
MUX
fINPUT
EXCL
PROGRAMMABLE
PRESCALER
CC2
CC1
CC0
TCE
FCRL
OIE
OVF
ARTCSR
OVF INTERRUPT
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ST7262xxx
PWM AUTO-RELOAD TIMER (Cont’d)
10.2.2 Functional Description
Counter
The free running 8-bit counter is fed by the output
of the prescaler, and is incremented on every rising edge of the clock signal.
It is possible to read or write the contents of the
counter on the fly by reading or writing the Counter
Access register (ARTCAR).
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the
ARTARR register (the prescaler is not affected).
Counter clock and prescaler
The counter clock frequency is given by:
fCOUNTER = fINPUT / 2CC[2:0]
The timer counter’s input clock (fINPUT) feeds the
7-bit programmable prescaler, which selects one
of the 8 available taps of the prescaler, as defined
by CC[2:0] bits in the Control/Status Register
(ARTCSR). Thus the division factor of the prescaler can be set to 2n (where n = 0, 1,..7).
This fINPUT frequency source is selected through
the EXCL bit of the ARTCSR register and can be
either the fCPU or an external input frequency fEXT.
The clock input to the counter is enabled by the
TCE (Timer Counter Enable) bit in the ARTCSR
register. When TCE is reset, the counter is
stopped and the prescaler and counter contents
are frozen. When TCE is set, the counter runs at
the rate of the selected clock source.
Counter and Prescaler Initialization
After RESET, the counter and the prescaler are
cleared and fINPUT = fCPU.
The counter can be initialized by:
– Writing to the ARTARR register and then setting
the FCRL (Force Counter Re-Load) and the TCE
(Timer Counter Enable) bits in the ARTCSR register.
– Writing to the ARTCAR counter access register,
In both cases the 7-bit prescaler is also cleared,
whereupon counting will start from a known value.
Direct access to the prescaler is not possible.
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Output compare control
The timer compare function is based on four different comparisons with the counter (one for each
PWMx output). Each comparison is made between the counter value and an output compare
register (OCRx) value. This OCRx register can not
be accessed directly, it is loaded from the duty cycle register (PWMDCRx) at each overflow of the
counter.
This double buffering method avoids glitch generation when changing the duty cycle on the fly.
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Figure 32. Output compare control
fCOUNTER
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COUNTER
FDh
ARTARR=FDh
FEh
FFh
OCRx
PWMDCRx
FDh
FEh
FFh
FEh
FEh
FDh
FEh
FDh
PWMx
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FDh
Doc ID 6996 Rev 5
FFh
ST7262xxx
PWM AUTO-RELOAD TIMER (Cont’d)
Independent PWM signal generation
This mode allows up to two Pulse Width Modulated signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during HALT mode.
Each PWMx output signal can be selected independently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as output push-pull alternate function.
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARTARR register value.
fPWM = fCOUNTER / (256 - ARTARR)
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
OPx (output polarity) bit in the PWMCR register.
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARTARR register.
The maximum available resolution for the PWMx
duty cycle is:
Resolution = 1 / (256 - ARTARR)
Note: To get the maximum resolution (1/256), the
ARTARR register must be 0. With this maximum
resolution, 0% and 100% can be obtained by
changing the polarity.
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Figure 33. PWM Auto-reload Timer Function
COUNTER
255
DUTY CYCLE
REGISTER
(PWMDCRx)
)
(s
AUTO-RELOAD
REGISTER
(ARTARR)
PWMx OUTPUT
000
WITH OEx=1
AND OPx=1
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WITH OEx=1
AND OPx=0
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ST7262xxx
Figure 34. PWM Signal from 0% to 100% Duty Cycle
fCOUNTER
ARTARR=FDh
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
FEh
PWMx OUTPUT
WITH OEx=1
AND OPx=0
OCRx=FCh
OCRx=FDh
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OCRx=FEh
OCRx=FFh
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ST7262xxx
PWM AUTO-RELOAD TIMER (Cont’d)
Output compare and Time base interrupt
On overflow, the OVF flag of the ARTCSR register
is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the
ARTCSR register, is set. The OVF flag must be reset by the user software. This interrupt can be
used as a time base in the application.
External clock and event detector mode
Using the fEXT external prescaler input clock, the
auto-reload timer can be used as an external clock
event detector. In this mode, the ARTARR register
is used to select the nEVENT number of events to
be counted before setting the OVF flag.
nEVENT = 256 - ARTARR
When entering HALT mode while fEXT is selected,
all the timer control registers are frozen but the
counter continues to increment. If the OIE bit is
set, the next overflow of the counter will generate
an interrupt which wakes up the MCU.
Caution: If HALT mode is used in the application,
prior to executing the HALT instruction, the counter must be disabled by clearing the TCE bit in the
ARTCSR register to avoid spurious counter increments.
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Figure 35. External Event Detector Example (3 counts)
fEXT=fCOUNTER
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ARTARR=FDh
COUNTER
FDh
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OVF
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FEh
FFh
FDh
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FEh
FFh
FDh
ARTCSR READ
ARTCSR READ
INTERRUPT
IF OIE=1
bs
INTERRUPT
IF OIE=1
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ST7262xxx
PWM AUTO-RELOAD TIMER (Cont’d)
Input capture function
This mode allows the measurement of external
signal pulse widths through ICRx registers.
Each input capture can generate an interrupt independently on a selected input signal transition.
This event is flagged by a set of the corresponding
CFx bits of the Input Capture Control/Status register (ICCSR).
These input capture interrupts are enabled
through the CIEx bits of the ICCSR register.
The active transition (falling or rising edge) is software programmable through the CSx bits of the
ICCSR register.
The read only input capture registers (ICRx) are
used to latch the auto-reload counter value when a
transition is detected on the ARTICx pin (CFx bit
set in ICCSR register). After fetching the interrupt
vector, the CFx flags can be read to identify the interrupt source.
Note: After a capture detection, data transfer in
the ICRx register is inhibited until the ARTICCSR
register is read (clearing the CFx bit).
The timer interrupt remains pending while the CFx
flag is set when the interrupt is enabled (CIEx bit
set). This means, the ARTICCSR register has to
be read at each capture event to clear the CFx
flag.
During HALT mode, input capture is inhibited (the
ICRx is never re-loaded) and only the external interrupt capability can be used.
External interrupt capability
This mode allows the Input capture capabilities to
be used as external interrupt sources.
The edge sensitivity of the external interrupts is
programmable (CSx bit of ICCSR register) and
they are independently enabled through CIEx bits
of the ICCSR register. After fetching the interrupt
vector, the CFx flags can be read to identify the interrupt source.
The interrupts are synchronized on the counter
clock rising edge (Figure 36).
During HALT mode, the external interrupts can still
be used to wake up the micro (if CIEx bit is set).
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Figure 36. ART External Interrupt
s
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fCOUNTER
)
(s
ARTICx PIN
t
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INTERRUPT
CFx FLAG
od
The timing resolution is given by auto-reload counter cycle time (1/fCOUNTER).
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Figure 37. Input Capture Timing Diagram
s
b
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fCOUNTER
COUNTER
01h
02h
03h
04h
05h
06h
07h
INTERRUPT
ARTICx PIN
CFx FLAG
xxh
04h
ICRx REGISTER
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Doc ID 6996 Rev 5
ST7262xxx
PWM AUTO-RELOAD TIMER (Cont’d)
10.2.3 Register Description
COUNTER ACCESS REGISTER (CAR)
Read/Write
Reset Value: 0000 0000 (00h)
CONTROL / STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
EXCL
CC2
CC1
CC0
TCE
FCRL
OIE
0
7
OVF
CA7
8 MHz
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
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CA3
CA2
CA1
CA0
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AUTO-RELOAD REGISTER (ARR)
Read/Write
Reset Value: 0000 0000 (00h)
)-
AR7
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CA4
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7
Bit 3 = TCE Timer Counter Enable
This bit is set and cleared by software. It puts the
timer in the lowest power consumption mode.
0: Counter stopped (prescaler and counter frozen).
1: Counter running.
Bit 2 = FCRL Force Counter Re-Load
This bit is write-only and any attempt to read it will
yield a logical zero. When set, it causes the contents
of ARR register to be loaded into the counter, and
the content of the prescaler register to be cleared in
order to initialize the timer before starting to count.
Bit 1 = OIE Overflow Interrupt Enable
This bit is set and cleared by software. It allows to
enable/disable the interrupt which is generated
when the OVF bit is set.
0: Overflow Interrupt disable.
1: Overflow Interrupt enable.
Bit 0 = OVF Overflow Flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates the transition
of the counter from FFh to the ARR value.
0: New transition not yet reached
1: Transition reached
CA5
Bit 7:0 = CA[7:0] Counter Access Data
These bits can be set and cleared either by hardware or by software. The CAR register is used to
read or write the auto-reload counter “on the fly”
(while it is counting).
With fINPUT=8 MHz CC2 CC1 CC0
fINPUT
fINPUT / 2
fINPUT / 4
fINPUT / 8
fINPUT / 16
fINPUT / 32
fINPUT / 64
fINPUT / 128
CA6
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Bit 7 = EXCL External Clock
This bit is set and cleared by software. It selects the
input clock for the 7-bit prescaler.
0: CPU clock.
1: External clock.
Bit 6:4 = CC[2:0] Counter Clock Control
These bits are set and cleared by software. They
determine the prescaler division ratio from fINPUT.
fCOUNTER
0
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AR6
0
AR5
AR4
AR3
AR2
AR1
AR0
Bit 7:0 = AR[7:0] Counter Auto-Reload Data
These bits are set and cleared by software. They
are used to hold the auto-reload value which is automatically loaded in the counter when an overflow
occurs. At the same time, the PWM output levels
are changed according to the corresponding OPx
bit in the PWMCR register.
This register has two PWM management functions:
– Adjusting the PWM frequency
– Setting the PWM duty cycle resolution
PWM Frequency vs. Resolution:
ARR value
0
[ 0..127 ]
[ 128..191 ]
[ 192..223 ]
[ 224..239 ]
Doc ID 6996 Rev 5
fPWM
Resolution
8-bit
> 7-bit
> 6-bit
> 5-bit
> 4-bit
Min
Max
~0.244-KHz
~0.244-KHz
~0.488-KHz
~0.977-KHz
~1.953-KHz
31.25-KHz
62.5-KHz
125-KHz
250-KHz
500-KHz
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ST7262xxx
PWM AUTO-RELOAD TIMER (Cont’d)
PWM CONTROL REGISTER (PWMCR)
Read/Write
Reset Value: 0000 0000 (00h)
7
DUTY CYCLE REGISTERS (DCRx)
Read/Write
Reset Value: 0000 0000 (00h)
0
0
0
OE1
OE0
0
0
OP1
7
OP0
DC7
Bit 7:6 = Reserved.
Bit 5:4 = OE[1:0] PWM Output Enable
These bits are set and cleared by software. They
enable or disable the PWM output channels independently acting on the corresponding I/O pin.
0: PWM output disabled.
1: PWM output enabled.
Bit 3:2 = Reserved.
Bit 1:0 = OP[1:0] PWM Output Polarity
These bits are set and cleared by software. They
independently select the polarity of the two PWM
output signals.
OPx
Counter OCRx
1
0
0
1
DC6
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DC2
DC1
DC0
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Notes:
– When an OPx bit is modified, the PWMx output
signal polarity is immediately reversed.
– If DCRx=FFh then the output level is always 0.
– If DCRx=00h then the output level is always 1.
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DC4
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DC5
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
A DCRx register is associated with the OCRx register of each PWM channel to determine the second edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARR register). These DCR registers allow
the duty cycle to be set independently for each
PWM channel.
)
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PWMx output level
0
Doc ID 6996 Rev 5
ST7262xxx
PWM AUTO-RELOAD TIMER (Cont’d)
INPUT CAPTURE
CONTROL / STATUS REGISTER (ARTICCSR)
Read/Write (except bits 1:0 read and clear)
Reset Value: 0000 0000 (00h)
INPUT CAPTURE REGISTERS (ARTICRx)
Read only
Reset Value: 0000 0000 (00h)
7
7
IC7
0
0
0
0
CS2
CS1
CIE2
CIE1
CF2
IC6
IC5
IC4
IC3
IC2
IC1
IC0
CF1
Bit 7:6 = Reserved, always read as 0.
Bit 5:4 = CS[2:1] Capture Sensitivity
These bits are set and cleared by software. They
determine the trigger event polarity on the corresponding input capture channel.
0: Falling edge triggers capture on channel x.
1: Rising edge triggers capture on channel x.
Bit 3:2 = CIE[2:1] Capture Interrupt Enable
These bits are set and cleared by software. They
enable or disable the Input capture channel interrupts independently.
0: Input capture channel x interrupt disabled.
1: Input capture channel x interrupt enabled.
Bit 7:0 = IC[7:0] Input Capture Data
These read only bits are set and cleared by hardware. An ARTICRx register contains the 8-bit
auto-reload counter value transferred by the input
capture channel x event.
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Bit 1:0 = CF[2:1] Capture Flag
These bits are set by hardware when a capture occurs and cleared by hardware when software
reads the ARTICCSR register. Each CFx bit indicates that an input capture x has occurred.
0: No input capture on channel x.
1: An input capture has occurred on channel x.
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ST7262xxx
PWM AUTO-RELOAD TIMER (Cont’d)
Table 16. PWM Auto-Reload Timer Register Map and Reset Values
Address
(Hex.)
0014h
Register
Label
PWMDCR1
Reset Value
PWMDCR0
Reset Value
PWMCR
Reset Value
ARTCSR
Reset Value
ARTCAR
Reset Value
ARTARR
Reset Value
ARTICCSR
Reset Value
ARTICR1
Reset Value
ARTICR2
Reset Value
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
7
6
5
4
3
2
1
0
DC7
0
DC7
0
0
0
EXCL
0
CA7
0
AR7
0
DC6
0
DC6
0
0
0
CC2
0
CA6
0
AR6
0
0
IC7
0
IC7
0
0
IC6
0
IC6
0
DC5
0
DC5
0
OE1
0
CC1
0
CA5
0
AR5
0
CS2
0
IC5
0
IC5
0
DC4
0
DC4
0
OE0
0
CC0
0
CA4
0
AR4
0
CS1
0
IC4
0
IC4
0
DC3
0
DC3
0
0
0
TCE
0
CA3
0
AR3
0
CIE2
0
IC3
0
IC3
0
DC2
0
DC2
0
0
0
FCRL
0
CA2
0
AR2
0
CIE1
0
IC2
0
IC2
0
DC1
0
DC1
0
OP1
0
OIE
0
CA1
0
AR1
0
CF2
0
IC1
0
IC1
0
DC0
0
DC0
0
OP0
0
OVF
0
CA0
0
AR0
0
CF1
0
IC0
0
IC0
0
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ST7262xxx
10.3 TIMEBASE UNIT (TBU)
10.3.1 Introduction
The Timebase unit (TBU) can be used to generate
periodic interrupts.
10.3.2 Main Features
■ 8-bit upcounter
■ Programmable prescaler
■ Period between interrupts: max. 8.1ms (at 8
MHz fCPU )
■ Maskable interrupt
■ Cascadable with PWM/ART TImer
10.3.3 Functional Description
The TBU operates as a free-running upcounter.
When the TCEN bit in the TBUCSR register is set
by software, counting starts at the current value of
the TBUCV register. The TBUCV register is incremented at the clock rate output from the prescaler
selected by programming the PR[2:0] bits in the
TBUCSR register.
When the counter rolls over from FFh to 00h, the
OVF bit is set and an interrupt request is generated if ITE is set.
The user can write a value at any time in the
TBUCV register.
If the cascading option is selected (CAS bit=1 in
the TBUCSR register), the TBU and the ART TImer counters act together as a 16-bit counter. In this
case, the TBUCV register is the high order byte,
the ART counter (ARTCAR register) is the low order byte. Counting is clocked by the ART timer
clock (Refer to the description of the ART Timer
ARTCSR register).
10.3.4 Programming Example
In this example, timer is required to generate an interrupt after a delay of 1 ms.
Assuming that fCPU is 8 MHz and a prescaler division factor of 256 will be programmed using the
PR[2:0] bits in the TBUCSR register, 1 ms = 32
TBU timer ticks.
In this case, the initial value to be loaded in the
TBUCV must be (256-32) = 224 (E0h).
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A, E0h
TBUCV, A ; Initialize counter value
A 1Fh
;
TBUCSR, A ; Prescaler factor = 256,
; interrupt enable,
; TBU enable
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Figure 38. TBU Block Diagram
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ART TIMER CARRY BIT
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P
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MSB
0
LSB
let
TBU 8-BIT UPCOUNTER (TBUCV REGISTER)
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MSB
LSB
ART PWM TIMER 8-BIT COUNTER
TBU PRESCALER
O
fCPU
0
CAS OVF
ITE TCEN PR2 PR1 PR0
TBUCSR REGISTER
TBU
INTERRUPT REQUEST
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ST7262xxx
TIMEBASE UNIT (Cont’d)
10.3.5 Low Power Modes
Mode
WAIT
HALT
Bit 6 = CAS Cascading Enable
This bit is set and cleared by software. It is used to
cascade the TBU and the PWM/ART timers.
0: Cascading disabled
1: Cascading enabled
Description
No effect on TBU
TBU halted.
10.3.6 Interrupts
Interrupt
Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Counter Overflow Event
OVF
ITE
Yes
No
Bit 5 = OVF Overflow Flag
This bit is set only by hardware, when the counter
value rolls over from FFh to 00h. It is cleared by
software reading the TBUCSR register. Writing to
this bit does not change the bit value.
0: No overflow
1: Counter overflow
Note: The OVF interrupt event is connected to an
interrupt vector (see Interrupts chapter).
It generates an interrupt if the ITE bit is set in the
TBUCSR register and the I-bit in the CC register is
reset (RIM instruction).
10.3.7 Register Description
TBU COUNTER VALUE REGISTER (TBUCV)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
CV7
CV6
CV5
CV4
CV3
CV2
CV1
Pr
TBU CONTROL/STATUS REGISTER (TBUCSR)
Read/Write
Reset Value: 0000 0000 (00h)
O
7
0
0
CAS OVF
ITE TCEN
PR2
PR1
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Bit 2:0 = PR[2:0] Prescaler Selection
These bits are set and cleared by software to select the prescaling factor.
CV0
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Bit 7:0 = CV[7:0] Counter Value
This register contains the 8-bit counter value
which can be read and written anytime by software. It is continuously incremented by hardware if
TCEN=1.
ete
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Bit 4 = ITE Interrupt enabled.
This bit is set and cleared by software.
0: Overflow interrupt disabled
1: Overflow interrupt enabled. An interrupt request
is generated when OVF=1.
Bit 3 = TCEN TBU Enable.
This bit is set and cleared by software.
0: TBU counter is frozen and the prescaler is reset.
1: TBU counter and prescaler running.
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PR2 PR1 PR0
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
256
PR0
Bit 7 = Reserved. Forced by hardware to 0.
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Prescaler Division Factor
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ST7262xxx
TIMEBASE UNIT (Cont’d)
Table 17. TBU Register Map and Reset Values
Address
Register
Label
7
6
5
4
3
2
1
0
0036h
TBUCV
Reset Value
CV7
0
CV6
0
CV5
0
CV4
0
CV3
0
CV2
0
CV1
0
CV0
0
0037h
TBUSR
Reset Value
0
CAS
0
OVF
0
ITE
0
TCEN
0
PR2
0
PR1
0
PR0
0
(Hex.)
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ST7262xxx
10.4 SERIAL PERIPHERAL INTERFACE (SPI)
10.4.1 Introduction
The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multimaster system.
10.4.2 Main Features
■ Full duplex synchronous transfers (on 3 lines)
■ Simplex synchronous transfers (on 2 lines)
■ Master or slave operation
■ Six master mode frequencies (fCPU/4 max.)
■ fCPU/2 max. slave mode frequency (see note)
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision, Master Mode Fault and Overrun
flags
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
10.4.3 General Description
Figure 39 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
The SPI is connected to external devices through
3 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and input by SPI slaves
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves individually and to avoid contention on the data
lines. Slave SS inputs can be driven by standard I/O ports on the master MCU.
Figure 39. Serial Peripheral Interface Block Diagram
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Data/Address Bus
Read
SPIDR
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Read Buffer
MOSI
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8-Bit Shift Register
Interrupt
request
SPICSR
7
SPIF WCOL OVR MODF
SOD SSM
SSI
Write
SS
SPI
STATE
CONTROL
SCK
7
SPIE
1
0
SPICR
0
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 40.
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
the MISO pin. This implies full duplex communication with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see Figure 43) but master and slave
must be programmed with the same timing mode.
)
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Figure 40. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
8-BIT SHIFT REGISTER
MSBit
SPI
CLOCK
GENERATOR
MISO
MISO
MOSI
MOSI
)-
SCK
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SS
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LSBit
8-BIT SHIFT REGISTER
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SCK
SS
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Not used if SS is managed
by software
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR register (see Figure 42)
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
– SS internal must be held high continuously
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see Figure 41):
If CPHA=1 (data latched on 2nd clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
VSS, or made free for standard I/O by managing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 10.4.5.3).
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Figure 41. Generic SS Timing Diagram
MOSI/MISO
Byte 1
Master SS
)
(s
Slave SS
(if CPHA=0)
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Slave SS
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Figure 42. Hardware/Software Slave Select Management
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Byte 2
SSM bit
SSI bit
1
SS external pin
0
SS internal
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ST7262xxx
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.3.3 Master Mode Operation
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
To operate the SPI in master mode, perform
the following two steps in order (if the SPICSR
register is not written first, the SPICR register
setting (MSTR bit) may be not taken into account):
1. Write to the SPICR register:
– Select the clock frequency by configuring the
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
43 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICSR register:
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when software
writes a byte in the SPIDR register.
10.4.3.4 Master Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CC register is cleared.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
10.4.3.5 Slave Mode Operation
In slave mode, the serial clock is received on the
SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the following actions:
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 43).
Note: The slave must have the same CPOL
and CPHA settings as the master.
– Manage the SS pin as described in Section
10.4.3.2 and Figure 41. If CPHA=1 SS must
be held low continuously. If CPHA=0 SS must
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
10.4.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CC register is
cleared.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPICSR register while the
SPIF bit is set.
2. A write or a read to the SPIDR register.
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 10.4.5.2).
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.4 Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 43).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 43, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by resetting the SPE bit.
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Figure 43. Data Clock Timing Diagram
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CPHA =1
SCK
(CPOL = 1)
r
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SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSBit
Bit 6
Bit 5
Bit 4
MSBit
Bit 6
Bit 5
Bit 4
Bit3
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Bit 2
Bit 1
LSBit
Bit 2
Bit 1
LSBit
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SS
(to slave)
CAPTURE STROBE
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CPHA =0
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SCK
(CPOL = 1)
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SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.5 Error Flags
10.4.5.1 Master Mode Fault (MODF)
Master mode fault occurs when the master device
has its SS pin pulled low.
When a Master mode fault occurs:
– The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI peripheral.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
1. A read access to the SPICSR register while the
MODF bit is set.
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
In a slave device, the MODF bit can not be set, but
in a multimaster configuration the device can be in
slave mode with the MODF bit set.
The MODF bit indicates that there might have
been a multimaster conflict and allows software to
handle this using an interrupt routine and either
perform to a reset or return to an application default state.
10.4.5.2 Overrun Condition (OVR)
An overrun condition occurs, when the master device has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
When an Overrun occurs:
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
The OVR bit is cleared by reading the SPICSR
register.
10.4.5.3 Write Collision Error (WCOL)
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode. See also Section 10.4.3.2 Slave Select
Management.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU operation.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 44).
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Figure 44. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
Read SPICSR
RESULT
2nd Step
Read SPIDR
SPIF =0
WCOL=0
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
Read SPICSR
RESULT
2nd Step
Read SPIDR
WCOL=0
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ST7262xxx
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.5.4 Single Master System
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 45).
The master device selects the individual slave devices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR
register.
Other transmission security methods can use
ports for handshake lines or data bytes with command fields.
)
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Figure 45. Single Master / Multiple Slave Configuration
SS
SCK
Slave
MCU
MOSI MISO
MOSI MISO
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MOSI MISO
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MOSI MISO
5V
SCK
Slave
MCU
Slave
MCU
SCK
Master
MCU
SS
SS
SCK
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SCK
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MOSI MISO
ST7262xxx
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.6 Low Power Modes
Mode
WAIT
HALT
Description
No effect on SPI.
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by
an interrupt with “exit from HALT mode” capability. The data received is subsequently
read from the SPIDR register when the software is running (interrupt vector fetching). If
several data are received before the wakeup event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the device.
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to perform an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake up the ST7 from Halt
mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low
when the ST7 enters Halt mode. So if Slave selection is configured as external (see Section
10.4.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
10.4.7 Interrupts
Interrupt Event
10.4.6.1 Using the SPI to wakeup the MCU from
Halt mode
In slave configuration, the SPI is able to wakeup
the ST7 device from HALT mode through a SPIF
interrupt. The data received is subsequently read
from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears
the SPIF bit, then the OVR bit is set by hardware.
SPI End of Transfer
Event
Master Mode Fault
Event
Overrun Error
Event
Flag
Enable
Control
Bit
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SPIF
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MODF
OVR
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SPIE
Exit
from
Wait
Exit
from
Halt
Yes
Yes
Yes
No
Yes
No
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Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
7
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.4.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
0
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
)
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Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
SPIF=1, MODF=1 or OVR=1 in the SPICSR
register
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by resetting the SPE bit.
u
d
o
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.4.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
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Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 18 SPI Master
mode SCK Frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
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Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
Note: These 2 bits have no effect in slave mode.
Table 18. SPI Master mode SCK Frequency
SPR2
SPR1
SPR0
Serial Clock
(fCPU = 8MHz)
Serial Clock
(fCPU= 4MHz)
SCK
1
0
0
fCPU/4
fCPU/2
2 MHz
0
0
0
fCPU/8
fCPU/4
1 MHz
0
0
1
fCPU/16
fCPU/8
0.5 MHz
1
1
0
fCPU/32
fCPU/16
0.25 MHz
0
1
0
fCPU/64
fCPU/32
125 kHz
0
1
1
fCPU/128
fCPU/64
62.5 kHz
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SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
7
0
SPIF
WCOL
OVR
MODF
-
SOD
SSM
SSI
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an external device has been completed.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the
SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see
Figure 44).
0: No write collision occurred
1: A write collision has been detected
Bit 2 = SOD SPI Output Disable.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
1: SPI output disabled
Bit 1 = SSM SS Management.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
10.4.3.2 Slave Select Management.
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O)
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Bit 0 = SSI SS Internal Mode.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0 : Slave selected
1 : Slave deselected
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Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 10.4.5.2). An interrupt is generated if
SPIE = 1 in SPICR register. The OVR bit is cleared
by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
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Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 10.4.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE=1 in the SPICR register. This
bit is cleared by a software sequence (An access
to the SPICSR register while MODF=1 followed by
a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
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DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
D7
0
D6
D5
D4
D3
D2
D1
D0
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of the shift
register (see Figure 39).
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Table 19. SPI Register Map and Reset Values
Address
Register
Label
7
6
5
4
3
2
1
0
0011h
SPIDR
Reset Value
MSB
x
x
x
x
x
x
x
LSB
x
0012h
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
0013h
SPICSR
Reset Value
SPIF
0
WCOL
0
OVR
0
MODF
0
0
SOD
0
SSM
0
SSI
0
(Hex.)
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10.5 SERIAL COMMUNICATIONS INTERFACE (SCI)
10.5.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two
baud rate generator systems.
10.5.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
■ Independently
programmable transmit and
receive baud rates up to 500K baud
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ Two receiver wake-up modes:
– Address bit (MSB)
– Idle line
■ Muting function for multiprocessor configurations
■ Separate enable bits for Transmitter and
Receiver
■ Four error detection flags:
– Overrun error
– Noise error
– Frame error
– Parity error
■ Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
10.5.3 General Description
The interface is externally connected to another
device by two pins (see Figure 47):
– TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin
returns to its I/O port configuration. When the
transmitter and/or the receiver are enabled and
nothing is to be transmitted, the TDO pin is at
high level.
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data recovery by discriminating between valid incoming
data and noise.
Through these pins, serial data is transmitted and
received as frames comprising:
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete
This interface uses two types of baud rate generator:
– A conventional type for commonly-used baud
rates
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 46. SCI Block Diagram
Write
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Transmit Data Register (TDR)
TDO
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Received Shift Register
Transmit Shift Register
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R8
TRANSMIT
WAKE
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CONTROL
UNIT
TIE TCIE RIE
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SCID
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M WAKE PCE PS
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RECEIVER
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SR
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TRANSMITTER RATE
fCPU
CONTROL
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/PR
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4 Functional Description
The block diagram of the Serial Control Interface,
is shown in Figure 46 It contains six dedicated registers:
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
– A baud rate register (SCIBRR)
– An extended prescaler receiver register (SCIERPR)
– An extended prescaler transmitter register (SCIETPR)
Refer to the register descriptions in Section
10.5.7for the definitions of each bit.
10.5.4.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 register (see Figure 46).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
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Figure 47. Word Length Programming
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9-bit Word length (M bit is set)
Possible
Parity
Bit
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Data Frame
Start
Bit
Bit2
Bit1
Bit0
Bit3
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Bit5
Bit4
Bit6
Bit7
Bit8
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Start
Bit
Bit0
Possible
Parity
Bit
Data Frame
Bit1
Bit2
Bit3
Bit4
Bit5
Next
Stop Start
Bit
Bit
Start
Bit
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Break Frame
Next Data Frame
Bit6
Bit7
Next Data Frame
Stop
Bit
Next
Start
Bit
Idle Frame
Start
Bit
Break Frame
Extra Start
Bit
‘1’
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.2 Transmitter
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 46).
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the SCIBRR
and the SCIETPR registers.
– Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first
transmission.
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR register without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CC register.
When a transmission is taking place, a write instruction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
When a frame transmission is complete (after the
stop bit) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the
CC register.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 47).
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
Idle Characters
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the current word.
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set, that is, before writing the next byte in the
SCIDR.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.3 Receiver
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 46).
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CC register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during reception.
Clearing the RDRF bit is performed by the following
software sequence done by:
1. An access to the SCISR register
2. A read to the SCIDR register.
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
Break Character
When a break character is received, the SCI handles it as a framing error.
Idle Character
When a idle frame is detected, there is the same
procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in
the CC register.
Overrun Error
An overrun error occurs when a character is received when RDRF has not been reset. Data can
not be transferred from the shift register to the
RDR register as long as the RDRF bit is not
cleared.
When an overrun error occurs:
– The OR bit is set.
– The RDR content is not lost.
– The shift register is overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CC register.
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation.
Noise Error
Oversampling techniques are used for data recovery by discriminating between valid incoming data
and noise. Normal data bits are considered valid if
three consecutive samples (8th, 9th, 10th) have
the same bit value, otherwise the NF flag is set. In
the case of start bit detection, the NF flag is set on
the basis of an algorithm combining both valid
edge detection and three samples (8th, 9th, 10th).
Therefore, to prevent the NF flag getting set during
start bit reception, there should be a valid edge detection as well as three valid samples.
When noise is detected in a frame:
– The NF flag is set at the rising edge of the RDRF
bit.
– Data is transferred from the Shift register to the
SCIDR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation.
During reception, if a false start bit is detected (e.g.
8th, 9th, 10th samples are 011,101,110), the
frame is discarded and the receiving sequence is
not started for this frame. There is no RDRF bit set
for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible
along with the RDRF bit when a next valid frame is
received.
Note: If the application Start Bit is not long enough
to match the above requirements, then the NF
Flag may get set due to the short Start Bit. In this
case, the NF flag may be ignored by the application software when the first valid byte is received.
See also Section 10.5.4.10.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 48. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
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SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
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SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
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CONVENTIONAL BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Framing Error
A framing error is detected when:
– The stop bit is not recognized on reception at the
expected time, following either a de-synchronization or excessive noise.
– A break is received.
When the framing error is detected:
– the FE bit is set by hardware
– Data is transferred from the Shift register to the
SCIDR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation.
10.5.4.4 Conventional Baud Rate Generation
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
Tx =
fCPU
Rx =
fCPU
(16*PR)*RR
(16*PR)*TR
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Rx =
Tx =
16*ERPR*(PR*RR)
16*ETPR*(PR*TR)
with:
ETPR = 1,..,255 (see SCIETPR register)
ERPR = 1,.. 255 (see SCIERPR register)
10.5.4.6 Receiver Muting and Wake-up Feature
In multiprocessor configurations it is often desirable that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
The non addressed devices may be placed in
sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in
sleep mode:
All the reception status bits can not be set.
All the receive interrupts are inhibited.
A muted receiver may be awakened by one of the
following two ways:
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Receiver wakes-up by Idle Line detection when
the Receive line has recognized an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an address. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
CAUTION: In Mute mode, do not write to the
SCICR2 register. If the SCI is in Mute mode during
the read operation (RWU = 1) and a address mark
wake up event occurs (RWU is reset) before the
write operation, the RWU bit is set again by this
write operation. Consequently the address byte is
lost and the SCI is not woken up from Mute mode.
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with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If fCPU is 8 MHz (normal mode) and if
PR = 13 and TR = RR = 1, the transmit and receive baud rates are 38400 baud.
Note: The baud rate registers MUST NOT be
changed while the transmitter or the receiver is enabled.
10.5.4.5 Extended Baud Rate Generation
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescaler, whereas the conventional Baud Rate Generator retains industry standard software compatibility.
The extended baud rate generator block diagram
is described in the Figure 48
The output clock rate sent to the transmitter or to
the receiver is the output from the 16 divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR register.
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Note: the extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
follows:
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.7 Parity Control
Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register.
Depending on the frame length defined by the M
bit, the possible SCI frame formats are as listed in
Table 20.
Table 20. Frame Formats
M bit
0
0
1
1
PCE bit
0
1
0
1
SCI frame
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Note: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
Even parity: the parity bit is calculated to obtain
an even number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit
is 0 if even parity is selected (PS bit = 0).
Odd parity: the parity bit is calculated to obtain an
odd number of “1s” inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to
0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit
is 1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the interface checks if the received data byte has an
even number of “1s” if even parity is selected
(PS = 0) or an odd number of “1s” if odd parity is
selected (PS = 1). If the parity check fails, the PE
flag is set in the SCISR register and an interrupt is
generated if PIE is set in the SCICR1 register.
10.5.4.8 SCI Clock Tolerance
During reception, each bit is sampled 16 times.
The majority of the 8th, 9th and 10th samples is
considered as the bit value. For a valid bit detection, all the three samples should have the same
value otherwise the noise flag (NF) is set. For example: If the 8th, 9th and 10th samples are 0, 1
and 1 respectively, then the bit value is “1”, but the
Noise Flag bit is set because the three samples
values are not the same.
Consequently, the bit length must be long enough
so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency
should not vary more than 6/16 (37.5%) within one
bit. The sampling clock is resynchronized at each
start bit, so that when receiving 10 bits (one start
bit, 1 data byte, 1 stop bit), the clock deviation
must not exceed 3.75%.
Note: The internal sampling clock of the microcontroller samples the pin value on every falling edge.
Therefore, the internal sampling clock and the time
the application expects the sampling to take place
may be out of sync. For example: If the baud rate
is 15.625 Kbaud (bit length is 64µs), then the 8th,
9th and 10th samples are at 28µs, 32µs and 36µs
respectively (the first sample starting ideally at
0µs). But if the falling edge of the internal clock occurs just before the pin value changes, the samples would then be out of sync by ~4us. This
means the entire bit length must be at least 40µs
(36µs for the 10th sample + 4µs for synchronization with the internal sampling clock).
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ST7262xxx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.9 Clock Deviation Causes
The causes which contribute to the total deviation
are:
– DTRA: Deviation due to transmitter error (Local
oscillator error of the transmitter or the transmitter is transmitting at a different baud rate).
– DQUANT: Error due to the baud rate quantization of the receiver.
– DREC: Deviation of the local oscillator of the
receiver: This deviation can occur during the
reception of one complete SCI message assuming that the deviation has been compensated at the beginning of the message.
– DTCL: Deviation due to the transmission line
(generally due to the transceivers)
All the deviations of the system should be added
and compared to the SCI clock tolerance:
DTRA + DQUANT + DREC + DTCL < 3.75%
10.5.4.10 Noise Error Causes
See also description of Noise error in Section
10.5.4.3.
Start bit
The noise flag (NF) is set during start bit reception
if one of the following conditions occurs:
1. A valid falling edge is not detected. A falling
edge is considered to be valid if the 3 consecutive samples before the falling edge occurs are
detected as '1' and, after the falling edge
occurs, during the sampling of the 16 samples,
if one of the samples numbered 3, 5 or 7 is
detected as a “1”.
2. During sampling of the 16 samples, if one of the
samples numbered 8, 9 or 10 is detected as a
“1”.
Therefore, a valid Start Bit must satisfy both the
above conditions to prevent the Noise Flag getting
set.
Data Bits
The noise flag (NF) is set during normal data bit reception if the following condition occurs:
– During the sampling of 16 samples, if all three
samples numbered 8, 9 and10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise
Flag getting set.
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Figure 49. Bit Sampling in Reception Mode
RDI LINE
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Sample
clock
sampled values
1
2
3
4
5
6
7
8
9
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13
14
15
16
6/16
7/16
7/16
One bit time
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ST7262xxx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.5 Low Power Modes
10.5.6 Interrupts
The SCI interrupt events are connected to the
Mode
Description
same interrupt vector.
No effect on SCI.
These events generate an interrupt if the correWAIT
SCI interrupts cause the device to exit from
sponding Enable Control Bit is set and the interWait mode.
rupt mask in the CC register is reset (RIM instrucSCI registers are frozen.
tion).
HALT
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
Enable Exit
Event
Control from
Flag
Bit
Wait
Interrupt Event
Transmit Data Register
TDRE
Empty
Transmission ComTC
plete
Received Data Ready
RDRF
to be Read
Overrun Error DetectOR
ed
Idle Line Detected
IDLE
Parity Error
PE
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TIE
Yes
TCIE
Yes
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Yes
No
Yes
No
Yes
Yes
No
No
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Exit
from
Halt
RIE
ILIE
PIE
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No
No
ST7262xxx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.7 Register Description
Note: The IDLE bit is not set again until the RDRF
bit has been set itself (that is, a new idle line ocSTATUS REGISTER (SCISR)
curs).
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
7
0
This bit is set by hardware when the word currently
being received in the shift register is ready to be
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
transferred into the RDR register while RDRF = 1.
An interrupt is generated if RIE = 1 in the SCICR2
register. It is cleared by a software sequence (an
Bit 7 = TDRE Transmit data register empty.
access to the SCISR register followed by a read to
This bit is set by hardware when the content of the
the SCIDR register).
TDR register has been transferred into the shift
0: No Overrun error
register. An interrupt is generated if the TIE bit = 1
1: Overrun error is detected
in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register folNote: When this bit is set RDR register content is
lowed by a write to the SCIDR register).
not lost but the shift register is overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
Note: Data is not transferred to the shift register
This bit is set by hardware when noise is detected
unless the TDRE bit is cleared.
on a received frame. It is cleared by a software sequence (an access to the SCISR register followed
by a read to the SCIDR register).
Bit 6 = TC Transmission complete.
0: No noise is detected
This bit is set by hardware when transmission of a
1: Noise is detected
frame containing Data is complete. An interrupt is
generated if TCIE = 1 in the SCICR2 register. It is
Note: This bit does not generate interrupt as it apcleared by a software sequence (an access to the
pears at the same time as the RDRF bit which itSCISR register followed by a write to the SCIDR
self generates an interrupt.
register).
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchronizaNote: TC is not set after the transmission of a Pretion, excessive noise or a break character is deamble or a Break.
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
Bit 5 = RDRF Received data ready flag.
the SCIDR register).
This bit is set by hardware when the content of the
0: No Framing error is detected
RDR register has been transferred to the SCIDR
1: Framing error or break character is detected
register. An interrupt is generated if RIE = 1 in the
Note: This bit does not generate interrupt as it apSCICR2 register. It is cleared by a software sepears at the same time as the RDRF bit which itquence (an access to the SCISR register followed
self generates an interrupt. If the word currently
by a read to the SCIDR register).
being transferred causes both frame error and
0: Data is not received
overrun error, it will be transferred and only the OR
1: Received data is ready to be read
bit will be set.
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Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE = 1 in
the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Bit 0 = PE Parity error.
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by
an access to the SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
1: Parity error
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ST7262xxx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
Reset Value: x000 0000 (x0h)
set or cleared by software.
0: Idle Line
7
0
1: Address Mark
R8
T8
SCID
M
WAKE
PCE
PS
PIE
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M = 1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmitted word when M = 1.
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte transfer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 2 = PCE Parity control enable.
This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB
position (9th bit if M = 1; 8th bit if M = 0) and parity
is checked on the received data. This bit is set and
cleared by software. Once it is set, PCE is active
after the current byte (in reception and in transmission).
0: Parity control disabled
1: Parity control enabled
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Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity is
selected after the current byte.
0: Even parity
1: Odd parity
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Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
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Note: The M bit must not be modified during a data
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Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hardware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled.
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ST7262xxx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Notes:
Read/Write
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
Reset Value: 0000 0000 (00h)
after the current word.
7
0
– When TE is set there is a 1 bit-time delay before
the transmission starts.
TIE
TCIE
RIE
ILIE
TE
RE
RWU SBK
CAUTION: The TDO pin is free for general purpose I/O only when the TE and RE bits are both
cleared (or if TE is never set).
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
Bit 2 = RE Receiver enable.
1: An SCI interrupt is generated whenever
This bit enables the receiver. It is set and cleared
TDRE=1 in the SCISR register
by software.
0: Receiver is disabled
Bit 6 = TCIE Transmission complete interrupt ena1: Receiver is enabled and begins searching for a
ble
start bit
This bit is set and cleared by software.
0: Interrupt is inhibited
Bit 1 = RWU Receiver wake-up.
1: An SCI interrupt is generated whenever TC=1 in
This bit determines if the SCI is in mute mode or
the SCISR register
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
Bit 5 = RIE Receiver interrupt enable.
recognized.
This bit is set and cleared by software.
0: Receiver in Active mode
0: Interrupt is inhibited
1: Receiver in Mute mode
1: An SCI interrupt is generated whenever OR=1
Note: Before selecting Mute mode (setting the
or RDRF=1 in the SCISR register
RWU bit), the SCI must receive some data first,
otherwise it cannot function in Mute mode with
Bit 4 = ILIE Idle line interrupt enable.
wake-up by idle line detection.
This bit is set and cleared by software.
0: Interrupt is inhibited
Bit 0 = SBK Send break.
1: An SCI interrupt is generated whenever IDLE=1
This bit set is used to send break characters. It is
in the SCISR register.
set and cleared by software.
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Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
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0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter sends a BREAK word at the end of the
current word.
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ST7262xxx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data character, depending on whether it is read from or written to.
7
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
TR dividing factor
SCT2
SCT1
SCT0
1
0
0
0
2
0
0
1
4
0
1
0
8
0
1
16
1
0
32
1
0
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift register (see Figure 46).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 46).
BAUD RATE REGISTER (SCIBRR)
Read/Write
Reset Value: 0000 0000 (00h)
SCT2
SCT1
SCT0
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SCR2
SCR1 SCR0
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
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SCP1
SCP0
0
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0
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1
0
1
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
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RR Dividing factor
7
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128
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SCR2
SCR1
SCR0
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2
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16
1
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ST7262xxx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
Read/Write
Reset Value: 0000 0000 (00h)
Allows setting of the Extended Prescaler rate division factor for the receive circuit.
7
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Reset Value:0000 0000 (00h)
Allows setting of the External Prescaler rate division factor for the transmit circuit.
0
7
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
7
6
5
4
3
2
1
0
0
ETPR
7
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 48) is divided by
the binary factor set in the SCIERPR register (in
the range 1 to 255).
The extended baud rate generator is not used after a reset.
ETPR
6
ETPR
5
ETPR
4
ETPR
3
ETPR
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Conditions
Parameter
fCPU
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Communication frequency 8 MHz
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Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 48) is divided by
the binary factor set in the SCIETPR register (in
the range 1 to 255).
The extended baud rate generator is not used after a reset.
Table 21. Baudrate Selection
Symbol
ETPR ETPR
1
0
~0.79%
Prescaler
Conventional Mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 3
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
Extended Mode
ETPR (or ERPR) = 35,
TR (or RR)= 1, PR=1
Doc ID 6996 Rev 5
Standard
300
1200
2400
4800
9600
10400
19200
38400
Baud
Rate
~300.48
~1201.92
~2403.84
~4807.69
~9615.38
~10416.67
~19230.77
~38461.54
Unit
Hz
14400 ~14285.71
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Table 22. SCI Register Map and Reset Values
Address
Register
Name
(Hex.)
7
6
5
4
3
2
1
0
1D
SCIERPR
Reset Value
ERPR7
0
ERPR6
0
ERPR5
0
ERPR4
0
ERPR3
0
ERPR2
0
ERPR1
0
ERPR0
0
1E
SCIETPR
Reset Value
ETPR7
0
ETPR6
0
ETPR5
0
ETPR4
0
ETPR3
0
ETPR2
0
ETPR1
0
ETPR0
0
20
SCISR
Reset Value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
21
SCIDR
Reset Value
DR7
x
DR6
x
DR5
x
DR4
x
DR3
x
DR2
x
DR1
x
22
SCIBRR
Reset Value
SCP1
0
SCP0
0
SCT2
0
SCT1
0
SCT0
0
SCR2
0
SCR1
0
SCR0
0
23
SCICR1
Reset Value
R8
x
T8
0
SCID
0
M
0
WAKE
0
PCE
0
PS
0
PIE
0
24
SCICR2
Reset Value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
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ST7262xxx
10.6 USB INTERFACE (USB)
10.6.1 Introduction
The USB Interface implements a low-speed function interface between the USB and the ST7 microcontroller. It is a highly integrated circuit which
includes the transceiver, 3.3 voltage regulator, SIE
and DMA. No external components are needed
apart from the external pull-up on USBDM for low
speed recognition by the USB host. The use of
DMA architecture allows the endpoint definition to
be completely flexible. Endpoints can be configured by software as in or out.
10.6.2 Main Features
■ USB Specification Version 1.1 Compliant
■ Supports Low-Speed USB Protocol
■ Two or Three Endpoints (including default one)
depending on the device (see device feature list
and register map)
■ CRC
generation/checking, NRZI encoding/
decoding and bit-stuffing
■ USB Suspend/Resume operations
■ DMA Data transfers
■ On-Chip 3.3V Regulator
■ On-Chip USB Transceiver
10.6.3 Functional Description
The block diagram in Figure 50, gives an overview
of the USB interface hardware.
For general information on the USB, refer to the
“Universal Serial Bus Specifications” document
available at http//:www.usb.org.
Serial Interface Engine
The SIE (Serial Interface Engine) interfaces with
the USB, via the transceiver.
The SIE processes tokens, handles data transmission/reception, and handshaking as required by
the USB standard. It also performs frame formatting, including CRC generation and checking.
Endpoints
The Endpoint registers indicate if the microcontroller is ready to transmit/receive, and how many
bytes need to be transmitted.
DMA
When a token for a valid Endpoint is recognized by
the USB interface, the related data transfer takes
place, using DMA. At the end of the transaction, an
interrupt is generated.
Interrupts
By reading the Interrupt Status register, application software can know which USB event has occurred.
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Figure 50. USB Block Diagram
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USBDM
Transceiver
USBDP
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6 MHz
ENDPOINT
REGISTERS
SIE
DMA
CPU
Address,
data buses
and interrupts
USBVCC
3.3V
Voltage
Regulator
INTERRUPT
REGISTERS
MEMORY
USBGND
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ST7262xxx
USB INTERFACE (Cont’d)
10.6.4 Register Description
DMA ADDRESS REGISTER (DMAR)
Read / Write
Reset Value: Undefined
INTERRUPT/DMA REGISTER (IDR)
Read / Write
Reset Value: xxxx 0000 (x0h)
7
7
0
DA15
DA14
DA13
DA12
DA11
DA10
DA9
DA7
0
DA6
EP1
EP0
CNT3
CNT2
CNT1
CNT0
DA8
Bits 7:0=DA[15:8] DMA address bits 15-8.
Software must write the start address of the DMA
memory area whose most significant bits are given
by DA15-DA6. The remaining 6 address bits are
set by hardware. See the description of the IDR
register and Figure 51.
Bits 7:6 = DA[7:6] DMA address bits 7-6.
Software must reset these bits. See the description of the DMAR register and Figure 51.
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Bits 5:4 = EP[1:0] Endpoint number (read-only).
These bits identify the endpoint which required attention.
00: Endpoint 0
01: Endpoint 1
10: Endpoint 2
When a CTR interrupt occurs (see register ISTR)
the software should read the EP bits to identify the
endpoint which has sent or received a packet.
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Bits 3:0 = CNT[3:0] Byte count (read only).
This field shows how many data bytes have been
received during the last data reception.
Note: Not valid for data transmission.
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Figure 51. DMA Buffers
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101111
Endpoint 2 TX
101000
100111
Endpoint 2 RX
100000
011111
011000
010111
010000
001111
Endpoint 1 TX
Endpoint 1 RX
Endpoint 0 TX
001000
000111
Endpoint 0 RX
DA15-6,000000
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Doc ID 6996 Rev 5
ST7262xxx
USB INTERFACE (Cont’d)
PID REGISTER (PIDR)
Read only
Reset Value: xx00 0000 (x0h)
INTERRUPT STATUS REGISTER (ISTR)
Read / Write
Reset Value: 0000 0000 (00h)
7
TP3
7
0
TP2
0
0
RX_
SEZ
0
RXD
SUSP
0
Bits 7:6 = TP[3:2] Token PID bits 3 & 2.
USB token PIDs are encoded in four bits. TP[3:2]
correspond to the variable token PID bits 3 & 2.
Note: PID bits 1 & 0 have a fixed value of 01.
When a CTR interrupt occurs (see register ISTR)
the software should read the TP3 and TP2 bits to
retrieve the PID name of the token received.
The USB standard defines TP bits as:
TP3
0
1
1
TP2
0
0
1
PID Name
OUT
IN
SETUP
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Bit 1 = RXD Received data
0: No K-state
1: USB lines are in K-state
This bit indicates the status of the RXD transceiver
output (differential receiver output).
Note: If the environment is noisy, the RX_SEZ and
RXD bits can be used to secure the application. By
interpreting the status, software can distinguish a
valid End Suspend event from a spurious wake-up
due to noise on the external USB line. A valid End
Suspend is followed by a Resume or Reset sequence. A Resume is indicated by RXD=1, a Reset is indicated by RX_SEZ=1.
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Bit 0 = Reserved. Forced by hardware to 0.
ERR
IOVR
ESUSP
RESET
SOF
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Bit 7 = SUSP Suspend mode request.
This bit is set by hardware when a constant idle
state is present on the bus line for more than 3 ms,
indicating a suspend mode request from the USB
bus. The suspend request check is active immediately after each USB reset event and its disabled
by hardware when suspend mode is forced
(FSUSP bit of CTLR register) until the end of
resume sequence.
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CTR
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Bit 2 = RX_SEZ Received single-ended zero
This bit indicates the status of the RX_SEZ transceiver output.
0: No SE0 (single-ended zero) state
1: USB lines are in SE0 (single-ended zero) state
P
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DOVR
When an interrupt occurs these bits are set by
hardware. Software must read them to determine
the interrupt type and clear them after servicing.
Note: These bits cannot be set by software.
Bits 5:3 Reserved. Forced by hardware to 0.
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Bit 6 = DOVR DMA over/underrun.
This bit is set by hardware if the ST7 processor
can’t answer a DMA request in time.
0: No over/underrun detected
1: Over/underrun detected
Bit 5 = CTR Correct Transfer. This bit is set by
hardware when a correct transfer operation is performed. The type of transfer can be determined by
looking at bits TP3-TP2 in register PIDR. The Endpoint on which the transfer was made is identified
by bits EP1-EP0 in register IDR.
0: No Correct Transfer detected
1: Correct Transfer detected
Note: A transfer where the device sent a NAK or
STALL handshake is considered not correct (the
host only sends ACK handshakes). A transfer is
considered correct if there are no errors in the PID
and CRC fields, if the DATA0/DATA1 PID is sent
as expected, if there were no data overruns, bit
stuffing or framing errors.
Bit 4 = ERR Error.
This bit is set by hardware whenever one of the errors listed below has occurred:
0: No error detected
1: Timeout, CRC, bit stuffing or nonstandard
framing error detected
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ST7262xxx
USB INTERFACE (Cont’d)
Bit 3 = IOVR Interrupt overrun.
This bit is set when hardware tries to set ERR, or
SOF before they have been cleared by software.
0: No overrun detected
1: Overrun detected
Bit 2 = ESUSP End suspend mode.
This bit is set by hardware when, during suspend
mode, activity is detected that wakes the USB interface up from suspend mode.
This interrupt is serviced by a specific vector, in order to wake up the ST7 from HALT mode.
0: No End Suspend detected
1: End Suspend detected
Bit 1 = RESET USB reset.
This bit is set by hardware when the USB reset sequence is detected on the bus.
0: No USB reset signal detected
1: USB reset signal detected
Note: The DADDR, EP0RA, EP0RB, EP1RA,
EP1RB, EP2RA and EP2RB registers are reset by
a USB reset.
of each bit, please refer to the corresponding bit
description in ISTR.
CONTROL REGISTER (CTLR)
Read / Write
Reset Value: 0000 0110 (06h)
7
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INTERRUPT MASK REGISTER (IMR)
Read / Write
Reset Value: 0000 0000 (00h)
7
SUS
PM
0
DOV
RM
CTR
M
ERR
M
IOVR
M
ESU
SPM
RES
ETM
SOF
M
Bits 7:0 = These bits are mask bits for all interrupt
condition bits included in the ISTR. Whenever one
of the IMR bits is set, if the corresponding ISTR bit
is set, and the I bit in the CC register is cleared, an
interrupt request is generated. For an explanation
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RESUME
PDWN
FSUSP
FRES
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Bits 7:4 = Reserved. Forced by hardware to 0.
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Bit 3 = RESUME Resume.
This bit is set by software to wake-up the Host
when the ST7 is in suspend mode.
0: Resume signal not forced
1: Resume signal forced on the USB bus.
Software should clear this bit after the appropriate
delay.
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Bit 2 = PDWN Power down.
This bit is set by software to turn off the 3.3V onchip voltage regulator that supplies the external
pull-up resistor and the transceiver.
0: Voltage regulator on
1: Voltage regulator off
Note: After turning on the voltage regulator, software should allow at least 3 µs for stabilisation of
the power supply before using the USB interface.
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Bit 0 = SOF Start of frame.
This bit is set by hardware when a low-speed SOF
indication (keep-alive strobe) is seen on the USB
bus. It is also issued at the end of a resume sequence.
0: No SOF signal detected
1: SOF signal detected
Note: To avoid spurious clearing of some bits, it is
recommended to clear them using a load instruction where all bits which must not be altered are
set, and all bits to be cleared are reset. Avoid readmodify-write instructions like AND, XOR..
0
Bit 1 = FSUSP Force suspend mode.
This bit is set by software to enter Suspend mode.
The ST7 should also be halted allowing at least
600 ns before issuing the HALT instruction.
0: Suspend mode inactive
1: Suspend mode active
When the hardware detects USB activity, it resets
this bit (it can also be reset by software).
Bit 0 = FRES Force reset.
This bit is set by software to force a reset of the
USB interface, just as if a RESET sequence came
from the USB.
0: Reset not forced
1: USB interface reset forced.
The USB is held in RESET state until software
clears this bit, at which point a “USB-RESET” interrupt will be generated if enabled.
Doc ID 6996 Rev 5
ST7262xxx
USB INTERFACE (Cont’d)
DEVICE ADDRESS REGISTER (DADDR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Bit 7 = Reserved. Forced by hardware to 0.
Bits 6:0 = ADD[6:0] Device address, 7 bits.
Software must write into this register the address
sent by the host during enumeration.
Note: This register is also reset when a USB reset
is received from the USB bus or forced through bit
FRES in the CTLR register.
7
STAT
_TX1
STAT
_TX0
TBC
3
TBC
2
TBC
1
TBC
0
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These registers (EP0RA, EP1RA and EP2RA) are
used for controlling data transmission. They are
also reset by the USB bus reset.
Note: Endpoint 2 and the EP2RA register are not
available on some devices (see device feature list
and register map).
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STAT_TX1 STAT_TX0 Meaning
DISABLED: transmission
0
0
transfers cannot be executed.
STALL: the endpoint is stalled
0
1
and all transmission requests
result in a STALL handshake.
NAK: the endpoint is naked
1
0
and all transmission requests
result in a NAK handshake.
VALID: this endpoint is ena1
1
bled for transmission.
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Bits 5:4 = STAT_TX[1:0] Status bits, for transmission transfers.
These bits contain the information about the endpoint status, which are listed below:
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ENDPOINT n REGISTER A (EPnRA)
Read / Write
Reset Value: 0000 xxxx (0xh)
ST_
OUT
Bit 6 = DTOG_TX Data Toggle, for transmission
transfers.
It contains the required value of the toggle bit
(0=DATA0, 1=DATA1) for the next transmitted
data packet. This bit is set by hardware at the reception of a SETUP PID. DTOG_TX toggles only
when the transmitter has received the ACK signal
from the USB host. DTOG_TX and also
DTOG_RX (see EPnRB) are normally updated by
hardware, at the receipt of a relevant PID. They
can be also written by software.
Bit 7 = ST_OUT Status out.
This bit is set by software to indicate that a status
out packet is expected: in this case, all nonzero
OUT data transfers on the endpoint are STALLed
instead of being ACKed. When ST_OUT is reset,
OUT transactions can have any number of bytes,
as needed.
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These bits are written by software. Hardware sets
the STAT_TX bits to NAK when a correct transfer
has occurred (CTR=1) related to a IN or SETUP
transaction addressed to this endpoint; this allows
the software to prepare the next set of data to be
transmitted.
Bits 3:0 = TBC[3:0] Transmit byte count for Endpoint n.
Before transmission, after filling the transmit buffer, software must write in the TBC field the transmit packet size expressed in bytes (in the range 08).
Warning: Any value outside the range 0-8 will induce undesired effects (such as continuous data
transmission).
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ST7262xxx
USB INTERFACE (Cont’d)
ENDPOINT n REGISTER B (EPnRB)
Read / Write
Reset Value: 0000 xxxx (0xh)
STAT_RX1
7
STAT_RX0 Meaning
1
0
1
1
NAK: the endpoint is naked and all reception requests result in a NAK
handshake.
VALID: this endpoint is
enabled for reception.
0
CTRL
DTOG
_RX
STAT
_RX1
STAT
_RX0
EA3
EA2
EA1
EA0
These registers (EP1RB and EP2RB) are used for
controlling data reception on Endpoints 1 and 2.
They are also reset by the USB bus reset.
Note: Endpoint 2 and the EP2RB register are not
available on some devices (see device feature list
and register map).
Bit 7 = CTRL Control.
This bit should be 0.
Note: If this bit is 1, the Endpoint is a control endpoint. (Endpoint 0 is always a control Endpoint, but
it is possible to have more than one control Endpoint).
These bits are written by software. Hardware sets
the STAT_RX bits to NAK when a correct transfer
has occurred (CTR=1) related to an OUT or SETUP transaction addressed to this endpoint, so the
software has the time to elaborate the received
data before acknowledging a new transaction.
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Bits 3:0 = EA[3:0] Endpoint address.
Software must write in this field the 4-bit address
used to identify the transactions directed to this
endpoint. Usually EP1RB contains “0001” and
EP2RB contains “0010”.
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Bit 6 = DTOG_RX Data toggle, for reception transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
This bit is cleared by hardware in the first stage
(Setup Stage) of a control transfer (SETUP transactions start always with DATA0 PID). The receiver toggles DTOG_RX only if it receives a correct
data packet and the packet’s data PID matches
the receiver sequence bit.
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Bits 5:4 = STAT_RX [1:0] Status bits, for reception
transfers.
These bits contain the information about the endpoint status, which are listed below:
STAT_RX1
STAT_RX0 Meaning
0
0
0
1
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DISABLED: reception
transfers cannot be executed.
STALL: the endpoint is
stalled and all reception
requests result in a
STALL handshake.
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ENDPOINT 0 REGISTER B (EP0RB)
Read / Write
Reset Value: 1000 0000 (80h)
7
1
0
DTOG
RX
STAT
RX1
STAT
RX0
0
0
0
0
This register is used for controlling data reception
on Endpoint 0. It is also reset by the USB bus reset.
Bit 7 = Forced by hardware to 1.
Bits 6:4 = Refer to the EPnRB register for a description of these bits.
Bits 3:0 = Forced by hardware to 0.
Doc ID 6996 Rev 5
USB INTERFACE (Cont’d)
10.6.5 Programming Considerations
The interaction between the USB interface and the
application program is described below. Apart
from system reset, action is always initiated by the
USB interface, driven by one of the USB events
associated with the Interrupt Status Register (ISTR) bits.
10.6.5.1 Initializing the Registers
At system reset, the software must initialize all registers to enable the USB interface to properly generate interrupts and DMA requests.
1. Initialize the DMAR, IDR, and IMR registers
(choice of enabled interrupts, address of DMA
buffers). Refer the paragraph titled initializing
the DMA Buffers.
2. Initialize the EP0RA and EP0RB registers to
enable accesses to address 0 and endpoint 0
to support USB enumeration. Refer to the paragraph titled Endpoint Initialization.
3. When addresses are received through this
channel, update the content of the DADDR.
4. If needed, write the endpoint numbers in the EA
fields in the EP1RB and EP2RB register.
10.6.5.2 Initializing DMA buffers
The DMA buffers are a contiguous zone of memory whose maximum size is 48 bytes. They can be
placed anywhere in the memory space to enable
the reception of messages. The 10 most significant bits of the start of this memory area are specified by bits DA15-DA6 in registers DMAR and
IDR, the remaining bits are 0. The memory map is
shown in Figure 51.
Each buffer is filled starting from the bottom (last 3
address bits=000) up.
10.6.5.3 Endpoint Initialization
To be ready to receive:
Set STAT_RX to VALID (11b) in EP0RB to enable
reception.
To be ready to transmit:
1. Write the data in the DMA transmit buffer.
2. In register EPnRA, specify the number of bytes
to be transmitted in the TBC field
3. Enable the endpoint by setting the STAT_TX
bits to VALID (11b) in EPnRA.
Note: Once transmission and/or reception are enabled, registers EPnRA and/or EPnRB (respectively) must not be modified by software, as the
hardware can change their value on the fly.
When the operation is completed, they can be accessed again to enable a new operation.
10.6.5.4 Interrupt Handling
Start of Frame (SOF)
The interrupt service routine may monitor the SOF
events for a 1 ms synchronization event to the
USB bus. This interrupt is generated at the end of
a resume sequence and can also be used to detect this event.
USB Reset (RESET)
When this event occurs, the DADDR register is reset, and communication is disabled in all endpoint
registers (the USB interface will not respond to any
packet). Software is responsible for reenabling
endpoint 0 within 10 ms of the end of reset. To do
this, set the STAT_RX bits in the EP0RB register
to VALID.
Suspend (SUSP)
The CPU is warned about the lack of bus activity
for more than 3 ms, which is a suspend request.
The software should set the USB interface to suspend mode and execute an ST7 HALT instruction
to meet the USB-specified power constraints.
End Suspend (ESUSP)
The CPU is alerted by activity on the USB, which
causes an ESUSP interrupt. The ST7 automatically terminates HALT mode.
Correct Transfer (CTR)
1. When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to NAK.
Note: Every valid endpoint is NAKed until software clears the CTR bit in the ISTR register,
independently of the endpoint number
addressed by the transfer which generated the
CTR interrupt.
Note: If the event triggering the CTR interrupt is
a SETUP transaction, both STAT_TX and
STAT_RX are set to NAK.
2. Read the PIDR to obtain the token and the IDR
to get the endpoint number related to the last
transfer.
Note: When a CTR interrupt occurs, the TP3TP2 bits in the PIDR register and EP1-EP0 bits
in the IDR register stay unchanged until the
CTR bit in the ISTR register is cleared.
3. Clear the CTR bit in the ISTR register.
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USB INTERFACE (Cont’d)
Table 23. USB Register Map and Reset Values
Address
Register
Name
(Hex.)
PIDR
25
Reset Value
DMAR
26
Reset Value
IDR
27
Reset Value
ISTR
28
Reset Value
IMR
29
2A
2B
2D
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1
0
TP3
TP2
0
0
0
RX_SEZ
RXD
0
x
x
0
0
0
0
0
0
DA15
DA14
DA13
DA12
DA11
DA10
DA9
DA8
x
x
x
x
x
x
x
x
DA7
DA6
EP1
EP0
CNT3
CNT2
CNT1
x
x
x
x
0
0
0
SUSP
DOVR
CTR
ERR
IOVR
ESUSP
RESET
0
0
0
0
0
0
0
CTRM
ERRM
IOVRM
0
0
0
CTLR
0
0
0
0
RESUME
Reset Value
0
0
0
0
DADDR
0
ADD6
ADD5
ADD4
ADD3
Reset Value
0
0
0
0
0
ST_OUT
Reset Value
0
EP0RB
1
Reset Value
1
0
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Reset Value
0
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0
0
0
0
CTRL
0
DTOG_TX STAT_TX1 STAT_TX0
0
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P
ST_OUT
0
t(s
0
DTOG_RX STAT_RX1 STAT_RX0
CTRL
Reset Value
EP2RB
0
)-
0
0
0
DTOG_RX STAT_RX1 STAT_RX0
0
DTOG_TX STAT_TX1 STAT_TX0
0
0
0
DTOG_RX STAT_RX1 STAT_RX0
0
0
0
Doc ID 6996 Rev 5
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Pr
ESUSPM RESETM
0
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CNT0
SOF
0
SOFM
0
0
PDWN
FSUSP
FRES
1
1
0
ADD2
ADD1
ADD0
0
0
0
TBC3
TBC2
TBC1
TBC0
x
x
x
x
0
0
0
0
0
0
0
0
TBC3
TBC2
TBC1
TBC0
x
x
x
x
EA3
EA2
EA1
EA0
x
x
x
x
TBC3
TBC2
TBC1
TBC0
x
x
x
x
EA3
EA2
EA1
EA0
x
x
x
x
ete
ol
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DTOG_TX STAT_TX1 STAT_TX0
0
ST_OUT
EP2RA
O
2
0
Reset Value
31
3
DOVRM
EP1RB
30
4
0
Reset Value
2F
5
SUSPM
EP1RA
2E
6
Reset Value
EP0RA
2C
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10.7 10-BIT A/D CONVERTER (ADC)
10.7.1 Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This
peripheral has up to 8 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 8 different sources.
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
10.7.2 Main Features
■ 10-bit conversion
■ Up to 8 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ Continuous or One-Shot mode
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 52.
digital ground plane via a single point on the
PCB. The analog power plane should be connected to the digital power plane via an RC network.
– Filter power to the analog power planes. The
best solution is to connect a 0.1µF capacitor, with
good high frequency characteristics, between
VDDA and VSSA and place it as close as possible
to the VDDA and VSSA pins and connect the analog and digital power supplies in a star network.
Do not use a resistor, as VDDA is used as a reference voltage by the A/D converter and resistance would cause a voltage drop and a loss of
accuracy.
– Properly place components and route the signal
traces on the PCB to shield the analog inputs.
Analog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signal from digital signals that may switch
while the analog inputs are being sampled by the
A/D converter. Do not toggle digital outputs on
the same I/O port as the A/D input being converted.
10.7.3.3 Digital A/D Conversion Result
The conversion is monotonic, meaning that the result never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (VAIN) is greater than VDDA
(high-level voltage reference) then the conversion
result is FFh in the ADCDRMSB register and 03h
in the ADCDRLSB register (without overflow indication).
If the input voltage (VAIN) is lower than VSSA (lowlevel voltage reference) then the conversion result
in the ADCDRMSB and ADCDRLSB registers is
00 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRMSB and
ADCDRLSB registers. The accuracy of the conversion is described in the Electrical Characteristics Section.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
allotted time.
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10.7.3 Functional Description
10.7.3.1 Analog Power Supply
Depending on the MCU pin count, the package
may feature separate VDDA and VSSA analog power supply pins. These pins supply power to the A/D
converter cell and function as the high and low reference voltages for the conversion. In smaller
packages VDDA and VSSA pins are not available
and the analog supply and reference pads are internally bonded to the VDD and VSS pins.
Separation of the digital and analog power pins allow board designers to improve A/D performance.
Conversion accuracy can be impacted by voltage
drops and noise in the event of heavily loaded or
badly decoupled power supply lines.
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10.7.3.2 PCB Design Guidelines
To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the noise-sensitive,
analog physical interface from noise-generating
CMOS logic signals.
– Use separate digital and analog planes. The analog ground plane should be connected to the
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10-BIT A/D CONVERTER (ADC) (Cont’d)
10.7.3.4 A/D Conversion
Conversion can be performed in One-Shot or Continuous mode. Continuous mode is typically used
for monitoring a single channel. One-shot mode
should be used when the application requires inputs from several channels.
2.Set the ADON bit to enable the A/D converter
and to start the conversion. The EOC bit is kept
low by hardware during the conversion.
Note: Changing the A/D channel during conversion will stop the current conversion and start conversion of the newly selected channel.
ADC Configuration
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the ADCCSR register:
– Select the CS[2:0] bits to assign the analog
channel to convert.
When a conversion is complete:
– The EOC bit is set by hardware.
– An interrupt request is generated if the ITE bit
is set.
– The ADON bit is reset by hardware.
– The result is in the ADCDR registers.
To read the 10 bits, perform the following steps:
1. Wait for interrupt or poll the EOC bit
2. Read ADCDRLSB
3. Read ADCDRMSB
The EOC bit is reset by hardware once the ADCDRMSB is read.
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ADC One-Shot Conversion mode
In the ADCCSR register:
1.Set the ONE SHOT bit to put the A/D converter
in one shot mode.
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Figure 52. ADC Block Diagram
fCPU
DIV 2
0
DIV 4
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EOC SPEED ADON
O
AIN1
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EOC Interrupt
ONE
SHOT CS2
CS1
CS0
ADCCSR
3
ANALOG TO DIGITAL
ANALOG
MUX
CONVERTER
AINx
ADCDRMSB
D9
D8
ADCDRLSB
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D7
0
D6
D5
0
Doc ID 6996 Rev 5
0
D4
0
D3
0
D2
0
D1
D0
10-BIT A/D CONVERTER (ADC) (Cont’d)
To read only 8 bits, perform the following steps:
1. Wait for interrupt or poll the EOC bit
2. Read ADCDRMSB
The EOC bit is reset by hardware once the ADCDRMSB is read.
To start another conversion, user should set the
ADON bit once again.
ADC Continuous Conversion mode
In the ADCCSR register:
1.Reset the ONE SHOT bit to put the A/D converter in continuous mode.
2.Set the ADON bit to enable the A/D converter
and to start the first conversion. From this time
on, the ADC performs a continuous conversion
of the selected channel.
Note: Changing the A/D channel during conversion will stop the current conversion and start conversion of the newly selected channel.
When a conversion is complete:
– The EOC bit is set by hardware.
– An interrupt request is generated if the ITE bit
is set.
– The result is in the ADCDR registers and remains valid until the next conversion has ended.
ADCCR consistency
If an End Of Conversion event occurs after software has read the ADCDRLSB but before it has
read the ADCDRMSB, there would be a risk that
the two values read would belong to different samples.
To guarantee consistency:
– The ADCDRMSB and the ADCDRLSB are
locked when the ADCCRLSB is read
– The ADCDRMSB and the ADCDRLSB are unlocked when the MSB is read or when ADON
is reset.
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Thus, it is mandatory to read the ADCDRMSB just
after reading the ADCDRLSB. This is especially
important in continuous mode, as the ADCDR register will not be updated until the ADCDRMSB is
read.
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10.7.4 Low Power Modes
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
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To read the 10 bits, perform the following steps:
1. Wait for interrupt or poll the EOC bit
2. Read ADCDRLSB
3. Read ADCDRMSB
The EOC bit is reset by hardware once the ADCDRMSB is read.
To read only 8 bits, perform the following steps:
1. Wait for interrupt
2. Read ADCDRMSB
The EOC bit is reset by hardware once the ADCDRMSB is read.
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Changing the conversion channel
The application can change channels during conversion. In this case the current conversion is
stopped and the A/D converter starts converting
the newly selected channel.
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Mode
WAIT
HALT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilisation time
tSTAB (see Electrical Characteristics)
before accurate conversions can be
performed.
10.7.5 Interrupts
Interrupt Event
End of Conversion
Enable
Event
Control
Flag
Bit
EOC
ITE
Exit
from
Wait
Yes
Exit
from
Halt
No
Note: The EOC interrupt event is connected to an
interrupt vector (see Interrupts chapter).
It generates an interrupt if the ITE bit is set in the
ADCCSR register and the interrupt mask in the CC
register is reset (RIM instruction).
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10-BIT A/D CONVERTER (ADC) (Cont’d)
10.7.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
7
Bit 2:0 = CS[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel*
CS2
CS1
CS0
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
EOC SPEED ADON
ONE
SHOT
ITE
CS2
CS1
CS0
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by software reading the ADCDRMSB register.
0: Conversion is not complete
1: Conversion complete
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DATA REGISTER (ADCDRMSB)
Read Only
Reset Value: 0000 0000 (00h)
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software or by hardware after the end of a one shot conversion.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
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Bit 3 = ONESHOT One Shot Conversion Selection
This bit is set and cleared by software.
0: Continuous conversion mode
1: One Shot conversion mode
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*The number of channels is device dependent. Refer to
the device pinout description.
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software.
0: fADC = fCPU/2
1: fADC = fCPU/4
Bit 4 = ITE Interrupt Enable
This bit is set and cleared by software.
0: EOC Interrupt disabled
1: EOC Interrupt enabled
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D8
0
D7
D6
D5
D4
D3
D2
Bit 7:0 = D[9:2] MSB of Analog Converted Value
This register contains the MSB of the converted
analog value.
DATA REGISTER (ADCDRLSB)
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
D1
D0
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Analog Converted Value
This register contains the LSB of the converted analog value.
Note: please refer to Section 15 IMPORTANT
NOTES
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11 INSTRUCTION SET
11.1 CPU ADDRESSING MODES
The CPU features 17 different addressing modes
which can be classified in seven main groups:
Addressing Mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset
so, most of the addressing modes may be subdivided in two submodes called long and short:
– Long addressing mode is more powerful because it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cycles.
– Short addressing mode is less powerful because
it can generally only access page zero (0000h 00FFh range), but the instruction size is more
compact, and faster. All memory to memory instructions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and
short addressing modes.
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byte,#5
The CPU Instruction set is designed to minimize
the number of bytes required per instruction: To do
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Table 24. CPU Addressing Mode Overview
Mode
Syntax
Inherent
nop
Immediate
ld A,#$55
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Short
Direct
ld A,$10
Long
Direct
ld A,$1000
No Offset
Direct
Indexed
Short
Direct
Indexed
Long
Direct
Short
Indirect
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Indexed
Pointer Size
(Hex.)
Length
(Bytes)
+0
+1
00..FF
+1
0000..FFFF
+2
ld A,(X)
00..FF
+0
ld A,($10,X)
00..1FE
+1
ld A,($1000,X)
0000..FFFF
+2
ld A,[$10]
00..FF
00..FF
byte
+2
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
od
Pr
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Destination
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Pointer
Address
(Hex.)
Long
Indirect
Short
Indirect
Indexed
ld A,([$10],X)
00..1FE
00..FF
byte
+2
Long
Indirect
Indexed
ld A,([$10.w],X)
0000..FFFF
00..FF
word
+2
Relative
Direct
jrne loop
PC+/-127
Relative
Indirect
jrne [$10]
PC+/-127
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
Relative
btjt $10,#7,skip
00..FF
Bit
Indirect
Relative
btjt [$10],#7,skip
00..FF
Doc ID 6996 Rev 5
+1
00..FF
byte
+2
+1
00..FF
byte
+2
+2
00..FF
byte
+3
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INSTRUCTION SET OVERVIEW (Cont’d)
11.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction
Function
NOP
No operation
TRAP
S/W Interrupt
WFI
Wait For Interrupt (Low Power Mode)
HALT
Halt Oscillator (Lowest Power
Mode)
RET
Sub-routine Return
IRET
Interrupt Sub-routine Return
SIM
Set Interrupt Mask (level 3)
RIM
Reset Interrupt Mask (level 0)
SCF
Set Carry Flag
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
LD
Load
CLR
Clear
PUSH/POP
Push/Pop to/from the stack
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Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
MUL
Byte Multiplication
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
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11.1.2 Immediate
Immediate instructions have 2 bytes, the first byte
contains the opcode, the second byte contains the
operand value.
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Immediate Instruction
LD
CP
Function
Load
Compare
BCP
Bit Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Operations
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11.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
submodes:
Indexed (No Offset)
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing
space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
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11.1.3 Direct
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two submodes:
Direct (short)
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
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11.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two submodes:
Indirect (short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Doc ID 6996 Rev 5
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the unsigned addition of an index register value (X or Y)
with a pointer value located in memory. The pointer address follows the opcode.
The indirect indexed addressing mode consists of
two submodes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Table 25. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Instructions
Load
Function
JRxx
Conditional Jump
CALLR
Call Relative
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The relative addressing mode consists of two submodes:
Relative (Direct)
The offset is following the opcode.
Relative (Indirect)
The offset is defined in memory, which address
follows the opcode.
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CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Additions/Substractions operations
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BCP
Bit Compare
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Short Instructions Only
CLR
Available Relative
Direct/Indirect
Instructions
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Function
LD
11.1.7 Relative mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
INC, DEC
Function
Clear
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
BSET, BRES
Bit Operations
BTJT, BTJF
Bit Test and Jump Operations
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
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INSTRUCTION SET OVERVIEW (Cont’d)
11.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
be subdivided into 13 main groups as illustrated in
the following table:
RSP
Increment/Decrement
INC
DEC
Compare and Tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit Operation
BSET
BRES
Conditional Bit Test and Branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and Rotates
SLL
SRL
SRA
RLC
RRC
Unconditional Jump or Call
JRA
JRT
JRF
JP
Conditional Branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Condition Code Flag modification
SIM
RIM
SCF
RCF
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Using a prebyte
The instructions are described with one to four opcodes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they precede.
The whole instruction becomes:
PC-2
End of previous instruction
PC-1
Prebyte
PC
Opcode
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the effective address
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CALL
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CALLR
SLA
NOP
RET
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These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent addressing mode by a Y one.
PIX 92
Replace an instruction using direct, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.
PIY 91
Replace an instruction using X indirect indexed addressing mode by a Y one.
Doc ID 6996 Rev 5
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
Description
Function/Example
Dst
Src
I1
H
I0
N
Z
C
ADC
Add with Carry
A=A+M+C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A, Memory
tst (A . M)
A
M
N
Z
BRES
Bit Reset
bres Byte, #3
M
BSET
Bit Set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1
M
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1
M
CALL
Call subroutine
CALLR
Call subroutine relative
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
CPL
One Complement
A = FFH-A
reg, M
DEC
Decrement
dec Y
reg, M
HALT
Halt
IRET
Interrupt routine return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
JRIH
Jump if ext. INT pin = 1
JRIL
Jump if ext. INT pin = 0
(ext. INT pin low)
JRH
Jump if H = 1
H=1?
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I1
1
N
Z
C
N
Z
1
N
Z
N
Z
N
Z
0
H
I0
C
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jrf *
Pr
(ext. INT pin high)
Jump if I1:0 = 11
I1:0 = 11 ?
Jump if I1:0 11
I1:0 11 ?
JRMI
Jump if N = 1 (minus)
N=1?
JRPL
Jump if N = 0 (plus)
N=0?
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Pr
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H=0?
JRNM
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reg, M
Jump if H = 0
JRM
C
reg, M
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JRNH
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C
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned >=
JRUGT
Jump if (C + Z = 0)
Unsigned >
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INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
Description
Dst
Src
JRULE
Jump if (C + Z = 1)
Unsigned
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