ST72F63BH2T1

ST7263BHx ST7263BDx ST7263BKx ST7263BEx Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI and I²C Features ■ ■ ■ Memories – 4, 8, 16 or 32 Kbytes Program memory: high density Flash (HDFlash), or ROM with Readout and Write Protection – In-application Programming (IAP) and incircuit programming (ICP) – 384, 512 or 1024 bytes RAM memory (128byte stack) Clock, reset and supply management – Run, Wait, Slow and Halt CPU modes – 12 or 24 MHz oscillator – RAM retention mode – Optional low voltage detector (LVD) Universal serial bus (USB) interface – DMA for low speed applications compliant with USB 1.5 Mbs (version 2.0) and HID specifications (version 1.0) – Integrated 3.3 V voltage regulator and transceivers – Supports USB DFU class specification – Suspend and Resume operations – 3 endpoints with programmable In/Out configuration ■ Up to 27 I/O ports – Up to 8 high sink I/Os (10 mA at 1.3 V) – 2 very high sink true open drain I/Os (25 mA at 1.5 V) – Up to 8 lines individually programmable as interrupt inputs ■ 1 analog peripheral – 8-bit A/D converter with 8 or 12 channels ■ 2 timers – Programmable watchdog – 16-bit timer with 2 input Captures, 2 output Compares, PWM output and clock input June 2009 LQFP48 (7x7) SDIP32 24 1 SO34(Shrink) QFN40 (6x6) SO24 ■ 2 communication Interfaces – Asynchronous serial communications interface – I²C multimaster interface up to 400 kHz ■ Instruction set – 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction – True bit manipulation ■ Development tools – Versatile development tools (under Windows) including assembler, linker, Ccompiler, archiver, source level debugger, software library, hardware emulator, programming boards and gang programmers, HID and DFU software layers Table 1. Device summary Reference Part number ST7263BHx ST7263BH2, ST7263BH6 ST7263BDx ST7263BD6 ST7263BKx ST7263BK1, ST7263BK2, ST7263BK4, ST7263BK6 ST7263BEx ST7263BE1, ST7263BE2, ST7263BE4, ST7263BE6 Doc ID 7516 Rev 8 1/186 www.st.com 1 Contents ST7263Bxx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 RESET signal (bidirectional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 OSCIN/OSCOUT: input/output oscillator pin . . . . . . . . . . . . . . . . . . . . . . 13 2.3 VDD/VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 VDDA/VSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.1 5 6 4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 6.2 2/186 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.2 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.3 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Doc ID 7516 Rev 8 ST7263Bxx 7 Contents 9 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1 8 6.2.1 Interrupt register (ITRFRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.3 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.4 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.3.3 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.3.4 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.3.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.3.6 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10 Miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 11.2 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.4 Software Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1.5 Hardware Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.1.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Doc ID 7516 Rev 8 3/186 Contents ST7263Bxx 11.3 11.4 11.5 11.6 4/186 11.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.2.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.2.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.3.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.3.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.3.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.3.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 USB interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.4.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.4.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.6.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 11.6.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Doc ID 7516 Rev 8 ST7263Bxx 12 Contents Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.1 12.2 13 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 12.1.2 Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.3.1 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 141 13.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.6.1 13.7 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 147 13.7.2 Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 148 13.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13.10 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 158 13.10.1 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 13.10.2 SCI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.10.3 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Doc ID 7516 Rev 8 5/186 Contents ST7263Bxx 13.11 8-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14 15 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.3 Soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Device configuration and ordering information . . . . . . . . . . . . . . . . . 172 15.1 Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.2 Device ordering information and transfer of customer code . . . . . . . . . . 173 15.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15.4 16 17 6/186 15.3.1 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.3.4 Order codes for ST7263Bx development tools . . . . . . . . . . . . . . . . . . 175 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.1 PA2 limitation with OCMP1 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.2 Unexpected RESET fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.3 USB behavior with LVD disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.4 I2C multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.5 Halt mode power consumption with ADC on . . . . . . . . . . . . . . . . . . . . . 182 16.6 SCI wrong BREAK duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Doc ID 7516 Rev 8 ST7263Bxx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device pin description (QFN40, LQFP48, SO34 and SDIP32). . . . . . . . . . . . . . . . . . . . . . 17 Device pin description (SO24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Interrupt vector map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Hardware register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Recommended Values for 24 MHz crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 I/O pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Port A0, A3, A4, A5, A6, A7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PA1, PA2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Port B description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Port C description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Port D description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I/O ports register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Watchdog timing (fCPU = 8 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 IC/R register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 OC/R register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Clock Control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Prescaling factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 TR dividing factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 RR dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 TP bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 STAT_TX bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 STAT_RX bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Slave Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Master Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 I²C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Doc ID 7516 Rev 8 7/186 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 57. Table 56. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. 8/186 ST7263Bxx Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Instructions supporting Direct, Indexed, Indirect and Indirect Indexed addressing modes133 Instructions supporting relative addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Operating conditions with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Dual voltage Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 USB DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 USB low-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 SCI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 SCL frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 8-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 ADC accuracy with VDD=5 V, fCPU= 8 MHz, fADC=4 MHz, RAIN< 10 κΩ. . . . . . . . . . . . .163 32-pin plastic dual in-line package, shrink 400-mil width, package mechanical data . . . . 166 34-pin plastic small outline package, 300-mil width, package mechanical data . . . . . . . . 167 24-pin plastic small outline package, 300-mil width package mechanical data . . . . . . . . 168 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 40-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . 170 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Supported order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Development tool order codes for the ST7263Bx family . . . . . . . . . . . . . . . . . . . . . . . . . 175 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Doc ID 7516 Rev 8 ST7263Bxx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 48-pin LQFP pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 40-lead QFN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 34-pin SO package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 32-pin SDIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 24-pin SO package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Low voltage detector functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Low Voltage Reset signal output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Temporization timing diagram after an internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 External clock source connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Crystal/ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Clock block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 PA0, PA3, PA4, PA5, PA6, PA7 and PD[7:4] configuration . . . . . . . . . . . . . . . . . . . . . . . . 45 PA1, PA2 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Port B and D[3:0] configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Port C configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 16-bit read sequence (from either the Counter register or the Alternate Counter register) 61 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Input Capture block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Input Capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Output Compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Output Compare timing diagram, ftimer = fcpu/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Output Compare timing diagram, ftimeR = fCPU/4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 One Pulse mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 One Pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Pulse Width modulation mode timing with 2 output Compare functions . . . . . . . . . . . . . . . 70 Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 USB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DMA buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 I²C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 I²C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Doc ID 7516 Rev 8 9/186 List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. 10/186 ST7263Bxx Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 ADC conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 fCPU maximum operating frequency versus VDD supply voltage . . . . . . . . . . . . . . . . . . . 141 Typ. IDD in Run at fCPU = 4 and 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Typ. IDD in Wait at fCPU= 4 and 8 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Typical application with a crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Two typical applications with VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Typ. IPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Typ. RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 VOL standard VDD=5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 VOL high sink VDD=5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 VOL very high sink VDD=5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 VOL standard vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 VOL high sink vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 VOL very high sink vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 |VDD-VOH| @ VDD=5 V (low current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 |VDD-VOH| @ VDD=5 V (high current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 |VDD-VOH| @ IIO=2 mA (low current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 |VDD-VOH| @ IIO=10 mA (high current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 USB data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 32-pin plastic dual in-line package, shrink 400-mil width, package outline. . . . . . . . . . . . 166 34-pin plastic small outline package, 300-mil width, package outline. . . . . . . . . . . . . . . . 167 24-pin plastic small outline package, 300-mil width package outline . . . . . . . . . . . . . . . . 168 48-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 40-lead very thin fine pitch quad flat no-lead package outline . . . . . . . . . . . . . . . . . . . . . 170 Option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Identifying silicon revision from device marking and box label . . . . . . . . . . . . . . . . . . . . . 183 Doc ID 7516 Rev 8 ST7263Bxx 1 Introduction Introduction The ST7263B microcontrollers form a sub-family of the ST7 MCUs dedicated to USB applications. The devices are based on an industry-standard 8-bit core and feature an enhanced instruction set. They operate at a 24 MHz or 12 MHz oscillator frequency. Under software control, the ST7263B MCUs may be placed in either Wait or Halt modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8-bit data management, the ST7263B MCUs feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. The devices include an ST7 core, up to 32 Kbytes of program memory, up to 1024 bytes of RAM, 27 I/O lines and the following on-chip peripherals: ● USB low speed interface with 3 endpoints with programmable in/out configuration using the DMA architecture with embedded 3.3 V voltage regulator and transceivers (no external components are needed). ● 8-bit analog-to-digital converter (ADC) with 12 multiplexed analog inputs ● Industry standard asynchronous SCI serial interface ● Watchdog ● 16-bit Timer featuring an External clock input, 2 input Captures, 2 output Compares with Pulse Generator capabilities ● Fast I²C multimaster interface ● Low voltage reset (LVD) ensuring proper power-on or power-off of the device The ST72F63B devices are Flash versions. They support programming in IAP mode (Inapplication programming) via the on-chip USB interface. Table 2. Device overview Features Program memory Kbytes (Flash / ROM) RAM (stack) bytes ST7263BHx 32 16 ST7263BDx 8 1024 512 384 (128) (128) (128) 32 32 1024 (128) Standard Peripherals 1024 512 (128 (128) 4 384 (128) 32 16 8 4 384 1024 512 384 384 (128 (128) (128) (128) (128) SCI, ADC AD 27 (10) SCI, I²C 19 (10) 14 (6) 4.0 V to 5.5 V 8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator) Operating temp. Packages 8 SCI, I²C, ADC Operating Supply CPU frequency 16 ST7263BEx Watchdog timer, 16-bit timer, USB Other Peripherals I/Os (high current) ST7263BKx 0 °C to +70 °C LQFP48 (7x7) QFN40 (6x6) SDIP32/ SO34 QFN40 (6x6) Doc ID 7516 Rev 8 SDIP32/ SO34 SO24 11/186 Introduction Figure 1. ST7263Bxx General block diagram INTERNAL CLOCK OSC/3 OSCIN OSCOUT OSCILLATOR I²C OSC/4 or OSC/2 for USB2) VDD VSS PORT A POWER SUPPLY PA[7:0] (8 bits) 16-BIT TIMER WATCHDOG CONTROL 8-BIT CORE ALU LVD USB DMA ADDRESS AND DATA BUS RESET PORT B ADC(1) PORT D VDDA PROGRAM MEMORY (32K Bytes) (UART) USB SIE VSSA RAM (1024 Bytes) PD[7:0] (8 bits) PORT C SCI VPP/TEST PB[7:0] (8 bits) PC[2:0] (3 bits) USBDP USBDM USBVCC 1. ADC channels: 12 on 48-pin devices (Port B and Port D[3:0]) 8 on 34 and 32-pin devices (Port B) None on 24-pin devices 2. 12 or 24 MHz OSCIN frequency required to generate 6 MHz USB clock. 3. The drive from USBVCC is sufficient to only drive an external pull-up in addition to the internal transceiver. 12/186 Doc ID 7516 Rev 8 ST7263Bxx Pin description 2 Pin description 2.1 RESET signal (bidirectional) It is active low and forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog is triggered or the VDD is low. It can be used to reset external peripherals. Note: Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected to VDD and VSS) will significantly improve product electromagnetic susceptibility performance. 2.2 OSCIN/OSCOUT: input/output oscillator pin These pins connect a parallel-resonant crystal, or an external source, to the on-chip oscillator. 2.3 VDD/VSS Main power supply and ground voltages Note: To enhance the reliability of operation, it is recommended that VDDA and VDD be connected together on the application board. This also applies to VSSA and VSS. 2.4 VDDA/VSSA Power supply and ground voltages for analog peripherals. Note: To enhance the reliability of operation, it is recommended that VDDA and VDD be connected together on the application board. This also applies to VSSA and VSS. 2.5 Alternate functions Several pins of the I/O ports assume software programmable alternate functions as shown in the pin description. Note: 1 The USBOE alternate function is mapped on Port C2 in 32/34/48 pin devices. In SO24 devices it is mapped on Port B1. 2 The timer OCMP1 alternate function is mapped on Port A6 in 32/34/48 pin devices. In SO24 devices it is not available. Doc ID 7516 Rev 8 13/186 Pin description 48-pin LQFP pinout PA0/MCO PA1(25mA)/SDA/ICCD PD7 PD6 PD5 PD4 PD3/AIN11 PD2/AIN10 PD1/AIN9 PD0/AIN8 PA2(25mA)/SCL/ICCC NC Figure 2. ST7263Bxx 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 TDO/PC1 RDI/PC0 RESET NC NC NC NC NC NC NC AIN7/IT8/PB7(10mA) AIN6/IT7/PB6(10mA) VSSA USBDP USBDM USBVCC VDDA VDD OSCOUT OSCIN VSS USBOE/PC2 NC NC 14/186 Doc ID 7516 Rev 8 PA3/EXTCLK PA4/ICAP1/IT1 PA5/ICAP2/IT2 PA6/OCMP1/IT3 PA7/OCMP2/IT4 PB0(10mA)/AIN0 PB1(10mA)/AIN1 PB2(10mA)/AIN2 PB3(10mA)/AIN3 PB4(10mA)/AIN4/IT5 PB5(10mA)/AIN5/IT6 VPP/TEST ST7263Bxx Pin description 40-lead QFN package pinout PA1(25mA)/SDA/ICCD PD71) PD61) PD51) PD41) PD31)/AIN11 PD21)/AIN10 PD11)/AIN9 PD01)/AIN8 PA2(25mA)/SCL/ICCC Figure 3. 40 39 38 37 36 35 34 33 32 31 1 30 2 29 3 28 4 27 5 26 6 25 7 24 8 23 9 22 10 21 13 14 15 16 17 18 19 PA3/EXTCLK PA4/ICAP1/IT1 PA5/ICAP2/IT2 PA6/OCMP1/IT3 PA7/OCMP2/IT4 PB0(10mA)/AIN0 PB1(10mA)/AIN1 PB2(10mA)/AIN2 PB3(10mA)/AIN3 PB4(10mA)/AIN4/IT5 20 IT8/AIN7/PB7(10mA) IT7/AIN6/PB6(10mA) VPP/TEST IT6/AIN5/PB5(10mA) 12 NC NC USBOE/PC2 11 TDO/PC1 RDI/PC0 RESET PA0/MCO VSSA USBDP USBDM USBVCC VDDA VDD OSCOUT OSCIN VSS 1. Port D functions are not available on the 8 Kbyte version of the QFN40 package (ST7263BK2) and should not be connected. Doc ID 7516 Rev 8 15/186 Pin description Figure 4. ST7263Bxx 34-pin SO package pinout VDD OSCOUT OSCIN VSS PC2/USBOE PC1/TDO PC0/RDI RESET NC AIN7/IT8/PB7(10mA) AIN6/PB6/IT7(10mA) VPP/TEST AIN5/IT6/PB5(10mA) AIN4/IT5/PB4(10mA) AIN3/PB3(10mA) AIN2/PB2(10mA) AIN1/PB1(10mA) Figure 5. 34 2 33 3 32 4 31 5 30 6 29 7 28 8 27 9 26 10 25 11 24 12 23 13 22 14 21 15 20 16 19 17 18 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 USBDP VSSA PA0/MCO PA1(25mA)/SDA/ICCDATA NC NC NC PA2(25mA)/SCL/ICCCLK PA3/EXTCLK PA4/ICAP1/IT1 PA5/ICAP2/IT2 PA6/OCMP1/IT3 PA7/OCMP2/IT4 PB0(10mA)/AIN0 VDDA USBVCC USBDM USBDP VSSA PA0/MCO PA1(25mA)/SDA/ICCDATA NC NC PA2(25mA)/SCL/ICCCLK PA3/EXTCLK PA4/ICAP1/IT1 PA5/ICAP2/IT2 PA6/OCMP1/IT3 PA7/OCMP2/IT4 PB0(10mA)/AIN0 24-pin SO package pinout VDD OSCOUT OSCIN VSS TDO/PC1 RDI/PC0 RESET/ IT7/PB6(10mA) VPP/TEST PB3(10mA) PB2(10mA) USBOE/PB1(10mA) 16/186 VDDA USBVCC USBDM 32-pin SDIP package pinout VDD OSCOUT OSCIN VSS PC2/USBOE PC1/TDO PC0/RDI RESET AIN7/IT8/PB7(10mA) AIN6/IT7/PB6(10mA) VPP/TEST AIN5/IT6/PB5(10mA) AIN4/IT5/PB4(10mA) AIN3/PB3(10mA) AIN2/PB2(10mA) AIN1/PB1/(10mA) Figure 6. 1 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 Doc ID 7516 Rev 8 USBVcc USBDM USBDP VSSA PA0/MCO PA1(25mA)/SDA/ICCDATA PA2(25mA)/SCL/ICCCLK PA3/EXTCLK PA4/ICAP1/IT1 PA5/ICAP2/IT2 PA7/OCMP2/IT4 PB0(10mA) ST7263Bxx Pin description Legend / Abbreviations for Table 3 and Table 4: Type: I = input, O = output, S = supply In/Output level:CT = CMOS 0.3VDD/0.7VDD with input trigger Output level: 10 mA = 10mA high sink (Fn N-buffer only) 25 mA = 25 mA very high sink (on N-buffer only) Port and control configuration: ● Input:float = floating, wpu = weak pull-up, int = interrupt, ana = analog ● Output: OD = open drain, PP = push-pull, T = True open drain The RESET configuration of each pin is shown in bold. This configuration is kept as long as the device is under reset state. Table 3. Device pin description (QFN40, LQFP48, SO34 and SDIP32) Level LQFP48 1 1 7 6 VDD S Power supply voltage (4- 5.5 V) 2 2 8 7 OSCOUT O Oscillator output 3 3 9 8 OSCIN I Oscillator input 4 4 10 9 VSS S Digital ground 5 5 11 10 PC2/USBOE I/O CT X X Port C2 USB output Enable 6 6 12 13 PC1/TDO I/O CT X X Port C1 SCI Transmit Data output 7 7 13 14 PC0/RDI I/O CT X X Port C0 SCI Receive Data input 8 8 14 15 RESET I/O X - 9 15 16 NC -- Not connected - - -- Not connected - - - 18 NC -- Not connected - - - 19 NC -- Not connected - - - 20 NC -- Not connected - - - 21 NC -- Not connected - - - 22 NC -- Not connected 16 17 NC PP OD Output ana int wpu Input float Input Pin name Output QFN40 Main function (after reset) SO34 Port /control SDIP32 Type Pin n° X Alternate function Reset 9 10 17 23 PB7/AIN7/IT8 I/O CT 10mA X X X X Port B7 ADC analog input 7 10 11 18 24 PB6/AIN6/IT7 I/O CT 10mA X X X X Port B6 ADC analog input 6 11 12 19 25 VPP/TEST S Programming supply 12 13 20 26 PB5/AIN5/IT6 I/O CT 10mA X X X X Port B5 ADC analog input 5 13 14 21 27 PB4/AIN4/IT5 I/O CT 10mA X X X X Port B4 ADC analog input 4 14 15 22 28 PB3/AIN3 I/O CT 10mA X X X Port B3 ADC analog input 3 Doc ID 7516 Rev 8 17/186 Pin description Device pin description (QFN40, LQFP48, SO34 and SDIP32) (continued) Port /control PP OD Output ana int wpu Input float Output Pin name Type Level LQFP48 QFN40 SO34 SDIP32 Pin n° Input Table 3. ST7263Bxx Main function (after reset) Alternate function 15 16 23 29 PB2/AIN2 I/O CT 10mA X X X Port B2 ADC analog input 2 16 17 24 30 PB1/AIN1 I/O CT 10mA X X X Port B1 ADC analog input 1 17 18 25 31 PB0/AIN0 I/O CT 10mA X X X Port B0 ADC analog input 0 18 19 26 32 PA7/OCMP2/IT4 I/O CT X X X Port A7 Timer output Compare 2 19 20 27 33 PA6/OCMP1/IT3 I/O CT X X X Port A6 Timer output Compare 1 20 21 28 34 PA5/ICAP2/IT2 I/O CT X X X Port A5 Timer input Capture 2 21 22 29 35 PA4/ICAP1/IT1 I/O CT X X X Port A4 Timer input Capture 1 22 23 30 36 PA3/EXTCLK I/O CT X X Port A3 Timer External clock 23 24 31 38 PA2/SCL/ICCCLK I/O CT 25mA X Port A2 I²C serial clock, ICC clock T - 32 39 PD0(1)/AIN8 I/O CT X X X Port D0 ADC analog input 8 - - 33 40 PD1(1)/AIN9 I/O CT X X X Port D1 ADC analog input 9 - - 34 41 PD2(1)/AIN10 I/O CT X X X Port D2 ADC analog input 10 - - 35 42 PD3(1)/AIN11 I/O CT X X X Port D3 ADC analog input 11 - - 36 43 PD4(1) I/O CT X X Port D4 - - 37 44 PD5(1) I/O CT X X Port D5 - - 38 45 PD6(1) I/O CT X X Port D6 - - (1) I/O CT X X Port D7 - 25 - - NC -- Not connected 24 26 - - NC -- Not connected 25 27 - - NC -- Not connected - 39 46 PD7 26 28 40 47 PA1/SDA/ICCDATA I/O CT 25mA X 27 29 1 48 PA0/MCO I/O CT T X X Port A1 I²C serial data, ICC data Port A0 Main clock output 28 30 2 1 VSSA 29 31 3 2 USBDP I/O USB bidirectional data (data +) 30 32 4 3 USBDM I/O USB bidirectional data (data -) 18/186 S Analog ground Doc ID 7516 Rev 8 ST7263Bxx Pin description Device pin description (QFN40, LQFP48, SO34 and SDIP32) (continued) Port /control PP OD Output ana float wpu Input Output Pin name Input Type LQFP48 Level QFN40 SO34 SDIP32 Pin n° int Table 3. Main function (after reset) Alternate function 31 33 5 4 USBVCC(2) O USB power supply 2) 32 34 6 5 VDDA S Analog supply voltage 1. Port D functions are not available on the 8 Kbyte version of the QFN40 package (ST7263BK2) and should not be connected. 2. The drive from USBVcc is sufficient to only drive an external pull-up in addition to the internal transceiver. Device pin description (SO24) Port /control PP OD Output ana int Input float Output SO24 Pin name Input Level Type Pin n° wpu Table 4. Main function (after reset) Alternate function 1 VDD S Power supply voltage (4- 5.5 V) 2 OSCOUT O Oscillator output 3 OSCIN I Oscillator input 4 VSS S Digital ground 5 PC1/TDO I/O 6 PC0/RDI 7 X X Port C1 SCI Transmit Data output I/O CT X X Port C0 SCI Receive Data input RESET I/O X 8 PB6/IT7 I/O CT 10mA 9 VPP/TEST 10 PB3 I/O CT 10mA X X X Port B3 11 PB2 I/O CT 10mA X X X Port B2 12 PB1/USBOE I/O CT 10mA X X X Port B1 13 PB0 I/O CT 10mA X X X Port B0 14 PA7/OCMP2/IT4 I/O CT X X X Port A7 Timer output Compare 2 15 PA5/ICAP2/IT2 I/O CT X X X Port A5 Timer input Capture 2 16 PA4/ICAP1/IT1 I/O CT X X X Port A4 Timer input Capture 1 17 PA3/EXTCLK I/O CT X X Port A3 Timer External clock 18 PA2/SCL/ ICCCLK I/O CT 25mA X T Port A2 I²C serial clock, ICC clock 19 PA1/SDA/ICCDATA I/O CT 25mA X T Port A1 I²C serial data, ICC Data CT X X X X Reset X S Port B6 Programming supply Doc ID 7516 Rev 8 USB output Enable 19/186 Pin description Device pin description (SO24) (continued) CT X PP OD ana int wpu Output Port A0 Alternate function PA0/MCO 21 VSSA 22 USBDP I/O USB bidirectional data (data +) 23 USBDM I/O USB bidirectional data (data -) 24 USBVCC O USB power supply S X Main function (after reset) 20 20/186 I/O Input float Type SO24 Pin name Port /control Output Level Pin n° Input Table 4. ST7263Bxx Main Clock output Analog ground Doc ID 7516 Rev 8 ST7263Bxx 3 Register and memory map Register and memory map As shown in Figure 7, the MCU is capable of addressing 32 Kbytes of memories and I/O registers. The available memory locations consist of up to 1024 bytes of RAM including 64 bytes of register locations, and up to 32K bytes of user program memory in which the upper 32 bytes are reserved for interrupt vectors. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh. The highest address bytes contain the user reset and interrupt vectors. Caution: Memory locations noted “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device. Figure 7. Memory map 0040h 0000h HW registers (See Table 5) 003Fh 0040h 00FFh 0100h RAM (384 / 512 / 1024 Bytes) 16-bit Addressing RAM Reserved 01BF / 023F / 043Fh 7FFFh 8000h 8000h Program memory (4 / 8 / 16 / 32 KBytes) FFFFh Table 5. Stack (128 Bytes) 017Fh 0180h 01BF / 023F / 043Fh 01C0 / 0240 / 0440h FFDFh FFE0h Short Addressing RAM (192 bytes) 32 KBytes C000h 16 KBytes Interrupt & Reset Vectors (See Table 4) E000h 8 KBytes F000h FFDFh 4 KBytes Interrupt vector map Vector address Description Masked Remarks Exit from Halt FFE0h-FFEDh FFEEh-FFEFh FFF0h-FFF1h FFF2h-FFF3h FFF4h-FFF5h FFF6h-FFF7h FFF8h-FFF9h FFFAh-FFFBh FFFCh-FFFDh FFFEh-FFFFh Reserved area USB interrupt vector SCI interrupt vector I²C interrupt vector TIMER interrupt vector IT1 to IT8 interrupt vector USB End Suspend mode interrupt vector Flash start programming interrupt vector TRAP (software) interrupt vector RESET vector I- bit I- bit I- bit I- bit I- bit I- bit I- bit None None Internal interrupt Internal interrupt Internal interrupt Internal interrupt External interrupt External interrupts Internal interrupt CPU interrupt No No No No Yes Yes Yes No Yes Doc ID 7516 Rev 8 21/186 Register and memory map Table 6. Address ST7263Bxx Hardware register memory map Block Register label Register name Reset status Remarks 0000h 0001h Port A PADR PADDR Port A Data register Port A Data Direction register 00h 00h R/W R/W 0002h 0003h Port B PBDR PBDDR Port B Data register Port B Data Direction register 00h 00h R/W R/W 0004h 0005h Port C PCDR PCDDR Port C Data register Port C Data Direction register 1111 x000b 1111 x000b R/W R/W 0006h 0007h Port D PDDR PDDDR Port D Data register Port D Data Direction register 00h 00h R/W R/W 0008h ITC ITIFRE Interrupt register 00h R/W 0009h MISC MISCR Miscellaneous register 00h R/W 000Ah 000Bh ADC ADCDR ADCCSR ADC Data register ADC control Status register 00h 00h Read only R/W 000Ch WDG WDGCR Watchdog Control register 7Fh R/W 000Dh to 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 22/186 Reserved (4 bytes) TIM TCR2 TCR1 TCSR TIC1HR TIC1LR TOC1HR TOC1LR TCHR TCLR TACHR TACLR TIC2HR TIC2LR TOC2HR TOC2LR Timer Control register 2 Timer Control register 1 Timer Control/Status register Timer input Capture High register 1 Timer input Capture Low register 1 Timer output Compare High register 1 Timer output Compare Low register 1 Timer Counter High register Timer Counter Low register Timer Alternate Counter High register Timer Alternate Counter Low register Timer input Capture High register 2 Timer input Capture Low register 2 Timer output Compare High register 2 Timer output Compare Low register 2 00h 00h 00h xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read only Read only R/W R/W Read only R/W Read only R/W Read only Read only R/W R/W SCI SCISR SCIDR SCIBRR SCICR1 SCICR2 SCI Status register SCI Data register SCI Baud Rate register SCI Control register 1 SCI Control register 2 C0h xxh 00h x000 0000b 00h Read only R/W R/W R/W R/W Doc ID 7516 Rev 8 ST7263Bxx Table 6. Address 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h Register and memory map Hardware register memory map (continued) Block USB Register label USBPIDR USBDMAR USBIDR USBISTR USBIMR USBCTLR USBDADDR USBEP0RA USBEP0RB USBEP1RA USBEP1RB USBEP2RA USBEP2RB Register name USB PID register USB DMA address register USB Interrupt/DMA register USB Interrupt Status register USB Interrupt Mask register USB Control register USB Device Address register USB Endpoint 0 register A USB Endpoint 0 register B USB Endpoint 1 register A USB Endpoint 1 register B USB Endpoint 2 register A USB Endpoint 2 register B Reset status Remarks x0h xxh x0h 00h 00h 06h 00h 0000 xxxxb 80h 0000 xxxxb 0000 xxxxb 0000 xxxxb 0000 xxxxb Read only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Flash Control /Status register 00h R/W I²C Data register Reserved I²C (7 Bits) Slave Address register I²C Clock Control register I²C 2nd Status register I²C 1st Status register I²C Control register 00h 00h 00h 00h 00h 00h R/W 0032h to Reserved (5 bytes) 0036h 0032h 0036h Reserved (5 Bytes) 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Flash FCSR Reserved (1 byte) I2CDR I²C I2COAR I2CCCR I2CSR2 I2CSR1 I2CCR Doc ID 7516 Rev 8 R/W R/W Read only Read only R/W 23/186 Flash program memory ST7263Bxx 4 Flash program memory 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming). The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main features ● 4.3 3 Flash programming modes: – Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. – ICP (in-circuit programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. – IAP (in-application programming). In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ● ICT (in-circuit testing) for downloading and executing user application test patterns in RAM ● Readout protection ● Register access security system (RASS) to prevent accidental programming or erasing Structure The Flash memory is organized in sectors and can be used for both code and data storage. Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 7). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 8). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh). Table 7. 24/186 Sectors available in Flash devices Flash size (Kbytes) Available sectors 4 Sector 0 8 Sectors 0,1 >8 Sectors 0,1, 2 Doc ID 7516 Rev 8 ST7263Bxx 4.3.1 Flash program memory Readout protection Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed. Readout protection selection depends on the device type: ● In Flash devices it is enabled and removed through the FMP_R bit in the option byte. ● In ROM devices it is enabled by mask option specified in the Option List. Figure 8. Memory map and sector address 4K 8K 10K 16K 24K 32K 48K 60K 1000h FLASH MEMORY SIZE 3FFFh 7FFFh 9FFFh SECTOR 2 BFFFh D7FFh DFFFh 2 Kbytes 8 Kbytes EFFFh FFFFh 4.4 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes 4 Kbytes 4 Kbytes SECTOR 1 SECTOR 0 ICC interface ICC (In-circuit communication) needs a minimum of four and up to six pins to be connected to the programming tool (see Figure 9). These pins are: ● RESET: device reset ● VSS: device power supply ground ● ICCCLK: ICC output serial clock pin ● ICCDATA: ICC input/output serial data pin ● ICCSEL/VPP: programming voltage ● OSC1(or OSCIN): main clock input for external source (optional) ● VDD: application board power supply (see Figure 9, Note 3) Doc ID 7516 Rev 8 25/186 Flash program memory Figure 9. ST7263Bxx Typical ICC interface PROGRAMMING TOOL ICC CONNECTOR ICC Cable APPLICATION BOARD (See Note 3) ICC CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note 4) 9 7 5 3 1 10 8 6 4 2 APPLICATION RESET SOURCE See Note 2 10kΩ CL1 ICCDATA RESET ST7 ICCCLK See Note 1 ICCSEL/VPP OSC1 OSC2 VDD CL2 VSS APPLICATION POWER SUPPLY APPLICATION I/O 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor 1K or a reset management IC with open drain output and pull-up resistor > 1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multioscillator capability need to have OSC2 grounded in this case. 4.5 ICP (in-circuit programming) To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 9). For more details on the pin locations, refer to the device pinout description. 26/186 Doc ID 7516 Rev 8 ST7263Bxx 4.6 Flash program memory IAP (in-application programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SCI or other type of serial interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.7 Related documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.8 Register description Flash Control/status register (FCSR) This register is reserved for use by programming tool software. It controls the Flash programming and erasing operations. Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Read/write Doc ID 7516 Rev 8 27/186 Central processing unit ST7263Bxx 5 Central processing unit 5.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation. 5.2 5.3 Main features ● 63 basic instructions ● Fast 8-bit by 8-bit multiply ● 17 main addressing modes ● Two 8-bit index registers ● 16-bit stack pointer ● Low power modes ● Maskable hardware interrupts ● Non-maskable software interrupt CPU registers The six CPU registers shown in Figure are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is the LSB) and PCH (program counter high which is the MSB). 28/186 Doc ID 7516 Rev 8 ST7263Bxx Central processing unit Condition Code register (CC) Reset value: 111x1xxx 7 6 5 4 3 2 1 0 1 1 1 H I N Z C Read/write The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 H Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 I Interrupt mask This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Doc ID 7516 Rev 8 29/186 Central processing unit ST7263Bxx Bit 2 N Negative This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 Z Zero This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 C Carry/borrow This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. Stack Pointer (SP) Reset value: 017Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 0 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Read/write The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 10). Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location 30/186 Doc ID 7516 Rev 8 ST7263Bxx Central processing unit pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 10. ● When an interrupt is received, the SP is decremented and the context is pushed on the stack. ● On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. Figure 10. Stack manipulation example CALL Subroutine PUSH Y Interrupt Event POP Y RET or RSP IRET @ 0100h SP SP Y CC A CC A CC A X X X PCH PCH PCH PCL PCL PCL PCH PCH PCH PCH PCH PCL PCL PCL PCL PCL SP @ 017Fh SP SP SP Stack Higher Address = 017Fh Stack Lower Address = 0100h Figure 11. CPU registers 7 0 ACCUMULATOR RESET VALUE = XXh 7 0 X INDEX REGISTER RESET VALUE = XXh 7 0 Y INDEX REGISTER RESET VALUE = XXh 15 PCH 8 7 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 1 1 1 H I N Z C CONDITION CODE REGISTER RESET VALUE = 1 1 1 X 1 X X X 15 8 7 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = undefined value Doc ID 7516 Rev 8 31/186 Reset and clock management ST7263Bxx 6 Reset and clock management 6.1 Reset The Reset procedure is used to provide an orderly software start-up or to exit low power modes. Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an external reset at the RESET pin. A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to be loaded into the PC and with program execution starting from this point. An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator becomes active. Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior. 6.1.1 Low voltage detector (LVD) Low voltage reset circuitry generates a reset when VDD is: ● Below VIT+ when VDD is rising ● Below VIT- when VDD is falling During low voltage reset, the RESET pin is held low, thus permitting the MCU to reset other devices. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly. 6.1.2 Watchdog reset When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset other devices in the same way as the low voltage reset (Figure 12). 6.1.3 External reset The external reset is an active low input signal applied to the RESET pin of the MCU. As shown in Figure 15, the RESET signal must stay low for a minimum of one and a half CPU clock cycles. An internal Schmitt trigger at the RESET pin is provided to improve noise immunity. 32/186 Doc ID 7516 Rev 8 ST7263Bxx Reset and clock management Figure 12. Low voltage detector functional diagram RESET LOW VOLTAGE DETECTOR VDD INTERNAL RESET FROM WATCHDOG RESET Figure 13. Low Voltage Reset signal output VIT+ VIT- VDD RESET 1. Hysteresis (VIT+-VIT-) = Vhys Figure 14. Temporization timing diagram after an internal Reset VDD VIT+ Temporization (4096 CPU clock cycles) Addresses $FFFE Doc ID 7516 Rev 8 33/186 Reset and clock management ST7263Bxx Figure 15. Reset timing diagram tDDR VDD OSCIN tOXOV fCPU FFFE PC RESET WATCHDOG RESET FFFF 4096 CPU CLOCK CYCLES DELAY 1. Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+, VIT- and Vhys 34/186 Doc ID 7516 Rev 8 ST7263Bxx Reset and clock management 6.2 Clock system 6.2.1 General description The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the external oscillator frequency (fOSC), which is divided by 3 (and by 2 or 4 for USB, depending on the external clock used). The internal clock is further divided by 2 by setting the SMS bit in the miscellaneous register. Using the OSC24/12 bit in the option byte, a 12 MHz or a 24 MHz external clock can be used to provide an internal frequency of either 2, 4 or 8 MHz while maintaining a 6 MHz for the USB (refer to Figure 18). The internal clock signal (fCPU) is also routed to the on-chip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%. The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or ceramic resonator in the frequency range specified for fosc. The circuit shown in Figure 17 is recommended when using a crystal, and Table 8 lists the recommended capacitance. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilization time. Table 8. Recommended Values for 24 MHz crystal resonator Recommended capacitance and resistance RSMAX(1) 20 Ω 25 Ω 70 Ω COSCIN 56pF 47pF 22pF COSCOUT 56pF 47pF 22pF RP 1-10 MΩ 1-10 MΩ 1-10 MΩ 1. RSMAX is the equivalent serial resistor of the crystal (see crystal specification). 6.2.2 External clock An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 16. The tOXOV specifications do not apply when using an external clock input. The equivalent specification of the external clock source should be used instead of tOXOV (see Table 62: Control timing characteristics). Figure 16. External clock source connections OSCIN OSCOUT NC EXTERNAL CLOCK Doc ID 7516 Rev 8 35/186 Reset and clock management ST7263Bxx Figure 17. Crystal/ceramic resonator OSCOUT OSCIN RP COSCIN COSCOUT Figure 18. Clock block diagram 0 %2 %3 8, 4 or 2 MHz CPU and peripherals) 1 SMS 1 24 or 12 MHz Crystal %2 %2 %2 0 OSC24/12 36/186 Doc ID 7516 Rev 8 6 MHz (USB) ST7263Bxx 7 Interrupts Interrupts The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in Table 9 and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 19. The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). When an interrupt has to be serviced: ● Normal processing is suspended at the end of the current instruction execution. ● The PC, X, A and CC registers are saved onto the stack. ● The I bit of the CC register is set to prevent additional interrupts. ● The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to Table 9 for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case several interrupts are simultaneously pending, a hardware priority defines which one will be serviced first (see Table 9). Non-maskable software interrupts This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 19. Interrupts and low power mode All interrupts allow the processor to leave the Wait low power mode. Only external and specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to the “Exit from HALT“ column in Table 9). External interrupts The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising edge occurs on this pin. Conversely, the ITl/PAn and ITm/PBn pins (l=3,4; m= 7,8; n=6,7) can generate an interrupt when a falling edge occurs on this pin. Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE register and if the I bit of the CC is reset. Doc ID 7516 Rev 8 37/186 Interrupts ST7263Bxx Peripheral interrupts Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: ● The I bit of the CC register is cleared. ● The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by one of the two following operations: Note: ● Writing “0” to the corresponding bit in the status register. ● Accessing the status register while the flag is set followed by a read or write of an associated register. 1 The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be enabled) will therefore be lost if the clear sequence is executed. 2 All interrupts allow the processor to leave the Wait low power mode. 3 Exit from Halt mode may only be triggered by an external interrupt on one of the ITi ports (PA4-PA7 and PB4-PB7), an end suspend mode interrupt coming from USB peripheral, or a reset. Figure 19. Interrupt processing flowchart FROM RESET BIT I SET N N Y Y FETCH NEXT INSTRUCTION N IRET Y EXECUTE INSTRUCTION STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT 38/186 INTERRUPT Doc ID 7516 Rev 8 ST7263Bxx Table 9. N° Interrupts Interrupt mapping Source block RESET Register label Description Priority order Reset Exit from Halt Vector address yes FFFEh-FFFFh no FFFCh-FFFDh yes FFFAh-FFFBh N/A TRAP Software interrupt FLASH Flash Start Programming interrupt USB Highest Priority End Suspend mode ISTR FFF8h-FFF9h yes 1 ITi 2 TIMER 3 I²C External interrupts ITRFRE FFF6h-FFF7h Timer Peripheral interrupts TIMSR FFF4h-FFF5h I²CSR1 I²C Peripheral interrupts I²CSR2 Lowest Priority FFF2h-FFF3h no 4 SCI SCI Peripheral interrupts SCISR FFF0h-FFF1h 5 USB USB Peripheral interrupts ISTR FFEEh-FFEFh 7.1 Interrupt register (ITRFRE) Address: 0008h Reset value: 0000 0000 (00h) 7 IT8E 0 IT7E IT6E IT5E IT4E IT3E IT2E IT1E Read/write [7:0] TiE (i=1 to 8). Interrupt Enable Control Bits. If an ITiE bit is set, the corresponding interrupt is generated when ● A rising edge occurs on the pin PA4/IT1 or PA5/IT2 or PB4/IT5 or PB5/IT6 ● Or a falling edge occurs on the pin PA6/IT3 or PA7/IT4 or PB6/IT7 or PB7/IT8 No interrupt is generated elsewhere. Note: Analog input must be disabled for interrupts coming from port B. Doc ID 7516 Rev 8 39/186 Power saving modes ST7263Bxx 8 Power saving modes 8.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7. After a Reset, the normal operating mode is selected by default (Run mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 3 (fCPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. 8.2 Halt mode The MCU consumes the least amount of power in Halt mode. The Halt mode is entered by executing the Halt instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. When entering Halt mode, the I bit in the Condition Code register is cleared. Thus, all external interrupts (ITi or USB end suspend mode) are allowed and if an interrupt occurs, the CPU clock becomes active. The MCU can exit Halt mode on reception of either an external interrupt on ITi, an end suspend mode interrupt coming from USB peripheral, or a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. 40/186 Doc ID 7516 Rev 8 ST7263Bxx Power saving modes Figure 20. Halt mode flowchart HALT INSTRUCTION OSCILLATOR PERIPH. CLOCK CPU CLOCK OFF OFF OFF CLEARED I-BIT N RESET N EXTERNAL INTERRUPT* Y Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT ON ON ON SET 4096 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT 1. Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped. 8.3 Slow mode In Slow mode, the oscillator frequency can be divided by 2 as selected by the SMS bit in the Miscellaneous register. The CPU and peripherals are clocked at this lower frequency. Slow mode is used to reduce power consumption, and enables the user to adapt the clock frequency to the available supply voltage. 8.4 Wait mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the “WFI” ST7 software instruction. All peripherals remain active. During Wait mode, the I bit of the CC register is forced to 0 to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. Doc ID 7516 Rev 8 41/186 Power saving modes ST7263Bxx The MCU will remain in Wait mode until a Reset or an interrupt occurs, causing it to wake up. Refer to Figure 21. Related documentation AN 980: ST7 Keypad Decoding Techniques, Implementing Wakeup on Keystroke AN1014: How to Minimize the ST7 Power Consumption AN1605: Using an active RC to wakeup the ST7LITE0 from power saving mode Figure 21. Wait mode flowchart WFI INSTRUCTION OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT ON ON OFF CLEARED N RESET N Y INTERRUPT Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT ON ON ON SET IF RESET 4096 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT 1. Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped. 42/186 Doc ID 7516 Rev 8 ST7263Bxx I/O ports 9 I/O ports 9.1 Introduction The I/O ports offer different functional modes: ● Transfer of data through digital inputs and outputs and for specific pins ● Analog signal input (ADC) ● Alternate signal input/output for the on-chip peripherals ● External interrupt generation An I/O port consists of up to 8 pins. Each pin can be programmed independently as a digital input (with or without interrupt generation) or a digital output. 9.2 Functional description Each port is associated to 2 main registers: ● Data register (DR) ● Data Direction register (DDR) Each I/O pin may be programmed using the corresponding register bits in DDR register: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. Table 10. I/O pin functions DDR Mode 0 Input 1 Output Input modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Note: 1 All the inputs are triggered by a Schmitt trigger. 2 When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output. Interrupt function When an I/O is configured as an input with interrupt, an event on this I/O can generate an external interrupt request to the CPU. The interrupt sensitivity is given independently according to the description mentioned in the ITRFRE interrupt register. Each pin can independently generate an interrupt request. Each external interrupt vector is linked to a dedicated group of I/O port pins (see interrupts section). If more than one input pin is selected simultaneously as an interrupt source, this is logically ORed. For this reason if one of the interrupt pins is tied low, the other ones are masked. Doc ID 7516 Rev 8 43/186 I/O ports ST7263Bxx Output mode The pin is configured in output mode by setting the corresponding DDR register bit (see Table 7). In this mode, writing “0” or “1” to the DR register applies this digital value to the I/O pin through the latch. Therefore, the previously saved value is restored when the DR register is read. Note: The interrupt function is disabled in this mode. Digital alternate function When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin’s state is also digitally readable by addressing the DR register. Note: 1 Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input. 2 When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0). Caution: The alternate function must not be activated as long as the pin is configured as an input with interrupt in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input the I/O must be configured as a floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. Warning: 44/186 The analog input voltage level must be within the limits stated in the absolute maximum ratings. Doc ID 7516 Rev 8 ST7263Bxx 9.3 I/O ports I/O port implementation The hardware implementation on each I/O port depends on the settings in the DDR register and specific feature of the I/O port such as ADC input or true open drain. 9.3.1 Port A Table 11. Port A0, A3, A4, A5, A6, A7 description I/Os PORT A Input(1) Alternate function Output Signal Condition PA0 with pull-up push-pull MCO (Main Clock output) MCO = 1 (MISCR) PA3 with pull-up push-pull Timer EXTCLK CC1 =1 CC0 = 1 (Timer CR2) PA4 with pull-up Timer ICAP1 Push-pull IT1 Schmitt triggered input IT1E = 1 (ITIFRE) Timer ICAP2 PA5 with pull-up Push-pull IT2 Schmitt triggered input IT2E = 1 (ITIFRE) Timer OCMP1 PA6(2) with pull-up Push-pull OC1E = 1 IT3 Schmitt triggered input IT3E = 1 (ITIFRE) Timer OCMP2 PA7 with pull-up Push-pull OC2E = 1 IT4 Schmitt triggered input IT4E = 1 (ITIFRE) 1. Reset state. 2. Not available on SO24 Figure 22. PA0, PA3, PA4, PA5, PA6, PA7 and PD[7:4] configuration ALTERNATE ENABLE ALTERNATE 1 OUTPUT VDD 0 P-BUFFER VDD DR PULL-UP DATA BUS LATCH ALTERNATE ENABLE DDR LATCH PAD DDR SEL N-BUFFER DR SEL ALTERNATE INPUT 1 0 DIODES ALTERNATE ENABLE VSS CMOS SCHMITT TRIGGER Doc ID 7516 Rev 8 45/186 I/O ports Table 12. ST7263Bxx PA1, PA2 description(1) I/O Port A Input1 Alternate function Output Signal Condition PA1 without pull-up Very high current open drain SDA (I²C data) I²C enable PA2 without pull-up Very high current open drain SCL (I²C clock) I²C enable 1. Reset state. Figure 23. PA1, PA2 configuration LATCH DDR LATCH DATA BUS PAD DDR SEL N-BUFFER DR SEL 1 ALTERNATE ENABLE VSS 0 CMOS SCHMITT TRIGGER 46/186 Doc ID 7516 Rev 8 ST7263Bxx I/O ports 9.3.2 Port B Table 13. Port B description I/O Port B PB0 PB1 Input(1) without pull-up without pull-up Alternate function Output push-pull Signal Condition Analog input (ADC) CH[3:0] = 000 (ADCCSR) Analog input (ADC) CH[3:0] = 001 (ADCCSR) USBOE (USB output enable)(2) USBOE =1 (MISCR) push-pull PB2 without pull-up push-pull Analog input (ADC) CH[3:0]= 010 (ADCCSR) PB3 without pull-up push-pull Analog input (ADC) CH[3:0]= 011 (ADCCSR) Analog input (ADC) CH[3:0]= 100 (ADCCSR) PB4 without pull-up push-pull IT5 Schmitt triggered IT5E = 1 (ITIFRE) input Analog input (ADC) PB5 without pull-up CH[3:0]= 101 (ADCCSR) push-pull IT6 Schmitt triggered IT6E = 1 (ITIFRE) input Analog input (ADC) PB6 without pull-up CH[3:0]= 110 (ADCCSR) push-pull IT7 Schmitt triggered IT7E = 1 (ITIFRE) input Analog input (ADC) PB7 without pull-up CH[3:0]= 111 (ADCCSR) push-pull IT8 Schmitt triggered IT8E = 1 (ITIFRE) input 1. Reset State 2. On SO24 only Doc ID 7516 Rev 8 47/186 I/O ports ST7263Bxx Figure 24. Port B and D[3:0] configuration ALTERNATE ENABLE ALTERNATE OUTPUT VDD 1 0 P-BUFFER DR LATCH VDD ALTERNATE ENABLE DDR PAD LATCH DATA BUS COMMON ANALOG RAIL ANALOG ENABLE (ADC) DDR SEL ANALOG SWITCH N-BUFFER DR SEL 1 ALTERNATE ENABLE 0 DIGITAL ENABLE ALTERNATE INPUT 48/186 DIODES Doc ID 7516 Rev 8 VSS ST7263Bxx I/O ports 9.3.3 Port C Table 14. Port C description I/O Port C Alternate function Input(1) Output Signal Condition PC0 with pull-up push-pull RDI (SCI input) PC1 with pull-up push-pull TDO (SCI output) SCI enable PC2(2) with pull-up push-pull USBOE (USB output enable) USBOE =1 (MISCR) 1. Reset state 2. Not available on SO24 Figure 25. Port C configuration ALTERNATE ENABLE VDD ALTERNATE OUTPUT 0 P-BUFFER DR PULL-UP LATCH VDD ALTERNATE ENABLE DATA BUS DDR PAD LATCH DDR SEL N-BUFFER DR SEL 1 DIODES ALTERNATE ENABLE VSS 0 ALTERNATE INPUT CMOS SCHMITT TRIGGER Doc ID 7516 Rev 8 49/186 I/O ports ST7263Bxx 9.3.4 Port D Table 15. Port D description I/O Port D Input(1) Alternate function Output Signal Condition PD0 without pull-up push-pull Analog input (ADC) CH[3:0] = 1000 (ADCCSR) PD1 without pull-up push-pull Analog input (ADC) CH[3:0] = 1001 (ADCCSR) PD2 without pull-up push-pull Analog input (ADC) CH[3:0] = 1010 (ADCCSR) PD3 without pull-up push-pull Analog input (ADC) CH[3:0] = 1011 (ADCCSR) PD4 with pull-up push-pull PD5 with pull-up push-pull PD6 with pull-up push-pull PD7 with pull-up push-pull 1. Reset state 9.3.5 Register description DATA registers (PxDR) Address Port A Data register (PADR): 0000h Port B Data register (PBDR): 0002h Port C Data register (PCDR): 0004h Port D Data register (PDDR): 0006h Reset value Port A: 0000 0000 (00h) Port B: 0000 0000 (00h) Port C: 1111 x000 (FXh) Port D: 0000 0000 (00h) Note: For Port C, unused bits (7-3) are not accessible. The DR register has a specific behavior according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). Note: 50/186 When using open-drain I/Os in output configuration, the value read in DR is the digital value applied to the I/Opin. Doc ID 7516 Rev 8 ST7263Bxx I/O ports . 7 0 D7 D6 D5 D4 D3 D2 D1 D0 Read/write [7:0] D[7:0] Data register 8 bits. Data Direction register (PxDDR) Address Port A Data Direction register (PADDR): 0001h Port B Data Direction register (PBDDR): 0003h Port C Data Direction register (PCDDR): 0005h Port D Data Direction register (PDDDR): 0007h Reset value Port A: 0000 0000 (00h) Port B: 0000 0000 (00h) Port C: 1111 x000 (FXh) Port D: 0000 0000 (00h) Note: For Port C, unused bits (7-3) are not accessible . 7 0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 Read/write [7:0]D D[7:0] Data Direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: input mode 1: output mode Table 16. Address (Hex.) I/O ports register map Register Label 7 6 5 4 3 2 1 0 00 PADR MSB LSB 01 PADDR MSB LSB 02 PBDR MSB LSB 03 PBDDR MSB LSB 04 PCDR MSB LSB 05 PCDDR MSB LSB 06 PDDR MSB LSB 07 PDDDR MSB LSB Doc ID 7516 Rev 8 51/186 I/O ports 9.3.6 ST7263Bxx Related documentation AN1045: S/W implementation of I2C bus master AN1048: Software LCD driver 52/186 Doc ID 7516 Rev 8 ST7263Bxx 10 Miscellaneous register Miscellaneous register Miscellaneous register (MISCR) Address: 0009h Reset value: 0000 0000 (00h) 7 - 0 - - - - SMS USBOE MCO Read/write [7:3] Reserved 2 SMS Slow mode Select. This bit is set by software and only cleared by hardware after a reset. If this bit is set, it enables the use of an internal divide-by-2 clock divider (refer to Figure 18 on page 36). The SMS bit has no effect on the USB frequency. 0: Divide-by-2 disabled and CPU clock frequency is standard 1: Divide-by-2 enabled and CPU clock frequency is halved. 1 USBOE USB enable. If this bit is set, the port PC2 (PB1 on SO24) outputs the USB output enable signal (at “1” when the ST7 USB is transmitting data). Unused bits 7-4 are set. 0 MCO Main Clock Out selection This bit enables the MCO alternate function on the PA0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU on I/O port) Doc ID 7516 Rev 8 53/186 On-chip peripherals ST7263Bxx 11 On-chip peripherals 11.1 Watchdog timer (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared. 11.1.2 11.1.3 Main features ● Programmable free-running counter (64 increments of 49,152 CPU cycles) ● Programmable reset ● Reset (if watchdog activated) when the T6 bit reaches zero ● Optional reset on HALT instruction (configurable by option byte) ● Hardware Watchdog selectable by option byte. Functional description The counter value stored in the CR register (bits T6:T0), is decremented every 49,152 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle by driving low the reset pin for tW(RSTL)out (see Table 72). The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This down counter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 17): 54/186 ● The WDGA bit is set (watchdog enabled) ● The T6 bit is set to prevent generating an immediate reset ● The T5:T0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Figure 26. Watchdog block diagram RESET WATCHDOG CONTROL REGISTER (CR) WDGA T6 T5 T4 T3 T2 T1 T0 7-BIT DOWNCOUNTER CLOCK DIVIDER ÷49152 fCPU a Table 17. Watchdog timing (fCPU = 8 MHz) CR register initial value Note: WDG timeout period (ms) Max FFh 393.216 Min C0h 6.144 Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 11.1.4 Software Watchdog option If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 11.1.5 Hardware Watchdog option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. 11.1.6 Low power modes WAIT instruction No effect on Watchdog. Doc ID 7516 Rev 8 55/186 On-chip peripherals ST7263Bxx HALT instruction If the Watchdog reset on HALT option is selected by option byte, a HALT instruction causes an immediate reset generation if the Watchdog is activated (WDGA bit is set). Using Halt mode with the WDG (option) If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be used when the watchdog is enabled. In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a reset is generated, the WDG is disabled (reset state). Recommendations: 11.1.7 ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. ● For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. ● The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. ● As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wakeup event (reset or external interrupt). Interrupts None. 56/186 Doc ID 7516 Rev 8 ST7263Bxx 11.1.8 On-chip peripherals Register description Control register (CR) Reset value: 0111 1111 (7Fh) 7 0 WDGA T6 T5 T4 T3 T2 T1 T0 Read/write 7 WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled [6:0] T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). Table 18. Watchdog timer register map and reset values Address Register Label (Hex.) 0Ch WDGCR Reset value 7 6 WDGA 0 T6 1 5 T5 1 Doc ID 7516 Rev 8 4 3 2 1 0 T4 1 T3 1 T2 1 T1 1 T0 1 57/186 On-chip peripherals ST7263Bxx 11.2 16-bit timer 11.2.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 11.2.2 Main features ● Programmable prescaler: fCPU divided by 2, 4 or 8 ● Overflow status flag and maskable interrupt ● External clock input (must be at least four times slower than the CPU clock speed) with the choice of active edge ● 1 or 2 output Compare functions each with: ● – 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt 1 or 2 input Capture functions each with: – 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt ● Pulse width modulation mode (PWM) ● One Pulse mode ● Reduced Power mode ● 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 27. Note: 58/186 Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be ‘1’. Doc ID 7516 Rev 8 ST7263Bxx 11.2.3 On-chip peripherals Functional description Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. ● Counter register (CR) Counter High register (CHR) is the most significant byte (MSB). Counter Low register (CLR) is the least significant byte (LSB). ● Alternate Counter register (ACR) Alternate Counter High register (ACHR) is the most significant byte (MSB). Alternate Counter Low register (ACLR) is the least significant byte (LSB). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 24. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency. Doc ID 7516 Rev 8 59/186 On-chip peripherals ST7263Bxx Figure 27. Timer block diagram ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE 8 low 8 8 8 low 8 high 8 low 8 high 8 low high 8 EXEDG high 8-bit buffer low 8 high 16 1/2 1/4 1/8 OUTPUT COMPARE REGISTER 2 OUTPUT COMPARE REGISTER 1 COUNTER REGISTER ALTERNATE COUNTER EXTCLK pin INPUT CAPTURE REGISTER 1 INPUT CAPTURE REGISTER 2 16 REGISTER 16 16 CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT OUTPUT COMPARE CIRCUIT 6 ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 EDGE DETECT CIRCUIT1 ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin LATCH1 OCMP1 pin LATCH2 OCMP2 pin 0 (Control/Status register) CSR ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 OC1E OC2E OPM PWM (Control register 1) CR1 CC1 CC0 IEDG2 EXEDG (Control register 2) CR2 (See note) TIMER INTERRUPT 1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table). 60/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Figure 28. 16-bit read sequence (from either the Counter register or the Alternate Counter register) Beginning of the sequence At t0 Read MS Byte LS Byte is buffered Other instructions Read At t0 +Δt LS Byte Returns the buffered LS Byte value at t0 Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: ● The TOF bit of the SR register is set. ● A timer interrupt is generated if: – TOIE bit of the CR1 register is set and – I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: Note: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by Wait mode. In Halt mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). External clock The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. Doc ID 7516 Rev 8 61/186 On-chip peripherals ST7263Bxx A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. Figure 29. Counter timing diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFD FFFE FFFF 0000 0001 0002 0003 TIMER OVERFLOW FLAG (TOF) 1. The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running. Figure 30. Counter timing diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000 0001 TIMER OVERFLOW FLAG (TOF) 1. The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running. Figure 31. Counter timing diagram, internal clock divided by 8 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000 TIMER OVERFLOW FLAG (TOF) 1. The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running. 62/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Input Capture In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see Figure 32). Table 19. IC/R register ICiR MS Byte LS Byte ICiHR ICiLR ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure To use the input capture function select the following in the CR2 register: 1. Select the timer clock (CC[1:0]) (see Table 24). 2. Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). 3. Select the following in the CR1 register: a) Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin b) Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). When an input capture occurs: ● ICFi bit is set. ● The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 33). ● A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Doc ID 7516 Rev 8 63/186 On-chip peripherals Note: ST7263Bxx 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2 The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3 The two input capture functions can be used together even if the timer also uses the two output compare functions. 4 In One Pulse mode and PWM mode only input Capture 2 can be used. 5 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6 The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh). Figure 32. Input Capture block diagram ICAP1 pin ICAP2 pin (Control register 1) CR1 EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1 ICIE IEDG1 (Status register) SR IC2R register IC1R register ICF1 ICF2 0 16-BIT FREE RUNNING COUNTER CC1 CC0 Figure 33. Input Capture timing diagram TIMER CLOCK FF01 FF02 FF03 ICAPi PIN ICAPi FLAG FF03 ICAPi REGISTER 1. The rising edge is the active edge. 64/186 0 (Control register 2) CR2 16-BIT COUNTER REGISTER 0 Doc ID 7516 Rev 8 IEDG2 ST7263Bxx On-chip peripherals Output Compare In this section, the index, i, may be 1 or 2 because there are two output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the output Compare register and the free running counter, the output compare function: ● Assigns pins with a programmable value if the OCiE bit is set ● Sets a flag in the status register ● Generates an interrupt if enabled Two 16-bit registers output Compare register 1 (OC1R) and output Compare register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. Table 20. OC/R register MS Byte LS Byte OCiHR OCiLR OCiR These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure To use the output compare function, select the following in the CR2 register: 1. Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. 2. Select the timer clock (CC[1:0]) (see Table 24). 3. Select the following in the CR1 register: a) Select the OLVLi bit to applied to the OCMPi pins after the match occurs. b) Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCiR register and CR register: ● OCFi bit is set. ● The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). ● A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula: Δ OCiR = Δt * fCPU PRESC Where: Δt = Output compare period (in seconds) fCPU = CPU clock frequency (in hertz) Doc ID 7516 Rev 8 65/186 On-chip peripherals ST7263Bxx PRESC= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 24) If the timer clock is an external clock, the formula is: Δ OCiR = Δt * fEXT Where: Δt = Output compare period (in seconds) fEXT = External timer clock frequency (in hertz) Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: Note: ● Write to the OCiHR register (further compares are inhibited). ● Read the SR register (first step of the clearance of the OCFi bit, which may be already set). ● Write to the OCiLR register (enables the output compare function and clears the OCFi bit). 1 After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2 If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3 In both internal and external clock modes, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 35 on page 67 for an example with fCPU/2 and Figure 36 on page 67 for an example with fCPU/4). This behavior is the same in OPM or PWM mode. 4 The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5 The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Forced Compare output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. The FOLVLi bits have no effect in both One Pulse mode and PWM mode. 66/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Figure 34. Output Compare block diagram 16 BIT FREE RUNNING COUNTER OC1E OC2E CC1 CC0 (Control register 2) CR2 16-bit (Control register 1) CR1 OUTPUT COMPARE CIRCUIT 16-bit OCIE FOLV2 FOLV1 OLVL2 OLVL1 16-bit Latch 1 Latch 2 OC1R register OCF1 OCF2 0 0 OCMP1 Pin OCMP2 Pin 0 OC2R register (Status register) SR Figure 35. Output Compare timing diagram, ftimer = fcpu/2 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER 2ECF 2ED0 OUTPUT COMPARE REGISTER i (OCRi) 2ED1 2ED2 2ED3 2ED4 2ED3 OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) Figure 36. Output Compare timing diagram, ftimeR = fCPU/4 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER 2ECF 2ED0 OUTPUT COMPARE REGISTER i (OCRi) 2ED1 2ED2 2ED3 2ED4 2ED3 OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) Doc ID 7516 Rev 8 67/186 On-chip peripherals ST7263Bxx One Pulse mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the input Capture1 function and the output Compare1 function. Procedure To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: 3. – Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. – Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then dedicated to the output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 24). Figure 37. One Pulse mode cycle When event occurs on ICAP1 ICR1 = Counter OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R OCMP1 = OLVL1 Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. Clearing the input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps: 68/186 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals The OC1R register value required for a specific timing application can be calculated using the following formula: t * fCPU OCiR Value = -5 PRESC Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC= Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 24) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 38). Note: 1 The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an output Compare interrupt. 2 When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3 If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin. 4 The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5 When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the One Pulse mode. Figure 38. One Pulse mode timing example COUNTER 2ED3 01F8 IC1R 01F8 FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD 2ED3 ICAP1 OCMP1 OLVL2 OLVL1 OLVL2 compare1 1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 Doc ID 7516 Rev 8 69/186 On-chip peripherals ST7263Bxx Figure 39. Pulse Width modulation mode timing with 2 output Compare functions COUNTER 34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 OLVL2 OCMP1 compare2 OLVL1 compare1 34E2 FFFC OLVL2 compare2 1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1 On timers with only one output Compare register, a fixed frequency PWM signal can be generated using the output compare and the counter overflow to define the pulse length. Pulse width modulation mode Pulse width modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses the complete output Compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated. In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1). Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column. 3. Select the following in the CR1 register: 4. 70/186 – Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC1R register. – Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC2R register. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 24). Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Figure 40. Pulse width modulation cycle Pulse Width Modulation cycle When Counter = OC1R OCMP1 = OLVL1 OCMP1 = OLVL2 When Counter = OC2R Counter is reset to FFFCh ICF1 bit is set If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin. The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value = t * fCPU -5 PRESC Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 24) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Signal or pulse period (in seconds) fEXT = External timer clock frequency (in hertz) The output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 39) Note: 1 After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the output Compare interrupt is inhibited. 3 The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4 In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set. 5 When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. Doc ID 7516 Rev 8 71/186 On-chip peripherals 11.2.4 ST7263Bxx Low power modes a Table 21. Low power modes Mode 11.2.5 Description WAIT No effect on 16-bit Timer. Timer interrupts cause the device to exit from Wait mode. HALT 16-bit Timer registers are frozen. In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from Halt mode” capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from Halt mode” capability, the ICFi bit is set, and the counter value present when exiting from Halt mode is captured into the ICiR register. Interrupts The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Table 22. Interrupts Interrupt Event Event flag Input Capture 1 event/Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Output Compare 1 event (not available in PWM mode) OCF1 Enable Control bit Exit from Wait Exit from Halt Yes No ICIE OCIE Output Compare 2 event (not available in PWM mode) OCF2 Timer Overflow event 11.2.6 TOF TOIE Summary of timer modes Table 23. Summary of timer modes Timer Resources Modes Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Input Capture (1 and/or 2) Output Compare (1 and/or 2) Not recommended(1) One Pulse mode No PWM mode Not recommended(3) 1. See note 4 in Section : One Pulse mode. 2. See note 5 in Section : One Pulse mode. 3. See note 4 in Section : Pulse width modulation mode. 72/186 Doc ID 7516 Rev 8 Partially(2) No No ST7263Bxx 11.2.7 On-chip peripherals Register description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. Control register 1 (CR1) Reset value: 0000 0000 (00h) 7 ICIE 0 OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 Read/write 7 ICIE input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. 6 OCIE output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. 5 TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. 4 FOLV2 Forced output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1:Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. 3 FOLV1 Forced output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. 2 OLVL2 output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode. 1 IEDG1 input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. 0 OLVL1 output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. Doc ID 7516 Rev 8 73/186 On-chip peripherals ST7263Bxx Control register 2 (CR2) Reset value: 0000 0000 (00h) 7 OC1E 0 OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Read/write 7 OC1E output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. 6 OC2E output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in output Compare mode). Whatever the value of the OC2E bit, the output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. 5 OPM One Pulse mode. 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register. 4 PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. [3:2] 74/186 CC[1:0] Clock Control. The timer clock mode depends on these bits (see Table 24). If the external clock pin is not available, programming the external clock configuration stops the counter. 1 IEDG2 input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. 0 EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register. Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Table 24. Clock Control bits Timer clock CC1 fCPU / 4 CC0 0 0 fCPU / 2 1 fCPU / 8 0 1 External Clock (where available) 1 Control/status register (CSR) Reset value: xxxx x0xx (xxh) 7 6 5 4 3 ICF1 OCF1 TOF ICF2 OCF2 Read only 0 TIMD 0 0 Read/write 7 ICF1 input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. 6 OCF1 output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. 5 TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1:The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. 4 ICF2 input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Doc ID 7516 Rev 8 75/186 On-chip peripherals ST7263Bxx 3 OCF2 output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. 2 TIMD Timer disable. This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: Timer enabled 1: Timer prescaler, counter and outputs disabled [1:0] Reserved, must be kept cleared. Input Capture 1 High register (IC1HR) Reset value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). 7 0 MSB LSB Read only Input Capture 1 Low register (IC1LR) Reset value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). 7 0 MSB LSB Read only Output Compare 1 High register (OC1HR) Reset value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 0 MSB LSB Read/write Output Compare 1 Low register (OC1LR) Reset value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. 76/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals 7 0 MSB LSB Read/write Output Compare 2 High register (OC2HR) Reset value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 0 MSB LSB Read/write Output Compare 2 Low register (OC2LR) Reset value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. 7 0 MSB LSB Read/write Counter High register (CHR) Reset value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. 7 0 MSB LSB Read only Counter Low register (CLR) Reset value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit. 7 0 MSB LSB Read only Alternate Counter High register (ACHR) Reset value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. Doc ID 7516 Rev 8 77/186 On-chip peripherals ST7263Bxx 7 0 MSB LSB Read only Alternate Counter Low register (ACLR) Reset value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register. 7 0 MSB LSB Read only Input Capture 2 High register (IC2HR) Reset value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input Capture 2 event). 7 0 MSB LSB Read only Input Capture 2 Low register (IC2LR) Reset value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input Capture 2 event). 7 0 MSB LSB Read only 78/186 Doc ID 7516 Rev 8 ST7263Bxx Table 25. Address On-chip peripherals 16-bit timer register map and reset values Register label 7 6 5 4 3 2 1 0 11 CR2 Reset value OC1E 0 OC2E 0 OPM 0 PWM 0 CC1 0 CC0 0 IEDG2 0 EXEDG 0 12 CR1 Reset value ICIE 0 OCIE 0 TOIE 0 FOLV2 0 FOLV1 0 OLVL2 0 IEDG1 0 OLVL1 0 13 CSR Reset value ICF1 0 OCF1 0 TOF 0 ICF2 0 OCF2 0 TIMD 0 0 0 0 0 14 IC1HR Reset value MSB LSB 15 IC1LR Reset value MSB LSB 16 OC1HR Reset value MSB 1 0 0 0 0 0 0 LSB 0 17 OC1LR Reset value MSB 0 0 0 0 0 0 0 LSB 0 18 CHR Reset value MSB 1 1 1 1 1 1 1 LSB 1 19 CLR Reset value MSB 1 1 1 1 1 1 0 LSB 0 1A ACHR Reset value MSB 1 1 1 1 1 1 1 LSB 1 1B ACLR Reset value MSB 1 1 1 1 1 1 0 LSB 0 1C IC2HR Reset value MSB LSB 1D IC2LR Reset value MSB LSB 1E OC2HR Reset value MSB 1 0 0 0 0 0 0 LSB 0 1F OC2LR Reset value MSB 0 0 0 0 0 0 0 LSB 0 (Hex.) Doc ID 7516 Rev 8 79/186 On-chip peripherals ST7263Bxx 11.3 Serial communications interface (SCI) 11.3.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems. 11.3.2 Main features ● Full duplex, asynchronous communications ● NRZ standard format (Mark/Space) ● Independently programmable transmit and receive baud rates up to 250K baud. ● Programmable data word length (8 or 9 bits) ● Receive buffer full, Transmit buffer empty and End of Transmission flags ● Two receiver Wakeup modes: – Address bit (MSB) – Idle line ● Muting function for multiprocessor configurations ● Separate enable bits for Transmitter and Receiver ● – – – – Four error detection flags: Overrun error Noise error Frame error Parity error – – – – – – Six interrupt sources with flags: Transmit data register empty Transmission complete Receive data register full Idle line received Overrun error detected Parity error ● 11.3.3 ● Parity control: – Transmits parity bit – Checks parity of received data byte ● Reduced power consumption mode General description The interface is externally connected to another device by two pins (see Figure 42): 80/186 ● TDO: Transmit Data output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level. ● RDI: Receive Data input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Through these pins, serial data is transmitted and received as frames comprising: ● An Idle Line prior to transmission or reception ● A start bit ● A data word (8 or 9 bits) least significant bit first ● A Stop bit indicating that the frame is complete. This interface uses two types of baud rate generator: ● A conventional type for commonly-used baud rates. Figure 41. SCI block diagram Write Read (DATA REGISTER) DR Received Data register (RDR) Transmit Data register (TDR) TDO Received Shift register Transmit Shift register RDI CR1 R8 TRANSMIT WAKE UP CONTROL UNIT T8 SCID M WAKE PCE PS PIE RECEIVER CLOCK RECEIVER CONTROL CR2 SR TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PE SCI INTERRUPT CONTROL TRANSMITTER CLOCK TRANSMITTER RATE fCPU CONTROL /16 /PR BRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 RECEIVER RATE CONTROL BAUD RATE GENERATOR Doc ID 7516 Rev 8 81/186 On-chip peripherals 11.3.4 ST7263Bxx Functional description The block diagram of the Serial Control Interface, is shown in Figure 41 It contains 6 dedicated registers: ● Two control registers (SCICR1 & SCICR2) ● A status register (SCISR) ● A baud rate register (SCIBRR) Refer to the register descriptions in Section 11.3.7 for the definitions of each bit. Serial data format Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 41). The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data. A Break character is interpreted on receiving “0”s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit. Transmission and reception are driven by their own baud rate generator. Figure 42. Word length programming 9-bit Word length (M bit is set) Possible Parity Bit Data Frame Start Bit Bit0 Bit2 Bit1 Bit3 Bit4 Bit5 Bit6 Start Bit Break Frame Extra ’1’ Possible Parity Bit Data Frame 82/186 Bit0 Bit8 Idle Frame 8-bit Word length (M bit is reset) Start Bit Bit7 Next Data Frame Next Stop Start Bit Bit Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Next Data Frame Stop Bit Next Start Bit Idle Frame Start Bit Break Frame Extra Start Bit ’1’ Doc ID 7516 Rev 8 Start Bit ST7263Bxx On-chip peripherals Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 41). Procedure 1. Select the M bit to define the word length. 2. Select the desired baud rate using the SCIBRR and the SCIETPR registers. 3. Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission. 4. Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. Clearing the TDRE bit is always performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register The TDRE bit is set by hardware and it indicates: ● The TDR register is empty. ● The data transfer is beginning. ● The next data can be written in the SCIDR register without overwriting the previous data. This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CC register. When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set. When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CC register. Clearing the TC bit is performed by the following software sequence: Note: 1. An access to the SCISR register 2. A write to the SCIDR register The TDRE and TC bits are cleared by the same software sequence. Break characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 42). Doc ID 7516 Rev 8 83/186 On-chip peripherals ST7263Bxx As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the SCIDR. Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register. Character reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 41). Procedure 1. Select the M bit to define the word length. 2. Select the desired baud rate using the SCIBRR and the SCIERPR registers. 3. Set the RE bit, this enables the receiver which begins searching for a start bit. When a character is received: ● The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. ● An interrupt is generated if the RIE bit is set and the I bit is cleared in the CC register. ● The error flags can be set if a frame error, noise or an overrun error has been detected during reception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SCISR register 2. A read to the SCIDR register. The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break character When a break character is received, the SCI handles it as a framing error. Idle character When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CC register. Overrun error An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the RDR register as long as the RDRF bit is not cleared. 84/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals When a overrun error occurs: ● The OR bit is set. ● The RDR content will not be lost. ● The shift register will be overwritten. ● An interrupt is generated if the RIE bit is set and the I bit is cleared in the CC register. The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation. Noise error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples. When noise is detected in a frame: ● The NF flag is set at the rising edge of the RDRF bit. ● Data is transferred from the Shift register to the SCIDR register. ● No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation. During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid frame is received. Note: If the application Start Bit is not long enough to match the above requirements, then the NF Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the application software when the first valid byte is received. See also Section . Framing error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. – A break is received. When the framing error is detected: – the FE bit is set by hardware – Data is transferred from the Shift register to the SCIDR register. – No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation. Doc ID 7516 Rev 8 85/186 On-chip peripherals ST7263Bxx Baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: Tx = fCPU Rx = (16*PR)*TR fCPU (16*PR)*RR with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCIBRR register. Example: If fCPU is 8 MHz (normal mode) and if PR=13 and TR=RR=1, the transmit and receive baud rates are 38400 baud. Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled. Receiver muting and Wakeup feature In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers. The non addressed devices may be placed in sleep mode by means of the muting function. Setting the RWU bit by software puts the SCI in sleep mode: All the reception status bits can not be set. All the receive interrupts are inhibited. A muted receiver may be awakened by one of the following two ways: ● By Idle Line detection if the WAKE bit is reset, ● By Address Mark detection if the WAKE bit is set. Receiver wakes-up by Idle Line detection when the Receive line has recognized an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. Receiver wakes-up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word. Caution: 86/186 In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the read operation (RWU=1) and a address mark wake up event occurs (RWU is reset) before the write operation, the RWU bit will be set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode. Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in Table 26. Table 26. Frame formats(1) M bit PCE bit SCI frame 0 0 | SB | 8 bit data | STB | 0 1 | SB | 7-bit data | PB | STB | 1 0 | SB | 9-bit data | STB | 1 1 | SB | 8-bit data PB | STB | 1. SB = Start Bit, STB = Stop Bit, PB = Parity Bit Note: In case of wakeup by an address mark, the MSB bit of the data is taken into account and not the parity bit Even parity: the parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0). Odd parity: the parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1). Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit. Reception mode: If the PCE bit is set then the interface checks if the received data byte has an even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register. SCI clock tolerance During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th samples is considered as the bit value. For a valid bit detection, all the three samples should have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be “1”, but the Noise Flag bit is be set because the three samples values are not the same. Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. Note: The internal sampling clock of the microcontroller samples the pin value on every falling edge. Therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit length is 64µs), then the 8th, 9th and 10th samples will be at 28µs, 32 µs & 36 µs respectively (the first sample starting ideally at 0 µs). But if the falling edge of the internal Doc ID 7516 Rev 8 87/186 On-chip peripherals ST7263Bxx clock occurs just before the pin value changes, the samples would then be out of sync by ~4 µs. This means the entire bit length must be at least 40 µs (36 µs for the 10th sample + 4 µs for synchronization with the internal sampling clock). Clock deviation causes The causes which contribute to the total deviation are: ● DTRA: Deviation due to transmitter error (Local oscillator error of the transmitter or the transmitter is transmitting at a different baud rate). ● DQUANT: Error due to the baud rate quantisation of the receiver. ● DREC: Deviation of the local oscillator of the receiver: This deviation can occur during the reception of one complete SCI message assuming that the deviation has been compensated at the beginning of the message. ● DTCL: Deviation due to the transmission line (generally due to the transceivers) All the deviations of the system should be added and compared to the SCI clock tolerance: DTRA + DQUANT + DREC + DTCL < 3.75% Noise error causes See also description of Noise error in Section . Start bit The noise flag (NF) is set during start bit reception if one of the following conditions occurs: 1. A valid falling edge is not detected. A falling edge is considered to be valid if the 3 consecutive samples before the falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a “1”. 2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a “1”. Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag getting set. Data bits The noise flag (NF) is set during normal data bit reception if the following condition occurs: ● During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. The majority of the 8th, 9th and 10th samples is considered as the bit value. Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the Noise Flag getting set. 88/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Figure 43. Bit sampling in reception mode RDI LINE sampled values Sample clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6/16 7/16 7/16 One bit time 11.3.5 Low power modes Table 27. Low power modes Mode Description No effect on SCI. SCI interrupts cause the device to exit from Wait mode. WAIT SCI registers are frozen. HALT 11.3.6 In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. Interrupts Table 28. Interrupts Interrupt event Event flag Enable Control bit Exit from Wait Exit from Halt Transmit Data register Empty TDRE TIE Yes No Transmission Complete TC TCIE Yes No Received Data Ready to be Read RDRF Yes No Yes No RIE Overrun Error Detected OR Idle Line Detected IDLE ILIE Yes No Parity Error PE PIE Yes No The SCI interrupt events are connected to the same interrupt vector. These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Doc ID 7516 Rev 8 89/186 On-chip peripherals 11.3.7 ST7263Bxx Register description Status register (SCISR) Reset value: 1100 0000 (C0h) 7 TDRE 0 TC RDRF IDLE OR NF FE PE Read only 7 TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Note: Data will not be transferred to the shift register unless the TDRE bit is cleared. 6 TC Transmission complete. This bit is set by hardware when transmission of a frame containing Data is complete. An interrupt is generated if TCIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Transmission is not complete 1: Transmission is complete Note: TC is not set after the transmission of a Preamble or a Break. 5 RDRF Received data ready flag. This bit is set by hardware when the content of the RDR register has been transferred to the SCIDR register. An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: Data is not received 1: Received data is ready to be read 4 IDLE Idle line detect. This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Idle Line is detected 1: Idle Line is detected Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line occurs). 90/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals 3 OR Overrun error. This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Overrun error 1: Overrun error is detected Note: When this bit is set RDR register content will not be lost but the shift register will be overwritten. 2 NF Noise flag. This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No noise is detected 1: Noise is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. 1 FE Framing error. This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Framing error is detected 1: Framing error or break character is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set. 0 PE Parity error. This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An interrupt is generated if PIE=1 in the SCICR1 register. 0: No parity error 1: Parity error Doc ID 7516 Rev 8 91/186 On-chip peripherals ST7263Bxx Control register 1 (SCICR1) Reset value: x000 0000 (x0h) 7 R8 0 T8 SCID M WAKE PCE PS PIE Read/write 7 R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. 6 T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmitted word when M=1. 5 SCID Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled 4 M Word length. This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit Note: The M bit must not be modified during a data transfer (both transmission and reception). 3 WAKE Wakeup method. This bit determines the SCI wakeup method, it is set or cleared by software. 0: Idle Line 1: Address Mark 2 PCE Parity control enable. This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled 1 PS Parity selection. This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity 0 PIE Parity interrupt enable. This bit enables the interrupt capability of the hardware parity control when a parity error is detected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled. 92/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Control register 2 (SCICR2) Reset value: 0000 0000 (00h) 7 TIE 0 TCIE RIE ILIE TE RE RWU SBK Read/write 7 TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE=1 in the SCISR register 6 TCIE Transmission complete interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TC=1 in the SCISR register 5 RIE Receiver interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever OR=1 or RDRF=1 in the SCISR register 4 ILIE Idle line interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1 in the SCISR register. 3 TE Transmitter enable. This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled Note: During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble (idle line) after the current word. When TE is set there is a 1 bit-time delay before the transmission starts. Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set). Doc ID 7516 Rev 8 93/186 On-chip peripherals ST7263Bxx 2 RE Receiver enable. This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit 1 RWU Receiver wakeup. This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wakeup sequence is recognized. 0: Receiver in Active mode 1: Receiver in Mute mode Note: Before selecting Mute mode (setting the RWU bit), the SCI must receive some data first, otherwise it cannot function in Mute mode with wakeup by idle line detection. 0 SBK Send break. This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted 1: Break characters are transmitted Note: If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end of the current word. Data register (SCIDR) Reset value: Undefined This register contains the received or transmitted data character, depending on whether it is read from or written to. 7 DR7 0 DR6 DR5 DR4 DR3 DR2 DR1 DR0 Read/write The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 41). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 41). 94/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Baud Rate register (SCIBRR) Reset value: 0000 0000 (00h) 7 SCP1 0 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 Read/write [7:6] SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges (see Table 29). [5:3] SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock (see Table 30). [2:0] SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock (see Table 31). Table 29. . Table 30. Table 31. Prescaling factors PR prescaling factor SCP1 SCP0 1 0 0 3 0 1 4 1 0 13 1 1 TR dividing factors TR dividing factor SCT2 SCT1 SCT0 1 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 RR dividing factor SCR2 SCR1 SCR0 1 0 0 0 2 0 0 1 4 0 1 0 RR dividing factor Doc ID 7516 Rev 8 95/186 On-chip peripherals Table 31. Table 32. 96/186 ST7263Bxx RR dividing factor RR dividing factor SCR2 SCR1 SCR0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 SCI register map and reset values Address (Hex.) Register label 7 6 5 4 3 2 1 0 20 SCISR Reset value TDRE 1 TC 1 RDRF 0 IDLE 0 OR 0 NF 0 FE 0 PE 0 21 SCIDR Reset value DR7 x DR6 x DR5 x DR4 x DR3 x DR2 x DR1 x DR0 x 22 SCIBRR Reset value SCP1 0 SCP0 0 SCT2 x SCT1 x SCT0 x SCR2 x SCR1 x SCR0 x 23 SCICR1 Reset value R8 x T8 x SCID 0 M x WAKE x PCE 0 PS 0 PIE 0 24 SCICR2 Reset value TIE 0 TCIE 0 RIE 0 ILIE 0 TE 0 RE 0 RWU 0 SBK 0 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals 11.4 USB interface (USB) 11.4.1 Introduction The USB Interface implements a low-speed function interface between the USB and the ST7 microcontroller. It is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and DMA. No external components are needed apart from the external pull-up on USBDM for low speed recognition by the USB host. The use of DMA architecture allows the endpoint definition to be completely flexible. Endpoints can be configured by software as in or out. 11.4.2 11.4.3 Main features ● USB Specification Version 1.1 Compliant ● Supports Low-Speed USB Protocol ● Two or Three Endpoints (including default one) depending on the device (see device feature list and register map) ● CRC generation/checking, NRZI encoding/decoding and bit-stuffing ● USB Suspend/Resume operations ● DMA Data transfers ● On-Chip 3.3 V Regulator ● On-Chip USB Transceiver Functional description The block diagram in Figure 44, gives an overview of the USB interface hardware. For general information on the USB, refer to the “Universal Serial Bus Specifications” document available at http//:www.usb.org. Serial interface engine The SIE (Serial Interface Engine) interfaces with the USB, via the transceiver. The SIE processes tokens, handles data transmission/reception, and handshaking as required by the USB standard. It also performs frame formatting, including CRC generation and checking. Endpoints The Endpoint registers indicate if the microcontroller is ready to transmit/receive, and how many bytes need to be transmitted. DMA When a token for a valid Endpoint is recognized by the USB interface, the related data transfer takes place, using DMA. At the end of the transaction, an interrupt is generated. Interrupts By reading the Interrupt Status register, application software can know which USB event has occurred. Doc ID 7516 Rev 8 97/186 On-chip peripherals ST7263Bxx Figure 44. USB block diagram 6 MHz ENDPOINT CPU REGISTERS USBDM Transceiver SIE Address, DMA USBDP data buses and interrupts USBVCC 3.3 V Voltage Regulator INTERRUPT REGISTERS MEMORY USBGND 11.4.4 Register description DMA Address register (DMAR) Reset value: undefined 7 DA15 0 DA14 DA13 DA12 DA11 DA10 DA9 DA8 Read.write [7:0] DA[15:8] DMA address bits 15-8. Software must write the start address of the DMA memory area whose most significant bits are given by DA15-DA6. The remaining 6 address bits are set by hardware. See the description of the IDR register and Figure 45. 98/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Interrupt/DMA register (IDR) Reset value: xxxx 0000 (x0h) 7 DA7 0 DA6 EP1 EP0 CNT3 CNT2 CNT1 CNT0 Read.write [7:6] DA[7:6] DMA address bits 7-6. Software must reset these bits. See the description of the DMAR register and Figure 45. [5:4] EP[1:0] Endpoint number (read-only). These bits identify the endpoint which required attention. 00: Endpoint 0 01: Endpoint 1 10: Endpoint 2 When a CTR interrupt occurs (see register ISTR) the software should read the EP bits to identify the endpoint which has sent or received a packet. [3:0] CNT[3:0] Byte count (read only). This field shows how many data bytes have been received during the last data reception. Note: Not valid for data transmission. Figure 45. DMA buffers 101111 Endpoint 2 TX 101000 100111 Endpoint 2 RX 100000 011111 011000 010111 010000 001111 Endpoint 1 TX Endpoint 1 RX Endpoint 0 TX 001000 000111 Endpoint 0 RX DA15-6,000000 000000 Doc ID 7516 Rev 8 99/186 On-chip peripherals ST7263Bxx PID register (PIDR) Reset value: xx00 0000 (x0h) 7 0 TP3 TP2 0 0 0 RX_ SEZ RXD 0 Read only [7:6] TP[3:2] Token PID bits 3 & 2. USB token PIDs are encoded in four bits. TP[3:2] correspond to the variable token PID bits 3 & 2. : PID bits 1 & 0 have a fixed value of 01. Note: When a CTR interrupt occurs (see register ISTR) the software should read the TP3 and TP2 bits to retrieve the PID name of the token received. The USB standard defines TP bits (see Table 33). [5:3] Reserved. Forced by hardware to 0. 2 RX_SEZ Received single-ended zero This bit indicates the status of the RX_SEZ transceiver output. 0: No SE0 (single-ended zero) state 1: USB lines are in SE0 (single-ended zero) state 1 RXD Received data 0: No K-state 1: USB lines are in K-state This bit indicates the status of the RXD transceiver output (differential receiver output). If the environment is noisy, the RX_SEZ and RXD bits can be used to secure the application. By interpreting the status, software can distinguish a valid End Suspend event from a spurious wakeup due to noise on the external USB line. A valid End Suspend is followed by a Resume or Reset sequence. A Resume is indicated by RXD=1, a Reset is indicated by RX_SEZ=1. 0 Reserved. Forced by hardware to 0. Table 33. 100/186 TP bit definition TP3 TP2 PID Name 0 0 OUT 1 0 IN 1 1 SETUP Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Interrupt Status register (ISTR) Reset value: 0000 0000 (00h) 7 SUSP 0 DOVR CTR ERR IOVR ESUSP RESET SOF Read.write When an interrupt occurs these bits are set by hardware. Software must read them to determine the interrupt type and clear them after servicing. Note: These bits cannot be set by software. 7 SUSP Suspend mode request. This bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the USB bus. The suspend request check is active immediately after each USB reset event and its disabled by hardware when suspend mode is forced (FSUSP bit of CTLR register) until the end of resume sequence. 6 DOVR DMA over/underrun. This bit is set by hardware if the ST7 processor can’t answer a DMA request in time. 0: No over/underrun detected 1: Over/underrun detected 5 CTR Correct Transfer. This bit is set by hardware when a correct transfer operation is performed. The type of transfer can be determined by looking at bits TP3-TP2 in register PIDR. The Endpoint on which the transfer was made is identified by bits EP1-EP0 in register IDR. 0: No Correct Transfer detected 1: Correct Transfer detected Note: A transfer where the device sent a NAK or STALL handshake is considered not correct (the host only sends ACK handshakes). A transfer is considered correct if there are no errors in the PID and CRC fields, if the DATA0/DATA1 PID is sent as expected, if there were no data overruns, bit stuffing or framing errors. 4 ERR Error. This bit is set by hardware whenever one of the errors listed below has occurred: 0: No error detected 1: Timeout, CRC, bit stuffing or nonstandard framing error detected 3 IOVR Interrupt overrun. This bit is set when hardware tries to set ERR, or SOF before they have been cleared by software. 0: No overrun detected 1: Overrun detected Doc ID 7516 Rev 8 101/186 On-chip peripherals ST7263Bxx 2 ESUSP End suspend mode. This bit is set by hardware when, during suspend mode, activity is detected that wakes the USB interface up from suspend mode. This interrupt is serviced by a specific vector, in order to wake up the ST7 from Halt mode. 0: No End Suspend detected 1: End Suspend detected 1 RESET USB reset. This bit is set by hardware when the USB reset sequence is detected on the bus. 0: No USB reset signal detected 1: USB reset signal detected Note: The DADDR, EP0RA, EP0RB, EP1RA, EP1RB, EP2RA and EP2RB registers are reset by a USB reset. 0 SOF Start of frame. This bit is set by hardware when a low-speed SOF indication (keep-alive strobe) is seen on the USB bus. It is also issued at the end of a resume sequence. 0: No SOF signal detected 1: SOF signal detected Note: To avoid spurious clearing of some bits, it is recommended to clear them using a load instruction where all bits which must not be altered are set, and all bits to be cleared are reset. Avoid read-modify-write instructions like AND, XOR. Interrupt Mask register (IMR) These bits are mask bits for all interrupt condition bits included in the ISTR. Whenever one of the IMR bits is set, if the corresponding ISTR bit is set, and the I bit in the CC register is cleared, an interrupt request is generated. For an explanation of each bit, please refer to the corresponding bit description in ISTR. Reset value: 0000 0000 (00h) 7 SUSPM 0 DOVRM CTRM ERRM IOVRM Read.write 102/186 Doc ID 7516 Rev 8 ESUSPM RESETM SOFM ST7263Bxx On-chip peripherals Control register (CTLR) Reset value: 0000 0110 (06h) 7 0 0 0 0 0 RESUME PDWN FSUSP FRES Read/write [7:4] Reserved. Forced by hardware to 0. 3 RESUME Resume. This bit is set by software to wakeup the Host when the ST7 is in suspend mode. 0: Resume signal not forced 1: Resume signal forced on the USB bus. Software should clear this bit after the appropriate delay. 2 PDWN Power down. This bit is set by software to turn off the 3.3 V on-chip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: Voltage regulator on 1: Voltage regulator off Note: After turning on the voltage regulator, software should allow at least 3 µs for stabilization of the power supply before using the USB interface. 1 FSUSP Force suspend mode. This bit is set by software to enter Suspend mode. The ST7 should also be halted allowing at least 600 ns before issuing the HALT instruction. 0: Suspend mode inactive 1: Suspend mode active When the hardware detects USB activity, it resets this bit (it can also be reset by software). 0 FRES Force reset. This bit is set by software to force a reset of the USB interface, just as if a RESET sequence came from the USB. 0: Reset not forced 1: USB interface reset forced. The USB is held in RESET state until software clears this bit, at which point a “USBRESET” interrupt will be generated if enabled. Device Address register (DADDR) Reset value: 0000 0000 (00h) 7 0 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Read.write 7 Reserved. Forced by hardware to 0. [6:0] ADD[6:0] Device address, 7 bits. Software must write into this register the address sent by the host during enumeration. Note: This register is also reset when a USB reset is received from the USB bus or forced through bit FRES in the CTLR register. Doc ID 7516 Rev 8 103/186 On-chip peripherals ST7263Bxx Endpoint n register A (EPnRA) These registers (EP0RA, EP1RA and EP2RA) are used for controlling data transmission. They are also reset by the USB bus reset. Note: Endpoint 2 and the EP2RA register are not available on some devices (see device feature list and register map). Reset value: 0000 xxxx (0xh) 7 0 ST_ OUT DTOG _TX STAT _TX1 STAT _TX0 TBC3 TBC2 TBC1 TBC0 Read.write 7 ST_OUT Status out. This bit is set by software to indicate that a status out packet is expected: in this case, all nonzero OUT data transfers on the endpoint are STALLed instead of being ACKed. When ST_OUT is reset, OUT transactions can have any number of bytes, as needed. 6 DTOG_TX Data Toggle, for transmission transfers. It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next transmitted data packet. This bit is set by hardware at the reception of a SETUP PID. DTOG_TX toggles only when the transmitter has received the ACK signal from the USB host. DTOG_TX and also DTOG_RX (see EPnRB) are normally updated by hardware, at the receipt of a relevant PID. They can be also written by software. [5:4] STAT_TX[1:0] Status bits, for transmission transfers. These bits contain the information about the endpoint status, which are listed in Table 34. These bits are written by software. Hardware sets the STAT_TX bits to NAK when a correct transfer has occurred (CTR=1) related to a IN or SETUP transaction addressed to this endpoint; this allows the software to prepare the next set of data to be transmitted. [3:0] TBC[3:0] Transmit byte count for Endpoint n. Before transmission, after filling the transmit buffer, software must write in the TBC field the transmit packet size expressed in bytes (in the range 0-8). Caution: Any value outside the range 0-8 willinduce undesired effects (such as continuous data transmission). Table 34. 104/186 STAT_TX bit definition STAT_TX1 STAT_TX0 Meaning 0 0 DISABLED: transmission transfers cannot be executed. 0 1 STALL: the endpoint is stalled and all transmission requests result in a STALL handshake. 1 0 NAK: the endpoint is naked and all transmission requests result in a NAK handshake. 1 1 VALID: this endpoint is enabled for transmission. Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Endpoint n register B (EPnRB) These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1 and 2. They are also reset by the USB bus reset. Note: Endpoint 2 and the EP2RB register are not available on some devices (see device feature list and register map). Reset value: 0000 xxxx (0xh) 7 0 DTOG _RX CTRL STAT _RX1 STAT _RX0 EA3 EA2 EA1 EA0 Read.write 7 CTRL Control. This bit should be 0. Note: If this bit is 1, the Endpoint is a control endpoint. (Endpoint 0 is always a control Endpoint, but it is possible to have more than one control Endpoint). 6 DTOG_RX Data toggle, for reception transfers. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. This bit is cleared by hardware in the first stage (Setup Stage) of a control transfer (SETUP transactions start always with DATA0 PID). The receiver toggles DTOG_RX only if it receives a correct data packet and the packet’s data PID matches the receiver sequence bit. [5:4] STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the endpoint status, which are listed in Table 35. These bits are written by software. Hardware sets the STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) related to an OUT or SETUP transaction addressed to this endpoint, so the software has the time to elaborate the received data before acknowledging a new transaction. [3:0] EA[3:0] Endpoint address. Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. Usually EP1RB contains “0001” and EP2RB contains “0010”. Table 35. STAT_RX bit definition STAT_RX1 STAT_RX0 Meaning 0 0 DISABLED: reception transfers cannot be executed. 0 1 STALL: the endpoint is stalled and all reception requests result in a STALL handshake. 1 0 NAK: the endpoint is naked and all reception requests result in a NAK handshake. 1 1 VALID: this endpoint is enabled for reception. Doc ID 7516 Rev 8 105/186 On-chip peripherals ST7263Bxx Endpoint 0 register B (EP0RB) This register is used for controlling data reception on Endpoint 0. It is also reset by the USB bus reset. Reset value: 1000 0000 (80h) 7 1 0 DTOG RX STAT RX1 STAT RX0 0 0 0 0 Read.write 7 Forced by hardware to 1. [6:4] Refer to the EPnRB register for a description of these bits. [3:0] Forced by hardware to 0. 11.4.5 Programming considerations The interaction between the USB interface and the application program is described below. Apart from system reset, action is always initiated by the USB interface, driven by one of the USB events associated with the Interrupt Status register (ISTR) bits. Initializing the registers At system reset, the software must initialize all registers to enable the USB interface to properly generate interrupts and DMA requests. 1. Initialize the DMAR, IDR, and IMR registers (choice of enabled interrupts, address of DMA buffers). Refer the paragraph titled initializing the DMA Buffers. 2. Initialize the EP0RA and EP0RB registers to enable accesses to address 0 and endpoint 0 to support USB enumeration. Refer to the paragraph titled Endpoint Initialization. 3. When addresses are received through this channel, update the content of the DADDR. 4. If needed, write the endpoint numbers in the EA fields in the EP1RB and EP2RB register. Initializing DMA buffers The DMA buffers are a contiguous zone of memory whose maximum size is 48 bytes. They can be placed anywhere in the memory space to enable the reception of messages. The 10 most significant bits of the start of this memory area are specified by bits DA15-DA6 in registers DMAR and IDR, the remaining bits are 0. The memory map is shown in Figure 45. Each buffer is filled starting from the bottom (last 3 address bits=000) up. Endpoint Initialization To be ready to receive, set STAT_RX to VALID (11b) in EP0RB to enable reception. To be ready to transmit: 106/186 1. Write the data in the DMA transmit buffer. 2. In register EPnRA, specify the number of bytes to be transmitted in the TBC field 3. Enable the endpoint by setting the STAT_TX bits to VALID (11b) in EPnRA. Doc ID 7516 Rev 8 ST7263Bxx Note: On-chip peripherals Once transmission and/or reception are enabled, registers EPnRA and/or EPnRB (respectively) must not be modified by software, as the hardware can change their value on the fly. When the operation is completed, they can be accessed again to enable a new operation. Interrupt handling Start of Frame (SOF) The interrupt service routine may monitor the SOF events for a 1 ms synchronization event to the USB bus. This interrupt is generated at the end of a resume sequence and can also be used to detect this event. USB Reset (RESET) When this event occurs, the DADDR register is reset, and communication is disabled in all endpoint registers (the USB interface will not respond to any packet). Software is responsible for reenabling endpoint 0 within 10 ms of the end of reset. To do this, set the STAT_RX bits in the EP0RB register to VALID. Suspend (SUSP) The CPU is warned about the lack of bus activity for more than 3 ms, which is a suspend request. The software should set the USB interface to suspend mode and execute an ST7 HALT instruction to meet the USB-specified power constraints. End Suspend (ESUSP) The CPU is alerted by activity on the USB, which causes an ESUSP interrupt. The ST7 automatically terminates Halt mode. Correct Transfer (CTR) Table 36. Address 1. When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to NAK. Every valid endpoint is NAKed until software clears the CTR bit in the ISTR register, independently of the endpoint number addressed by the transfer which generated the CTR interrupt. If the event triggering the CTR interrupt is a SETUP transaction, both STAT_TX and STAT_RX are set to NAK. 2. Read the PIDR to obtain the token and the IDR to get the endpoint number related to the last transfer. When a CTR interrupt occurs, the TP3-TP2 bits in the PIDR register and EP1-EP0 bits in the IDR register stay unchanged until the CTR bit in the ISTR register is cleared. 3. Clear the CTR bit in the ISTR register. USB register map and reset values Register Name 7 6 5 4 3 2 1 0 25 PIDR Reset value TP3 x TP2 x 0 0 0 0 0 0 RX_SEZ 0 RXD 0 0 0 26 DMAR Reset value DA15 x DA14 x DA13 x DA12 x DA11 x DA10 x DA9 x DA8 x (Hex.) Doc ID 7516 Rev 8 107/186 On-chip peripherals Table 36. Address ST7263Bxx USB register map and reset values (continued) Register Name 7 6 5 4 3 2 1 0 27 IDR Reset value DA7 x DA6 x EP1 x EP0 x CNT3 0 CNT2 0 CNT1 0 CNT0 0 28 ISTR Reset value SUSP 0 DOVR 0 CTR 0 ERR 0 IOVR 0 ESUSP 0 RESET 0 SOF 0 29 IMR Reset value SUSPM 0 DOVRM 0 CTRM 0 ERRM 0 IOVRM 0 ESUSP M 0 RESETM 0 SOFM 0 2A CTLR Reset value 0 0 0 0 0 0 0 0 RESUM E 0 PDWN 1 FSUSP 1 FRES 0 2B DADDR Reset value 0 0 ADD6 0 ADD5 0 ADD4 0 ADD3 0 ADD2 0 ADD1 0 ADD0 0 2C EP0RA Reset value TBC3 x TBC2 x TBC1 x TBC0 x 2D EP0RB Reset value 0 0 0 0 0 0 0 0 2E EP1RA Reset value TBC3 x TBC2 x TBC1 x TBC0 x 2F EP1RB Reset value EA3 x EA2 x EA1 x EA0 x 30 EP2RA Reset value TBC3 x TBC2 x TBC1 x TBC0 x 31 EP2RB Reset value EA3 x EA2 x EA1 x EA0 x (Hex.) 108/186 ST_OUT DTOG_TX STAT_TX1 STAT_TX0 0 0 0 0 1 1 DTOG_RX 0 STAT_RX 1 0 STAT_RX 0 0 ST_OUT DTOG_TX STAT_TX1 STAT_TX0 0 0 0 0 CTRL 0 DTOG_RX 0 STAT_RX 1 0 STAT_RX 0 0 ST_OUT DTOG_TX STAT_TX1 STAT_TX0 0 0 0 0 CTRL 0 DTOG_RX 0 STAT_RX 1 0 STAT_RX 0 0 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals 11.5 I²C bus interface 11.5.1 Introduction The I²C bus interface serves as an interface between the microcontroller and the serial I²C bus. It provides both multimaster and slave functions, and controls all I²C bus-specific sequencing, protocol, arbitration and timing. It supports fast I²C mode (400 kHz). 11.5.2 Main features ● Parallel-bus/I²C protocol converter ● Multimaster capability ● 7-bit addressing ● Transmitter/receiver flag ● End-of-byte transmission flag ● Transfer problem detection I²C master features ● Clock generation ● I²C bus busy flag ● Arbitration Lost Flag ● End of byte transmission flag ● Transmitter/Receiver Flag ● Start bit detection flag ● Start and Stop generation I²C slave features 11.5.3 ● Stop bit detection ● I²C bus busy flag ● Detection of misplaced start or stop condition ● Programmable I²C Address detection ● Transfer problem detection ● End-of-byte transmission flag ● Transmitter/Receiver flag General description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by software. The interface is connected to the I²C bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard I²C bus and a Fast I²C bus. This selection is made by software. Doc ID 7516 Rev 8 109/186 On-chip peripherals ST7263Bxx Mode selection The interface can operate in the four following modes: ● Slave transmitter/receiver ● Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, allowing then Multi-Master capability. Communication flow In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. In Slave mode, the interface is capable of recognizing its own address (7-bit), and the General Call address. The General Call address detection may be enabled or disabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the start condition is the address byte; it is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 46. Figure 46. I²C bus protocol SDA ACK MSB SCL 1 2 8 START CONDITION 9 STOP CONDITION VR02119B Acknowledge may be enabled and disabled by software. The I²C interface address and/or general call address can be selected by software. The speed of the I²C interface may be selected between Standard (up to 100 kHz) and Fast I²C (up to 400 kHz). SDA/SCL line control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data register. The SCL frequency (FSCL) is controlled by a programmable clock divider which depends on the I²C bus mode. When the I²C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. 110/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals When the I²C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins. Figure 47. I²C interface block diagram DATA REGISTER (DR) SDA or SDAI DATA CONTROL DATA SHIFT REGISTER COMPARATOR OWN ADDRESS REGISTER (OAR) CLOCK CONTROL SCL or SCLI CLOCK CONTROL REGISTER (CCR) CONTROL REGISTER (CR) STATUS REGISTER 1 (SR1) CONTROL LOGIC STATUS REGISTER 2 (SR2) INTERRUPT 11.5.4 Functional description Refer to the CR, SR1 and SR2 registers in Section 11.5.7. for the bit definitions. By default the I²C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. Slave mode As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the General Call address (if selected by software). ● Address not matched: the interface ignores it and waits for another Start condition. ● Address matched The interface generates in sequence: – Acknowledge pulse if the ACK bit is set. – EVF and ADSL bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register, holding the SCL line low (see Figure 48 Transfer sequencing EV1). Next, software must read the DR register to determine from the least significant bit (Data Direction Bit) if the slave must enter Receiver or Transmitter mode. Slave receiver Doc ID 7516 Rev 8 111/186 On-chip peripherals ST7263Bxx Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: ● Acknowledge pulse if the ACK bit is set ● EVF and BTF bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 48 Transfer sequencing EV2). Slave transmitter Following the address reception and after the SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register. The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 48 Transfer sequencing EV3). When the acknowledge pulse is received, the EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Closing Slave communication After the last data byte is transferred a Stop Condition is generated by the master. The interface detects this condition and sets EVF and STOPF bits with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR2 register (see Figure 48 Transfer sequencing EV4). Error cases Note: ● BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and the BERR bits are set with an interrupt if the ITE bit is set. If it is a Stop, then the interface discards the data, released the lines and waits for another Start condition. If it is a Start, then the interface discards the data and waits for the next slave address on the bus. ● AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set. The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. In case of errors, SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. While AF=1, the SCL line may be held low due to SB or BTF flags that are set at the same time. It is then necessary to release both lines by software. How to Release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte. Master mode To switch from default Slave mode to Master mode, a Start condition generation is needed. Start condition 112/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition. Once the Start condition is sent, the EVF and SB bits are set by hardware with an interrupt if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave address byte, holding the SCL line low (see Figure 48 Transfer sequencing EV5). Slave address transmission Then the slave address byte is sent to the SDA line via the internal shift register. After completion of this transfer (and acknowledge from the slave if the ACK bit is set), the EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the CR register (for example set PE bit), holding the SCL line low (see Figure 48 Transfer sequencing EV6). Next the master must enter Receiver or Transmitter mode. Master receiver Following the address transmission and after the SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: ● Acknowledge pulse if the ACK bit is set ● EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 48 Transfer sequencing EV7). To close the communication: before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte. Master transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 48 Transfer sequencing EV8). When the acknowledge bit is received, the interface sets, EVF and BTF bits with an interrupt if the ITE bit is set. To close the communication: after writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Error cases ● BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set by hardware with an interrupt if ITE is set. Note that BERR will not be set if an error is detected during the first or second pulse of Doc ID 7516 Rev 8 113/186 On-chip peripherals ST7263Bxx each 9-bit transaction: Single Master mode If a Start or Stop is issued during the first or second pulse of a 9-bit transaction, the BERR flag will not be set and transfer will continue however the BUSY flag will be reset. To work around this, slave devices should issue a NACK when they receive a misplaced Start or Stop. The reception of a NACK or BUSY by the master in the middle of communication gives the possibility to reinitiate transmission. Multimaster mode Normally the BERR bit would be set whenever unauthorized transmission takes place while transfer is already in progress. However, an issue will arise if an external master generates an unauthorized Start or Stop while the I2C master is on the first or second pulse of a 9-bit transaction. It is possible to work around this by polling the BUSY bit during I2C master mode transmission. The resetting of the BUSY bit can then be handled in a similar manner as the BERR flag being set. Note: 114/186 ● AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the START or STOP bit. The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. ● ARLO: Detection of an arbitration lost condition. In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared). In all these cases, the SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. While AF=1, the SCL line may be held low due to SB or BTF flags that are set at the same time. It is then necessary to release both lines by software. Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Figure 48. Transfer sequencing Table 37. Slave receiver S Addres s A Data1 A Data2 A DataN A P ..... EV 1 Table 38. S EV 2 EV 2 EV 2 EV 4 Slave Transmitter Addres A s Data1 A Data2 A DataN N A P ..... EV EV 1 3 Table 39. EV 3 EV3 -1 EV 4 Master receiver Addres s S EV 3 A Data1 A Data2 A DataN N A P ..... EV 5 EV 6 Table 40. EV 7 EV 7 Master Transmitter Addres A s S EV 7 Data1 A Data2 A DataN A P ..... EV 5 EV EV 6 8 EV 8 EV 8 EV 8 1. Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge EVx=Event (with interrupt if ITE=1)EV1: EVF=1, ADSL=1, cleared by reading the SR1 register. EV2: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register. EV3: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register. EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading the SR1 register. The BTF is cleared by releasing the lines (STOP=1, STOP=0) or by writing the DR register (DR=FFh). Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen. EV4: EVF=1, STOPF=1, cleared by reading the SR2 register. EV5: EVF=1, SB=1, cleared by reading the SR1 register followed by writing the DR register. EV6: EVF=1, cleared by reading the SR1 register followed by writing the CR register (for example PE=1). EV7: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register. EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register. Doc ID 7516 Rev 8 115/186 On-chip peripherals 11.5.5 ST7263Bxx Low power modes Table 41. Low power modes Mode 11.5.6 Description WAIT No effect on I²C interface. I²C interrupts cause the device to exit from Wait mode. HALT I²C registers are frozen. In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The I²C interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt mode” capability. Interrupts Figure 49. Event flags and interrupt generation BTF ADSL SB AF STOPF ARLO BERR ITE INTERRUPT EVF (1) 1. EVF can also be set by EV6 or an error from the SR2 register. Table 42. Interrupts Exit from Wait Exit from Halt BTF Yes No ADSL Yes No Start Bit Generation Event (Master mode) SB Yes No Acknowledge Failure Event AF Yes No Interrupt event End of Byte Transfer Event Address Matched Event (Slave mode) Event flag Enable control bit ITE Stop Detection Event (Slave mode) STOPF Yes No Arbitration Lost Event (Multimaster configuration) ARLO Yes No Bus Error Event BERR Yes No The I²C interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction). 116/186 Doc ID 7516 Rev 8 ST7263Bxx 11.5.7 On-chip peripherals Register description I²C Control register (CR) Reset value: 0000 0000 (00h) 7 0 0 0 PE ENGC START ACK STOP ITE Read/write [7:6] Reserved. Forced to 0 by hardware. 5 PE Peripheral enable. This bit is set and cleared by software. 0: Peripheral disabled 1: Master/Slave capability Note: When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released while PE=0. When PE=1, the corresponding I/O pins are selected by hardware as alternate functions. To enable the I²C interface, write the CR register TWICE with PE=1 as the first write only activates the interface (only PE is set). 4 ENGC Enable General Call. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored). 0: General Call disabled 1: General Call enabled Note: In accordance with the I2C standard, when GCAL addressing is enabled, an I2C slave can only receive data. It will not transmit data to the master. 3 START Generation of a Start condition. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1). In master mode: 0: No start generation 1: Repeated start generation In slave mode: 0: No start generation 1: Start generation when the bus is free Doc ID 7516 Rev 8 117/186 On-chip peripherals ST7263Bxx 2 ACK Acknowledge enable. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). 0: No acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received 1 STOP Generation of a Stop condition. This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). In Master mode: 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. In Slave mode: 0: No stop generation 1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the STOP bit has to be cleared by software. 0 ITE Interrupt enable. This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 49 for the relationship between the events and the interrupt. SCL is held low when the SB, BTF or ADSL flags or an EV6 event (See Figure 48) is detected. 118/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals I²C Status register 1 (SR1) Reset value: 0000 0000 (00h) 7 EVF 0 0 TRA BUSY BTF ADSL M/SL SB Read only 7 EVF Event flag This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register in case of error event or as described in Figure 48. It is also cleared by hardware when the interface is disabled (PE=0). 0: No event 1: One of the following events has occurred: ● BTF=1 (Byte received or transmitted) ● ADSL=1 (Address matched in Slave mode while ACK=1) ● SB=1 (Start condition generated in Master mode) ● AF=1 (No acknowledge received after byte transmission) ● STOPF=1 (Stop condition detected in Slave mode) ● ARLO=1 (Arbitration lost in Master mode) ● BERR=1 (Bus error, misplaced Start or Stop condition detected) ● Address byte successfully transmitted in Master mode. 6 Reserved. Forced to 0 by hardware. 5 TRA Transmitter/Receiver. When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0). 0: Data byte received (if BTF=1) 1: Data byte transmitted 4 BUSY Bus busy. This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs. 0: No communication on the bus 1: Communication ongoing on the bus Note: The BUSY flag is NOT updated when the interface is disabled (PE=0). This can have consequences when operating in Multimaster mode; i.e. a second active I2C master commencing a transfer with an unset BUSY bit can cause a conflict resulting in lost data. A software workaround consists of checking that the I2C is not busy before enabling the I2C Multimaster cell. Doc ID 7516 Rev 8 119/186 On-chip peripherals ST7263Bxx 3 BTF Byte transfer finished. This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0). Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (See Figure 48). BTF is cleared by reading SR1 register followed by writing the next byte in DR register. Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register. The SCL line is held low while BTF=1. 0: Byte transfer not done 1: Byte transfer succeeded 2 ADSL Address matched (Slave mode). This bit is set by hardware as soon as the received slave address matched with the OAR register content or a general call is recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE=0). The SCL line is held low while ADSL=1. 0: Address mismatched or not received 1: Received address matched 1 M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0). 0: Slave mode 1: Master mode 0 SB Start bit (Master mode). This bit is set by hardware as soon as the Start condition is generated (following a write START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE=0). 0: No Start condition 1: Start condition generated 120/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals I²C Status register 2 (SR2) Reset value: 0000 0000 (00h) 7 0 0 0 0 AF STOPF ARLO BERR GCAL Read only [7:5] Reserved. Forced to 0 by hardware. 4 AF Acknowledge failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). 0: No acknowledge failure 1: Acknowledge failure Note: While AF=1, the SCL line may be held low due to SB or BTF flags that are set at the same time. It is then necessary to release both lines by software. 3 STOPF Stop detection (Slave mode). This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while STOPF=1. 0: No Stop condition detected 1: Stop condition detected Doc ID 7516 Rev 8 121/186 On-chip peripherals ST7263Bxx 2 ARLO Arbitration lost. This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). After an ARLO event the interface switches back automatically to Slave mode (M/SL=0). The SCL line is not held low while ARLO=1. 0: No arbitration lost detected 1: Arbitration lost detected Note: In a Multimaster environment, when the interface is configured in Master Receive mode it does not perform arbitration during the reception of the Acknowledge Bit. Mishandling of the ARLO bit from the I2CSR2 register may occur when a second master simultaneously requests the same data from the same slave and the I2C master does not acknowledge the data. The ARLO bit is then left at 0 instead of being set. 1 BERR Bus error. This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while BERR=1. 0: No misplaced Start or Stop condition 1: Misplaced Start or Stop condition Note: If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication 0 GCAL General Call (Slave mode). This bit is set by hardware when a general call address is detected on the bus while ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled (PE=0). 0: No general call address detected on bus 1: general call address detected on bus I²C Clock Control register (CCR) Reset value: 0000 0000 (00h) 7 FM/SM 0 CC6 CC5 CC4 CC3 CC2 CC1 CC0 Read/write 7 FM/SM Fast/Standard I²C mode. This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 0: Standard I²C mode 1: Fast I²C mode [6:0] CC[6:0] 7-bit clock divider. These bits select the speed of the bus (FSCL) depending on the I²C mode. They are not cleared when the interface is disabled (PE=0). Refer to the Electrical Characteristics section for the table of value. Note: The programmed FSCL assumes no load on SCL and SDA lines. 122/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals I²C Data register (DR) These bits contain the byte to be received or transmitted on the bus. ● Transmitter mode: byte transmission start automatically when the software writes in the DR register. ● Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address. The following data bytes are then received one by one after reading the DR register. Reset value: 0000 0000 (00h) 7 D7 0 D6 D5 D4 D3 D2 D1 D0 Read/write I²C Own Address register (OAR) Reset value: 0000 0000 (00h) 7 ADD7 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Read/write [7:1] ADD[7:1] Interface address. These bits define the I²C bus address of the interface. They are not cleared when the interface is disabled (PE=0). 0 ADD0 Address direction bit. This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0). Note: Address 01h is always ignored. Doc ID 7516 Rev 8 123/186 On-chip peripherals Table 43. ST7263Bxx I²C register map Address Register name (Hex.) Note: 124/186 7 6 5 4 3 39 DR DR7 .. DR0 3B OAR ADD7 .. ADD0 3C CCR 3D SR2 3E SR1 3F CR FM/SM EVF 2 1 0 CC6 .. CC0 AF STOPF ARLO BERR GCAL TRA BUSY BTF ADSL M/SL SB PE ENGC START ACK STOP ITE Refer to Section 16: Known limitations for information regarding a limitation on the alternate function on pin PA2 (SCL). Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals 11.6 8-bit A/D converter (ADC) 11.6.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. The result of the conversion is stored in a 8-bit Data register. The A/D converter is controlled through a Control/Status register. 11.6.2 Main features ● 8-bit conversion ● Up to 12 channels with multiplexed input ● Linear successive approximation ● Data register (DR) which contains the results ● Conversion complete status flag ● On/off bit (to reduce consumption) The block diagram is shown in Figure 50. 11.6.3 Functional description Analog power supply VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. See electrical characteristics section for more details. Doc ID 7516 Rev 8 125/186 On-chip peripherals ST7263Bxx Figure 50. ADC block diagram fCPU COCO 0 ADON 0 fADC DIV 4 CH3 CH2 CH1 CH0 ADCCSR 4 AIN0 HOLD CONTROL AIN1 ANALOG MUX RADC ANALOG TO DIGITAL CONVERTER CADC AINx ADCDR D7 D6 D5 D4 D3 D2 D1 D0 Digital A/D conversion result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than or equal to VDDA (high-level voltage reference) then the conversion result in the DR register is FFh (full scale) without overflow indication. If input voltage (VAIN) is lower than or equal to VSSA (low-level voltage reference) then the conversion result in the DR register is 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDR register. The accuracy of the conversion is described in the parametric section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the allotted time. A/D conversion phases The A/D conversion is based on two conversion phases as shown in Figure 51: ● Sample capacitor loading [duration: tLOAD] During this phase, the VAIN input voltage to be measured is loaded into the CADC sample capacitor. ● A/D conversion [duration: tCONV] During this phase, the A/D conversion is computed (8 successive approximations cycles) and the CADC sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. While the ADC is on, these two phases are continuously repeated. At the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. The advantage of this behavior is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 126/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals Software procedure Refer to the control/status register (CSR) and data register (DR) in Section 11.6.6 for the bit definitions and to Figure 51 for the timings. ADC configuration The total duration of the A/D conversion is 12 ADC clock periods (1/fADC=4/fCPU). The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the «I/O ports» chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the CSR register: ● Select the CH[3:0] bits to assign the analog channel to be converted. ADC conversion In the CSR register: ● Set the ADON bit to enable the A/D converter and to start the first conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete: ● The COCO bit is set by hardware. ● No interrupt is generated. ● The result is in the DR register and remains valid until the next conversion has ended. A write to the CSR register (with ADON set) aborts the current conversion, resets the COCO bit and starts a new conversion. Figure 51. ADC conversion timings ADON ADCCSR WRITE OPERATION tCONV HOLD CONTROL tLOAD 11.6.4 COCO BIT SET Low power modes Table 44. Low power modes Mode Note: Description WAIT No effect on A/D Converter HALT A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilization time before accurate conversions can be performed. The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. Doc ID 7516 Rev 8 127/186 On-chip peripherals 11.6.5 ST7263Bxx Interrupts None 11.6.6 Register description Control/Status register (CSR) Reset value: 0000 0000 (00h) 7 COCO 0 0 ADON 0 CH3 CH2 CH1 CH0 Read/write 7 COCO Conversion Complete This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete 1: Conversion can be read from the DR register 6 Reserved. must always be cleared. 5 ADON A/D Converter On This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on 4 Reserved. must always be cleared. [3:0] CH[3:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert (see Table 45). Table 45. Channel selection Channel pin(1) CH3(2) CH2 CH1 CH0 AIN0 0 0 0 0 AIN1 0 0 0 1 AIN2 0 0 1 0 AIN3 0 0 1 1 AIN4 0 1 0 0 AIN5 0 1 0 1 AIN6 0 1 1 0 AIN7 0 1 1 1 AIN8 1 0 0 0 AIN9 1 0 0 1 AIN10 1 0 1 0 AIN11 1 0 1 1 1. The number of pins AND the channel selection varies according to the device. Refer to the device pinout. 128/186 Doc ID 7516 Rev 8 ST7263Bxx On-chip peripherals 2. For SDIP/SO34 devices, the CH3 bit is always at ‘0’. If, however, set to ‘1’ on error, channel (11:8) becomes enabled which may result in a higher and unnecessary level of consumption. Data register (DR) This register contains the converted analog value in the range 00h to FFh. Reset value: 0000 0000 (00h) 7 D7 0 D6 D5 D4 D3 D2 D1 D0 Read only Note: Reading this register reset the COCO flag. Table 46. ADC register map Address Register name (Hex.) 0Ah DR 0Bh CSR 7 6 5 4 3 2 1 0 CH2 CH1 CH0 AD7 .. AD0 COCO 0 ADON Doc ID 7516 Rev 8 0 CH3 129/186 Instruction set ST7263Bxx 12 Instruction set 12.1 ST7 addressing modes The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Table 47. Addressing modes Addressing mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset byte,#5 The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do so, most of the addressing modes may be subdivided in two sub-modes called long and short: ● Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. ● Short addressing mode is less powerful because it can generally only access page zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes. Table 48. ST7 addressing mode overview Mode Destination/ source Syntax Pointer address Pointer size (Hex.) Length (bytes) Inherent nop +0 Immediate ld A,#$55 +1 Short Direct ld A,$10 00..FF +1 Long Direct ld A,$1000 0000..FFFF +2 No Offset Direct Indexed ld A,(X) 00..FF + 0 (with X register) + 1 (with Y register) Short Direct Indexed ld A,($10,X) 00..1FE +1 Long Direct Indexed ld A,($1000,X) 0000..FFFF +2 Short Indirect ld A,[$10] 00..FF 130/186 Doc ID 7516 Rev 8 00..FF byte +2 ST7263Bxx Table 48. Instruction set ST7 addressing mode overview (continued) Mode Syntax Destination/ source Pointer address Pointer size (Hex.) Length (bytes) Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2 Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2 Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2 Relative Direct jrne loop PC128/PC+127(1) Relative Indirect jrne [$10] PC128/PC+127(1) Bit Direct bset $10,#7 00..FF Bit Indirect bset [$10],#7 00..FF Bit Direct Relative btjt $10,#7,skip 00..FF Bit Indirect Relative btjt [$10],#7,skip 00..FF +1 00..FF byte +2 +1 00..FF byte +2 +2 00..FF byte +3 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx. 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. Table 49. Inherent instructions Inherent instruction Function NOP No operation TRAP S/W interrupt WFI Wait For Interrupt (Low Power mode) HALT Halt Oscillator (Lowest Power mode) RET Sub-routine Return IRET Interrupt Sub-routine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero Doc ID 7516 Rev 8 131/186 Instruction set Table 49. 12.1.2 ST7263Bxx Inherent instructions (continued) Inherent instruction Function CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles Immediate instructions Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value. Table 50. 12.1.3 Immediate instructions Immediate instruction Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub-modes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 12.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. 132/186 Doc ID 7516 Rev 8 ST7263Bxx Instruction set Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two submodes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 51. Instructions supporting Direct, Indexed, Indirect and Indirect Indexed addressing modes Long and Short instructions Function LD Load CP Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Addition/subtraction operations Doc ID 7516 Rev 8 133/186 Instruction set ST7263Bxx Table 51. 12.1.7 Instructions supporting Direct, Indexed, Indirect and Indirect Indexed addressing modes (continued) Long and Short instructions Function BCP Bit Compare Short Instructions only Function CLR Clear INC, DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement BSET, BRES Bit Operations BTJT, BTJF Bit Test and Jump Operations SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles CALL, JP Call or Jump subroutine Relative mode (Direct, Indirect) This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it. Table 52. Instructions supporting relative addressing mode Available relative direct/Indirect instructions Function JRxx Conditional Jump CALLR Call Relative The relative addressing mode consists of two sub-modes: Relative (Direct) The offset follows the opcode. Relative (Indirect) The offset is defined in memory, of which the address follows the opcode. 134/186 Doc ID 7516 Rev 8 ST7263Bxx 12.2 Instruction set Instruction groups The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Table 53. Instruction groups Load and Transfer LD CLR Stack operation PUSH POP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF RSP RET Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2End of previous instruction PC-1Prebyte PCOpcode PC+1Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91Replace an instruction using X indirect indexed addressing mode by a Y one. Doc ID 7516 Rev 8 135/186 Instruction set Table 54. ST7263Bxx Instructions Mnemo Description Function/example Dst Src H ADC Add with Carry A=A+M+C A M ADD Addition A=A+M A M AND Logical And A=A.M A BCP Bit compare A, Memory tst (A . M) A BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear CP Arithmetic Compare tst(Reg - M) reg CPL One Complement A = FFH-A DEC Decrement dec Y HALT Halt IRET Interrupt routine return Pop CC, A, X, PC INC Increment inc X JP Absolute Jump jp [TBL.w] JRA Jump relative always JRT Jump relative JRF Never jump JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H=1? JRNH Jump if H = 0 H=0? JRM Jump if I = 1 I=1? JRNM Jump if I = 0 I=0? JRMI Jump if N = 1 (minus) N=1? JRPL Jump if N = 0 (plus) N=0? JREQ Jump if Z = 1 (equal) Z=1? JRNE Jump if Z = 0 (not equal) Z=0? JRC Jump if C = 1 C=1? JRNC Jump if C = 0 C=0? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= 136/186 I N Z C H N Z C H N Z C M N Z M N Z reg, M 0 1 N Z C reg, M N Z 1 reg, M N Z N Z N Z M 0 H reg, M jrf * Doc ID 7516 Rev 8 I C ST7263Bxx Table 54. Instruction set Instructions (continued) Mnemo Description Function/example Dst Src JRUGT Jump if (C + Z = 0) Unsigned > JRULE Jump if (C + Z = 1) Unsigned