ST7FLI49MK1T6

ST7LITE49M 8-bit MCU with single voltage Flash memory data EEPROM, ADC, 8/12-bit timers, and I²C interface Features ■ ■ ■ Memories – 4 Kbytes single voltage extended Flash (XFlash) Program memory with Read-Out Protection In-circuit programming and in-application programming (ICP and IAP) Endurance: 10k write/erase cycles guaranteed Data retention: 20 years at 55 °C – 384 bytes RAM – 128 bytes data EEPROM with Read-Out Protection. 300K write/erase cycles guaranteed, data retention: 20 years at 55 °C. Clock, reset and supply management – 3-level low voltage supervisor (LVD) for main supply and an auxiliary voltage detector (AVD) for safe power-on/off – Clock sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock – Five power saving modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow I/O Ports – Up to 24 multifunctional bidirectional I/Os – 8 high sink outputs Table 1. LQFP32 (7x7mm) SDIP32 ■ 5 timers – Configurable watchdog timer – Dual 8-bit Lite timers with prescaler, 1 real-time base and 1 input capture – Dual 12-bit Auto-reload timers with 4 PWM outputs, input capture, output compare, dead-time generation and enhanced onepulse mode functions ■ Communication interface: – I²C multimaster interface ■ A/D converter: 10 input channels ■ Interrupt management – 13 interrupt vectors plus TRAP and RESET ■ Instruction set – 8-bit data manipulation – 63 basic instructions with illegal opcode detection – 17 main addressing modes – 8 x 8 unsigned multiply instructions ■ Development tools – Full HW/SW development package – DM (Debug Module) Device summary Features November 2009 ST7LITE49M Program memory 4 Kbytes RAM (stack) - bytes 384 (128) Data EEPROM - bytes 128 Operating supply 2.4 to 5.5 V CPU frequency Up to 8 MHz Operating temperature -40 to +125 °C Packages LQFP32, SDIP32 Doc ID 13562 Rev 3 1/188 www.st.com 1 Contents ST7LITE49M Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Register and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Flash programmable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.2 In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5.1 Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5.2 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.6 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 Description of Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . 23 Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4 2/188 4.3.1 5.3.1 Read operation (E2LAT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3.2 Write operation (E2LAT=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4.1 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4.2 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4.3 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.5 Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.6 Data EEPROM read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.7 EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 13562 Rev 3 ST7LITE49M 6 7 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3.5 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 7.2 7.3 7.4 7.5 8 Contents RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1.2 Auto-wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.1 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.2 Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.3 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3.3 External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3.4 Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.4.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.4.2 Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.4.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.5.1 Main clock control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . 44 7.5.2 RC control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.5.3 System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 45 7.5.4 AVD threshold selection register (AVDTHCR) . . . . . . . . . . . . . . . . . . . . 46 7.5.5 Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 47 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Doc ID 13562 Rev 3 3/188 Contents 9 ST7LITE49M 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4/188 Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.2.2 Interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.4 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.5 Description of interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.5.1 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.5.2 Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 53 8.5.3 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 56 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.4 Active-halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.5 10 8.2.1 9.4.1 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.5.1 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.5.2 AWUFH control/status register (AWUCSR) . . . . . . . . . . . . . . . . . . . . . . 66 9.5.3 AWUFH prescaler register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.4 Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.4 Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.7 Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Doc ID 13562 Rev 3 ST7LITE49M 11 Contents 10.7.1 Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.7.2 Other ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.1 11.2 11.3 11.4 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.1.4 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.1.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.1.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Dual 12-bit autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.2.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Lite timer 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 11.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 11.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.3.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.4.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.5 11.4.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.4.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Doc ID 13562 Rev 3 5/188 Contents 12 ST7LITE49M 11.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.5.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11.5.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.1 12.2 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.1.1 Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 12.1.2 Immediate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.1.3 Direct modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.1.4 Indexed modes (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . 132 12.1.5 Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.1.6 Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.1.7 Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.2.1 13 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.4 13.5 6/188 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 142 13.3.3 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 143 13.3.4 Voltage drop between AVD flag setting and LVD reset generation . . . 143 13.3.5 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.4.1 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.4.2 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 150 Doc ID 13562 Rev 3 ST7LITE49M Contents 13.5.1 13.6 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.6.1 Auto-wakeup from Halt oscillator (AWU) . . . . . . . . . . . . . . . . . . . . . . . 152 13.6.2 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 153 13.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 13.8 EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 156 13.9 13.8.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 156 13.8.2 EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 157 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 13.9.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 13.9.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 13.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 13.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14 Device configuration and ordering information . . . . . . . . . . . . . . . . . 173 14.1 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 14.1.2 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.3.4 Order codes for development and programming tools . . . . . . . . . . . . . 177 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.1 16 14.1.1 14.2 14.4 15 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Doc ID 13562 Rev 3 7/188 List of tables ST7LITE49M List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. 8/188 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt software priority truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CPU clock delay during reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Reset source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 AVD threshold selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Clock register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Setting the interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Interrupt vector vs. ISPRx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ST7LITE49M interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Enabling/disabling Active-halt and Halt modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 AWU register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 DR value and output pin status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 PA5:0, PB7:0, PC7:4 and PC2:0 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 PA7:6 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 PC3 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 I/O port register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Watchdog timer register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Effect of low power modes on autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Effect of low power modes on Lite timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Lite timer register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Effect of low power modes on the I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Configuration of I2C delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 I2C register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Effect of low power modes on the A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Channel selection using CH[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Configuring the ADC clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Doc ID 13562 Rev 3 ST7LITE49M Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. List of tables ADC register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Instructions supporting inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . 132 Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 133 Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Operating characteristics with AVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Voltage drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Internal RC oscillator characteristics (3.3 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 SCL frequency (multimaster I2C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 AWU from Halt characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Typical ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 RAM and hardware registers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Flash program memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Data EEPROM memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 ADC accuracy with VDD = 3.3 to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 ADC accuracy with VDD = 2.7 to 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 ADC accuracy with VDD = 2.4 to 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Configuration of sector size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Development tool order codes for the ST7LITE49M family . . . . . . . . . . . . . . . . . . . . . . . 177 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 32-pin plastic dual in-line package, shrink 400-mil width, (mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . . . . . . . . 183 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Doc ID 13562 Rev 3 9/188 List of figures ST7LITE49M List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 10/188 ST7LITE49M general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 32-pin SDIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 32-pin LQFP 7x7 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ST7LITE49M memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 EEPROM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Data EEPROM write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Single timer mode (ENCNTR2=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Dual timer mode (ENCNTR2=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 PWM polarity inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 PWM signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Dead time generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ST7LITE49M block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Block diagram of output compare mode (single timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Block diagram of input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Long range input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Long range input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Doc ID 13562 Rev 3 ST7LITE49M Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. List of figures Block diagram of One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 One-pulse mode and PWM timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Dynamic DCR2/3 update in One-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Force overflow timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Lite timer 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 fCPU maximum operating frequency versus VDD supply voltage . . . . . . . . . . . . . . . . . . 142 Frequency vs voltage at four different ambient temperatures (RC at 5 V) . . . . . . . . . . . . 145 Frequency vs voltage at four different ambient temperatures (RC at 3.3 V). . . . . . . . . . . 145 Accuracy in % vs voltage at 4 different ambient temperatures (RC at 5 V) . . . . . . . . . . . 146 Accuracy in % vs voltage at 4 different ambient temperatures (RC at 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Typical IDD in Run mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Typical IDD in WFI vs. fCPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Typical IDD in slow mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Typical IDD in Slow-wait mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Typical IDD vs. temperature at VDD = 5 V and fCPU = 8 MHz . . . . . . . . . . . . . . . . . . . . 149 Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Rpu resistance versus voltage at four different temperatures . . . . . . . . . . . . . . . . . . . . . . 159 Ipu current versus voltage at four different temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 159 Typical VOL at VDD = 2.4 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Typical VOL at VDD = 3 V (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Typical VOL at VDD = 5 V (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Typical VOL at VDD = 2.4 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Typical VOL at VDD = 3 V (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Typical VOL at VDD = 5 V (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Typical VOL vs. VDD at IIO = 2 mA (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Typical VOL vs. VDD at IIO = 4 mA (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Typical VOL vs VDD at IIO = 2 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Typical VOL vs VDD at IO = 8 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Typical VOL vs VDD at IIO = 12 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Typical VDD-VOH vs. IIO at VDD = 2.4 V (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Typical VDD-VOH vs. IIO at VDD = 3 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Typical VDD-VOH vs. IIO at VDD = 5 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Typical VDD-VOH vs. IIO at VDD = 2.4 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Typical VDD-VOH vs. IIO at VDD = 3 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Typical VDD-VOH vs. IIO at VDD = 5 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Typical VDD-VOH vs. VDD at IIO = 2 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Typical VDD-VOH vs. VDD at IIO = 4 mA (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Doc ID 13562 Rev 3 11/188 List of figures ST7LITE49M Figure 100. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Figure 101. 32-pin plastic dual in-line package, shrink 400-mil width, package outline. . . . . . . . . . . . 182 Figure 102. 32-pin low profile quad flat package (7x7), package outline . . . . . . . . . . . . . . . . . . . . . . . 183 12/188 Doc ID 13562 Rev 3 ST7LITE49M 1 Description Description The ST7LITE49M is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7LITE49M features Flash memory with byte-by-byte in-circuit programming (ICP) and in-application programming (IAP) capability. Under software control, the ST7LITE49M device can be placed in Wait, Slow, or Halt mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. The ST7LITE49M features an on-chip Debug Module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC protocol reference manual. Figure 1. ST7LITE49M general block diagram CLKIN OSC1 OSC2 /2 Ext. OSC 1MHz to 16MHz Int. 8 MHz RC OSC Int. 32 kHz RC OSC /2 12-bit Auto-reload dual timer Internal clock 8-bit dual Lite timer Power Supply RESET Control 8-bit core ALU ADDRESS AND DATA BUS LVD, AVD VDD VSS Flash program memory (4K bytes) RAM (384 bytes) Port A PA7:0 (8 bits) Port B PB7:0 (8 bits) Port C PC7:0 (8 bits) 10-bit ADC I2 C Watchdog Debug module Data EEPROM (128 bytes) Doc ID 13562 Rev 3 13/188 Pin description 2 ST7LITE49M Pin description Figure 2. 32-pin SDIP package pinout BREAK/PC7 PA0(HS) ATIC/PA1(HS) ATPWM0/PA2(HS) ATPWM1/PA3(HS) ATPWM2/MCO/PA4(HS) ATPWM3/PA5(HS) I2CDATA/PA6(HS) I2CCLK/PA7(HS) RESET NC VDD VSS OSC1/CLKIN OSC2 VSSA 1 ei2 2 32 ei2 3 30 4 5 6 31 29 28 ei0 ei2 27 7 26 8 25 9 24 10 11 23 ei1 22 12 21 13 20 14 19 15 18 16 17 PC6 PC5 PC4/LTIC PC3/ICCCLK PC2/ICCDATA PC1/AIN9 PC0/AIN8 PB7/AIN7 PB6/AIN6 PB5/AIN5 PB4/AIN4 PB3/AIN3 PB2/AIN2 PB1/AIN1/CLKIN PB0/AIN0 VDDA (HS) 20 mA high sink capability eix associated external interrupt vector Note 1: Available on 8 Kbytes version only 32-pin LQFP 7x7 package pinout PA2(HS)/ATPWM0 PA1(HS)/ATIC PA0(HS) PC7/BREAK PC6 PC5 PC4/LTIC PC3/ICCCLK Figure 3. 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 ei2 ei0 22 21 20 ei1 19 18 17 9 10 11 12 13 14 15 16 VSS OSC1/CLKIN OSC2 VSSA VDDA AIN0/PB0 CLKIN/AIN1/PB1 AIN2/PB2 ATPWM1/PA3(HS) ATPWM2/MCO/PA4(HS) ATPWM3/PA5(HS) I2CDATA/PA6(HS) I2CCLK/PA7(HS) RESET NC VDD 14/188 Doc ID 13562 Rev 3 PC2/ICCDATA PC1/AIN9 PC0/AIN8 PB7/AIN7 PB6/AIN6 PB5/AIN5 PB4/AIN4 PB3/AIN3 (HS) 20 mA high sink capability eix associated external interrupt vector ST7LITE49M Pin description Legend / Abbreviations for Table 2: Type: I = input, O = output, S = supply In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20 mA high sink (on N-buffer only) Port and control configuration: ● Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog ● Output: OD = open-drain, PP = push-pull The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state. Device pin description SDIP32 Pin name Input Output Port/control LQFP32 1 5 PA3(HS)/ATPWM1 I/O CT HS x 2 6 PA4(HS)/ ATPWM2/MCO I/O CT HS x 3 7 PA5 (HS)ATPWM3 I/O CT HS 4 8 PA6(HS)/ I2CDATA I/O CT 5 9 PA7(HS)/I2CCLK I/O CT 6 10 RESET Alternate function x x Port A3 (HS) ATPWM1 x x Port A4 (HS) ATPWM2/ MCO x x x Port A5 (HS) ATPWM3 HS x T Port A6 (HS) I2CDATA HS x T Port A7 (HS) I2CCLK float PP Output Main function (after reset) OD(1) Input ei0 ana Type Level int Pin number wpu Table 2. ei0 x x Reset (2) S Digital supply voltage 8 12 VDD 9 13 VSS(2) S Digital ground voltage 10 14 OSC1/CLKIN I Resonator oscillator inverter input or external clock input 11 15 OSC2 O Resonator oscillator output 16 VSSA(2) S Analog ground voltage 17 VDDA(2) S Analog supply voltage 12 13 Doc ID 13562 Rev 3 15/188 Pin description Table 2. ST7LITE49M Device pin description Pin number Port/control OD(1) PP 18 PB0/AIN0 I/O CT x x x x Port B0 AIN0 15 19 PB1/AIN1/CLKIN I/O CT x x x x Port B1 AIN1/ External clock source 16 20 PB2/AIN2 I/O CT x x x x Port B2 AIN2 x x x Port B3 AIN3 int wpu Input float Output 14 Input Pin name ana Alternate function SDIP32 Main function (after reset) LQFP32 Type Level ei1 Output 17 21 PB3/AIN3 I/O CT x 18 22 PB4/AIN4 I/O CT x x x x Port B4 AIN4 19 23 PB5/AIN5 I/O CT x x x x Port B5 AIN5 20 24 PB6/AIN6 I/O CT x x x x Port B6 AIN6 21 25 PB7/AIN7 I/O CT x x x x Port B7 AIN7 22 26 PC0/AIN8 I/O CT x x x x Port C0 AIN8 23 27 PC1/AIN9 I/O CT x x x x Port C1 AIN9 24 28 PC2/ICCDATA I/O CT x x x Port C2 ICCDATA 25 29 PC3/ICCCLK I/O CT x x x Port C3 ICCCLK 26 30 PC4/LTIC I/O CT x x x Port C4 LTIC 27 31 PC5 I/O CT x x x Port C5 28 32 PC6 I/O CT x x x Port C6 29 1 PC7/BREAK I/O CT x x x 30 2 PA0 (HS) I/O CT HS x x x 31 3 PA1 (HS)/ATIC I/O CT HS x x x Port A1 (HS) ATIC 32 4 PA2 (HS)/ATPWM0 I/O CT HS x x x Port A2 (HS) ATPWM0 ei2 x ei2 ei0 Port C7 BREAK Port A0 (HS) 1. In the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to VDD are not implemented). 2. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground. 16/188 Doc ID 13562 Rev 3 ST7LITE49M 3 Register and memory mapping Register and memory mapping As shown in Figure 4, the MCU is capable of addressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM, 128 bytes of data EEPROM and 4 Kbytes of Flash program memory. The RAM space includes up to 128 bytes for the stack from 180h to 1FFh. The highest address bytes contain the user reset and interrupt vectors. The Flash memory contains two sectors (see Figure 4) mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (FFE0h-FFFFh). The size of Flash Sector 0 and other device options are configurable by option bytes (refer to Section 14.1 on page 173). Caution: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device. Figure 4. 0000h 007Fh 0080h ST7LITE49M memory map HW registers (seeTable 3) RAM (384 bytes) 0080h 00FFh 0100h 017Fh 0180h 01FFh 0200h 01FFh Short addressing RAM (zero page) RAM 128 bytes Stack DEE0h DEE1h Reserved 0FFFh 1000h DEE2h DEE3h Data EEPROM (128 bytes) 107Fh 1080h FFFFh RCCRL0 RCCRH1 RCCRL1 see Section 7.1.1 Reserved 4K Flash program memory Flash memory (4K) 3 Kbytes (SECTOR 1) 1 Kbytes (SECTOR 0) EFFFh F000h FFDFh FFE0h RCCRH0 F000h FFFFh Interrupt & reset vectors (see Table 16) Doc ID 13562 Rev 3 17/188 Register and memory mapping Table 3. ST7LITE49M Hardware register map(1) Address Block Register label Register name Reset status Remarks 0000h 0001h 0002h Port A PADR PADDR PAOR Port A data register Port A Data direction register Port A option register 00h 00h 00h R/W R/W R/W 0003h 0004h 0005h Port B PBDR PBDDR PBOR Port B data register Port B data direction register Port B option register 00h 00h 00h R/W R/W R/W 0006h 0007h 0008h Port C PCDR PCDDR PCOR Port C data register Port C data direction register Port C option register 00h 00h 08h R/W R/W R/W 0009h to 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah Reserved area (3 bytes) LITE TIMER LTCSR2 LTARR LTCNTR LTCSR1 LTICR Lite timer control/status register 2 Lite timer auto-reload register Lite timer counter register Lite timer control/status register 1 Lite timer input capture register 0Fh 00h 00h 0x00 0000b xxh R/W R/W Read Only R/W Read Only AUTORELOAD TIMER ATCSR CNTR1H CNTR1L ATR1H ATR1L PWMCR PWM0CSR PWM1CSR PWM2CSR PWM3CSR DCR0H DCR0L DCR1H DCR1L DCR2H DCR2L DCR3H DCR3L ATICRH ATICRL ATCSR2 BREAKCR ATR2H ATR2L DTGR BREAKEN Timer control/status register Counter register 1 High Counter register 1 Low Auto-reload register 1 High Auto-reload register 1 Low PWM output control register PWM 0 control/status register PWM 1 control/status register PWM 2 control/status register PWM 3 control/status register PWM 0 duty cycle register High PWM 0 duty cycle register Low PWM 1 duty cycle register High PWM 1 duty cycle register Low PWM 2 duty cycle register High PWM 2 duty cycle register Low PWM 3 duty cycle register High PWM 3 duty cycle register Low Input capture register High Input capture register Low Timer control/status register 2 Break control register Auto-reload register 2 High Auto-reload register 2 Low Dead time generation register Break enable register 0x00 0000b 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 03h 00h 00h 00h 00h 03h R/W Read Only Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only Read Only R/W R/W R/W R/W R/W R/W FFh FFh FFh FFh 00h R/W R/W R/W R/W R/W 002Bh to 002Ch 002Dh 002Eh 002Fh 0030h 0031h 18/188 Reserved area (2 bytes) ITC ISPR0 ISPR1 ISPR2 ISPR3 EICR Interrupt software priority register 0 Interrupt software priority register 1 Interrupt software priority register 2 Interrupt software priority register 3 External interrupt control register Doc ID 13562 Rev 3 ST7LITE49M Table 3. Address Register and memory mapping Hardware register map(1) (continued) Block Register label 0032h Register name Reset status Remarks Reserved area (1 byte) 0033h WDG WDGCR Watchdog control register 7Fh R/W 0034h FLASH FCSR Flash control/status register 00h R/W 0035h EEPROM EECSR Data EEPROM control/status register 00h R/W 0036h 0037h 0038h ADC ADCCSR ADCDRH ADCDRL A/D control status register A/D data register high 00h xxh 0xh R/W Read Only R/W 0039h 003Ah 003Bh 003Ch Reserved area (1 byte) MCC Clock and reset 003Dh MCCSR Main Clock Control/Status register 00h R/W RCCR SICSR RC oscillator control register System integrity control/status register FFh 011x 0x00b R/W R/W AVDTHCR AVD threshold selection register / RC prescaler 00h R/W 003Eh to 0047h 0048h 0049h Reserved area (10 bytes) AWU AWUCSR AWUPR AWU control/status register AWU Preload register FFh 00h R/W R/W 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h DM(2) DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L DMCR2 DM control register DM status register DM breakpoint register 1 High DM breakpoint register 1 Low DM breakpoint register 2 High DM breakpoint register 2 Low DM control register 2 00h 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W 0051h Clock Controller CKCNTCSR Clock controller status register 09h R/W 00h 00h 00h 00h 00h 40h 00h R/W Read only Read only R/W R/W R/W R/W 0052h to 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah Reserved area (18 bytes) I2C I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR I2C control register I2C status register 1 I2C status register 2 2 I C clock control register I2C own address register 1 I2C own address register 2 I2C data register 1. Legend: x=undefined, R/W=read/write. 2. For a description of the debug module registers, see ICC protocol reference manual. Doc ID 13562 Rev 3 19/188 Flash programmable memory ST7LITE49M 4 Flash programmable memory 4.1 Introduction The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using in-circuit programming or in-application programming. The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 4.3 Main features ● ICP (in-circuit programming) ● IAP (in-application programming) ● ICt (in-circuit testing) for downloading and executing user application test patterns in RAM ● Sector 0 size configurable by option byte ● Read-out and write protection Programming modes The ST7 can be programmed in three different ways: 4.3.1 ● Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased. ● In-circuit programming. In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased without removing the device from the application board. ● In-application programming. In this mode, sector 1 and data EEPROM (if present) can be programmed or erased without removing the device from the application board and while the application is running. In-circuit programming (ICP) ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps: Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific reset vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. 20/188 ● Download ICP Driver code in RAM from the ICCDATA pin ● Execute ICP Driver code in RAM to program the Flash memory Doc ID 13562 Rev 3 ST7LITE49M Flash programmable memory Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In-application programming (IAP) This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is Write/Erase protected to allow recovery in case errors occur during the programming operation. 4.4 ICC interface ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are: Note: ● RESET: device reset ● VSS: device power supply ground ● ICCCLK: ICC output serial clock pin ● ICCDATA: ICC input serial data pin ● OSC1: main clock input for external source ● VDD: application board power supply (optional, see Note 3) 1 If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2 During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5 mA at high level (push pull output or pull-up resistor1 kΩ or a reset management IC with open-drain output and pull-up resistor>1 kΩ, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3 The use of pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4 In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. In “disabled option byte” mode (35-pulse ICC mode), pin 9 has to be connected to the PB1/CLKIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. Caution: During normal operation the ICCCLK pin must be internally or externally pulled- up (external pull-up of 10 kΩ mandatory in noisy environment) to avoid entering ICC mode unexpectedly Doc ID 13562 Rev 3 21/188 Flash programmable memory ST7LITE49M during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up. Figure 5. Typical ICC interface PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE (See Note 3) OPTIONAL (See Note 4) 9 7 5 3 1 10 8 6 4 2 APPLICATION BOARD APPLICATION RESET SOURCE See Note 2 22/188 See Note 1 and Caution Doc ID 13562 Rev 3 ICCDATA RESET ST7 ICCCLK See Note 1 PB1/CLKIN VDD APPLICATION POWER SUPPLY APPLICATION I/O ST7LITE49M 4.5 Flash programmable memory Memory protection There are two different types of memory protection: Read-out protection and Write/Erase Protection which can be applied individually. 4.5.1 Read-out protection Read-out protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Both program and data EEPROM memory are protected. In Flash devices, this protection is removed by reprogramming the option. In this case, both program and data EEPROM memory are automatically erased and the device can be reprogrammed. Read-Out Protection selection depends on the device type: 4.5.2 ● In Flash devices it is enabled and removed through the FMP_R bit in the option byte. ● In ROM devices it is enabled by mask option specified in the option list. Flash write/erase protection Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to EEPROM data. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. Write/erase protection is enabled through the FMP_W bit in the option byte. Caution: Once set, write/erase protection can never be removed. A write-protected Flash device is no longer reprogrammable. 4.6 Related documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash programming reference manual and to the ST7 ICC protocol reference manual. 4.7 Description of Flash control/status register (FCSR) This register controls the XFlash erasing and programming using ICP, IAP or other programming methods. 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh) When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically. Reset value: 000 0000 (00h) 7 0 0 0 0 0 0 OPT LAT PGM Read/write Doc ID 13562 Rev 3 23/188 Data EEPROM ST7LITE49M 5 Data EEPROM 5.1 Introduction The electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 5.2 Main features ● Up to 32 bytes programmed in the same cycle ● EEPROM mono-voltage (charge pump) ● Chained erase and programming cycles ● Internal control of the global programming cycle duration ● Wait mode management ● Read-out protection Figure 6. EEPROM block diagram HIGH VOLTAGE PUMP EECSR 0 0 0 0 ADDRESS DECODER 0 4 0 E2LAT E2PGM EEPROM MEMORY MATRIX (1 ROW = 32 x 8 BITS) ROW DECODER 128 4 128 DATA MULTIPLEXER 32 x 8 BITS DATA LATCHES 4 ADDRESS BUS 24/188 DATA BUS Doc ID 13562 Rev 3 ST7LITE49M 5.3 Data EEPROM Memory access The data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these different memory access modes. 5.3.1 Read operation (E2LAT=0) The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared. On this device, data EEPROM can also be used to execute machine code. Take care not to write to the data EEPROM while executing from it. This would result in an unexpected code being executed. 5.3.2 Write operation (E2LAT=1) To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the 32 data latches according to its address. When PGM bit is set by the software, all the previous bytes written in the data latches (up to 32) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five Least Significant Bits of the address can change. At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously. Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit. It is not possible to read the latched data (see Figure 9). Figure 7. Data EEPROM programming flowchart READ MODE E2LAT=0 E2PGM=0 READ BYTES IN EEPROM AREA WRITE MODE E2LAT=1 E2PGM=0 WRITE UP TO 32 BYTES IN EEPROM AREA (with the same 11 MSB of the address) START PROGRAMMING CYCLE E2LAT=1 E2PGM=1 (set by software) 0 E2LAT 1 CLEARED BY HARDWARE Doc ID 13562 Rev 3 25/188 Data EEPROM ST7LITE49M Figure 8. Data EEPROM write operation ROW DEFINITION ⇓ Row / byte ⇒ 0 1 2 3 ... 30 31 Physical Address 0 00h...1Fh 1 20h...3Fh ... N Nx20h...Nx20h+1Fh Read operation impossible Byte 1 E2LAT bit Byte 2 Byte 32 Read operation possible Programming cycle PHASE 1 PHASE 2 Writing data latches Waiting E2PGM and E2LAT to fall Set by USER application Cleared by hardware E2PGM bit 1. If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed. 5.4 Power saving modes 5.4.1 Wait mode The data EEPROM can enter Wait mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-halt mode.The data EEPROM will immediately enter this mode if there is no programming in progress, otherwise the data EEPROM will finish the cycle and then enter Wait mode. 5.4.2 Active-halt mode Refer to Wait mode. 5.4.3 Halt mode The data EEPROM immediately enters Halt mode if the microcontroller executes the Halt instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted. 5.5 Access error handling If a read access occurs while E2LAT=1, then the data bus will not be driven. If a write access occurs while E2LAT=0, then the data on the bus will not be latched. If a programming cycle is interrupted (by a RESET action), the integrity of the data in memory will not be guaranteed. 26/188 Doc ID 13562 Rev 3 ST7LITE49M 5.6 Data EEPROM Data EEPROM read-out protection The read-out protection is enabled through an option bit (see Section 14.1: Option bytes). When this option is selected, the programs and data stored in the EEPROM memory are protected against Read-out (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the option byte, the entire Program memory and EEPROM is first automatically erased. Note: Both program memory and data EEPROM are protected using the same option bit. Figure 9. Data EEPROM programming cycle READ OPERATION NOT POSSIBLE Internal Programming voltage ERASE CYCLE WRITE OF DATA LATCHES READ OPERATION POSSIBLE WRITE CYCLE tPROG LAT PGM 5.7 EEPROM control/status register (EECSR) Address: 0035h Reset value: 0000 0000 (00h) 7 0 0 0 0 0 0 0 E2LAT E2PGM Read/write Bits 7:2 = Reserved, forced by hardware to 0 0: Read mode 1: Write mode Bit 1 = E2LAT Latch access transfer bit: this bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared Bit 0 = E2PGM Programming control and status bit This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware. 0: Programming finished or not yet started 1: Programming cycle is in progress Note: If the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed. Doc ID 13562 Rev 3 27/188 Central processing unit ST7LITE49M 6 Central processing unit 6.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation. 6.2 6.3 Main features ● 63 basic instructions ● Fast 8-bit by 8-bit multiply ● 17 main addressing modes ● Two 8-bit index registers ● 16-bit stack pointer ● Low power modes ● Maskable hardware interrupts ● Non-maskable software interrupt CPU registers The six CPU registers shown in Figure 10. They are not present in the memory mapping and are accessed by specific instructions. Figure 10. CPU registers 7 0 ACCUMULATOR RESET VALUE = XXh 7 0 X INDEX REGISTER RESET VALUE = XXh 7 0 Y INDEX REGISTER RESET VALUE = XXh 15 PCH 8 7 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 1 1 1 H I N Z C CONDITION CODE REGISTER RESET VALUE = 1 1 1 X 1 X X X 15 8 7 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 28/188 Doc ID 13562 Rev 3 ST7LITE49M 6.3.1 Central processing unit Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 6.3.2 Index registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). 6.3.3 Program counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is the LSB) and PCH (program counter high which is the MSB). 6.3.4 Condition code register (CC) The 8-bit condition code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. Reset value: 111x 1xxx 7 1 0 1 I1 H I0 N Z C Read/write These bits can be individually tested and/or controlled by specific instructions. Arithmetic management bits Bit 4 = H Half carry bit This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Doc ID 13562 Rev 3 29/188 Central processing unit ST7LITE49M Bit 3 = I Interrupt mask bit This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative bit This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero bit This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow bit This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. Interrupt management bits Bits 5,3 = I1, I0 Interrupt bits The combination of the I1 and I0 bits gives the current interrupt software priority. These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See Section 10.6: Interrupts for more details. 30/188 Doc ID 13562 Rev 3 ST7LITE49M Central processing unit * Table 4. 6.3.5 Interrupt software priority truth table Interrupt software priority I1 I0 Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1 Stack pointer (SP) Reset value: 01FFh 15 0 0 0 0 0 0 0 8 7 1 1 0 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Read/write The stack pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11). Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU reset, or after a reset stack pointer instruction (RSP), the stack pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address. The least significant byte of the stack pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11. ● When an interrupt is received, the SP is decremented and the context is pushed on the stack. ● On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. Doc ID 13562 Rev 3 31/188 Central processing unit ST7LITE49M Figure 11. Stack manipulation example CALL Subroutine PUSH Y Interrupt Event POP Y RET or RSP IRET @ 0180h SP SP CC A SP X X X PCH PCH PCL PCL PCL PCH PCH PCH PCH PCH PCL PCL PCL PCL PCL Stack Higher Address = 01FFh Stack Lower Address = 0180h 32/188 CC A PCH SP @ 01FFh Y CC A Doc ID 13562 Rev 3 SP SP ST7LITE49M 7 Supply, reset and clock management Supply, reset and clock management The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. The main features are the following: ● Clock management – 8 MHz internal RC oscillator (enabled by option byte) – Auto-wakeup RC oscillator (enabled by option byte) – 1 to 16 MHz or 32 kHz External crystal/ceramic resonator (selected by option byte) – External clock input (enabled by option byte) ● Reset sequence manager (RSM) ● System integrity management (SI) – Main supply low voltage detection (LVD) with reset generation (enabled by option byte) – Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main supply (enabled by option byte) 7.1 RC oscillator adjustment 7.1.1 Internal RC oscillator The device contains an internal RC oscillator with a specific accuracy for a given device, temperature and voltage range (4.5 V - 5.5 V). It must be calibrated to obtain the frequency required in the application. This is done by software writing a 10-bit calibration value in the RCCR (RC control register) and in the bits 6:5 in the SICSR (SI control status register). Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in EEPROM for 3 and 5 V VDD supply voltages at 25 °C (see Table 5). Table 5. Predefined RC oscillator calibration values ST7LITE49M RCCR Conditions RCCRH0 VDD= 5V TA= 25°C fRC = 8 MHz DEE0h(1) (CR[9:2]) VDD = 3.3 V TA= 25°C fRC = 8 MHz DEE2h(1) (CR[9:2]) RCCRL0 RCCRH1 RCCRL1 Address DEE1h(1) (CR[1:0]) DEE3h(1) (CR[1:0]) 1. The DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area in non-volatile memory. They are read-only bytes for the application code. This area cannot be erased or programmed by any ICC operations. For compatibility reasons with the SICSR register, CR[1:0] bits are stored in the 5th and 6th position of DEE1 and DEE3 addresses. Doc ID 13562 Rev 3 33/188 Supply, reset and clock management ST7LITE49M In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. Section 13: Electrical characteristics on page 139 for more information on the frequency and accuracy of the RC oscillator. To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100 nF, between the VDD and VSS pins and also between the VDDA and VSSA pins as close as possible to the ST7 device. These bytes are systematically programmed by ST, including on FASTROM devices. Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN1324 for information on how to calibrate the RC frequency using an external reference signal. 7.1.2 Auto-wakeup RC oscillator The ST7LITE49M also contains an Auto-wakeup RC oscillator. This RC oscillator should be enabled to enter auto-wakeup from halt mode. The auto-wakeup (AWU) RC oscillator can also be configured as the startup clock through the CKSEL[1:0] option bits (see Section 14.1: Option bytes on page 173). This is recommended for applications where very low power consumption is required. Switching from one startup clock to another can be done in run mode as follows (see Figure 12): Case 1 Switching from internal RC to AWU 1. Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator 2. The RC_FLAG is cleared and the clock output is at 1. 3. Wait 3 AWU RC cycles till the AWU_FLAG is set 4. The switch to the AWU clock is made at the positive edge of the AWU clock signal 5. Once the switch is made, the internal RC is stopped Case 2 Switching from AWU RC to internal RC Note: 34/188 1. Reset the RC/AWU bit to enable the internal RC oscillator 2. Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is running on internal RC clock. 3. Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC cycles) 4. The switch to the internal RC clock is made at the positive edge of the internal RC clock signal 5. Once the switch is made, the AWU RC is stopped 1 When the internal RC is not selected, it is stopped so as to save power consumption. 2 When the internal RC is selected, the AWU RC is turned on by hardware when entering Auto-wakeup from Halt mode. 3 When the external clock is selected, the AWU RC oscillator is always on. Doc ID 13562 Rev 3 ST7LITE49M Supply, reset and clock management Figure 12. Clock switching Internal RC Set RC/AWU AWU RC Poll AWU_FLAG until set Reset RC/AWU AWU RC Internal RC Poll RC_FLAG until set Figure 13. Clock management block diagram CK2 CK1 CR9 CK0 CR8 CR7 CR6 CR5 CR1 CR4 CR3 CR2 RCCR CR0 Tunable RC Oscillator RC/AWUCKCNTCSR 8 MHz (fRC) Prescaler 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz CLKSEL[1:0] Option bits CLKIN OSC2 AWU RC OSC Clock controller RC OSC CLKIN CLKIN CLKIN /OSC1 12-BIT AT TIMER 2 fCPU OSC 1-16 MHz or 32kHz fOSC /2 DIVIDER CLKIN/2 OSC /2 DIVIDER CLKIN/2 OSC/2 CLKSEL[1:0] Option bits 8-BIT LITE TIMER 2 COUNTER fOSC /32 DIVIDER fOSC/32 fOSC 1 0 fLTIMER (1ms timebase @ 8 MHz fOSC) fCPU TO CPU AND PERIPHERALS MCO SMS MCCSR fCPU Doc ID 13562 Rev 3 MCO 35/188 Supply, reset and clock management 7.2 ST7LITE49M Multi-oscillator (MO) The main clock of the ST7 can be generated by four different source types coming from the multi-oscillator block (1 to 16 MHz): ● An external source ● 5 different configurations for crystal or ceramic resonator oscillators ● An internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 6. Refer to the electrical characteristics section for more details. 7.2.1 External clock source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Note: When the Multi-Oscillator is not used OSCI1 and OSCI2 must be tied to ground, and PB1 is selected by default as the external clock. 7.2.2 Crystal/ceramic oscillators In this mode, with a self-controlled gain feature, oscillator of any frequency from 1 to 16 MHz can be placed on OSC1 and OSC2 pins. This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. 7.2.3 Internal RC oscillator In this mode, the tunable 1% RC oscillator is used as main clock source. The two oscillator pins have to be tied to ground. The calibration is done through the RCCR[7:0] and SICSR[6:5] registers. 36/188 Doc ID 13562 Rev 3 ST7LITE49M Supply, reset and clock management Table 6. ST7 clock sources External Clock Hardware configuration ST7 OSC1 OSC2 EXTERNAL Crystal/Ceramic Resonators SOURCE ST7 OSC1 CL1 OSC2 CL2 LOAD Internal RC Oscillator CAPACITORS ST7 OSC1 7.3 Reset sequence manager (RSM) 7.3.1 Introduction OSC2 The reset sequence manager includes three RESET sources as shown in Figure 15: Note: ● External RESET source pulse ● Internal LVD RESET (low voltage detection) ● Internal WATCHDOG RESET A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Section 12.2.1 on page 136 for further details. These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory mapping. The basic RESET sequence consists of 3 phases as shown in Figure 14: ● Active phase depending on the RESET source ● 256 CPU clock cycle delay (see Table 7) Doc ID 13562 Rev 3 37/188 Supply, reset and clock management Caution: ST7LITE49M When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior. The 256 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the reset state. The shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte. The reset vector fetch phase duration is 2 clock cycles. Table 7. CPU clock delay during reset sequence Clock source CPU clock cycle delay Internal RC 8 MHz oscillator 4096 Internal RC 32 kHz oscillator 256 External clock (connected to CLKIN/PB1 pin) 4096 External crystal/ceramic oscillator (connected to OSC1/OSC2 pins) 4096 External crystal/ceramic 1-16 MHz oscillator 4096 External crystal/ceramic 32 kHz oscillator 256 Figure 14. Reset sequence phases RESET active phase 38/188 Internal reset 256 or 4096 clock cycles Doc ID 13562 Rev 3 Fetch vector ST7LITE49M 7.3.2 Supply, reset and clock management Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristics section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 16: Reset sequences). This detection is asynchronous and therefore the MCU can enter reset state even in Halt mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. Figure 15. Reset block diagram VDD RON INTERNAL RESET Filter RESET PULSE GENERATOR ___ WATCHDOG RESET ___ ILLEGAL OPCODE RESET 1) ___ LVD RESET 1. See Section 12.2.1: Illegal opcode reset on page 136 for more details on illegal opcode reset conditions. 7.3.3 External power-on reset If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 7.3.4 Internal low voltage detector (LVD) reset Two different reset sequences caused by the internal LVD circuitry can be distinguished: ● Power-on reset ● Voltage drop reset The device RESET pin acts as an output that is pulled low when VDD is lower than VIT+ (rising edge) or VDD lower than VIT- (falling edge) as shown in Figure 16. The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets. Doc ID 13562 Rev 3 39/188 Supply, reset and clock management 7.3.5 ST7LITE49M Internal watchdog reset The reset sequence generated by an internal watchdog counter overflow is shown in Figure 16: Reset sequences Starting from the watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 16. Reset sequences VDD VIT+(LVD) VIT-(LVD) RUN LVD RESET RUN ACTIVE PHASE EXTERNAL RESET ACTIVE PHASE WATCHDOG RESET RUN ACTIVE PHASE RUN tw(RSTL)out th(RSTL)in EXTERNAL RESET SOURCE RESET PIN WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH 40/188 Doc ID 13562 Rev 3 ST7LITE49M 7.4 Supply, reset and clock management System integrity management (SI) The system integrity management block contains the low voltage detector (LVD) and auxiliary voltage detector (AVD) functions. It is managed by the SICSR register. Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Section 12.2.1 on page 136 for further details. 7.4.1 Low voltage detector (LVD) The low voltage detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD reset circuitry generates a reset when VDD is below: ● VIT+(LVD) when VDD is rising ● VIT-(LVD) when VDD is falling The LVD function is illustrated in Figure 17. The voltage threshold can be configured by option byte to be low, medium or high. See Section 14.1 on page 173. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD), the MCU can only be in two modes: ● Under full software control ● In static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Note: Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull VDD down to 0 V to ensure optimum restart conditions. Refer to circuit example in Figure 96 on page 169 and note 4. The LVD is an optional function which can be selected by option byte. See Section 14.1 on page 173. It allows the device to be used without any external RESET circuitry. If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from reset, to ensure the application functions properly. Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD levels are not correlated. Refer to section Section 13.3.2 on page 142 and Section 13.3.3 on page 143 for more details. Caution: If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will clear the watchdog flag. Doc ID 13562 Rev 3 41/188 Supply, reset and clock management ST7LITE49M Figure 17. Low voltage detector vs reset VDD Vhys VIT+(LVD) VIT-(LVD) RESET Figure 18. Reset and supply management block diagram WATCHDOG TIMER (WDG) RESET RESET SEQUENCE MANAGER (RSM) STATUS FLAG SYSTEM INTEGRITY MANAGEMENT AVD Interrupt Request SICSR 0 CR1 CR0 WDGF 0 LVDRF AVDF AVDIE LOW VOLTAGE DETECTOR (LVD) VSS VDD AUXILIARY VOLTAGE DETECTOR (AVD) 7.4.2 Auxiliary voltage detector (AVD) The voltage detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply voltage (VAVD). The VIT-(AVD) reference value for falling voltage is lower than the VIT+(AVD) reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly readable by the application software through a real-time status bit (AVDF) in the SICSR register. This bit is read only. Monitoring the VDD main supply The AVD threshold is selected by the AVD[1:0] bits in the AVDTHCR register. If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit is set). In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 19. The interrupt on the rising edge is used to inform the application that the VDD warning state is over. 42/188 Doc ID 13562 Rev 3 ST7LITE49M Note: Supply, reset and clock management Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD levels are not correlated. Refer to Section 13.3.2 on page 142 and Section 13.3.3 on page 143 for more details. Figure 19. Using the AVD to monitor VDD VDD Early Warning Interrupt (Power has dropped, MCU not not yet in reset) Vhyst VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD) AVDF bit 0 1 RESET 0 1 AVD INTERRUPT REQUEST IF AVDIE bit = 1 INTERRUPT Cleared by reset LVD RESET 7.4.3 INTERRUPT Cleared by hardware Low power modes Table 8. Low power modes Mode Description Wait No effect on SI. AVD interrupts cause the device to exit from Wait mode. Halt The SICSR register is frozen. The AVD remains active but the AVD interrupt cannot be used to exit from Halt mode. Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction). Table 9. Description of interrupt events Interrupt event Event flag Enable Control bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No Doc ID 13562 Rev 3 43/188 Supply, reset and clock management ST7LITE49M 7.5 Register description 7.5.1 Main clock control/status register (MCCSR) Reset value: 0000 0000 (00h) 7 0 0 0 0 0 0 0 MCO SMS Read/write Bits 7:2 = Reserved, must be kept cleared. Bit 1 = MCO Main clock out enable bit This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock. 0: MCO clock disabled, I/O port free for general purpose I/O. 1: MCO clock enabled. Bit 0 = SMS Slow mode selection bit This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock fOSC or fOSC/32. 0: Normal mode (fCPU = fOSC 1: Slow mode (fCPU = fOSC/32) 7.5.2 RC control register (RCCR) Reset value: 1111 1111 (FFh) 7 CR9 0 CR8 CR7 CR6 CR5 CR4 CR3 CR2 Read/write Bits 7:0 = CR[9:2] RC oscillator frequency adjustment bits These bits must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. The application can store the correct value for each voltage range in Flash memory and write it to this register at start-up. 00h = maximum available frequency FFh = lowest available frequency These bits are used with the CR[1:0] bits in the SICSR register. Refer to Chapter 7.5.3. Note: 44/188 To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h. Doc ID 13562 Rev 3 ST7LITE49M 7.5.3 Supply, reset and clock management System integrity (SI) control/status register (SICSR) Reset value: 011x 0x00 (xxh) 7 0 0 CR1 CR0 WDGRF 0 LVDRF AVDF AVDIE Read/write Bit 7 = Reserved, must be kept cleared Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. Refer to Section 7.1.1: Internal RC oscillator on page 33. Bit 4 = WDGRF Watchdog reset flag This bit indicates that the last reset was generated by the watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). The WDGRF and the LVDRF flags areis used to select the reset source (see Table 10: Reset source selection on page 45). Table 10. Reset source selection RESET source LVDRF WDGRF External RESET pin 0 0 Watchdog 0 1 LVD 1 X Bit 3 = Reserved, must be kept cleared Bit 2 = LVDRF LVD reset flag This bit indicates that the last reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled by option byte, the LVDRF bit value is undefined. The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not. Bit 1 = AVDF Voltage detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit is set. Refer to Figure 19 and to Section for additional details. 0: VDD over AVD threshold 1: VDD under AVD threshold Doc ID 13562 Rev 3 45/188 Supply, reset and clock management ST7LITE49M Bit 0 = AVDIE Voltage detector interrupt enable bit This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled 7.5.4 AVD threshold selection register (AVDTHCR) Reset value: 0000 0000 (00h) 7 CK2 0 CK1 CK0 0 0 0 AVD1 AVD0 Read/write Bits 7:5 = CK[2:0] internal RC prescaler selection These bits are set by software and cleared by hardware after a reset. These bits select the prescaler of the internal RC oscillator. See Figure 13: Clock management block diagram on page 35 and Table 11. If the internal RC is used with a supply operating range below 3.3 V, a division ratio of at least 2 must be enabled in the RC prescaler. Table 11. Internal RC prescaler selection bits CK2 CK1 CK0 fOSC 0 0 1 fRC/2 0 1 0 fRC/4 0 1 1 fRC/8 1 0 0 fRC/16 others fRC Bits 4:2 = Reserved, must be cleared. Bits 1:0 = AVD[1:0] AVD threshold selection. These bits are used to select the AVD threshold. They are set and cleared by software. They are set by hardware after a reset. Table 12. 46/188 AVD threshold selection bits AVD1 AVD0 Functionality 0 0 Low 0 1 Medium 1 0 High 1 1 AVD off Doc ID 13562 Rev 3 ST7LITE49M 7.5.5 Supply, reset and clock management Clock controller control/status register (CKCNTCSR) Reset value: 0000 1001 (09h) 7 0 0 0 0 0 AWU_FLAG RC_FLAG 0 RC/AWU Read/write Bits 7:4 = Reserved, must be kept cleared. Bit 3 = AWU_FLAG AWU selection bit This bit is set and cleared by hardware. 0: No switch from AWU to RC requested 1: AWU clock activated and temporization completed Bit 2 = RC_FLAG RC selection bit This bit is set and cleared by hardware. 0: No switch from RC to AWU requested 1: RC clock activated and temporization completed Bit 1 = Reserved, must be kept cleared. Bit 0 = RC/AWU RC/AWU selection bit 0: RC enabled 1: AWU enabled (default value) Table 13. Address Clock register mapping and reset values Register label 7 6 5 4 3 2 1 0 003Ah MCCSR Reset value 0 0 0 0 0 0 MCO 0 SMS 0 003Bh RCCR Reset value CR9 1 CR8 1 CR7 1 CR6 1 CR5 1 CR4 1 CR3 1 CR2 1 003Ch SICSR Reset value 0 CR1 1 CR0 1 WDGRF 0 0 LVDRF x AVDF x AVDIE x 003Dh AVDTHCR Reset value CK2 0 CK1 0 CK0 0 0 0 0 AVD1 0 AVD0 0 0051h CKCNTCSR Reset value 0 0 0 0 AWU_ FLAG 1 RC_FLA G 0 0 RC/AWU 1 (Hex.) Doc ID 13562 Rev 3 47/188 Interrupts ST7LITE49M 8 Interrupts 8.1 Introduction The ST7 enhanced interrupt management provides the following features: ● Hardware interrupts ● Software interrupt (TRAP) ● Nested or concurrent interrupt management with flexible interrupt priority and level management: – Up to 4 software programmable nesting levels – 13 interrupt vectors fixed by hardware – 2 non maskable events: RESET, TRAP This interrupt management is based on: ● Bit 5 and bit 3 of the CPU CC register (I1:0), ● Interrupt software priority registers (ISPRx), ● Fixed interrupt vector addresses located at the high addresses of the memory mapping (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller. 8.2 Masking and processing flow The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 14). The processing flow is shown in Figure 20. When an interrupt request has to be serviced: ● Normal processing is suspended at the end of the current instruction execution. ● The PC, X, A and CC registers are saved onto the stack. ● I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. ● The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to interrupt mapping table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: 48/188 As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Doc ID 13562 Rev 3 ST7LITE49M Table 14. Interrupts Interrupt software priority levels Interrupt software priority Level Level 0 (main) I1 I0 1 0 Low Level 1 1 0 Level 2 0 High Level 3 (= interrupt disable) 1 1 Figure 20. Interrupt processing flowchart Y Interrupt has the same or a lower software priority than current one N FETCH NEXT INSTRUCTION Y “IRET” N RESTORE PC, X, A, CC FROM STACK TLI EXECUTE INSTRUCTION THE INTERRUPT STAYS PENDING Y N I1:0 Interrupt has a higher software priority than current one PENDING INTERRUPT RESET STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR Doc ID 13562 Rev 3 49/188 Interrupts 8.2.1 ST7LITE49M Servicing pending interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: ● The highest software priority interrupt is serviced, ● If several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 21 describes this decision process. Figure 21. Priority decision process PENDING INTERRUPTS Same SOFTWARE PRIORITY Different HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note: 8.2.2 1 The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. 2 RESET and TRAP can be considered as having the highest software priority in the decision process. Interrupt vector sources Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals). Non-maskable sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 20). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit Halt mode. ● TRAP (non maskable software interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 20. ● RESET The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details. 50/188 Doc ID 13562 Rev 3 ST7LITE49M Interrupts Maskable sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. ● External interrupts External interrupts allow the processor to exit from Halt low power mode. External interrupt sensitivity is software selectable through the external interrupt control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed. ● Peripheral interrupts Usually the peripheral interrupts cause the MCU to exit from Halt mode except those mentioned in Table 18: ST7LITE49M interrupt mapping. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being serviced) will therefore be lost if the clear sequence is executed. 8.3 Interrupts and low power modes All interrupts allow the processor to exit the Wait low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the Halt modes (see column “Exit from Halt” in Table 18: ST7LITE49M interrupt mapping). When several pending interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt with exit from Halt mode capability and it is selected through the same decision process shown in Figure 21. Note: If an interrupt, that is not able to Exit from Halt mode, is pending with the highest priority when exiting Halt mode, this interrupt is serviced after the first one serviced. Doc ID 13562 Rev 3 51/188 Interrupts 8.4 ST7LITE49M Concurrent and nested management The following Figure 22 and Figure 23 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 23. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT5, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt. Caution: A stack overflow may occur without notifying the software of the failure. IT1 IT0 IT4 IT5 IT2 SOFTWARE PRIORITY LEVEL IT0 IT1 IT2 IT2 IT3 IT4 RIM IT5 MAIN MAIN 11 / 10 I1 I0 3 1 1 3 1 1 3 1 1 3 1 1 3 1 1 3 1 1 USED STACK = 10 BYTES HARDWARE PRIORITY IT3 Figure 22. Concurrent interrupt management 3/0 10 IT1 IT0 IT4 IT5 IT2 SOFTWARE PRIORITY LEVEL TLI IT0 IT1 IT1 IT2 IT2 IT3 RIM IT4 IT4 MAIN MAIN 11 / 10 52/188 10 Doc ID 13562 Rev 3 I1 I0 3 1 1 3 1 1 2 0 0 1 0 1 3 1 1 3 1 1 3/0 USED STACK = 20 BYTES HARDWARE PRIORITY IT3 Figure 23. Nested interrupt management ST7LITE49M Interrupts 8.5 Description of interrupt registers 8.5.1 CPU CC register interrupt bits Reset value: 111x 1010(xAh) 7 1 0 1 I1 H I0 N Z C Read/write Bits 5, 3 = I1, I0 Software interrupt priority bits These two bits indicate the current interrupt software priority (see Table 15). These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see Table 17: Dedicated interrupt instruction set). TRAP and RESET events can interrupt a level 3 program. Table 15. Setting the interrupt software priority Interrupt software priority Level Level 0 (main) I1 I0 1 0 Low Level 1 1 0 Level 2 0 High Level 3 (= interrupt disable*) 8.5.2 1 1 Interrupt software priority registers (ISPRx) All ISPRx register bits are read/write except bit 7:4 of ISPR3 which are read only. Reset value: 1111 1111 (FFh) 7 0 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0 ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4 ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8 ISPR3 1 1 1 1 1 1 I1_12 I0_12 ISPRx registers contain the interrupt software priority of each interrupt vector. Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers to define its software priority. This correspondence is shown in Table 16. Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. Doc ID 13562 Rev 3 53/188 Interrupts ST7LITE49M The RESET and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is kept (Example: previous = CFh, write = 64h, result = 44h). Table 16. Interrupt vector vs. ISPRx bits Vector address ISPRx bits FFFBh-FFFAh I1_0 and I0_0 bits(1) FFF9h-FFF8h I1_1 and I0_1 bits ... ... FFE1h-FFE0h I1_13 and I0_13 bits 1. Bits in the ISPRx registers can be read and written but they are not significant in the interrupt process management. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x). Table 17. Dedicated interrupt instruction set(1) Instruction New description Function/example HALT Entering Halt mode IRET Interrupt routine return Pop CC, A, X, PC JRM Jump if I1:0 = 11 (level 3) I1:0 = 11 JRNM Jump if I1:0 11 I1:0 11 POP CC Pop CC from the stack RIM I1 H 1 I0 N Z C 0 I1 H I0 N Z C Mem => CC I1 H I0 N Z C Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0 SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1 TRAP Software trap Software NMI 1 1 WFI Wait for interrupt 1 0 1. During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions. 54/188 Doc ID 13562 Rev 3 ST7LITE49M Table 18. Number Interrupts ST7LITE49M interrupt mapping Source block Description Register label Exit from Priority HALT order or AWUFH Address vector (1) RESET Reset yes FFFEh-FFFFh Software interrupt no FFFCh-FFFDh Auto-wakeup interrupt yes(2) FFFAh-FFFBh no FFF8h-FFF9h N/A TRAP 0 AWU 1 AVD Auxiliary voltage detector interrupt 2 ei0 External interrupt 0 (Port A) 3 ei1 External interrupt 1 (Port B) 4 ei2 External interrupt 2 (Port C) 5 I 2C 10 (3) 12 yes FFF0h-FFF1h no FFEEh-FFEFh AT timer overflow 1 interrupt no FFECh-FFEDh AT timer Overflow 2 interrupt no FFEAh-FFEBh no FFE8h-FFE9h yes FFE6h-FFE7h no FFE4h-FFE5h no FFE2h-FFE3h ATCSR I2C interrupt N/A Lowest Priority Lite timer RTC interrupt LITE TIMER FFF4h-FFF5h FFF2h-FFF3h AT timer input capture interrupt 8 11 FFF6h-FFF7 N/A no AT TIMER 7 9 N/A Highest Priority AT timer output compare interrupt 6 (3) AWUCSR Lite timer Input Capture interrupt LTCSR2 Lite timer RTC2 interrupt 1. For an interrupt, all events do not have the same capability to wake up the MCU from Halt, Active-halt or Auto-wakeup from Halt modes. Refer to the description of interrupt events for more details. 2. This interrupt exits the MCU from Auto Wake-up from Halt mode only. 3. These interrupts exit the MCU from Active-halt mode only. Doc ID 13562 Rev 3 55/188 Interrupts 8.5.3 ST7LITE49M External interrupt control register (EICR) Reset value: 0000 0000 (00h) 7 0 0 0 IS21 IS20 IS11 IS10 IS01 IS00 Read/write Bits 7:6 = Reserved, must be kept cleared. Bits 5:4 = IS2[1:0] ei2 sensitivity bits These bits define the interrupt sensitivity for ei2 (Port C) according to Table 19. Bits 3:2 = IS1[1:0] ei1 sensitivity bits These bits define the interrupt sensitivity for ei1 (Port B) according to Table 19. Bits 1:0 = IS0[1:0] ei0 sensitivity bits These bits define the interrupt sensitivity for ei0 (Port A) according to Table 19. Note: 1 These 8 bits can be written only when the I bit in the CC register is set. 2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Refer to Section : External interrupt function. Table 19. 56/188 Interrupt sensitivity bits ISx1 ISx0 External interrupt sensitivity 0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge Doc ID 13562 Rev 3 ST7LITE49M Power saving modes 9 Power saving modes 9.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 24): ● Slow ● Wait (and Slow-wait) ● Active-halt ● Auto-wakeup from Halt (AWUFH) ● Halt After a reset the normal operating mode is selected by default (Run mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency (fOSC). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 24. Power saving mode transitions High Run Slow Wait Slow Wait Active Halt Halt Low POWER CONSUMPTION Doc ID 13562 Rev 3 57/188 Power saving modes 9.2 ST7LITE49M Slow mode This mode has two targets: ● To reduce power consumption by decreasing the internal clock in the device, ● To adapt the internal clock frequency (fCPU) to the available supply voltage. Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables Slow mode. In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked at this lower frequency. Note: Slow-wait mode is activated when entering Wait mode while the device is already in Slow mode. Figure 25. Slow mode clock transition fOSC/32 fOSC fCPU fOSC SMS NORMAL RUN MODE REQUEST 9.3 Wait mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During Wait mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. The MCU will remain in Wait mode until a reset or an interrupt occurs, causing it to wake up. Refer to Figure 26 for a description of the Wait mode flowchart. 58/188 Doc ID 13562 Rev 3 ST7LITE49M Power saving modes Figure 26. Wait mode flowchart WFI INSTRUCTION OSCILLATOR PERIPHERALS CPU I BIT ON ON OFF 0 N RESET Y N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I BIT ON OFF ON 0 256 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I BIT ON ON ON X 1) FETCH RESET VECTOR OR SERVICE INTERRUPT 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 9.4 Active-halt and Halt modes Active-halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Activehalt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following table: Table 20. Enabling/disabling Active-halt and Halt modes LTCSR TBIE bit ATCSR OVFIE ATCSRCK1 bit ATCSRCK0 bit bit 0 x x 0 0 0 x x 0 1 1 1 1 x x x x 1 0 1 Meaning Active-halt mode disabled Active-halt mode enabled Doc ID 13562 Rev 3 59/188 Power saving modes 9.4.1 ST7LITE49M Active-halt mode Active-halt mode is the lowest power consumption mode of the MCU with a real-time clock available. It is entered by executing the ‘HALT’ instruction when Active-halt mode is enabled. The MCU can exit Active-halt mode on reception of a Lite timer/ AT timer interrupt or a reset. ● When exiting Active-halt mode by means of a reset, a 256 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by fetching the reset vector which woke it up (see Figure 28). ● When exiting Active-halt mode by means of an interrupt, the CPU immediately resumes operation by servicing the interrupt vector which woke it up (see Figure 28). When entering Active-halt mode, the I bit in the CC register is cleared to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In Active-halt mode, only the main oscillator and the selected timer counter (LT/AT) are running to keep a wakeup time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). Caution: As soon as Active-halt is enabled, executing a HALT instruction while the watchdog is active does not generate a reset if the WDGHALT bit is reset. This means that the device cannot spend more than a defined delay in this power saving mode. Figure 27. Active-halt timing overview RUN [Active-halt Enabled] ACTIVE HALT 256 CPU CYCLE DELAY 1) HALT INSTRUCTION RESET OR INTERRUPT RUN FETCH VECTOR 1. This delay occurs only if the MCU exits Active-halt mode by means of a RESET. 60/188 Doc ID 13562 Rev 3 ST7LITE49M Power saving modes Figure 28. Active-halt mode flowchart HALT INSTRUCTION (Active-halt enabled) OSCILLATOR ON PERIPHERALS 2) OFF CPU OFF I BIT 0 N RESET N Y INTERRUPT 3) Y OSCILLATOR ON PERIPHERALS 2) OFF CPU ON I BIT X 4) 256 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I BITS ON ON ON X 4) FETCH RESET VECTOR OR SERVICE INTERRUPT 1. This delay occurs only if the MCU exits Active-halt mode by means of a RESET. 2. Peripherals clocked with an external clock source can still be active. 3. Only the Lite timer RTC and AT timer interrupts can exit the MCU from Active-halt mode. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 9.4.2 Halt mode The Halt mode is the lowest power consumption mode of the MCU. It is entered by executing the HALT instruction when Active-halt mode is disabled. The MCU can exit Halt mode on reception of either a specific interrupt (see Table 18: ST7LITE49M interrupt mapping) or a reset. When exiting Halt mode by means of a reset or an interrupt, the main oscillator is immediately turned on and the 256 CPU cycle delay is used to stabilize it. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 30). When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately. In Halt mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of watchdog operation with Halt mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the watchdog system is enabled, can generate a watchdog reset (see Section 14.1: Option bytes for more details). Doc ID 13562 Rev 3 61/188 Power saving modes ST7LITE49M Figure 29. Halt timing overview RUN HALT HALT INSTRUCTION 256 CPU CYCLE DELAY RUN RESET OR INTERRUPT FETCH VECTOR [Active-halt disabled] 1. A reset pulse of at least 42 µs must be applied when exiting from Halt mode. Figure 30. Halt mode flowchart HALT INSTRUCTION (Active-halt disabled) ENABLE WDGHALT 1) WATCHDOG 0 DISABLE 1 WATCHDOG RESET OSCILLATOR OFF PERIPHERALS 2) OFF CPU OFF I BIT 0 N RESET N Y INTERRUPT 3) Y OSCILLATOR PERIPHERALS CPU I BIT ON OFF ON X 4) 256 CPU CLOCK CYCLE DELAY 5) OSCILLATOR PERIPHERALS CPU I BITS ON ON ON X 4) FETCH RESET VECTOR OR SERVICE INTERRUPT 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 18: ST7LITE49M interrupt mappingfor more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 5. The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode. 62/188 Doc ID 13562 Rev 3 ST7LITE49M Power saving modes Halt mode recommendations 9.5 ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. ● For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. ● The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a Program Counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. ● As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wakeup event (reset or external interrupt). Auto-wakeup from Halt mode Auto-wakeup from Halt (AWUFH) mode is similar to Halt mode with the addition of a specific internal RC oscillator for wakeup (Auto-wakeup from Halt oscillator) which replaces the main clock which was active before entering Halt mode. Compared to Active-halt mode, AWUFH has lower power consumption (the main clock is not kept running), but there is no accurate real-time clock available. It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set. Figure 31. AWUFH mode block diagram AWU RC oscillator fAWU_RC /64 divider to 8-bit timer input capture AWUFH prescaler/1 .. 255 Doc ID 13562 Rev 3 AWUFH interrupt (ei0 source) 63/188 Power saving modes ST7LITE49M As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the AWUPR register. The output of this prescaler provides the delay time. When the delay has elapsed, the following actions are performed: ● the AWUF flag is set by hardware, ● an interrupt wakes up the MCU from Halt mode, ● the main oscillator is immediately turned on and the 256 CPU cycle delay is used to stabilize it. After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU flag and its associated interrupt are cleared by software reading the AWUCSR register. To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency fAWU_RC and then calculating the right prescaler value. Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run mode. This connects fAWU_RC to the input capture of the 8-bit Lite timer, allowing the fAWU_RC to be measured using the main oscillator clock as a reference timebase. Similarities with Halt mode The following AWUFH mode behavior is the same as normal Halt mode: ● The MCU can exit AWUFH mode by means of any interrupt with exit from Halt capability or a reset (see Section 9.4: Active-halt and Halt modes). ● When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. ● In AWUFH mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator). ● The compatibility of watchdog operation with AWUFH mode is configured by the WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the watchdog system is enabled, can generate a watchdog reset. Figure 32. AWUF Halt timing diagram tAWU RUN MODE HALT MODE 256 tCPU RUN MODE fCPU fAWU_RC Clear by software AWUFH interrupt 64/188 Doc ID 13562 Rev 3 ST7LITE49M Power saving modes Figure 33. AWUFH mode flowchart HALT INSTRUCTION (Active-Halt disabled) (AWUCSR.AWUEN=1) ENABLE WDGHALT 1) WATCHDOG DISABLE 0 1 WATCHDOG RESET AWU RC OSC ON MAIN OSC OFF 2) PERIPHERALS OFF CPU OFF I[1:0] BITS 10 N RESET N Y INTERRUPT 3) Y AWU RC OSC OFF MAIN OSC ON PERIPHERALS OFF CPU ON I[1:0] BITS XX 4) 256 CPU CLOCK CYCLE DELAY AWU RC OSC OFF MAIN OSC ON PERIPHERALS ON CPU ON I[1:0] BITS XX 4) FETCH RESET VECTOR OR SERVICE INTERRUPT 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 18: ST7LITE49M interrupt mapping for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. Doc ID 13562 Rev 3 65/188 Power saving modes ST7LITE49M 9.5.1 Register description 9.5.2 AWUFH control/status register (AWUCSR) Reset value: 0000 0000 (00h) 7 0 0 0 0 0 0 AWU F AWUM AWUEN Read/Write Bits 7:3 = Reserved Bit 2 = AWUF Auto-wakeup flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value. 0: No AWU interrupt occurred 1: AWU interrupt occurred Bit 1 = AWUM Auto-wakeup measurement bit This bit enables the AWU RC oscillator and connects its output to the Input Capture of the 8-bit Lite timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compensate this dispersion by providing the right value in the AWUPRE register. 0: Measurement disabled 1: Measurement enabled Bit 0 = AWUEN Auto-wakeup from Halt enabled bit This bit enables the Auto-wakeup from halt feature: once Halt mode is entered, the AWUFH wakes up the microcontroller after a time delay dependent on the AWU prescaler value. It is set and cleared by software. 0: AWUFH (Auto-wakeup from Halt) mode disabled 1: AWUFH (Auto-wakeup from Halt) mode enabled Note: 66/188 Whatever the clock source, this bit should be set to enable the AWUFH mode once the HALT instruction has been executed. Doc ID 13562 Rev 3 ST7LITE49M 9.5.3 Power saving modes AWUFH prescaler register (AWUPR) Reset value: 1111 1111 (FFh) 7 0 AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0 Read/Write Bits 7:0= AWUPR[7:0] Auto-wakeup prescaler These 8 bits define the AWUPR dividing factor (see Table 21). Table 21. Configuring the dividing factor AWUPR[7:0] Dividing factor 00h Forbidden 01h 1 ... ... FEh 254 FFh 255 In AWU mode, the time during which the MCU stays in Halt mode, tAWU, is given by the equation below. See also Figure 32 on page 64. 1 t AWU = 64 × AWUPR × -------------------- + t RCSTRT f AWURC The AWUPR prescaler register can be programmed to modify the time during which the MCU stays in Halt mode before waking up automatically. Note: If 00h is written to AWUPR, the AWUPR remains unchanged. Table 22. AWU register mapping and reset values Address (Hex.) Register label 7 6 5 4 3 2 1 0 0048h AWUCSR Reset value 0 0 0 0 0 AWUF AWUM AWUEN 0049h AWUPR Reset value AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0 1 1 1 1 1 1 1 1 Doc ID 13562 Rev 3 67/188 I/O ports ST7LITE49M 10 I/O ports 10.1 Introduction The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include external interrupt, alternate signal input/output for on-chip peripherals or analog input. 10.2 Functional description A data register (DR) and a data direction register (DDR) are always associated with each port. The Option register (OR), which allows input/output options, may or may not be implemented. The following description takes into account the OR register. Refer to the port configuration table for device specific information. An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit x corresponding to pin x of the port. Figure 34 shows the generic I/O block diagram. 10.2.1 Input modes Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital value from that I/O pin. If an OR bit is available, different input modes can be configured by software: floating or pullup. Refer to I/O Port Implementation section for configuration. Note: 1 Writing to the DR modifies the latch value but does not change the state of the input pin. 2 Do not use read/modify/write instructions (BSET/BRES) to modify the DR register. External interrupt function Depending on the device, setting the ORx bit while in input mode can configure an I/O as an input with interrupt. In this configuration, a signal edge or level input on the I/O generates an interrupt request via the corresponding interrupt vector (eix). Falling or rising edge sensitivity is programmed independently for each interrupt vector. The External Interrupt Control register (EICR) or the Miscellaneous register controls this sensitivity, depending on the device. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. For this reason if one of the interrupt pins is tied low, it may mask the others. External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. 68/188 Doc ID 13562 Rev 3 ST7LITE49M I/O ports Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by the OR register. To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the OR register bit and configuring the appropriate sensitivity again. Caution: In case a pin level change occurs during these operations (asynchronous signal input), as interrupts are generated according to the current sensitivity, it is advised to disable all interrupts before and to reenable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge. This corresponds to the following steps: a) Set the interrupt mask with the SIM instruction (in cases where a pin level change could occur) b) Select rising edge c) Enable the external interrupt through the OR register d) Select the desired sensitivity if different from rising edge e) Reset the interrupt mask with the RIM instruction (in cases where a pin level change could occur) 2. To disable an external interrupt: a) 10.2.2 Set the interrupt mask with the SIM instruction SIM (in cases where a pin level change could occur) b) Select falling edge c) Disable the external interrupt through the OR register d) Select rising edge e) Reset the interrupt mask with the RIM instruction (in cases where a pin level change could occur) Output modes Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the I/O through the latch. Reading the DR bits returns the previously stored value. If an OR bit is available, different output modes can be selected by software: push-pull or open-drain. Refer to I/O Port Implementation section for configuration. Table 23. DR value and output pin status DR Push-pull Open-drain 0 VOL VOL 1 VOH Floating Doc ID 13562 Rev 3 69/188 I/O ports 10.2.3 ST7LITE49M Alternate functions Many ST7s I/Os have one or more alternate functions. These may include output signals from, or input signals to, on-chip peripherals.Table 2 describes which peripheral signals can be input/output to which ports. A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripheral’s control register). The peripheral configures the I/O as an output and takes priority over standard I/O programming. The I/O’s state is readable by addressing the corresponding I/O data register. Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this will increase current consumption. Before using an I/O as an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur. Configure an I/O as input floating for an on-chip peripheral signal which can be input and output. Caution: I/Os which can be configured as both an analog and digital alternate function need special attention. The user must control the peripherals so that the signals do not arrive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function. Figure 34. I/O port general block diagram ALTERNATE OUTPUT REGISTER ACCESS 1 From on-chip peripheral VDD 0 ALTERNATE ENABLE BIT P-BUFFER (see table below) PULL-UP (see table below) DR VDD DDR PULL-UP CONDITION DATA BUS OR PAD If implemented OR SEL N-BUFFER DIODES (see table below) DDR SEL DR SEL CMOS SCHMITT TRIGGER 1 0 EXTERNAL INTERRUPT REQUEST (eix) 70/188 ANALOG INPUT ALTERNATE INPUT Combinational Logic SENSITIVITY SELECTION To on-chip peripheral FROM OTHER BITS Note: Refer to the Port Configuration table for device specific information. Doc ID 13562 Rev 3 ST7LITE49M I/O ports Table 24. I/O port mode options (1) Diodes Configuration mode Pull-up Floating with/without Interrupt Off Pull-up with Interrupt On Input P-buffer to VDD to VSS On On Off Push-pull On Output Off Open-drain (logic level) Off 1. Off means implemented not activated, On means implemented and activated. Table 25. I/O port configuration Hardware configuration DR REGISTER ACCESS DR REGISTER INPUT (1) PAD W DATA BUS R ALTERNATE INPUT To on-chip peripheral FROM OTHER PINS EXTERNAL INTERRUPT SOURCE (eix) INTERRUPT COMBINATIONAL POLARITY LOGIC SELECTION CONDITION PUSH-PULL OUTPUT(2) OPEN-DRAIN OUTPUT(2) ANALOG INPUT DR REGISTER ACCESS PAD DR REGISTER R/W DATA BUS DR REGISTER ACCESS DR REGISTER PAD ALTERNATE ENABLE BIT R/W DATA BUS ALTERNATE OUTPUT From on-chip peripheral 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content. Doc ID 13562 Rev 3 71/188 I/O ports 10.2.4 ST7LITE49M Analog alternate function Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the ADC input. Analog Recommendations Do not change the voltage level or loading on any I/O while conversion is in progress. Do not have clocking pins located close to a selected analog pin. Caution: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 10.3 I/O port implementation The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific I/O port features such as ADC input or open-drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 35. Other transitions are potentially risky and should be avoided, since they may present unwanted side-effects such as spurious interrupt generation. Figure 35. Interrupt I/O port state transitions 01 00 10 11 INPUT floating/pull-up interrupt INPUT floating (reset state) OUTPUT open-drain OUTPUT push-pull XX 10.4 = DDR, OR Unused I/O pins Unused I/O pins must be connected to fixed voltage levels. Refer to Section 13.9: I/O port pin characteristics. 10.5 Low power modes s Table 26. 72/188 Effect of low power modes on I/O ports Mode Description Wait No effect on I/O ports. External interrupts cause the device to exit from Wait mode. Halt No effect on I/O ports. External interrupts cause the device to exit from Halt mode. Doc ID 13562 Rev 3 ST7LITE49M 10.6 I/O ports Interrupts The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction). Table 27. Description of interrupt events Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt External interrupt on selected external event - DDRx ORx Yes Yes See application notes AN1045 software implementation of I2C bus master, and AN1048 software LCD driver 10.7 Device-specific I/O port configuration The I/O port register configurations are summarized in Section 10.7.1: Standard ports and Section 10.7.2: Other ports. 10.7.1 Standard ports Table 28. 10.7.2 PA5:0, PB7:0, PC7:4 and PC2:0 pins Mode DDR OR floating input 0 0 pull-up interrupt input 0 1 open-drain output 1 0 push-pull output 1 1 Mode DDR OR floating input 0 0 interrupt input 0 1 open-drain output 1 0 push-pull output 1 1 Mode DDR OR floating input 0 0 pull-up input 0 1 Other ports Table 29. M Table 30. PA7:6 pins PC3 pin Doc ID 13562 Rev 3 73/188 I/O ports ST7LITE49M Table 30. Table 31. PC3 pin (continued) Mode DDR OR open-drain output 1 0 push-pull output 1 1 Port configuration Input Port Output Pin name OR = 0 OR = 1 OR = 0 OR = 1 PA5:0 floating pull-up interrupt open-drain push-pull PA7:6 floating interrupt Port B PB7:0 floating pull-up interrupt open-drain push-pull floating pull-up interrupt open-drain push-pull Port C PC7:4, PC2:0 PC3 floating pull-up open-drain push-pull Port A Table 32. Address true open-drain I/O port register mapping and reset values Register label 7 6 5 4 3 2 1 0 0000h PADR Reset value MSB 0 0 0 0 0 0 0 LSB 0 0001h PADDR Reset value MSB 0 0 0 0 0 0 0 LSB 0 0002h PAOR Reset value MSB 0 0 0 0 0 0 0 LSB 0 0003h PBDR Reset value MSB 0 0 0 0 0 0 0 LSB 0 0004h PBDDR Reset value MSB 0 0 0 0 0 0 0 LSB 0 0005h PBOR Reset value MSB 0 0 0 0 0 0 0 LSB 0 0006h PCDR Reset value MSB 0 0 0 0 0 0 0 LSB 0 0007h PCDDR Reset value MSB 0 0 0 0 0 0 0 LSB 0 0008h PCOR Reset value MSB 0 0 0 0 1 0 0 LSB 0 (Hex.) 74/188 Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals 11 On-chip peripherals 11.1 Watchdog timer (WDG) 11.1.1 Introduction The watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared. 11.1.2 11.1.3 Main features ● Programmable free-running downcounter (64 increments of 16000 CPU cycles) ● Programmable reset ● Reset (if watchdog activated) when the T6 bit reaches zero ● Optional reset on HALT instruction (configurable by option byte) ● Hardware Watchdog selectable by option byte Functional description The counter value stored in the CR register (bits T[6:0]), is decremented every 16000 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the RESET pin for typically 30 µs. Figure 36. Watchdog block diagram RESET WATCHDOG CONTROL REGISTER (CR) WDGA T6 T5 T4 T3 T2 T1 T0 7-BIT DOWNCOUNTER fCPU CLOCK DIVIDER ÷16000 Doc ID 13562 Rev 3 75/188 On-chip peripherals ST7LITE49M The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 33: Watchdog timing): ● The WDGA bit is set (watchdog enabled) ● The T6 bit is set to prevent generating an immediate reset ● The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a reset. Watchdog timing (1)(2) Table 33. fCPU = 8 MHz WDG counter code min [ms] max [ms] C0h 1 2 FFh 127 128 1. The timing variation shown in Table 33 is due to the unknown status of the prescaler when writing to the CR register. 2. The number of CPU clock cycles applied during the reset phase (256 or 4096) must be taken into account in addition to these timings. 11.1.4 Hardware watchdog option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the option byte description in Section 14 on page 173. Using Halt mode with the WDG (WDGHALT option) If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. Same behavior in Active-halt mode. 11.1.5 Interrupts None. 76/188 Doc ID 13562 Rev 3 ST7LITE49M 11.1.6 On-chip peripherals Register description Control register (WDGCR) Reset value: 0111 1111 (7Fh) 7 WDGA 0 T6 T5 T4 T3 T2 T1 T0 Read/Write Bit 7 = WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB) These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). Table 34. Address (Hex.) 0033h Watchdog timer register mapping and reset values Register label 7 6 5 4 3 2 1 0 WDGCR Reset value WDGA 0 T6 1 T5 1 T4 1 T3 1 T2 1 T1 1 T0 1 Doc ID 13562 Rev 3 77/188 On-chip peripherals ST7LITE49M 11.2 Dual 12-bit autoreload timer 11.2.1 Introduction The 12-bit autoreload timer can be used for general-purpose timing functions. It is based on one or two free-running 12-bit upcounters with an input capture register and four PWM output channels. There are 7 external pins: 11.2.2 78/188 ● Four PWM outputs ● ATIC/LTIC pins for the input capture function ● BREAK pin for forcing a break condition on the PWM outputs Main features ● Single timer or dual timer mode with two 12-bit upcounters (CNTR1/CNTR2) and two 12-bit autoreload registers (ATR1/ATR2) ● Maskable overflow interrupts ● PWM mode – Generation of four independent PWMx signals – Dead time generation for Half bridge driving mode with programmable dead time – Frequency 2 kHz - 4 MHz (@ 8 MHz fCPU) – Programmable duty-cycles – Polarity control – Programmable output modes ● Output Compare mode ● Input Capture mode – 12-bit input capture register (ATICR) – Triggered by rising and falling edges – Maskable IC interrupt – Long range input capture ● Internal/external break control ● Flexible clock control ● One-pulse mode on PWM2/3 ● Force update Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals Figure 37. Single timer mode (ENCNTR2=0) ATIC 12-bit Input Capture Edge Detection Circuit Output Compare PWM0 Duty Cycle Generator OE0 Dead Time Generator OE1 DTE bit OE2 12-Bit Autoreload register 1 PWM2 Duty Cycle Generator 12-Bit Upcounter 1 PWM0 Break Function PWM1 Duty Cycle Generator CMP Interrupt OE3 PWM3 Duty Cycle Generator PWM1 PWM2 PWM3 OVF1 interrupt BPEN bit Clock Control OFF fCPU 1 ms from Lite timer Figure 38. Dual timer mode (ENCNTR2=1) ATIC 12-bit Input Capture Edge Detection Circuit Output Compare 12-Bit Autoreload register 1 PWM1 Duty Cycle Generator OVF1 interrupt OVF2 interrupt 12-Bit Upcounter 2 OE0 Dead Time Generator OE1 DTE bit OE2 PWM2 Duty Cycle Generator PWM3 Duty Cycle Generator One-pulse mode PWM0 Break Function 12-Bit Upcounter 1 PWM0 Duty Cycle Generator CMP Interrupt OE3 PWM1 PWM2 PWM3 12-Bit Autoreload register 2 Output Compare Clock Control OP_EN bit BPEN bit OFF CMP Interrupt fCPU 1 ms from Lite timer LTIC Doc ID 13562 Rev 3 79/188 On-chip peripherals 11.2.3 ST7LITE49M Functional description PWM mode This mode allows up to four pulse width modulated signals to be generated on the PWMx output pins. ● PWM frequency The four PWM signals can have the same frequency (fPWM) or can have two different frequencies. This is selected by the ENCNTR2 bit which enables Single timer or Dual timer mode (see Figure 37 and Figure 38). The frequency is controlled by the counter period and the ATR register value. In Dual timer mode, PWM2 and PWM3 can be generated with a different frequency controlled by CNTR2 and ATR2. f PWM = f COUNTER ⁄ ( 4096 – ATR ) Following the above formula, if fCOUNTER equals 4 MHz, the maximum value of fPWM is 2 MHz (ATR register value = 4094), and the minimum value is 1 kHz (ATR register value = 0). The maximum value of ATR is 4094 because it must be lower than the DC4R value which must be 4095 in this case. To update the DCRx registers at 32 MHz, the following precautions must be taken: ● – If the PWM frequency is < 1 MHz and the TRANx bit is set asynchronously, it should be set twice after a write to the DCRx registers. – If the PWM frequency is > 1 MHz, the TRANx bit should be set along with FORCEx bit with the same instruction (use a load instruction and not 2 bset instructions). Duty cycle The duty cycle is selected by programming the DCRx registers. These are preload registers. The DCRx values are transferred in Active duty cycle registers after an overflow event if the corresponding transfer bit (TRANx bit) is set. The TRAN1 bit controls the PWMx outputs driven by counter 1 and the TRAN2 bit controls the PWMx outputs driven by counter 2. PWM generation and output compare are done by comparing these active DCRx values with the counter. The maximum available resolution for the PWMx duty cycle is: Resolution = 1 ⁄ ( 4096 – ATR ) where ATR is equal to 0. With this maximum resolution, 0% and 100% duty cycle can be obtained by changing the polarity. At reset, the counter starts counting from 0. When a upcounter overflow occurs (OVF event), the preloaded Duty cycle values are transferred to the active Duty Cycle registers and the PWMx signals are set to a high level. When the upcounter matches the active DCRx value the PWMx signals are set to a low level. To obtain a signal on a PWMx pin, the contents of the corresponding active DCRx register must be greater than the contents of the ATR register. 80/188 Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case. ● Polarity inversion The polarity bits can be used to invert any of the four output signals. The inversion is synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2 register is set (reset value). See Figure 39. Figure 39. PWM polarity inversion inverter PWMx PIN PWMx PWMxCSR register OPx TRANx DFF ATCSR2 register counter overflow The data flip flop (DFF) applies the polarity inversion when triggered by the counter overflow input. ● Output control The PWMx output signals can be enabled or disabled using the OEx bits in the PWMCR register. Figure 40. PWM function COUNTER 4095 DUTY CYCLE REGISTER (DCRx) AUTO-RELOAD REGISTER (ATR) PWMx OUTPUT 000 t WITH OE=1 AND OPx=0 WITH OE=1 AND OPx=1 Doc ID 13562 Rev 3 81/188 On-chip peripherals ST7LITE49M Figure 41. PWM signal from 0% to 100% duty cycle fCOUNTER ATR= FFDh PWMx OUTPUT WITH MOD00=1 AND OPx=1 PWMx OUTPUT WITH MOD00=1 AND OPx=0 COUNTER FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh DCRx=000h DCRx=FFDh DCRx=FFEh DCRx=000h t Dead time generation A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is required for half-bridge driving where PWM signals must not be overlapped. The nonoverlapping PWM0/PWM1 signals are generated through a programmable dead time by setting the DTE bit. Dead time = DT [ 6:0 ] × Tcounter1 DTGR[7:0] is buffered inside so as to avoid deforming the current PWM cycle. The DTGR effect will take place only after an overflow. Note: 82/188 1 Dead time is generated only when DTE=1 and DT[6:0] ≠ 0. If DTE is set and DT[6:0]=0, PWM output signals will be at their reset state. 2 Half Bridge driving is possible only if polarities of PWM0 and PWM1 are not inverted, i.e. if OP0 and OP1 are not set. If polarity is inverted, overlapping PWM0/PWM1 signals will be generated. 3 Dead time generation does not work at 1ms timebase. Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals Figure 42. Dead time generation Tcounter1 CK_CNTR1 CNTR1 DCR0 DCR0+1 OVF ATR1 if DTE = 0 counter = DCR0 PWM 0 counter = DCR1 PWM 1 if DTE = 1 Tdt PWM 0 Tdt PWM 1 Tdt = DT[6:0] x Tcounter1 In the above example, when the DTE bit is set: ● PWM goes low at DCR0 match and goes high at ATR1+Tdt ● PWM1 goes high at DCR0+Tdt and goes low at ATR match. With this programmable delay (Tdt), the PWM0 and PWM1 signals which are generated are not overlapped. Break function The break function can be used to perform an emergency shutdown of the application being driven by the PWM signals. The break function is activated by the external BREAK pin. This can be selected by using the BRSEL bit in BREAKCR register. In order to use the break function it must be previously enabled by software setting the BPEN bit in the BREAKCR register. The Break active level can be programmed by the BREDGE bit in the BREAKCR register. When an active level is detected on the BREAK pin, the BA bit is set and the break function is activated. In this case, the PWM signals are forced to BREAK value if respective OEx bit is set in PWMCR register. Software can set the BA bit to activate the break function without using the BREAK pin. The BREN1 and BREN2 bits in the BREAKEN register are used to enable the break activation on the 2 counters respectively. In Dual Timer mode, the break for PWM2 and PWM3 is enabled by the BREN2 bit. In Single timer mode, the BREN1 bit enables the break for all PWM channels. Doc ID 13562 Rev 3 83/188 On-chip peripherals ST7LITE49M When a break function is activated (BA bit =1 and BREN1/BREN2 =1): ● The break pattern (PWM[3:0] bits in the BREAKCR) is forced directly on the PWMx output pins if respective OEx is set. (after the inverter). ● The 12-bit PWM counter CNTR1 is put to its reset value, i.e. 00h (if BREN1 = 1). ● The 12-bit PWM counter CNTR2 is put to its reset value,i.e. 00h (if BREN2 = 1). ● ATR1, ATR2, preload and active DCRx are put to their reset values. ● Counters stop counting. When the break function is deactivated after applying the break (BA bit goes from 1 to 0 by software), Timer takes the control of PWM ports. Figure 43. ST7LITE49M block diagram of break function BRSEL BREDGE BREAKCR register BREAK pin Level Selection BREAKCR register BA BPEN OEx PWM3 PWM2 PWM1 PWM0 PWM0 PWM1 (Inverters) PWM0 PWM1 PWM2 PWM2 PWM3 PWM3 BREAKEN register PWM0/1 Break Enable BREN2 BREN1 PWM2/3 Break Enable ENCNTR2 bit Output compare mode To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers. When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is generated if the CMPIE bit is set. In Single Timer mode the output compare function is performed only on CNTR1. The difference between both the modes is that, in Single timer mode, CNTR1 can be compared with any of the four DCR registers, and in Dual timer mode, CNTR1 is compared with DCR0 or DCR1 and CNTR2 is compared with DCR2 or DCR3. Note: 84/188 1 The output compare function is only available for DCRx values other than 0 (reset value). 2 Duty cycle registers are buffered internally. The CPU writes in Preload duty cycle registers and these values are transferred in Active duty cycle registers after an overflow event if the corresponding transfer bit (TRANx bit) is set. Output compare is done by comparing these active DCRx values with the counters. Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals Figure 44. Block diagram of output compare mode (single timer) DCRx PRELOAD DUTY CYCLE REG0/1/2/3 (ATCSR2) TRAN1 (ATCSR) OVF ACTIVE DUTY CYCLE REGx OUTPUT COMPARE CIRCUIT CNTR1 COUNTER 1 CMPFx (PWMxCSR) CMP INTERRUPT REQUEST CMPIE (ATCSR) Input capture mode The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter CNTR1 after a rising or falling edge is detected on the ATIC pin. When an Input Capture occurs, the ICF bit is set and the ATICR register contains the value of the free running upcounter. An IC interrupt is generated if the ICIE bit is set. The ICF bit is reset by reading the ATICRH/ATICRL register when the ICF bit is set. The ATICR is a read only register and always contains the free running upcounter value which corresponds to the most recent input capture. Any further input capture is inhibited while the ICF bit is set. Figure 45. Block diagram of input capture mode ATIC 12-BIT INPUT CAPTURE REGISTER ATICR IC INTERRUPT REQUEST ATCSR ICF ICIE CK1 CK0 fLTIMER (1 ms timebase @ 8MHz) fCPU OFF 12-BIT UPCOUNTER1 CNTR1 ATR1 12-BIT AUTORELOAD REGISTER Doc ID 13562 Rev 3 85/188 On-chip peripherals ST7LITE49M Figure 46. Input capture timing diagram fCOUNTER COUNTER1 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah ATIC PIN INTERRUPT ATICR READ INTERRUPT ICF FLAG xxh 09h 04h t Long range input capture Pulses that last more than 8 µs can be measured with an accuracy of 4 µs if fOSC equals 8 MHz in the following conditions: ● The 12-bit AT4 timer is clocked by the Lite timer (RTC pulse: CK[1:0] = 01 in the ATCSR register) ● The ICS bit in the ATCSR2 register is set so that the LTIC pin is used to trigger the AT4 timer capture. ● The signal to be captured is connected to LTIC pin ● Input Capture registers LTICR, ATICRH and ATICRL are read This configuration allows to cascade the Lite timer and the 12-bit AT4 timer to get a 20-bit input capture value. Refer to Figure 47. Figure 47. Long range input capture block diagram LTICR 8-bit Input Capture register fOSC/32 8 LSB bits 8-bit Timebase Counter1 LITE TIMER 20 cascaded bits 12-bit ARTIMER ATR1 12-bit AutoReload register fLTIMER ICS 1 ATIC 86/188 fcpu OFF LTIC 0 CNTR1 12-bit Upcounter1 ATICR 12-bit Input Capture register Doc ID 13562 Rev 3 12 MSB bits ST7LITE49M On-chip peripherals Since the input capture flags (ICF) for both timers (AT4 timer and LT timer) are set when signal transition occurs, software must mask one interrupt by clearing the corresponding ICIE bit before setting the ICS bit. If the ICS bit changes (from 0 to 1 or from 1 to 0), a spurious transition might occur on the Input Capture signal because of different values on LTIC and ATIC. To avoid this situation, it is recommended to do as follows: 1. First, reset both ICIE bits. 2. Then set the ICS bit. 3. Reset both ICF bits. 4. And then set the ICIE bit of desired interrupt. Computing a pulse length in long input capture mode is not straightforward since both timers are used. The following steps are required: 1. 2. At the first input capture on the rising edge of the pulse, we assume that values in the registers are the following: – LTICR = LT1 – ATICRH = ATH1 – ATICRL = ATL1 – Hence ATICR1 [11:0] = ATH1 & ATL1. Refer to Figure 48 on page 88. At the second input capture on the falling edge of the pulse, we assume that the values in the registers are as follows: – LTICR = LT2 – ATICRH = ATH2 – ATICRL = ATL2 – Hence ATICR2 [11:0] = ATH2 & ATL2. Now pulse width P between first capture and second capture is given by: P = decimal × ( F9 – LT1 + LT2 + 1 ) × 0.004ms + decimal ( ( FFF × N ) + N + ATICR2 – ATICR1 – 1 ) × 1ms where N is the number of overflows of 12-bit CNTR1. Doc ID 13562 Rev 3 87/188 On-chip peripherals ST7LITE49M Figure 48. Long range input capture timing diagram fOSC/32 TB Counter1 CNTR1 F9h 00h ___ LT1 F9h 00h ___ ___ ATH1 & ATL1 ___ ___ LT2 ___ ___ ATH2 & ATL2 LTIC LTICR 00h LT1 LT2 ATICRH 0h ATH1 ATH2 ATICRL 00h ATL1 ATL2 ATICR = ATICRH[3:0] & ATICRL[7:0] 88/188 Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals One-pulse mode One-pulse mode can be used to control PWM2/3 signal with an external LTIC pin. This mode is available only in Dual Timer mode i.e. only for CNTR2, when the OP_EN bit in PWM3CSR register is set. One-pulse mode is activated by the external LTIC input. The active edge of the LTIC pin is selected by the OPEDGE bit in the PWM3CSR register. After getting the active edge of the LTIC pin, CNTR2 is reset (000h) and PWM3 is set to high. CNTR2 starts counting from 000h, when it reaches the active DCR3 value then PWM3 goes low. Till this time, any further transitions on the LTIC signal will have no effect. If there are LTIC transitions after CNTR2 reaches DCR3 value, CNTR2 is reset again and PWM3 goes high. If there is no LTIC active edge, CNTR2 counts until it reaches the ATR2 value, then it is reset again and PWM3 is set to high. The counter again starts counting from 000h, when it reaches the active DCR3 value PWM3 goes low, the counter counts until it reaches ATR2, it resets and PWM3 is set to high and so on. The same operation applies for PWM2, but in this case the comparison is done on DCR2. OP_EN and OPEDGE bits take effect on the fly and are not synchronized with Counter 2 overflow. The output bit OP2/3 can be used to inverse the polarity of PWM2/3 in one-pulse mode. The update of these bits (OP2/3) is synchronized with the counter 2 overflow, they will be updated if the TRAN2 bit is set. The time taken from activation of LTIC input and CNTR2 reset is between 1 and 2 tCPU cycles, that is, 125 ns to 250 ns (with 8-MHz fCPU). Lite timer Input Capture interrupt should be disabled while 12-bit ARtimer is in One-pulse mode. This is to avoid spurious interrupts. The priority of the various conditions for PWM3 is the following: Break > one-pulse mode with active LTIC edge > Forced overflow by s/w > one-pulse mode without active LTIC edge > normal PWM operation. It is possible to update DCR2/3 and OP2/3 at the counter 2 reset, the update is synchronized with the counter reset. This is managed by the overflow interrupt which is generated if counter is reset either due to ATR match or active pulse at LTIC pin. DCR2/3 and OP2/3 update in one-pulse mode is performed dynamically using a software force update. DCR3 update in this mode is not synchronized with any event. That may lead to a longer next PWM3 cycle duration than expected just after the change. In One-pulse mode ATR2 value must be greater than DCR2/3 value for PWM2/3. (opposite to normal PWM mode). If there is an active edge on the LTIC pin after the counter has reset due to an ATR2 match, then the timer again gets reset and appears as modified Duty cycle depending on whether the new DCR value is less than or more than the previous value. The TRAN2 bit should be set along with the FORCE2 bit with the same instruction after a write to the DCR register. ATR2 value should be changed after an overflow in one-pulse mode to avoid any irregular PWM cycle. When exiting from one-pulse mode, the OP_EN bit in the PWM3CSR register should be reset first and then the ENCNTR2 bit (if counter 2 must be stopped). Doc ID 13562 Rev 3 89/188 On-chip peripherals ST7LITE49M How to enter One-pulse mode The steps required to enter One-pulse mode are the following: 1. Load ATR2H/ATR2L with required value. 2. Load DCR3H/DCR3L for PWM3. ATR2 value must be greater than DCR3. 3. Set OP3 in PWM3CSR if polarity change is required. 4. Select CNTR2 by setting ENCNTR2 bit in ATCSR2. 5. Set TRAN2 bit in ATCSR2 to enable transfer. 6. "Wait for Overflow" by checking the OVF2 flag in ATCSR2. 7. Select counter clock using CK bits in ATCSR. 8. Set OP_EN bit in PWM3CSR to enable one-pulse mode. 9. Enable PWM3 by OE3 bit of PWMCR. The "Wait for Overflow" in step 6 can be replaced by a forced update. Follow the same procedure for PWM2 with the bits corresponding to PWM2. Note: When break is applied in One-pulse mode, CNTR2, DCR2/3 & ATR2 registers are reset. So, these registers have to be initialized again when break is removed. Figure 49. Block diagram of One-pulse mode LTIC pin Edge Selection 12-bit Upcounter 2 OPEDGE OP_EN PWM3CSR register PWM Generation 12-bit AutoReload register 2 PWM2/3 12-bit Active DCR2/3 OP2/3 Figure 50. One-pulse mode and PWM timing diagram OP_EN=1 fcounter2 CNTR2 000 DCR2/3 ATR2 DCR2/3 000 DCR2/3 ATR2 DCR2/3 ATR2 LTIC OP_EN=0 1) PWM2/3 fcounter2 CNTR2 OVF OVF OVF ATR2 LTIC PWM2/3 Note 1: When OP_EN=0, LTIC edges are not taken into account as the timer runs in PWM mode. 90/188 Doc ID 13562 Rev 3 000 ST7LITE49M On-chip peripherals Figure 51. Dynamic DCR2/3 update in One-pulse mode fcounter2 000 CNTR2 FFF 000 (DCR3)old (DCR3)new ATR2 000 OP_EN=1 LTIC FORCE2 TRAN2 (DCR2/3)old DCR2/3 (DCR2/3)new PWM2/3 extra PWM3 period due to DCR3 update dynamically in one-pulse mode. Force update In order not to wait for the counterx overflow to load the value into active DCRx registers, a programmable counterx overflow is provided. For both counters, a separate bit is provided which when set, make the counters start with the overflow value, i.e. FFFh. After overflow, the counters start counting from their respective auto reload register values. These bits are FORCE1 and FORCE2 in the ATCSR2 register. FORCE1 is used to force an overflow on Counter 1 and, FORCE2 is used for Counter 2. These bits are set by software and reset by hardware after the respective counter overflow event has occurred. This feature can be used at any time. All related features such as PWM generation, output compare, input capture, One-pulse (refer to Figure 51: Dynamic DCR2/3 update in Onepulse mode) etc. can be used this way. Figure 52. Force overflow timing diagram fCNTRx FORCEx CNTRx E03 E04 FFF ARRx FORCE2 FORCE1 ATCSR2 register Doc ID 13562 Rev 3 91/188 On-chip peripherals 11.2.4 ST7LITE49M Low power modes Table 35. 11.2.5 Effect of low power modes on autoreload timer Mode Description Wait No effect on AT timer Halt AT timer halted. Interrupts Table 36. Description of interrupt events Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt Exit from Active-halt Overflow Event OVF1 OVIE1 Yes No Yes AT4 IC Event ICF ICIE Yes No No Overflow Event2 OVF2 OVIE2 Yes No No Note: The AT4 IC is connected to an interrupt vector. The OVF event is mapped on a separate vector (see Interrupts chapter). They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction). 11.2.6 Register description Timer control status register (ATCSR) Reset value: 0x00 0000 (x0h) 7 0 0 ICF ICIE CK1 CK0 OVF1 OVFIE1 CMPIE Read / Write Bit 7 = Reserved Bit 6 = ICF Input capture flag This Bit is set by hardware and cleared by software by reading the ATICR register (a read access to ATICRH or ATICRL clears this flag). Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred Bit 5 = ICIE IC interrupt enable bit This bit is set and cleared by software. 0: Input capture interrupt disabled 1: Input capture interrupt enabled 92/188 Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals Bits 4:3 = CK[1:0] Counter clock selection bits These bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter. Table 37. Counter clock selection Counter clock selection CK1 CK0 OFF 0 0 selection forbidden 1 1 fLTIMER (1 ms timebase @ 8 MHz) 0 1 fCPU 1 0 Bit 2 = OVF1 Overflow flag This bit is set by hardware and cleared by software by reading the ATCSR register. It indicates the transition of the counter1 CNTR1 from FFFh to ATR1 value. 0: No counter overflow occurred 1: Counter overflow occurred Bit 1 = OVFIE1 Overflow interrupt enable bit This bit is read/write by software and cleared by hardware after a reset. 0: Overflow Interrupt Disabled. 1: Overflow Interrupt Enabled. Bit 0 = CMPIE Compare interrupt enable bit This bit is read/write by software and cleared by hardware after a reset. it can be used to mask the interrupt generated when any of the cmpfx bit is set. 0: Output compare interrupt disabled. 1: Output compare interrupt enabled. Counter register 1 high (CNTR1H) Reset value: 0000 0000 (00h) 15 0 8 0 0 CNTR1_ 11 0 CNTR1_ 10 CNTR1_9 CNTR1_8 Read only Counter register 1 low (CNTR1L) Reset value: 0000 0000 (00h) 7 CNTR1_7 0 CNTR1_6 CNTR1_5 CNTR1_4 CNTR1_3 CNTR1_2 CNTR1_1 CNTR1_0 Read only Bits 15:12 = Reserved Doc ID 13562 Rev 3 93/188 On-chip peripherals ST7LITE49M Bits 11:0 = CNTR1[11:0] Counter value This 12-bit register is read by software and cleared by hardware after a reset. The counter CNTR1 increments continuously as soon as a counter clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations. As there is no latch, it is recommended to read LSB first. In this case, CNTR1H can be incremented between the two read operations and to have an accurate result when ftimer=fCPU, special care must be taken when CNTR1L values close to FFh are read. When a counter overflow occurs, the counter restarts from the value specified in the ATR1 register. Autoreload register (ATR1H) Reset value: 0000 0000 (00h) 15 0 8 0 0 0 ATR11 ATR10 ATR9 ATR8 Read/write Autoreload register (ATR1L) Reset value: 0000 0000 (00h) 7 ATR7 0 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 Read/write Bits 11:0 = ATR1[11:0] Autoreload register 1: This is a 12-bit register which is written by software. The ATR1 register value is automatically loaded into the upcounter CNTR1 when an overflow occurs. The register value is used to set the PWM frequency. PWM output control register (PWMCR) Reset value: 0000 0000 (00h) 7 0 0 OE3 0 OE2 0 OE1 0 OE0 Read/write Bits 7:0 = OE[3:0] PWMx output enable bits These bits are set and cleared by software and cleared by hardware after a reset. 0: PWM mode disabled. PWMx output alternate function disabled (I/O pin free for general purpose I/O) 1: PWM mode enabled 94/188 Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals PWMX control status register (PWMxCSR) Reset value: 0000 0000 (00h) 7 0 0 0 0 0 OP_EN OPEDGE OPx CMPFx Read/write Bits 7:4= Reserved, must be kept cleared. Bit 3 = OP_EN One-pulse mode enable bit This bit is read/write by software and cleared by hardware after a reset. This bit enables the One-pulse feature for PWM2 and PWM3 (only available for PWM3CSR) 0: One-pulse mode disable for PWM2/3. 1: One-pulse mode enable for PWM2/3. Bit 2 = OPEDGE One-pulse edge selection bit This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the LTIC signal for One-pulse feature. This bit will be effective only if OP_EN bit is set (only available for PWM3CSR) 0: Falling edge of LTIC is selected. 1: Rising edge of LTIC is selected. Bit 1 = OPx PWMx output polarity bit This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM signal. 0: The PWM signal is not inverted. 1: The PWM signal is inverted. Bit 0 = CMPFx PWMx compare flag This bit is set by hardware and cleared by software by reading the PWMxCSR register. It indicates that the upcounter value matches the Active DCRx register value. 0: Upcounter value does not match DCRx value. 1: Upcounter value matches DCRx value. Break control register (BREAKCR) Reset value: 0000 0000 (00h) 7 0 0 BREDGE BA BPEN PWM3 PWM2 PWM1 PWM0 Read/write Bit 7 = Reserved Doc ID 13562 Rev 3 95/188 On-chip peripherals ST7LITE49M Bit 6 = BREDGE Break input edge selection bit This bit is read/write by software and cleared by hardware after reset. It selects the active level of Break signal. 0: Low level of Break selected as active level 1: High level of Break selected as active level Bit 5 = BA Break active bit This bit is read/write by software, cleared by hardware after reset and set by hardware when the active level defined by the BR1EDGE bit is applied on the BREAK pin. It activates/deactivates the Break function. 0: Break not active 1: Break active Bit 4 = BPEN Break pin enable bit This bit is read/write by software and cleared by hardware after reset. 0: Break pin disabled 1: Break pin enabled Bits 3:0 = PWM[3:0] Break pattern bits These bits are read/write by software and cleared by hardware after a reset. They are used to force the four PWMx output signals into a stable state when the Break function is active and corresponding OEx bit is set. PWMx duty cycle register High (DCRxH) Reset value: 0000 0000 (00h) 15 0 8 0 0 0 DCR11 DCR10 DCR9 DCR8 Read/write Bits 15:12 = Reserved. PWMx duty cycle register Low (DCRxL) Reset value: 0000 0000 (00h) 7 DCR7 0 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0 Read/write Bits 11:0 = DCRx[11:0] PWMx duty cycle value: this 12-bit value is written by software. It defines the duty cycle of the corresponding PWM output signal (see Figure 40). In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWMx output signal (see Figure 40). In output compare mode, they define the value to be compared with the 12-bit upcounter value. 96/188 Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals Input capture register high (ATICRH) Reset value: 0000 0000 (00h) 15 0 8 0 0 0 ICR11 ICR10 ICR9 ICR8 Read only Bits 15:12 = Reserved. Input capture register low (ATICRL) Reset value: 0000 0000 (00h) 7 ICR7 0 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 Read only Bits 11:0 = ICR[11:0] Input capture data. This is a 12-bit register which is readable by software and cleared by hardware after a reset. The ATICR register contains captured the value of the 12-bit CNTR1 register when a rising or falling edge occurs on the ATIC or LTIC pin (depending on ICS). Capture will only be performed when the ICF flag is cleared. Break enable register (BREAKEN) Reset value: 0000 0011 (03h) 7 0 0 0 0 0 0 0 BREN2 BREN1 Read/write Bits 7:2 = Reserved, must be kept cleared. Bit 1 = BREN2 Break enable for counter 2 bit This bit is read/write by software. It enables the break functionality for Counter2 if BA bit is set in BREAKCR. It controls PWM2/3 if ENCNTR2 bit is set. 0: No Break applied for CNTR2 1: Break applied for CNTR2 Bit 0 = BREN1 Break enable for counter 1 bit This bit is read/write by software. It enables the break functionality for Counter1. If BA bit is set, it controls PWM0/1 by default, and controls PWM2/3 also if ENCNTR2 bit is reset. 0: No Break applied for CNTR1 1: Break applied for CNTR1 Doc ID 13562 Rev 3 97/188 On-chip peripherals ST7LITE49M Timer control register 2 (ATCSR2) Reset value: 0000 0011 (03h) 7 FORCE2 0 FORCE1 ICS OVFIE2 OVF2 ENCNTR2 TRAN2 TRAN1 Read/write Bit 7 = FORCE2 Force counter 2 overflow bit This bit is read/set by software. When set, it loads FFFh in the CNTR2 register. It is reset by hardware one CPU clock cycle after counter 2 overflow has occurred. 0 : No effect on CNTR2 1 : Loads FFFh in CNTR2 Note: This bit must not be reset by software Bit 6 = FORCE1 Force counter 1 overflow bit This bit is read/set by software. When set, it loads FFFh in CNTR1 register. It is reset by hardware one CPU clock cycle after counter 1 overflow has occurred. 0 : No effect on CNTR1 1 : Loads FFFh in CNTR1 Note: This bit must not be reset by software Bit 5 = ICS Input capture shorted bit This bit is read/write by software. It allows the ATtimer CNTR1 to use the LTIC pin for long Input Capture. 0 : ATIC for CNTR1 input capture 1 : LTIC for CNTR1 input capture Bit 4 = OVFIE2 Overflow interrupt 2 enable bit This bit is read/write by software and controls the overflow interrupt of counter2. 0: Overflow interrupt disabled. 1: Overflow interrupt enabled. Bit 3 = OVF2 Overflow flag This bit is set by hardware and cleared by software by reading the ATCSR2 register. It indicates the transition of the counter2 from FFFh to ATR2 value. 0: No counter overflow occurred 1: Counter overflow occurred Bit 2 = ENCNTR2 Enable counter2 for PWM2/3 This bit is read/write by software and switches the PWM2/3 operation to the CNTR2 counter. If this bit is set, PWM2/3 will be generated using CNTR2. 0: PWM2/3 is generated using CNTR1. 1: PWM2/3 is generated using CNTR2. Note: 98/188 Counter 2 gets frozen when the ENCNTR2 bit is reset. When ENCNTR2 is set again, the counter will restart from the last value. Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals Bit 1= TRAN2 Transfer enable2 bit This bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR2. It allows the value of the Preload DCRx registers to be transferred to the Active DCRx registers after the next overflow event. The OPx bits are transferred to the shadow OPx bits in the same way. Note: 1 DCR2/3 transfer will be controlled using this bit if ENCNTR2 bit is set. 2 This bit must not be reset by software Bit 0 = TRAN1 Transfer enable 1 bit This bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR1. It allows the value of the Preload DCRx registers to be transferred to the Active DCRx registers after the next overflow event. The OPx bits are transferred to the shadow OPx bits in the same way. Note: 1 DCR0,1 transfers are always controlled using this bit. 2 DCR2/3 transfer will be controlled using this bit if ENCNTR2 is reset. 3 This bit must not be reset by software Autoreload register 2 (ATR2H) Reset value: 0000 0000 (00h) 15 0 8 0 0 0 ATR11 ATR10 ATR9 ATR8 Read/write Autoreload register (ATR2L) Reset value: 0000 0000 (00h) 7 ATR7 0 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 Read/write Bits 11:0 = ATR2[11:0] Autoreload register 2 This is a 12-bit register which is written by software. The ATR2 register value is automatically loaded into the upcounter CNTR2 when an overflow of CNTR2 occurs. The register value is used to set the PWM2/PWM3 frequency when ENCNTR2 is set. Doc ID 13562 Rev 3 99/188 On-chip peripherals ST7LITE49M Dead time generator register (DTGR) Reset value: 0000 0000 (00h) 7 0 DTE DT6 DT5 DT4 DT3 DT2 DT1 DT0 Read/write Bit 7 = DTE Dead time enable bit This bit is read/write by software. It enables a dead time generation on PWM0/PWM1. 0: No Dead time insertion. 1: Dead time insertion enabled. Bits 6:0 = DT[6:0] Dead time value These bits are read/write by software. They define the dead time inserted between PWM0/PWM1. Dead time is calculated as follows: Dead Time = DT[6:0] x Tcounter1 Note: If DTE is set and DT[6:0]=0, PWM output signals will be at their reset state. Table 38. Register mapping and reset values Add. (Hex) Register label 7 6 5 4 3 2 1 0 0011 ATCSR Reset value 0 ICF 0 ICIE 0 CK1 0 CK0 0 OVF1 0 OVFIE1 0 CMPIE 0 0012 CNTR1H Reset value 0 0 0 0 CNTR1_1 1 0 0013 CNTR1L Reset value 0014 ATR1H Reset value 0 0 0 0 ATR11 0 ATR10 0 ATR9 0 ATR8 0 0015 ATR1L Reset value ATR7 0 ATR6 0 ATR5 0 ATR4 0 ATR3 0 ATR2 0 ATR1 0 ATR0 0 0016 PWMCR Reset value 0 OE3 0 0 OE2 0 0 OE1 0 0 OE0 0 0017 PWM0CSR Reset value 0 0 0 0 0 0 OP0 0 CMPF0 0 0018 PWM1CSR Reset value 0 0 0 0 0 0 OP1 0 CMPF1 0 0019 PWM2CSR Reset value 0 0 0 0 0 0 OP2 0 CMPF2 0 001A PWM3CSR Reset value 0 0 0 0 OP_EN 0 OPEDGE 0 OP3 0 CMPF3 0 001B DCR0H Reset value 0 0 0 0 DCR11 0 DCR10 0 DCR9 0 DCR8 0 100/188 CNTR1_7 CNTR1_8 0 0 CNTR1_ CNTR1_6 CNTR1_3 7 0 0 0 Doc ID 13562 Rev 3 CNTR1_1 CNTR1_ CNTR1_9 0 8 0 0 0 CNTR1_2 CNTR1_1 0 0 CNTR1_ 0 0 ST7LITE49M Table 38. On-chip peripherals Register mapping and reset values (continued) Add. (Hex) Register label 7 6 5 4 3 2 1 0 001C DCR0L Reset value DCR7 0 DCR6 0 DCR5 0 DCR4 0 DCR3 0 DCR2 0 DCR1 0 DCR0 0 001D DCR1H Reset value 0 0 0 0 DCR11 0 DCR10 0 DCR9 0 DCR8 0 001E DCR1L Reset value DCR7 0 DCR6 0 DCR5 0 DCR4 0 DCR3 0 DCR2 0 DCR1 0 DCR0 0 001F DCR2H Reset value 0 0 0 0 DCR11 0 DCR10 0 DCR9 0 DCR8 0 0020 DCR2L Reset value DCR7 0 DCR6 0 DCR5 0 DCR4 0 DCR3 0 DCR2 0 DCR1 0 DCR0 0 0021 DCR3H Reset value 0 0 0 0 DCR11 0 DCR10 0 DCR9 0 DCR8 0 0022 DCR3L Reset value DCR7 0 DCR6 0 DCR5 0 DCR4 0 DCR3 0 DCR2 0 DCR1 0 DCR0 0 0023 ATICRH Reset value 0 0 0 0 ICR11 0 ICR10 0 ICR9 0 ICR8 0 0024 ATICRL Reset value ICR7 0 ICR6 0 ICR5 0 ICR4 0 ICR3 0 ICR2 0 ICR1 0 ICR0 0 0025 ATCSR2 Reset value FORCE2 0 FORCE1 0 ICS 0 OVFIE2 0 OVF2 0 ENCNTR2 0 TRAN2 1 TRAN1 1 0026 BREAKCR Reset value 0 BREDGE 0 BA 0 BPEN 0 PWM3 0 PWM2 0 PWM1 0 PWM0 0 0027 ATR2H Reset value 0 0 0 0 ATR11 0 ATR10 0 ATR9 0 ATR8 0 0028 ATR2L Reset value ATR7 0 ATR6 0 ATR5 0 ATR4 0 ATR3 0 ATR2 0 ATR1 0 ATR0 0 0029 DTGR Reset value DTE 0 DT6 0 DT5 0 DT4 0 DT3 0 DT2 0 DT1 0 DT0 0 002A BREAKEN Reset value 0 0 0 0 0 0 BREN2 1 BREN1 1 Doc ID 13562 Rev 3 101/188 On-chip peripherals ST7LITE49M 11.3 Lite timer 2 (LT2) 11.3.1 Introduction The Lite timer can be used for general-purpose timing functions. It is based on two freerunning 8-bit upcounters and an 8-bit input capture register. 11.3.2 Main features ● ● Real-time clock – One 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 MHz fOSC) – One 8-bit upcounter with autoreload and programmable timebase period from 4 µs to 1.024 ms in 4 µs increments (@ 8 MHz fOSC) – 2 maskable timebase interrupts Input capture – ● 8-bit input capture register (LTICR) Maskable interrupt with wakeup from Halt mode capability Figure 53. Lite timer 2 block diagram fOSC/32 LTTB2 LTCNTR Interrupt request LTCSR2 8-bit TIMEBASE COUNTER 2 0 0 0 0 0 0 TB2IE TB2F 8 LTARR fLTIMER 8-bit AUTORELOAD REGISTER /2 8-bit TIMEBASE COUNTER 1 fLTIMER 8 To 12-bit AT TImer 1 0 Timebase 1 or 2 ms (@ 8 MHz fOSC) LTICR LTIC 8-bit INPUT CAPTURE REGISTER LTCSR1 ICIE ICF TB TB1IE TB1F LTTB1 INTERRUPT REQUEST LTIC INTERRUPT REQUEST 102/188 Doc ID 13562 Rev 3 ST7LITE49M 11.3.3 On-chip peripherals Functional description Timebase counter 1 The 8-bit value of counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of fOSC/32. An overflow event occurs when the counter rolls over from F9h to 00h. If fOSC = 8 MHz, then the time period between two counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the LTCSR1 register. When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1 register. Input capture The 8-bit Input Capture register is used to latch the free-running upcounter (Counter 1) 1 after a rising or falling edge is detected on the LTIC pin. When an Input Capture occurs, the ICF bit is set and the LTICR register contains the counter 1 value. An interrupt is generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register. The LTICR is a read-only register and always contains the data from the last Input Capture. Input Capture is inhibited if the ICF bit is set. Timebase counter 2 Counter 2 is an 8-bit autoreload upcounter. It can be read by accessing the LTCNTR register. After an MCU reset, it increments at a frequency of fOSC/32 starting from the value stored in the LTARR register. A counter overflow event occurs when the counter rolls over from FFh to the LTARR reload value. Software can write a new value at any time in the LTARR register, this value will be automatically loaded in the counter when the next overflow occurs. When Counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software reading the LTCSR2 register. Figure 54. Input capture timing diagram 4µs (@ 8 MHz fOSC) fCPU fOSC/32 8-bit COUNTER 1 01h 02h 03h 04h 05h 06h 07h CLEARED BY S/W READING LTIC REGISTER LTIC PIN ICF FLAG LTICR REGISTER xxh 04h 07h t Doc ID 13562 Rev 3 103/188 On-chip peripherals 11.3.4 ST7LITE49M Low power modes Table 39. 11.3.5 Effect of low power modes on Lite timer 2 Mode Description Slow No effect on Lite timer (this peripheral is driven directly by fOSC/32) Wait No effect on Lite timer Active-halt No effect on Lite timer Halt Lite timer stops counting Interrupts Table 40. Description of interrupt events Interrupt event Event flag Enable control Bit Timebase 1 Event TB1F TB1IE Timebase 2 Event TB2F TB2IE IC Event ICF ICIE Exit from Wait Exit from Active-halt Exit from Halt Yes Yes No No No The TBxF and ICF interrupt events are connected to separate interrupt vectors (see Section 8: Interrupts). They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the interrupt mask in the CC register is reset (RIM instruction). 11.3.6 Register description Lite timer control/status register 2 (LTCSR2) Reset value: 0000 0000 (00h) 7 0 0 0 0 0 0 Read / Write Bits 7:2 = Reserved, must be kept cleared. Bit 1 = TB2IE Timebase 2 Interrupt enable bit This bit is set and cleared by software. 0: Timebase (TB2) interrupt disabled 1: Timebase (TB2) interrupt enabled 104/188 Doc ID 13562 Rev 3 0 TB2IE TB2F ST7LITE49M On-chip peripherals Bit 0 = TB2F Timebase 2 Interrupt flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No Counter 2 overflow 1: A Counter 2 overflow has occurred Lite timer autoreload register (LTARR) Reset value: 0000 0000 (00h) 7 AR7 0 AR6 AR5 AR4 AR3 AR2 AR1 AR0 Read / Write Bits 7:0 = AR[7:0] Counter 2 reload value These bits register is read/write by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs. Lite timer counter 2 (LTCNTR) Reset value: 0000 0000 (00h) 7 CNT7 0 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 Read only Bits 7:0 = CNT[7:0] Counter 2 Reload value This register is read by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs. Lite timer control/status register (LTCSR1) Reset value: 0x00 0000 (x0h) 7 ICIE 0 ICF TB TB1IE TB1F Read / Write Bit 7 = ICIE Interrupt enable bit This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled Doc ID 13562 Rev 3 105/188 On-chip peripherals ST7LITE49M Bit 6 = ICF Input capture flag This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value. 0: No Input Capture 1: An Input Capture has occurred Note: After an MCU reset, software must initialize the ICF bit by reading the LTICR register Bit 5 = TB Timebase period selection bit This bit is set and cleared by software. 0: Timebase period = tOSC * 8000 (1 ms @ 8 MHz) 1: Timebase period = tOSC * 16000 (2 ms @ 8 MHz) Bit 4 = TB1IE Timebase Interrupt enable bit This bit is set and cleared by software. 0: Timebase (TB1) interrupt disabled 1: Timebase (TB1) interrupt enabled Bit 3 = TB1F Timebase Interrupt flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No counter overflow 1: A counter overflow has occurred Bits 2:0 = Reserved, must be kept cleared. Lite timer input capture register (LTICR) Reset value: 0000 0000 (00h) 7 ICR7 0 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 Read only Bits 7:0 = ICR[7:0] Input capture value These bits are read by software and cleared by hardware after a reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling edge occurs on the LTIC pin. Table 41. Address Lite timer register mapping and reset values Register label 7 6 5 4 3 2 1 0 0C LTCSR2 Reset value 0 0 0 0 0 0 TB2IE 0 TB2F 0 0D LTARR Reset value AR7 0 AR6 0 AR5 0 AR4 0 AR3 0 AR2 0 AR1 0 AR0 0 0E LTCNTR Reset value CNT7 0 CNT6 0 CNT5 0 CNT4 0 CNT3 0 CNT2 0 CNT1 0 CNT0 0 (Hex.) 106/188 Doc ID 13562 Rev 3 ST7LITE49M Table 41. Address On-chip peripherals Lite timer register mapping and reset values (continued) Register label 7 6 5 4 3 2 1 0 0F LTCSR1 Reset value ICIE 0 ICF x TB 0 TB1IE 0 TB1F 0 0 0 0 10 LTICR Reset value ICR7 0 ICR6 0 ICR5 0 ICR4 0 ICR3 0 ICR2 0 ICR1 0 ICR0 0 (Hex.) Doc ID 13562 Rev 3 107/188 On-chip peripherals ST7LITE49M 11.4 I2C bus interface (I2C) 11.4.1 Introduction The I2C Bus Interface serves as an interface between the microcontroller and the serial I2C bus. It provides both multimaster and slave functions, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports fast I2C mode (400 kHz). 11.4.2 Main features ● Parallel-bus/I2C protocol converter ● Multi-master capability ● 7-bit/10-bit addressing ● Transmitter/receiver flag ● End-of-byte transmission flag ● Transfer problem detection I2C master features: ● Clock generation ● I2C bus busy flag ● Arbitration lost flag ● End of byte transmission flag ● Transmitter/receiver Flag ● Start bit detection flag ● Start and stop generation I2C slave features: 11.4.3 ● Stop bit detection ● I2C bus busy flag ● Detection of misplaced start or stop condition ● Programmable I2C address detection ● Transfer problem detection ● End-of-byte transmission flag ● Transmitter/Receiver flag General description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by software. The interface is connected to the I2C bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard I2C bus and a Fast I2C bus. This selection is made by software. 108/188 Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals Mode selection The interface can operate in the four following modes: ● Slave transmitter/receiver ● Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, allowing then Multi-Master capability. Communication flow In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. In Slave mode, the interface is capable of recognizing its own address (7 or 10-bit), and the general call address. The general call address detection may be enabled or disabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 55. Figure 55. I2C bus protocol SDA ACK MSB SCL 1 2 8 START CONDITION 9 STOP CONDITION Acknowledge may be enabled and disabled by software. The I2C interface address and/or general call address can be selected by software. The speed of the I2C interface may be selected between Standard (up to 100 kHz) and Fast I2C (up to 400 kHz). SDA/SCL line control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the data register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. The SCL frequency (Fscl) is controlled by a programmable clock divider which depends on the I2C bus mode. Doc ID 13562 Rev 3 109/188 On-chip peripherals ST7LITE49M When the I2C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. When the I2C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins. Figure 56. I2C interface block diagram DATA REGISTER (DR) SDA or SDAI DATA CONTROL DATA SHIFT REGISTER COMPARATOR OWN ADDRESS REGISTER 1 (OAR1) OWN ADDRESS REGISTER 2 (OAR2) SCL or SCLI CLOCK CONTROL CLOCK CONTROL REGISTER (CCR) CONTROL REGISTER (CR) STATUS REGISTER 1 (SR1) CONTROL LOGIC STATUS REGISTER 2 (SR2) INTERRUPT 110/188 Doc ID 13562 Rev 3 ST7LITE49M 11.4.4 On-chip peripherals Functional description Refer to the CR, SR1 and SR2 registers in Section 11.4.7. for the bit definitions. By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the interface frequency must be configured using the FRi bits in the OAR2 register. Slave mode As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. ● Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set. ● Address not matched: the interface ignores it and waits for another Start condition. ● Address matched: the interface generates in sequence: – Acknowledge pulse if the ACK bit is set. – EVF and ADSL bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register, holding the SCL line low (see Figure 57 transfer sequencing EV1). Next, in 7-bit mode read the DR register to determine from the least significant bit (data direction bit) if the slave must enter Receiver or Transmitter mode. In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1). Slave receiver Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: ● Acknowledge pulse if the ACK bit is set ● EVF and BTF bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 57 Transfer sequencing EV2). Slave transmitter Following the address reception and after SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register. The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 57 Transfer sequencing EV3). When the acknowledge pulse is received the EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Doc ID 13562 Rev 3 111/188 On-chip peripherals ST7LITE49M Closing slave communication After the last data byte is transferred a stop condition is generated by the master. The interface detects this condition and sets: EVF and STOPF bits with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR2 register (see Figure 57 Transfer sequencing EV4). Error cases Note: ● BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and the BERR bits are set with an interrupt if the ITE bit is set. If it is a Stop then the interface discards the data, released the lines and waits for another Start condition. If it is a Start then the interface discards the data and waits for the next slave address on the bus. ● AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set. The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. In both cases, SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time. How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte. SMBus compatibility ST7 I2C is compatible with SMBus V1.1 protocol. It supports all SMBus addressing modes, SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave Driver For ST7 I2C Peripheral. 112/188 Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals Master mode To switch from default Slave mode to Master mode a Start condition generation is needed. Start condition Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition. Once the Start condition is sent, the EVF and SB bits are set by hardware with an interrupt if the ITE bit is set. The master then waits for a read of the SR1 register followed by a write in the DR register with the Slave address, holding the SCL line low (see Figure 57 Transfer sequencing EV5). Slave address transmission 1. Note: The slave address is then sent to the SDA line via the internal shift register. – In 7-bit addressing mode, one address byte is sent. – In 10-bit addressing mode, sending the first byte including the header sequence causes the following event. The EVF bit is set by hardware with interrupt generation if the ITE bit is set. 2. The master then waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 57 transfer sequencing EV9). 3. Then the second address byte is sent by the interface. 4. After completion of this transfer (and acknowledge from the slave if the ACK bit is set), the EVF bit is set by hardware with interrupt generation if the ITE bit is set. 5. The master waits for a read of the SR1 register followed by a write in the CR register (for example set PE bit), holding the SCL line low (see Figure 57 transfer sequencing EV6). 6. Next the master must enter receiver or transmitter mode. In 10-bit addressing mode, to switch the master to receiver mode, software must generate a repeated Start condition and resend the header sequence with the least significant bit set (11110xx1). Master receiver Following the address transmission and after SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: ● Acknowledge pulse if the ACK bit is set ● EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 57 transfer sequencing EV7). To close the communication: before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte. Doc ID 13562 Rev 3 113/188 On-chip peripherals ST7LITE49M Master transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 57 Transfer sequencing EV8). When the acknowledge bit is received, the interface sets EVF and BTF bits with an interrupt if the ITE bit is set. To close the communication: after writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Error cases Note: 114/188 ● BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set by hardware with an interrupt if ITE is set. Note that BERR will not be set if an error is detected during the first pulse of each 9-bit transaction: Single Master mode If a Start or Stop is issued during the first pulse of a 9-bit transaction, the BERR flag will not be set and transfer will continue however the BUSY flag will be reset. To work around this, slave devices should issue a NACK when they receive a misplaced Start or Stop. The reception of a NACK or BUSY by the master in the middle of communication gives the possibility to reinitiate transmission. Multimaster mode Normally the BERR bit would be set whenever unauthorized transmission takes place while transfer is already in progress. However, an issue will arise if an external master generates an unauthorized Start or Stop while the I2C master is on the first pulse of a 9-bit transaction. It is possible to work around this by polling the BUSY bit during I2C master mode transmission. The resetting of the BUSY bit can then be handled in a similar manner as the BERR flag being set. ● AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit. The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. ● ARLO: Detection of an arbitration lost condition. In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared). In all these cases, the SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time. Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals Figure 57. Transfer sequencing 7-bit slave receiver S Address A Data1 A Data2 A DataN A P ..... EV1 EV2 EV2 EV2 EV4 7-bit slave transmitter S Address A Data1 A Data N Data2 A .... . EV1 EV3 EV3 NA EV3 P EV31 EV4 NA P 7-bit master receiver S Address A Data1 EV5 A Data2 EV6 A EV7 .... EV7 . DataN A .... . EV7 7-bit master transmitter S Address A Data1 EV5 A Data2 EV6 EV8 EV8 Data N A EV8 P EV8 10-bit slave receiver S Header A Address A Data1 A DataN A P ..... EV1 EV2 EV2 EV4 10-bit slave transmitter Sr Header A Data N Data1 A A P ... EV1 EV3 EV31 EV4 DataN A P EV3 10-bit master transmitter S Header A Address A Data1 A .... EV5 EV9 EV6 EV8 EV8 EV8 10-bit master receiver Sr Header A Data1 A DataN A P ..... EV5 EV6 EV7 EV7 1. S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge, EVx=Event (with interrupt if ITE=1). 2. EV1: EVF=1, ADSL=1, cleared by reading SR1 register. 3. EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. 4. EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. 5. EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). If lines are released by STOP=1, STOP=0, the Doc ID 13562 Rev 3 115/188 On-chip peripherals ST7LITE49M subsequent EV4 is not seen. 6. EV4: EVF=1, STOPF=1, cleared by reading SR2 register. 7. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. 8. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). 9. EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. 10. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. 11. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register. 11.4.5 Low power modes Effect of low power modes on the I2C interface Table 42. Mode Description Wait I No effect on I2C interface. interrupts cause the device to exit from Wait mode. I2C registers are frozen. In Halt mode, the I interface is inactive and does not acknowledge data on the bus. The I2C interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt mode” capability. 2C Halt 11.4.6 2C Interrupts Figure 58. Event flags and interrupt generation ADD10 BTF ADSL SB AF STOPF ARLO BERR ITE INTERRUPT EVF * * EVF can also be set by EV6 or an error from the SR2 register. Table 43. Description of interrupt events Exit from Wait Exit from Halt ADD10 Yes No End of byte transfer event BTF Yes No Address matched event (Slave mode) ADSL Yes No Start bit generation event (Master mode) SB Yes No Interrupt event(1) Event flag 10-bit address sent event (Master mode) Enable control bit ITE Acknowledge failure event AF Yes No Stop detection event (Slave mode) STOPF Yes No Arbitration lost event (Multimaster configuration) ARLO Yes No Bus error event BERR Yes No 2 1. The I C interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction). 116/188 Doc ID 13562 Rev 3 ST7LITE49M 11.4.7 On-chip peripherals Register description I2C control register (I2CCR) Reset value: 0000 0000 (00h) 7 0 0 0 PE ENGC START ACK STOP ITE Read / Write Bits 7:6 = Reserved. Forced to 0 by hardware. Bit 5 = PE Peripheral Enable bit This bit is set and cleared by software. 0: Peripheral disabled 1: Master/Slave capability Note: When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released while PE=0 When PE=1, the corresponding I/O pins are selected by hardware as alternate functions. To enable the I2C interface, write the CR register TWICE with PE=1 as the first write only activates the interface (only PE is set). Bit 4 = ENGC Enable general call bit This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored). 0: General Call disabled 1: General Call enabled Note: In accordance with the I2C standard, when GCAL addressing is enabled, an I2C slave can only receive data. It will not transmit data to the master. Bit 3 = START Generation of a Start condition bit. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1). ● In master mode: 0: No start generation 1: Repeated start generation ● In slave mode: 0: No start generation 1: Start generation when the bus is free Bit 2 = ACK Acknowledge enable bit This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). 0: No acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received Doc ID 13562 Rev 3 117/188 On-chip peripherals ST7LITE49M Bit 1 = STOP Generation of a Stop condition bit This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). ● In master mode: 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. ● In slave mode: 0: No stop generation 1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the STOP bit has to be cleared by software. Bit 0 = ITE Interrupt enable bit This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 58 for the relationship between the events and the interrupt. SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See Figure 57) is detected. 118/188 Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals I2C status register 1 (I2CSR1) Reset value: 0000 0000 (00h) 7 EVF 0 ADD10 TRA BUSY BTF ADSL M/SL SB Read Only Bit 7 = EVF Event flag This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register in case of error event or as described in Figure 57. It is also cleared by hardware when the interface is disabled (PE=0). 0: No event 1: One of the following events has occurred: – BTF=1 (byte received or transmitted) – ADSL=1 (Address matched in Slave mode while ACK=1) – SB=1 (Start condition generated in Master mode) – AF=1 (No acknowledge received after byte transmission) – STOPF=1 (Stop condition detected in Slave mode) – ARLO=1 (Arbitration lost in Master mode) – BERR=1 (Bus error, misplaced Start or Stop condition detected) – ADD10=1 (Master has sent header byte) – Address byte successfully transmitted in Master mode. Bit 6 = ADD10 10-bit addressing in Master mode This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading SR2 register followed by a write in the DR register of the second address byte. It is also cleared by hardware when the peripheral is disabled (PE=0). 0: No ADD10 event occurred. 1: Master has sent first address byte (header) Bit 5 = TRA Transmitter/Receiver bit When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0). 0: Data byte received (if BTF=1) 1: Data byte transmitted Bit 4 = BUSY Bus busy bit This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs. 0: No communication on the bus 1: Communication ongoing on the bus Doc ID 13562 Rev 3 119/188 On-chip peripherals ST7LITE49M Bit 3 = BTF Byte transfer finished bit This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0). – Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (See Figure 57). BTF is cleared by reading SR1 register followed by writing the next byte in DR register. – Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register. The SCL line is held low while BTF=1. 0: byte transfer not done 1: byte transfer succeeded Bit 2 = ADSL Address matched bit (slave mode). This bit is set by hardware as soon as the received slave address matched with the OAR register content or a general call is recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE=0). The SCL line is held low while ADSL=1. 0: Address mismatched or not received 1: Received address matched Bit 1 = M/SL Master/Slave bit This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0). 0: Slave mode 1: Master mode Bit 0 = SB Start bit (master mode). This bit is set by hardware as soon as the Start condition is generated (following a write START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE=0). 0: No Start condition 1: Start condition generated 120/188 Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals I2C status register 2 (I2CSR2) Reset value: 0000 0000 (00h) 7 0 0 0 0 AF STOPF ARLO BERR GCAL Read Only Bits 7:5 = Reserved. Forced to 0 by hardware. Bit 4 = AF Acknowledge failure bit This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time. 0: No acknowledge failure 1: Acknowledge failure Bit 3 = STOPF Stop detection bit (slave mode) This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while STOPF=1. 0: No Stop condition detected 1: Stop condition detected Bit 2 = ARLO Arbitration lost bit This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). After an ARLO event the interface switches back automatically to Slave mode (M/SL=0). The SCL line is not held low while ARLO=1. 0: No arbitration lost detected 1: Arbitration lost detected Note: In a Multimaster environment, when the interface is configured in master receive mode it does not perform arbitration during the reception of the Acknowledge Bit. Mishandling of the ARLO bit from the I2CSR2 register may occur when a second master simultaneously requests the same data from the same slave and the I2C master does not acknowledge the data. The ARLO bit is then left at 0 instead of being set. Bit 1 = BERR Bus error bit This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while BERR=1. 0: No misplaced Start or Stop condition 1: Misplaced Start or Stop condition Doc ID 13562 Rev 3 121/188 On-chip peripherals Note: ST7LITE49M If a bus error occurs, a Stop or a repeated Start condition should be generated by the Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication Bit 0 = GCAL General Call bit (slave mode). This bit is set by hardware when a general call address is detected on the bus while ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled (PE=0). 0: No general call address detected on bus 1: general call address detected on bus I2C clock control register (I2CCCR) Reset value: 0000 0000 (00h) 7 FM/SM 0 CC6 CC5 CC4 CC3 CC2 CC1 CC0 Read / Write Bit 7 = FM/SM Fast/Standard I2C mode bit This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 0: Standard I2C mode 1: Fast I2C mode Bits 6:0 = CC[6:0] 7-bit clock divider bits These bits select the speed of the bus (FSCL) depending on the I2C mode. They are not cleared when the interface is disabled (PE=0). Refer to the Electrical Characteristics section for the table of values. Note: The programmed FSCL assumes no load on SCL and SDA lines. I2C data register (I2CDR) Reset value: 0000 0000 (00h) 7 D7 0 D6 D5 D4 D3 D2 D1 D0 Read / Write Bits 7:0 = D[7:0] 8-bit data register These bits contain the byte to be received or transmitted on the bus. 122/188 – Transmitter mode: byte transmission start automatically when the software writes in the DR register. – Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address. Then, the following data bytes are received one by one after reading the DR register. Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals I2C own address register (I2COAR1) Reset value: 0000 0000 (00h) 7 ADD7 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Read / Write ● In 7-bit addressing mode Bits 7:1 = ADD[7:1] Interface address. These bits define the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0). Bit 0 = ADD0 Address direction bit. This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0). Note: Address 01h is always ignored. ● In 10-bit addressing mode Bits 7:0 = ADD[7:0] Interface address. These are the least significant bits of the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0). I2C own address register (I2COAR2) Reset value: 0100 0000 (40h) 7 FR1 0 FR0 0 0 0 ADD9 ADD8 0 Read / Write Bits 7:6 = FR[1:0] Frequency bits These bits are set by software only when the interface is disabled (PE=0). To configure the interface to I2C specified delays select the value corresponding to the microcontroller frequency fCPU. Table 44. Configuration of I2C delay times fCPU FR1 FR0 < 6 MHz 0 0 6 to 8 MHz 0 1 Bits 5:3 = Reserved Bits 2:1 = ADD[9:8] Interface address These are the most significant bits of the I2C bus address of the interface (10-bit mode only). They are not cleared when the interface is disabled (PE=0). Bit 0 = Reserved. Doc ID 13562 Rev 3 123/188 On-chip peripherals Table 45. Address (Hex.) ST7LITE49M I2C register mapping and reset values Register label 7 6 5 4 3 2 1 0 0 0 PE 0 ENGC 0 START 0 ACK 0 STOP 0 ITE 0 EVF 0 ADD10 0 TRA 0 BUSY 0 BTF 0 ADSL 0 M/SL 0 SB 0 0 0 0 AF 0 STOPF 0 ARLO 0 BERR 0 GCAL 0 0064h I2CCR Reset value 0065h I2CSR1 Reset value 0066h I2CSR2 Reset value 0067h I2CCCR Reset value FM/SM 0 CC6 0 CC5 0 CC4 0 CC3 0 CC2 0 CC1 0 CC0 0 0068h I2COAR1 Reset value ADD7 0 ADD6 0 ADD5 0 ADD4 0 ADD3 0 ADD2 0 ADD1 0 ADD0 0 0069h I2COAR2 Reset value FR1 0 FR0 1 0 0 0 ADD9 0 ADD8 0 0 006Ah I2CDR Reset value MSB 0 0 0 0 0 0 0 LSB 0 124/188 Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals 11.5 10-bit A/D converter (ADC) 11.5.1 Introduction The on-chip analog to digital converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 10 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 10 different sources. The result of the conversion is stored in a 10-bit data register. The A/D converter is controlled through a control/status register. 11.5.2 Main features ● 10-bit conversion ● Up to 10 channels with multiplexed input ● Linear successive approximation ● Data register (DR) which contains the results ● Conversion complete status flag ● On/off bit (to reduce consumption) The block diagram is shown in Figure 59. 11.5.3 Functional description Analog power supply VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. Doc ID 13562 Rev 3 125/188 On-chip peripherals ST7LITE49M Figure 59. ADC block diagram fCPU DIV 4 DIV 2 1 0 fADC 0 1 SLOW bit EOC SPEED ADON 0 CH3 CH2 CH1 ADCCSR CH0 4 AIN0 HOLD CONTROL RADC AIN1 ANALOG TO DIGITAL ANALOG MUX CONVERTER CADC AINx ADCDRH D9 D8 ADCDRL D7 D6 0 D5 0 D4 0 D3 0 D2 SLOW 0 D1 D0 Digital A/D conversion result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than VDDA (high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication). If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is described in the Electrical Characteristics section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 126/188 Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals Configuring the A/D conversion The analog input ports must be configured as input, no pull-up, no interrupt (see Section 10: I/O ports). Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. To assign the analog channel to convert, select the CH[2:0] bits in the ADCCSR register. Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete: ● The EOC bit is set by hardware. ● The result is in the ADCDR registers. A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit. To read the 10 bits, perform the following steps: 1. Poll the EOC bit 2. Read ADCDRL 3. Read ADCDRH. This clears EOC automatically. To read only 8 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRH. This clears EOC automatically. Changing the conversion channel The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel. 11.5.4 Low power modes The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. Table 46. 11.5.5 Effect of low power modes on the A/D converter Mode Description Wait No effect on A/D converter Halt A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilization time tSTAB (see Electrical Characteristics) before accurate conversions can be performed. Interrupts None. Doc ID 13562 Rev 3 127/188 On-chip peripherals 11.5.6 ST7LITE49M Register description Control/status register (ADCCSR) Reset value: 0000 0000 (00h) 7 EOC 0 SPEED ADON 0 Read only CH3 CH2 CH1 CH0 Read/write Bit 7 = EOC End of conversion bit This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH register or writes to any bit of the ADCCSR register. 0: Conversion is not complete 1: Conversion complete Bit 6 = SPEED ADC clock selection bit This bit is set and cleared by software. It is used together with the SLOW bit to configure the ADC clock speed. Refer to the table in the SLOW bit description (ADCDRL register). Bit 5 = ADON A/D converter ON bit This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on Bit 4 = Reserved, must be kept cleared. Bits 3:0 = CH[3:0] Channel selection These bits select the analog input to convert. They are set and cleared by software. Table 47. Channel selection using CH[3:0] Channel pin(1) CH3 CH2 CH1 CH0 AIN0 0 0 0 0 AIN1 0 0 0 1 AIN2 0 0 1 0 AIN3 0 0 1 1 AIN4 0 1 0 0 AIN5 0 1 0 1 AIN6 0 1 1 0 AIN7 0 1 1 1 AIN8 1 0 0 0 AIN9 1 0 0 1 1. The number of channels is device dependent. Refer to the device pinout description. 128/188 Doc ID 13562 Rev 3 ST7LITE49M On-chip peripherals Data register high (ADCDRH) Reset value: xxxx xxxx (xxh) 7 D9 0 D8 D7 D6 D5 D4 D3 D2 Read only Bits 7:0 = D[9:2] MSB of analog converted value ADC control/data register low (ADCDRL) Reset value: 0000 00xx (0xh) 7 0 0 0 0 0 SLOW 0 D1 D0 Read/write Bits 7:4 = Reserved. Forced by hardware to 0. Bit 3 = SLOW Slow mode bit This bit is set and cleared by software. It is used together with the SPEED bit in the ADCCSR register to configure the ADC clock speed as shown on the table below. Table 48. Configuring the ADC clock speed fADC(1) SLOW SPEED fCPU/2 0 0 fCPU 0 1 fCPU/4 1 x 1. The maximum allowed value of fADC is 4 MHz (see Section 13.11 on page 170) Bit 2 = Reserved. Forced by hardware to 0. Bits 1:0 = D[1:0] LSB of analog converted value Table 49. Address ADC register mapping and reset values Register label 7 0036h ADCCSR Reset value EOC 0 0037h ADCDRH Reset value D9 x D8 x 0038h ADCDRL Reset value 0 0 0 0 (Hex.) 6 5 4 3 2 1 0 0 0 CH3 0 CH2 0 CH1 0 CH0 0 D7 x D6 x D5 x D4 x D3 x D2 x 0 0 0 SLOW 0 0 D1 x D0 x SPEED ADON 0 0 Doc ID 13562 Rev 3 129/188 Instruction set ST7LITE49M 12 Instruction set 12.1 ST7 addressing modes The ST7 core features 17 different addressing modes which can be classified in seven main groups: Table 50. Description of addressing modes Addressing mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset byte,#5 The ST7 instruction set is designed to minimize the number of bytes required per instruction: To do so, most of the addressing modes may be subdivided in two submodes called long and short: ● Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. ● Short addressing mode is less powerful because it can generally only access page zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes. Table 51. ST7 addressing mode overview Mode Syntax Destination/ source Pointer address Pointer size Length (bytes) Inherent nop +0 Immediate ld A,#$55 +1 Short Direct ld A,$10 00..FF +1 Long Direct ld A,$1000 0000..FFFF +2 No Offset Direct Indexed ld A,(X) 00..FF + 0 (with X register) + 1 (with Y register) Short Direct Indexed ld A,($10,X) 00..1FE +1 Long Direct Indexed ld A,($1000,X) 0000..FFFF +2 Short Indirect ld A,[$10] 00..FF 00..FF byte +2 Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2 Short Indirect ld A,([$10],X) 00..1FE 00..FF byte +2 130/188 Indexed Doc ID 13562 Rev 3 ST7LITE49M Table 51. Instruction set ST7 addressing mode overview (continued) Syntax Destination/ source Pointer address Pointer size Length (bytes) ld A,([$10.w],X) 0000..FFFF 00..FF word +2 Mode 1. Long Indirect Indexed Relative Direct jrne loop PC128/PC+127(1) Relative Indirect jrne [$10] PC128/PC+127(1) Bit Direct bset $10,#7 00..FF Bit Indirect bset [$10],#7 00..FF Bit Direct Relative btjt $10,#7,skip 00..FF Bit Indirect Relative btjt [$10],#7,skip 00..FF +1 00..FF byte +2 +1 00..FF byte +2 +2 00..FF byte +3 At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx. 12.1.1 Inherent mode All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. Table 52. Instructions supporting inherent addressing mode Instruction Function NOP No operation TRAP S/W interrupt WFI Wait for interrupt (low power mode) HALT Halt oscillator (lowest power mode) RET Subroutine return IRET Interrupt subroutine return SIM Set interrupt mask RIM Reset interrupt mask SCF Set carry flag RCF Reset carry flag RSP Reset stack pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/decrement TNZ Test negative or zero CPL, NEG 1 or 2 complement Doc ID 13562 Rev 3 131/188 Instruction set Table 52. 12.1.2 ST7LITE49M Instructions supporting inherent addressing mode (continued) Instruction Function MUL Byte multiplication SLL, SRL, SRA, RLC, RRC Shift and rotate operations SWAP Swap nibbles Immediate mode Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. Imm Table 53. 12.1.3 Instructions supporting inherent immediate addressing mode Immediate instruction Function LD Load CP Compare BCP Bit compare AND, OR, XOR Logical operations ADC, ADD, SUB, SBC Arithmetic operations Direct modes In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) addressing mode The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF addressing space. Direct (long) addressing mode The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 12.1.4 Indexed modes (no offset, short, long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three submodes: Indexed mode (no offset) There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed mode (short) The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE addressing space. 132/188 Doc ID 13562 Rev 3 ST7LITE49M Instruction set Indexed mode (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 Indirect modes (short, long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two submodes: Indirect mode (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect mode (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 12.1.6 Indirect indexed modes (short, long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two submodes: Indirect indexed mode (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect indexed mode (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 54. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes Instructions Function Long and short instructions LD Load CP Compare AND, OR, XOR Logical operations ADC, ADD, SUB, SBC Arithmetic addition/subtraction operations BCP Bit compare Doc ID 13562 Rev 3 133/188 Instruction set Table 54. ST7LITE49M Instructions supporting direct, indexed, indirect and indirect indexed addressing modes (continued) Instructions Function Short instructions only 12.1.7 CLR Clear INC, DEC Increment/decrement TNZ Test negative or zero CPL, NEG 1 or 2 complement BSET, BRES Bit operations BTJT, BTJF Bit test and jump operations SLL, SRL, SRA, RLC, RRC Shift and rotate operations SWAP Swap nibbles CALL, JP Call or jump subroutine Relative modes (direct, indirect) This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it. Table 55. Instructions supporting relative modes Available Relative Direct/Indirect instructions Function JRxx Conditional jump CALLR Call relative The relative addressing mode consists of two submodes: Relative mode (direct) The offset follows the opcode. Relative mode (indirect) The offset is defined in memory, of which the address follows the opcode. 134/188 Doc ID 13562 Rev 3 ST7LITE49M 12.2 Instruction set Instruction groups The ST7 family devices use an instruction set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Table 56. ST7 instruction set Instructions Load and Transfer LD CLR Stack operation PUSH POP Increment/decrement INC DEC Compare and tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit operation BSET BRES Conditional bit test and branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and rotate SLL SRL SRA RLC RRC SWAP SLA Unconditional jump or call JRA JRT JRF JP CALL CALLR NOP Conditional branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF RSP RET Using a prebyte The instructions are described with 1 to 4 bytes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes by: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. Doc ID 13562 Rev 3 135/188 Instruction set 12.2.1 ST7LITE49M Illegal opcode reset In order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implemented: a reset is generated if the code to be executed does not correspond to any opcode or prebyte value. This, combined with the Watchdog, allows the detection and recovery from an unexpected fault or interference. A valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset. Table 57. I Illegal opcode detection Mnemo Description Function/Example Dst Src H ADC Add with Carry A=A+M+C A M ADD Addition A=A+M A M AND Logical And A=A.M A BCP Bit compare A, Memory tst (A . M) A BRES Bit reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear CP Arithmetic compare tst(Reg - M) reg CPL One Complement A = FFH-A DEC Decrement dec Y HALT Halt IRET Interrupt routine return Pop CC, A, X, PC INC Increment inc X JP Absolute jump jp [TBL.w] JRA Jump relative always JRT Jump relative JRF Never jump JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H=1? JRNH Jump if H = 0 H=0? JRM Jump if I = 1 I=1? JRNM Jump if I = 0 I=0? JRMI Jump if N = 1 (minus) N=1? 136/188 I N Z C H N Z C H N Z C M N Z M N Z reg, M 0 1 N Z C reg, M N Z 1 reg, M N Z N Z N Z M 0 H reg, M jrf * Doc ID 13562 Rev 3 I C ST7LITE49M Table 57. Instruction set Illegal opcode detection (continued) Mnemo Description Function/Example Dst Src JRPL Jump if N = 0 (plus) N=0? JREQ Jump if Z = 1 (equal) Z=1? JRNE Jump if Z = 0 (not equal) Z=0? JRC Jump if C = 1 C=1? JRNC Jump if C = 0 C=0? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned > JRULE Jump if (C + Z = 1) Unsigned