ST7LITE1xB
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
DATA EEPROM, ADC, 5 TIMERS, SPI
Memories
– up to 4 Kbytes single voltage extended Flash
(XFlash) Program memory with read-out protection, In-Circuit Programming and In-Application programming (ICP and IAP). 10K write/
erase cycles guaranteed, data retention: 20
years at 55°C.
– 256 bytes RAM
– 128 bytes data EEPROM with read-out protection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C.
■ Clock, Reset and Supply Management
– Enhanced reset system
– Enhanced low voltage supervisor (LVD) for
main supply and an auxiliary voltage detector
(AVD) with interrupt capability for implementing safe power-down procedures
– Clock sources: Internal 1% RC oscillator (on
ST7FLITE15B and ST7FLITE19B), crystal/
ceramic resonator or external clock
– Internal 32-MHz input clock for Auto-reload
timer
– Optional x4 or x8 PLL for 4 or 8 MHz internal
clock
– Five Power Saving Modes: Halt, Active-Halt,
Auto Wake-up from Halt, Wait and Slow
■ I/O Ports
– Up to 17 multifunctional bidirectional I/O lines
– 7 high sink outputs
■ 5 Timers
– Configurable watchdog timer
– Two 8-bit Lite Timers with prescaler,
1 realtime base and 1 input capture
– Two 12-bit Auto-reload Timers with 4 PWM
Device Summary
■
Features
Program memory - bytes
RAM (stack) - bytes
Data EEPROM - bytes
Peripherals
Operating Supply
CPU Frequency
Operating Temperature
Packages
ST7LITE10B
SO20
DIP20
QFN20
■
■
■
■
■
■
SO16
DIP16
300”
outputs, 1 input capture, 4 output compare
and one pulse functions
Communication Interface
– SPI synchronous serial interface
Interrupt Management
– 12 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (on 4 vectors)
Analog Comparator
A/D Converter
– 7 input channels
– Fixed gain Op-amp
– 13-bit precision for 0 to 430 mV (@ 5V VDD)
– 10-bit precision for 430 mV to 5V (@ 5V VDD)
Instruction Set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode detection
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
Development Tools
– Full hardware/software development package
– DM (Debug Module)
ST7LITE15B
ST7LITE19B
2K/4K
256 (128)
128
Lite Timer with Wdg, Autoreload
Lite Timer with Wdg, Autoreload Timer with 32-MHz input clock, SPI,
Timer, SPI, 10-bit ADC with Op-Amp
10-bit ADC with Op-Amp, Analog Comparator
2.7V to 5.5V
Up to 8Mhz(w/ ext OSC at 16MHz)
Up to 8Mhz (w/ ext OSC at 16MHz or int 1MHz RC 1%, PLLx8/4MHz)
-40°C to +85°C / -40°C to +125°C
SO20 300”, DIP20, SO16 300”, DIP16
SO20 300”, DIP20, SO16 300”, DIP16, QFN20
Rev 6
June 2008
1/159
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.6 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
. . . . 48
10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.8 MULTIPLEXED INPUT/OUTPUT PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.2 DUAL 12-BIT AUTORELOAD TIMER 4 (AT4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.5 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.6 ANALOG COMPARATOR (CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 137
13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
13.12 ANALOG COMPARATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
13.13 PROGRAMMABLE INTERNAL VOLTAGE REFERENCE CHARACTERISTICS . . . . . 143
13.14 CURRENT BIAS CHARACTERISTICS (FOR COMPARATOR AND INTERNAL VOLTAGE
REFERENCE) 143
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
14.2 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 149
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
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ST7LITE1xB
1 INTRODUCTION
The ST7LITE1xB is a member of the ST7 microcontroller family. All ST7 devices are based on a
common industry-standard 8-bit core, featuring an
enhanced instruction set.
The ST7LITE1xB features FLASH memory with
byte-by-byte In-Circuit Programming (ICP) and InApplication Programming (IAP) capability.
Under software control, the ST7LITE1xB device
can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is
in idle or standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes.
For easy reference, all parametric data are located
in section 13 on page 110. The ST7LITE1xB features an on-chip Debug Module (DM) to support
In-Circuit Debugging (ICD). For a description of
the DM registers, refer to the ST7 ICC Protocol
Reference Manual.
Figure 1. General Block Diagram
Programmable
Internal Reference
Int.
1% RC
1MHz
Comparator
PLL
8MHz -> 32MHz
12-Bit
Auto-Reload
TIMER 2
PLL x 8
or PLL X4
CLKIN
8-Bit
LITE TIMER 2
/2
OSC1
OSC2
Ext.
OSC
1MHz
to
16MHz
Internal
CLOCK
VDD
VSS
RESET
POWER
SUPPLY
CONTROL
8-BIT CORE
ALU
PROGRAM
MEMORY
(up to 4K Bytes)
RAM
(256 Bytes)
PORT B
ADDRESS AND DATA BUS
LVD, AVD
PORT A
PORT C
ADC
+ OpAmp
SPI
Debug Module
DATA EEPROM
(128 Bytes)
WATCHDOG
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1
PA7:0
(8 bits)
PB6:0
(7 bits)
PC1:0
(2 bits)
ST7LITE1xB
2 PIN DESCRIPTION
Figure 2. 20-Pin SO and DIP Package Pinout
VSS
1
20
OSC1/CLKIN/PC0
VDD
RESET
2
19
3
18
OSC2/PC1
PA0 (HS)/LTIC
COMPIN+/SS/AIN0/PB0
4
17
PA1 (HS)/ATIC
SCK/AIN1/PB1
5
16
PA2 (HS)/ATPWM0
MISO/AIN2/PB2
6
15
PA3 (HS)/ATPWM1
MOSI/AIN3/PB3
7
14
PA4 (HS)/ATPWM2
COMPIN-/CLKIN/AIN4/PB4
8
13
AIN5/PB5
AIN6/PB6
9
12
PA5 (HS)/ATPWM3/ICCDATA
PA6/MCO/ICCCLK/BREAK
10
11
PA7(HS)/COMPOUT
ei0
ei3
ei2
ei1
(HS) 20mA High sink capability
eix associated external interrupt vector
RESET
1
PC1/OSC2
17
COMPIN+/SS/AIN0/PB0
2
VSS
20 19 18
VDD
PC0/OSC1/CLKIN
Figure 3. 20-Pin QFN Package Pinout
16
PA0 (HS)/LTIC
15
PA1 (HS)/ATIC
14
PA2 (HS)/ATPWM0
13
PA3 (HS)/ATPWM1
12
PA4 (HS)/ATPWM2
11
PA5 (HS)/ATPWM3/ICCDATA
ei0
SCK/AIN1/PB1
3
MISO/AIN2/PB2
4
MOSI/AIN3/PB3
5
ei3
ei2
7
8
9
10
AIN6/PB6
COMPOUT/PA7(HS)
MCO/ICCCLKBREAK/PA6
6
AIN5/PB5
COMPIN-/CLKIN/AIN4/PB4
ei1
(HS) 20mA High sink capability
eix associated external interrupt vector
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1
ST7LITE1xB
PIN DESCRIPTION (Cont’d)
Figure 4. 16-Pin SO and DIP Package Pinout
VSS
16
OSC1/CLKIN/PC0
2
15
3
14
OSC2/PC1
PA0 (HS)/LTIC
13
PA2 (HS)/ATPWM0
12
PA4 (HS)/ATPWM2
6
11
PA5 (HS)/ATPWM3/ICCDATA
MOSI/AIN3/PB3
7
10
PA6/MCO/ICCCLK/BREAK
COMPIN-/CLKIN/AIN4/PB4
8
1
VDD
RESET
COMPIN+/SS/AIN0/PB0
4
SCK/AIN1/PB1
5
MISO/AIN2/PB2
ei0
ei3
ei2
ei1
9
PA7(HS)/COMPOUT
(HS) 20mA high sink capability
eix associated external interrupt vector
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1
ST7LITE1xB
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
In/Output level: CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt, ana = analog
– Output:
OD = open drain, PP = push-pull
The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 1. Device Pin Description
PP
OD
ana
int
wpu
Alternate Function
S
Ground
S
Main power supply
2
VDD
3
1
3
RESET
4
Main
Output Function
(after
reset)
1)
20
2
Input
VSS 1)
2
4
Port / Control
float
1
Input
19
Output
SO16/DIP16
1
Pin Name
Type
QFN20
Level
SO20/DPI20
Pin No.
PB0/COMPIN+/
AIN0/SS
I/O CT
I/O
CT
X
X
X
Top priority non maskable interrupt (active low)
X
X
X
Port B0
ei3
ADC Analog Input 0 2) or SPI Slave
Select (active low) or Analog Comparator Input
Caution: No negative current injection allowed on this pin.
ADC Analog Input 1 2) or SPI Serial
Clock
ADC Analog Input 2 2) or SPI Master In/ Slave Out Data
ADC Analog Input 3 2) or SPI Master Out / Slave In Data
ADC Analog Input 4 2) or External
clock input or Analog Comparator
External Reference Input
5
3
5
PB1/AIN1/SCK
I/O
CT
X
X
X
X
Port B1
6
4
6
PB2/AIN2/MISO
I/O
CT
X
X
X
X
Port B2
7
5
7
PB3/AIN3/MOSI
I/O
CT
X
X
X
X
Port B3
8
6
8
PB4/AIN4/CLKIN/
I/O
COMPIN-
CT
X
X
X
X
Port B4
9
7
-
PB5/AIN5
I/O
CT
X
X
X
X
Port B5
ADC Analog Input 5 2)
10
8
-
PB6/AIN6
I/O
CT
X
X
X
X
Port B6
ADC Analog Input 6 2)
11
9
9
PA7/COMPOUT
I/O CT HS X
X
X
Port A7
Analog Comparator Output
ei2
ei1
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ST7LITE1xB
Port / Control
Alternate Function
PP
Main
Output Function
(after
reset)
OD
ana
int
wpu
Input
float
Input
Type
SO16/DIP16
QFN20
SO20/DPI20
Pin Name
Output
Level
Pin No.
Main Clock Output or In Circuit
Communication Clock or External
BREAK
12 10 10
PA6 /MCO/
ICCCLK/BREAK
I/O
13 11 11
PA5 /ICCDATA/
ATPWM3
I/O CT HS X
CT
X
ei1
X
X
Port A6
X
X
Port A5
ei1
Caution: During normal operation
this pin must be pulled- up, internally or externally (external pull-up
of 10k mandatory in noisy environment). This is to avoid entering ICC
mode unexpectedly during a reset.
In the application, even if the pin is
configured as output, any reset will
put it back in input pull-up
In Circuit Communication Data or
Auto-Reload Timer PWM3
14 12 12 PA4/ATPWM2
I/O CT HS X
X
X
Port A4
Auto-Reload Timer PWM2
15 13
PA3/ATPWM1
I/O CT HS X
X
X
Port A3
Auto-Reload Timer PWM1
16 14 13 PA2/ATPWM0
I/O CT HS X
X
X
Port A2
Auto-Reload Timer PWM0
17 15
-
-
ei0
PA1/ATIC
I/O CT HS X
X
X
Port A1
Auto-Reload Timer Input Capture
18 16 14 PA0/LTIC
I/O CT HS X
X
X
Port A0
Lite Timer Input Capture
19 17 15 OSC2/PC1
I/O
X
X
Port C13)
20 18 16 OSC1/CLKIN/PC0 I/O
X
X
Port C03)
Resonator oscillator inverter output
Resonator oscillator inverter input
or External clock input
Notes:
1. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA
pins to ground.
2. When the pin is configured as analog input, positive and negative current injections are not allowed.
3. PCOR not implemented but p-transistor always active in output mode (refer to Figure 32 on page 50).
8/159
1
ST7LITE1xB
3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 128
bytes of register locations, 256 bytes of RAM, 128
bytes of data EEPROM and up to 4 Kbytes of flash
program memory. The RAM space includes up to
128 bytes for the stack from 180h to 1FFh.
The highest address bytes contain the user reset
and interrupt vectors.
The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7 ad-
dressing space so the reset and interrupt vectors
are located in Sector 0 (F000h-FFFFh).
The size of Flash Sector 0 and other device options are configurable by Option byte (refer to section 15.1 on page 149).
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the
device.
Figure 5. Memory Map
0000h
007Fh
0080h
00FFh
0100h
HW Registers
(see Table 2)
RAM
(128 Bytes)
Reserved
017Fh
0180h
01FFh
0200h
RAM
(128 Bytes)
0080h
Short Addressing
RAM (zero page)
00FFh
0100h
Reserved
017Fh
0180h
01FFh
DEE0h
128 Bytes Stack
RCCRL0
RCCRH1
DEE3h
RCCRL1
see section 7.1 on page 23
Data EEPROM
(128 Bytes)
2K FLASH
PROGRAM MEMORY
107Fh
1080h
Reserved
F800h
FBFFh
FC00h
EFFFh
F000h
FFFFh
Flash Memory
(2K or 4K)
FFDFh
FFE0h
FFFFh
RCCRH0
DEE2h
Reserved
0FFFh
1000h
DEE1h
Interrupt & Reset Vectors
(see Table 5)
1 Kbyte
(SECTOR 1)
1 Kbyte
(SECTOR 0)
4K FLASH
PROGRAM MEMORY
F000h
FBFFh
FC00h
FFFFh
3 Kbytes
(SECTOR 1)
1 Kbyte
(SECTOR 0)
9/159
1
ST7LITE1xB
Table 2. Hardware Register Map
Address
Block
Register Label
0000h
0001h
0002h
Port A
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
FFh1)
00h
40h
R/W
R/W
R/W
0003h
0004h
0005h
Port B
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
FFh 1)
00h
00h
R/W
R/W
R/W2)
0006h
0007h
Port C
PCDR
PCDDR
Port C Data Register
Port C Data Direction Register
0xh
00h
LITE
TIMER 2
LTCSR2
LTARR
LTCNTR
LTCSR1
LTICR
Lite Timer Control/Status Register 2
Lite Timer Auto-reload Register
Lite Timer Counter Register
Lite Timer Control/Status Register 1
Lite Timer Input Capture Register
00h
00h
00h
0X00 0000b
00h
R/W
R/W
Read Only
R/W
Read Only
ATCSR
CNTRH
CNTRL
ATRH
ATRL
PWMCR
PWM0CSR
PWM1CSR
PWM2CSR
PWM3CSR
DCR0H
DCR0L
DCR1H
DCR1L
DCR2H
DCR2L
DCR3H
DCR3L
ATICRH
ATICRL
ATCSR2
BREAKCR
ATR2H
ATR2L
DTGR
BREAKEN
Timer Control/Status Register
Counter Register High
Counter Register Low
Auto-Reload Register High
Auto-Reload Register Low
PWM Output Control Register
PWM 0 Control/Status Register
PWM 1 Control/Status Register
PWM 2 Control/Status Register
PWM 3 Control/Status Register
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
PWM 1 Duty Cycle Register High
PWM 1 Duty Cycle Register Low
PWM 2 Duty Cycle Register High
PWM 2 Duty Cycle Register Low
PWM 3 Duty Cycle Register High
PWM 3 Duty Cycle Register Low
Input Capture Register High
Input Capture Register Low
Timer Control/Status Register 2
Break Control Register
Auto-Reload Register 2 High
Auto-Reload Register 2 Low
Dead Time Generation Register
Break Enable Register
0X00 0000b
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
03h
00h
00h
00h
00h
03h
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
AUTORELOAD
TIMER 2
0027h to
002Bh
Reset Status
Remarks
R/W
R/W
Reserved area (5 bytes)
002Ch
Comparator
Voltage
VREFCR
Reference
Internal Voltage Reference Control Register
00h
R/W
002Dh
Comparator CMPCR
Comparator and Internal Reference Control Register
00h
R/W
Watchdog Control Register
7Fh
R/W
002Eh
10/159
1
Register Name
WDG
WDGCR
ST7LITE1xB
Address
Block
Register Label
0002Fh
FLASH
FCSR
Flash Control/Status Register
00h
R/W
00030h
EEPROM
EECSR
Data EEPROM Control/Status Register
00h
R/W
0031h
0032h
0033h
SPI
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
xxh
0xh
00h
R/W
R/W
R/W
0034h
0035h
0036h
ADC
ADCCSR
ADCDRH
ADCDRL
A/D Control Status Register
A/D Data Register High
A/D Amplifier Control/Data Low Register
00h
xxh
0xh
R/W
Read Only
R/W
0037h
ITC
EICR
External Interrupt Control Register
00h
R/W
0038h
MCC
MCCSR
Main Clock Control/Status Register
00h
R/W
0039h
003Ah
Clock and
Reset
RCCR
SICSR
RC oscillator Control Register
System Integrity Control/Status Register
FFh
0110 0xx0b
R/W
R/W
003Bh
PLL clock
select
PLLTST
PLL test register
00h
R/W
003Ch
ITC
EISR
External Interrupt Selection Register
0Ch
R/W
003Dh to
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h to
007Fh
Register Name
Reset Status
Remarks
Reserved area (12 bytes)
AWU
AWUPR
AWUCSR
AWU Prescaler Register
AWU Control/Status Register
FFh
00h
R/W
R/W
DM3)
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DMCR2
DM Control Register
DM Status Register
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
DM Control Register 2
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved area (46 bytes)
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the Debug Module registers, see ICC protocol reference manual.
11/159
1
ST7LITE1xB
4 FLASH PROGRAM MEMORY
4.1 Introduction
The ST7 single voltage extended Flash (XFlash) is
a non-volatile memory that can be electrically
erased and programmed either on a byte-by-byte
basis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board
(plugged in a programming tool) or on-board using
In-Circuit Programming or In-Application Programming.
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 Main Features
■
■
■
■
■
ICP (In-Circuit Programming)
IAP (In-Application Programming)
ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
Sector 0 size configurable by option byte
Read-out and write protection
4.3 PROGRAMMING MODES
The ST7 can be programmed in three different
ways:
– Insertion in a programming tool. In this mode,
FLASH sectors 0 and 1, option byte row and
data EEPROM (if present) can be programmed or erased.
– In-Circuit Programming. In this mode, FLASH
sectors 0 and 1, option byte row and data
EEPROM (if present) can be programmed or
erased without removing the device from the
application board.
– In-Application Programming. In this mode,
sector 1 and data EEPROM (if present) can
be programmed or erased without removing
the device from the application board and
while the application is running.
12/159
1
4.3.1 In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable.
ICP is performed in three steps:
Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal
sequence on the ICCCLK/DATA pins while the
RESET pin is pulled low. When the ST7 enters
ICC mode, it fetches a specific RESET vector
which points to the ST7 System Memory containing the ICC protocol routine. This routine enables
the ST7 to receive bytes from the ICC interface.
– Download ICP Driver code in RAM from the
ICCDATA pin
– Execute ICP Driver code in RAM to program
the FLASH memory
Depending on the ICP Driver code downloaded in
RAM, FLASH memory programming can be fully
customized (number of bytes to program, program
locations, or selection of the serial communication
interface for downloading).
4.3.2 In Application Programming (IAP)
This mode uses an IAP Driver program previously
programmed in Sector 0 by the user (in ICP
mode).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (user-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored etc.)
IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during
the programming operation.
ST7LITE1xB
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC interface
classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
3. The use of pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Programming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 has to be connected to the OSC1 pin of
the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.
5. In 38-pulse ICC mode, the internal RC oscillator
is forced as a clock source, regardless of the selection in the option byte. For ST7LITE10B devices which do not support the internal RC oscillator,
the “option byte disabled” mode must be used (35pulse ICC mode entry, clock provided by the tool).
Caution: During normal operation the ICCCLK pin
must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if
the pin is configured as output, any reset will put it
back in input pull-up.
ICP needs a minimum of 4 and up to 6 pins to be
connected to the programming tool. These pins
are:
– RESET: device reset
– VSS: device power supply ground
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
– OSC1: main clock input for external source
(not required on devices without OSC1/OSC2
pins)
– VDD: application board power supply (optional, see Note 3)
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to be implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
2. During the ICP session, the programming tool
must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor 32MHz
OSC,PLLOFF,
CLKSEL[1:0]
Option bits
CLKIN
CLKIN
/OSC1
RC OSC
PLL 1MHz -> 8MHz
PLL 1MHz -> 4MHz
CLKIN
CLKIN
OSC
1-16 MHZ
12-BIT
AT TIMER 2
/2
DIVIDER
OSC
CLKIN/2
ck_pllx4x8
fOSC
/2
plldiv2
CLKIN/2
OSC/2
/2
DIVIDER
OSC2
OSC,PLLOFF,
CLKSEL[1:0]
Option bits
8-BIT
LITE TIMER 2 COUNTER
fOSC
/32 DIVIDER
fOSC/32
fOSC
1
0
fLTIMER
(1ms timebase @ 8 MHz fOSC)
fCPU
TO CPU AND
PERIPHERALS
MCO SMS MCCSR
fCPU
Note: The PLL cannot be used with the external resonator oscillator
26/159
1
MCO
ST7LITE1xB
7.4 MULTI-OSCILLATOR (MO)
Table 4. ST7 Clock Sources
External Clock
Hardware Configuration
Crystal/Ceramic Resonators
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
Note: when the Multi-Oscillator is not used, PB4 is
selected by default as external clock.
Crystal/Ceramic Oscillators
In this mode, with a self-controlled gain feature,
oscillator of any frequency from 1 to 16MHz can be
placed on OSC1 and OSC2 pins. This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. In this
mode of the multi-oscillator, the resonator and the
load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Internal RC Oscillator
In this mode, the tunable 1%RC oscillator is used
as main clock source. The two oscillator pins have
to be tied to ground if dedicately using for oscillator
else can be found as general purpose IO.
The calibration is done through the RCCR[7:0] and
SICSR[6:5] registers.
Internal RC Oscillator
The main clock of the ST7 can be generated by
four different source types coming from the multioscillator block (1 to 16MHz):
■ an external source
■ 5 different configurations for crystal or ceramic
resonator oscillators
■ an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 4. Refer to the
electrical characteristics section for more details.
ST7
OSC1
OSC2
EXTERNAL
SOURCE
ST7
OSC1
CL1
OSC2
LOAD
CAPACITORS
CL2
ST7
OSC1
OSC2
27/159
1
ST7LITE1xB
7.5 RESET SEQUENCE MANAGER (RSM)
7.5.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 16:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Refer to section 12.2.1 on page 107 for further details.
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 15:
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (see table
below)
■ RESET vector fetch
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recommended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte:
The RESET vector fetch phase duration is 2 clock
cycles.
28/159
1
Clock Source
Internal RC Oscillator
External clock (connected to CLKIN pin)
External Crystal/Ceramic Oscillator
(connected to OSC1/OSC2 pins)
CPU clock
cycle delay
256
256
4096
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of tSTARTUP (see
Figure 13).
Figure 15. RESET Sequence Phases
RESET
Active Phase
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
7.5.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized (see Figure 17). This detection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
ST7LITE1xB
Figure 16. Reset Block Diagram
VDD
RON
RESET
INTERNAL
RESET
Filter
PULSE
GENERATOR
WATCHDOG RESET
ILLEGAL OPCODE RESET 1)
LVD RESET
Note 1: See “Illegal Opcode Reset” on page 107. for more details on illegal opcode reset conditions.
29/159
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ST7LITE1xB
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteristics section.
7.5.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until VDD is over the minimum
level specified for the selected fOSC frequency.
A proper reset signal for a slow rising VDD supply
can generally be provided by an external RC network connected to the RESET pin.
7.5.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD VN
VN > VP
VP > VN
VN > VP
COMPOUT
1
0
0
1
11.6.2.2
Programmable
External/Internal
Voltage Reference
The voltage reference module can be configured
to connect the comparator pin COMPIN- to one of
the following:
- Fixed internal voltage bandgap
- Programmable internal reference voltage
- External voltage reference
1) Fixed Internal Voltage Bandgap
The voltage reference module can generate a
fixed voltage reference of 1.2V on the VN input.
This is done by setting the VCBGR bit in the
VREFCR register.
2) Programmable Internal Voltage Reference
100/159
The internal voltage reference module can provide 16 distinct internally generated voltage levels from 3.2V to 0.2V each at a step of 0.2V on
comparator pin VN. The voltage is selected
through the VR[3:0] bits in the VREFCR register.
3) External Reference Voltage
If a reference voltage other than that generated
by the internal voltage reference module is
required, COMPIN- can be connected to an
external voltage source. This configuration can
be selected by setting the VCEXT bit in the
VREFCR register.
11.6.3 Functional Description
To make an analog comparison, the CMPON bit in
the CMPCR register must be set to power-on the
comparator and internal voltage reference module.
The VP comparator input is mapped on PB0 and is
also connected to ADC channel 0.
The VN comparator input is mapped on PB4 for
external voltage input, and is also connected to
ADC channel 4.
The internal voltage reference can provide a range
of different voltages to the comparator VN input,
selected by several bits in the VREFCR register,
as described in Table 20.
To select pins PB0 and PB4 for A/D conversion,
(default reset state), channel 0 or 4 must be selected through the channel selection bits in the ADCCSR register (refer to Section 11.5.6)
The comparator output is connected to pin PA7
when the COUT bit in the CMPCR register is set.
The comparator output is also connected internally
to the break function of the 12-bit Autoreload Timer (refer to Section 11.2)
When the Comparator is OFF, the output value of
comparator is ‘1’.
Important note: To avoid spurious toggling of the
output of the comparator due to noise on the voltage reference, it is recommended to enable the
hysteresis through the CHYST bit in the CMPCR
register.
ST7LITE1xB
ANALOG COMPARATOR (Cont’d)
Figure 61. Analog Comparator and Internal Voltage Reference
ADC channel 0
COMPIN+
(PB0)
Comparator
Voltage Reference
VP
VN
COMP
+
-
1.2V Bandgap
COMPIN(PB4)
4
Break input
to 12-bit Autoreload Timer
VR[3:0] bits
VCBGR bit
VCEXT bit
ADC Channel 4
Figure 62. Analog Comparator
Comparator
+
COMP
-
COMPOUT
Port PA7
CINV
CHYST
Rising Edge
0
Falling Edge
1
0
CINV CMPIF CMPIE CMP COUT CMPON
CMPCR
Comparator Interrupt
101/159
ST7LITE1xB
ANALOG COMPARATOR (Cont’d)
11.6.4 Register Description
Internal Voltage Reference Register (VREFCR)
Read/Write
Reset Value : 0000 0000 (00h)
7
VCEXT VCBGR VR3
0
VR2
VR1
VR0
0
0
VCEXT VCBGR VR3 VR2 VR1 VR0
bit
bit
bit bit bit bit
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
VN Voltage
1.2V
1V
0.8V
0.6V
0.4V
0.2V
Bits 1:0 = Reserved, Must be kept cleared.
Bit 7 = VCEXT External Voltage Reference for
Comparator
This bit is set or cleared by software. It is used to
connect the external reference voltage to the VN
comparator input.
0: External reference voltage not connected to VN
1: External reference voltage connected to VN
Bit 6 = VCBGR Bandgap Voltage for Comparator
This bit is set or cleared by software. It is used to
connect the bandgap voltage of 1.2V to the VN
comparator input.
0: Bandgap voltage not connected to VN
1: Bandgap voltage connected to VN
Bits 5:2 = VR[3:0] Programmable Internal Voltage
Reference Range Selection
These bits are set or cleared by software. They are
used to select one of 16 different voltages available from the internal voltage reference module and
connect it to comparator input VN.
Refer to Table 20.
Table 20. Voltage Reference Programming
VCEXT VCBGR VR3 VR2 VR1 VR0
bit
bit
bit bit bit bit
1
x
x
x
x
x
0
1
x
x
x
x
0
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
0
1
1
0
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
102/159
VN Voltage
VEXT
1.2 bandgap
3.2V
3V
2.8V
2.6V
2.4V
2.2V
2V
1.8V
1.6V
1.4V
Comparator Control Register (CMPCR)
Read/Write
Reset Value : 1000 0000 (80h)
7
CHYST
0
0
CINV CMPIF CMPIE CMP
COUT CMPON
Bit 7= CHYST Comparator Hysteresis Enable
This bit is set or cleared by software and set by
hardware reset. When this bit is set, the comparator hysteresis is enabled.
0: Hysteresis disabled
1: Hysteresis enabled
Note: To avoid spurious toggling of the output of
the comparator due to noise on the voltage reference, it is recommended to enable the hysteresis.
Bit 6 = Reserved, Must be kept cleared
Bit 5 = CINV Comparator Output Inversion Select
This bit is set or cleared by software and cleared
by hardware reset. When this bit is set, the comparator output is inverted.
If interrupt enable bit CMPIE is set in the CMPCR
register, the CINV bit is also used to select which
type of level transition on the comparator output
will generate the interrupt. When this bit is reset,
interrupt will be generated at the rising edge of the
comparator output change (COMP signal, refer to
Figure 62 on page 101). When this bit is set, interrupt will be generated at the falling edge of comparator output change (COMP signal, refer to Figure
62 on page 101).
0: Comparator output not inverted and interrupt
generated at the rising edge of COMP
1: Comparator output inverted and interrupt generated at the falling edge of COMP
ST7LITE1xB
ANALOG COMPARATOR (Cont’d)
Bit 4 = CMPIF Comparator Interrupt Flag
This bit is set by hardware when interrupt is generated at the rising edge (CINV = 0) or falling edge
(CINV = 1) of comparator output. This bit is
cleared by reading the CMPCR register. Writing to
this bit does not change the value.
0 : Comparator interrupt flag cleared
1 : Comparator interrupt flag set and can generate
interrupt if CMPIE is set.
Bit 1 = COUT Comparator Output Enable on Port
This bit is set or cleared by software. When this bit
is set, the comparator output is available on PA7
port.
0 : Comparator output not connected to PA7
1 : Comparator output connected to PA7
Bit 0 : CMPON Comparator ON/OFF
This bit is set or cleared by software and reset by
hardware reset. This bit is used to switch ON/OFF
the comparator, internal voltage reference and
current bias which provides 4µA current to both.
0: Comparator, Internal Voltage Reference, Bias
OFF (in power-down state).
1: Comparator, Internal Voltage Reference, Bias
ON
Note: For the comparator interrupt generation, it
takes 250ns delay from comparator output change
to rising or falling edge of interrupt generated.
Bit 3 : CMPIE Comparator Interrupt Enable
This bit is set or reset by software and cleared by
hardware reset. This bit enables or disables the interrupt generation depending on interrupt flag
0: Interrupt not generated
1: Interrupt generated if interrupt flag is set
Note:
This bit should be set to enable interrupt only after
the comparator has been switched ON, i.e. when
CMPON is set.
Once CMPON bit is set, it is recommended to wait
the specified stabilization time before setting
CMPIE bit in order to avoid a spurious interrupt
(see section 13.12 on page 143).
Bit 2 : CMP Comparator Output
This bit is set or reset by software and cleared by
hardware reset. It stores the value of comparator
output.
Table 21. Analog Comparator Register Map and Reset Values
Address
(Hex.)
002Ch
002Dh
Register
Label
VREFCR
Reset Value
CMPCR
Reset value
7
6
5
4
3
2
1
0
VCEXT
0
VCBGR
0
VR3
0
VR2
VR1
-
0
0
VR0
0
0
0
CHYST
1
-
CINV
CMPIF
CMPIE
CMP
COUT
CMPON
0
0
0
0
0
0
0
103/159
ST7LITE1xB
12 INSTRUCTION SET
12.1 ST7 ADDRESSING MODES
The ST7 Core features 17 different addressing
modes which can be classified in seven main
groups:
Addressing Mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset
byte,#5
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be subdivided in two submodes called long and short:
– Long addressing mode is more powerful because it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cycles.
– Short addressing mode is less powerful because
it can generally only access page zero (0000h 00FFh range), but the instruction size is more
compact, and faster. All memory to memory instructions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 22. ST7 Addressing Mode Overview
Mode
Syntax
Pointer
Address
(Hex.)
Destination/
Source
Pointer
Size
(Hex.)
Length
(Bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No Offset
Direct
Indexed
ld A,(X)
00..FF
+ 0 (with X register)
+ 1 (with Y register)
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed
Short
Indirect
ld A,($1000,X)
0000..FFFF
ld A,[$10]
00..FF
+2
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect
Indexed
ld A,([$10],X)
00..1FE
00..FF
byte
+2
Long
Indirect
Indexed
ld A,([$10.w],X)
0000..FFFF
00..FF
word
+2
byte
+2
1)
+1
Relative
Direct
jrne loop
PC-128/PC+127
Relative
Indirect
jrne [$10]
PC-128/PC+1271) 00..FF
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
btjt $10,#7,skip
00..FF
Relative
+1
00..FF
byte
+2
+2
Bit
Indirect Relative btjt [$10],#7,skip 00..FF
00..FF
byte
+3
Note:
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
104/159
ST7LITE1xB
ST7 ADDRESSING MODES (cont’d)
12.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction
Function
NOP
No operation
TRAP
S/W Interrupt
WFI
Wait For Interrupt (Low Power
Mode)
HALT
Halt Oscillator (Lowest Power
Mode)
RET
Subroutine Return
IRET
Interrupt Subroutine Return
SIM
Set Interrupt Mask
RIM
Reset Interrupt Mask
SCF
Set Carry Flag
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
LD
Load
CLR
Clear
PUSH/POP
Push/Pop to/from the stack
INC/DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
MUL
Byte Multiplication
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
12.1.2 Immediate
Immediate instructions have 2 bytes, the first byte
contains the opcode, the second byte contains the
operand value.
Immediate Instruction
Function
LD
Load
CP
Compare
BCP
Bit Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Operations
12.1.3 Direct
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two submodes:
Direct (Short)
The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF addressing
space.
Direct (Long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
12.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
submodes:
Indexed (No Offset)
There is no offset (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only 1 byte after
the opcode and allows 00 - 1FE addressing space.
Indexed (Long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
12.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two submodes:
Indirect (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
105/159
ST7LITE1xB
ST7 ADDRESSING MODES (cont’d)
12.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the unsigned addition of an index register value (X or Y)
with a pointer value located in memory. The pointer address follows the opcode.
The indirect indexed addressing mode consists of
two submodes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Table 23. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Instructions
Function
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Addition/subtraction operations
BCP
Bit Compare
Short Instructions Only
Function
CLR
Clear
INC, DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
BSET, BRES
Bit Operations
BTJT, BTJF
Bit Test and Jump Operations
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
106/159
12.1.7 Relative Mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Indirect Instructions
Function
JRxx
Conditional Jump
CALLR
Call Relative
The relative addressing mode consists of two submodes:
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the address follows the opcode.
ST7LITE1xB
12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
Increment/Decrement
INC
DEC
Compare and Tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit Operation
BSET
BRES
Conditional Bit Test and Branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and Rotates
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional Jump or Call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Conditional Branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Condition Code Flag modification
SIM
RIM
SCF
RCF
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they precede.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
RSP
RET
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit or direct relative addressing
mode to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruction using indirect X indexed addressing
mode.
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
12.2.1 Illegal Opcode Reset
In order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implemented. If a code to
be executed does not correspond to any opcode
or prebyte value, a reset is generated. This, combined with the Watchdog, allows the detection and
recovery from an unexpected fault or interference.
Note: A valid prebyte associated with a valid opcode forming an unauthorized combination does
not generate a reset.
107/159
ST7LITE1xB
INSTRUCTION GROUPS (cont’d)
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
ADC
Add with Carry
A=A+M+C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A, Memory
tst (A . M)
A
M
N
Z
BRES
Bit Reset
bres Byte, #3
M
BSET
Bit Set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1
M
C
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1
M
C
CALL
Call subroutine
CALLR
Call subroutine relative
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
CPL
One Complement
A = FFH-A
DEC
Decrement
dec Y
reg, M
HALT
Halt
IRET
Interrupt routine return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
JRIH
Jump if ext. interrupt = 1
1
Z
C
reg, M
N
Z
1
reg, M
N
Z
N
Z
N
Z
0
jrf *
JRIL
Jump if ext. interrupt = 0
JRH
Jump if H = 1
H=1?
JRNH
Jump if H = 0
H=0?
JRM
Jump if I = 1
I=1?
JRNM
Jump if I = 0
I=0?
JRMI
Jump if N = 1 (minus)
N=1?
JRPL
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned >=
JRUGT
Jump if (C + Z = 0)
Unsigned >
108/159
0
N
M
H
reg, M
I
C
ST7LITE1xB
INSTRUCTION GROUPS (cont’d)
Mnemo
Description
Function/Example
Dst
Src
JRULE
Jump if (C + Z = 1)
Unsigned
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