ST7LITE20F2 ST7LITE25F2
ST7LITE29F2
8-bit microcontroller with single voltage Flash memory, data
EEPROM, ADC, Timers, SPI
Datasheet - production data
Features
• Memories
– 8 Kbytes single voltage Flash Program
memory with Read-out protection
– In-circuit programming and in-application
programming (ICP and IAP)
– 10K write/erase cycles guaranteed
– Data retention: 20 years at 55 °C
– Temperature ranges:
–
-40 °C to +85 °C
–
-40 °C to +105 °C
– 384 bytes RAM
DIP20
SO20 300”
• 1 communication interface
– SPI synchronous serial interface.
• Interrupt management
– 10 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (on 4 vectors)
• Clock, reset and supply management
– Enhanced reset system
– Enhanced low voltage supervisor (LVD) for
main supply and an auxiliary voltage
detector (AVD) with interrupt capability for
implementing safe power-down procedures
– Clock sources: internal 1% RC oscillator,
crystal/ceramic resonator or external clock
– Internal 32-MHz input clock for auto-reload
timer
– Optional x4 or x8 PLL for 4 or 8 MHz
internal clock
– Five power saving modes: Halt, Active-halt,
Wait and Slow, Auto-wakeup from Halt
• Instruction set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode
detection
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
• I/O ports
– Up to 15 multifunctional bidirectional I/O
lines
– 7 high sink outputs
• Development tools
– Full hardware/software development
package
– DM (debug module)
• A/D converter
– 7 input channels
– Fixed gain op-amp
– 13-bit resolution for 0 to 430 mV
(@ 5 V VDD)
– 10-bit resolution for 430 mV to 5 V (@ 5 V
VDD)
• 4 timers
– Configurable watchdog timer
– Two 8-bit Lite timers with prescaler
– 1 real-time base and 1 input capture
– One 12-bit auto-reload timer with 4 PWM
outputs, input capture and output compare
functions
January 2014
This is information on a product in full production.
DocID8349 Rev 7
1/170
www.st.com
Contents
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
6
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4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3
Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.1
In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.2
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5
Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5.1
Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5.2
Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3
Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5
Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.6
Data EEPROM Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1
Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2
Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.3
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.4
Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.5
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.6
8
9
7.5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.5.2
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.5.3
External power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.5.4
Internal low voltage detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . 40
7.5.5
Internal watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.6.1
Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.6.2
Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.6.3
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.6.4
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.1
Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.2
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.3
Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2
SLOW mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.3
WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.4
HALT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.4.1
HALT mode recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.5
ACTIVE-HALT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.6
Auto-wakeup from HALT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.6.1
10
Contents
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.2.2
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.2.3
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.3
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.4
Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.5
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.7
Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.1
11.2
11.3
11.4
4/170
10.2.1
Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.1.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.1.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.1.4
Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.1.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.1.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12-bit autoreload timer 2 (AT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.2.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
11.2.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
11.2.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.2.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.2.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Lite timer 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.3.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.3.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.3.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.3.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.3.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.4.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.4.4
Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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12
11.4.5
Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.4.6
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.4.7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
11.4.8
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.5.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.5.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.5.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.5.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.5.6
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12.1
12.2
ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
12.1.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.1.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.1.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.1.4
Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.1.5
Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.1.6
Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.1.7
Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
12.2.1
13
Contents
Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
13.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
13.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.3.2
Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 121
13.3.3
Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 123
13.3.4
Internal RC oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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13.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.5
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.5.1
Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 131
13.6
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
13.7
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
13.7.1
Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . 134
13.7.2
Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . 135
13.7.3
Absolute maximum ratings (Electrical sensitivity) . . . . . . . . . . . . . . . . 136
13.8
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
13.9
Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
13.10 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 145
13.10.1 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
13.11 10-Bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
13.11.1 Amplifier output offset variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
14
15
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.2
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
15.1
16
6/170
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
15.1.1
Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
15.1.2
Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.2
Device ordering information and transfer of customer code . . . . . . . . . . 157
15.3
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
15.4
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
16.1
Execution of BTJX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
16.2
ADC conversion spurious results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
16.3
A/D converter accuracy for first conversion . . . . . . . . . . . . . . . . . . . . . . 165
16.4
Negative injection impact on ADC accuracy . . . . . . . . . . . . . . . . . . . . . 165
16.5
Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . 165
16.6
Using PB4 as external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
16.7
Timebase 2 interrupt in slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
DocID8349 Rev 7
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
17
Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
DocID8349 Rev 7
7/170
7
List of tables
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
8/170
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Row definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DATA EEPROM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Predefined calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CPU clock cycle delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Effect of low power modes on SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Flag description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
External interrupt I/O pin ei3[1:0] selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
External interrupt I/O pin ei2[1:0] selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
External interrupt I/O pin ei1[1:0] selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
External interrupt I/O pin ei0[1:0] selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ACTIVE-HALT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
AWU prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
DR value and output pin status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
I/O configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O port interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Ports PA7:0, PB6:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Port configuration (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Port configuration (Interrupt ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Ports where the external interrupt capability selected using the EISR register . . . . . . . . . 70
I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Effect of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Interrupts events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Effect of low power modes on Lite timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
TBxF and ICF interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Lite timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
WAIT and HALT mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SPI master mode SCK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Low power modes effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Channel selection bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
ADC clock speed selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
DocID8349 Rev 1
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
List of tables
ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Long and short instructions supporting direct, indexed,
indirect and indirect indexed addressing modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Short instructions supporting direct, indexed, indirect and indirect
indexed addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Relative direct and indirect instructions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Power on/power down operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
AVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Internal RC oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
RC oscillator and PLL characteristics
(tested for TA = -40 to +85°C) @ VDD = 4.5 to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
32 MHz PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Auto Wakeup from Halt Oscillator (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Resonator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Resonator performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
EEPROM data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Emission test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
ADC accuracy with VDD = 5.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Typical offset variation over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Small outline package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Dual in-line package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . 153
Option bytes values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Size definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Option byte default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
List of valid option combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Supported part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
ST7LITE2 FASTROM microcontroller option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
DocID8349 Rev 1
9/170
10
List of tables
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Table 99.
STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 100. ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 101. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
10/170
DocID8349 Rev 1
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
20-pin SO package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
20-pin DIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
EEPROM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data EEPROM Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PLL output frequency timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
RESET sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
RESET sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Low voltage detector vs. Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SLOW mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
WAIT mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HALT timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
HALT mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
ACTIVE-HALT timing overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ACTIVE-HALT mode Flow-chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
AWUF mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
AWUF halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
AWUF mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PWM inversion diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PWM signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Lite timer 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Generic SS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . . 98
Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
DocID8349 Rev 7
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12
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
12/170
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
fCPU maximum operating frequency versus VDD supply voltage . . . . . . . . . . . . . . . . . . . 121
RC Osc Freq vs VDD @ TA= 25°C (calibrated with RCCR1: 3V @ 25°C) . . . . . . . . . . . 125
RC Osc Freq vs VDD (calibrated with RCCR0: 5V@ 25°C). . . . . . . . . . . . . . . . . . . . . . . 126
Typical RC oscillator Accuracy vs temperature @ VDD=5V
(calibrated with RCCR0: 5V @ 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
RC Osc Freq vs VDD and RCCR Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
PLL DfCPU/fCPU versus time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
PLLx4 Output vs CLKIN frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
PLLx8 Output vs CLKIN frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Tipical IDD in RUN vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Typical IDD in SLOW vs. fCPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Typical IDD in WAIT vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Typical IDD in SLOW-WAIT vs. fCPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Typical IDD in AWUF mode at TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Typical IDD vs. temperature at VDD = 5V and fCPU = 8MHz . . . . . . . . . . . . . . . . . . . . . 130
Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Two typical applications with unused I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Typical IPU vs. VDD with VIN =VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Typical VOL at VDD = 2.4V (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Typical VOL at VDD = 2.7V (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Typical VOL at VDD = 3.3V (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Typical VOL at VDD = 5V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Typical VOL at VDD = 2.4V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Typical VOL at VDD = 5V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Typical VOL at VDD = 3V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Typical VDD-VOH at VDD = 2.4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Typical VDD-VOH at VDD = 2.7V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Typical VDD-VOH at VDD = 3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Typical VDD-VOH at VDD = 4V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Typical VDD-VOH at VDD = 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
VOL vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Typical VOL vs. VDD (high-sink I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Typical VDD-VOH vs. VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SPI slave timing diagram with CPHA = 0(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SPI slave timing diagram with CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SPI master timing diagram(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
ADC accuracy characteristics with amplifier disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
ADC accuracy characteristics with amplifier enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Amplifier noise vs voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
20-pin plastic small outline package, 300-mil width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
20-pin plastic dual in-line package, 300-mil width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
DocID8349 Rev 7
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
1
Description
Description
ST7LITE20F2, ST7LITE25F2 and ST7LITE29F2 are referred to as ST7LITE2. The
ST7LITE2 is a member of the ST7 microcontroller family. All ST7 devices are based on a
common industry-standard 8-bit core, featuring an enhanced instruction set.
The ST7LITE2 features FLASH memory with byte-by-byte In-Circuit Programming (ICP)
and In-Application Programming (IAP) capability.
Under software control, the ST7LITE2 device can be placed in WAIT, SLOW, or HALT
mode, reducing power consumption when the application is in idle or standby state.
The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
For easy reference, all parametric data are located in Section 15: Device configuration.
The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD).
For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.
Table 1. Device summary
Features
ST7LITE20F2
ST7LITE25F2
Program memory bytes
8 Kbyte
RAM (stack) - bytes
384 (128)
Data EEPROM - bytes
Peripherals
−
Lite timer with Watchdog,
autoreload timer, SPI,
10-bit ADC with Op-Amp
Operating supply
CPU frequency
Operating temperature
−
ST7LITE29F2
256
Lite timer with watchdog,
autoreload timer with 32-MHz input clock, SPI,
10-bit ADC with op-amp
2.4V to 5.5 V
Up to 8 MHz
(w/ ext OSC up to 16 MHz)
–40 °C to +85 °C
Packages
Up to 8 MHz (w/ ext OSC up to 16 MHz
and int 1MHz RC 1% PLLx8/4 MHz)
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +105 °C
SO20 300”, DIP20
DocID8349 Rev 7
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169
Description
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Figure 1. General block diagram
PLL
8 MHz -> 32 MHz
Int.
1% RC
1MHz
PLL x 8
or PLL X4
12-bit
Auto-reload
Timer 2
CLKIN
8-bit
Lite timer 2
/2
OSC1
OSC2
Ext.
OSC
1 MHz
to
16 MHz
Internal
clock
VDD
VSS
RESET
Power
supply
Control
8-bit core
ALU
14/170
Port B
ADDRESS AND DATA BUS
LVD
Port A
ADC
+ Op-amp
SPI
Debug module
Program
memory
(8 Kbytes)
Data EEPROM
(256 bytes)
RAM
(384 bytes)
Watchdog
DocID8349 Rev 7
PA7:0
(8 bits)
PB6:0
(7 bits)
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
2
Pin description
Pin description
Figure 2. 20-pin SO package pinout
VSS
VDD
RESET
1
20
2
19
3
18
SS/AIN0/PB0
4
SCK/AIN1/PB1
MISO/AIN2/PB2
MOSI/AIN3/PB3
CLKIN/AIN4/PB4
AIN5/PB5
IN/AIN6/PB6
5
ei3
17
ei0
16
6
15
7
14
8
ei2
13
ei1
9
12
10
11
OSC1/CLKIN
OSC2
PA0 (HS)/LTIC
PA1 (HS)/ATIC
PA2 (HS)/ATPWM0
PA3 (HS)/ATPWM1
PA4 (HS)/ATPWM2
PA5 (HS)/ATPWM3/ICCDATA
PA6/MCO/ICCCLK/BREAK
PA7(HS)
(HS) 20mA high sink capability
eix associated external interrupt vector
Figure 3. 20-pin DIP package pinout
MISO/AIN2/PB2
MOSI/AIN3/PB3
CLKIN/AIN4/PB4
1
ei3
ei3
2
3
20
19
18
ei2
AIN5/PB5
4
17
AIN6/PB6
PA7(HS)
MCO/ICCCLK/BREAK/PA6
ATPWM3/ICCDATA/PA5(HS)
ATPWM2/PA4(HS)
ATPWM1/PA3(HS)
5
16
6
15
7
14
ei1
13
8
9
10
ei0
ei0
12
11
SCK/AIN1/PB1
SS/AIN0/PB0
RESET
VDD
VSS
OSC1/CLKIN
OSC2
PA0(HS)/LTIC
PA1(HS)/ATIC
PA2(HS)/ATPWM0
(HS) 20mA high sink capability
eix associated external interrupt vector
Legend and abbreviations for device pin description (seeTable 2 below):
•
•
Type:
–
I = input
–
O = output
–
S = supply
In/Output level:
–
•
CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level:
–
HS = 20mA high sink (on N-buffer only)
DocID8349 Rev 7
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169
Pin description
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Port and control configuration:
•
Input:
–
•
float = floating, wpu = weak pull-up, int = interrupt, ana = analog
Output:
–
OD = open drain
–
PP = push-pull
The RESET configuration of each pin is shown in bold which is valid as long as the device is
in reset state.
Table 2. Device pin description
Pin
No.
Level
Port / Control
Main
function
(after
reset)
Input
Output
float
wpu
int
ana
Alternate function
DIP20
Output
SO20
Pin name
Type
Input
1
16 VSS
S
-
-
-
-
-
-
-
-
Ground
2
17 VDD
S
-
-
-
-
-
-
-
-
Main power supply
3
18 RESET
I/O CT
-
-
X
-
-
X
-
Top priority non maskable interrupt (active
low)
4
19 PB0/AIN0/SS
I/O
CT
X
X
X
X
Port B0
ADC analog input 0 or SPI Slave
Select (active low)(1)
5
20 PB1/AIN1/SCK
I/O
CT
X
X
X
X
Port B1
ADC analog input 1 or SPI Serial
Clock(1)
6
1
PB2/AIN2/MISO
I/O
CT
X
X
X
X
Port B2
ADC analog input 2 or SPI Master
in/ Slave out data
7
2
PB3/AIN3/MOSI
I/O
CT
X
X
X
X
Port B3
ADC analog input 3 or SPI Master
out / Slave in data
8
3
PB4/AIN4/CLKIN I/O
CT
X
X
X
X
Port B4
ADC analog input 4 or external
clock input
9
4
PB5/AIN5
I/O
CT
X
X
X
X
Port B5
ADC analog input 5
10 5
PB6/AIN6
I/O
CT
X
X
X
X
Port B6
ADC analog input 6
11 6
PA7
I/O CT HS
X
ei1
-
X
X
Port A7
12 7
PA6 /MCO/
ICCCLK/BREAK
I/O
X
ei1
-
X
X
Port A6
Main clock output or in circuit
communication clock or external
BREAK(2)
13 8
PA5 /ATPWM3/
ICCDATA
I/O CT HS
X
-
X
X
Port A5
Auto-reload timer PWM3 or In
circuit communication data
14 9
PA4/ATPWM2
I/O CT HS
X
-
X
X
Port A4
Auto-reload timer PWM2
16/170
CT
ei3
ei2
ei1
OD PP
DocID8349 Rev 7
-
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Pin description
Table 2. Device pin description (continued)
Pin
No.
Level
Port / Control
15 10 PA3/ATPWM1
I/O CT HS
X
16 11 PA2/ATPWM0
I/O CT HS
X
17 12 PA1/ATIC
I/O CT HS
X
18 13 PA0/LTIC
I/O CT HS
X
19 14 OSC2
O
−
−
-
-
20 15 OSC1/CLKIN
I
−
−
-
-
Output
ana
int
wpu
float
Output
Input
Pin name
Type
DIP20
SO20
Input
OD PP
Main
function
(after
reset)
Alternate function
-
X
X
Port A3
Auto-reload timer PWM1
-
X
X
Port A2
Auto-reload timer PWM0
-
X
X
Port A1
Auto-reload timer input capture
-
X
X
Port A0
Lite timer input capture
-
-
-
-
Resonator oscillator inverter output
-
-
-
-
Resonator oscillator inverter input or external
clock input
ei0
1. No negative current injection allowed on this pin. For details (refer toTable 58: Current characteristics).
2. During normal operation this pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy
environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is
configured as output, any reset will put it back in input pull-up.
DocID8349 Rev 7
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169
Register & memory map
3
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Register & memory map
As shown in Figure 4, the MCU is able of addressing 64K bytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, 384 bytes of
RAM, 256 bytes of data EEPROM and 8 Kbytes of user program memory. The RAM space
includes up to 128 bytes for the stack from 180h to 1FFh.
The highest address bytes contain the user reset and interrupt vectors.
The Flash memory contains two sectors (see Figure 4) mapped in the upper part of the ST7
addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh).
The size of Flash Sector 0 and other device options are configurable by Option byte (refer to
Section 15: Device configuration).
Note:
Memory locations marked as “Reserved” must never be accessed. Accessing a reserved
area can have unpredictable effects on the device.
Figure 4. Memory map
0080h
Short Addressing
RAM (zero page)
0000h
007Fh
0080h
00FFh
0100h
HW
registers(1)
16-bit Addressing
RAM
RAM
(384 Bytes)
017Fh
0180h
Reserved
01FFh
01FFh
20h
128 Bytes Stack
0FFFh
1000h
10FFh
1100h
1000h
Data EEPROM
(256 Bytes)
1001h
Reserved
E000h
Flash memory
(8K)
FBFFh
FC00h
FFFFh
7 Kbytes
SECTOR 1
1 Kbyte
SECTOR 0
FFDEh
Interrupt
& reset vectors(2)
FFFFh
FFDFh
1. SeeTable 3: Hardware register map
2. See Table 12: Interrupt mapping
3. See Section 7.1: Internal RC oscillator adjustment
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(3)
RCCR1
8K Flash
PROGRAM MEMORY
DFFFh
E000h
FFDFh
FFE0h
RCCR0
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RCCR0
RCCR1
(3)
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Register & memory map
Table 3. Hardware register map(1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
Register name
Reset
status
Port A
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
FFh(2)
00h
40h
R/W
R/W
R/W
Port B
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
FFh(2)
00h
00h
R/W
R/W
R/W(3)
Block
Register
label
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
Remarks
Reserved area (2 bytes)
Lite
TIMER 2
LTCSR2
LTARR
LTCNTR
LTCSR1
LTICR
Lite Timer Control/Status Register 2
Lite Timer Auto-reload Register
Lite Timer Counter Register
Lite Timer Control/Status Register 1
Lite Timer Input Capture Register
00h
00h
00h
0X00 0000h
00h
R/W
R/W
Read only
R/W
Read only
Autoreload
TIMER 2
ATCSR
CNTRH
CNTRL
ATRH
ATRL
PWMCR
PWM0CSR
PWM1CSR
PWM2CSR
PWM3CSR
DCR0H
DCR0L
DCR1H
DCR1L
DCR2H
DCR2L
DCR3H
DCR3L
ATICRH
ATICRL
TRANCR
BREAKCR
Timer Control/Status Register
Counter Register High
Counter Register Low
Auto-Reload Register High
Auto-Reload Register Low
PWM Output Control Register
PWM 0 Control/Status Register
PWM 1 Control/Status Register
PWM 2 Control/Status Register
PWM 3 Control/Status Register
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
PWM 1 Duty Cycle Register High
PWM 1 Duty Cycle Register Low
PWM 2 Duty Cycle Register High
PWM 2 Duty Cycle Register Low
PWM 3 Duty Cycle Register High
PWM 3 Duty Cycle Register Low
Input Capture Register High
Input Capture Register Low
Transfer Control Register
Break Control Register
0X00 0000h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
01h
00h
R/W
Read only
Read only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read only
Read only
R/W
R/W
0023h to
002Dh
Reserved area (11 bytes)
002Eh
WDG
WDGCR
Watchdog Control Register
7Fh
R/W
0002Fh
Flash
FCSR
Flash Control/Status Register
00h
R/W
00030h
EEPROM
EECSR
Data EEPROM Control/Status Register
00h
R/W
0031h
0032h
0033h
SPI
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
xxh
0xh
00h
R/W
R/W
R/W
0034h
0035h
0036h
ADC
ADCCSR
ADCDRH
ADCDRL
A/D Control Status Register
A/D Data Register High
A/D Amplifier Control/Data Low Register
00h
xxh
0xh
R/W
Read Only
R/W
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Table 3. Hardware register map(1) (continued)
Address
Block
0037h
ITC
0038h
MCC
0039h
003Ah
Clock and
Reset
Register
label
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
Remarks
External Interrupt Control Register
00h
R/W
MCCSR
Main Clock Control/Status Register
00h
R/W
RCCR
SICSR
RC oscillator Control Register
System Integrity Control/Status Register
FFh
R/W
0000 0XX0h R/W
Reserved area (1 byte)
ITC
EISR
003Dh to
0048h
0049h
004Ah
Reset
status
EICR
003Bh
003Ch
Register name
External Interrupt Selection Register
0Ch
R/W
Reserved area (12 bytes)
AWU
AWUPR
AWUCSR
AWU Prescaler Register
AWU Control/Status Register
FFh
00h
R/W
R/W
DM(4)
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DM Control Register
DM Status Register
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
0051h to
007Fh
Reserved area (47 bytes)
1. Legend: x = undefined, R/W = read/write.
2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
3. The bits associated with unavailable pins must always keep their reset value.
4. For a description of the Debug Module registers, see ICC reference manual.
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Flash program memory
4
Flash program memory
4.1
Introduction
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be
electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in
parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using in-circuit programming or in-application programming.
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
4.3
Main features
•
ICP (in-circuit programming)
•
IAP (in-application programming)
•
ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
•
Sector 0 size configurable by option byte
•
Read-out and write protection
Programming modes
The ST7 can be programmed in three different ways:
4.3.1
•
Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte row
and data EEPROM (if present) can be programmed or erased.
•
In-circuit programming. In this mode, Flash sectors 0 and 1, option byte row and data
EEPROM (if present) can be programmed or erased without removing the device from
the application board.
•
In-application programming. In this mode, sector 1 and data EEPROM (if present) can
be programmed or erased without removing the device from the application board and
while the application is running.
In-circuit programming (ICP)
ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a
printed circuit board (PCB) to communicate with an external programming device connected
via cable. ICP is performed in three steps:
1.
Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a
specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low.
When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the
ST7 System Memory containing the ICC protocol routine. This routine enables the ST7
to receive bytes from the ICC interface.
2.
Download ICP driver code in RAM from the ICCDATA pin.
3.
Execute ICP driver code in RAM to program the Flash memory.
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Depending on the ICP driver code downloaded in RAM, Flash memory programming can be
fully customized (number of bytes to program, program locations, or selection of the serial
communication interface for downloading).
4.3.2
In-application programming (IAP)
This mode uses an IAP driver program previously programmed in Sector 0 by the user (in
ICP mode).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored etc.).
IAP mode can be used to program any memory areas except Sector 0, which is write/erase
protected to allow recovery in case errors occur during the programming operation.
4.4
ICC interface
ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These
pins are:
•
RESET: device reset
•
VSS: device power supply ground
•
ICCCLK: ICC output serial clock pin
•
ICCDATA: ICC input serial data pin
•
CLKIN/PB4: main clock input for external source
•
VDD: application board power supply (optional).
If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal
isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an
ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the
application. If they are used as inputs by the application, isolation such as a serial resistor
has to be implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
During the ICP session, the programming tool must control the RESET pin. This can lead to
conflicts between the programming tool and the application reset circuit if it drives more than
5mA at high level (push pull output or pull-up resistor1 kΩ or a reset management IC with open drain output and pull-up resistor > 1 kΩ, no
additional components are needed. In all cases the user must ensure that no external reset
is generated by the application during the ICC session.
The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This
pin must be connected when using most ST Programming Tools (it is used to monitor the
application power supply). Please refer to the Programming Tool manual.
Pin 9 has to be connected to the CLKIN/PB4 pin of the ST7 when the clock is not available
in the application or if the selected clock option is not programmed in the option byte. ST7
devices with multi-oscillator capability need to have OSC1 and OSC2 grounded in this case.
With any programming tool, while the ICP option is disabled, the external clock has to be
provided on PB4.
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Caution:
Flash program memory
During normal operation the ICCCLK pin must be pulled up, internally or externally (external
pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode
unexpectedly during a reset. In the application, even if the pin is configured as output, any
reset will put it back in input pull-up.
Figure 5. Typical ICC interface
Programming tool
ICC connector
ICC Cable
ICC connector
HE10 connector type
Optional
9
7
5
3
1
10
8
6
4
2
Application board
Application
reset source
Application
power supply
4.5
ICCDATA
RESET
ST7
ICCCLK
CLKIN/PB4
(See Note 5)
VDD
Application
I/O
Memory protection
There are two different types of memory protection: Read-Out Protection and Write/Erase
Protection which can be applied individually.
4.5.1
Read-out protection
Read-out protection, when selected provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller. Both program and data E2 memory are protected.
In flash devices, this protection is removed by reprogramming the option. In this case, both
program and data E2 memory are automatically erased and the device can be
reprogrammed.
Read-out protection selection depends on the device type:
4.5.2
•
In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
•
In ROM devices it is enabled by mask option specified in the Option List.
Flash write/erase protection
Write/erase protection, when set, makes it impossible to both overwrite and erase program
memory. It does not apply to E2 data. Its purpose is to provide advanced security to
applications and prevent any change being made to the memory content.
Caution:
Once set, Write/erase protection can never be removed. A write-protected flash device is no
longer reprogrammable.
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Write/erase protection is enabled through the FMP_W bit in the option byte.
4.6
Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual.
4.7
Register description
Flash control/status register (FCSR)
Read / Write
Reset value: 0000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
7
0
Note:
0
0
0
0
0
OPT
LAT
PGM
This register is reserved for programming using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing operations.
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys
are sent automatically.
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5
Data EEPROM
5.1
Introduction
Data EEPROM
The Electrically Erasable Programmable Read Only Memory can be used as a non-volatile
backup for storing data. Using the EEPROM requires a basic access protocol described in
this chapter.
5.2
Main features
•
Up to 32 bytes programmed in the same cycle
•
EEPROM mono-voltage (charge pump)
•
Chained erase and programming cycles
•
Internal control of the global programming cycle duration
•
WAIT mode management
•
Read-out protection
Figure 6. EEPROM block diagram
High voltage
pump
EECSR
0
0
0
Address
decoder
0
0
4
0
E2LAT E2PGM
EEPROM
Row
memory matrix
decoder
(1 ROW = 32 x 8 BITS)
128
4
128
Data
32 x 8 bits
multiplexer
data latches
4
Address bus
5.3
DATA BUS
Memory access
The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the
EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these
different memory access modes.
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Read operation (E2LAT=0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR
register is cleared.
On this device, Data EEPROM can also be used to execute machine code. Take care not to
write to the Data EEPROM while executing from it. This would result in an unexpected code
being executed.
Write operation (E2LAT=1)
To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains
cleared). When a write access to the EEPROM area occurs, the value is latched inside the
32 data latches according to its address.
When PGM bit is set by the software, all the previous bytes written in the data latches (up to
32) are programmed in the EEPROM cells. The effective high address (row) is determined
by the last EEPROM write sequence. To avoid wrong programming, the user must take care
that all the bytes written between two programming sequences have the same high
address: only the five Least Significant Bits of the address can change.
At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.
Note:
Care should be taken during the programming cycle. Writing to the same memory location
will over-program the memory (logical AND between the two write access data result)
because the data latches are only cleared at the end of the programming cycle and by the
falling edge of the E2LAT bit.
It is not possible to read the latched data.
This note is illustrated by the Figure 9: Data EEPROM programming cycle.
Figure 7. Data EEPROM programming flowchart
Read mode
E2LAT=0
E2PGM=0
Write mode
E2LAT=1
E2PGM=0
Read bytes
in EEPROM area
Write up to 32 bytes
in EEPROM area
(with the same 11 MSB of the address)
Start programming cycle
E2LAT=1
E2PGM=1 (set by software)
0
Cleared by hardware
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Data EEPROM
Table 4. Row definition
⇓ Row / Byte ⇒
0
1
2
3
...
30
31
Physical address
0
00h...1Fh
1
20h...3Fh
...
N
Nx20h...Nx20h+1Fh
Figure 8. Data EEPROM Write operation
Read operation impossible
Byte 1
Byte 2
Byte 32
Read operation possible
Programming cycle
PHASE 1
PHASE 2
Writing data latches
Waiting E2PGM and E2LAT to fall
E2LAT bit
Set by USER application
Cleared by hardware
E2PGM bit
Note:
If a programming cycle is interrupted (by a reset action), the integrity of the data in memory
is not guaranteed.
5.4
Power saving modes
WAIT mode
The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the
microcontroller or when the microcontroller enters ACTIVE-HALT mode.The DATA
EEPROM will immediately enter this mode if there is no programming in progress, otherwise
the DATA EEPROM will finish the cycle and then enter WAIT mode.
ACTIVE-HALT mode
Refer to WAIT mode.
HALT mode
The DATA EEPROM immediately enters HALT mode if the microcontroller executes the
HALT instruction. Therefore the EEPROM will stop the function in progress, and data may
be corrupted.
5.5
Access error handling
If a read access occurs while E2LAT=1, then the data bus will not be driven.
If a write access occurs while E2LAT=0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by a RESET action), the memory data will not be
guaranteed.
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Data EEPROM Read-out protection
The Read-out protection is enabled through an option bit (see Section 15.1: Option bytes).
When this option is selected, the programs and data stored in the EEPROM memory are
protected against Read-out (including a re-write protection). In Flash devices, when this
protection is removed by reprogramming the Option Byte, the entire Program memory and
EEPROM is first automatically erased.
Note:
Both Program Memory and DATA EEPROM are protected using the same option bit.
Figure 9. Data EEPROM programming cycle
Read operation not possible
Read operation possible
Internal
programming
voltage
Erase cycle
Write cycle
Write of
data latches
tPROG
LAT
PGM
5.7
Register description
EEPROM Control/Status register (EECSR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
Note:
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0
0
0
0
0
0
E2LAT
E2PGM
•
Bits 7:2 = Reserved, forced by hardware to 0.
•
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hardware at the end of the programming
cycle. It can only be cleared by software if the E2PGM bit is cleared.
0: Read mode
1: Write mode
•
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming cycle. At the end of the
programming cycle, this bit is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
If the E2PGM bit is cleared during the programming cycle, the memory data is not
guaranteed.
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Data EEPROM
Table 5. DATA EEPROM register map and reset values
Address
(Hex.)
0030h
Register
label
EECSR
Reset
Value
7
6
5
4
3
2
1
0
0
0
0
0
0
0
E2LAT
0
E2PGM
0
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6
Central processing unit
6.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient
8-bit data manipulation.
6.2
6.3
Main features
•
63 basic instructions
•
Fast 8-bit by 8-bit multiply
•
17 main addressing modes
•
Two 8-bit index registers
•
16-bit stack pointer
•
Low power modes
•
Maskable hardware interrupts
•
Non-maskable software interrupt
CPU registers
The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are
accessed by specific instructions.
Figure 10. CPU registers
7
0
Accumulator
Reset value = XXh
7
0
X index register
Reset value = XXh
7
0
Y index register
Reset value = XXh
15
PCH
PCL
8 7
0
Program counter
Reset value = reset vector @ FFFEh-FFFFh
7
0
1 1 1 H I
Reset value =
15
N Z C
Condition code register
1 1 1 X 1 X X X
8 7
0
Stack pointer
Reset value = stack higher address
X = Undefined value
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Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
Index registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective
addresses or temporary storage areas for data manipulation. The cross-assembler
generates a precede instruction (PRE) to indicate that the following instruction refers to the
Y register.
The Y register is not affected by the interrupt automatic procedures (not pushed to and
popped from the stack).
Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is
the LSB) and PCH (program counter high which is the MSB).
Condition code register (CC)
Read / Write
Reset value: 111x1xxx
7
1
0
1
1
H
I
N
Z
C
The 8-bit Condition Code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
•
Bit 4 = H Half carry
•
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during
an ADD or ADC instruction. It is reset by hardware during the same instructions.
0: No half carry has occurred
1: A half carry has occurred
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
Bit 3 = I Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled
1: Interrupts are disabled
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM
and JRNM instructions.
Note:
Interrupts requested while I is set are latched and can be processed when I is cleared. By
default an interrupt routine is not interruptible because the I bit is set by hardware at the start
of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared
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by software in the interrupt routine, pending interrupts are serviced regardless of the priority
level of the current interrupt routine.
•
Bit 2 = N Negative
This bit is set and cleared by hardware. It is representative of the result sign of the last
arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.
0: The result of the last operation is positive or null
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1)
This bit is accessed by the JRMI and JRPL instructions.
•
Bit 1 = Z Zero
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero
1: The result of the last operation is zero
This bit is accessed by the JREQ and JRNE test instructions.
•
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred
1: An overflow or underflow has occurred
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
Stack pointer register (SP)
Read / Write
Reset value: 01FFh
15
0
8
0
0
0
0
0
0
7
1
1
0
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 11).
Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD
instruction.
Note:
When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
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pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 11:
•
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
•
On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 11. Stack manipulation example
CALL
Subroutine
PUSH Y
Interrupt
Event
POP Y
RET
or RSP
IRET
@ 0180h
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
SP
@ 01FFh
SP
SP
SP
Stack higher address = 01FFh
Stack lower address = 0180h
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7
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Supply, reset and clock management
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components.
Main features
•
7.1
Clock management
–
1 MHz internal RC oscillator (enabled by option byte, available on ST7LITE25 and
ST7LITE29 devices only)
–
1 to 16 MHz or 32kHz External crystal/ceramic resonator (selected by option byte)
–
External Clock Input (enabled by option byte)
–
PLL for multiplying the frequency by 8 or 4 (enabled by option byte)
–
For clock ART counter only: PLL32 for multiplying the 8 MHz frequency by 4
(enabled by option byte). The 8 MHz input frequency is mandatory and can be
obtained in the following ways:
. 1 MHz RC + PLLx8
. 16 MHz external clock (internally divided by 2)
. 2 MHz external clock (internally divided by 2) + PLLx8
. Crystal oscillator with 16 MHz output frequency (internally divided by 2).
•
Reset Sequence Manager (RSM)
•
System Integrity Management (SI)
–
Main supply Low Voltage Detection (LVD) with reset generation (enabled by option
byte)
–
Auxiliary Voltage Detector (AVD) with interrupt capability for monitoring the main
supply (enabled by option byte).
Internal RC oscillator adjustment
The device contains an internal RC oscillator with an accuracy of 1% for a given device,
temperature and voltage range (4.5 V - 5.5 V). It must be calibrated to obtain the frequency
required in the application. This is done by software writing a calibration value in the RCCR
(RC Control Register).
Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each
time the device is reset, the calibration value must be loaded in the RCCR. Predefined
calibration values are stored in EEPROM for 3 and 5 V VDD supply voltages at 25 °C, as
shown in Table 6.
Table 6. Predefined calibration values
RCCR
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Conditions
ST7LITE29
address
ST7LITE25
address
RCCR0
VDD = 5 V, TA = 25 °C, fRC = 1 MHz
1000h and FFDEh
FFDEh
RCCR1
VDD = 3 V, TA = 25 °C, fRC = 700 kHz
1001h and FFDFh
FFDFh
DocID8349 Rev 7
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Note:
Supply, reset and clock management
See Section 13: Electrical characteristics for more information on the frequency and
accuracy of the RC oscillator.
To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7
device.
These two bytes are systematically programmed by ST, including on FASTROM devices.
Consequently, customers intending to use FASTROM service must not use these two bytes.
RCCR0 and RCCR1 calibration values will be erased if the Read-out protection bit is reset
after it has been set. See Section 4.5.1: Read-out protection.
Caution:
If the voltage or temperature conditions change in the application, the frequency may need
to be recalibrated.
Refer to application note AN1324 for information on how to calibrate the RC frequency using
an external reference signal.
7.2
Phase locked loop (PLL)
The PLL can be used to multiply a 1 MHz frequency from the RC oscillator or the external
clock by 4 or 8 to obtain fOSC of 4 or 8 MHz. The PLL is enabled and the multiplication factor
of 4 or 8 is selected by 2 option bits.
The x4 PLL is intended for operation with VDD in the 2.4 V to 3.3 V range
•
The x8 PLL is intended for operation with VDD in the 3.3 V to 5.5 V range
Refer to Section 15.1: Option bytes for the option byte description.
If the PLL is disabled and the RC oscillator is enabled, then fOSC = 1 MHz.
If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock.
Figure 12. PLL output frequency timing diagram
LOCKED bit set
4/8 x
input
freq.
tSTAB
Output freq.
Note:
•
tLOCK
tSTARTUP
t
When the PLL is started, after reset or wakeup from HALT mode or AWUF mode, it outputs
the clock after a delay of tSTARTUP.
When the PLL output signal reaches the operating frequency, the LOCKED bit in the
SICSCR register is set. Full PLL accuracy (ACCPLL) is reached after a stabilization time of
tSTAB (see Figure 12 below and Figure 64: RC oscillator and PLL characteristics (tested
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
for TA = -40 to +85°C) @ VDD = 4.5 to 5.5 V).
Refer to Section 7.6.4: Register description for a description of the LOCKED bit in the
SICSR register.
7.3
Register description
Main clock control/status register (MCCSR)
Read / Write
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
MCO
SMS
•
Bits 7:2 = Reserved, must be kept cleared
•
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by hardware after a reset. This bit allows
to enable the MCO output clock.
0: MCO clock disabled, I/O port free for general purpose I/O.
1: MCO clock enabled.
•
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the input clock fOSC2 or fOSC2/32.
0: Normal mode (fCPU = fOSC2
1: Slow mode (fCPU = fOSC2/32)
RC control register (RCCR)
Read / Write
Reset value: 1111 1111 (FFh)
7
CR70
•
Note:
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0
CR60
CR50
CR40
CR30
CR20
CR10
CR0
Bits 7:0 = CR[7:0] RC oscillator frequency adjustment bits
These bits must be written immediately after reset to adjust the RC oscillator frequency
and to obtain an accuracy of 1%. The application can store the correct value for each
voltage range in EEPROM and write it to this register at startup.
00h = maximum available frequency
FFh = lowest available frequency
To tune the oscillator, write a serie of different values in the register until the correct
frequency is reached. The fastest method is to use a dichotomy starting with 80h.
DocID8349 Rev 7
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Supply, reset and clock management
Figure 13. Clock management block diagram
CR7
CR6
CR5
CR4
CR3
CR2
CR1
RCCR
CR0
PLL
8 MHz -> 32 MHz
fCPU
Tunable
1% RC oscillator
Osc,PLLoff,
OSCRANGE[2:0]
Option bits
12-bit
at TIMER 2
RC OSC
PLLx4x8
CLKIN
CLKIN
CLKIN
CLKIN
/OSC1
OSC2
OSC
1-16 MHZ
or 32 kHz
PLL 1 MHz -> 8 MHz
PLL 1 MHz -> 4 MHz
/2
divider
OSC
fOSC
CLKIN/2
CLKIN/2
OSC/2
/2
divider
Osc,PLLoff,
OSCRANGE[2:0]
Option bits
8-bit
Lite timer 2 counter
fOSC
/32 divider
fOSC/32
fOSC
fLTIMER
(1ms timebase @ 8 MHz fOSC)
1
0
fCPU
To CPU and
peripherals
MCO SMS MCCSR
fCPU
7.4
MCO
Multi-oscillator (MO)
The main clock of the ST7 can be generated by four different source types coming from the
multioscillator block (1 to 16MHz or 32kHz):
•
an external source
•
5 crystal or ceramic resonator oscillators
•
an internal high frequency RC oscillator.
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Table 7.
Note:
Refer to Section 13: Electrical characteristics for more details.
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
When the Multi-oscillator is not used, PB4 is selected by default as external clock.
Crystal/ceramic oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main
clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges
has to be done by option byte in order to reduce consumption (refer to Section 15.1: Option
bytes for more details on the frequency ranges). In this mode of the multi-oscillator, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. The loading
capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the RESET phase to avoid losing time in the
oscillator startup phase.
Internal RC oscillator
In this mode, the tunable 1% RC oscillator is used as main clock source. The two oscillator
pins have to be tied to ground.
Table 7. ST7 clock sources
Clock source
Hardware configuration
ST7
OSC1
OSC2
External clock
External
source
ST7
OSC1
OSC2
Crystal/ceramic resonators
CL1
Load
capacitors
CL2
ST7
OSC1
Internal RC oscillator or
external clock on PB4
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Supply, reset and clock management
7.5
Reset sequence manager (RSM)
7.5.1
Introduction
The reset sequence manager includes three RESET sources as shown in Figure 15: Reset
block diagram:
Note:
•
External RESET source pulse
•
Internal LVD RESET (low voltage detection)
•
Internal WATCHDOG RESET
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 12.2.1: Illegal opcode reset for further details.
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic RESET sequence consists of 3 phases as shown in Figure 14:
•
Active Phase depending on the RESET source
•
256 or 4096 CPU clock cycle delay (see table below)
•
RESET vector fetch.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay is
automatically selected depending on the clock source chosen by option byte:
Table 8. CPU clock cycle delay
CPU clock
cycle delay
Clock source
Internal RC oscillator
256
External clock (connected to CLKIN pin)
256
External crystal/ceramic oscillator
(connected to OSC1/OSC2 pins)
4096
The RESET vector fetch phase duration is 2 clock cycles.
If the PLL is enabled by option byte, it outputs the clock after an additional delay of tSTARTUP
(see Figure 12: PLL output frequency timing diagram).
Figure 14. RESET sequence phases
RESET
Active phase
Internal reset
256 or 4096 clock cycles
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7.5.2
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device.
Note:
See Section 13: Electrical characteristics for more details.
A RESET signal originating from an external source must have a duration of at least
th(RSTL)in in order to be recognized (see Figure 16: RESET sequences). This detection is
asynchronous and therefore the MCU can enter reset state even in HALT mode.
Figure 15. Reset block diagram
VDD
RON
RESET
Internal
reset
Filter
Pulse
generator
Note:
WATCHDOG RESET
Illegal OPCODE RESET
LVD RESET
See Section 12.2.1: Illegal opcode reset for more details on illegal opcode reset conditions.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in Section 13:
Electrical characteristics.
7.5.3
External power-on RESET
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until VDD is over
the minimum level specified for the selected fOSC frequency.
A proper reset signal for a slow rising VDD supply can generally be provided by an external
RC network connected to the RESET pin.
7.5.4
Internal low voltage detector (LVD) RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
•
Power-on RESET
•
Voltage drop RESET.
The device RESET pin acts as an output that is pulled low when VDD=
−
−
−
−
−
−
−
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−
reg, M
jrf *
DocID8349 Rev 7
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Instruction set
Table 56. Instruction set overview (continued)
Mnemo
Description
Function/example
Dst
Src
H
I
N
Z
C
JRUGT
Jump if (C + Z = 0)
Unsigned >
−
−
−
−
−
−
−
JRULE
Jump if (C + Z = 1)
Unsigned
