ST7LITE3xF2
8-bit MCU with single voltage Flash, data EEPROM, ADC, timers,
SPI, LINSCI™
Features
■
■
■
■
Memories
– 8 Kbytes program memory: single voltage extended Flash (XFlash) Program memory with
read-out protection, In-Circuit Programming
and In-Application programming (ICP and
IAP), data retention: 20 years at 55°C.
– 384 bytes RAM
– 256 bytes data EEPROM with read-out protection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C.
Clock, Reset and Supply Management
– Enhanced reset system
– Enhanced low voltage supervisor (LVD) for
main supply and an auxiliary voltage detector
(AVD) with interrupt capability for implementing safe power-down procedures
– Clock sources: Internal RC 1% oscillator,
crystal/ceramic resonator or external clock
– Optional x4 or x8 PLL for 4 or 8 MHz internal
clock
– Five Power Saving Modes: Halt, Active-Halt,
Wait and Slow, Auto Wake Up From Halt
I/O Ports
– Up to 15 multifunctional bidirectional I/O lines
– 7 high sink outputs
5 Timers
– Configurable Watchdog Timer
– Two 8-bit Lite Timers with prescaler,
1 realtime base and 1 input capture
– Two 12-bit Auto-reload Timers with 4 PWM
outputs, input capture and output compare
functions
QFN20
SO20
DIP20
2 Communication Interfaces
– Master/slave LINSCI™ asynchronous serial
interface
– SPI synchronous serial interface
■ Interrupt Management
– 10 interrupt vectors plus TRAP and RESET
– 12 external interrupt lines (on 4 vectors)
■ A/D Converter
– 7 input channels
– 10-bit resolution
■ Instruction Set
8-bit data manipulation
– 63 basic instructions with illegal opcode
detection
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
■ Development Tools
– Full hardware/software development package
– DM (Debug module)
■
Table 1. Device summary
Features
Program memory - bytes
RAM (stack) - bytes
Data EEPROM - bytes
Peripherals
Operating Supply
CPU Frequency
Operating Temperature
Packages
ST7LITE30F2
ST7LITE35F2
ST7LITE39F2
8K
384 (128)
256
Lite Timer, Autoreload Timer, SPI, LINSCI, 10-bit ADC
2.7V to 5.5V
Up to 8Mhz
Up to 8Mhz (w/ ext OSC up to 16MHz
(w/ ext OSC up to 16MHz)
and int 1MHz RC 1% PLLx8/4MHz)
-40°C to +125°C
SO20 300”, DIP20, QFN20
Rev. 9
November 2007
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1
Table of Contents
ST7LITE3xF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4
ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5
MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6
RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7
REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3
MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4
POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5
ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6
DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7
REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3
CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2
PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3
REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4
MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5
RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.6
SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.2
EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.3
PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.2
SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.3
WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.4
HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Table of Contents
9.5
ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.6
AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2 DUAL 12-BIT AUTORELOAD TIMER 3 (AT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . . 90
11.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS . . . . . . . . . . . . 146
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 155
13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
14.2 THERMAL CHARACTERISTICS
160
15 DEVICE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
15.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 163
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
16.1 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 169
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16.2 LINSCI LIMITATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
To obtain the most recent version of this datasheet,
please check at www.st.com
Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 169.
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ST7LITE3xF2
1 INTRODUCTION
The ST7LITE3 is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set.
The ST7LITE3 features FLASH memory with
byte-by-byte In-Circuit Programming (ICP) and InApplication Programming (IAP) capability.
Under software control, the ST7LITE3 device can
be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in
idle or standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes.
For easy reference, all parametric data are located
in section 13 on page 131.
The devices feature an on-chip Debug Module
(DM) to support in-circuit debugging (ICD). For a
description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.
Figure 1. General Block Diagram
Int.
1% RC
1MHz
12-Bit
Auto-Reload
TIMER 2
PLL x 8
or PLL X4
CLKIN
8-Bit
LITE TIMER 2
/2
OSC1
OSC2
Ext.
OSC
1MHz
to
16MHz
Internal
CLOCK
VDD
VSS
RESET
POWER
SUPPLY
CONTROL
8-BIT CORE
ALU
ADDRESS AND DATA BUS
LVD
PORT A
PORT B
PA7:0
(8 bits)
PB6:0
(7 bits)
ADC
Debug Module
SPI
LINSCI
PROGRAM
MEMORY
(8K Bytes)
WDG
RAM
(384 Bytes)
DATA EEPROM
( 256 Bytes)
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1
ST7LITE3xF2
2 PIN DESCRIPTION
OSC2
17
VSS
20 19 18
VDD
OSC1/CLKIN
Figure 2. 20-Pin QFN Package Pinout
RESET
1
16
PA0 (HS)/LTIC
SS/AIN0/PB0
2
15
PA1 (HS)/ATIC
SCK/AIN1/PB1
3
14
PA2 (HS)/ATPWM0
MISO/AIN2/PB2
4
13
PA3 (HS)/ATPWM1
MOSI/AIN3/PB3
5
12
PA4 (HS)/ATPWM2
11
PA5 (HS)/ATPWM3/ICCDATA
ei3
ei0
ei2
ei1
ei2
7
8
9
10
RDI/AIN6/PB6
TDO/PA7(HS)
MCO/ICCCLKBREAK/PA6
6
AIN5/PB5
CLKIN/AIN4/PB4
(HS) 20mA High sink capability
eix associated external interrupt vector
Figure 3. 20-Pin SO and DIP Package Pinout
VSS
20
OSC1/CLKIN
2
19
3
18
OSC2
PA0 (HS)/LTIC
SS/AIN0/PB0
4
17
PA1 (HS)/ATIC
VDD
RESET
1
SCK/AIN1/PB1
5
MISO/AIN2/PB2
6
MOSI/AIN3/PB3
7
CLKIN/AIN4/PB4
8
AIN5/PB5
RDI/AIN6/PB6
9
10
ei3
ei0
ei2
ei1
ei2
16
PA2 (HS)/ATPWM0
15
PA3 (HS)/ATPWM1
14
PA4 (HS)/ATPWM2
13
12
PA5 (HS)/ATPWM3/ICCDATA
PA6/MCO/ICCCLK/BREAK
11
PA7 (HS)/TDO
(HS) 20mA high sink capability
eix associated external interrupt vector
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ST7LITE3xF2
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations for Table 2:
Type:
I = input, O = output, S = supply
In/Output level: CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt, ana = analog
– Output:
OD = open drain, PP = push-pull
The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 2. Device Pin Description
Port / Control
S
Ground
20
2
VDD
1)
S
Main power supply
1
3
RESET
2
4
PB0/AIN0/SS
I/O CT
I/O
X
CT
X
X
Top priority non maskable interrupt (active low)
X
X
X
Port B0
ei3
3
5
4
6
5
7
6
8
7
9
PB5/AIN5
ADC Analog Input 0 or SPI Slave Select
(active low)
Caution: No negative current injection
allowed on this pin. For details, refer to
section 13.2.2 on page 132
ADC Analog Input 1 or SPI Serial Clock
Caution: No negative current injection
allowed on this pin. For details, refer to
section 13.2.2 on page 132
ADC Analog Input 2 or SPI Master In/
Slave Out Data
ADC Analog Input 3 or SPI Master Out
/ Slave In Data
ADC Analog Input 4 or External clock
input
CT
X
X
X
X
Port B1
I/O
CT
X
X
X
X
Port B2
I/O
CT
X
X
X
X
Port B3
I/O
CT
X
X
X
X
Port B4
I/O
CT
X
X
X
X
Port B5
ADC Analog Input 5
CT
X
X
X
X
Port B6
ADC Analog Input 6 or LINSCI Input
X
X
Port A7
LINSCI Output
PB1/AIN1/SCK I/O
PB2/AIN2/
MISO
PB3/AIN3/
MOSI
PB4/AIN4/
CLKIN**
Alternate Function
PP
ana
int
wpu
float
Input
OD
VSS 1)
Output
1
Input
19
Pin Name
Type
SO20/DIP20
Main
Output Function
(after
reset)
QFN20
Level
8
10 PB6/AIN6/RDI
I/O
9
11 PA7/TDO
I/O CT HS
ei2
X
ei2
X
X
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1
ST7LITE3xF2
Port / Control
Alternate Function
PP
Main
Output Function
(after
reset)
OD
ana
int
wpu
Input
float
Output
Input
Pin Name
Type
SO20/DIP20
QFN20
Level
Main Clock Output or In Circuit Communication Clock or External BREAK
PA6 /MCO/
10 12 ICCCLK/
BREAK
I/O
CT
X
X
X
Port A6
ei1
Caution: During normal operation this
pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to
avoid entering ICC mode unexpectedly
during a reset. In the application, even
if the pin is configured as output, any reset will put it back in input pull-up.
Auto-Reload Timer PWM3 or In Circuit
Communication Data
PA5 /ATPWM3/
I/O CT HS
ICCDATA
X
X
X
Port A5
12 14 PA4/ATPWM2
I/O CT HS
X
X
X
Port A4
Auto-Reload Timer PWM2
13 15 PA3/ATPWM1
I/O CT HS
X
X
X
Port A3
Auto-Reload Timer PWM1
14 16 PA2/ATPWM0
I/O CT HS
X
X
X
Port A2
Auto-Reload Timer PWM0
15 17 PA1/ATIC
I/O CT HS
X
X
X
Port A1
Auto-Reload Timer Input Capture
16 18 PA0/LTIC
I/O CT HS
X
X
X
Port A0
Lite Timer Input Capture
17 19 OSC2
O
Resonator oscillator inverter output
18 20 OSC1/CLKIN
I
Resonator oscillator inverter input or External
clock input
11 13
ei0
X
Notes:
1. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA
pins to ground.
2. For input with interrupt possibility “eix” defines the associated external interrupt vector which can be assigned to one of the I/O pins using the EISR register. Each interrupt can be either weak pull-up or floating
defined through option register OR.
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ST7LITE3xF2
3 REGISTER & MEMORY MAP
As shown in Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 128
bytes of register locations, 384 bytes of RAM, 256
bytes of data EEPROM and 8 Kbytes of user program memory. The RAM space includes up to 128
bytes for the stack from 180h to 1FFh.
The highest address bytes contain the user reset
and interrupt vectors.
The Flash memory contains two sectors (see Figure 4) mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors
are located in Sector 0 (F000h-FFFFh).
The size of Flash Sector 0 and other device options are configurable by Option byte.
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the
device.
Figure 4. Memory Map
0080h
Short Addressing
RAM (zero page)
0000h
007Fh
0080h
HW Registers
(see Table 3)
00FFh
0100h
16-bit Addressing
RAM
RAM
(384 Bytes)
017Fh
0180h
Reserved
01FFh
01FFh
0200h
128 Bytes Stack
0FFFh
1000h
10FFh
1100h
DEE0h
Data EEPROM
(256 Bytes)
DEE1h
RCCRH0
RCCRL0
DEE2h
RCCRH1
DEE3h
Reserved
DFFFh
E000h
E000h
Flash Memory
(8K)
FFDFh
FFE0h
8K FLASH
PROGRAM MEMORY
FBFFh
FC00h
FFFFh
DEE4h
RCCRL1
see section 7.1 on page 23
and Note 1)
7 Kbytes
SECTOR 1
1 Kbyte
SECTOR 0
Interrupt & Reset Vectors
(see Table 6)
FFFFh
1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes
containing also the RC calibration values which are read-accessible only in user mode. If all the EEPROM
data or Flash space (including the RC calibration values locations) has been erased (after the read out
protection removal), then the RC calibration values can still be obtained through these addresses.
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ST7LITE3xF2
Table 3. Hardware Register Map
Address
0000h
0001h
0002h
0003h
0004h
0005h
Block
Register
Label
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
1
Remarks
Port A
Port A Data Register
Port A Data Direction Register
Port A Option Register
FFh1)
00h
40h
R/W
R/W
R/W
Port B
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
FFh 1)
00h
00h
R/W
R/W
R/W2)
Reserved area (2 bytes)
LITE
TIMER 2
AUTORELOAD
TIMER 3
LTCSR2
LTARR
LTCNTR
LTCSR1
LTICR
Lite Timer Control/Status Register 2
Lite Timer Auto-reload Register
Lite Timer Counter Register
Lite Timer Control/Status Register 1
Lite Timer Input Capture Register
0Fh
00h
00h
0x00 00x0b
xxh
R/W
R/W
Read Only
R/W
Read Only
ATCSR
CNTR1H
CNTR1L
ATR1H
ATR1L
PWMCR
PWM0CSR
PWM1CSR
PWM2CSR
PWM3CSR
DCR0H
DCR0L
DCR1H
DCR1L
DCR2H
DCR2L
DCR3H
DCR3L
ATICRH
ATICRL
ATCSR2
BREAKCR
ATR2H
ATR2L
DTGR
Timer Control/Status Register
Counter Register 1 High
Counter Register 1 Low
Auto-Reload Register 1 High
Auto-Reload Register 1 Low
PWM Output Control Register
PWM 0 Control/Status Register
PWM 1 Control/Status Register
PWM 2 Control/Status Register
PWM 3 Control/Status Register
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
PWM 1 Duty Cycle Register High
PWM 1 Duty Cycle Register Low
PWM 2 Duty Cycle Register High
PWM 2 Duty Cycle Register Low
PWM 3 Duty Cycle Register High
PWM 3 Duty Cycle Register Low
Input Capture Register High
Input Capture Register Low
Timer Control/Status Register 2
Break Control Register
Auto-Reload Register 2 High
Auto-Reload Register 2 Low
Dead Time Generator Register
0x00 0000b
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
03h
00h
00h
00h
00h
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
0026h to
002Dh
Reserved area (8 bytes)
002Eh
WDG
0002Fh
FLASH
00030h
EEPROM
10/173
Reset Status
PADR
PADDR
PAOR
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
Register Name
WDGCR
Watchdog Control Register
7Fh
R/W
FCSR
Flash Control/Status Register
00h
R/W
EECSR
Data EEPROM Control/Status Register
00h
R/W
ST7LITE3xF2
Register
Label
Address
Block
0031h
0032h
0033h
SPI
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
xxh
0xh
00h
R/W
R/W
R/W
0034h
0035h
0036h
ADC
ADCCSR
ADCDRH
ADCDRL
A/D Control Status Register
A/D Data Register High
A/D control and Data Register Low
00h
xxh
x0h
R/W
Read Only
R/W
0037h
ITC
EICR
External Interrupt Control Register
00h
R/W
0038h
MCC
MCCSR
Main Clock Control/Status Register
00h
R/W
0039h
003Ah
Clock and
Reset
RCCR
SICSR
RC oscillator Control Register
System Integrity Control/Status Register
FFh
0110 0xx0b
R/W
R/W
00h
R/W
003Bh
003Ch
ITC
EISR
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h to
007Fh
Remarks
External Interrupt Selection Register
Reserved area (3 bytes)
LINSCI
(LIN Master/Slave)
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCICR3
SCIERPR
SCIETPR
0048h
0049h
004Ah
Reset Status
Reserved area (1 byte)
003Dh to
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
Register Name
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Control Register 3
SCI Extended Receive Prescaler Register
SCI Extended Transmit Prescaler Register
C0h
xxh
00xx xxxxb
xxh
00h
00h
00h
00h
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved area (1 byte)
AWU
AWUPR
AWUCSR
AWU Prescaler Register
AWU Control/Status Register
FFh
00h
R/W
R/W
DM3)
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DM Control Register
DM Status Register
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
Reserved area (47 bytes)
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the DM registers, see the ST7 ICC Reference Manual.
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ST7LITE3xF2
4 FLASH PROGRAM MEMORY
4.1 Introduction
The ST7 single voltage extended Flash (XFlash) is
a non-volatile memory that can be electrically
erased and programmed either on a byte-by-byte
basis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board
(plugged in a programming tool) or on-board using
In-Circuit Programming or In-Application Programming.
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 Main Features
■
■
■
■
■
ICP (In-Circuit Programming)
IAP (In-Application Programming)
ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
Sector 0 size configurable by option byte
Read-out and write protection
4.3 PROGRAMMING MODES
The ST7 can be programmed in three different
ways:
– Insertion in a programming tool. In this mode,
FLASH sectors 0 and 1, option byte row and
data EEPROM (if present) can be programmed or erased.
– In-Circuit Programming. In this mode, FLASH
sectors 0 and 1, option byte row and data
EEPROM (if present) can be programmed or
erased without removing the device from the
application board.
– In-Application Programming. In this mode,
sector 1 and data EEPROM (if present) can
be programmed or erased without removing
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the device from the application board and
while the application is running.
4.3.1 In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable.
ICP is performed in three steps:
Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal
sequence on the ICCCLK/DATA pins while the
RESET pin is pulled low. When the ST7 enters
ICC mode, it fetches a specific RESET vector
which points to the ST7 System Memory containing the ICC protocol routine. This routine enables
the ST7 to receive bytes from the ICC interface.
– Download ICP Driver code in RAM from the
ICCDATA pin
– Execute ICP Driver code in RAM to program
the FLASH memory
Depending on the ICP Driver code downloaded in
RAM, FLASH memory programming can be fully
customized (number of bytes to program, program
locations, or selection of the serial communication
interface for downloading).
4.3.2 In Application Programming (IAP)
This mode uses an IAP Driver program previously
programmed in Sector 0 by the user (in ICP
mode).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (user-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored etc.)
IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during
the programming operation.
ST7LITE3xF2
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC INTERFACE
ICP needs a minimum of 4 and up to 6 pins to be
connected to the programming tool. These pins
are:
– RESET: device reset
– VSS: device power supply ground
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
– CLKIN/PB4: main clock input for external
source
– VDD: application board power supply (optional, see Note 3)
Figure 5. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
OPTIONAL
(See Note 4)
9
7
5
3
1
10
8
6
4
2
APPLICATION BOARD
APPLICATION
RESET SOURCE
See Note 2
APPLICATION
POWER SUPPLY
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to be implemented if another device
forces the signal. Refer to the Programming Tool
documentation for recommended resistor values.
2. During the ICP session, the programming tool
must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
ICCDATA
ST7
ICCCLK
RESET
CLKIN/PB4
(See Note 5)
VDD
See Note 1 and caution APPLICATION
I/O
See Note 1
must be connected when using most ST Programming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 must be connected to the PB4 pin of the
ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with
multi-oscillator capability must have OSC2
grounded in this case.
5. With any programming tool, while the ICP option
is disabled, the external clock must be provided on
PB4.
6. In 38-pulse ICC mode, the internal RC oscillator
is forced as a clock source, regardless of the selection in the option byte. For ST7LITE30 devices
which do not support the internal RC oscillator, the
“option byte disabled” mode must be used (35pulse ICC mode entry, clock provided by the tool).
Caution: During normal operation ICCCLK pin
must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This avoids entering ICC mode
unexpectedly during a reset. In the application,
even if the pin is configured as output, any reset
puts it back in input pull-up.
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ST7LITE3xF2
FLASH PROGRAM MEMORY (Cont’d)
4.5 Memory Protection
4.6 Related Documentation
There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually.
4.5.1 Read out Protection
Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory.
Even if no protection can be considered as totally
unbreakable, the feature provides a very high level
of protection for a general purpose microcontroller.
Both program and data E2 memory are protected.
In flash devices, this protection is removed by reprogramming the option. In this case, both program and data E2 memory are automatically
erased and the device can be reprogrammed.
– Read-out protection selection is enabled and removed through the FMP_R bit in the option byte.
4.5.2 Flash Write/Erase Protection
Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to E2 data. Its purpose is to
provide advanced security to applications and prevent any change being made to the memory content.
Warning: Once set, Write/erase protection can
never be removed. A write-protected flash device
is no longer reprogrammable.
Write/erase protection is enabled through the
FMP_W bit in the option byte.
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.
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4.7 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
7
0
0
0
0
0
0
OPT
LAT
PGM
Note: This register is reserved for programming
using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing operations.
When an EPB or another programming tool is
used (in socket or ICP mode), the RASS keys are
sent automatically.
ST7LITE3xF2
5 DATA EEPROM
5.1 INTRODUCTION
5.2 MAIN FEATURES
The Electrically Erasable Programmable Read
Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a
basic access protocol described in this chapter.
■
■
■
■
■
■
Up to 32 Bytes programmed in the same cycle
EEPROM mono-voltage (charge pump)
Chained erase and programming cycles
Internal control of the global programming cycle
duration
WAIT mode management
Readout protection
Figure 6. EEPROM Block Diagram
HIGH VOLTAGE
PUMP
EECSR
0
0
0
ADDRESS
DECODER
0
0
4
0
E2LAT E2PGM
EEPROM
ROW
MEMORY MATRIX
DECODER
(1 ROW = 32 x 8 BITS)
128
4
128
DATA
32 x 8 BITS
MULTIPLEXER
DATA LATCHES
4
ADDRESS BUS
DATA BUS
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ST7LITE3xF2
DATA EEPROM (Cont’d)
5.3 MEMORY ACCESS
The Data EEPROM memory read/write access
modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these different memory
access modes.
Read Operation (E2LAT=0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is
cleared.
On this device, Data EEPROM can also be used to
execute machine code. Take care not to write to
the Data EEPROM while executing from it. This
would result in an unexpected code being executed.
Write Operation (E2LAT=1)
To access the write mode, the E2LAT bit has to be
set by software (the E2PGM bit remains cleared).
When a write access to the EEPROM area occurs,
the value is latched inside the 32 data latches according to its address.
When PGM bit is set by the software, all the previous bytes written in the data latches (up to 32) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the five Least
Significant Bits of the address can change.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously.
Note: Care should be taken during the programming cycle. Writing to the same memory location
will over-program the memory (logical AND between the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of the
E2LAT bit.
It is not possible to read the latched data.
This note is ilustrated by the Figure 9.
Figure 7. Data EEPROM Programming Flowchart
READ MODE
E2LAT=0
E2PGM=0
READ BYTES
IN EEPROM AREA
WRITE MODE
E2LAT=1
E2PGM=0
WRITE UP TO 32 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
START PROGRAMMING CYCLE
E2LAT=1
E2PGM=1 (set by software)
0
CLEARED BY HARDWARE
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E2LAT
1
ST7LITE3xF2
DATA EEPROM (Cont’d)
Figure 8. Data E2PROM Write Operation
⇓ Row / Byte ⇒
ROW
DEFINITION
0
1
2
3
...
30 31
Physical Address
0
00h...1Fh
1
20h...3Fh
...
Nx20h...Nx20h+1Fh
N
Read operation impossible
Byte 1
Byte 2
Byte 32
Read operation possible
Programming cycle
PHASE 1
PHASE 2
Writing data latches
Waiting E2PGM and E2LAT to fall
E2LAT bit
Set by USER application
Cleared by hardware
E2PGM bit
Note: If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not
guaranteed.
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ST7LITE3xF2
DATA EEPROM (Cont’d)
5.4 POWER SAVING MODES
5.5 ACCESS ERROR HANDLING
Wait mode
The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-HALT
mode.The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
If a read access occurs while E2LAT=1, then the
data bus will not be driven.
If a write access occurs while E2LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by RESET
action), the integrity of the data in memory is not
guaranteed.
5.6 Data EEPROM Read-out Protection
Active-Halt mode
Refer to Wait mode.
Halt mode
The DATA EEPROM immediately enters HALT
mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
The read-out protection is enabled through an option bit (see section 15.1 on page 161).
When this option is selected, the programs and
data stored in the EEPROM memory are protected
against read-out (including a re-write protection).
In Flash devices, when this protection is removed
by reprogramming the Option Byte, the entire Program memory and EEPROM is first automatically
erased.
Note: Both Program Memory and data EEPROM
are protected using the same option bit.
Figure 9. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE
WRITE OF
DATA LATCHES
WRITE CYCLE
tPROG
LAT
PGM
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ST7LITE3xF2
DATA EEPROM (Cont’d)
5.7 REGISTER DESCRIPTION
EEPROM CONTROL/STATUS REGISTER (EECSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
E2LAT E2PGM
Bits 7:2 = Reserved, forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can
only be cleared by software if the E2PGM bit is
cleared.
0: Read mode
1: Write mode
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: if the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed
Table 4. DATA EEPROM Register Map and Reset Values
Address
(Hex.)
0030h
Register
Label
7
6
5
4
3
2
1
0
0
0
0
0
0
0
E2LAT
0
E2PGM
0
EECSR
Reset Value
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ST7LITE3xF2
6 CENTRAL PROCESSING UNIT
6.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
6.2 MAIN FEATURES
■
■
■
■
■
■
■
■
63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes
Two 8-bit index registers
16-bit stack pointer
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
6.3 CPU REGISTERS
The six CPU registers shown in Figure 10 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 10. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
15
PCH
8 7
PCL
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1 1 1 H I
0
N Z C
CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8 7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
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ST7LITE3xF2
CPU REGISTERS (cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
7
1
1
1
H
I
N
Z
0
logical or data manipulation. It is a copy of the 7th
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
C
This bit is accessed by the JRMI and JRPL instructions.
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 3 = I Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptible
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the current interrupt routine.
Bit 2 = N Negative
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,
Bit 1 = Z Zero
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
CPU REGISTERS (Cont’d)
STACK POINTER (SP)
Read/Write
Reset Value: 01FFh
15
0
8
0
0
0
0
0
0
7
1
1
0
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 11).
Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an
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MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 11.
– When an interrupt is received, the SP is decremented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 11. Stack Manipulation Example
CALL
Subroutine
PUSH Y
Interrupt
Event
POP Y
RET
or RSP
IRET
@ 0180h
SP
SP
CC
A
X
X
X
PCH
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
Stack Lower Address = 0180h
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SP
Y
CC
A
CC
A
SP
SP
ST7LITE3xF2
7 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and reducing the number of external components.
Main features
■
Clock Management
– 1 MHz internal RC oscillator (enabled by option byte, available on ST7LITE35 and
ST7LITE39 devices only)
– 1 to 16 MHz or 32kHz External crystal/ceramic
resonator (selected by option byte)
– External Clock Input (enabled by option byte)
– PLL for multiplying the frequency by 8 or 4
(enabled by option byte)
■
Reset Sequence Manager (RSM)
■
System Integrity Management (SI)
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply (enabled by option byte)
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT
The device contains an internal RC oscillator with
an accuracy of 1% for a given device, temperature
and voltage range (4.5V-5.5V). It must be calibrated to obtain the frequency required in the application. This is done by software writing a 8-bit calibration value in the RCCR (RC Control Register)
and in the bits [6:5] in the SICSR (SI Control Status Register).
Whenever the microcontroller is reset, the RCCR
returns to its default value (FFh), i.e. each time the
device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are
stored in EEPROM for 3V and 5V VDD supply voltages at 25°C, as shown in the following table.
RCCR
RCCRH0
RCCRL0
RCCRH1
RCCRL1
Conditions
VDD=5V
TA=25°C
fRC=1MHz
VDD=3.3V
TA=25°C
fRC=1MHz
ST7LITE3
Addresses
DEE0h 1) (CR[9:2] bits)
DEE1h 1) (CR[1:0] bits)
DEE2h 1) (CR[9:2] bits)
DEE3h 1) (CR[1:0] bits)
1. DEE0h, DEE1h, DEE2h and DEE3h addresses
are located in a reserved area of non-volatile
memory. They are read-only bytes for the applica-
tion code. This area cannot be erased or programmed by any ICC operation.
For compatibility reasons with the SICSR register,
CR[1:0] bits are stored in the 5th and 6th position
of DEE1 and DEE3 addresses.
Note:
– In 38-pulse ICC mode, the internal RC oscillator
is forced as a clock source, regardless of the selection in the option byte. For ST7LITE30 devices which do not support the internal RC
oscillator, the “option byte disabled” mode must
be used (35-pulse ICC mode entry, clock provided by the tool).
– See “ELECTRICAL CHARACTERISTICS” on
page 131. for more information on the frequency
and accuracy of the RC oscillator.
– To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and
VSS pins as close as possible to the ST7 device
– These bytes are systematically programmed by
ST, including on FASTROM devices. Consequently, customers intending to use FASTROM
service must not use these bytes.
– RCCR0 and RCCR1 calibration values will not
be erased if the read-out protection bit is reset after it has been set . See “Read out Protection” on
page 14.
Caution: If the voltage or temperature conditions
change in the application, the frequency may need
to be recalibrated.
Refer to application note AN1324 for information
on how to calibrate the RC frequency using an external reference signal.
7.2 PHASE LOCKED LOOP
The PLL can be used to multiply a 1MHz frequency from the RC oscillator or the external clock by 4
or 8 to obtain fOSC of 4 or 8 MHz. The PLL is enabled and the multiplication factor of 4 or 8 is selected by 2 option bits.
– The x4 PLL is intended for operation with VDD in
the 2.7V to 3.3V range
– The x8 PLL is intended for operation with VDD in
the 3.3V to 5.5V range
Refer to Section 15.1 for the option byte description.
If the PLL is disabled and the RC oscillator is enabled, then fOSC = 1MHz.
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If both the RC oscillator and the PLL are disabled,
fOSC is driven by the external clock.
Figure 12. PLL Output Frequency Timing
Diagram
LOCKED bit set
7.3 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
7
4/8 x
input
freq.
0
0
0
0
0
0
0
MCO
SMS
tSTAB
Output freq.
Bits 7:2 = Reserved, must be kept cleared.
tLOCK
tSTARTUP
t
When the PLL is started, after reset or wakeup
from Halt mode or AWUFH mode, it outputs the
clock after a delay of tSTARTUP.
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACCPLL) is reached after
a stabilization time of tSTAB (see Figure 12 and
13.3.4Internal RC Oscillator and PLL)
Refer to section 7.6.4 on page 34 for a description
of the LOCKED bit in the SICSR register.
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by
hardware after a reset. This bit allows to enable
the MCO output clock.
0: MCO clock disabled, I/O port free for general
purpose I/O.
1: MCO clock enabled.
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the input
clock fOSC or fOSC/32.
0: Normal mode (fCPU = fOSC
1: Slow mode (fCPU = fOSC/32)
RC CONTROL REGISTER (RCCR)
Read / Write
Reset Value: 1111 1111 (FFh)
7
CR9
0
CR8
CR7
CR6
CR5
CR4
CR3
CR2
Bits 7:0 = CR[9:2] RC Oscillator Frequency Adjustment Bits
These bits must be written immediately after reset
to adjust the RC oscillator frequency and to obtain
an accuracy of 1%. The application can store the
correct value for each voltage range in EEPROM
and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
These bits are used with the CR[1:0] bits in the
SICSR register. Refer to section 7.6.4 on page 34
Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h.
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Figure 13. Clock Management Block Diagram
CR9
CR8
CR7
CR6
CR5
CR1
CR4
CR3
CR2
RCCR
CR0
SICSR
CLKIN/2 (Ext Clock)
Tunable
1% RC Oscillator
1MHz
8MHz
PLL 1MHz -> 8MHz
PLL 1MHz -> 4MHz 4MHz
OSCRANGE[2:0]
Option bits
CLKIN
CLKIN/
OSC1
OSC2
CLKIN
fCLKIN
CLKIN
OSC Option bit
OSC,PLLOFF,
OSCRANGE[2:0]
Option bits
Crystal OSC /2
/2
DIVIDER
8-BIT
LITE TIMER 2 COUNTER
fOSC
/32 DIVIDER
fOSC
PLLx4x8
/2
DIVIDER
OSC
1-16 MHZ
or 32kHz
RC OSC
PLL
Clock
fOSC/32
fOSC
1
0
fLTIMER
(1ms timebase @ 8 MHz fOSC)
fCPU
TO CPU AND
PERIPHERALS
MCO SMS MCCSR
fCPU
MCO
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7.4 MULTI-OSCILLATOR (MO)
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to section 15.1 on page 161 for more details on the
frequency ranges). In this mode of the multi-oscillator, the resonator and the load capacitors have
to be placed as close as possible to the oscillator
pins in order to minimize output distortion and
start-up stabilization time. The loading capacitance values must be adjusted according to the
selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Internal RC Oscillator
In this mode, the tunable 1%RC oscillator is used
as main clock source. The two oscillator pins have
to be tied to ground.
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Table 5. ST7 Clock Sources
External Clock
Hardware Configuration
Crystal/Ceramic Resonators
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
Note: when the Multi-Oscillator is not used, PB4 is
selected by default as external clock.
The calibration is done through the RCCR[7:0] and
SICSR[6:5] registers.
Internal RC Oscillator
The main clock of the ST7 can be generated by
four different source types coming from the multioscillator block (1 to 16MHz or 32kHz):
■ an external source
■ 5 crystal or ceramic resonator oscillators
■ an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 5. Refer to the
electrical characteristics section for more details.
ST7
OSC1
OSC2
EXTERNAL
SOURCE
ST7
OSC1
CL1
OSC2
LOAD
CAPACITORS
ST7
OSC1
OSC2
CL2
ST7LITE3xF2
7.5 RESET SEQUENCE MANAGER (RSM)
7.5.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 15:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Refer to section 12.2.1 on page 128 for further details.
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (see table
below)
■ RESET vector fetch
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recommended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte:
The RESET vector fetch phase duration is 2 clock
cycles.
Clock Source
Internal RC Oscillator
External clock (connected to CLKIN pin)
External Crystal/Ceramic Oscillator
(connected to OSC1/OSC2 pins)
CPU clock
cycle delay
256
256
4096
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of tSTARTUP (see
Figure 12).
Figure 14. RESET Sequence Phases
RESET
Active Phase
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
7.5.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized (see Figure 16). This detection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
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Figure 15. Reset Block Diagram
VDD
RON
RESET
INTERNAL
RESET
Filter
PULSE
GENERATOR
WATCHDOG RESET
ILLEGAL OPCODE RESET1)
LVD RESET
Note 1: See “Illegal Opcode Reset” on page 128. for more details on illegal opcode reset conditions.
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RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteristics section.
7.5.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until VDD is over the minimum
level specified for the selected fOSC frequency.
A proper reset signal for a slow rising VDD supply
can generally be provided by an external RC network connected to the RESET pin.
7.5.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD Reset value
PWM Mode -> Reset value
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
11.2.3.2 Output Compare Mode
To use this function, load a 12-bit value in the
Preload DCRxH and DCRxL registers.
When the 12-bit upcounter (CNTR1) reaches the
value stored in the Active DCRxH and DCRxL registers, the CMPFx bit in the PWMxCSR register is
set and an interrupt request is generated if the
CMPIE bit is set.
The output compare function is always performed
on CNTR1 in both Single Timer mode and Dual
Timer mode, and never on CNTR2. The difference
is that in Single Timer mode the counter 1 can be
compared with any of the four DCR registers, and
in Dual Timer mode, counter 1 is compared with
DCR0 or DCR1.
Notes:
1. The output compare function is only available
for DCRx values other than 0 (reset value).
2. Duty cycle registers are buffered internally. The
CPU writes in Preload Duty Cycle Registers and
these values are transferred in Active Duty Cycle
Registers after an overflow event if the corresponding transfer bit (TRAN1 bit) is set. Output
compare is done by comparing these active DCRx
values with the counter.
Figure 41. Block Diagram of Output Compare Mode (single timer)
DCRx
PRELOAD DUTY CYCLE REGx
(ATCSR2) TRAN1
(ATCSR) OVF
ACTIVE DUTY CYCLE REGx
OUTPUT COMPARE CIRCUIT
CNTR1
COUNTER 1
CMP
INTERRUPT REQUEST
CMPFx (PWMxCSR)
CMPIE (ATCSR)
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
11.2.3.3 Input Capture Mode
The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter CNTR1 after a rising or falling edge is detected on the ATIC
pin. When an input capture occurs, the ICF bit is
set and the ATICR register contains the value of
the free running upcounter. An IC interrupt is generated if the ICIE bit is set. The ICF bit is reset by
reading the ATICRH/ATICRL register when the
ICF bit is set. The ATICR is a read only register
and always contains the free running upcounter
value which corresponds to the most recent input
capture. Any further input capture is inhibited while
the ICF bit is set.
Figure 42. Block Diagram of Input Capture Mode
ATIC
12-BIT INPUT CAPTURE REGISTER
ATICR
IC INTERRUPT
REQUEST
ATCSR
ICF
ICIE
CK1
fLTIMER
(1 ms
timebase
@ 8MHz)
CK0
12-BIT UPCOUNTER1
fCPU
CNTR1
OFF
ATR1
12-BIT AUTORELOAD REGISTER
Figure 43. Input Capture timing diagram
fCOUNTER
COUNTER1
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
ATIC PIN
INTERRUPT
ATICR READ
INTERRUPT
ICF FLAG
xxh
04h
09h
t
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
Long input capture
Pulses that last between 8µs and 2s can be measured with an accuracy of 4µs if fOSC = 8MHz in the
following conditions:
– The 12-bit AT3 Timer is clocked by the Lite Timer
(RTC pulse: CK[1:0] = 01 in the ATCSR register)
– The ICS bit in the ATCSR2 register is set so that
the LTIC pin is used to trigger the AT3 Timer capture.
■
– The signal to be captured is connected to LTIC
pin
– Input Capture registers LTICR, ATICRH and
ATICRL are read
This configuration allows to cascade the Lite Timer
and the 12-bit AT3 Timer to get a 20-bit input capture value. Refer to Figure 44.
Figure 44. Long Range Input Capture Block Diagram
LTICR
8-bit Input Capture Register
fOSC/32
8 LSB bits
8-bit Timebase Counter1
LITE TIMER
12-Bit ARTIMER
ATR1
20
cascaded
bits
12-bit AutoReload Register
fLTIMER
ICS
12-bit Upcounter1
OFF
LTIC
1
ATIC
fcpu
CNTR1
0
ATICR
12-bit Input Capture Register
Notes:
1. Since the input capture flags (ICF) for both timers (AT3 Timer and LT Timer) are set when signal
transition occurs, software must mask one interrupt by clearing the corresponding ICIE bit before
setting the ICS bit.
2. If the ICS bit changes (from 0 to 1 or from 1 to
0), a spurious transition might occur on the input
capture signal because of different values on LTIC
and ATIC. To avoid this situation, it is recommended to do as follows:
– First, reset both ICIE bits.
– Then set the ICS bit.
– Reset both ICF bits.
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12 MSB bits
– And then set the ICIE bit of desired interrupt.
3. How to compute a pulse length with long input
capture feature.
As both timers are used, computing a pulse length
is not straight-forward. The procedure is as follows:
– At the first input capture on the rising edge of the
pulse, we assume that values in the registers are
as follows:
LTICR = LT1
ATICRH = ATH1
ATICRL = ATL1
Hence ATICR1 [11:0] = ATH1 & ATL1
Refer to Figure 45 on page 65.
ST7LITE3xF2
DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
– At the second input capture on the falling edge of
the pulse, we assume that the values in the registers are as follows:
LTICR = LT2
ATICRH = ATH2
ATICRL = ATL2
Hence ATICR2 [11:0] = ATH2 & ATL2
Now pulse width P between first capture and second capture will be:
P = decimal (F9 – LT1 + LT2 + 1) * 0.004ms + decimal (ATICR2 - ATICR1 – 1) * 1ms
Figure 45. Long Range Input Capture Timing Diagram
fOSC/32
TB Counter1
CNTR1
F9h
00h
___
LT1
F9h
00h
___
___
___
ATH1 & ATL1
___
LT2
___
___
ATH2 & ATL2
LTIC
LTICR
00h
LT1
LT2
ATICRH
0h
ATH1
ATH2
ATICRL
00h
ATL1
ATL2
ATICR = ATICRH[3:0] & ATICRL[7:0]
11.2.4 Low Power Modes
Mode
SLOW
WAIT
ACTIVEHALT
HALT
Description
The input frequency is divided by 32
No effect on AT timer
AT timer halted except if CK0=1,
CK1=0 and OVFIE=1
AT timer halted.
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
11.2.5 Interrupts
Interrupt
Event 1)
Enable Exit
Event
Control from
Flag
Bit
WAIT
Overflow
OVF1 OVIE1
Event
AT3 IC
ICF
ICIE
Event
CMP Event CMPFx CMPIE
Exit
Exit
from
from
ACTIVE
HALT
-HALT
Yes
No
Yes2)
Yes
No
No
Yes
No
No
Note 1: The CMP and AT3 IC events are connected to the same interrupt vector.
The OVF event is mapped on a separate vector
(see Interrupts chapter).
They generate an interrupt if the enable bit is set in
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the ATCSR register and the interrupt mask in the
CC register is reset (RIM instruction).
Note 2: Only if CK0=1 and CK1=0 (fCOUNTER =
fLTIMER)
ST7LITE3xF2
DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
11.2.6 Register Description
TIMER CONTROL STATUS REGISTER
(ATCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
7
6
0
ICF
0
ICIE
CK1
CK0
OVF1 OVFIE1 CMPIE
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset. It can be used to mask the
interrupt generated when any of the CMPFx bit is
set.
0: Output compare interrupt disabled.
1: Output Compare interrupt enabled.
Bit 7 = Reserved.
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the ATICR register (a read access to
ATICRH or ATICRL will clear this flag). Writing to
this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
Bit 5 = ICIE IC Interrupt Enable.
This bit is set and cleared by software.
0: Input capture interrupt disabled
1: Input capture interrupt enabled
COUNTER REGISTER 1 HIGH (CNTR1H)
Read only
Reset Value: 0000 0000 (000h)
15
0
8
0
0
0
CNTR1_ CNTR1_ CNTR1_ CNTR1_
11
10
9
8
COUNTER REGISTER 1 LOW (CNTR1L)
Read only
Reset Value: 0000 0000 (000h)
7
Bits 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter.
Counter Clock Selection
CK1
CK0
OFF
0
0
OFF
1
1
fLTIMER (1 ms timebase @ 8 MHz)
0
1
fCPU
1
0
Bit 2 = OVF1 Overflow Flag.
This bit is set by hardware and cleared by software
by reading the TCSR register. It indicates the transition of the counter1 CNTR1 from FFh to ATR1
value.
0: No counter overflow occurred
1: Counter overflow occurred
0
CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_
7
6
5
4
3
2
1
0
Bits 15:12 = Reserved.
Bits 11:0 = CNTR1[11:0] Counter Value.
This 12-bit register is read by software and cleared
by hardware after a reset. The counter CNTR1 is
incremented continuously as soon as a counter
clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations. The CNTR1H register can
be incremented between the two reads, and in order to be accurate when fTIMER=fCPU, the software
should take this into account when CNTR1L and
CNTR1H are read. If CNTR1L is close to its highest value, CNTR1H could be incremented before it
is read.
When a counter overflow occurs, the counter restarts from the value specified in the ATR1 register.
Bit 1 = OVFIE1 Overflow Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset.
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
AUTORELOAD REGISTER (ATR1H)
Read / Write
Reset Value: 0000 0000 (00h)
PWMx CONTROL STATUS REGISTER
(PWMxCSR)
Read / Write
Reset Value: 0000 0000 (00h)
15
0
8
0
0
0
ATR11 ATR10 ATR9
AUTORELOAD REGISTER (ATR1L)
Read / Write
Reset Value: 0000 0000 (00h)
0
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
Bits 11:0 = ATR1[11:0] Autoreload Register 1.
This is a 12-bit register which is written by software. The ATR1 register value is automatically
loaded into the upcounter CNTR1 when an overflow occurs. The register value is used to set the
PWM frequency.
PWM OUTPUT CONTROL REGISTER
(PWMCR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
OE3
0
OE2
0
OE1
0
OE0
Bits 7:0 = OE[3:0] PWMx output enable.
These bits are set and cleared by software and
cleared by hardware after a reset.
0: PWM mode disabled. PWMx Output Alternate
Function disabled (I/O pin free for general purpose I/O)
1: PWM mode enabled
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1
6
0
0
0
0
0
0
0
OPx
CMPFx
Bits 7:2= Reserved, must be kept cleared.
7
ATR7
7
ATR8
Bit 1 = OPx PWMx Output Polarity.
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the polarity
of the PWM signal.
0: The PWM signal is not inverted.
1: The PWM signal is inverted.
Bit 0 = CMPFx PWMx Compare Flag.
This bit is set by hardware and cleared by software
by reading the PWMxCSR register. It indicates
that the upcounter value matches the Active DCRx
register value.
0: Upcounter value does not match DCRx value.
1: Upcounter value matches DCRx value.
BREAK CONTROL REGISTER (BREAKCR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
BA
BPEN
PWM3
PWM2
PWM1
PWM0
Bits 7:6 = Reserved. Forced by hardware to 0.
Bit 5 = BA Break Active.
This bit is read/write by software, cleared by hardware after reset and set by hardware when the
BREAK pin is low. It activates/deactivates the
Break function.
0: Break not active
1: Break active
ST7LITE3xF2
DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
Bit 4 = BPEN Break Pin Enable.
This bit is read/write by software and cleared by
hardware after Reset.
0: Break pin disabled
1: Break pin enabled
Bit 3:0 = PWM[3:0] Break Pattern.
These bits are read/write by software and cleared
by hardware after a reset. They are used to force
the four PWMx output signals into a stable state
when the Break function is active.
PWMx DUTY CYCLE REGISTER HIGH (DCRxH)
Read / Write
Reset Value: 0000 0000 (00h)
15
INPUT CAPTURE REGISTER HIGH (ATICRH)
Read only
Reset Value: 0000 0000 (00h)
15
0
8
0
0
0
ICR11 ICR10
ICR9
ICR8
INPUT CAPTURE REGISTER LOW (ATICRL)
Read only
Reset Value: 0000 0000 (00h)
7
ICR7
0
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
ICR0
8
Bits 15:12 = Reserved.
0
0
0
0
DCR11 DCR10 DCR9 DCR8
PWMx DUTY CYCLE REGISTER LOW (DCRxL)
Read / Write
Reset Value: 0000 0000 (00h)
7
DCR7 DCR6 DCR5 DCR4 DCR3
Bits 11:0 = ICR[11:0] Input Capture Data.
This is a 12-bit register which is readable by software and cleared by hardware after a reset. The
ATICR register contains captured the value of the
12-bit CNTR1 register when a rising or falling edge
occurs on the ATIC or LTIC pin (depending on
ICS). Capture will only be performed when the ICF
flag is cleared.
0
DCR2
DCR1 DCR0
Bits 15:12 = Reserved.
Bits 11:0 = DCRx[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. It defines
the duty cycle of the corresponding PWM output
signal (see Figure 37).
In PWM mode (OEx=1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the
PWMx output signal (see Figure 37). In Output
Compare mode, they define the value to be compared with the 12-bit upcounter value.
TIMER CONTROL REGISTER2 (ATCSR2)
Read/Write
Reset Value: 0000 0011 (03h)
7
0
0
0
ICS
OVFIE2 OVF2
ENCNT
TRAN2 TRAN1
R2
Bits 7:6 = Reserved. Forced by hardware to 0.
Bit 5 = ICS Input Capture Shorted
This bit is read/write by software. It allows the ATtimer CNTR1 to use the LTIC pin for long input
capture.
0 : ATIC for CNTR1 input capture
1 : LTIC for CNTR1 input capture
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ST7LITE3xF2
DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
Bit 4 = OVFIE2 Overflow interrupt 2 enable
This bit is read/write by software and controls the
overflow interrupt of counter2.
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
Bit 3 = OVF2 Overflow Flag.
This bit is set by hardware and cleared by software
by reading the ATCSR2 register. It indicates the
transition of the counter2 from FFFh to ATR2 value.
0: No counter overflow occurred
1: Counter overflow occurred
AUTORELOAD REGISTER2 (ATR2H)
Read / Write
Reset Value: 0000 0000 (00h)
15
0
8
0
0
0
ATR11 ATR10 ATR9
AUTORELOAD REGISTER (ATR2L)
Read / Write
Reset Value: 0000 0000 (00h)
7
Bit 2 = ENCNTR2 Enable counter2
This bit is read/write be software and switches the
second counter CNTR2. If this bit is set, PWM2
and PWM3 will be generated using CNTR2.
0: CNTR2 stopped.
1: CNTR2 starts running.
Bit 1= TRAN2 Transfer enable2
This bit is read/write by software, cleared by hardware after each completed transfer and set by
hardware after reset. It controls the transfers on
CNTR2.
It allows the value of the Preload DCRx registers
to be transferred to the Active DCRx registers after
the next overflow event.
The OPx bits are transferred to the shadow OPx
bits in the same way.
(Only DCR2/DCR3 can be controlled with this bit)
Bit 0 = TRAN1 Transfer enable 1
This bit is read/write by software, cleared by hardware after each completed transfer and set by
hardware after reset. It controls the transfers on
CNTR1. It allows the value of the Preload DCRx
registers to be transferred to the Active DCRx registers after the next overflow event.
The OPx bits are transferred to the shadow OPx
bits in the same way.
70/173
1
ATR8
ATR7
0
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
Bits 11:0 = ATR2[11:0] Autoreload Register 2.
This is a 12-bit register which is written by software. The ATR2 register value is automatically
loaded into the upcounter CNTR2 when an overflow of CNTR2 occurs. The register value is used
to set the PWM2/PWM3 frequency when
ENCNTR2 is set.
DEAD TIME GENERATOR REGISTER (DTGR)
Read/Write
Reset Value: 0000 0000 (00h)
7
DTE
0
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Bits 7 = DTE Dead Time Enable
This bit is read/write by software. It enables a dead
time generation on PWM0/PWM1.
0: No Dead time insertion.
1: Dead time insertion enabled.
Bit 6:0 = DT[6:0] Dead Time Value
These bits are read/write by software. They define
the dead time inserted between PWM0/PWM1.
Dead time is calculated as follows:
Dead Time = DT[6:0] x Tcounter1
ST7LITE3xF2
DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
Table 16. Register Map and Reset Values
Address
Register
Label
7
6
5
4
3
2
1
0
0D
ATCSR
Reset Value
0
ICF
0
ICIE
0
CK1
0
CK0
0
OVF1
0
OVFIE1
0
CMPIE
0
0E
CNTR1H
Reset Value
0
0
0
0
0F
CNTR1L
CNTR1_7 CNTR1_6 CNTR1_5 CNTR1_4 CNTR1_3
Reset Value
0
0
0
0
0
10
ATR1H
Reset Value
0
0
0
0
ATR11
0
ATR10
0
ATR9
0
ATR8
0
11
ATR1L
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
12
PWMCR
Reset Value
0
OE3
0
0
OE2
0
0
OE1
0
0
OE0
0
13
PWM0CSR
Reset Value
0
0
0
0
0
0
OP0
0
CMPF0
0
14
PWM1CSR
Reset Value
0
0
0
0
0
0
OP1
0
CMPF1
0
15
PWM2CSR
Reset Value
0
0
0
0
0
0
OP2
0
CMPF2
0
16
PWM3CSR
Reset Value
0
0
0
0
0
0
OP3
0
CMPF3
0
17
DCR0H
Reset Value
0
0
0
0
DCR11
0
DCR10
0
DCR9
0
DCR8
0
18
DCR0L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
19
DCR1H
Reset Value
0
0
0
0
DCR11
0
DCR10
0
DCR9
0
DCR8
0
1A
DCR1L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
1B
DCR2H
Reset Value
0
0
0
0
DCR11
0
DCR10
0
DCR9
0
DCR8
0
1C
DCR2L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
1D
DCR3H
Reset Value
0
0
0
0
DCR11
0
DCR10
0
DCR9
0
DCR8
0
1E
DCR3L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
1F
ATICRH
Reset Value
0
0
0
0
ICR11
0
ICR10
0
ICR9
0
ICR8
0
20
ATICRL
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
(Hex.)
CNTR1_11 CNTR1_10 CNTR1_9 CNTR1_8
0
0
0
0
CNTR1_2 CNTR1_1 CNTR1_0
0
0
0
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ST7LITE3xF2
Address
Register
Label
7
6
21
ATCSR2
Reset Value
0
0
22
BREAKCR
Reset Value
0
23
ATR2H
Reset Value
24
25
(Hex.)
72/173
1
5
4
3
2
1
0
ICS
OVFIE2
OVF2
ENCNTR2
TRAN2
TRAN1
0
0
0
0
1
1
0
BA
0
BPEN
0
PWM3
0
PWM2
0
PWM1
0
PWM0
0
0
0
0
0
ATR11
0
ATR10
0
ATR9
0
ATR8
0
ATR2L
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
DTGR
Reset Value
DTE
DT6
DT5
DT4
DT3
DT2
DT1
DT0
0
0
0
0
0
0
0
0
ST7LITE3xF2
11.3 LITE TIMER 2 (LT2)
11.3.1 Introduction
The Lite Timer can be used for general-purpose
timing functions. It is based on two free-running 8bit upcounters and an 8-bit input capture register.
■
11.3.2 Main Features
■ Realtime Clock (RTC)
– One 8-bit upcounter 1 ms or 2 ms timebase
period (@ 8 MHz fOSC)
– One 8-bit upcounter with autoreload and programmable timebase period from 4µs to
1.024ms in 4µs increments (@ 8 MHz fOSC)
– 2 Maskable timebase interrupts
Input Capture
– 8-bit input capture register (LTICR)
– Maskable interrupt with wakeup from Halt
Mode capability
Figure 46. Lite Timer 2 Block Diagram
fOSC/32
LTTB2
LTCNTR
Interrupt request
LTCSR2
8-bit TIMEBASE
COUNTER 2
0
0
0
0
0
0
TB2IE TB2F
8
LTARR
fLTIMER
8-bit AUTORELOAD
REGISTER
/2
8-bit TIMEBASE
COUNTER 1
fLTIMER
8
To 12-bit AT TImer
1
0 Timebase
1 or 2 ms
(@ 8MHz
fOSC)
LTICR
LTIC
8-bit
INPUT CAPTURE
REGISTER
LTCSR1
ICIE
ICF
TB
TB1IE TB1F
LTTB1 INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
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ST7LITE3xF2
LITE TIMER (Cont’d)
11.3.3 Functional Description
11.3.3.1 Timebase Counter 1
The 8-bit value of Counter 1 cannot be read or
written by software. After an MCU reset, it starts
incrementing from 0 at a frequency of fOSC/32. An
overflow event occurs when the counter rolls over
from F9h to 00h. If fOSC = 8 MHz, then the time period between two counter overflow events is 1 ms.
This period can be doubled by setting the TB bit in
the LTCSR1 register.
When Counter 1 overflows, the TB1F bit is set by
hardware and an interrupt request is generated if
the TB1IE bit is set. The TB1F bit is cleared by
software reading the LTCSR1 register.
11.3.3.2 Timebase Counter 2
Counter 2 is an 8-bit autoreload upcounter. It can
be read by accessing the LTCNTR register. After
an MCU reset, it increments at a frequency of
fOSC/32 starting from the value stored in the
LTARR register. A counter overflow event occurs
when the counter rolls over from FFh to the
LTARR reload value. Software can write a new
value at anytime in the LTARR register, this value
will be automatically loaded in the counter when
the next overflow occurs.
When Counter 2 overflows, the TB2F bit in the
LTCSR2 register is set by hardware and an interrupt request is generated if the TB2IE bit is set.
The TB2F bit is cleared by software reading the
LTCSR2 register.
11.3.3.3 Input Capture
The 8-bit input capture register is used to latch the
free-running upcounter (Counter 1) 1 after a rising
or falling edge is detected on the LTIC pin. When
an input capture occurs, the ICF bit is set and the
LTICR register contains the value of Counter 1. An
interrupt is generated if the ICIE bit is set. The ICF
bit is cleared by reading the LTICR register.
The LTICR is a read-only register and always contains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
Figure 47. Input Capture Timing Diagram.
4µs
(@ 8MHz fOSC)
fCPU
fOSC/32
8-bit COUNTER 1
01h
02h
03h
04h
05h
06h
07h
CLEARED
BY S/W
READING
LTIC REGISTER
LTIC PIN
ICF FLAG
LTICR REGISTER
xxh
04h
07h
t
74/173
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ST7LITE3xF2
LITE TIMER (Cont’d)
11.3.4 Low Power Modes
11.3.6 Register Description
Mode
Description
No effect on Lite timer
SLOW
(this peripheral is driven directly
by fOSC/32)
WAIT
No effect on Lite timer
ACTIVE-HALT No effect on Lite timer
HALT
Lite timer stops counting
11.3.5 Interrupts
Interrupt
Event
7
0
0
0
0
0
0
0
TB2IE
TB2F
Bits 7:2 = Reserved, must be kept cleared.
Exit
from
Wait
Exit
from
Active
Halt
Exit
from
Halt
TB1IE
Yes
Yes
No
TB2IE
Yes
No
No
ICIE
Yes
No
No
Enable
Event
Control
Flag
Bit
Timebase 1
TB1F
Event
Timebase 2
TB2F
Event
IC Event
ICF
LITE TIMER CONTROL/STATUS REGISTER 2
(LTCSR2)
Read / Write
Reset Value: 0x00 0000 (x0h)
Note: The TBxF and ICF interrupt events are connected to separate interrupt vectors (see Interrupts chapter).
They generate an interrupt if the enable bit is set in
the LTCSR1 or LTCSR2 register and the interrupt
mask in the CC register is reset (RIM instruction).
Bit 1 = TB2IE Timebase 2 Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
Bit 0 = TB2F Timebase 2 Interrupt Flag.
This bit is set by hardware and cleared by software
reading the LTCSR2 register. Writing to this bit
has no effect.
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred
LITE
TIMER
AUTORELOAD
(LTARR)
Read / Write
Reset Value: 0000 0000 (00h)
REGISTER
7
AR7
0
AR7
AR7
AR7
AR3
AR2
AR1
AR0
Bits 7:0 = AR[7:0] Counter 2 Reload Value.
These bits register is read/write by software. The
LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
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ST7LITE3xF2
LITE TIMER (Cont’d)
LITE TIMER COUNTER 2 (LTCNTR)
Read only
Reset Value: 0000 0000 (00h)
7
CNT7
0
CNT7
CNT7
CNT7
CNT3
CNT2
CNT1
CNT0
Bits 7:0 = CNT[7:0] Counter 2 Reload Value.
This register is read by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs.
LITE TIMER CONTROL/STATUS REGISTER
(LTCSR1)
Read / Write
Reset Value: 0x00 00x0 (xxh)
7
ICIE
0
ICF
TB
TB1IE
TB1F
-
-
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the LTICR register. Writing to this bit
does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialise
the ICF bit by reading the LTICR register
1
Bit 4 = TB1IE Timebase Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
Bit 3 = TB1F Timebase Interrupt Flag.
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
0: No counter overflow
1: A counter overflow has occurred
Bits 2:0 = Reserved
-
Bit 7 = ICIE Interrupt Enable.
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
76/173
Bit 5 = TB Timebase period selection.
This bit is set and cleared by software.
0: Timebase period = tOSC * 8000 (1ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2ms @ 8
MHz)
LITE TIMER INPUT CAPTURE REGISTER
(LTICR)
Read only
Reset Value: 0000 0000 (00h)
7
ICR7
0
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
ICR0
Bits 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by
hardware after a reset. If the ICF bit in the LTCSR
is cleared, the value of the 8-bit up-counter will be
captured when a rising or falling edge occurs on
the LTIC pin.
ST7LITE3xF2
LITE TIMER (Cont’d)
Table 17. Lite Timer Register Map and Reset Values
Address
Register
Label
7
6
5
4
3
2
1
0
08
LTCSR2
Reset Value
0
0
0
0
0
0
TB2IE
0
TB2F
0
09
LTARR
Reset Value
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
0A
LTCNTR
Reset Value
CNT7
0
CNT6
0
CNT5
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
0B
LTCSR1
Reset Value
ICIE
0
ICF
x
TB
0
TB1IE
0
TB1F
0
0
x
0
0C
LTICR
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
(Hex.)
77/173
1
ST7LITE3xF2
ON-CHIP PERIPHERALS (cont’d)
11.4 SERIAL PERIPHERAL INTERFACE (SPI)
11.4.1 Introduction
The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
11.4.2 Main Features
■ Full duplex synchronous transfers (on three
lines)
■ Simplex synchronous transfers (on two lines)
■ Master or slave operation
■ 6 master mode frequencies (fCPU/4 max.)
■ fCPU/2 max. slave mode frequency (see note)
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision, Master Mode Fault and Overrun
flags
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
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11.4.3 General Description
Figure 48 on page 79 shows the serial peripheral
interface (SPI) block diagram. There are three registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
The SPI is connected to external devices through
four pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and input by SPI slaves
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves individually and to avoid contention on the data
lines. Slave SS inputs can be driven by standard I/O ports on the master Device.
ST7LITE3xF2
SERIAL PERIPHERAL INTERFACE (SPI) (cont’d)
Figure 48. Serial Peripheral Interface Block Diagram
Data/Address Bus
SPIDR
Read
Interrupt
request
Read Buffer
MOSI
MISO
8-bit Shift Register
SPICSR
7
SPIF WCOL OVR MODF
SOD
bit
0
SOD SSM
0
SSI
Write
SS
SPI
STATE
CONTROL
SCK
7
SPIE
1
0
SPICR
0
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
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ST7LITE3xF2
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 49.
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits data to a
slave device via MOSI pin, the slave device responds by sending data to the master device via
the MISO pin. This implies full duplex communication with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see Figure 52 on page 83) but master
and slave must be programmed with the same timing mode.
Figure 49. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
8-bit SHIFT REGISTER
SPI
CLOCK
GENERATOR
MSBit
MISO
MISO
MOSI
MOSI
SCK
SS
LSBit
8-bit SHIFT REGISTER
SCK
+5V
SS
Not used if SS is managed
by software
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ST7LITE3xF2
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR register (see Figure 51).
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
– SS internal must be held high continuously
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see Figure 50):
If CPHA = 1 (data latched on second clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
VSS, or made free for standard I/O by managing the SS function by software (SSM = 1 and
SSI = 0 in the in the SPICSR register)
If CPHA = 0 (data latched on first clock edge):
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 11.4.5.3).
Figure 50. Generic SS Timing Diagram
MOSI/MISO
Byte 1
Byte 2
Byte 3
Master SS
Slave SS
(if CPHA = 0)
Slave SS
(if CPHA = 1)
Figure 51. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
SS external pin
0
SS internal
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SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.3.3 Master Mode Operation
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the
following steps in order:
1. Write to the SPICR register:
– Select the clock frequency by configuring the
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
52 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICSR register:
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
Important note: if the SPICSR register is not written first, the SPICR register setting (MSTR bit)
may be not taken into account.
The transmit sequence begins when software
writes a byte in the SPIDR register.
11.4.3.4 Master Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware.
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register
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Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
11.4.3.5 Slave Mode Operation
In slave mode, the serial clock is received on the
SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the following actions:
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 52).
Note: The slave must have the same CPOL
and CPHA settings as the master.
– Manage the SS pin as described in Section
11.4.3.2 and Figure 50. If CPHA = 1 SS must
be held low continuously. If CPHA = 0 SS
must be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
11.4.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware.
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPICSR register while the
SPIF bit is set
2. A write or a read to the SPIDR register
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 11.4.5.2).
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SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.4 Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 52).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0).
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge.
Figure 52 shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin and
the MOSI pin are directly connected between the
master and the slave device.
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by resetting the SPE bit.
Figure 52. Data Clock Timing Diagram
CPHA = 1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
CPHA = 0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
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SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.5 Error Flags
11.4.5.1 Master Mode Fault (MODF)
Master mode fault occurs when the master device’s SS pin is pulled low.
When a Master mode fault occurs:
– The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI peripheral.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
1. A read access to the SPICSR register while the
MODF bit is set.
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
In a slave device, the MODF bit can not be set, but
in a multimaster configuration the device can be in
slave mode with the MODF bit set.
The MODF bit indicates that there might have
been a multimaster conflict and allows software to
handle this using an interrupt routine and either
perform a reset or return to an application default
state.
11.4.5.2 Overrun Condition (OVR)
An overrun condition occurs when the master device has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
When an Overrun occurs:
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
The OVR bit is cleared by reading the SPICSR
register.
11.4.5.3 Write Collision Error (WCOL)
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted and
the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode. See also Section 11.4.3.2 Slave Select
Management.
Note: A "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the CPU operation.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 53).
Figure 53. Clearing the WCOL Bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
Read SPICSR
2nd Step
Read SPIDR
RESULT
SPIF = 0
WCOL = 0
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
Read SPICSR
RESULT
2nd Step
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Read SPIDR
WCOL = 0
Note: Writing to the SPIDR register instead of reading it does not reset the
WCOL bit.
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SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.5.4 Single Master and Multimaster
Configurations
There are two types of SPI systems:
– Single Master System
– Multimaster System
Single Master System
A typical single master system may be configured
using a device as the master and four devices as
slaves (see Figure 54).
The master device selects the individual slave devices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line,
the master allows only one active slave device
during a transmission.
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR
register.
Other transmission security methods can use
ports for handshake lines or data bytes with command fields.
Multimaster System
A multimaster system may also be configured by
the user. Transfer of master control could be implemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The multimaster system is principally handled by
the MSTR bit in the SPICR register and the MODF
bit in the SPICSR register.
Figure 54. Single Master / Multiple Slave Configuration
SS
SCK
Slave
Device
MOSI MISO
SS
SS
SCK
Slave
Device
MOSI
MISO
SS
SCK
Slave
Device
SCK
Slave
Device
MOSI
MOSI
MISO
MISO
SCK
Master
Device
5V
Ports
MOSI MISO
SS
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SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.6 Low Power Modes
Mode
WAIT
HALT
Description
No effect on SPI.
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the device is woken up
by an interrupt with “exit from HALT mode”
capability. The data received is subsequently
read from the SPIDR register when the software is running (interrupt vector fetching). If
several data are received before the wakeup event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the Device.
11.4.6.1 Using the SPI to wake up the device
from Halt mode
In slave configuration, the SPI is able to wake up
the device from HALT mode through a SPIF interrupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from HALT mode, if the
SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring
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the SPI from HALT mode state to normal state. If
the SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake up the device from
HALT mode only if the Slave Select signal (external SS pin or the SSI bit in the SPICSR register) is
low when the device enters HALT mode. So, if
Slave selection is configured as external (see Section 11.4.3.2), make sure the master drives a low
level on the SS pin when the slave enters HALT
mode.
11.4.7 Interrupts
Interrupt Event
SPI End of
Transfer Event
Master Mode
Fault Event
Overrun Error
Event
Flag
Enable
Control
Bit
Exit
from
Wait
SPIF
MODF
Exit
from
Halt
Yes
SPIE
Yes
No
OVR
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
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11.4.8 Register Description
SPI CONTROL REGISTER (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
7
SPIE
0
SPE
SPR2 MSTR CPOL CPHA SPR1
SPR0
Bit 7 = SPIE Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End
of Transfer event, Master Mode Fault or Overrun error occurs (SPIF = 1, MODF = 1 or
OVR = 1 in the SPICSR register)
Bit 6 = SPE Serial Peripheral Output Enable
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see Section 11.4.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 18 SPI Master
Mode SCK Frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
Bit 3 = CPOL Clock Polarity
This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by resetting the SPE bit.
Bit 2 = CPHA Clock Phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
Note: These 2 bits have no effect in slave mode.
Table 18. SPI Master Mode SCK Frequency
Serial Clock
SPR2
fCPU/4
1
fCPU/8
fCPU/16
fCPU/32
fCPU/64
Bit 4 = MSTR Master Mode
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see Section 11.4.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
fCPU/128
0
SPR1
0
0
1
1
0
SPR0
1
0
1
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SERIAL PERIPHERAL INTERFACE (cont’d)
SPI CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
7
SPIF
0
WCOL
OVR
MODF
-
SOD
SSM
SSI
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only)
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE = 1 in the SPICR register. It is cleared by
a software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an external device has been completed.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
Bit 6 = WCOL Write Collision status (Read only)
This bit is set by hardware when a write to the
SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see
Figure 53).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = OVR SPI Overrun error (Read only)
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 11.4.5.2). An interrupt is generated if
SPIE = 1 in the SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
Bit 4 = MODF Mode Fault flag (Read only)
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 11.4.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE = 1 in the SPICR register.
This bit is cleared by a software sequence (An access to the SPICSR register while MODF = 1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
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Bit 2 = SOD SPI Output Disable
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
Bit 1 = SSM SS Management
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
11.4.3.2 Slave Select Management.
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O)
Bit 0 = SSI SS Internal Mode
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
SPI DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
D7
0
D6
D5
D4
D3
D2
D1
D0
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of the shift
register (see Figure 48).
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Table 19. SPI Register Map and Reset Values
Address
Register
Label
7
6
5
4
3
2
1
0
0031h
SPIDR
Reset Value
MSB
x
x
x
x
x
x
x
LSB
x
0032h
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
0033h
SPICSR
Reset Value
SPIF
0
WCOL
0
OVR
0
MODF
0
0
SOD
0
SSM
0
SSI
0
(Hex.)
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11.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE)
11.5.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two
baud rate generator systems.
The LIN-dedicated features support the LIN (Local
Interconnect Network) protocol for both master
and slave nodes.
This chapter is divided into SCI Mode and LIN
mode sections. For information on general SCI
communications, refer to the SCI mode section.
For LIN applications, refer to both the SCI mode
and LIN mode sections.
11.5.2 SCI Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Independently
programmable transmit and
receive baud rates up to 500K baud
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ 2 receiver wake-up modes:
– Address bit (MSB)
– Idle line
■ Muting function for multiprocessor configurations
■ Separate enable bits for Transmitter and
Receiver
■ Overrun, Noise and Frame error detection
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6 interrupt sources
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error
– Parity interrupt
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
11.5.3 LIN Features
– LIN Master
– 13-bit LIN Synch Break generation
– LIN Slave
– Automatic Header Handling
– Automatic baud rate resynchronization based
on recognition and measurement of the LIN
Synch Field (for LIN slave nodes)
– Automatic baud rate adjustment (at CPU frequency precision)
– 11-bit LIN Synch Break detection capability
– LIN Parity check on the LIN Identifier Field
(only in reception)
– LIN Error management
– LIN Header Timeout
– Hot plugging support
■
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LINSCI™ SERIAL COMMUNICATION INTERFACE (cont’d)
11.5.4 General Description
– A conventional type for commonly-used baud
rates
The interface is externally connected to another
device by two pins:
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
– TDO: Transmit Data Output. When the transmitoscillator frequencies
ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena– A LIN baud rate generator with automatic resynbled and nothing is to be transmitted, the TDO
chronization
pin is at high level.
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data recovery by discriminating between valid incoming
data and noise.
Through these pins, serial data is transmitted and
received as characters comprising:
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the character is complete
This interface uses three types of baud rate generator:
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
Figure 55. SCI Block Diagram (in Conventional Baud Rate Generator Mode)
Write
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Transmit Data Register (TDR)
TDO
Receive Shift Register
Transmit Shift Register
RDI
SCICR1
R8
TRANSMIT
WAKE
UP
CONTROL
UNIT
T8
SCID M
WAKE PCE
PS PIE
RECEIVER
CLOCK
RECEIVER
CONTROL
SCISR
SCICR2
TIE TCIE RIE
ILIE
TE
RE RWU SBK
OR/
TDRE TC RDRF IDLE
LHE
NF
FE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
fCPU
CONTROL
/16
/PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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PE
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.5.1 Serial Data Format
11.5.5 SCI Mode - Functional Description
Word length may be selected as being either 8 or 9
Conventional Baud Rate Generator Mode
bits by programming the M bit in the SCICR1 regThe block diagram of the Serial Control Interface
ister (see Figure 56).
in conventional baud rate generator mode is
shown in Figure 55.
The TDO pin is in low state during the start bit.
It uses four registers:
The TDO pin is in high state during the stop bit.
– 2 control registers (SCICR1 and SCICR2)
An Idle character is interpreted as a continuous
logic high level for 10 (or 11) full bit times.
– A status register (SCISR)
A Break character is a character with a sufficient
– A baud rate register (SCIBRR)
number of low level bits to break the normal data
Extended Prescaler Mode
format followed by an extra “1” bit to acknowledge
the start bit.
Two additional prescalers are available in extended prescaler mode. They are shown in Figure 57.
– An extended prescaler receiver register (SCIERPR)
– An extended prescaler transmitter register (SCIETPR)
Figure 56. Word Length Programming
9-bit Word length (M bit is set)
Possible
Parity
Bit
Data Character
Start
Bit
Bit0
Bit2
Bit1
Bit3
Bit4
Bit5
Bit6
Start
Bit
Break Character
Extra
’1’
Possible
Parity
Bit
Data Character
Bit0
Bit8
Next
Stop Start
Bit
Bit
Idle Line
8-bit Word length (M bit is reset)
Start
Bit
Bit7
Next Data Character
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Start
Bit
Next Data Character
Stop
Bit
Next
Start
Bit
Idle Line
Start
Bit
Break Character
Extra Start
Bit
’1’
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.5.2 Transmitter
When no transmission is taking place, a write instruction to the SCIDR register places the data diThe transmitter can send data words of either 8 or
rectly in the shift register, the data transmission
9 bits depending on the M bit status. When the M
starts, and the TDRE bit is immediately set.
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
When a character transmission is complete (after
register.
the stop bit) the TC bit is set and an interrupt is
generated if the TCIE is set and the I[1:0] bits are
Character Transmission
cleared in the CCR register.
During an SCI transmission, data shifts out least
Clearing the TC bit is performed by the following
significant bit first on the TDO pin. In this mode,
software sequence:
the SCIDR register consists of a buffer (TDR) be1. An access to the SCISR register
tween the internal bus and the transmit shift regis2. A write to the SCIDR register
ter (see Figure 55).
Note: The TDRE and TC bits are cleared by the
Procedure
same software sequence.
– Select the M bit to define the word length.
Break Characters
– Select the desired baud rate using the SCIBRR
Setting the SBK bit loads the shift register with a
and the SCIETPR registers.
break character. The break character length de– Set the TE bit to send a preamble of 10 (M = 0)
pends on the M bit (see Figure 56).
or 11 (M = 1) consecutive ones (Idle Line) as first
As long as the SBK bit is set, the SCI sends break
transmission.
characters to the TDO pin. After clearing this bit by
– Access the SCISR register and write the data to
software, the SCI inserts a logic 1 bit at the end of
send in the SCIDR register (this sequence clears
the last break character to guarantee the recognithe TDRE bit). Repeat this sequence for each
tion of the start bit of the next character.
data to be transmitted.
Idle Line
Clearing the TDRE bit is always performed by the
Setting the TE bit drives the SCI to send a preamfollowing software sequence:
ble of 10 (M = 0) or 11 (M = 1) consecutive ‘1’s
1. An access to the SCISR register
(idle line) before the first character.
2. A write to the SCIDR register
In this case, clearing and then setting the TE bit
The TDRE bit is set by hardware and it indicates:
during a transmission sends a preamble (idle line)
– The TDR register is empty.
after the current word. Note that the preamble duration (10 or 11 consecutive ‘1’s depending on the
– The data transfer is beginning.
M bit) does not take into account the stop bit of the
– The next data can be written in the SCIDR regisprevious character.
ter without overwriting the previous data.
Note: Resetting and setting the TE bit causes the
This flag generates an interrupt if the TIE bit is set
data in the TDR register to be lost. Therefore the
and the I[|1:0] bits are cleared in the CCR register.
best time to toggle the TE bit is when the TDRE bit
When a transmission is taking place, a write inis set, that is, before writing the next byte in the
struction to the SCIDR register stores the data in
SCIDR.
the TDR register and which is copied in the shift
register at the end of the current transmission.
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.5.3 Receiver
– The OR bit is set.
The SCI can receive data words of either 8 or 9
– The RDR content will not be lost.
bits. When the M bit is set, word length is 9 bits
– The shift register will be overwritten.
and the MSB is stored in the R8 bit in the SCICR1
– An interrupt is generated if the RIE bit is set and
register.
the I[|1:0] bits are cleared in the CCR register.
Character reception
The OR bit is reset by an access to the SCISR regDuring a SCI reception, data shifts in least signifiister followed by a SCIDR register read operation.
cant bit first through the RDI pin. In this mode, the
Noise Error
SCIDR register consists or a buffer (RDR) between the internal bus and the received shift regisOversampling techniques are used for data recovter (see Figure 55).
ery by discriminating between valid incoming data
and noise.
Procedure
When noise is detected in a character:
– Select the M bit to define the word length.
– The NF bit is set at the rising edge of the RDRF
– Select the desired baud rate using the SCIBRR
bit.
and the SCIERPR registers.
– Data is transferred from the Shift register to the
– Set the RE bit, this enables the receiver which
SCIDR register.
begins searching for a start bit.
– No interrupt is generated. However this bit rises
When a character is received:
at the same time as the RDRF bit which itself
– The RDRF bit is set. It indicates that the content
generates an interrupt.
of the shift register is transferred to the RDR.
The NF bit is reset by a SCISR register read oper– An interrupt is generated if the RIE bit is set and
ation followed by a SCIDR register read operation.
the I[1:0] bits are cleared in the CCR register.
Framing Error
– The error flags can be set if a frame error, noise
A framing error is detected when:
or an overrun error has been detected during reception.
– The stop bit is not recognized on reception at the
expected time, following either a desynchronizaClearing the RDRF bit is performed by the following
tion or excessive noise.
software sequence done by:
–
A break is received.
1. An access to the SCISR register
When the framing error is detected:
2. A read to the SCIDR register.
– the FE bit is set by hardware
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
– Data is transferred from the Shift register to the
error.
SCIDR register.
Idle Line
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
When an idle line is detected, there is the same
generates an interrupt.
procedure as a data received character plus an interrupt if the ILIE bit is set and the I[|1:0] bits are
The FE bit is reset by a SCISR register read opercleared in the CCR register.
ation followed by a SCIDR register read operation.
Overrun Error
Break Character
An overrun error occurs when a character is re– When a break character is received, the SCI
ceived when RDRF has not been reset. Data can
handles it as a framing error. To differentiate a
not be transferred from the shift register to the
break character from a framing error, it is necesTDR register as long as the RDRF bit is not
sary to read the SCIDR. If the received value is
cleared.
00h, it is a break character. Otherwise it is a
framing error.
When an overrun error occurs:
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.5.4 Conventional Baud Rate Generation
11.5.5.5 Extended Baud Rate Generation
The baud rates for the receiver and transmitter (Rx
The extended prescaler option gives a very fine
and Tx) are set independently and calculated as
tuning on the baud rate, using a 255 value prescalfollows:
er, whereas the conventional Baud Rate Generator retains industry standard software compatibilifCPU
fCPU
ty.
Rx =
Tx =
The extended baud rate generator block diagram
(16*PR)*RR
(16*PR)*TR
is described in Figure 57.
with:
The output clock rate sent to the transmitter or to
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
TR = 1, 2, 4, 8, 16, 32, 64,128
SCIERPR or the SCIETPR register.
(see SCT[2:0] bits)
Note: The extended prescaler is activated by setRR = 1, 2, 4, 8, 16, 32, 64,128
ting the SCIETPR or SCIERPR register to a value
(see SCR[2:0] bits)
other than zero. The baud rates are calculated as
follows:
All these bits are in the SCIBRR register.
Example: If fCPU is 8 MHz (normal mode) and if
fCPU
fCPU
PR = 13 and TR = RR = 1, the transmit and reRx =
Tx =
ceive baud rates are 38400 baud.
16*ERPR*(PR*RR)
16*ETPR*(PR*TR)
Note: The baud rate registers MUST NOT be
changed while the transmitter or the receiver is enwith:
abled.
ETPR = 1, ..., 255 (see SCIETPR register)
ERPR = 1, ..., 255 (see SCIERPR register)
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
Figure 57. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
fCPU
TRANSMITTER RATE
CONTROL
/16
/PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.5.6 Receiver Muting and Wake-up Feature
ceived an address character (most significant bit
= ’1’), the receivers are waken up. The receivers
In multiprocessor configurations it is often desirawhich are not addressed set RWU bit to enter in
ble that only the intended message recipient
mute mode. Consequently, they will not treat the
should actively receive the full message contents,
next characters constituting the next part of the
thus reducing redundant SCI service overhead for
message.
all non-addressed receivers.
11.5.5.7 Parity Control
The non-addressed devices may be placed in
sleep mode by means of the muting function.
Hardware byte Parity control (generation of parity
bit in transmission and parity checking in recepSetting the RWU bit by software puts the SCI in
tion) can be enabled by setting the PCE bit in the
sleep mode:
SCICR1 register. Depending on the character forAll the reception status bits can not be set.
mat defined by the M bit, the possible SCI character formats are as listed in Table 20.
All the receive interrupts are inhibited.
Note: In case of wake-up by an address mark, the
A muted receiver may be woken up in one of the
MSB bit of the data is taken into account and not
following ways:
the parity bit
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Idle Line Detection
Receiver wakes up by Idle Line detection when the
Receive line has recognized an Idle Line. Then the
RWU bit is reset by hardware but the IDLE bit is
not set.
This feature is useful in a multiprocessor system
when the first characters of the message determine the address and when each message ends
by an idle line: As soon as the line becomes idle,
every receivers is waken up and analyse the first
characters of the message which indicates the addressed receiver. The receivers which are not addressed set RWU bit to enter in mute mode. Consequently, they will not treat the next characters
constituting the next part of the message. At the
end of the message, an idle line is sent by the
transmitter: this wakes up every receivers which
are ready to analyse the addressing characters of
the new message.
In such a system, the inter-characters space must
be smaller than the idle time.
Address Mark Detection
Receiver wakes up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an address. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
This feature is useful in a multiprocessor system
when the most significant bit of each character
(except for the break character) is reserved for Address Detection. As soon as the receivers re-
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1
Table 20. Character Formats
M bit
0
1
PCE bit
0
1
0
1
Character format
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data | PB | STB |
Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Even parity: The parity bit is calculated to obtain
an even number of “1s” inside the character made
of the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit
will be 0 if even parity is selected (PS bit = 0).
Odd parity: The parity bit is calculated to obtain
an odd number of “1s” inside the character made
of the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit
will be 1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the interface checks if the received data byte has an
even number of “1s” if even parity is selected
(PS = 0) or an odd number of “1s” if odd parity is
selected (PS = 1). If the parity check fails, the PE
flag is set in the SCISR register and an interrupt is
generated if PCIE is set in the SCICR1 register.
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.6 Low Power Modes
11.5.7 Interrupts
Mode
WAIT
HALT
Description
No effect on SCI.
SCI interrupts cause the device to exit from
Wait mode.
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
Interrupt Event
Enable Exit
Event
Control from
Flag
Bit
Wait
Transmit Data Register
TDRE
Empty
Transmission ComTC
plete
Received Data Ready
RDRF
to be Read
Overrun Error or LIN
OR/
Synch Error Detected
LHE
Idle Line Detected
IDLE
Parity Error
PE
LIN Header Detection LHDF
Exit
from
Halt
TIE
TCIE
RIE
Yes
No
ILIE
PIE
LHIE
The SCI interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.8 SCI Mode Register Description
STATUS REGISTER (SCISR)
Bit 3 = OR Overrun error
Read Only
The OR bit is set by hardware when the word curReset Value: 1100 0000 (C0h)
rently being received in the shift register is ready to
be transferred into the RDR register whereas
7
0
RDRF is still set. An interrupt is generated if
RIE = 1 in the SCICR2 register. It is cleared by a
1)
1)
1)
1)
TDRE
TC
RDRF IDLE OR
NF
FE
PE
software sequence (an access to the SCISR register followed by a read to the SCIDR register).
0: No Overrun error
Bit 7 = TDRE Transmit data register empty
1: Overrun error detected
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
Note: When this bit is set, RDR register contents
register. An interrupt is generated if the TIE = 1 in
will not be lost but the shift register will be overwritthe SCICR2 register. It is cleared by a software seten.
quence (an access to the SCISR register followed
by a write to the SCIDR register).
0: Data is not transferred to the shift register
Bit 2 = NF Character Noise flag
1: Data is transferred to the shift register
This bit is set by hardware when noise is detected
on a received character. It is cleared by a software
sequence (an access to the SCISR register folBit 6 = TC Transmission complete
lowed by a read to the SCIDR register).
This bit is set by hardware when transmission of a
0: No noise
character containing Data is complete. An inter1: Noise is detected
rupt is generated if TCIE = 1 in the SCICR2 regisNote: This bit does not generate interrupt as it apter. It is cleared by a software sequence (an acpears at the same time as the RDRF bit which itcess to the SCISR register followed by a write to
self generates an interrupt.
the SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error
Note: TC is not set after the transmission of a PreThis bit is set by hardware when a desynchronizaamble or a Break.
tion, excessive noise or a break character is detected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
Bit 5 = RDRF Received data ready flag
the SCIDR register).
This bit is set by hardware when the content of the
0: No Framing error
RDR register has been transferred to the SCIDR
1: Framing error or break character detected
register. An interrupt is generated if RIE = 1 in the
Note: This bit does not generate an interrupt as it
SCICR2 register. It is cleared by a software seappears at the same time as the RDRF bit which itquence (an access to the SCISR register followed
self generates an interrupt. If the word currently
by a read to the SCIDR register).
being transferred causes both a frame error and
0: Data is not received
an overrun error, it will be transferred and only the
1: Received data is ready to be read
OR bit will be set.
Bit 4 = IDLE Idle line detected
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the ILIE = 1 in
the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (that is, a new idle line
occurs).
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1
Bit 0 = PE Parity error
This bit is set by hardware when a byte parity error
occurs (if the PCE bit is set) in receiver mode. It is
cleared by a software sequence (a read to the status register followed by an access to the SCIDR
data register). An interrupt is generated if PIE = 1
in the SCICR1 register.
0: No parity error
1: Parity error detected
ST7LITE3xF2
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
CONTROL REGISTER 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method
Reset Value: x000 0000 (x0h)
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
7
0
0: Idle Line
1: Address Mark
R8
T8
SCID
M
WAKE PCE1)
PS
PIE
Note: If the LINE bit is set, the WAKE bit is deactivated and replaced by the LHDM bit.
1)
This bit has a different function in LIN mode, please
refer to the LIN mode register description.
Bit 7 = R8 Receive data bit 8
This bit is used to store the 9th bit of the received
word when M = 1.
Bit 6 = T8 Transmit data bit 8
This bit is used to store the 9th bit of the transmitted word when M = 1.
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte transfer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 4 = M Word length
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
Bit 2 = PCE Parity control enable
This bit is set and cleared by software. It selects
the hardware parity control (generation and detection for byte parity, detection only for LIN parity).
0: Parity control disabled
1: Parity control enabled
Bit 1 = PS Parity selection
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
1: Odd parity
Bit 0 = PIE Parity interrupt enable
This bit enables the interrupt capability of the hardware parity control when a parity error is detected
(PE bit set). The parity error involved can be a byte
parity error (if bit PCE is set and bit LPE is reset) or
a LIN parity error (if bit PCE is set and bit LPE is
set).
0: Parity error interrupt disabled
1: Parity error interrupt enabled
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
CONTROL REGISTER 2 (SCICR2)
1: Receiver is enabled and begins searching for a
Read/Write
start bit
Reset Value: 0000 0000 (00h)
Bit 1 = RWU Receiver wake-up
7
0
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
TIE
TCIE
RIE
ILIE
TE
RE
RWU1) SBK1)
cleared by hardware when a wake-up sequence is
recognized.
1)
0: Receiver in active mode
This bit has a different function in LIN mode, please
1: Receiver in mute mode
refer to the LIN mode register description.
Notes:
Bit 7 = TIE Transmitter interrupt enable
This bit is set and cleared by software.
– Before selecting Mute mode (by setting the RWU
0: Interrupt is inhibited
bit) the SCI must first receive a data byte, other1: In SCI interrupt is generated whenever
wise it cannot function in Mute mode with wakeTDRE = 1 in the SCISR register
up by Idle line detection.
– In Address Mark Detection Wake-Up configuraBit 6 = TCIE Transmission complete interrupt enation (WAKE bit = 1) the RWU bit cannot be modble
ified by software while the RDRF bit is set.
This bit is set and cleared by software.
0: Interrupt is inhibited
Bit 0 = SBK Send break
1: An SCI interrupt is generated whenever TC = 1
This bit set is used to send break characters. It is
in the SCISR register
set and cleared by software.
0: No break character is transmitted
Bit 5 = RIE Receiver interrupt enable
1: Break characters are transmitted
This bit is set and cleared by software.
Note: If the SBK bit is set to “1” and then to “0”, the
0: Interrupt is inhibited
transmitter will send a BREAK word at the end of
1: An SCI interrupt is generated whenever OR = 1
the current word.
or RDRF = 1 in the SCISR register
Bit 4 = ILIE Idle line interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
IDLE = 1 in the SCISR register.
Bit 3 = TE Transmitter enable
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
– When TE is set there is a 1 bit-time delay before
the transmission starts.
Bit 2 = RE Receiver enable
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled in the SCISR register
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DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data character, depending on whether it is read from or written to.
7
DR7
0
DR6
DR5
DR4
DR3
DR2
DR1
DR0
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift register (see Figure 55).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 55).
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
BAUD RATE REGISTER (SCIBRR)
TR dividing factor
Read/Write
1
Reset Value: 0000 0000 (00h)
2
7
0
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1 SCR0
4
SCT2
0
0
1
8
16
Note: When LIN slave mode is disabled, the SCIBRR register controls the conventional baud rate
generator.
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
PR Prescaling factor
1
3
4
13
SCP1
0
1
SCP0
0
1
0
1
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and
SCP0 bits define the total division applied to the
bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
32
64
SCT1
0
1
1
128
SCT0
0
1
0
1
0
1
0
1
Bits 2:0 = SCR[2:0] SCI Receiver rate divider
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
RR dividing factor
SCR2
1
2
4
0
0
1
8
16
32
64
128
SCR1
0
1
1
SCR0
0
1
0
1
0
1
0
1
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIERPR)
REGISTER (SCIETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
7
6
5
4
3
2
1
0
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this register. The clock frequency from the 16 divider (see
Figure 57) is divided by the binary factor set in the
SCIERPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
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7
ETPR
7
0
ETPR
6
ETPR
5
ETPR
4
ETPR
3
ETPR
2
ETPR ETPR
1
0
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this register. The clock frequency from the 16 divider (see
Figure 57) is divided by the binary factor set in the
SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
Note: In LIN slave mode, the Conventional and
Extended Baud Rate Generators are disabled.
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode)
11.5.9 LIN Mode - Functional Description.
Slave
The block diagram of the Serial Control Interface,
Set the LSLV bit in the SCICR3 register to enter
in LIN slave mode is shown in Figure 59.
LIN slave mode. In this case, setting the SBK bit
will have no effect.
It uses six registers:
In LIN Slave mode the LIN baud rate generator is
– 3 control registers: SCICR1, SCICR2 and
selected instead of the Conventional or Extended
SCICR3
Prescaler. The LIN baud rate generator is com– 2 status registers: the SCISR register and the
mon to the transmitter and the receiver.
LHLR register mapped at the SCIERPR address
Then the baud rate can be programmed using
– A baud rate register: LPR mapped at the SCILPR and LPRF registers.
BRR address and an associated fraction register
Note: It is mandatory to set the LIN configuration
LPFR mapped at the SCIETPR address
first before programming LPR and LPRF, because
The bits dedicated to LIN are located in the
the LIN configuration uses a different baud rate
SCICR3. Refer to the register descriptions in Secgenerator from the standard one.
tion 11.5.10for the definitions of each bit.
11.5.9.1 Entering LIN Mode
11.5.9.2 LIN Transmission
To use the LINSCI in LIN mode the following conIn LIN mode the same procedure as in SCI mode
figuration must be set in SCICR3 register:
has to be applied for a LIN transmission.
– Clear the M bit to configure 8-bit word length.
To transmit the LIN Header the proceed as fol– Set the LINE bit.
lows:
Master
– First set the SBK bit in the SCICR2 register to
start transmitting a 13-bit LIN Synch Break
To enter master mode the LSLV bit must be reset
In this case, setting the SBK bit will send 13 low
– reset the SBK bit
bits.
– Load the LIN Synch Field (0x55) in the SCIDR
Then the baud rate can programmed using the
register to request Synch Field transmission
SCIBRR, SCIERPR and SCIETPR registers.
– Wait until the SCIDR is empty (TDRE bit set in
In LIN master mode, the Conventional and / or Exthe SCISR register)
tended Prescaler define the baud rate (as in stand– Load the LIN message Identifier in the SCIDR
ard SCI mode)
register to request Identifier transmission.
105/173
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
Figure 58. LIN Characters
8-bit Word length (M bit is reset)
Next Data Character
Data Character
Next
Start
Start
Stop
Bit
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Start
Bit
Idle Line
LIN Synch Field
LIN Synch Break = 13 low bits
LIN Synch Field
Next
Start
Start
Stop
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Bit
Measurement for baud rate autosynchronization
106/173
Extra Start
‘1’ Bit
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
Figure 59. SCI Block Diagram in LIN Slave Mode
Write
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Transmit Data Register (TDR)
TDO
Receive Shift Register
Transmit Shift Register
RDI
SCICR1
R8
TRANSMIT
WAKE
UP
CONTROL
UNIT
T8 SCID M
WAKE PCE
PS
PIE
RECEIVER
CONTROL
RECEIVER
CLOCK
SCISR
SCICR2
TIE TCIE RIE ILIE
TE
RE RWU SBK
OR/
TDRE TC RDRF IDLE
LHE NF
FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
fCPU
SCICR3
LIN SLAVE BAUD RATE
AUTO SYNCHRONIZATION
UNIT
LDUM LINE LSLV LASE LHDM LHIE LHDF LSF
SCIBRR
LPR7
LPR0
CONVENTIONAL BAUD RATE
GENERATOR
+
EXTENDED PRESCALER
fCPU
/ LDIV
/16
0
1
LIN SLAVE BAUD RATE GENERATOR
107/173
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.9.3 LIN Reception
Note:
In LIN mode the reception of a byte is the same as
In LIN slave mode, the FE bit detects all frame erin SCI mode but the LINSCI has features for hanror which does not correspond to a break.
dling the LIN Header automatically (identifier deIdentifier Detection (LHDM = 1):
tection) or semiautomatically (Synch Break detecThis case is the same as the previous one except
tion) depending on the LIN Header detection
that the LHDF and the RDRF flags are set only afmode. The detection mode is selected by the
ter the entire header has been received (this is
LHDM bit in the SCICR3.
true whether automatic resynchronization is enaAdditionally, an automatic resynchronization feabled or not). This indicates that the LIN Identifier is
ture can be activated to compensate for any clock
available in the SCIDR register.
deviation, for more details please refer to Section
Notes:
11.5.9.5 LIN Baud Rate.
During LIN Synch Field measurement, the SCI
LIN Header Handling by a Slave
state machine is switched off: No characters are
Depending on the LIN Header detection method
transferred to the data register.
the LINSCI will signal the detection of a LIN HeadLIN Slave parity
er after the LIN Synch Break or after the Identifier
has been successfully received.
In LIN Slave mode (LINE and LSLV bits are set)
LIN parity checking can be enabled by setting the
Note:
PCE bit.
It is recommended to combine the Header detecIn this case, the parity bits of the LIN Identifier
tion function with Mute mode. Putting the LINSCI
Field are checked. The identifier character is recin Mute mode allows the detection of Headers only
ognized as the third received character after a
and prevents the reception of any other characbreak character (included):
ters.
This mode can be used to wait for the next Header
parity bits
without being interrupted by the data bytes of the
current message in case this message is not relevant for the application.
Synch Break Detection (LHDM = 0):
When a LIN Synch Break is received:
LIN Synch
LIN Synch
Identifier
– The RDRF bit in the SCISR register is set. It inField
Break
Field
dicates that the content of the shift register is
transferred to the SCIDR register, a value of
0x00 is expected for a Break.
The bits involved are the two MSB positions (7th
and 8th bits if M = 0; 8th and 9th bits if M = 0) of
– The LHDF flag in the SCICR3 register indicates
the identifier character. The check is performed as
that a LIN Synch Break Field has been detected.
specified by the LIN specification:
– An interrupt is generated if the LHIE bit in the
SCICR3 register is set and the I[1:0] bits are
cleared in the CCR register.
parity bits stop bit
start bit
– Then the LIN Synch Field is received and measidentifier bits
ured.
ID0 ID1 ID2 ID3 ID4 ID5 P0 P1
– If automatic resynchronization is enabled (LASE bit = 1), the LIN Synch Field is not transIdentifier Field
ferred to the shift register: There is no need to
clear the RDRF bit.
P0 = ID0 ⊕ ID1 ⊕ ID2 ⊕ ID4
M=0
– If automatic resynchronization is disabled (LAP1 = ID1 ⊕ ID3 ⊕ ID4 ⊕ ID5
SE bit = 0), the LIN Synch Field is received as
a normal character and transferred to the
SCIDR register and RDRF is set.
108/173
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.9.4 LIN Error Detection
edge of the Synch Field. Let us refer to this period deviation as D:
LIN Header Error Flag
If the LHE flag is set, it means that:
The LIN Header Error Flag indicates that an invalid
LIN Header has been detected.
D > 15.625%
When a LIN Header Error occurs:
If LHE flag is not set, it means that:
– The LHE flag is set
D < 16.40625%
– An interrupt is generated if the RIE bit is set and
If 15.625% ≤ D < 16.40625%, then the flag can
the I[1:0] bits are cleared in the CCR register.
be either set or reset depending on the dephasing between the signal on the RDI line and the
If autosynchronization is enabled (LASE bit = 1),
CPU clock.
this can mean that the LIN Synch Field is corrupted, and that the SCI is in a blocked state (LSF bit is
– The second check is based on the measurement
set). The only way to recover is to reset the LSF bit
of each bit time between both edges of the Synch
and then to clear the LHE bit.
Field: this checks that each of these bit times is
large enough compared to the bit time of the cur– The LHE bit is reset by an access to the SCISR
rent baud rate.
register followed by a read of the SCIDR register.
When
LHE is set due to this error then the SCI
LHE/OVR Error Conditions
goes into a blocked state (LSF bit is set).
When Auto Resynchronization is disabled (LASE
LIN Header Time-out Error
bit = 0), the LHE flag detects:
When the LIN Identifier Field Detection Method is
– That the received LIN Synch Field is not equal to
used (by configuring LHDM to 1) or when LIN
55h.
auto-resynchronization is enabled (LASE bit = 1),
– That an overrun occurred (as in standard SCI
the
LINSCI
automatically
monitors
the
mode)
THEADER_MAX condition given by the LIN protocol.
– Furthermore, if LHDM is set it also detects that a
If the entire Header (up to and including the STOP
LIN Header Reception Timeout occurred (only if
bit of the LIN Identifier Field) is not received within
LHDM is set).
the maximum time limit of 57 bit times then a LIN
Header Error is signalled and the LHE bit is set in
When the LIN auto-resynchronization is enabled
the SCISR register.
(LASE bit = 1), the LHE flag detects:
– That the deviation error on the Synch Field is
outside the LIN specification which allows up to
+/-15.5% of period deviation between the slave
and master oscillators.
– A LIN Header Reception Timeout occurred.
If THEADER > THEADER_MAX then the LHE flag is
set. Refer to Figure 60. (only if LHDM is set to 1)
– An overflow during the Synch Field Measurement, which leads to an overflow of the divider
registers. If LHE is set due to this error then the
SCI goes into a blocked state (LSF bit is set).
– That an overrun occurred on Fields other than
the Synch Field (as in standard SCI mode)
Deviation Error on the Synch Field
The deviation error is checking by comparing the
current baud rate (relative to the slave oscillator)
with the received LIN Synch Field (relative to the
master oscillator). Two checks are performed in
parallel:
– The first check is based on a measurement between the first falling edge and the last falling
Figure 60. LIN Header Reception Timeout
LIN Synch
Break
LIN Synch
Field
Identifier
Field
THEADER
The time-out counter is enabled at each break detection. It is stopped in the following conditions:
- A LIN Identifier Field has been received
- An LHE error occurred (other than a timeout error).
- A software reset of LSF bit (transition from high to
low) occurred during the analysis of the LIN Synch
Field or
If LHE bit is set due to this error during the LIN
Synchr Field (if LASE bit = 1) then the SCI goes
into a blocked state (LSF bit is set).
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
If LHE bit is set due to this error during Fields other
LIN Header Length
than LIN Synch Field or if LASE bit is reset then
Even if no timeout occurs on the LIN Header, it is
the current received Header is discarded and the
possible to have access to the effective LIN headSCI searches for a new Break Field.
er Length (THEADER) through the LHL register.
This allows monitoring at software level the
Note on LIN Header Time-out Limit
TFRAME_MAX condition given by the LIN protocol.
According to the LIN specification, the maximum
This feature is only available when LHDM bit = 1
length of a LIN Header which does not cause a
or when LASE bit = 1.
timeout
is
equal
to
1.4 * (34 + 1) = 49
TBIT_MASTER.
Mute Mode and Errors
TBIT_MASTER refers to the master baud rate.
In mute mode when LHDM bit = 1, if an LHE error
occurs during the analysis of the LIN Synch Field
When checking this timeout, the slave node is deor if a LIN Header Time-out occurs then the LHE
synchronized for the reception of the LIN Break
bit is set but it does not wake up from mute mode.
and Synch fields. Consequently, a margin must be
In this case, the current header analysis is discardallowed, taking into account the worst case: This
ed. If needed, the software has to reset LSF bit.
occurs when the LIN identifier lasts exactly 10
Then the SCI searches for a new LIN header.
TBIT_MASTER periods. In this case, the LIN Break
and Synch fields last 49 - 10 = 39TBIT_MASTER peIn mute mode, if a framing error occurs on a data
riods.
(which is not a break), it is discarded and the FE bit
Assuming the slave measures these first 39 bits
is not set.
with a desynchronized clock of 15.5%. This leads
When LHDM bit = 1, any LIN header which reto a maximum allowed Header Length of:
spects the following conditions causes a wake-up
from mute mode:
39 x (1/0.845) TBIT_MASTER + 10TBIT_MASTER
= 56.15 TBIT_SLAVE
- A valid LIN Break Field (at least 11 dominant bits
followed by a recessive bit)
A margin is provided so that the time-out occurs
when the header length is greater than 57
- A valid LIN Synch Field (without deviation error)
TBIT_SLAVE periods. If it is less than or equal to 57
- A LIN Identifier Field without framing error. Note
TBIT_SLAVE periods, then no timeout occurs.
that a LIN parity error on the LIN Identifier Field
does not prevent wake-up from mute mode.
- No LIN Header Time-out should occur during
Header reception.
Figure 61. LIN Synch Field Measurement
TCPU = CPU period
TBR = Baud Rate period
TBR = 16.LP.TCPU
SM = Synch Measurement Register (15 bits)
TBR
LIN Synch Field
LIN Synch Break
Extra
‘1’
Start
Bit Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Stop
Bit
Next
Start
Bit
Measurement = 8.TBR = SM.TCPU
LPR(n+1)
LPR(n)
LPR = TBR / (16.TCPU) = Rounding (SM / 128)
110/173
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.9.5 LIN Baud Rate
mitter are both set to the same value, depending
on the LIN Slave baud rate generator:
Baud rate programming is done by writing a value
in the LPR prescaler or performing an automatic
resynchronization as described below.
fCPU
Automatic Resynchronization
Tx = Rx =
(16*LDIV)
To automatically adjust the baud rate based on
measurement of the LIN Synch Field:
with:
– Write the nominal LIN Prescaler value (usually
LDIV is an unsigned fixed point number. The mandepending on the nominal baud rate) in the
tissa is coded on 8 bits in the LPR register and the
LPFR / LPR registers.
fraction is coded on 4 bits in the LPFR register.
– Set the LASE bit to enable the Auto SynchroniIf LASE bit = 1 then LDIV is automatically updated
zation Unit.
at the end of each LIN Synch Field.
When Auto Synchronization is enabled, after each
Three registers are used internally to manage the
LIN Synch Break, the time duration between five
auto-update of the LIN divider (LDIV):
falling edges on RDI is sampled on fCPU and the
- LDIV_NOM (nominal value written by software at
result of this measurement is stored in an internal
LPR/LPFR addresses)
15-bit register called SM (not user accessible)
(see Figure 61). Then the LDIV value (and its as- LDIV_MEAS (results of the Field Synch meassociated LPFR and LPR registers) are automatiurement)
cally updated at the end of the fifth falling edge.
- LDIV (used to generate the local baud rate)
During LIN Synch field measurement, the SCI
The control and interactions of these registers, exstate machine is stopped and no data is transplained in Figure 62 and Figure 63, depend on the
ferred to the data register.
LDUM bit setting (LIN Divider Update Method).
11.5.9.6 LIN Slave Baud Rate Generation
Note:
In LIN mode, transmission and reception are drivAs explained in Figure 62 and Figure 63, LDIV can
en by the LIN baud rate generator
be updated by two concurrent actions: a transfer
Note: LIN Master mode uses the Extended or
from LDIV_MEAS at the end of the LIN Sync Field
Conventional prescaler register to generate the
and a transfer from LDIV_NOM due to a software
baud rate.
write of LPR. If both operations occur at the same
If LINE bit = 1 and LSLV bit = 1 then the Conventime, the transfer from LDIV_NOM has priority.
tional and Extended Baud Rate Generators are
disabled: the baud rate for the receiver and trans-
111/173
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
Figure 62. LDIV Read / Write Operations When LDUM = 0
Write LPR
Write LPFR
MANT(7:0) FRAC(3:0)
LDIV_NOM
LIN Sync Field
Measurement
Write LPR
MANT(7:0) FRAC(3:0) LDIV_MEAS
Update
at end of
Synch Field
Baud Rate
Generation
MANT(7:0) FRAC(3:0) LDIV
Read LPR
Read LPFR
Figure 63. LDIV Read / Write Operations When LDUM = 1
Write LPR
Write LPFR
MANT(7:0) FRAC(3:0)
LDIV_NOM
LIN Sync Field
Measurement
RDRF = 1
MANT(7:0) FRAC(3:0) LDIV_MEAS
Update
at end of
Synch Field
MANT(7:0) FRAC(3:0) LDIV
Read LPR
112/173
Read LPFR
Baud Rate
Generation
ST7LITE3xF2
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.9.7 LINSCI Clock Tolerance
Consequently, the clock frequency should not vary
more than 6/16 (37.5%) within one bit.
LINSCI Clock Tolerance when unsynchronized
The sampling clock is resynchronized at each start
When LIN slaves are unsynchronized (meaning no
bit, so that when receiving 10 bits (one start bit, 1
characters have been transmitted for a relatively
data byte, 1 stop bit), the clock deviation should
long time), the maximum tolerated deviation of the
not exceed 3.75%.
LINSCI clock is +/-15%.
11.5.9.8 Clock Deviation Causes
If the deviation is within this range then the LIN
Synch Break is detected properly when a new reThe causes which contribute to the total deviation
ception occurs.
are:
This is made possible by the fact that masters
– DTRA: Deviation due to transmitter error.
Note: The transmitter can be either a master
send 13 low bits for the LIN Synch Break, which
or a slave (in case of a slave listening to the
can be interpreted as 11 low bits (13 bits -15% =
response of another slave).
11.05) by a “fast” slave and then considered as a
LIN Synch Break. According to the LIN specifica– DMEAS: Error due to the LIN Synch measuretion, a LIN Synch Break is valid when its duration
ment performed by the receiver.
is greater than tSBRKTS = 10. This means that the
– DQUANT: Error due to the baud rate quantizaLIN Synch Break must last at least 11 low bits.
tion of the receiver.
Note: If the period desynchronization of the slave
–
DREC: Deviation of the local oscillator of the
is +15% (slave too slow), the character “00h”
receiver:
This deviation can occur during the
which represents a sequence of 9 low bits must
reception
of one complete LIN message asnot be interpreted as a break character (9 bits +
suming that the deviation has been compen15% = 10.35). Consequently, a valid LIN Synch
sated at the beginning of the message.
break must last at least 11 low bits.
–
D
TCL: Deviation due to the transmission line
LINSCI Clock Tolerance when Synchronized
(generally due to the transceivers)
When synchronization has been performed, folAll the deviations of the system should be added
lowing reception of a LIN Synch Break, the LINSand compared to the LINSCI clock tolerance:
CI, in LIN mode, has the same clock deviation tolDTRA + DMEAS +DQUANT + DREC + DTCL < 3.75%
erance as in SCI mode, which is explained below:
During reception, each bit is oversampled 16
times. The mean of the 8th, 9th and 10th samples
is considered as the bit value.
Figure 64.Bit Sampling in Reception Mode
RDI LINE
sampled values
Sample
clock
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6/16
7/16
7/16
One bit time
113/173
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.9.9 Error due to LIN Synch measurement
Consequently, at a given CPU frequency, the
maximum possible nominal baud rate (LPRMIN)
The LIN Synch Field is measured over eight bit
should
be chosen with respect to the maximum toltimes.
erated deviation given by the equation:
This measurement is performed using a counter
DTRA + 2 / (128*LDIVMIN) + 1 / (2*16*LDIVMIN)
clocked by the CPU clock. The edge detections
+ DREC + DTCL < 3.75%
are performed using the CPU clock cycle.
This leads to a precision of 2 CPU clock cycles for
the measurement which lasts 16*8*LDIV clock cyExample:
cles.
A nominal baud rate of 20Kbits/s at TCPU = 125ns
Consequently, this error (DMEAS) is equal to:
(8 MHz) leads to LDIVNOM = 25d.
2 / (128*LDIVMIN).
LDIVMIN = 25 - 0.15*25 = 21.25
LDIVMIN corresponds to the minimum LIN prescalDMEAS = 2 / (128*LDIVMIN) * 100 = 0.00073%
er content, leading to the maximum baud rate, takD
QUANT = 1 / (2*16*LDIVMIN) * 100 = 0.0015%
ing into account the maximum deviation of +/-15%.
11.5.9.10 Error due to Baud Rate Quantization
The baud rate can be adjusted in steps of 1 / (16 *
LDIV). The worst case occurs when the “real”
baud rate is in the middle of the step.
This leads to a quantization error (DQUANT) equal
to 1 / (2*16*LDIVMIN).
11.5.9.11 Impact of Clock Deviation on
Maximum Baud Rate
The choice of the nominal baud rate (LDIVNOM)
will influence both the quantization error (DQUANT)
and the measurement error (DMEAS). The worst
case occurs for LDIVMIN.
114/173
LIN Slave systems
For LIN Slave systems (the LINE and LSLV bits
are set), receivers wake up by LIN Synch Break or
LIN Identifier detection (depending on the LHDM
bit).
Hot Plugging Feature for LIN Slave Nodes
In LIN Slave Mute Mode (the LINE, LSLV and
RWU bits are set) it is possible to hot plug to a network during an ongoing communication flow. In
this case the SCI monitors the bus on the RDI line
until 11 consecutive dominant bits have been detected and discards all the other bits received.
ST7LITE3xF2
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.10 LIN Mode Register Description
framing error is detected (if the stop bit is dominant
(0) and at least one of the other bits is recessive
STATUS REGISTER (SCISR)
(1). It is not set when a break occurs, the LHDF bit
Read Only
is used instead as a break flag (if the LHDM
Reset Value: 1100 0000 (C0h)
bit = 0). It is cleared by a software sequence (an
access to the SCISR register followed by a read to
7
0
the SCIDR register).
0: No Framing error
TDRE
TC
RDRF IDLE
LHE
NF
FE
PE
1: Framing error detected
Bits 7:4 = Same function as in SCI mode; please
refer to Section 11.5.8 SCI Mode Register Description.
Bit 3 = LHE LIN Header Error.
During LIN Header this bit signals three error
types:
– The LIN Synch Field is corrupted and the SCI is
blocked in LIN Synch State (LSF bit = 1).
– A timeout occurred during LIN Header reception
– An overrun error was detected on one of the
header field (see OR bit description in Section
11.5.8 SCI Mode Register Description).
An interrupt is generated if RIE = 1 in the SCICR2
register. If blocked in the LIN Synch State, the LSF
bit must first be reset (to exit LIN Synch Field state
and then to be able to clear LHE flag). Then it is
cleared by the following software sequence: An
access to the SCISR register followed by a read to
the SCIDR register.
0: No LIN Header error
1: LIN Header error detected
Note:
Apart from the LIN Header this bit signals an Overrun Error as in SCI mode (see description in Section 11.5.8 SCI Mode Register Description).
Bit 2 = NF Noise flag
In LIN Master mode (LINE bit = 1 and LSLV bit =
0), this bit has the same function as in SCI mode;
please refer to Section 11.5.8 SCI Mode Register
Description.
In LIN Slave mode (LINE bit = 1 and LSLV bit = 1)
this bit has no meaning.
Bit 0 = PE Parity error.
This bit is set by hardware when a LIN parity error
occurs (if the PCE bit is set) in receiver mode. It is
cleared by a software sequence (a read to the status register followed by an access to the SCIDR
data register). An interrupt is generated if PIE = 1
in the SCICR1 register.
0: No LIN parity error
1: LIN Parity error detected
CONTROL REGISTER 1 (SCICR1)
Read/Write
Reset Value: x000 0000 (x0h)
7
R8
0
T8
SCID
M
WAKE
PCE
PS
PIE
Bits 7:3 = Same function as in SCI mode; please
refer to Section 11.5.8 SCI Mode Register Description.
Bit 2 = PCE Parity control enable.
This bit is set and cleared by software. It selects
the hardware parity control for LIN identifier parity
check.
0: Parity control disabled
1: Parity control enabled
When a parity error occurs, the PE bit in the
SCISR register is set.
Bit 1 = Reserved
Bit 0 = Same function as in SCI mode; please refer
to Section 11.5.8 SCI Mode Register Description.
Bit 1 = FE Framing error.
In LIN slave mode, this bit is set only when a real
115/173
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
CONTROL REGISTER 2 (SCICR2)
1: LDIV is updated at the next received character
Read/Write
(when RDRF = 1) after a write to the LPR regisReset Value: 0000 0000 (00h)
ter
Notes:
7
0
- If no write to LPR is performed between the setting of LDUM bit and the reception of the next
TIE
TCIE
RIE
ILIE
TE
RE
RWU SBK
character, LDIV will be updated with the old value.
- After LDUM has been set, it is possible to reset
Bits 7:2 Same function as in SCI mode; please rethe LDUM bit by software. In this case, LDIV can
fer to Section 11.5.8 SCI Mode Register Descripbe modified by writing into LPR / LPFR registers.
tion.
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Notes:
– Mute mode is recommended for detecting only
the Header and avoiding the reception of any
other characters. For more details, please refer
to Section 11.5.9.3 LIN Reception.
– In LIN slave mode, when RDRF is set, the software can not set or clear the RWU bit.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
CONTROL REGISTER 3 (SCICR3)
Read/Write
Reset Value: 0000 0000 (00h)
7
LDUM LINE
LINE
LSLV
Meaning
0
x
LIN mode disabled
0
LIN Master Mode
1
LIN Slave Mode
1
The LIN Master configuration enables:
The capability to send LIN Synch Breaks (13 low
bits) using the SBK bit in the SCICR2 register.
The LIN Slave configuration enables:
– The LIN Slave Baud Rate generator. The LIN
Divider (LDIV) is then represented by the LPR
and LPFR registers. The LPR and LPFR registers are read/write accessible at the address
of the SCIBRR register and the address of the
SCIETPR register
– Management of LIN Headers.
– LIN Synch Break detection (11-bit dominant).
– LIN Wake-Up method (see LHDM bit) instead
of the normal SCI Wake-Up method.
– Inhibition of Break transmission capability
(SBK has no effect)
– LIN Parity Checking (in conjunction with the
PCE bit)
0
LSLV
LASE
LHDM
LHIE LHDF
LSF
Bit 7 = LDUM LIN Divider Update Method.
This bit is set and cleared by software and is also
cleared by hardware (when RDRF = 1). It is only
used in LIN Slave mode. It determines how the LIN
Divider can be updated by software.
0: LDIV is updated as soon as LPR is written (if no
Auto Synchronization update occurs at the
same time).
116/173
Bits 6:5 = LINE, LSLV LIN Mode Enable Bits.
These bits configure the LIN mode:
Bit 4 = LASE LIN Auto Synch Enable.
This bit enables the Auto Synch Unit (ASU). It is
set and cleared by software. It is only usable in LIN
Slave mode.
0: Auto Synch Unit disabled
1: Auto Synch Unit enabled.
Bit 3 = LHDM LIN Header Detection Method
This bit is set and cleared by software. It is only usable in LIN Slave mode. It enables the Header Detection Method. In addition if the RWU bit in the
ST7LITE3xF2
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
SCICR2 register is set, the LHDM bit selects the
Figure 65. LSF Bit Set and Clear
Wake-Up method (replacing the WAKE bit).
11 dominant bits
parity bits
0: LIN Synch Break Detection Method
1: LIN Identifier Field Detection Method
Bit 2 = LHIE LIN Header Interrupt Enable
This bit is set and cleared by software. It is only usable in LIN Slave mode.
0: LIN Header Interrupt is inhibited.
1: An SCI interrupt is generated whenever
LHDF = 1.
Bit 1 = LHDF LIN Header Detection Flag
This bit is set by hardware when a LIN Header is
detected and cleared by a software sequence (an
access to the SCISR register followed by a read of
the SCICR3 register). It is only usable in LIN Slave
mode.
0: No LIN Header detected.
1: LIN Header detected.
Notes: The header detection method depends on
the LHDM bit:
– If LHDM = 0, a header is detected as a LIN
Synch Break.
– If LHDM = 1, a header is detected as a LIN
Identifier, meaning that a LIN Synch Break
Field + a LIN Synch Field + a LIN Identifier
Field have been consecutively received.
Bit 0 = LSF LIN Synch Field State
This bit indicates that the LIN Synch Field is being
analyzed. It is only used in LIN Slave mode. In
Auto Synchronization Mode (LASE bit = 1), when
the SCI is in the LIN Synch Field State it waits or
counts the falling edges on the RDI line.
It is set by hardware as soon as a LIN Synch Break
is detected and cleared by hardware when the LIN
Synch Field analysis is finished (see Figure 65).
This bit can also be cleared by software to exit LIN
Synch State and return to idle mode.
0: The current character is not the LIN Synch Field
1: LIN Synch Field State (LIN Synch Field undergoing analysis)
LSF bit
LIN Synch
Break
LIN Synch
Field
Identifier
Field
LIN DIVIDER REGISTERS
LDIV is coded using the two registers LPR and LPFR. In LIN Slave mode, the LPR register is accessible at the address of the SCIBRR register and
the LPFR register is accessible at the address of
the SCIETPR register.
LIN PRESCALER REGISTER (LPR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
LPR7
LPR6
LPR5
LPR4
LPR3
LPR2
LPR1
LPR0
LPR[7:0] LIN Prescaler (mantissa of LDIV)
These 8 bits define the value of the mantissa of the
LIN Divider (LDIV):
LPR[7:0]
Rounded Mantissa (LDIV)
00h
SCI clock disabled
01h
1
...
...
FEh
254
FFh
255
Caution: LPR and LPFR registers have different
meanings when reading or writing to them. Consequently bit manipulation instructions (BRES or
BSET) should never be used to modify the
LPR[7:0] bits, or the LPFR[3:0] bits.
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
LIN PRESCALER FRACTION REGISTER
will effectively update LDIV and so the clock gen(LPFR)
eration.
Read/Write
2. In LIN Slave mode, if the LPR[7:0] register is
Reset Value: 0000 0000 (00h)
equal to 00h, the transceiver and receiver input
clocks are switched off.
7
0
0
0
0
0
LPFR
3
LPFR
2
LPFR
1
LPFR
0
Bits 7:4 = Reserved.
Bits 3:0 = LPFR[3:0] Fraction of LDIV
These 4 bits define the fraction of the LIN Divider
(LDIV):
LPFR[3:0]
Fraction (LDIV)
0h
0
1h
1/16
...
...
Eh
14/16
Fh
15/16
1. When initializing LDIV, the LPFR register must
be written first. Then, the write to the LPR register
118/173
Examples of LDIV coding:
Example 1: LPR = 27d and LPFR = 12d
This leads to:
Mantissa (LDIV) = 27d
Fraction (LDIV) = 12/16 = 0.75d
Therefore LDIV = 27.75d
Example 2: LDIV = 25.62d
This leads to:
LPFR = rounded(16*0.62d)
= rounded(9.92d) = 10d = Ah
LPR = mantissa (25.620d) = 25d = 1Bh
Example 3: LDIV = 25.99d
This leads to:
LPFR = rounded(16*0.99d)
= rounded(15.84d) = 16d
ST7LITE3xF2
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
LIN HEADER LENGTH REGISTER (LHLR)
LHL[1:0]
Read Only
0h
Reset Value: 0000 0000 (00h).
7
0
LHL7
LHL6
LHL5
LHL4
LHL3
LHL2
LHL1
LHL0
Note: In LIN Slave mode when LASE = 1 or LHDM
= 1, the LHLR register is accessible at the address
of the SCIERPR register.
Otherwise this register is always read as 00h.
Bits 7:0 = LHL[7:0] LIN Header Length.
This is a read-only register, which is updated by
hardware if one of the following conditions occurs:
- After each break detection, it is loaded with
“FFh”.
- If a timeout occurs on THEADER, it is loaded with
00h.
- After every successful LIN Header reception (at
the same time than the setting of LHDF bit), it is
loaded with a value (LHL) which gives access to
the number of bit times of the LIN header length
(THEADER). The coding of this value is explained
below:
LHL Coding:
THEADER_MAX = 57
LHL(7:2) represents the mantissa of (57 - THEADER)
LHL(1:0) represents the fraction (57 - THEADER)
LHL[7:2]
Mantissa
(57 - THEADER)
Mantissa
(THEADER)
0h
0
57
1h
1
56
...
...
...
39h
56
1
3Ah
57
0
3Bh
58
Never Occurs
...
...
...
3Eh
62
Never Occurs
3Fh
63
Initial value
Fraction (57 - THEADER)
0
1h
1/4
2h
1/2
3h
3/4
Example of LHL coding:
Example 1: LHL = 33h = 001100 11b
LHL(7:3) = 1100b = 12d
LHL(1:0) = 11b = 3d
This leads to:
Mantissa (57 - THEADER) = 12d
Fraction (57 - THEADER) = 3/4 = 0.75
Therefore:
(57 - THEADER) = 12.75d
and THEADER = 44.25d
Example 2:
57 - THEADER = 36.21d
LHL(1:0) = rounded(4*0.21d) = 1d
LHL(7:2) = Mantissa (36.21d) = 36d = 24h
Therefore LHL(7:0) = 10010001 = 91h
Example 3:
57 - THEADER = 36.90d
LHL(1:0) = rounded(4*0.90d) = 4d
The carry must be propagated to the matissa:
LHL(7:2) = Mantissa (36.90d) + 1 = 37d =
Therefore LHL(7:0) = 10110000 = A0h
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master/Slave) (Cont’d)
Table 21. LINSCI1 Register Map and Reset Values
Addr.
(Hex.)
Register Name
7
6
5
4
3
2
1
0
40
SCISR
Reset Value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR/LHE
0
NF
0
FE
0
PE
0
41
SCIDR
Reset Value
DR7
-
DR6
-
DR5
-
DR4
-
DR3
-
DR2
-
DR1
-
DR0
-
42
SCIBRR
LPR (LIN Slave Mode)
Reset Value
SCP1
LPR7
0
SCP0
LPR6
0
SCT2
LPR5
0
SCT1
LPR4
0
SCT0
LPR3
0
SCR2
LPR2
0
SCR1
LPR1
0
SCR0
LPR0
0
43
SCICR1
Reset Value
R8
x
T8
0
SCID
0
M
0
WAKE
0
PCE
0
PS
0
PIE
0
44
SCICR2
Reset Value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
45
SCICR3
Reset Value
NP
0
LINE
0
LSLV
0
LASE
0
LHDM
0
LHIE
0
LHDF
0
LSF
0
46
SCIERPR
LHLR (LIN Slave Mode)
Reset Value
ERPR7
LHL7
0
ERPR6
LHL6
0
ERPR5
LHL5
0
ERPR4
LHL4
0
ERPR3
LHL3
0
ERPR2
LHL2
0
ERPR1
LHL1
0
ERPR0
LHL0
0
47
SCITPR
LPFR (LIN Slave Mode)
Reset Value
ETPR7
LDUM
0
ETPR6
0
0
ETPR5
0
0
ETPR4
0
0
ETPR3
LPFR3
0
ETPR2
LPFR2
0
ETPR1
LPFR1
0
ETPR0
LPFR0
0
120/173
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11.6 10-BIT A/D CONVERTER (ADC)
11.6.1 Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This
peripheral has up to 7 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 7 different sources.
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
Data register (DR) which contains the results
Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 66.
■
■
11.6.3 Functional Description
11.6.3.1 Analog Power Supply
VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the VDD and VSS pins.
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
11.6.2 Main Features
■ 10-bit conversion
■ Up to 7 channels with multiplexed input
■ Linear successive approximation
Figure 66. ADC Block Diagram
fCPU
DIV 4
DIV 2
1
fADC
0
0
1
EOC SPEED ADON
SLOW
bit
0
0
CH2
CH1
ADCCSR
CH0
3
AIN0
HOLD CONTROL
RADC
AIN1
ANALOG TO DIGITAL
ANALOG
MUX
CONVERTER
CADC
AINx
ADCDRH
D9
D8
ADCDRL
D7
D6
0
D5
0
D4
0
D3
0
D2
SLOW
0
D1
D0
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10-BIT A/D CONVERTER (ADC) (Cont’d)
11.6.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the result never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (VAIN) is greater than VDDA
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
If the input voltage (VAIN) is lower than VSSA (lowlevel voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
11.6.3.3 A/D Conversion
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the ADCCSR register:
– Select the CS[2:0] bits to assign the analog
channel to convert.
ADC Conversion mode
In the ADCCSR register:
Set the ADON bit to enable the A/D converter and
to start the conversion. From this time on, the ADC
performs a continuous conversion of the selected
channel.
When a conversion is complete:
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH or a write to any bit of the
ADCCSR register resets the EOC bit.
122/173
To read the 10 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRL
3. Read ADCDRH. This clears EOC automatically.
To read only 8 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRH. This clears EOC automatically.
11.6.3.4 Changing the conversion channel
The application can change channels during conversion.
When software modifies the CH[2:0] bits in the
ADCCSR register, the current conversion is
stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel.
11.6.4 Low Power Modes
The A/D converter may be disabled by resetting
the ADON bit. This feature allows reduced power
consumption when no conversion is needed and
between single shot conversions.
Mode
WAIT
HALT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilization time
tSTAB (see Electrical Characteristics)
before accurate conversions can be
performed.
11.6.5 Interrupts
None.
ST7LITE3xF2
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.6.6 Register Description
DATA REGISTER HIGH (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
7
EOC SPEED ADON
0
0
CH2
CH1
0
7
CH0
D9
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit description.
0
D8
D7
D6
D5
D4
D3
D2
Bit 7:0 = D[9:2] MSB of Analog Converted Value
CONTROL AND DATA REGISTER LOW (ADCDRL)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
SLOW
0
D1
D0
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 7:5 = Reserved. Forced by hardware to 0.
Bit 4:3 = Reserved. Must be kept cleared.
Bit 3 = SLOW Slow mode
Bit 4 = Reserved. Forced by hardware to 0.
Bit 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH2
CH1
CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
This bit is set and cleared by software. It is used
together with the SPEED bit to configure the ADC
clock speed as shown on the table below.
fADC
fCPU/2
fCPU
fCPU/4
SLOW SPEED
0
0
1
0
1
x
Bit 2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Analog Converted Value
*The number of channels is device dependent. Refer to
the device pinout description.
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Table 22. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
0034h
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
0
0
0
0
CH2
0
CH1
0
CH0
0
0035h
ADCDRH
Reset Value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
0036h
ADCDRL
Reset Value
0
0
0
0
0
0
0
0
SLOW
0
0
0
D1
0
D0
0
124/173
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12 INSTRUCTION SET
12.1 ST7 ADDRESSING MODES
The ST7 Core features 17 different addressing
modes which can be classified in seven main
groups:
Addressing Mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset
byte,#5
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be subdivided in two submodes called long and short:
– Long addressing mode is more powerful because it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cycles.
– Short addressing mode is less powerful because
it can generally only access page zero (0000h 00FFh range), but the instruction size is more
compact, and faster. All memory to memory instructions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 23. ST7 Addressing Mode Overview
Mode
Syntax
Pointer
Address
(Hex.)
Destination/
Source
Pointer
Size
(Hex.)
Length
(Bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No Offset
Direct
Indexed
ld A,(X)
00..FF
+ 0 (with X register)
+ 1 (with Y register)
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed
Short
Indirect
ld A,($1000,X)
0000..FFFF
ld A,[$10]
00..FF
+2
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect
Indexed
ld A,([$10],X)
00..1FE
00..FF
byte
+2
Long
Indirect
Indexed
ld A,([$10.w],X)
0000..FFFF
00..FF
word
+2
byte
+2
1)
+1
Relative
Direct
jrne loop
PC-128/PC+127
Relative
Indirect
jrne [$10]
PC-128/PC+1271) 00..FF
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
btjt $10,#7,skip
00..FF
Relative
+1
00..FF
byte
+2
+2
Bit
Indirect Relative btjt [$10],#7,skip 00..FF
00..FF
byte
+3
Note:
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
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ST7LITE3xF2
ST7 ADDRESSING MODES (cont’d)
12.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction
Function
NOP
No operation
TRAP
S/W Interrupt
WFI
Wait For Interrupt (Low Power
Mode)
HALT
Halt Oscillator (Lowest Power
Mode)
RET
Subroutine Return
IRET
Interrupt Subroutine Return
SIM
Set Interrupt Mask
RIM
Reset Interrupt Mask
SCF
Set Carry Flag
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
LD
Load
CLR
Clear
PUSH/POP
Push/Pop to/from the stack
INC/DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
MUL
Byte Multiplication
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
12.1.2 Immediate
Immediate instructions have 2 bytes, the first byte
contains the opcode, the second byte contains the
operand value.
Immediate Instruction
Function
LD
Load
CP
Compare
BCP
Bit Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Operations
126/173
12.1.3 Direct
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two submodes:
Direct (Short)
The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF addressing
space.
Direct (Long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
12.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
submodes:
Indexed (No Offset)
There is no offset (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only 1 byte after
the opcode and allows 00 - 1FE addressing space.
Indexed (Long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
12.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two submodes:
Indirect (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
ST7LITE3xF2
ST7 ADDRESSING MODES (cont’d)
12.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the unsigned addition of an index register value (X or Y)
with a pointer value located in memory. The pointer address follows the opcode.
The indirect indexed addressing mode consists of
two submodes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
12.1.7 Relative Mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Indirect Instructions
Function
JRxx
Conditional Jump
CALLR
Call Relative
The relative addressing mode consists of two submodes:
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the address follows the opcode.
Table 24. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Instructions
Function
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Addition/subtraction operations
BCP
Bit Compare
Short Instructions Only
Function
CLR
Clear
INC, DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
BSET, BRES
Bit Operations
BTJT, BTJF
Bit Test and Jump Operations
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
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12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
Increment/Decrement
INC
DEC
Compare and Tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit Operation
BSET
BRES
Conditional Bit Test and Branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and Rotates
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional Jump or Call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Conditional Branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Condition Code Flag modification
SIM
RIM
SCF
RCF
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they precede.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
128/173
RSP
RET
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit or direct relative addressing
mode to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruction using indirect X indexed addressing
mode.
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
12.2.1 Illegal Opcode Reset
In order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implemented. If a code to
be executed does not correspond to any opcode
or prebyte value, a reset is generated. This, combined with the Watchdog, allows the detection and
recovery from an unexpected fault or interference.
Note: A valid prebyte associated with a valid opcode forming an unauthorized combination does
not generate a reset.
ST7LITE3xF2
INSTRUCTION GROUPS (cont’d)
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
ADC
Add with Carry
A=A+M+C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A, Memory
tst (A . M)
A
M
N
Z
BRES
Bit Reset
bres Byte, #3
M
BSET
Bit Set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1
M
C
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1
M
C
CALL
Call subroutine
CALLR
Call subroutine relative
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
CPL
One Complement
A = FFH-A
DEC
Decrement
dec Y
reg, M
HALT
Halt
IRET
Interrupt routine return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
JRIH
Jump if ext. interrupt = 1
0
1
N
Z
C
reg, M
N
Z
1
reg, M
N
Z
N
Z
N
Z
M
0
H
reg, M
I
C
jrf *
JRIL
Jump if ext. interrupt = 0
JRH
Jump if H = 1
H=1?
JRNH
Jump if H = 0
H=0?
JRM
Jump if I = 1
I=1?
JRNM
Jump if I = 0
I=0?
JRMI
Jump if N = 1 (minus)
N=1?
JRPL
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned >=
JRUGT
Jump if (C + Z = 0)
Unsigned >
129/173
ST7LITE3xF2
INSTRUCTION GROUPS (cont’d)
Mnemo
Description
Function/Example
Dst
Src
JRULE
Jump if (C + Z = 1)
Unsigned
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