ST7FLITEU09M6

ST7LITEU05 ST7LITEU09 8-bit MCU with single voltage Flash memory, ADC, timers Datasheet - production data Features • Memories – 2K Bytes single voltage Flash program memory with readout protection, in-circuit and in-application programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55 °C – 128 bytes RAM – 128 bytes data EEPROM. 300K write/erase cycles guaranteed, data retention: 20 years at 55 °C • Clock, reset and supply management – 3-level low voltage supervisor (LVD) and auxiliary voltage detector (AVD) for safe power- on/off procedures – Clock sources: internal trimmable 8-MHz RC oscillator, internal low power, low frequency RC oscillator or external clock – Five Power Saving Modes: Halt, AutoWakeup from Halt, Active-halt, Wait and Slow ) s t( SO8 150” DIP8 DFN8 c u d • A/D converter – 10-bit resolution for 0 to VDD – 5 input channels e t le o r P • Instruction set – 8-bit data manipulation – 63 basic instructions with illegal opcode detection – 17 main addressing modes – 8 x 8 unsigned multiply instruction o s b O ) t(s c u d o r P • Development tools – Full hardware/software development package – Debug module • Interrupt management – 11 interrupt vectors plus TRAP and RESET – 5 external interrupt lines (on 5 vectors) e t e ol • I/O Ports – 5 multifunctional bidirectional I/O lines – 1 additional output line – 6 alternate function lines – 5 high sink outputs s b O • 2 timers – One 8-bit lite timer (LT) with prescaler including: watchdog, 1 realtime base and 1 input capture – One 12-bit auto-reload timer (AT) with output compare function and PWM October 2016 This is information on a product in full production. DocID13474 Rev 3 1/146 www.st.com Contents ST7LITEU05 ST7LITEU09 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ) s t( 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 c u d In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.2 In Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 O ) 4.5.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5.2 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 s ( t c Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 r P e u d o Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4 2/146 o s b 4.6 t e l o s b O e t le 4.4 4.7.1 5 o r P 4.3.1 5.3.1 Read operation (E2LAT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.2 Write operation (E2LAT=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4.1 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4.2 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4.3 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5 Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.6 Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 5.7.1 6 EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . 28 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3.5 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ) s t( c u d 7.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2 Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.4 e t le o s b 7.3.1 Main clock control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . 37 7.3.2 RC control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.3 System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 38 7.3.4 AVD threshold selection register (AVDTHCR) . . . . . . . . . . . . . . . . . . . . 38 O ) u d o r P e let o s b 7.5 s ( t c Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 39 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4.1 8 o r P Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.3.5 O Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.4.3 External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.4.4 Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 41 7.4.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.5.1 Multiplexed IO reset control register 1 (MUXCR1) . . . . . . . . . . . . . . . . 43 7.5.2 Multiplexed IO reset control register 0 (MUXCR0) . . . . . . . . . . . . . . . . 43 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Priority management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Interrupts and low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.1 Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DocID13474 Rev 3 3/146 7 Contents ST7LITEU05 ST7LITEU09 8.3 8.4 9 Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.3.1 External interrupt control register 1 (EICR1) . . . . . . . . . . . . . . . . . . . . . 47 8.3.2 External interrupt control register 2 (EICR2) . . . . . . . . . . . . . . . . . . . . . 47 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.4.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.4.2 Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.4.3 Low-power modes 8.4.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ) s t( Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 c u d 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.4 Active-halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.5 e t le 9.4.1 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 o s b Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 O ) 9.5.1 10 o r P Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 s ( t c I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Ob 11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 r P e let so 10.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.2.4 Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.3 Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.6 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.1 4/146 u d o 10.1 Lite timer (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 Contents 11.1.4 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.1.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.1.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.2 11.3 12 12-bit autoreload timer (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.2.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.2.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 c u d 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 o r P 11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.3.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.3.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 e t le o s b O ) s ( t c Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.1 e t e ol s b O 12.2 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 u d o 12.1.1 Pr Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.1.4 Indexed mode (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.1.5 Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.1.6 Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.1.7 Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 12.2.1 13 ) s t( Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 DocID13474 Rev 3 5/146 7 Contents ST7LITEU05 ST7LITEU09 13.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 13.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 13.4 13.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 13.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 102 13.3.3 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 103 13.3.4 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 ) s t( 13.4.1 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13.4.2 Internal RC oscillator supply characteristics . . . . . . . . . . . . . . . . . . . . 107 13.4.3 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 c u d 13.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 13.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13.7 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 13.8 13.9 e t le o r P 13.7.1 Functional EMS (electro magnetic susceptibility) . . . . . . . . . . . . . . . . 112 13.7.2 EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 113 o s b O ) I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 s ( t c 13.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 u d o Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Pr 13.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 14 s b O e t e ol 15 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 14.1 Device configuration and ordering information . . . . . . . . . . . . . . . . . 133 15.1 6/146 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 15.1.1 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 15.1.2 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 15.2 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 15.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 Contents 15.3.4 Order codes for development and programming tools . . . . . . . . . . . . 138 15.4 16 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O DocID13474 Rev 3 7/146 7 List of tables ST7LITEU05 ST7LITEU09 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data EEPROM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Clock register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CPU clock cycle delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Multiplexed IO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Description of low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 AVD threshold selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 System integrity register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Enabling/disabling Active-halt and Halt modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 DR value and output pin status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Effect of low-power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Description of low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Lite timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Description of low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Effect of low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Configuring the ADC clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Instructions supporting inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . 92 Instructions supporting direct, indexed, indirect and indirect indexed addressing modes . 93 Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ) s t( c u d e t le o s b O ) s ( t c u d o r P e t e l o s b O 8/146 DocID13474 Rev 3 o r P ST7LITEU05 ST7LITEU09 Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. List of tables Operating characteristics with AVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Voltage drop between AVD flag set and LVD reset generation . . . . . . . . . . . . . . . . . . . . 103 Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Internal RC oscillator characteristics (3.3 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Internal RC oscillator supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Auto-wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 EEPROM data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 ADC accuracy with VDD = 3.3 V to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ADC accuracy with VDD = 2.7 V to 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ADC accuracy with VDD = 2.4 V to 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8-lead very thin fine pitch dual flat no-lead package, mechanical data . . . . . . . . . . . . . . 128 8-pin plastic small outline package - 150-mil width, mechanical data. . . . . . . . . . . . . . . . 129 8-pin plastic dual in-line outline package, 300-mil width, mechanical data. . . . . . . . . . . . 130 16-pin plastic dual in-line package, 300-mil width, mechanical data . . . . . . . . . . . . . . . . 131 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Sector 0 size selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 ST7LITEU0 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Development tool order codes for the ST7LITEU0x family. . . . . . . . . . . . . . . . . . . . . . . . 139 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O DocID13474 Rev 3 9/146 9 List of figures ST7LITEU05 ST7LITEU09 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8-pin SO and DIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8-pin DFN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 16-pin package pinout 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 EEPROM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Data EEPROM write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Lite timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 PWM signal example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 fCPU maximum operating frequency versus VDD supply voltage . . . . . . . . . . . . . . . . . . 102 Typical accuracy with RCCR=RCCR0 vs VDD= 2.4-6.0 V and temperature . . . . . . . . . . 105 Typical accuracy with RCCR=RCCR1 vs VDD= 2.4-6.0V and temperature. . . . . . . . . . . 105 Typical IDD in run mode vs. internal clock frequency and VDD . . . . . . . . . . . . . . . . . . . 108 Typical IDD in WFI mode vs. internal clock frequency and VDD . . . . . . . . . . . . . . . . . . . 108 Typical IDD in Slow, Slow-wait and Active-halt mode vs VDD & int ) s t( c u d e t le o s b O ) s ( t c u d o r P e t e l o s b O 10/146 DocID13474 Rev 3 o r P ST7LITEU05 ST7LITEU09 Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. List of figures RC = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Idd vs temp @VDD 5 V & int RC = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Idd vs temp @VDD 5 V & int RC = 4 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Idd vs temp @VDD 5V & int RC = 2 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Typical IPU vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Typical RPU vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Typical VOL at vDD = 2.4 V (standard pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Typical vOL at vDD = 3 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Typical VOL at VDD = 5 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Typical VOL at VDD = 2.4 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Typical VOL at VDD = 3 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Typical VOL at VDD = 5 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Typical VDD-VOH at VDD = 2.4 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Typical VDD-VOH at VDD = 3 V (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Typical VDD-VOH at VDD = 5 V (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Typical VOL vs. VDD (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Typical VDD-VOH vs. VDD (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8-lead very thin fine pitch dual flat no-lead package, package outline . . . . . . . . . . . . . . . 127 8-pin plastic small outline package - 150-mil width, package outline . . . . . . . . . . . . . . . . 128 8-pin plastic dual in-line outline package - 300-mil width, package outline. . . . . . . . . . . . 129 16-pin plastic dual in-line package, 300-mil width, package outline . . . . . . . . . . . . . . . . . 130 ST7LITEU0 FASTROM microcontroller option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O DocID13474 Rev 3 11/146 11 Description 1 ST7LITEU05 ST7LITEU09 Description The ST7ULTRALITE is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7ULTRALITE features Flash memory with byte-by-byte in-circuit programming (ICP) and in-application programming (IAP) capability. Under software control, the ST7ULTRALITE device can be placed in Wait, Slow, or Halt mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all the ST7 microcontrollers feature a true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. ) s t( c u d For easy reference, all parametric data are located in Section 13: Electrical characteristics. o r P The devices feature an on-chip debug module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC protocol reference manual. e t le Figure 1. General block diagram o s b -O AWU RC osc. ) s ( ct Internal Clock 8-MHz RC osc. External clock r P e VSS PA3 / RESET so let Ob 12/146 with watchdog Power supply Port A Control 8-bit core ALU 2 Kbyte Flash memory ADDRESS AND DATA BUS u d o VDD Lite timer LVD RAM (128 Bytes) DocID13474 Rev 3 12-bit autoreload timer 10-bit ADC Data EEPROM (128 Bytes) PA5:0 (6 bits) ST7LITEU05 ST7LITEU09 2 Pin description Pin description Figure 2. 8-pin SO and DIP package pinout VDD 1 PA5 (HS) / AIN4 / CLKIN 2 ei4 PA4 (HS) / AIN3 / MCO 3 ei3 PA3 / RESET 4 1. HS : High sink capability 2. eix : associated external interrupt vector 8 VSS ei0 7 PA0 (HS) / AIN0 / ATPWM / ICCDATA ei1 6 PA1 (HS) / AIN1 / ICCCLK ei2 5 PA2 (HS) / LTIC / AIN2 ) s t( c u d o r P Figure 3. 8-pin DFN package pinout VDD 1 PA5 (HS) / AIN4 / CLKIN 2 )- PA4 (HS) / AIN3 / MCO s ( t c PA3 / RESET 3 4 e t le 8 VSS Ob 7 PA0 (HS) / AIN0 / ATPWM / ICCDATA so ei4 ei0 ei3 ei1 6 PA1 (HS) / AIN1 / ICCCLK ei2 5 PA2 (HS) / LTIC / AIN2 u d o r P e 1. HS : High sink capability 2. eix : associated external interrupt vector t e l o s b O DocID13474 Rev 3 13/146 145 Pin description ST7LITEU05 ST7LITEU09 Figure 4. 16-pin package pinout 1 Reserved 2) 1 1 NC VDD 2 1 VSS RESET 3 ei0 1 PA0 (HS) / AIN0 / ATPWM ICCCLK 4 ei1 1 PA1 (HS) / AIN1 PA5 (HS) / AIN4 / CLKIN 5 ei4 12 NC PA4 (HS) / AIN3 / MCO 6 ei3 11 ICCDATA PA3 7 10 PA2 (HS) / LTIC / AIN2 NC 8 ei2 9 NC e t le 1. For development or tool prototyping purposes only. Package not orderable in production quantities. 2. Must be tied to ground. Note: o s b c u d o r P The differences versus the 8-pin packages are listed below: The ICC signals (ICCCLK and ICCDATA) are mapped on dedicated pins. The RESET signal is mapped on a dedicated pin. It is not multiplexed with PA3. The PA3 pin is always configured as output. Any change on multiplexed IO reset control registers (MUXCR1 and MUXCR2) have no effect on PA3 functionality. Refer to Section 7.5: Register description. O ) s ( t c u d o r P e t e l o s b O 14/146 ) s t( DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 Pin description Legend / abbreviations for Table 1: Type: I = input, O = output, S = supply In/Output level: CT= CMOS 0.3 VDD /0.7 VDD with input trigger Output level: HS = High sink (on N-buffer only) Port and control configuration: • Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog • Output: OD = open drain, PP = push-pull The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state. ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O DocID13474 Rev 3 15/146 145 Pin description ST7LITEU05 ST7LITEU09 Table 1. Device pin description Level Port / Control - I/O CT HS X PA4/AIN3/MCO I/O CT HS X 4 PA3/RESET (2) O 5 PA2/AIN2/LTIC I/O CT 2 PA5/AIN4/CLKIN 3 6 PA1/AIN1/ICCCLK PP wpu - S - - - - ei4 X X X Port A5 Analog input 4 or external clock input ei3 X X X Port A4 Analog input 3 or main clock output X X Port A3 RESET (2) X X Port A2 Analog input 2 or lite timer input capture X I/O CT HS X ei2 X 7 t e l o PA0/AIN0/ATPWM/ I/O CT ICCDATA s b O 8 1. VSS (1) S - ) s t( Main power supply e t e l o s c u d o r P X ei1 X X X Port A1 Analog input 1 or In Circuit Communication Clock Caution: During normal operation this pin must be pulledup, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset puts it back in pull-up HS X ei0 X X X Port A0 Analog input 0 or Auto-Reload Timer PWM or In Circuit Communication Data - - - - - ) s ( ct HS b O - u d o r P e Alternate function OD float - VDD (1) main function (after reset) ana Output - 1 Output int Input Pin Name Type Pin No. Input - - Ground It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground. 2. After a reset, the multiplexed PA3/RESET pin acts as RESET. To configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1. For further details, please refer to Section 7.5 on page 43. 16/146 DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 3 Register & memory map Register & memory map As shown in Figure 5 below, the MCU is capable of addressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM and 1 Kbyte of user program memory. The RAM space includes up to 64 bytes for the stack from 00C0h to 00FFh. The highest address bytes contain the user reset and interrupt vectors. The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (FC00-FFFFh). ) s t( The size of Flash Sector 0 and other device options are configurable by Option byte. c u d Important: The memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device. Figure 5. Memory map 0000h 007Fh 0080h 0FFFh 1000h ete l o s Ob (s) FFFFh 64-Byte Stack 00FFh DEE0h 1) DEE1h du DEE2h Data EEPROM (128 Bytes) DEE3h F800h Flash memory (2K) RCCRH0 RCCRL0 RCCRH1 RCCRL1 2K FLASH PROGRAM MEMORY Reserved F7FFh F800h FFDFh FFE0h Short addressing RAM (zero page) ct Reserved o r P 107Fh 1080h -O 00C0h RAM (128 Bytes) 00FFh 0100h o s b 0080h HW registers (see Table 2) e t le o r P FBFFh FC00h FFFFh 1 Kbyte SECTOR 1 1 Kbyte SECTOR 0 Interrupt & reset vectors (see Table 9) 1. See Section 7.2: Internal RC oscillator adjustment. Note: The DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes containing also the RC calibration values which are read-accessible only in user mode. If all the EEPROM data or Flash space (including the RC calibration values locations) has been erased (after the readout protection removal), then the RC calibration values can still be obtained through these addresses. DocID13474 Rev 3 17/146 145 Register & memory map ST7LITEU05 ST7LITEU09 Table 2. Hardware register map Address Block 0000h 0001h 0002h Port A Register label PADR PADDR PAOR Port A data register Port A data direction register Port A option register 0003h to 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h Lite timer Remarks 00h (2) 08h 02h (3) R/W R/W R/W R/W Read only Auto-reload timer LTCSR LTICR Lite timer control/status register Lite timer input capture register 0xh 00h ATCSR CNTRH CNTRL ATRH ATRL PWMCR PWM0CSR Timer control/status register Counter register high Counter register low Auto-reload register high Auto-reload register low PWM output control register PWM 0 control/status register 00h 00h 00h 00h 00h 00h 00h e t le Reserved area (3 bytes) Auto-reload timer (1) PWM 0 duty cycle register high PWM 0 duty cycle register low ) s t( c u d o r P so DCR0H DCR0L 0019h to 002Eh R/W Read only Read only R/W R/W R/W R/W 00h 00h R/W R/W Flash control/status register 00h R/W Data EEPROM control/status register 00h R/W b O - Reserved area (22 bytes) 0002Fh Flash 00030h EEPROM ct EECSR o r P 0034h 0035h 0036h ADC 0037h ITC 0038h MCC 0039h 003Ah Clock and reset e t e ol (s) FCSR du 0031h to 0033h s b O Reset status (1) Reserved area (8 bytes) 0014h to 0016h 0017h 0018h Register name Reserved area (3 bytes) ADCCSR ADCDRH ADCDRL A/D control status register A/D data register high A/D data register low 00h xxh 00h R/W Read only R/W EICR1 External interrupt control register 1 00h R/W MCCSR Main clock control/status register 00h R/W RCCR SICSR RC oscillator control register System integrity control/status register FFh 0000 0x00b R/W R/W 003Bh to 003Ch Reserved area (2 bytes) 003Dh ITC EICR2 External interrupt control register 2 00h R/W 003Eh AVD AVDTHCR AVD threshold selection register 03h R/W 003Fh Clock controller CKCNTCSR Clock controller control/status register 09h R/W 00h 00h R/W R/W 0040h to 0046h 0047h 0048h 18/146 Reserved area (7 bytes) MuxIOreset MUXCR0 MUXCR1 Mux IO-reset control register 0 Mux IO-reset control register 1 DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 Register & memory map Table 2. Hardware register map (continued) Address Block 0049h 004Ah AWU AWUPR AWUCSR DM (4) DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L 004Bh 004Ch 004Dh 004Eh 004Fh 0050h Reset status (1) Remarks AWU prescaler register AWU control/status register FFh 00h R/W R/W DM control register DM status register DM breakpoint register 1 high DM breakpoint register 1 low DM breakpoint register 2 high DM breakpoint register 2 low 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W Register label Register name 0051h to 007Fh (1) ) s t( Reserved area (47 bytes) c u d 1. Legend: x=undefined, R/W=read/write. 2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 3. The bits associated with unavailable pins must always keep their reset value. 4. For a description of the DM registers, see the ST7 ICC Protocol Reference Manual. e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O DocID13474 Rev 3 19/146 145 Flash program memory ST7LITEU05 ST7LITEU09 4 Flash program memory 4.1 Introduction The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using in-circuit programming or in-application programming. The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 ) s t( c u d Main features o r P • ICP (In-circuit programming) • IAP (In-application programming) • ICT (In-circuit testing) for downloading and executing user application test patterns in RAM • Sector 0 size configurable by option byte • Readout and write protection. e t le o s b 4.3 O Programming modes) s ( t c u d o r P e t e ol The ST7 can be programmed in three different ways: s b O 4.3.1 20/146 • Insertion in a programming tool. In this mode, Flash sectors 0 and 1 and option byte row can be programmed or erased. • In-Circuit Programming. In this mode, Flash sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board. • In-application programming. In this mode, sector 1 can be programmed or erased without removing the device from the application board and while the application is running. In-circuit programming (ICP) ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps: • Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 system memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. • Download ICP driver code in RAM from the ICCDATA pin • Execute ICP driver code in RAM to program the Flash memory DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 Flash program memory Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In Application Programming (IAP) This mode uses an IAP driver program previously programmed in sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.4 ) s t( c u d ICC interface o r P ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are: e t le • RESET: device reset • VSS: device power supply ground • ICCCLK: ICC output serial clock pin (see note 1) • ICCDATA: ICC input serial data pin • CLKIN: main clock input for external source • VDD: application board power supply (see note 3) o s b O ) s ( t c u d o r P e t e l o s b O DocID13474 Rev 3 21/146 145 Flash program memory ST7LITEU05 ST7LITEU09 Figure 6. Typical ICC interface PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE (See Note 3) OPTIONAL (See Note 4) 9 7 5 3 1 10 8 6 4 2 APPLICATION BOARD APPLICATION RESET SOURCE See Note 2 3.3kΩ (See Note 5) APPLICATION POWER SUPPLY See Note 1 and Caution ) s t( APPLICATION I/O c u d ICCDATA RESET ST7 ICCCLK VDD CLKIN See Note 1 o r P 1. If the ICCCLK or ICCDATA pins are only usedas outputs in the application, no signal isolation is necessary. As soon as the programming tool isplugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins arenot available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the programmingtool documentation for recommended resistor values. e t le 2. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5 mA at high level (push pull output or pull-up resistor < 1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor >1 K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. o s b O ) 3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual. s ( t c 4. Pin 9 has to be connected to the CLKIN pin of the ST7 when ICC mode is selected with option bytes disabled (35-pulse ICC entry mode). When option bytes are enabled (38-pulse ICC entry mode), the internal RC clock is forced, regardless of the selection in the option byte. u d o 5. A serial resistor must be connected to ICC connector pin 6 in order to prevent contention on PA3/RESET pin. Contention may occur if a tool forces a state on RESET pin while PA3 pin forces the opposite state in output mode. The resistor value is defined to limit the current below 2 mA at 5 V. If PA3 is used as output push-pull, then the application must be switched off to allow the tool to take control of the RESET pin (PA3). To allow the programming tool to drive the RESET pin below VIL, special care must also be taken when a pull-up is placed on PA3 for application reasons. r P e t e l o Caution: s b O 22/146 During normal operation, ICCCLK pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset puts it back in input pull-up. DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 4.5 Flash program memory Memory protection There are two different types of memory protection: readout protection and write/erase protection which can be applied individually. 4.5.1 Readout protection Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Program memory is protected. In Flash devices, this protection is removed by reprogramming the option. In this case, program memory is automatically erased, and the device can be reprogrammed. ) s t( Readout protection selection depends on the device type: 4.5.2 c u d • In Flash devices it is enabled and removed through the FMP_R bit in the option byte. • In ROM devices it is enabled by mask option specified in the option list. Flash write/erase protection e t le o r P Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. o s b Warning: O ) Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable. s ( t c u d o Write/erase protection is enabled through the FMP_W bit in the option byte. 4.6 r P e Related documentation s b O t e l o For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. DocID13474 Rev 3 23/146 145 Flash program memory ST7LITEU05 ST7LITEU09 4.7 Register description 4.7.1 Flash control/status register (FCSR) This register controls the XFlash erasing and programming using ICP, IAP or other programming methods. 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh) When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically. ) s t( Reset value: 000 0000 (00h) uc 7 0 0 0 0 0 r P e Read/write Address (Hex.) 002Fh Register label 7 6 5 FCSR Reset Value 0 0 0 ) (s 4 0 t c u d o r P e t e l o s b O 24/146 t e l o s b O DocID13474 Rev 3 od OPT LAT 0 PGM 3 2 1 0 0 OPT 0 LAT 0 PGM 0 ST7LITEU05 ST7LITEU09 Data EEPROM 5 Data EEPROM 5.1 Introduction The electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 5.2 Main features ) s t( • Up to 32 bytes programmed in the same cycle • EEPROM mono-voltage (charge pump) • Chained erase and programming cycles • Internal control of the global programming cycle duration • Wait mode management • Readout protection e t le c u d o r P Figure 7. EEPROM block diagram so EECSR 0 0 0 u d o DECODER Ob 5.3 0 ) s ( ct ADDRESS r P e let so 0 4 b O 0 HIGH VOLTAGE PUMP E2LAT E2PGM EEPROM ROW MEMORY MATRIX DECODER (1 ROW = 32 x 8 BITS) 128 4 128 DATA 32 x 8 BITS MULTIPLEXER DATA LATCHES 4 ADDRESS BUS DATA BUS Memory access The data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 8 describes these different memory access modes. DocID13474 Rev 3 25/146 145 Data EEPROM 5.3.1 ST7LITEU05 ST7LITEU09 Read operation (E2LAT=0) The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared. On this device, data EEPROM can also be used to execute machine code. Take care not to write to the data EEPROM while executing from it. This would result in an unexpected code being executed. 5.3.2 Write operation (E2LAT=1) To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the 32 data latches according to its address. ) s t( When PGM bit is set by the software, all the previous bytes written in the data latches (up to 32) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five Least Significant Bits of the address can change. c u d e t le o r P At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously. Note: Care should be taken during the programming cycle. Writing to the same memory location over-programs the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit. It is not possible to read the latched data. This note is ilustrated by the Figure 10. o s b O ) s ( t c Figure 8. Data EEPROM programming flowchart du ete l o s o r P READ MODE E2LAT=0 E2PGM=0 READ BYTES IN EEPROM AREA Ob WRITE MODE E2LAT=1 E2PGM=0 WRITE UP TO 32 BYTES IN EEPROM AREA (with the same 11 MSB of the address) START PROGRAMMING CYCLE E2LAT=1 E2PGM=1 (set by software) 0 CLEARED BY HARDWARE 26/146 DocID13474 Rev 3 E2LAT 1 ST7LITEU05 ST7LITEU09 Data EEPROM Figure 9. Data EEPROM write operation ROW DEFINITION  Row / byte  0 1 2 3 ... 30 31 Physical address 0 - - - - - - - 00h...1Fh 1 - - - - - - - 20h...3Fh ... - - - - - - - - N - - - - - - - Nx20h...Nx20h+1Fh Read operation impossible Byte 1 E2LAT bit Byte 2 Byte 32 ) s t( Read operation possible c u d Programming cycle PHASE 1 PHASE 2 Writing data latches Waiting E2PGM and E2LAT to fall Set by USER application e t le E2PGM bit o r P Cleared by hardware o s b 1. If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed. 5.4 Power saving modes 5.4.1 Wait mode O ) s ( t c u d o The data EEPROM can enter Wait mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-Halt mode.The DATA EEPROM immediately enters this mode if there is no programming in progress, otherwise the data EEPROM finishes the cycle and then enter Wait mode. t e l o 5.4.2 bs O 5.4.3 r P e Active-halt mode Refer to Wait mode. Halt mode The data EEPROM immediately enters Halt mode if the microcontroller executes the HALT instruction. Therefore the EEPROM stops the function in progress, and data may be corrupted. 5.5 Access error handling If a read access occurs while E2LAT=1, then the data bus is not driven. If a write access occurs while E2LAT=0, then the data on the bus is not latched. If a programming cycle is interrupted (by a Reset action), the integrity of the data in memory is not guaranteed. DocID13474 Rev 3 27/146 145 Data EEPROM 5.6 ST7LITEU05 ST7LITEU09 Data EEPROM readout protection The readout protection is enabled through an option bit (see option byte section). When this option is selected, the programs and data stored in the EEPROM memory are protected against readout (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the option byte, the entire Program memory and EEPROM is first automatically erased. Note: Both program memory and data EEPROM are protected using the same option bit. Figure 10. Data EEPROM programming cycle Read operation possible ) s t( Read operation not possible Internal programming voltage ERASE CYCLE c u d WRITE CYCLE WRITE OF DATA LATCHES tPROG e t le o r P LAT PGM o s b 5.7 Register description 5.7.1 EEPROM control/status register (EECSR) O ) s ( t c Address: 0030h u d o Reset value: 0000 0000 (00h) 7 ete 0 ol bs O Pr 0 0 0 0 0 0 E2LAT Read/write Bits 7:2 = Reserved, forced by hardware to 0 Bit 1 = E2LAT Latch access transfer bit: This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared 0: Read mode 1: Write mode Bit 0 = E2PGM Programming control and status bit This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware. 0: Programming finished or not yet started 1: Programming cycle is in progress Note: 28/146 E2PGM If the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed. DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 Data EEPROM Table 3. Data EEPROM register map and reset values Address (Hex.) 0030h Register Label EECSR Reset Value 7 6 5 4 3 2 1 0 0 0 0 0 0 0 E2LAT 0 E2PGM 0 ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O DocID13474 Rev 3 29/146 145 Central processing unit ST7LITEU05 ST7LITEU09 6 Central processing unit 6.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation. 6.2 6.3 Main features • 63 basic instructions • Fast 8-bit by 8-bit multiply • 17 main addressing modes • Two 8-bit index registers • 16-bit stack pointer • Low-power modes • Maskable hardware interrupts • Non-maskable software interrupt ) s t( c u d e t le o r P o s b CPU registers O ) The six CPU registers shown in Figure 11 are not present in the memory mapping and are accessed by specific instructions. 6.3.1 Accumulator (A) s ( t c u d o The accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 6.3.2 t e l o s b O 6.3.3 r P e Index registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The cross-assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is the LSB) and PCH (Program Counter High which is the MSB). 30/146 DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 Central processing unit Figure 11. CPU registers 7 0 ACCUMULATOR RESET VALUE = XXh 7 0 X INDEX REGISTER RESET VALUE = XXh 7 0 Y INDEX REGISTER RESET VALUE = XXh PCH 15 PCL 8 7 0 PROGRAM COUNTER ) s t( RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 1 1 1 H I N Z C c u d CONDITION CODE REGISTER RESET VALUE = 1 1 1 X 1 X X X 15 8 7 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS 1. 6.3.4 e t le X = undefined value o r P o s b Condition code register (CC) The 8-bit condition code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. O ) s ( t c Reset value: 111x 1xxx u d o 7 1 e t e ol Pr 1 1 0 H I N Z C Read/write These bits can be individually tested and/or controlled by specific instructions. s b O Bit 4 = H Half carry bit This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask bit This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. DocID13474 Rev 3 31/146 145 Central processing unit Note: ST7LITEU05 ST7LITEU09 Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative bit This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). ) s t( This bit is accessed by the JRMI and JRPL instructions. c u d Bit 1 = Z Zero bit This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. e t le o r P This bit is accessed by the JREQ and JRNE test instructions. o s b Bit 0 = C Carry/borrow bit This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. O ) 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. s ( t c This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. u d o 6.3.5 Stack pointer (SP) r P e Reset Value: 00 FFh let o s b O 15 0 8 0 0 0 0 0 0 0 Read/write 7 1 0 1 SP5 SP4 SP3 SP2 SP1 SP0 Read/write The stack pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 12). Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address. 32/146 DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 Central processing unit The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 12. • When an interrupt is received, the SP is decremented and the context is pushed on the stack. • On return from interrupt, the SP is incremented and the context is popped from the stack. ) s t( c u d A subroutine call occupies two locations and an interrupt five locations in the stack area. o r P Figure 12. Stack manipulation example CALL Subroutine e t e PUSH Y Interrupt event POP Y RET or RSP IRET l o s @ 00C0h b O - SP ) s ( t SP od SP Pr @ 00FFh e t e ol bs 1. uc CC A Y CC A SP CC A X X X PCH PCH PCH SP PCL PCL PCL PCH PCH PCH PCH PCH PCL PCL PCL PCL PCL SP Stack higher address = 00FFh Stack lower address = 00C0h O DocID13474 Rev 3 33/146 145 Supply, reset and clock management 7 ST7LITEU05 ST7LITEU09 Supply, reset and clock management The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. 7.1 Main features • Clock management – 8 MHz internal RC oscillator (enabled by option byte) – External clock input (enabled by option byte) • Reset sequence manager (RSM) • System integrity management (SI) ) s t( c u d o r P – Main supply low voltage detection (LVD) with reset generation (enabled by option byte) – Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main supply e t le o s b 7.2 Internal RC oscillator adjustment O ) The ST7 contains an internal RC oscillator with a specific accuracy for a given device, temperature and voltage. It can be selected as the start up clock through the CKSEL[1:0] option bits (see Section 15.1: Option bytes). It must be calibrated to obtain the frequency required in the application. This is done by software writing a 10-bit calibration value in the RCCR (RC Control Register) and in the bits [6:5] in the SICSR (SI control status register). s ( t c u d o Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in Flash memory for 3.3 and 5 V VDD supply voltages at 25 °C, as shown in the following table. r P e t e l o s b O Table 4. Predefined RC oscillator calibration values RCCR Conditions ST7LITEU05/ST7LITEU09 address RCCRH0 VDD = 5 V TA= 25 °C fRC = 8 MHz DEE0h (1) (CR[9:2] bits) VDD = 3.3 V TA= 25 °C fRC = 8 MHz DEE2h (1) (CR[9:2] bits) RCCRL0 RCCRH1 RCCRL1 DEE1h (1) (CR[1:0] bits) DEE3h (1) (CR[1:0] bits) 1. DEE0h, DEE1h, DEE2h and DEE3h are located in a reserved area but are special bytes containing also the RC calibration values which are read-accessible only in user mode. If all the Flash space (including the RC calibration value locations) has been erased (after the readout protection removal), then the RC calibration values can still be obtained through these two addresses. 34/146 DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 Note: Supply, reset and clock management In ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. Refer to note 5 in Section 4.4: ICC interface for further details. Section 13: Electrical characteristics for more information on the frequency and accuracy of the RC oscillator. To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN2326 for information on how to calibrate the RC frequency using an external reference signal. ) s t( The ST7ULTRALITE also contains an Auto Wake Up RC oscillator. This RC oscillator should be enabled to enter Auto Wake-up from Halt mode. c u d The Auto-wakeup RC oscillator can also be configured as the startup clock through the CKSEL[1:0] option bits (see Section 15.1: Option bytes). o r P This is recommended for applications where very low power-consumption is required. e t le Switching from one startup clock to another can be done in run mode as follows (see Figure 13): o s b Case 1: Switching from internal RC to AWU: 1. Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator 2. The RC_FLAG is cleared and the clock output is at 1. 3. Wait 3 AWU RC cycles till the AWU_FLAG is set 4. The switch to the AWU clock is made at the positive edge of the AWU clock signal 5. Once the switch is made, the internal RC is stopped O ) s ( t c u d o Case 2: Switching from AWU RC to internal RC: r P e 1. 2. t e l o 3. s b O Note: Reset the RC/AWU bit to enable the internal RC oscillator Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is running on internal RC clock. Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC cycles) 4. The switch to the internal RC clock is made at the positive edge of the internal RC clock signal 5. Once the switch is made, the AWU RC is stopped 1 When the internal RC is not selected, it is stopped so as to save power consumption. 2 When the internal RC is selected, the AWU RC is turned on by hardware when entering Auto Wake-Up from Halt mode. 3 When the external clock is selected, the AWU RC oscillator is always on. DocID13474 Rev 3 35/146 145 Supply, reset and clock management ST7LITEU05 ST7LITEU09 Figure 13. Clock switching Internal RC Set RC/AWU Poll AWU_FLAG until set AWU RC Reset RC/AWU Poll RC_FLAG until set AWU RC Internal RC Figure 14. Clock management block diagram CR9 CR8 CR7 CR6 CR5 CR1 CR4 CR3 CR2 CK1 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz t(s CLKIN so e t e l Ob c u d o r P fCLKIN RC OSC )- CK0 AWU RC e t le so Ob Clock Controller fOSC AWU CK Ext Clock AVDTHCR CKSEL[1:0] Option bits 33kHz /2 DIVIDER 13-BIT LITE TIMER COUNTER fOSC fOSC o r P RC/AWU CKCNTCSR 8 MHz(fRC) CK2 c u d SICSR CR0 Tunable internal RC Oscillator Prescaler ) s t( RCCR /32 DIVIDER fOSC/32 0 1 fLTIMER (1ms timebase @ 8 MHz fOSC) fCPU TO CPU AND PERIPHERALS MCO SMS MCCSR MCO 36/146 DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 Supply, reset and clock management 7.3 Register description 7.3.1 Main clock control/status register (MCCSR) Reset value: 0000 0000 (00h) 7 0 0 0 0 0 0 0 MCO SMS Read/write Bits 7:2 = Reserved, must be kept cleared. ) s t( Bit 1 = MCO Main Clock Out enable bit c u d This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock. o r P 0: MCO clock disabled, I/O port free for general purpose I/O. 1: MCO clock enabled. e t le Bit 0 = SMS Slow mode selection bit This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock fOSC or fOSC/32. o s b 0: Normal mode (fCPU = fOSC) O ) 1: Slow mode (fCPU = fOSC/32) 7.3.2 RC control register (RCCR) s ( t c Reset value: 1111 1111 (FFh) 7 Pr CR9 ete l o s Ob u d o CR8 CR7 0 CR6 CR5 CR4 CR3 CR2 Read/write Bits 7:0 = CR[9:2] RC oscillator frequency adjustment bits These bits, as well as CR[1:0] bits in the SICSR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy. The application can store the correct value for each voltage range in Flash memory and write it to this register at start-up. 00h = maximum available frequency FFh = lowest available frequency Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h. DocID13474 Rev 3 37/146 145 Supply, reset and clock management 7.3.3 ST7LITEU05 ST7LITEU09 System integrity (SI) control/status register (SICSR) Reset Value: 0000 0x00 (0xh) 7 0 0 CR1 CR0 0 0 LVDRF AVDF AVDIE Read/write Bit 7 = Reserved, must be kept cleared. Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy. Refer to Section 7.2: Internal RC oscillator adjustment. ) s t( c u d Bits 4:3 = Reserved, must be kept cleared. Bits 2:0 = System Integrity bits. Refer to Section 8.4: System integrity management (SI). 7.3.4 AVD threshold selection register (AVDTHCR) e t le Reset Value: 0000 0011 (03h) 7 CK2 CK1 CK0 o s b 0 0 o r P 0 0 AVD1 AVD0 -O Read/write ) s ( ct Bits 7:5 = CK[2:0] internal RC prescaler selection These bits are set by software and cleared by hardware after a reset. These bits select the prescaler of the internal RC oscillator. See Figure 14 and the following table and note: u d o r P e t e l o bs O Table 5. Internal RC prescaler selection bits CK2 CK1 CK0 fOSC 0 0 1 fRC/2 0 1 0 fRC/4 0 1 1 fRC/8 1 0 0 fRC/16 others Note: fRC If the internal RC is used with a supply operating range below 3.3V, a division ratio of at least 2 must be enabled in the RC prescaler. Bits 4:2 = Reserved, must be kept cleared. Bits 1:0 = AVD threshold selection bits. Refer to Section 8.4: System integrity management (SI). 38/146 DocID13474 Rev 3 ST7LITEU05 ST7LITEU09 7.3.5 Supply, reset and clock management Clock controller control/status register (CKCNTCSR) Reset Value: 0000 1001 (09h) 7 0 0 0 0 0 AWU_FLAG RC_FLAG 0 RC/AWU Read/write Bits 7:4 = Reserved, must be kept cleared. Bit 3 = AWU_FLAG AWU selection bit This bit is set and cleared by hardware. ) s t( 0: No switch from AWU to RC requested 1: AWU clock activated and temporization completed c u d Bit 2 = RC_FLAG RC selection bit This bit is set and cleared by hardware. 0: No switch from RC to AWU requested e t le 1: RC clock activated and temporization completed Bit 1 = Reserved, must be kept cleared. o s b Bit 0 = RC/AWU RC/AWU selection bit 0: RC enabled o r P O ) 1: AWU enabled (default value) s ( t c 6 5 4 3 2 1 0 0 0 0 0 0 MCO 0 SMS 0 CR9 1 CR8 1 CR7 1 CR6 1 CR5 1 CR4 1 CR3 1 CR2 1 SICSR Reset Value 0 CR1 0 CR0 0 0 0 LVDRF x AVDF 0 AVDIE 0 003Eh AVDTHCR Reset Value CK2 0 CK1 0 CK0 0 0 0 0 AVD1 1 AVD2 1 003Fh CKCNTCSR Reset Value 0 0 0 0 AWU_FLAG 1 RC_FLAG 0 0 RC/AWU 1 Table 6. Clock register map and reset values Address Register label 7 MCCSR Reset Value 0 RCCR Reset Value 003Ah (Hex.) 0038h e t e l 0039h O o s b du o r P DocID13474 Rev 3 39/146 145 Supply, reset and clock management ST7LITEU05 ST7LITEU09 7.4 Reset sequence manager (RSM) 7.4.1 Introduction The reset sequence manager includes three Reset sources as shown in Figure 16: Note: • External RESET source pulse • Internal LVD Reset (low voltage detection) • Internal WATCHDOG Reset A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Figure 16. ) s t( These sources act on the RESET pin and it is always kept low during the delay phase. The Reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. c u d The basic Reset sequence consists of 3 phases as shown in Figure 15: Caution: • Active phase depending on the Reset source • 256 or 512 CPU clock cycle delay (see table below) • Reset vector fetch e t le o r P When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior. o s b O ) The 256 or 512 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte after a reset or depending on the clock source selected before entering Halt mode or AWU from Halt mode. Refer to Table 7. s ( t c u d o The Reset vector fetch phase duration is 2 clock cycles. so let Ob r P e Table 7. CPU clock cycle delay Clock source CPU clock cycle delay Internal RC oscillator 512 External clock (connected to CLKIN pin) AWURC 256 Figure 15. Reset sequence phases RESET Active Phase 40/146 INTERNAL RESET 256 OR 512 CLOCK CYCLES DocID13474 Rev 3 FETCH VECTOR ST7LITEU05 ST7LITEU09 Supply, reset and clock management Figure 16. Reset block diagram VDD RON RESET INTERNAL RESET FILTER PULSE GENERATOR WATCHDOG RESET ILLEGAL OPCODE RESET 1) LVD RESET ) s t( c u d 1. See Section 12.2.1: Illegal opcode reset for more details on illegal opcode reset conditions. 7.4.2 Asynchronous external RESET pin e t le o r P The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. o s b O ) A Reset signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 17). This detection is asynchronous and therefore the MCU can enter reset state even in Halt mode. s ( t c The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 7.4.3 u d o r P e External power-on reset t e l o s b O 7.4.4 If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fCLKIN frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. Internal low voltage detector (LVD) reset Two different Reset sequences caused by the internal LVD circuitry can be distinguished: • Power-on reset • Voltage drop reset The device RESET pin acts as an output that is pulled low when VDD - - - - - - - JRULE Jump if (C + Z = 1) Unsigned