ST7FOXA0
8-bit MCU with single voltage Flash memory,
ADC, timers
Features
■
■
Memories
– 2 Kbytes single voltage extended Flash
(XFlash) Program memory with
Read-Out Protection
In-Circuit Programming and In-Application
programming (ICP and IAP)
Endurance: 1K write/erase cycles
guaranteed
Data retention: 20 years at 55 °C
– 128 bytes RAM
Clock, Reset and Supply Management
– Low voltage supervisor (LVD) for safe
power-on/off
– Clock sources: Internal trimmable 8 MHz
RC oscillator, auto wakeup internal low
power - low frequency oscillator or external
clock
– External reset source and watchdog reset
– Five power saving modes: Halt, Active-Halt,
Auto Wakeup from Halt, Wait and Slow
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SO8
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Table 1.
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A/D converter: 5 input channels
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Interrupt management
– 11 interrupt vectors plus TRAP and RESET
■
Instruction set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode
detection
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
■
Development tools
– Full HW/SW development package
– DM (Debug Module)
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2 timers
– One 8-bit Lite timer with prescaler
including: watchdog,
1 real time base and 1 input capture
– Single 12-bit Auto-reload timer with 1 PWM
output, input capture, output compare,
dead-time generation and enhanced one
pulse mode functions
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I/O Ports
– 5 multifunctional bidirectional I/Os
– 1 additional output line
– 5 high sink outputs
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DIP8
Device summary
Features
ST7FOXA0
Program memory - bytes
2K
RAM (stack) - bytes
128 (64)
Timers
1 x 8-bit timer, 1 x 12-bit AT (1 PWM)
ADC
1 x 10-bit
Packages
SO8 150”, DIP8 300”
February 2008
Rev 3
1/123
www.st.com
1
Contents
ST7FOXA0
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Register and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Flash programmable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3
Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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In-Circuit Programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.2
In Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5
Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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4.5.1
Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5.2
Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7
Description of Flash Control/Status register (FCSR) . . . . . . . . . . . . . . . . 20
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5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2
let
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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5.3.1
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3.2
Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3.3
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3.4
Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3.5
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1
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Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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4.1
RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.1
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.2
Customized RC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.3
Auto wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ST7FOXA0
Contents
6.2
6.3
6.4
Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.1
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.2
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.2
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.3
External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.4
Internal Low Voltage Detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.5
Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.6
Multiplexed IO reset control register 1 (MUXCR1) . . . . . . . . . . . . . . . . . 34
6.3.7
Multiplexed IO reset control register 0 (MUXCR0) . . . . . . . . . . . . . . . . . 34
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System Integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.1
6.5
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Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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6.5.1
RC calibration control/status register (RCC_CSR) . . . . . . . . . . . . . . . . 37
6.5.2
Main Clock Control/Status Register (MCCSR) . . . . . . . . . . . . . . . . . . . 37
6.5.3
RC Control Register High (RCCRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5.4
RC Control Register Low (RCCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.5.5
Prescaler register (PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.5.6
Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 40
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Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.4
Active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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7.5
7.4.1
Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.4.2
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Auto wakeup from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.5.1
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.5.2
AWUFH Control/Status Register (AWUCSR) . . . . . . . . . . . . . . . . . . . . 51
7.5.3
AWUFH Prescaler Register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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Contents
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ST7FOXA0
8.2.1
Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.2.2
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.2.3
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.2.4
Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.3
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.4
Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.5
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.7
Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.1
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.1.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.1.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1.4
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1.5
Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1.6
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1.7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1.8
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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9.3
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12-bit Autoreload Timer (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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9.1.1
9.2.1
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Lite Timer (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.2.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.2.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.2.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.2.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.3.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.3.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.3.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.3.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.3.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ST7FOXA0
Contents
10.1
10.2
ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.1.1
Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.1.2
Immediate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.1.3
Direct modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.1.4
Indexed modes (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . 80
10.1.5
Indirect modes (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.1.6
Indirect indexed modes (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.1.7
Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.2.1
11
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Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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11.1
Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.2
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.3
Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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11.3.1
External Interrupt Control Register 1 (EICR1) . . . . . . . . . . . . . . . . . . . . 90
11.3.2
External Interrupt Control Register 2 (EICR2) . . . . . . . . . . . . . . . . . . . . 91
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Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.1
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Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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12.1.2
12.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.4
12.5
12.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.3.2
Operating conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . 95
12.3.3
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.4.1
Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.4.2
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.5.1
12.6
Auto wakeup from Halt oscillator (AWU) . . . . . . . . . . . . . . . . . . . . . . . . 98
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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ST7FOXA0
12.7
12.8
12.9
EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 100
12.7.1
Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 100
12.7.2
EMI (Electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.7.3
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 102
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.8.1
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.8.2
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
12.9.1
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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12.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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Device configuration and ordering information . . . . . . . . . . . . . . . . . 110
13.1
13.2
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Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.1.1
ST7FOXA0 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.1.2
ST7FOXA0 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
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Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
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ST7FOX failure analysis service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.3
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.3.2
Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.3.3
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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13.4
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Order codes for development and programming tools . . . . . . . . . . . . . 113
ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
14.1
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
ST7FOXA0
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device pin description (8-pin package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ST7FOXA0 Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CPU clock delay during Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Multiplexed IO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Clock register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Enabling/disabling active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
AWU register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DR Value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
ST7FOXA0 I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Effect on Lite timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Lite timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Effect of low power modes on the A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Channel selection using CH[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Configuring the ADC clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ADC register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Instructions supporting inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . 80
Instructions supporting direct, indexed, indirect and indirect indexed addressing modes . 81
Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ST7FOXA0 interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Interrupt register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
AWU from Halt characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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7/123
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
ST7FOXA0
RAM and hardware registers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Flash program memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
ST7FOXA0 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ADC accuracy with VDD = 4.5 to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Configuration of sector size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Development tool order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8-pin plastic small outline package, 150-mil width, mechanical data . . . . . . . . . . . . . . . . 119
8-pin plastic dual in-line outline package - 300-mil width, mechanical data . . . . . . . . . . . 120
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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ST7FOXA0
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ST7FOXA0 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical ICC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ST7FOXA0 stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
RCCRH_USER and RCCRL_USER programming flowchart . . . . . . . . . . . . . . . . . . . . . . . 26
RC user calibration programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ST7FOXA0 clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ST7FOXA0 reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
AWUF halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Lite timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PWM Signal example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
ST7FOXA0 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8-pin plastic small outline package - 150-mil width, package outline . . . . . . . . . . . . . . . . 119
8-pin plastic dual in-line outline package - 300-mil width, package outline. . . . . . . . . . . . 120
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Description
1
ST7FOXA0
Description
The ST7FOXA0 is a member of the ST7 microcontroller family. All ST7 devices are based
on a common industry-standard 8-bit core, featuring an enhanced instruction set.
The device is positioned at the entry level of the 8-bit microcontroller range providing an
attractive cost while at the same time embedding the most advanced features.
The ST7FOXA0 features Flash memory with byte-by-byte In-Circuit Programming (ICP) and
In-Application Programming (IAP) capability.
Under software control, the ST7FOXA0 device can be placed in Wait, Slow, or Halt mode,
reducing power consumption when the application is in idle or standby state.
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The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
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The ST7FOXA0 features an on-chip Debug Module (DM) to support In-Circuit Debugging
(ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference
Manual.
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Figure 1.
General block diagram
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External
Clock
bs
O
AWU RC
Osc
8-MHz RC
Osc
Lite timer
with watchdog
Port A
LVD
VDD
VSS
PA3 / RESET
Power
Supply
Control
8-bit core
ALU
2 K Byte
Flash
Memory
RAM
(128 Bytes)
10/123
Internal
Clock
ADDRESS AND DATA BUS
ol
ete
Pr
s
b
O
12-bit autoreload timer
10-bit ADC
PA5:0
(6 bits)
ST7FOXA0
2
Pin description
Pin description
Figure 2.
8-pin package pinout
VDD
1
8
VSS
PA5 (HS) / AIN4 / CLKIN
2 ei4
ei0 7
PA0 (HS) / AIN0 / ATPWM / ICCDATA
PA4 (HS) / AIN3 / MCO
3 ei3
ei1 6
PA1 (HS) / AIN1 / ICCCLK
4
ei2 5
PA2 (HS) / LTIC / AIN2
PA3 / RESET
)
s
(
ct
u
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(HS) : High sink capability
eix : associated external interrupt vector
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11/123
Pin description
ST7FOXA0
Legend / Abbreviations for Table 2:
Type: I = input, O = output, S = supply
In/Output level:CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level: HS = 20 mA high sink (on N-buffer only)
Port and control configuration:
Note:
●
Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
●
Output: OD = open drain, PP = push-pull
The RESET configuration of each pin is shown in bold which is valid as long as the device is
in reset state.
Device pin description (8-pin package)
u
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Port / Control
1
VDD (1)
S
2
PA5/AIN4/
CLKIN
I/
CT HS
O
X
ei4
3
PA4/AIN3/MCO
I/
CT HS
O
X
ei3
4
PA3/RESET (2)
O
5
PA2/AIN2/LTIC
I/
CT HS
O
PP
Main
Output Function
(after
reset)
OD
ana
int
Input
float
Output
Pin Name
Input
Pin
No.
Type
Level
wpu
Table 2.
)
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P
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Alternate Function
t
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o
Main power supply
X
u
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X
ei2
X
Port A5
Analog input 4 or External Clock Input
)-
X
X
Port A4
Analog input 3 or Main clock output
X
X
Port A3
RESET (2)
X
X
X
Port A2
Analog input 2 or Lite Timer Input
Capture
s
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c
X
s
b
O
X
X
Pr
6
PA1/AIN1/
ICCCLK
I/
CT HS
O
X
ei1
X
X
X
Port A1
Analog input 1 or In Circuit
Communication Clock
Caution: During normal operation
this pin must be pulled-up, internally
or externally (external pull-up of 10k
mandatory in noisy environment).
This is to avoid entering ICC mode
unexpectedly during a reset. In the
application, even if the pin is
configured as output, any reset will
put it back in pull-up
7
PA0/AIN0/
ATPWM/
ICCDATA
I/
CT HS
O
X
ei0
X
X
X
Port A0
Analog input 0 or Auto-Reload Timer
PWM or In Circuit Communication
Data
8
VSS (1)
S
e
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e
ol
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Ground
1. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground.
2. After a reset, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to
MUXCR0 and AAh to MUXCR1.
12/123
ST7FOXA0
3
Register and memory mapping
Register and memory mapping
As shown in Figure 3, the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM
and 2 Kbytes of Flash program memory. The RAM space includes up to 64 bytes for the
stack from C0h to FFh.
The highest address bytes contain the user reset and interrupt vectors.
The Flash memory contains two sectors (see Figure 3) mapped in the upper part of the ST7
addressing space so the reset and interrupt vectors are located in Sector 0 (FFE0h-FFFFh).
)
s
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ct
The size of Flash Sector 0 and other device options are configurable by option bytes (refer
to Section 13.1 on page 110).
Caution:
u
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Memory locations marked as “Reserved” must never be accessed. Accessing a reserved
area can have unpredictable effects on the device.
Figure 3.
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ST7FOXA0 memory map
0000h
007Fh
0080h
t
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0080h
HW Registers
(see Table 3)
Short Addressing
RAM (zero page)
s
b
O
00C0h
64-Byte Stack
RAM
(128 Bytes)
00FFh
)-
00FFh
0100h
s
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bs
O
Table 3.
F7FFh
F800h
FFDFh
FFE0h
RCCRH_USER
RCCRL_USER
DEE0h
du
ro
1000h
1001h
DEE1h
RCCRH0
RCCRL0
Reserved
2K Flash
program memory
F800h
Flash Memory
(2K)
FBFFh
FC00h
FFFFh
see Section 6.1.1
1 Kbyte
SECTOR 1
1 Kbyte
SECTOR 0
Interrupt & Reset Vectors
(see )
FFFFh
ST7FOXA0 Hardware register map(1)
Address
Block
Register label
Register name
Reset status
Remarks
0000h
0001h
0002h
Port A
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h (2)
08h
02h (3)
R/W
R/W
R/W
0003h to
000Ah
Reserved area (8 bytes)
13/123
Register and memory mapping
Table 3.
ST7FOXA0
ST7FOXA0 Hardware register map(1) (continued)
Address
Block
Register label
Register name
Reset status
Remarks
000Bh
000Ch
LITE
TIMER
LTCSR
LTICR
Lite Timer Control/Status Register
Lite Timer Input Capture Register
0xh
00h
R/W
Read Only
AUTORELOAD
TIMER
ATCSR
CNTRH
CNTRL
ATRH
ATRL
PWMCR
PWM0CSR
Timer Control/Status Register
Counter Register High
Counter Register Low
Auto-Reload Register High
Auto-Reload Register Low
PWM Output Control Register
PWM 0 Control/Status Register
00h
00h
00h
00h
00h
00h
00h
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h to
0016h
0017h
0018h
AUTORELOAD
TIMER
DCR0H
DCR0L
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
0019h to
002Eh
let
FLASH
FCSR
Flash Control/Status Register
u
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0030h
RC
Calibration
RCC_CSR
RC calibration Control/Status register
R/W
R/W
00h
R/W
00h
R/W
A/D Control Status Register
A/D Data Register High
A/D Data Register Low
00h
xxh
00h
R/W
Read Only
R/W
External Interrupt Control Register 1
00h
R/W
MCCSR
Main Clock Control/Status Register
00h
R/W
RCCRH
RCCRL
RC oscillator Control Register High
RC oscillator Control Register Low
FFh
0000 0x00b
R/W
R/W
o
s
b
0031h to
0033h
Reserved area (3 bytes)
0034h
0035h
0036h
ADC
ADCCSR
ADCDRH
ADCDRL
0037h
ITC
EICR1
0038h
MCC
0039h
003Ah
Clock and
Reset
e
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O
)
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du
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P
003Bh to
003Ch
O
00h
00h
r
P
e
Reserved area (22 bytes)
0002Fh
bs
)
s
(
ct
Reserved area (3 bytes)
Reserved area (2 bytes)
003Dh
ITC
EICR2
External Interrupt Control Register 2
00h
R/W
003Eh
003Fh
Clock
controller
PSCR
CKCNTCSR
Prescaler Register
Clock Controller Control/Status Register
03h
09h
R/W
R/W
0040h to
0046h
Reserved area (7 bytes)
0047h
0048h
MuxIOreset
MUXCR0
MUXCR1
Mux IO-Reset Control Register 0
Mux IO-Reset Control Register 1
00h
00h
R/W
R/W
0049h
004Ah
AWU
AWUPR
AWUCSR
AWU Prescaler Register
AWU Control/Status Register
FFh
00h
R/W
R/W
14/123
ST7FOXA0
Table 3.
Address
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
Register and memory mapping
ST7FOXA0 Hardware register map(1) (continued)
Block
Register label
Register name
Reset status
Remarks
DM (4)
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DM Control Register
DM Status Register
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
0051h to
007Fh
Reserved area (47 bytes)
1. Legend: x=undefined, R/W=read/write.
)
s
(
ct
2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
3. The bits associated with unavailable pins must always keep their reset value.
u
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o
4. For a description of the Debug Module registers, see ICC protocol reference manual.
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15/123
Flash programmable memory
ST7FOXA0
4
Flash programmable memory
4.1
Introduction
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be
electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in
parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using In-Circuit Programming or In-Application Programming.
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
)
s
(
ct
4.3
Main features
u
d
o
●
ICP (In-Circuit Programming)
●
IAP (In-Application Programming)
●
ICT (In-Circuit Testing) for downloading and executing user application test patterns in
RAM
●
Sector 0 size configurable by option byte
●
Read-out and write protection
)
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Programming modes
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The ST7 can be programmed in three different ways:
●
Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte row
can be programmed or erased.
●
In-Circuit Programming. In this mode, Flash sectors 0 and 1, option byte row can be
programmed or erased without removing the device from the application board.
●
P
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4.3.1
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In-Application Programming. In this mode, sector 1 can be programmed or erased
without removing the device from the application board and while the application is
running.
In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on
a printed circuit board (PCB) to communicate with an external programming device
connected via cable. ICP is performed in three steps:
Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific
signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the
ST7 enters ICC mode, it fetches a specific Reset vector which points to the ST7 System
Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes
from the ICC interface.
16/123
●
Download ICP Driver code in RAM from the ICCDATA pin
●
Execute ICP Driver code in RAM to program the Flash memory
ST7FOXA0
Flash programmable memory
Depending on the ICP Driver code downloaded in RAM, Flash memory programming can
be fully customized (number of bytes to program, program locations, or selection of the
serial communication interface for downloading).
4.3.2
In Application Programming (IAP)
This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in
ICP mode).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored etc.)
IAP mode can be used to program any memory areas except Sector 0, which is Write/Erase
protected to allow recovery in case errors occur during the programming operation.
4.4
)
s
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u
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ICC interface
ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These
pins are:
Note:
1
r
P
e
●
RESET: device reset
●
VSS: device power supply ground
●
ICCCLK: ICC output serial clock pin
●
ICCDATA: ICC input serial data pin
●
OSC1: main clock input for external source
●
VDD: application board power supply (optional, see Note 3)
)
(s
t
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s
b
O
If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal
isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an
ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the
application. If they are used as inputs by the application, isolation such as a serial resistor
has to be implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
t
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2
During the ICP session, the programming tool must control the RESET pin. This can lead to
conflicts between the programming tool and the application reset circuit if it drives more than
5mA at high level (push pull output or pull-up resistor1 kΩ or a reset management IC with open drain output and pull-up resistor>1 kΩ, no
additional components are needed. In all cases the user must ensure that no external reset
is generated by the application during the ICC session.
3
The use of pin 7 of the ICC connector depends on the Programming Tool architecture. This
pin must be connected when using most ST Programming Tools (it is used to monitor the
application power supply). Please refer to the Programming Tool manual.
4
In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a
clock source, regardless of the selection in the option byte. In “disabled option byte” mode
(35-pulse ICC mode), pin 9 has to be connected to the CLKIN pin of the ST7 when the clock
is not available in the application or if the selected clock option is not programmed in the
option byte.
5
A serial resistor must be connected to ICC connector pin 6 in order to prevent contention on
PA3/RESET pin. Contention may occur if a tool forces a state on RESET pin while PA3 pin
forces the opposite state in output mode. The resistor value is defined to limit the current
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17/123
Flash programmable memory
ST7FOXA0
below 2mA at 5V. If PA3 is used as output push-pull, then the application must be switched
off to allow the tool to take control of the RESET pin (PA3). To allow the programming tool to
drive the RESET pin below VIL, special care must also be taken when a pull-up is placed on
PA3 for application reasons.
During normal operation the ICCCLK pin must be internally or externally pulled- up (external
pull-up of 10 kΩ mandatory in noisy environment) to avoid entering ICC mode unexpectedly
during a reset. In the application, even if the pin is configured as output, any reset will put it
back in input pull-up.
Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
OPTIONAL
(See Note 4)
9
7
5
3
1
10
8
6
4
2
CL2
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18/123
RESET
VDD
)
(s
t
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s
b
O
ST7
u
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o
APPLICATION BOARD
r
P
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CL1
CLKIN
APPLICATION
POWER SUPPLY
)
s
(
ct
APPLICATION
RESET SOURCE
See Note 2
3.3kΩ
(See Note 5)
ICCDATA
Figure 4.
ICCCLK
Caution:
See Note 1 and Caution
See Note 1
APPLICATION
I/O
ST7FOXA0
4.5
Flash programmable memory
Memory protection
There are two different types of memory protection: Read-Out Protection and Write/Erase
Protection which can be applied individually.
4.5.1
Read-out protection
Read-Out Protection, when selected provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
●
4.5.2
In Flash devices, this protection is removed by reprogramming the option. In this case,
the program memory is automatically erased and the device can be reprogrammed.
The read-out protection is enabled and removed through the FMP_R bit in the option
byte.
)
s
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u
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o
Flash write/erase protection
r
P
e
Write/Erase Protection, when set, makes it impossible to both overwrite and erase program
memory. Its purpose is to provide advanced security to applications and prevent any change
being made to the memory content. Write/Erase Protection is enabled through the FMP_W
bit in the option byte.
t
e
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o
Caution:
Once set, Write/Erase Protection can never be removed. A write-protected Flash
device is no longer reprogrammable.
4.6
Related documentation
)
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For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual.
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19/123
Flash programmable memory
4.7
ST7FOXA0
Description of Flash Control/Status register (FCSR)
This register controls the XFlash erasing and programming using ICP, IAP or other
programming methods.
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys
are sent automatically.
Reset value: 000 0000 (00h)
7
0
0
0
0
0
0
OPT
Read/write
Table 4.
Address
(Hex.)
002Fh
7
6
5
FCSR
Reset Value
0
0
0
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20/123
PGM
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Flash register mapping and reset values
Register
label
)
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LAT
4
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0
3
2
1
0
0
OPT
0
LAT
0
PGM
0
ST7FOXA0
Central processing unit
5
Central processing unit
5.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.
5.2
5.3
Main features
●
63 basic instructions
●
Fast 8-bit by 8-bit multiply
●
17 main addressing modes
●
Two 8-bit index registers
●
16-bit stack pointer
●
Low power modes
●
Maskable hardware interrupts
●
Non-maskable software interrupt
)
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CPU registers
The six CPU registers shown in Figure 5. They are not present in the memory mapping and
are accessed by specific instructions.
Figure 5.
CPU registers
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7
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15
)
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Pr
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
PCH
8 7
PCL
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1 1 1 H I
0
N Z C
CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8 7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
21/123
Central processing unit
5.3.1
ST7FOXA0
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
5.3.2
Index registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective
addresses or temporary storage areas for data manipulation. (The Cross-Assembler
generates a precede instruction (PRE) to indicate that the following instruction refers to the
Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and
popped from the stack).
5.3.3
)
s
(
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Program Counter (PC)
u
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The Program Counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter low which is
the LSB) and PCH (Program Counter high which is the MSB).
5.3.4
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Condition Code register (CC)
The 8-bit Condition Code register contains the interrupt mask and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
)
(s
Reset value: 111x 1xxx
7
1
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1
1
od
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0
H
I
N
Z
C
Read/write
These bits can be individually tested and/or controlled by specific instructions.
t
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Arithmetic management bits
s
b
O
Bit 4 = H Half carry bit
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during
an ADD or ADC instruction. It is reset by hardware during the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
22/123
ST7FOXA0
Central processing unit
Bit 3 = I Interrupt mask bit
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM
and JRNM instructions.
Note:
Interrupts requested while I is set are latched and can be processed when I is cleared. By
default an interrupt routine is not interruptible because the I bit is set by hardware at the start
of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared
by software in the interrupt routine, pending interrupts are serviced regardless of the priority
level of the current interrupt routine.
)
s
(
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Bit 2 = N Negative bit
This bit is set and cleared by hardware. It is representative of the result sign of the last
arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.
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0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1).
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This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero bit
s
b
O
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
)
(s
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
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This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow bit
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
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5.3.5
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
Stack Pointer (SP)
Reset value: 00FFh
15
0
0
0
0
0
0
0
8
7
0
1
0
1
SP5 SP4 SP3 SP2 SP1 SP0
Read/write
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 6).
23/123
Central processing unit
ST7FOXA0
Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD
instruction.
Note:
When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 6.
)
s
(
ct
●
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
●
On return from interrupt, the SP is incremented and the context is popped from the
stack.
u
d
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r
P
e
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 6.
CALL
Subroutine
let
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O
24/123
d
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P
e
@ 00FFh
)
(s
t
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SP
s
b
O
PUSH Y
Interrupt
Event
@ 00C0h
SP
t
e
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o
ST7FOXA0 stack manipulation example
POP Y
RET
or RSP
IRET
SP
CC
A
Y
CC
A
SP
CC
A
X
X
X
PCH
PCH
PCH
SP
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
Stack Higher Address = 00FFh
Stack Lower Address = 00C0h
SP
ST7FOXA0
6
Supply, reset and clock management
Supply, reset and clock management
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. The main features are the following:
●
Clock management
–
8 MHz internal RC oscillator (enabled by option byte)
–
Auto wakeup RC oscillator (enabled by option byte)
–
External clock input (enabled by option byte)
●
Reset Sequence Manager (RSM)
●
System Integrity management (SI)
–
)
s
(
ct
Main supply Low voltage detection (LVD) with reset generation (enabled by option
byte)
6.1
RC oscillator adjustment
6.1.1
Internal RC oscillator
u
d
o
r
P
e
t
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l
o
The device contains an internal RC oscillator with a specific accuracy for a given device,
temperature and voltage range (4.5 V - 5.5 V). It must be calibrated to obtain the frequency
required in the application. This is done by software writing a 10-bit calibration value in the
RCCRH (RC Control register High) and in the bits 6:5 in the RCCRL (RC Control register
Low).
)
(s
s
b
O
Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each
time the device is reset, the calibration value must be loaded in the RCCR. Predefined
calibration values are stored for 5 V VDD supply voltage at 25 °C (see Table 5).
t
c
u
Table 5.
P
e
let
O
o
s
b
d
o
r
Predefined RC oscillator calibration values
RCCR
Conditions
RCCRH
VDD= 5V
TA= 25°C
fRC = 8 MHz
RCCRL
ST7FOX
Address
DEE0h(1) (CR[9:2])
DEE1h(1) (CR[1:0])
1. The DEE0h and DEE1h addresses are located in a reserved area in non-volatile memory. They are readonly bytes for the application code. This area cannot be erased or programmed by any ICC operations.
For compatibility reasons with the RCCRL register, CR[1:0] bits are stored in the 5th and 6th position of
DEE1 address.
In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of
the selection in the option byte.
Section 12: Electrical characteristics on page 92 for more information on the frequency and
accuracy of the RC oscillator.
To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100 nF, between the VDD and VSS pins and also between the VDDA and
VSSA pins as close as possible to the ST7 device.
These bytes are systematically programmed by ST.
25/123
Supply, reset and clock management
6.1.2
ST7FOXA0
Customized RC calibration
If the application requires a higher frequency accuracy or if the voltage or temperature
conditions change in the application, the frequency may need to be recalibrated. Two nonvolatile bytes (RCCRH_USER and RCCRL_USER) are reserved for storing these new
values. These two-byte area is Electrically Erasable Programmable Read Only Memory.
Note:
Refer to application note AN1324 for information on how to calibrate the RC frequency using
an external reference signal.
How to program RCCRH_USER and RCCRL_USER
To access the write mode, the RCCLAT bit has to be set by software (the RCCPGM bit
remains cleared). When a write access to this two-byte area occurs, the values are latched.
)
s
(
ct
When RCCPGM bit is set by the software, the latched data are programmed in the
EEPROM cells. To avoid wrong programming, the user must take care to only access these
two-byte addresses.
u
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P
e
At the end of the programming cycle, the RCCPGM and RCCLAT bits are cleared
simultaneously.
Note:
t
e
l
o
During the programming cycle, it is forbidden to access the latched data (see Figure 7).
Figure 7.
RCCRH_USER and RCCRL_USER programming flowchart
READ MODE
RCCLAT=0
RCCPGM=0
)
(s
t
c
u
od
r
P
e
s
b
O
READ BYTES
Note:
WRITE THE 2 BYTES
AT THEIR ADDRESS
START PROGRAMMING CYCLE
RCCLAT=1
RCCPGM=1 (set by software)
t
e
l
o
s
b
O
WRITE MODE
RCCLAT=1
RCCPGM=0
0 RCCLAT 1
CLEARED BY HARDWARE
If a programming cycle is interrupted (by a reset action), the integrity of the data in memory
is not guaranteed.
Access error handling
If a read access occurs while RCCLAT=1, then the data bus will not be driven.
If a write access occurs while RCCLAT=0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by a RESET action), the integrity of the data in
memory will not be guaranteed.
26/123
ST7FOXA0
Caution:
Supply, reset and clock management
When the Read-Out Protection is enabled through an option bit (see Section 13.1: Option
bytes), these two bytes are protected against Read-out (including a re-write protection). In
Flash devices, when this protection is removed by reprogramming the option byte, these two
bytes are automatically erased.
Figure 8.
RC user calibration programming cycle
READ OPERATION POSSIBLE
READ OPERATION NOT POSSIBLE
Internal
Programming
voltage
WRITE OF
DATA LATCHES
ERASE CYCLE
tPROG
WRITE CYCLE
)
s
(
ct
Byte 1 Byte 2
RCCLAT
u
d
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r
P
e
tPROG is typically 5 ms and max 10 ms
6.1.3
Auto wakeup RC oscillator
RCCPGM
t
e
l
o
s
b
O
The ST7FOX also contains an Auto wakeup RC oscillator. This RC oscillator should be
enabled to enter Auto wakeup from halt mode.
)
(s
The Auto wakeup (AWU) RC oscillator can also be configured as the startup clock through
the CKSEL[1:0] option bits (see Section 13.1: Option bytes on page 110).
t
c
u
This is recommended for applications where very low power consumption is required.
d
o
r
Switching from one startup clock to another can be done in run mode as follows (see
Figure 9):
P
e
Case 1 Switching from internal RC to AWU
t
e
l
o
1.
O
bs
2.
Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator
The RC_FLAG is cleared and the clock output is at 1.
3.
Wait 3 AWU RC cycles till the AWU_FLAG is set
4.
The switch to the AWU clock is made at the positive edge of the AWU clock signal
5.
Once the switch is made, the internal RC is stopped
27/123
Supply, reset and clock management
ST7FOXA0
Case 2 Switching from AWU RC to internal RC
Note:
1.
Reset the RC/AWU bit to enable the internal RC oscillator
2.
Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is
running on internal RC clock.
3.
Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC
cycles)
4.
The switch to the internal RC clock is made at the positive edge of the internal RC clock
signal
5.
Once the switch is made, the AWU RC is stopped
1
When the internal RC is not selected, it is stopped so as to save power consumption.
2
When the internal RC is selected, the AWU RC is turned on by hardware when entering
Auto wakeup from Halt mode.
3
When the external clock is selected, the AWU RC oscillator is always on.
Figure 9.
u
d
o
Clock switching
r
P
e
Internal RC Set RC/AWU
AWU RC
Poll AWU_FLAG until set
AWU RC
bs
t
e
l
o
Reset RC/AWU
Poll RC_FLAG until set
O
)
s
(
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28/123
)
s
(
ct
Internal RC
ST7FOXA0
Supply, reset and clock management
Figure 10. ST7FOXA0 clock management block diagram
CR9
CR8
CR7
CR6
CR5
CR1
CR4
CR3
RCCRH
CR2
RCCRL
CR0
Tunable
internal RC Oscillator
RC/AWU CKCNTCSR
8MHz(fRC)
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
Prescaler
Clock
Controller
RC OSC
fOSC
)
s
(
ct
AWU CK
Ext Clock
CK2
CK1
fCLKIN
r
P
e
33kHz
AWU
RC
CLKIN
)
(s
t
c
u
/32 DIVIDER
d
o
r
CKSEL[1:0]
Option bits
t
e
l
o
/2
DIVIDER
s
b
O
13-BIT
LITE TIMER COUNTER
fOSC
u
d
o
PSCR
CK0
fOSC
fOSC/32
0
1
fLTIMER
(1ms timebase @ 8 MHz fOSC)
fCPU
TO CPU AND
PERIPHERALS
MCO SMS MCCSR
P
e
MCO
t
e
l
o
s
b
O
6.2
Multi-oscillator (MO)
The main clock of the ST7 can be generated by four different source types coming from the
multi-oscillator block (1 to 16 MHz):
6.2.1
●
An external source
●
An internal high frequency RC oscillator
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive CLKIN.
29/123
Supply, reset and clock management
6.2.2
ST7FOXA0
Internal RC oscillator
In this mode, the tunable RC oscillator is used as main clock source. The two oscillator pins
have to be tied to ground.
The calibration is done through the RCCRH[7:0] and RCCRL[6:5] registers.
6.3
Reset sequence manager (RSM)
6.3.1
Introduction
)
s
(
ct
The reset sequence manager includes three RESET sources as shown in Figure 12:
●
External RESET source pulse
●
Internal LVD RESET (Low Voltage Detection)
●
Internal WATCHDOG RESET
u
d
o
r
P
e
Note:
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 10.2.1 on page 84 for further details.
t
e
l
o
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
mapping.
s
b
O
The basic RESET sequence consists of 3 phases as shown in Figure 11:
Caution:
●
Active Phase depending on the RESET source
●
256 or 512 CPU clock cycle delay (see Table 6)
)
(s
t
c
u
When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
d
o
r
The 256 or 512 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay is
automatically selected depending on the clock source chosen by option byte.
P
e
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o
The Reset vector fetch phase duration is 2 clock cycles.
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30/123
Table 6.
CPU clock delay during Reset sequence
Clock source
CPU clock cycle delay
Internal RC 8 MHz Oscillator
512
Internal RC 32 kHz Oscillator
256
External clock connected to CLKIN pin
512
ST7FOXA0
Supply, reset and clock management
Figure 11. ST7FOXA0 reset sequence phases
RESET
active phase
Fetch
vector
Internal reset
256 or 512 clock cycles
)
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(
ct
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)
(s
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31/123
Supply, reset and clock management
6.3.2
ST7FOXA0
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Electrical Characteristic
section for more details.
A RESET signal originating from an external source must have a duration of at least
th(RSTL)in in order to be recognized (see Figure 13: Reset sequences). This detection is
asynchronous and therefore the MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
)
s
(
ct
Figure 12. Reset block diagram
VDD
u
d
o
r
P
e
RON
Filter
RESET
t
e
l
o
PULSE
GENERATOR
)
(s
s
b
O
INTERNAL
RESET
___ WATCHDOG RESET
___ ILLEGAL OPCODE RESET 1)
___ LVD RESET
1. See Section 10.2.1: Illegal opcode reset on page 84 for more details on illegal opcode reset conditions.
t
c
u
6.3.3
External power-on reset
d
o
r
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until VDD is over
the minimum level specified for the selected fOSC frequency.
P
e
t
e
l
o
A proper reset signal for a slow rising VDD supply can generally be provided by an external
RC network connected to the RESET pin.
s
b
O
6.3.4
Internal Low Voltage Detector (LVD) reset
Two different Reset sequences caused by the internal LVD circuitry can be distinguished:
●
Power-On reset
●
Voltage Drop reset
The device RESET pin acts as an output that is pulled low when VDD is lower than VIT+
(rising edge) or VDD lower than VIT- (falling edge) as shown in Figure 13.
The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.
32/123
ST7FOXA0
6.3.5
Supply, reset and clock management
Internal watchdog reset
The Reset sequence generated by an internal watchdog counter overflow is shown in
Figure 13: Reset sequences
Starting from the watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
Figure 13. Reset sequences
VDD
VIT+(LVD)
VIT-(LVD)
LVD
RESET
RUN
RUN
ACTIVE PHASE
EXTERNAL
RESET
ACTIVE
PHASE
RUN
ACTIVE
PHASE
RUN
u
d
o
r
P
e
th(RSTL)in
)
s
(
ct
WATCHDOG
RESET
tw(RSTL)out
t
e
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o
EXTERNAL
RESET
SOURCE
RESET PIN
)
(s
WATCHDOG
RESET
ct
u
d
o
s
b
O
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU)
VECTOR FETCH
r
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33/123
Supply, reset and clock management
6.3.6
ST7FOXA0
Multiplexed IO reset control register 1 (MUXCR1)
Reset value: 0000 0000 (00h)
7
MIR15
0
MIR14
MIR13
MIR12
MIR11
MIR10
MIR9
MIR8
Read/write once only
6.3.7
Multiplexed IO reset control register 0 (MUXCR0)
Reset value: 0000 0000 (00h)
)
s
(
ct
7
MIR7
0
MIR6
MIR5
MIR4
MIR3
u
d
o
MIR2
MIR0
r
P
e
Read/write once only
Bits 15:0 = MIR[15:0]
MIR1
t
e
l
o
This 16-bit register is read/write by software but can be written only once between two
reset events. It is cleared by hardware after a reset; When both MUXCR0 and
MUXCR1 registers are at 00h, the multiplexed PA3/RESET pin will act as RESET. To
configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1.
s
b
O
These registers are one-time writable only.
)
(s
To configure PA3 as general purpose output:
After power-on / reset, the application program has to configure the I/O port by writing
to these registers as described above. Once the pin is configured as an I/O output, it
cannot be changed back to a reset pin by the application code.
t
c
u
d
o
r
To configure PA3 as RESET:
An internally generated reset (such as POR, WDG, illegal opcode) will clear the two
registers and the pin will act again as a reset function. Otherwise, a power-down is
required to put the pin back in reset configuration.
P
e
t
e
l
o
Table 7.
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O
34/123
Address
Multiplexed IO register map and reset values
Register
Label
7
6
5
4
3
2
1
0
0047h
MUXCR0
Reset Value
MIR7
0
MIR6
0
MIR5
0
MIR4
0
MIR3
0
MIR2
0
MIR1
0
MIR0
0
0048h
MUXCR1
Reset Value
MIR15
0
MIR14
0
MIR13
0
MIR12
0
MIR11
0
MIR10
0
MIR9
0
MIR8
0
(Hex.)
ST7FOXA0
6.4
Supply, reset and clock management
System Integrity management (SI)
The System Integrity Management block contains the Low voltage Detector (LVD).
Note:
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 10.2.1 on page 84 for further details.
6.4.1
Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the VDD supply
voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well
as the power-down keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when VDD is below:
●
VIT+(LVD) when VDD is rising
●
VIT-(LVD) when VDD is falling
The LVD function is illustrated in Figure 14.
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
The voltage threshold can be enabled/disabled by option byte. See Section 13.1 on page
110.
s
b
O
Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD),
the MCU can only be in two modes:
)
(s
●
Under full software control
●
In static safe reset
t
c
u
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
d
o
r
During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU
to reset other devices.
Note:
P
e
Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur
in the application, it is recommended to pull VDD down to 0 V to ensure optimum restart
conditions. Refer to circuit example in Figure 39 on page 106 and note 4.
t
e
l
o
s
b
O
The LVD is an optional function which can be selected by option byte. See Section 13.1 on
page 110.
It allows the device to be used without any external RESET circuitry.
If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset.
It is recommended to make sure that the VDD supply voltage rises monotonously when the
device is exiting from Reset, to ensure the application functions properly.
Caution:
If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will
clear the watchdog flag.
35/123
Supply, reset and clock management
ST7FOXA0
Figure 14. Low voltage detector vs reset
VDD
Vhys
VIT+(LVD)
VIT-(LVD)
RESET
Figure 15. Reset and supply management block diagram
WATCHDOG
TIMER (WDG)
STATUS FLAG
)
s
(
ct
SYSTEM INTEGRITY MANAGEMENT
RESET SEQUENCE
MANAGER
(RSM)
RESET
0
CR1 CR0
)
(s
t
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36/123
WDGF
0
s
b
O
LVDRF
0
r
P
e
t
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o
VSS
VDD
u
d
o
RCCRL
LOW VOLTAGE
DETECTOR
(LVD)
0
ST7FOXA0
Supply, reset and clock management
6.5
Register description
6.5.1
RC calibration control/status register (RCC_CSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
RCCLAT
RCCPGM
Read/write
Bits 7:2 = Reserved, forced by hardware to 0
)
s
(
ct
0: Read mode
1: Write mode
u
d
o
Bit 1 = RCCLAT Latch Access Transfer bit: this bit is set by software.
It is cleared by hardware at the end of the programming cycle. It can only be cleared by
software if the RCCPGM bit is cleared
r
P
e
Bit 0 = RCCPGM Programming Control and Status bit
t
e
l
o
This bit is set by software to begin the programming cycle. At the end of the
programming cycle, this bit is cleared by hardware.
s
b
O
0: Programming finished or not yet started
1: Programming cycle is in progress
)
(s
Note:
If the RCCPGM bit is cleared during the programming cycle, the memory data is not
guaranteed.
6.5.2
Main Clock Control/Status Register (MCCSR)
t
c
u
d
o
r
Reset value: 0000 0000 (00h)
P
e
7
b
O
so
let
0
0
0
0
0
0
0
MCO
SMS
Read/write
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = MCO Main Clock Out enable bit
This bit is read/write by software and cleared by hardware after a reset. This bit allows
to enable the MCO output clock.
0: MCO clock disabled, I/O port free for general purpose I/O.
1: MCO clock enabled.
Bit 0 = SMS Slow mode selection bit
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the input clock fOSC or fOSC/32.
0: Normal mode (fCPU = fOSC
1: Slow mode (fCPU = fOSC/32)
37/123
Supply, reset and clock management
6.5.3
ST7FOXA0
RC Control Register High (RCCRH)
Reset value: 1111 1111 (FFh)
7
CR9
0
CR8
CR7
CR6
CR5
CR4
CR3
CR2
Read/write
Bits 7:0 = CR[9:2] RC Oscillator Frequency Adjustment bits
These bits must be written immediately after reset to adjust the RC oscillator
frequency. The application can store the correct value for each voltage range in Flash
memory and write it to this register at start-up.
)
s
(
ct
00h = maximum available frequency
FFh = lowest available frequency
u
d
o
These bits are used with the CR[1:0] bits in the RCCRL register. Refer to
Chapter 6.5.4.
r
P
e
Note:
To tune the oscillator, write a series of different values in the register until the correct
frequency is reached. The fastest method is to use a dichotomy starting with 80h.
t
e
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o
)
(s
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38/123
s
b
O
ST7FOXA0
6.5.4
Supply, reset and clock management
RC Control Register Low (RCCRL)
Reset value: 0000 0000 (00h)
7
0
0
CR1
CR0
0
0
LVDRF
0
0
Read/write
Bit 7 = Reserved, must be kept cleared
Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits
These bits, as well as CR[9:2] bits in the RCCRH register must be written immediately
after reset to adjust the RC oscillator frequency. Refer to Section 6.1.1: Internal RC
oscillator on page 25.
)
s
(
ct
u
d
o
Bits 4:3 = Reserved, must be kept cleared
Bit 2 = LVDRF LVD reset flag
r
P
e
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled
by option byte, the LVDRF bit value is undefined.
t
e
l
o
The LVDRF flag is not cleared when another RESET type occurs (external or
watchdog), the LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can
not.
)
(s
s
b
O
Bits 1:0 = Reserved, must be kept cleared
t
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s
b
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39/123
Supply, reset and clock management
6.5.5
ST7FOXA0
Prescaler register (PSCR)
Reset value: 0000 0011 (03h)
7
CK2
0
CK1
CK0
0
0
0
1
1
Read/write
Bits 7:5 = CK[2:0] internal RC Prescaler Selection
These bits are set by software and cleared by hardware after a reset. These bits select
the prescaler of the internal RC oscillator. See Figure 10: ST7FOXA0 clock
management block diagram on page 29 and Table 8.
)
s
(
ct
If the internal RC is used with a supply operating range below 3.3 V, a division ratio of
at least 2 must be enabled in the RC prescaler.
Table 8.
u
d
o
Internal RC prescaler selection bits
CK2
CK1
CK0
0
0
1
0
1
0
0
1
1
1
0
0
fOSC
r
P
e
fRC/2
t
e
l
o
others
)
(s
s
b
O
fRC/4
fRC/8
fRC/16
fRC
Bits 4:0 = Reserved, must be kept at their reset value.
t
c
u
6.5.6
Clock controller control/status register (CKCNTCSR)
d
o
r
Reset value: 0000 1001 (09h)
P
e
t
e
l
o
bs
O
7
0
0
0
0
0
AWU_FLAG
RC_FLAG
Read/write
Bits 7:4 = Reserved, must be kept cleared.
Bit 3 = AWU_FLAG AWU Selection bit
This bit is set and cleared by hardware.
0: No switch from AWU to RC requested
1: AWU clock activated and temporization completed
Bit 2 = RC_FLAG RC Selection bit
This bit is set and cleared by hardware.
0: No switch from RC to AWU requested
1: RC clock activated and temporization completed
Bit 1 = Reserved, must be kept cleared.
40/123
0
RC/AWU
ST7FOXA0
Supply, reset and clock management
Bit 0 = RC/AWU RC/AWU Selection bit
0: RC enabled
1: AWU enabled (default value)
Table 9.
Addre
ss
Clock register mapping and reset values
Register
label
7
6
5
4
3
2
1
0
0030h
RCC_CSR
0
0
0
0
0
0
RCCLAT
0
RCCPGM
0
003Ah
MCCSR
Reset Value
0
0
0
0
0
0
MCO
0
SMS
0
003Bh
RCCRH
Reset Value
CR9
1
CR8
1
CR7
1
CR6
1
CR5
1
CR4
1
003Ch
RCCRL
Reset Value
0
CR1
1
CR0
1
0
0
003Dh
PSCR
Reset Value
CK2
0
CK1
0
CK0
0
0
0051h
CKCNTCSR
Reset Value
0
0
0
(Hex.)
)
(s
0
CR3
1
CR2
1
LVDRF
x
0
0
0
0
1
1
AWU_
FLAG
1
RC_FLA
G
0
0
RC/AWU
1
r
P
e
t
e
l
o
s
b
O
u
d
o
)
s
(
ct
t
c
u
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P
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t
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s
b
O
41/123
Power saving modes
ST7FOXA0
7
Power saving modes
7.1
Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 16):
●
Slow
●
Wait (and Slow-Wait)
●
Active Halt
●
Auto wakeup From Halt (AWUFH)
●
Halt
)
s
(
ct
After a reset the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency (fOSC).
u
d
o
r
P
e
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
t
e
l
o
Figure 16. Power saving mode transitions
)-
s
(
t
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bs
O
42/123
s
b
O
High
Run
Slow
Wait
Slow Wait
Active Halt
Halt
Low
POWER CONSUMPTION
ST7FOXA0
7.2
Power saving modes
Slow mode
This mode has two targets:
●
To reduce power consumption by decreasing the internal clock in the device,
●
To adapt the internal clock frequency (fCPU) to the available supply voltage.
Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables
Slow mode.
In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked
at this lower frequency.
Note:
Slow-Wait mode is activated when entering Wait mode while the device is already in Slow
mode.
)
s
(
ct
Figure 17. Slow mode clock transition
fOSC/32
r
P
e
fOSC
SMS
7.3
Wait mode
)
(s
u
d
o
fOSC
fCPU
s
b
O
t
e
l
o
NORMAL RUN MODE
REQUEST
t
c
u
d
o
r
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
P
e
This power saving mode is selected by calling the ‘WFI’ instruction.
s
b
O
t
e
l
o
All peripherals remain active. During Wait mode, the I bit of the CC register is cleared, to
enable all interrupts. All other registers and memory remain unchanged. The MCU remains
in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches
to the starting address of the interrupt or Reset service routine.
The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake
up.
Refer to Figure 18 for a description of the Wait mode flowchart.
43/123
Power saving modes
ST7FOXA0
Figure 18. Wait mode flowchart
WFI INSTRUCTION
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
OFF
0
N
RESET
Y
N
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
OFF
ON
0
)
s
(
ct
u
d
o
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I BIT
t
e
l
o
r
P
e
ON
ON
ON
X 1)
s
b
O
FETCH RESET VECTOR
OR SERVICE INTERRUPT
)
(s
1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
t
c
u
7.4
Active-halt and halt modes
d
o
r
Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in ActiveHalt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following
table:
P
e
t
e
l
o
s
b
O
Table 10.
Enabling/disabling active-halt and halt modes
LTCSR TBIE
bit
ATCSR OVFIE
ATCSRCK1 bit ATCSRCK0 bit
bit
0
x
x
0
0
0
x
x
0
1
1
1
1
x
x
x
x
1
0
1
Meaning
Active-Halt mode disabled
Active-Halt mode enabled
44/123
ST7FOXA0
7.4.1
Power saving modes
Active-halt mode
Active-Halt mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ instruction when active halt mode is enabled.
The MCU can exit Active-Halt mode on reception of a Lite timer/ AT timer interrupt or a
Reset.
●
When exiting Active-Halt mode by means of a Reset, a 256 CPU cycle delay occurs.
After the start up delay, the CPU resumes operation by fetching the Reset vector which
woke it up (see Figure 20).
●
When exiting Active-Halt mode by means of an interrupt, the CPU immediately
resumes operation by servicing the interrupt vector which woke it up (see Figure 20).
When entering Active-Halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
)
s
(
ct
In Active-Halt mode, only the main oscillator and the selected timer counter (LT/AT) are
running to keep a wakeup time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
Caution:
u
d
o
r
P
e
As soon as Active-Halt is enabled, executing a HALT instruction while the Watchdog is
active does not generate a Reset if the WDGHALT bit is reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
t
e
l
o
s
b
O
Figure 19. Active-halt timing overview
RUN
s
(
t
c
u
d
o
[Active Halt Enabled]
r
P
e
)-
ACTIVE
HALT
HALT
INSTRUCTION
256 CPU
CYCLE DELAY 1)
RESET
OR
INTERRUPT
RUN
FETCH
VECTOR
1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET.
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45/123
Power saving modes
ST7FOXA0
Figure 20. Active-halt mode flowchart
HALT INSTRUCTION
(Active Halt enabled)
OSCILLATOR
ON
PERIPHERALS 2) OFF
CPU
OFF
I BIT
0
N
RESET
N
Y
INTERRUPT 3)
Y
OSCILLATOR
ON
PERIPHERALS 2) OFF
CPU
ON
I BIT
X 4)
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I BITS
ON
ON
ON
X 4)
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
FETCH RESET VECTOR
OR SERVICE INTERRUPT
s
b
O
1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET.
2. Peripherals clocked with an external clock source can still be active.
)
(s
3. Only the Lite timer RTC and AT timer interrupts can exit the MCU from Active-Halt mode.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
7.4.2
Halt mode
t
c
u
d
o
r
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the HALT instruction when active halt mode is disabled.
P
e
t
e
l
o
s
b
O
The MCU can exit Halt mode on reception of either a specific interrupt (seeTable : ) or a
Reset. When exiting Halt mode by means of a Reset or an interrupt, the main oscillator is
immediately turned on and the 256 CPU cycle delay is used to stabilize it. After the start up
delay, the CPU resumes operation by servicing the interrupt or by fetching the Reset vector
which woke it up (see Figure 22).
When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog Reset (see Section 13.1: Option bytes for
more details).
46/123
ST7FOXA0
Power saving modes
Figure 21. Halt timing overview
RUN
HALT
HALT
INSTRUCTION
256 CPU CYCLE
DELAY
RUN
RESET
OR
INTERRUPT
FETCH
VECTOR
[Active Halt disabled]
1. A reset pulse of at least 42 µs must be applied when exiting from Halt mode.
Figure 22. Halt mode flowchart
HALT INSTRUCTION
(Active Halt disabled)
ENABLE
r
P
e
DISABLE
1
WATCHDOG
RESET
s
(
t
c
)-
N
u
d
o
r
P
e
s
b
O
t
e
l
o
u
d
o
WATCHDOG
0
WDGHALT 1)
)
s
(
ct
t
e
l
o
OSCILLATOR
OFF
PERIPHERALS 2) OFF
CPU
OFF
I BIT
0
s
b
O
N
RESET
Y
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
OFF
ON
X 4)
256 CPU CLOCK CYCLE
DELAY 5)
OSCILLATOR
PERIPHERALS
CPU
I BITS
ON
ON
ON
X 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
Table : for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
5. The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.
47/123
Power saving modes
ST7FOXA0
Halt mode recommendations
7.5
●
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
●
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
●
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
●
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a Program Counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
●
As the HALT instruction clears the I bit in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits before executing the HALT instruction.
This avoids entering other peripheral interrupt routines after executing the external
interrupt routine corresponding to the wakeup event (reset or external interrupt).
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
Auto wakeup from halt mode
Auto wakeup from halt (AWUFH) mode is similar to Halt mode with the addition of a specific
internal RC oscillator for wakeup (Auto wakeup from Halt oscillator) which replaces the main
clock which was active before entering Halt mode. Compared to Active-Halt mode, AWUFH
has lower power consumption (the main clock is not kept running), but there is no accurate
real-time clock available.
)
(s
s
b
O
t
c
u
It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR
register has been set.
d
o
r
Figure 23. AWUFH mode block diagram
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48/123
AWU RC
oscillator
fAWU_RC
/64
divider
to 8-bit timer Input Capture
AWUFH
prescaler/1 .. 255
AWUFH
interrupt
(ei0 source)
ST7FOXA0
Power saving modes
As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR
register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by
a fixed divider and a programmable prescaler controlled by the AWUPR register. The output
of this prescaler provides the delay time. When the delay has elapsed, the following actions
are performed:
●
the AWUF flag is set by hardware,
●
an interrupt wakes-up the MCU from Halt mode,
●
the main oscillator is immediately turned on and the 256 CPU cycle delay is used to
stabilize it.
After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The
AWU flag and its associated interrupt are cleared by software reading the AWUCSR
register.
)
s
(
ct
To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated
by measuring the clock frequency fAWU_RC and then calculating the right prescaler value.
Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run
mode. This connects fAWU_RC to the Input Capture of the 8-bit Lite timer, allowing the
fAWU_RC to be measured using the main oscillator clock as a reference timebase.
u
d
o
r
P
e
Similarities with halt mode
t
e
l
o
The following AWUFH mode behavior is the same as normal Halt mode:
●
The MCU can exit AWUFH mode by means of any interrupt with exit from Halt
capability or a reset (see Section 7.4: Active-halt and halt modes).
●
When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
●
In AWUFH mode, the main oscillator is turned off causing all internal processing to be
stopped, including the operation of the on-chip peripherals. None of the peripherals are
clocked except those which get their clock supply from another clock generator (such
as an external or auxiliary oscillator like the AWU oscillator).
)
(s
s
b
O
t
c
u
d
o
r
●
The compatibility of watchdog operation with AWUFH mode is configured by the
WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction
when executed while the watchdog system is enabled, can generate a watchdog Reset.
P
e
t
e
l
o
Figure 24. AWUF halt timing diagram
s
b
O
tAWU
RUN MODE
HALT MODE
256 tCPU
RUN MODE
fCPU
fAWU_RC
Clear
by software
AWUFH interrupt
49/123
Power saving modes
ST7FOXA0
Figure 25. AWUFH mode flowchart
HALT INSTRUCTION
(Active-Halt disabled)
(AWUCSR.AWUEN=1)
ENABLE
WATCHDOG
DISABLE
0
WDGHALT 1)
1
AWU RC OSC
ON
MAIN OSC
OFF
2)
PERIPHERALS OFF
CPU
OFF
I[1:0] BITS
10
WATCHDOG
RESET
)
s
(
ct
N
RESET
N
u
d
o
Y
INTERRUPT 3)
Y
r
P
e
AWU RC OSC
OFF
MAIN OSC
ON
PERIPHERALS OFF
CPU
ON
I[1:0] BITS
XX 4)
t
e
l
o
256 CPU CLOCK
CYCLE DELAY
)
(s
t
c
u
d
o
r
s
b
O
AWU RC OSC
OFF
MAIN OSC
ON
PERIPHERALS ON
CPU
ON
I[1:0] BITS
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
P
e
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
t
e
l
o
3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external
interrupt). Refer to Table : for more details.
s
b
O
50/123
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
ST7FOXA0
Power saving modes
7.5.1
Register description
7.5.2
AWUFH Control/Status Register (AWUCSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
AWU
F
0
AWUM
AWUEN
Read/Write
)
s
(
ct
Bits 7:3 = Reserved
Bit 2 = AWUF Auto wakeup flag
This bit is set by hardware when the AWU module generates an interrupt and cleared
by software on reading AWUCSR. Writing to this bit does not change its value.
u
d
o
0: No AWU interrupt occurred
r
P
e
1: AWU interrupt occurred
t
e
l
o
Bit 1 = AWUM Auto wakeup Measurement bit
This bit enables the AWU RC oscillator and connects its output to the Input Capture of
the 8-bit Lite timer. This allows the timer to be used to measure the AWU RC oscillator
dispersion and then compensate this dispersion by providing the right value in the
AWUPRE register.
)
(s
0: Measurement disabled
1: Measurement enabled
s
b
O
t
c
u
Bit 0 = AWUEN Auto wakeup From Halt Enabled bit
This bit enables the Auto wakeup from halt feature: once Halt mode is entered, the
AWUFH wakes up the microcontroller after a time delay dependent on the AWU
prescaler value. It is set and cleared by software.
d
o
r
P
e
0: AWUFH (Auto wakeup from Halt) mode disabled
t
e
l
o
Note:
s
b
O
1: AWUFH (Auto wakeup from Halt) mode enabled
Whatever the clock source, this bit should be set to enable the AWUFH mode once the
HALT instruction has been executed.
51/123
Power saving modes
7.5.3
ST7FOXA0
AWUFH Prescaler Register (AWUPR)
Reset value: 1111 1111 (FFh)
7
0
AWUPR7
AWUPR6
AWUPR5
AWUPR4
AWUPR3
AWUPR2
AWUPR1
AWUPR0
Read/Write
Bits 7:0= AWUPR[7:0] Auto wakeup Prescaler
These 8 bits define the AWUPR Dividing factor (see Table 11).
Table 11.
)
s
(
ct
Configuring the dividing factor
AWUPR[7:0]
Dividing factor
00h
Forbidden
01h
1
u
d
o
r
P
e
...
...
t
e
l
o
FEh
FFh
254
255
s
b
O
In AWU mode, the time during which the MCU stays in Halt mode, tAWU, is given by the
equation below. See also Figure 24 on page 49.
)
(s
1
t AWU = 64 × AWUPR × -------------------- + t RCSTRT
f AWURC
t
c
u
The AWUPR prescaler register can be programmed to modify the time during which the
MCU stays in Halt mode before waking up automatically.
d
o
r
Note:
If 00h is written to AWUPR, the AWUPR remains unchanged.
Table 12.
AWU register mapping and reset values
P
e
t
e
l
o
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
0048h
AWUCSR
Reset
Value
0
0
0
0
0
AWUF
AWUM
AWUEN
0049h
AWUPR
Reset
Value
s
b
O
52/123
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
1
1
1
1
1
1
1
1
ST7FOXA0
I/O ports
8
I/O ports
8.1
Introduction
The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be
programmed independently either as a digital input or digital output. In addition, specific pins
may have several other functions. These functions can include external interrupt, alternate
signal input/output for on-chip peripherals or analog input.
8.2
Functional description
)
s
(
ct
A Data register (DR) and a Data Direction register (DDR) are always associated with each
port. The Option register (OR), which allows input/output options, may or may not be
implemented. The following description takes into account the OR register. Refer to the Port
Configuration table for device specific information.
u
d
o
r
P
e
An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit
x corresponding to pin x of the port.
t
e
l
o
Figure 26 shows the generic I/O block diagram.
8.2.1
Input modes
s
b
O
Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital
value from that I/O pin.
)
(s
If an OR bit is available, different input modes can be configured by software: floating or pullup. Refer to I/O Port Implementation section for configuration.
Note:
t
c
u
1
Writing to the DR modifies the latch value but does not change the state of the input pin.
2
Do not use read/modify/write instructions (BSET/BRES) to modify the DR register.
d
o
r
External interrupt function
P
e
Depending on the device, setting the ORx bit while in input mode can configure an I/O as an
input with interrupt. In this configuration, a signal edge or level input on the I/O generates an
interrupt request via the corresponding interrupt vector (eix).
s
b
O
t
e
l
o
Falling or rising edge sensitivity is programmed independently for each interrupt vector. The
External Interrupt Control register (EICR) or the Miscellaneous register controls this
sensitivity, depending on the device.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout
description and interrupt section). If several I/O interrupt pins on the same interrupt vector
are selected simultaneously, they are logically combined. For this reason if one of the
interrupt pins is tied low, it may mask the others.
External interrupts are hardware interrupts. Fetching the corresponding interrupt vector
automatically clears the request latch. Changing the sensitivity of a particular external
interrupt clears this pending interrupt. This can be used to clear unwanted pending
interrupts.
53/123
I/O ports
ST7FOXA0
Spurious interrupts
When enabling/disabling an external interrupt by setting/resetting the related OR register bit,
a spurious interrupt is generated if the pin level is low and its edge sensitivity includes
falling/rising edge. This is due to the edge detector input which is switched to '1' when the
external interrupt is disabled by the OR register.
To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and
falling edge for disabling) has to be selected before changing the OR register bit and
configuring the appropriate sensitivity again.
Caution:
In case a pin level change occurs during these operations (asynchronous signal input), as
interrupts are generated according to the current sensitivity, it is advised to disable all
interrupts before and to reenable them after the complete previous sequence in order to
avoid an external interrupt occurring on the unwanted edge.
)
s
(
ct
This corresponds to the following steps:
Set the interrupt mask with the SIM instruction (in cases where a pin level change
could occur)
b)
Select rising edge
c)
Enable the external interrupt through the OR register
d)
Select the desired sensitivity if different from rising edge
e)
Reset the interrupt mask with the RIM instruction (in cases where a pin level
change could occur)
r
P
e
t
e
l
o
2. To disable an external interrupt:
s
b
O
a)
Set the interrupt mask with the SIM instruction SIM (in cases where a pin level
change could occur)
b)
Select falling edge
c)
Disable the external interrupt through the OR register
d)
Select rising edge
e)
Reset the interrupt mask with the RIM instruction (in cases where a pin level
change could occur)
)
(s
t
c
u
d
o
r
P
e
t
e
l
o
8.2.2
s
b
O
Output modes
Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the
I/O through the latch. Reading the DR bits returns the previously stored value.
If an OR bit is available, different output modes can be selected by software: push-pull or
open-drain. Refer to I/O Port Implementation section for configuration.
Table 13.
54/123
u
d
o
a)
DR Value and output pin status
DR
Push-Pull
Open-Drain
0
VOL
VOL
1
VOH
Floating
ST7FOXA0
8.2.3
I/O ports
Alternate functions
Many ST7s I/Os have one or more alternate functions. These may include output signals
from, or input signals to, on-chip peripherals.Table 2 describes which peripheral signals can
be input/output to which ports.
A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the
on-chip peripheral as an output (enable bit in the peripheral’s control register). The
peripheral configures the I/O as an output and takes priority over standard I/O programming.
The I/O’s state is readable by addressing the corresponding I/O data register.
Configuring an I/O as floating enables alternate function input. It is not recommended to
configure an I/O as pull-up as this will increase current consumption. Before using an I/O as
an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur.
)
s
(
ct
Configure an I/O as input floating for an on-chip peripheral signal which can be input and
output.
Caution:
u
d
o
I/Os which can be configured as both an analog and digital alternate function need special
attention. The user must control the peripherals so that the signals do not arrive at the same
time on the same pin. If an external clock is used, only the clock alternate function should be
employed on that I/O pin and not the other alternate function.
r
P
e
t
e
l
o
Figure 26. I/O port general block diagram
ALTERNATE
OUTPUT
REGISTER
ACCESS
From on-chip peripheral
ALTERNATE
ENABLE
BIT
u
d
o
DDR
O
DATA BUS
r
P
e
bs
0
)
s
(
ct
DR
t
e
l
o
1
OR
bs
VDD
-O
P-BUFFER
(see table below)
PULL-UP
(see table below)
VDD
PULL-UP
CONDITION
PAD
If implemented
OR SEL
N-BUFFER
DIODES
(see table below)
DDR SEL
DR SEL
CMOS
SCHMITT
TRIGGER
1
0
EXTERNAL
INTERRUPT
REQUEST (eix)
ANALOG
INPUT
ALTERNATE
INPUT
Combinational
Logic
SENSITIVITY
SELECTION
To on-chip peripheral
FROM
OTHER
BITS Note: Refer to the Port Configuration
table for device specific information.
55/123
I/O ports
ST7FOXA0
Table 14.
I/O port mode options (1)
Diodes
Configuration mode
Pull-Up
Floating with/without Interrupt
Off
Pull-up with Interrupt
On
P-Buffer
Input
to VDD
to VSS
On
On
Off
Push-pull
On
Output
Off
Open Drain (logic level)
Off
1. Off means implemented not activated, On means implemented and activated.
Table 15.
)
s
(
ct
ST7FOXA0 I/O port configuration
Hardware configuration
u
d
o
DR REGISTER ACCESS
r
P
e
DR
REGISTER
t
e
l
o
INPUT (1)
PAD
OPEN-DRAIN OUTPUT(2)
)-
s
(
t
c
r
P
e
PAD
PUSH-PULL OUTPUT(2)
DATA BUS
R
ALTERNATE INPUT
To on-chip peripheral
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (eix)
INTERRUPT COMBINATIONAL POLARITY
LOGIC SELECTION
CONDITION
ANALOG INPUT
u
d
o
t
e
l
o
s
b
O
s
b
O
W
DR REGISTER ACCESS
DR
REGISTER
R/W
DATA BUS
DR REGISTER ACCESS
PAD
DR
REGISTER
ALTERNATE
ENABLE
BIT
R/W
DATA BUS
ALTERNATE
OUTPUT
From on-chip peripheral
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
56/123
ST7FOXA0
8.2.4
I/O ports
Analog alternate function
Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled
by the ADC registers) switches the analog voltage present on the selected pin to the
common analog rail, connected to the ADC input.
Analog Recommendations
Do not change the voltage level or loading on any I/O while conversion is in progress. Do not
have clocking pins located close to a selected analog pin.
Caution:
The analog input voltage level must be within the limits stated in the absolute maximum
ratings.
8.3
I/O port implementation
)
s
(
ct
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific I/O port features such as ADC input or open drain.
u
d
o
r
P
e
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 27.
Other transitions are potentially risky and should be avoided, since they may present
unwanted side-effects such as spurious interrupt generation.
t
e
l
o
s
b
O
Figure 27. Interrupt I/O port state transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
)
(s
t
c
u
XX
= DDR, OR
8.4
d
o
r
P
e
Unused I/O pins
s
b
O8.5
t
e
l
o
Unused I/O pins must be connected to fixed voltage levels. Refer to Section 12.8: I/O port
pin characteristics.
Low power modes
s
Table 16.
Effect of low power modes on I/O ports
Mode
Description
Wait
No effect on I/O ports. External interrupts cause the device to exit from Wait
mode.
Halt
No effect on I/O ports. External interrupts cause the device to exit from Halt
mode.
57/123
I/O ports
8.6
ST7FOXA0
Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM
instruction).
Table 17.
Description of interrupt events
Interrupt Event
Event flag
Enable
Control bit
Exit from
Wait
Exit from
Halt
External interrupt on selected
external event
-
DDRx
ORx
Yes
Yes
)
s
(
ct
See application notes AN1045 software implementation of I2C bus master, and AN1048 software LCD driver
8.7
Device-specific I/O port configuration
r
P
e
The I/O port register configurations are summarized in Table 18.
Table 18.
t
e
l
o
Port configuration
Input (DDR=0)
Port
Pin name
OR = 0
PA0:2, PA4:5 (1)
Port A
PA3
floating
)
(s
(2)
-
s
b
O
u
d
o
Output (DDR=1)
OR = 1
OR = 0
OR = 1
pull-up interrupt (1)
open drain
push-pull
-
open drain
push-pull
t
c
u
1. IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in HALT and AWUFH modes. Refer
to 11.3.2: External Interrupt Control Register 2 (EICR2) on page 91.
2. After reset, to configure PA3 as a general purpose output, the application has to program the MUXCR0
and MUXCR1 registers. See Section 6.3.6: Multiplexed IO reset control register 1 (MUXCR1) on page 34
and Section 6.3.7: Multiplexed IO reset control register 0 (MUXCR0) on page 34
P
e
Table 19.
let
Address
o
s
b
O
58/123
d
o
r
I/O port register map and reset values
Register
Label
7
6
5
4
3
2
1
0
0000h
PADR
Reset
Value
MSB
0
0
0
0
0
0
0
LSB
0
0001h
PADDR
Reset
Value
MSB
0
0
0
0
1
0
0
LSB
0
0002h
PAOR
Reset
Value
MSB
0
0
0
0
0
0
1
LSB
0
(Hex.)
ST7FOXA0
9
On-chip peripherals
On-chip peripherals
9.1
9.1.1
Lite Timer (LT)
Introduction
The Lite Timer can be used for general-purpose timing functions. It is based on a freerunning 13-bit upcounter with two software-selectable timebase periods, an 8-bit input
capture register and watchdog function.
9.1.2
)
s
(
ct
Main features
●
u
d
o
●
Real-time Clock
–
13-bit upcounter
–
1 ms or 2 ms timebase period (@ 8 MHz fOSC)
–
Maskable timebase interrupt
t
e
l
o
Input Capture
●
r
P
e
s
b
O
–
8-bit input capture register (LTICR)
–
Maskable interrupt with wakeup from Halt Mode capability
Watchdog
)
(s
–
Enabled by hardware or software (configurable by option byte)
–
Optional reset on HALT instruction (configurable by option byte)
–
Automatically resets the device unless disable bit is refreshed
–
Software reset (Forced Watchdog reset)
–
Watchdog reset status flag
t
c
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O
59/123
On-chip peripherals
ST7FOXA0
Figure 28. Lite timer block diagram
fLTIMER
To 12-bit AT TImer
fWDG
fOSC
13-bit UPCOUNTER
LTICR
/2
1
fLTIMER
0
WATCHDOG
Timebase
1 or 2 ms
(@ 8 MHz
fOSC)
8 MSB
)
s
(
ct
8-bit
INPUT CAPTURE
REGISTER
LTIC
u
d
o
LTCSR
ICIE
ICF
TB
TBF WDG
RF
TBIE
r
P
e
7
let
9.1.3
WATCHDOG RESET
o
s
b
WDGE WDGD
0
LTTB INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
O
)
Functional description
s
(
t
c
The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it
starts incrementing from 0 at a frequency of fOSC. A counter overflow event occurs when the
counter rolls over from 1F3Fh to 00h. If fOSC = 8 MHz, then the time period between two
counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the
LTCSR register.
u
d
o
r
P
e
When the timer overflows, the TBF bit is set by hardware and an interrupt request is
generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register.
t
e
l
o
9.1.4
s
b
O
Watchdog
The watchdog is enabled using the WDGE bit. The normal Watchdog timeout is 2 ms
(@ fosc = 8 MHz), after which it then generates a reset.
To prevent this watchdog reset occurring, software must set the WDGD bit. The WDGD bit is
cleared by hardware after tWDG. This means that software must write to the WDGD bit at
regular intervals to prevent a watchdog reset occurring. Refer to Figure 29.
If the watchdog is not enabled immediately after reset, the first watchdog timeout will be
shorter than 2 ms, because this period is counted starting from reset. Moreover, if a 2 ms
period has already elapsed after the last MCU reset, the watchdog reset will take place as
soon as the WDGE bit is set. For these reasons, it is recommended to enable the Watchdog
immediately after reset.
A Watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced
watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the
WDGRF bit has to be set.
60/123
ST7FOXA0
On-chip peripherals
The WDGRF bit also acts as a flag, indicating that the Watchdog was the source of the
reset. It is automatically cleared after it has been read.
Caution:
Once the WDGRF bit is set, if the watchdog is enabled, the microcontoller is immediatly
reset, even if the WDGD bit is set by software.
Hardware Watchdog Option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGE bit in the LTCSR is not used.
Refer to the Option Byte description in the "device configuration and ordering information"
section.
Using Halt Mode with the Watchdog (option)
)
s
(
ct
If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be
used when the watchdog is enabled.
u
d
o
In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite
Timer stops counting and is no longer able to generate a Watchdog reset until the
microcontroller receives an external interrupt or a reset.
r
P
e
If an external interrupt is received, the WDG restarts counting after 256 or 512 CPU clocks.
If a reset is generated, the Watchdog is disabled (reset state).
t
e
l
o
If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
)
(s
s
b
O
Figure 29. Watchdog timing diagram
ct
u
d
o
fWDG
r
P
e
HARDWARE CLEARS
WDGD BIT
tWDG
(2 ms @ 8 MHz fOSC)
WDGD BIT
s
b
O
t
e
l
o
9.1.5
INTERNAL
WATCHDOG
RESET
SOFTWARE SETS
WDGD BIT
WATCHDOG RESET
Input capture
The 8-bit input capture register is used to latch the free-running upcounter after a rising or
falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and
the LTICR register contains the MSB of the free-running upcounter. An interrupt is
generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.
An overflow can be detected through the timebase event. This overflow occurs when the
counter rolls over from 1F3Fh to 00h, that is, from F9h to 00h if only the 8 MSB of the LTIC
counter are taken into account. In this case, the TB bit in the LTCSR register must be reset
to detect all overflows.
The LTICR is a read only register and always contains the data from the last input capture.
Input capture is inhibited if the ICF bit is set.
61/123
On-chip peripherals
9.1.6
ST7FOXA0
Low power modes
Table 20.
9.1.7
Effect on Lite timer
Mode
Description
Wait
Active-halt
Halt
No effect on Lite timer
No effect on Lite timer
Lite timer stops counting
Interrupts
Table 21.
Interrupt events
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Timebase event
TBF
TBIE
Yes
No
IC Event
ICF
ICIE
Yes
du
Yes
ro
No
P
e
Note:
)
s
(
ct
Exit
from
Active-Halt
No
The TBF and ICF interrupt events are connected to separate interrupt vectors (see
Interrupts chapter). They generate an interrupt if the enable bit is set in the LTCSR register
and the interrupt mask in the CC register is reset (RIM instruction).
t
e
l
o
s
b
O
Figure 30. Input capture timing diagram
)
(s
125ns
(@ 8MHz fOSC)
t
c
u
fCPU
od
fOSC
Pr
13-bit COUNTER
ete
ol
s
b
O
9.1.8
0001h
0002h
0003h
0004h
0005h
0006h
0007h
CLEARED
BY S/W
READING
LTIC REGISTER
LTIC PIN
ICF FLAG
LTICR REGISTER
xxh
07h
04h
t
Register description
Lite Timer Control/Status Register (LTCSR)
Reset Value: 0000 0x00 (0xh)
7
ICIE
0
ICF
TB
TBIE
TBF
Read/Write
62/123
WDGRF
WDGE
WDGD
ST7FOXA0
On-chip peripherals
Bit 7 = ICIE Interrupt Enable.
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software by reading the LTICR register. Writing to
this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
Note:
After an MCU reset, software must initialize the ICF bit by reading the LTICR register
)
s
(
ct
Bit 5 = TB Timebase period selection.
This bit is set and cleared by software.
u
d
o
0: Timebase period = tOSC * 8000 (1 ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2 ms @ 8 MHz)
r
P
e
Bit 4 = TBIE Timebase Interrupt enable.
This bit is set and cleared by software.
t
e
l
o
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
Bit 3 = TBF Timebase Interrupt Flag.
s
b
O
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
)
(s
0: No counter overflow
t
c
u
1: A counter overflow has occurred
d
o
r
Bit 2 = WDGRF Force Reset/ Reset Status Flag
This bit is used in two ways: it is set by software to force a watchdog reset. It is set by
hardware when a watchdog reset occurs. It can be cleared by software after a read
access to the LTCSR register.
P
e
s
b
O
t
e
l
o
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog reset occurred (read).
Bit 1 = WDGE Watchdog Enable
This bit is set and cleared by software.
0: Watchdog disabled
1: Watchdog enabled
Bit 0 = WDGD Watchdog Reset Delay
This bit is set by software. It is cleared by hardware at the end of each tWDG period.
0: Watchdog reset not delayed
1: Watchdog reset delayed
63/123
On-chip peripherals
ST7FOXA0
Lite Timer Input Capture Register (LTICR)
Reset Value: 0000 0000 (00h)
7
ICR7
0
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
ICR0
Read only
Bits 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by hardware after a reset. If the ICF bit in
the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or
falling edge occurs on the LTIC pin.
Table 22.
Address
(Hex.)
Register
Label
7
6
5
4
3
0B
LTCSR
Reset Value
ICIE
0
ICF
0
TB
0
TBIE
0
TBF
0
0C
LTICR
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
)
(s
t
c
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s
b
O
64/123
)
s
(
ct
Lite timer register map and reset values
b
O
l
o
s
ete
du
2
o
r
P
ICR3
0
WDGRF
x
ICR2
0
1
0
WDGE WDGD
0
0
ICR1
0
ICR0
0
ST7FOXA0
On-chip peripherals
9.2
12-bit Autoreload Timer (AT)
9.2.1
Introduction
The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based
on a free-running 12-bit upcounter with a PWM output channel.
Main Features
●
12-bit upcounter with 12-bit autoreload register (ATR)
●
Maskable overflow interrupt
●
PWM signal generator
●
Frequency range 2KHz-4MHz (@ 8 MHz fCPU)
Programmable duty-cycle
–
Polarity control
–
Maskable Compare interrupt
u
d
o
r
P
e
Output Compare Function
Figure 31. Block diagram
7 ATCSR
0
0
Pr
DCR0H
DCR0L
Preload
Preload
ol
9.2.3
CK0
12-BIT DUTY CYCLE VALUE (shadow)
OVF INTERRUPT
REQUEST
0
OVF OVFIE CMPIE
-O
CMP INTERRUPT
REQUEST
CMPF0
fCOUNTER
12-BIT UPCOUNTER
Update on OVF Event
CNTR
12-BIT AUTORELOAD VALUE
ATR
OE0 bit
OE0 bit CMPF0 bit
0
on OVF Event
IF OE0=1
t
e
l
o
bs
CK1
u
d
o
fCPU
ete
0
)
s
(
ct
fLTIMER
(1 ms timebase
@ 8MHz)
s
b
O
)
s
(
ct
1
COMPPARE
OP0 bit
fPWM POLARITY
OUTPUT CONTROL
●
–
PWM GENERATION
9.2.2
PWM0
Functional description
PWM Mode
This mode allows a Pulse Width Modulated signals to be generated on the PWM0 output pin
with minimum core processing overhead. The PWM0 output signal can be enabled or
disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is
configured as output push-pull alternate function.
Note:
CMPF0 is available in PWM mode (see PWM0CSR description on page 71).
65/123
On-chip peripherals
ST7FOXA0
PWM Frequency and Duty Cycle
The PWM signal frequency (fPWM) is controlled by the counter period and the ATR register
value.
fPWM = fCOUNTER / (4096 - ATR)
Following the above formula, if fCPU is 8 MHz, the maximum value of fPWM is 4 Mhz (ATR
register value = 4094), and the minimum value is 2 kHz (ATR register value = 0).
Note:
The maximum value of ATR is 4094 because it must be lower than the DCR value which
must be 4095 in this case.
At reset, the counter starts counting from 0.
Software must write the duty cycle value in the DCR0H and DCR0L preload registers. The
DCR0H register must be written first. See caution below.
)
s
(
ct
When a upcounter overflow occurs (OVF event), the ATR value is loaded in the upcounter,
the preloaded Duty cycle value is transferred to the Duty Cycle register and the PWM0
signal is set to a high level. When the upcounter matches the DCRx value the PWM0 signals
is set to a low level. To obtain a signal on the PWM0 pin, the contents of the DCR0 register
must be greater than the contents of the ATR register.
u
d
o
r
P
e
t
e
l
o
The polarity bit can be used to invert the output signal.
The maximum available resolution for the PWM0 duty cycle is:
Resolution = 1 / (4096 - ATR)
s
b
O
Note:
To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum
resolution and assuming that DCR=ATR, a 0% or 100% duty cycle can be obtained by
changing the polarity.
Caution:
As soon as the DCR0H is written, the compare function is disabled and will start only when
the DCR0L value is written. If the DCR0H write occurs just before the compare event, the
signal on the PWM output may not be set to a low level. In this case, the DCRx register
should be updated just after an OVF event. If the DCR and ATR values are close, then the
DCRx register should be updated just before an OVF event, in order not to miss a compare
event and to have the right signal applied on the PWM output.
)
(s
t
c
u
d
o
r
P
e
t
e
l
o
Figure 32. PWM function
COUNTER
s
b
O
4095
DUTY CYCLE
REGISTER
(DCR0)
AUTO-RELOAD
REGISTER
(ATR)
PWM0 OUTPUT
000
66/123
WITH OE0=1
AND OP0=0
WITH OE0=1
AND OP0=1
t
ST7FOXA0
On-chip peripherals
Figure 33. PWM Signal example
fCOUNTER
PWM0 OUTPUT
WITH OE0=1
AND OP0=0
ATR= FFDh
COUNTER
FFDh
FFEh
FFFh
FFDh
FFEh
FFFh
FFDh
FFEh
DCR0=FFEh
t
Output Compare Mode
To use this function, the OE bit must be 0, otherwise the compare is done with the shadow
register instead of the DCRx register. Software must then write a 12-bit value in the DCR0H
and DCR0L registers. This value will be loaded immediately (without waiting for an OVF
event).
)
s
(
ct
u
d
o
The DCR0H must be written first, the output compare function starts only when the DCR0L
value is written.
r
P
e
When the 12-bit upcounter (CNTR) reaches the value stored in the DCR0H and DCR0L
registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is
generated if the CMPIE bit is set.
t
e
l
o
Note:
The output compare function is only available for DCRx values other than 0 (reset value).
Caution:
At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L value
has not yet been written (in this case, the shadow register will contain the new DCR0H value
and the old DCR0L value), then:
- If OE=1 (PWM mode): the compare is done between the timer counter and the shadow
register (and not DCRx)
- if OE=0 (OCMP mode): the compare is done between the timer counter and DCRx. There
is no PWM signal. The compare between DCRx or the shadow register and the timer
counter is locked until DCR0L is written.
)
(s
s
b
O
t
c
u
d
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s
b
O
67/123
On-chip peripherals
9.2.4
ST7FOXA0
Low power modes
9.2.5
Mode
Description
Slow
The input frequency is divided by 32
Wait
No effect on AT timer
Active-Halt
AT timer halted except if CK0=1, CK1=0 and OVFIE=1
Halt
AT timer halted
Interrupts
Interrupt Event 1)
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Overflow Event
OVF
OVFIE
Yes
No
CMP Event
CMPFx
CMPIE
Yes
No
Note:
9.2.6
)
s
(
ct
Exit
from
Active-Halt
du
P
e
ro
Yes2)
No
1
The interrupt events are connected to separate interrupt vectors (see Interrupts chapter).
They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt
mask in the CC register is reset (RIM instruction).
2
only if CK0=1 and CK1=0
Register description
t
e
l
o
s
b
O
)
(s
TImer Control Status Register (ATCSR)
t
c
u
Reset Value: 0000 0000 (00h)
7
d
o
r
0
0
0
0
CK1
P
e
t
e
l
o
CK0
OVF
OVFIE
CMPIE
Read/Write
Bits 7:5 = Reserved, must be kept cleared.
s
b
O
Bits 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and cleared by hardware after a reset. They
select the clock frequency of the counter.
Table 23.
68/123
Counter clock selection
Counter Clock Selection
CK1
CK0
OFF
0
0
fLTIMER (1 ms timebase @ 8 MHz)
0
1
fCPU
1
0
Reserved
1
1
ST7FOXA0
On-chip peripherals
Bit 2 = OVF Overflow Flag.
This bit is set by hardware and cleared by software by reading the ATCSR register. It
indicates the transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
Caution:
When set, the OVF bit stays high for 1 fCOUNTER cycle (up to 1ms depending on the clock
selection) after it has been cleared by software.
Bit 1 = OVFIE Overflow Interrupt Enable.
This bit is read/write by software and cleared by hardware after a reset.
0: OVF interrupt disabled
1: OVF interrupt enabled
)
s
(
ct
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and clear by hardware after a reset. It allows to mask
the interrupt generation when CMPF bit is set.
0: CMPF interrupt disabled
1: CMPF interrupt enabled
u
d
o
r
P
e
Counter register high (CNTRH)
t
e
l
o
Reset Value: 0000 0000 (00h)
bs
15
0
0
0
0
O
)
CN11
8
CN10
CN9
CN8
Read only
s
(
t
c
Counter register low (CNTRL)
u
d
o
Reset value: 0000 0000 (00h)
7
Pr
CN7
e
t
e
ol
O
bs
CN6
0
CN5
CN4
CN3
CN2
CN1
CN0
Read only
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = CNTR[11:0] Counter Value.
This 12-bit register is read by software and cleared by hardware after a reset. The
counter is incremented continuously as soon as a counter clock is selected. To obtain
the 12-bit value, software should read the counter value in two consecutive read
operations. As there is no latch, it is recommended to read LSB first. In this case,
CNTRH can be incremented between the two read operations and to have an accurate
result when ftimer=fCPU, special care must be taken when CNTRL values close to FFh
are read.
When a counter overflow occurs, the counter restarts from the value specified in the
ATR register.
69/123
On-chip peripherals
ST7FOXA0
Auto reload register high (ATRH)
Reset value: 0000 0000 (00h)
15
0
8
0
0
0
ATR11
ATR10
ATR9
ATR8
Read/Write
Auto reload register low (ATRL)
)
s
(
ct
Reset value: 0000 0000 (00h)
7
ATR7
ATR6
ATR5
ATR4
ATR3
ATR1
ATR0
r
P
e
Read/Write
t
e
l
o
Bits 15:12 = Reserved, must be kept cleared.
s
b
O
Bits 11:0 = ATR[11:0] Autoreload Register.
)
(s
u
d
o
ATR2
0
This is a 12-bit register which is written by software. The ATR register value is
automatically loaded into the upcounter when an overflow occurs. The register value is
used to set the PWM frequency.
t
c
u
d
o
r
PWM0 duty cycle register high (DCR0H)
P
e
Reset value: 0000 0000 (00h)
so
let
b
O
15
0
8
0
0
0
DCR11
DCR10
DCR9
DCR8
Read/Write
PWM0 duty cycle register low (DCR0L)
Reset value: 0000 0000 (00h)
7
DCR7
0
DCR6
DCR5
DCR4
Read/Write
70/123
DCR3
DCR2
DCR1
DCR0
ST7FOXA0
On-chip peripherals
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. The high register must be written first.
In PWM mode (OE0=1 in the PWMCR register) the DCR[11:0] bits define the duty
cycle of the PWM0 output signal (see Figure 32). In Output Compare mode, (OE0=0 in
the PWMCR register) they define the value to be compared with the 12-bit upcounter
value.
PWM0 control/status register (PWM0CSR)
Reset value: 0000 0000 (00h)
)
s
(
ct
7
0
0
0
0
0
0
Read/Write
e
t
e
ol
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = OP0 PWM0 Output Polarity.
du
0
OP0
CMPF0
o
r
P
s
b
O
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the polarity of the PWM0 signal.
0: The PWM0 signal is not inverted.
1: The PWM0 signal is inverted.
)
(s
t
c
u
d
o
r
Bit 0 = CMPF0 PWM0 Compare Flag.
This bit is set by hardware and cleared by software by reading the PWM0CSR register.
It indicates that the upcounter value matches the DCR0 register value.
0: Upcounter value does not match DCR value.
1: Upcounter value matches DCR value.
P
e
s
b
O
t
e
l
o
PWM output control register (PWMCR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
0
OE0
Read/Write
Bits 7:1 = Reserved, must be kept cleared.
Bit 0 = OE0 PWM0 Output enable.
71/123
On-chip peripherals
ST7FOXA0
This bit is set and cleared by software.
0: PWM0 output Alternate Function disabled (I/O pin free for general purpose I/O)
1: PWM0 output enabled
Table 24.
Address
Register map and reset values
Register
Label
7
6
5
4
3
2
1
0
0D
ATCSR
Reset Value
0
0
0
CK1
0
CK0
0
OVF
0
OVFIE
0
CMPIE
0
0E
CNTRH
Reset Value
0
0
0
0
CN11
0
CN10
0
CN9
0
CN8
0
0F
CNTRL
Reset Value
CN7
0
CN6
0
CN5
0
CN4
0
CN3
0
CN2
0
CN1
0
CN0
0
10
ATRH
Reset Value
0
0
0
0
ATR11
0
ATR10
0
ATR9
0
ATR8
0
11
ATRL
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
12
PWMCR
Reset Value
0
0
0
0
0
0
0
OE0
0
13
PWM0CSR
Reset Value
0
0
0
0
0
0
OP
0
CMPF0
0
17
DCR0H
Reset Value
0
0
0
DCR11
0
DCR10
0
DCR9
0
DCR8
0
18
DCR0L
Reset Value
DCR7
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
(Hex.)
s
b
O
72/123
DCR6
0
u
d
o
r
P
e
t
e
l
o
s
(
t
c
)0
DCR5
0
s
b
O
u
d
o
r
P
e
t
e
l
o
)
s
(
ct
ST7FOXA0
On-chip peripherals
9.3
10-bit A/D converter (ADC)
9.3.1
Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 5
multiplexed analog input channels (refer to device pin out description) that allow the
peripheral to convert the analog voltage levels from up to 5 different sources.
The result of the conversion is stored in a 10-bit Data register. The A/D converter is
controlled through a Control/Status register.
9.3.2
Main features
)
s
(
ct
●
10-bit conversion
●
Up to 5 channels with multiplexed input
●
Linear successive approximation
●
Data register (DR) which contains the results
●
Conversion complete status flag
●
On/off bit (to reduce consumption)
Functional description
)
(s
Analog power supply
r
P
e
t
e
l
o
The block diagram is shown in Figure 34.
9.3.3
u
d
o
s
b
O
VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to
device pin out description) they are internally connected to the VDD and VSS pins.
t
c
u
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of
heavily loaded or badly decoupled power supply lines.
d
o
r
P
e
t
e
l
o
s
b
O
73/123
On-chip peripherals
ST7FOXA0
Figure 34. ADC block diagram
DIV 4
fCPU
DIV 2
1
0
fADC
0
1
SLOW
bit
EOC SPEED ADON
0
CH2
CH1
ADCCSR
CH0
4
AIN0
)
s
(
ct
HOLD CONTROL
RADC
AIN1
ANALOG TO DIGITAL
u
d
o
ANALOG
MUX
CONVERTER
r
P
e
CADC
AINx
ADCDRH
D9
t
e
l
o
D8
bs
ADCDRL
D7
D6
0
0
D5
D4
0
D3
0
D2
SLOW
0
D1
D0
O
)
Digital A/D conversion result
s
(
t
c
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
u
d
o
If the input voltage (VAIN) is greater than VDDA (high-level voltage reference) then the
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
r
P
e
t
e
l
o
If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
bs
O
74/123
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in the Electrical
Characteristics Section.
RAIN is the maximum recommended impedance for an analog input signal. If the impedance
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the alloted time.
ST7FOXA0
On-chip peripherals
Configuring the A/D conversion
The analog input ports must be configured as input, no pull-up, no interrupt (see Section 8:
I/O ports). Using these pins as analog inputs does not affect the ability of the port to be read
as a logic input.
To assign the analog channel to convert, select the CH[2:0] bits in the ADCCSR register.
Set the ADON bit to enable the A/D converter and to start the conversion. From this time on,
the ADC performs a continuous conversion of the selected channel.
When a conversion is complete:
●
The EOC bit is set by hardware.
●
The result is in the ADCDR registers.
)
s
(
ct
A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit.
To read the 10 bits, perform the following steps:
1.
Poll the EOC bit
2.
Read ADCDRL
3.
Read ADCDRH. This clears EOC automatically.
To read only 8 bits, perform the following steps:
u
d
o
r
P
e
t
e
l
o
1.
Poll EOC bit
2.
Read ADCDRH. This clears EOC automatically.
s
b
O
Changing the conversion channel
)
(s
The application can change channels during conversion. When software modifies the
CH[2:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
t
c
u
9.3.4
Low power modes
d
o
r
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
P
e
t
e
l
o
Table 25.
s
b
O
9.3.5
Effect of low power modes on the A/D converter
Mode
Description
Wait
No effect on A/D Converter
Halt
A/D Converter disabled.
After wakeup from Halt mode, the A/D Converter requires a stabilization time
tSTAB (see Electrical Characteristics) before accurate conversions can be
performed.
Interrupts
None.
75/123
On-chip peripherals
9.3.6
ST7FOXA0
Register description
Control/status register (ADCCSR)
Reset value: 0000 0000 (00h)
7
EOC
0
SPEED
ADON
0
0
Read only
CH2
CH1
CH0
Read/write
Bit 7 = EOC End of Conversion bit
This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH
register or writes to any bit of the ADCCSR register.
)
s
(
ct
0: Conversion is not complete
u
d
o
1: Conversion complete
Bit 6 = SPEED ADC clock selection bit
r
P
e
This bit is set and cleared by software. It is used together with the SLOW bit to
configure the ADC clock speed. Refer to the table in the SLOW bit description
(ADCDRL register).
Bit 5 = ADON A/D Converter on bit
s
b
O
This bit is set and cleared by software.
0: A/D converter is switched off
)
(s
1: A/D converter is switched on
t
e
l
o
Bits 4:3 = Reserved, must be kept cleared.
t
c
u
Bits 2:0 = CH[2:0] Channel Selection
These bits select the analog input to convert. They are set and cleared by software.
Table 26.
P
e
d
o
r
t
e
l
o
s
b
O
Channel selection using CH[2:0]
Channel Pin(1)
CH2
CH1
CH0
AIN0
0
0
0
AIN1
0
0
1
AIN2
0
1
0
AIN3
0
1
1
AIN4
1
0
0
1. The number of channels is device dependent. Refer to the device pinout description.
Data register High (ADCDRH)
Reset value: xxxx xxxx (xxh)
7
D9
0
D8
D7
D6
D5
Read only
76/123
D4
D3
D2
ST7FOXA0
On-chip peripherals
Bits 7:0 = D[9:2] MSB of Analog Converted Value
ADC Control/data register Low (ADCDRL)
Reset value: 0000 00xx (0xh)
7
0
0
0
0
0
SLOW
0
D1
D0
Read/write
Bits 7:4 = Reserved. Forced by hardware to 0.
Bit 3 = SLOW Slow mode bit
)
s
(
ct
This bit is set and cleared by software. It is used together with the SPEED bit in the
ADCCSR register to configure the ADC clock speed as shown on the table below.
Table 27.
u
d
o
Configuring the ADC clock speed
Pr
fADC(1)
fCPU/2
e
t
e
ol
fCPU
fCPU/4
s
b
O
SLOW
SPEED
0
0
0
1
1
x
1. The maximum allowed value of fADC is 4 MHz (see Section 12.10 on page 108)
Bits 1:0 = D[1:0] LSB of Analog Converted value
Table 28.
t
c
u
Address
Register
label
7
ADCCSR
Reset Value
d
o
r
EOC
0
0037h
ADCDRH
Reset Value
D9
x
D8
x
0038h
ADCDRL
Reset Value
0
0
0
0
(Hex.)
0036h
P
e
t
e
l
o
s
b
O
)
(s
ADC register mapping and reset values
6
5
4
3
2
1
0
0
0
0
0
CH2
0
CH1
0
CH0
0
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
0
0
0
SLOW
0
0
D1
x
D0
x
SPEED ADON
0
0
77/123
Instruction set
ST7FOXA0
10
Instruction set
10.1
ST7 addressing modes
The ST7 core features 17 different addressing modes which can be classified in seven main
groups:
Table 29.
Description of addressing modes
Addressing mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
)
s
(
ct
u
d
o
r
P
e
Relative
jrne loop
Bit operation
t
e
l
o
bset
byte,#5
The ST7 instruction set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be subdivided in two submodes
called long and short:
s
b
O
●
Long addressing mode is more powerful because it can use the full 64 Kbyte address
space, however it uses more bytes and more CPU cycles.
●
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
)
(s
t
c
u
d
o
r
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 30.
P
e
ST7 addressing mode overview
t
e
l
o
Mode
Syntax
bs
O
Destination/
source
Pointer
address
Pointer
size
Length
(bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No Offset
Direct
Indexed
ld A,(X)
00..FF
+ 0 (with X register)
+ 1 (with Y register)
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed
ld A,($1000,X)
0000..FFFF
+2
Short
Indirect
ld A,[$10]
00..FF
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect
ld A,([$10],X)
00..1FE
00..FF
byte
+2
78/123
Indexed
ST7FOXA0
Table 30.
Instruction set
ST7 addressing mode overview (continued)
Syntax
Destination/
source
Pointer
address
Pointer
size
Length
(bytes)
ld
A,([$10.w],X)
0000..FFFF
00..FF
word
+2
Mode
1.
Long
Indirect
Indexed
Relative
Direct
jrne loop
PC128/PC+127(1)
Relative
Indirect
jrne [$10]
PC128/PC+127(1)
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
Relative
btjt
$10,#7,skip
00..FF
Bit
Indirect
Relative
btjt
[$10],#7,skip
00..FF
+1
00..FF
byte
+2
+1
00..FF
byte
+2
)
s
(
ct
+2
00..FF
u
d
o
byte
+3
r
P
e
At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
10.1.1
t
e
l
o
Inherent mode
All Inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Table 31.
Instruction
)-
s
(
t
c
NOP
s
b
O
Pr
Function
No operation
TRAP
S/W interrupt
WFI
Wait for interrupt (low power mode)
HALT
Halt oscillator (lowest power mode)
RET
Subroutine return
IRET
Interrupt subroutine return
SIM
Set interrupt mask
RIM
Reset interrupt mask
SCF
Set carry flag
RCF
Reset carry flag
RSP
Reset stack pointer
LD
Load
CLR
Clear
PUSH/POP
Push/Pop to/from the stack
INC/DEC
Increment/decrement
TNZ
Test negative or zero
CPL, NEG
1 or 2 complement
u
d
o
e
t
e
ol
s
b
O
Instructions supporting inherent addressing mode
79/123
Instruction set
ST7FOXA0
Table 31.
10.1.2
Instructions supporting inherent addressing mode (continued)
Instruction
Function
MUL
Byte multiplication
SLL, SRL, SRA, RLC, RRC
Shift and rotate operations
SWAP
Swap nibbles
Immediate mode
Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte
contains the operand value.
Imm
Table 32.
Immediate Instruction
Function
LD
Load
u
d
o
r
P
e
CP
Compare
BCP
Bit compare
let
AND, OR, XOR
ADC, ADD, SUB, SBC
10.1.3
)
s
(
ct
Instructions supporting inherent immediate addressing mode
Direct modes
o
s
b
Logical operations
Arithmetic operations
O
)
In Direct instructions, the operands are referenced by their memory address.
s
(
t
c
The direct addressing mode consists of two submodes:
Direct (Short) addressing mode
u
d
o
The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF
addressing space.
r
P
e
Direct (Long) addressing mode
t
e
l
o
s
b
O
10.1.4
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after
the opcode.
Indexed modes (No Offset, Short, Long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three submodes:
Indexed mode (No Offset)
There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space.
Indexed mode (Short)
The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE
addressing space.
80/123
ST7FOXA0
Instruction set
Indexed mode (Long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the
opcode.
10.1.5
Indirect modes (Short, Long)
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two
submodes:
Indirect mode (Short)
)
s
(
ct
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing
space, and requires 1 byte after the opcode.
u
d
o
Indirect mode (Long)
r
P
e
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
10.1.6
t
e
l
o
Indirect indexed modes (Short, Long)
s
b
O
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
)
(s
The indirect indexed addressing mode consists of two submodes:
t
c
u
Indirect indexed mode (Short)
d
o
r
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing
space, and requires 1 byte after the opcode.
P
e
Indirect indexed mode (Long)
s
b
O
t
e
l
o
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
Table 33.
Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes
Instructions
Function
Long and short instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical operations
ADC, ADD, SUB, SBC
Arithmetic addition/subtraction operations
BCP
Bit compare
81/123
Instruction set
ST7FOXA0
Table 33.
Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes (continued)
Instructions
Function
Short instructions only
10.1.7
CLR
Clear
INC, DEC
Increment/decrement
TNZ
Test negative or zero
CPL, NEG
1 or 2 complement
BSET, BRES
Bit operations
BTJT, BTJF
Bit test and jump operations
SLL, SRL, SRA, RLC, RRC
Shift and rotate operations
SWAP
Swap nibbles
CALL, JP
Call or jump subroutine
)
s
(
ct
u
d
o
Relative modes (direct, indirect)
r
P
e
t
e
l
o
This addressing mode is used to modify the PC register value by adding an 8-bit signed
offset to it.
Table 34.
s
b
O
Instructions supporting relative modes
)-
Available Relative Direct/Indirect instructions
t(s
JRxx
c
u
d
CALLR
Function
Conditional jump
Call relative
The relative addressing mode consists of two submodes:
o
r
P
Relative mode (Direct)
e
t
e
ol
The offset follows the opcode.
Relative mode (Indirect)
s
b
O
82/123
The offset is defined in memory, of which the address follows the opcode.
ST7FOXA0
10.2
Instruction set
Instruction groups
The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Table 35.
ST7 instruction set
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
Increment/decrement
INC
DEC
Compare and tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit operation
BSET
BRES
Conditional bit test and branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and rotate
SLL
SRL
SRA
RLC
Unconditional jump or call
JRA
JRT
JRF
JP
Conditional branch
JRxx
Pr
Interruption management
TRAP
WFI
HALT
IRET
Condition Code Flag modification
SIM
RIM
SCF
RCF
RSP
bs
e
t
e
ol
)
s
(
ct
u
d
o
RRC
SWAP
SLA
CALL
CALLR
NOP
RET
O
)
Using a prebyte
The instructions are described with 1 to 4 bytes.
s
(
t
c
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
u
d
o
r
P
e
The whole instruction becomes by:
PC-2 End of previous instruction
b
O
so
let
PC-1 Prebyte
PC Opcode
PC+1 Additional word (0 to 2) according to the number of bytes required to compute
the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using
indirect X indexed addressing mode.
PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
83/123
Instruction set
10.2.1
ST7FOXA0
Illegal opcode reset
In order to provide enhanced robustness to the device against unexpected behavior, a
system of illegal opcode detection is implemented: a reset is generated if the code to be
executed does not correspond to any opcode or prebyte value. This, combined with the
Watchdog, allows the detection and recovery from an unexpected fault or interference.
A valid prebyte associated with a valid opcode forming an unauthorized combination does
not generate a reset.
Table 36.
I
Illegal opcode detection
Mnemo
Description
Function/Example
Dst
Src
H
ADC
Add with Carry
A=A+M+C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A, Memory
tst (A . M)
A
M
N
Z
BRES
Bit Reset
bres Byte, #3
M
BSET
Bit Set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1
M
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1
M
CALL
Call subroutine
CALLR
Call subroutine relative
CLR
Clear
CP
Arithmetic Compare
CPL
One Complement
DEC
Decrement
HALT
Halt
IRET
Interrupt routine return
Pop CC, A, X, PC
Increment
inc X
Absolute Jump
jp [TBL.w]
e
t
e
ol
INC
JP
s
b
O
JRA
t
c
u
od
Pr
)
(s
N
Z
C
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
C
C
s
b
O
reg, M
M
0
1
N
Z
C
1
tst(Reg - M)
reg
A = FFH-A
reg, M
N
Z
dec Y
reg, M
N
Z
N
Z
N
Z
0
Jump relative always
JRT
Jump relative
JRF
Never jump
JRIH
Jump if ext. interrupt = 1
JRIL
Jump if ext. interrupt = 0
JRH
Jump if H = 1
H=1?
JRNH
Jump if H = 0
H=0?
JRM
Jump if I = 1
I=1?
JRNM
Jump if I = 0
I=0?
JRMI
Jump if N = 1 (minus)
N=1?
84/123
I
jrf *
H
reg, M
I
C
ST7FOXA0
Table 36.
Instruction set
Illegal opcode detection (continued)
Mnemo
Description
Function/Example
JRPL
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned >=
JRUGT
Jump if (C + Z = 0)
Unsigned >
JRULE
Jump if (C + Z = 1)
Unsigned
