ST7SCR1E4, ST7SCR1R4
8-bit low-power, full-speed USB MCU with 16-Kbyte Flash,
768-byte RAM, smartcard interface and timer
Datasheet − production data
Features
Memories
■
Up to 16 Kbytes of ROM or High Density Flash
(HDFlash) program memory with read/write
protection, HDFlash In-Circuit and In-Application
Programming. 100 write/erase cycles
guaranteed, data retention: 40 years at 55°C
SO24
LQFP64 14x14
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ISO7816-3 UART interface
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4 MHz clock generation
■
Synchronous/Asynchronous protocols
(T=0, T=1)
Clock, reset and supply management
■
Automatic retry on parity error
■
Low voltage reset
■
■
2 power saving modes: Halt and Wait modes
Programmable baud rate from 372 clock
pulses up to 11.625 clock pulses (D=32/F=372)
■
PLL for generating 48 MHz USB clock using a
4 MHz crystal
■
Card Insertion/Removal Detection
■
Up to 768 bytes of RAM including up to 128
bytes stack and 256 bytes USB buffer
Interrupt management
■
Nested Interrupt controller
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Smartcard power supply
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Selectable card VCC 1.8V, 3V, and 5V
■
Internal step-up converter for 5V supplied
Smartcards (with a current of up to 55mA)
using only two external components.
■
Programmable Smartcard Internal Voltage
Regulator (1.8V to 3.0V) with current overload
protection and 4 KV ESD protection (Human
Body Model) for all Smartcard Interface I/Os
USB (Universal Serial Bus) interface
■
256-byte buffer for full speed bulk, control and
interrupt transfer types compliant with USB
specification (version 2.0)
■
On-Chip 3.3V USB voltage regulator and
transceivers with software power-down
■
7 USB endpoints:
– One 8-byte Bidirectional Control Endpoint
– One 64-byte In Endpoint,
– One 64-byte Out Endpoint
– Four 8-byte In Endpoints
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35 or 4 I/O ports
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Up to 4 LED outputs with software
programmable constant current (3 or 7 mA).
■
2 General purpose I/Os programmable as
interrupts
■
Up to 8 line inputs programmable as interrupts
■
Up to 20 outputs
■
1 line assigned by default as static input after
reset
July 2012
This is information on a product in full production.
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One 8-bit timer
■
Time Base Unit (TBU) for generating periodic
interrupts.
Development tools
■
Full hardware/software development package
ECOPACK® packages
Table 1.
Device summary
Reference
Part number
ST7SCR1R4
ST7FSCR1T1, ST7SCR1T1
ST7SCR1E4
ST7FSCR1M1, ST7SCR1M1,
ST7SCR1U1
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www.st.com
1
Contents
ST7SCR1E4, ST7SCR1R4
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4
ICP (In-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5
IAP (In-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6
Program memory read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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4.1
Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.2
External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2
Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3
Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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7.4
Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.5
Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.2
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.3
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.3
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.4
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9.3.1
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.3.2
Ports B and D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.3.3
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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12.2
Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.1.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.1.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.1.4
Software watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.1.5
Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.1.6
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.1.7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.1.8
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Time base unit (TBU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.2.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12.2.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12.2.4
Programming example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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Contents
ST7SCR1E4, ST7SCR1R4
12.3
12.4
13
12.2.5
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.2.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.2.7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
USB interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.3.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.3.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.3.4
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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Smartcard interface (CRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.4.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.4.4
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13.1
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CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13.1.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
13.1.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
13.1.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
13.1.4
Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
13.1.6
Indirect indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.1.7
Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.3
Supply and reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
14.4
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
14.5
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13.1.5
14.4.1
General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
14.4.2
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
14.4.3
Crystal resonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
14.5.1
RAM and hardware registers
14.5.2
FLASH memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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ST7SCR1E4, ST7SCR1R4
14.6
Smartcard supply supervisor electrical characteristics . . . . . . . . . . . . . 103
14.7
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
14.8
14.7.1
Functional EMS (Electro magnetic susceptibility) . . . . . . . . . . . . . . . . 105
14.7.2
Electro magnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . 106
14.7.3
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 106
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 107
14.8.1
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Contents
USB - Universal bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
16
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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15.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
15.2
Recommended reflow oven profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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Device configuration and ordering information . . . . . . . . . . . . . . . . . 111
16.0.1
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
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Device ordering information and transfer of customer code . . . . . . . . . . 112
16.2
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
16.3
ST7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
16.4
Important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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16.4.1
Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
16.4.2
Flash devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
16.4.3
Smart card UART automatic repetition and retry . . . . . . . . . . . . . . . . . 119
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
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List of tables
ST7SCR1E4, ST7SCR1R4
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Detailed device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Hardware register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Sectors available in FLASH devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Recommended values for 4 MHz crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Current interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Interrupt vectors and corresponding bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I/O pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Port A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Port B and D description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Port C description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
I/O ports register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Watchdog timing (fCPU = 8 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Instructions supporting direct, indexed, indirect and indirect indexed addressing modes . 91
Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Current injection on i/o port and control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
I/O port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
LED pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Low voltage detector and supervisor (LVDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Typical crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Dual voltage flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Smartcard supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
USB: Full speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ST7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
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ST7SCR1E4, ST7SCR1R4
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
ST7SCR block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
64-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
24-Pin SO package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
24-lead QFN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Smartcard interface reference application - 24-pin SO package . . . . . . . . . . . . . . . . . . . . 14
Smartcard interface reference application - 64-Pin LQFP package . . . . . . . . . . . . . . . . . . 15
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Typical ICP interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
External clock source connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LVD RESET sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Watchdog RESET sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
WAIT mode flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
HALT mode flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PA0, PA1, PA2, PA3, PA4, PA5 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PA6 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Port B and D configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Port C configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
TBU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
USB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Endpoint buffer size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Smartcard interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Compensation mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Waiting time counter example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Card detection block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Card deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Card voltage selection and power OFF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Power off timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Card clock selection block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Smartcard I/O pin structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Typical application with a crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Two typical applications with VPP pin1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
USB: Data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
64-pin low profile quad flat package (14x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
24-pin plastic small outline package, 300-mil width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Sales type coding rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ST7SCR microcontroller option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Revision marking on box label and device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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Description
1
ST7SCR1E4, ST7SCR1R4
Description
The ST7SCR and ST7FSCR devices are members of the ST7 microcontroller family
designed for USB applications. All devices are based on a common industry-standard 8-bit
core, featuring an enhanced instruction set.
The ST7SCR ROM devices are factory-programmed and are not reprogrammable.
The ST7FSCR versions feature dual-voltage Flash memory with Flash Programming
capability.
They operate at a 4 MHz external oscillator frequency.
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Under software control, all devices can be placed in WAIT or HALT mode, reducing power
consumption when the application is in idle or stand-by state.
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The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
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The devices include an ST7 core, up to 16 Kbytes of program memory, up to 512 bytes of
user RAM, up to 35 I/O lines and the following on-chip peripherals:
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USB full speed interface with 7 endpoints, programmable in/out configuration and
embedded 3.3V voltage regulator and transceivers (no external components are
needed).
●
ISO7816-3 UART interface with programmable baud rate from 372 clock pulses up to
11.625 clock pulses
●
Smartcard Supply Block able to provide programmable supply voltage and I/O voltage
levels to the smartcards
●
Low voltage reset ensuring proper power-on or power-off of the device (selectable by
option)
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Table 2.
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Watchdog timer
8-bit timer (TBU)
Detailed device summary
ST7SCR1R4
ST7SCR1E4
Features
Program memory
ST7FSCR1T1
ST7SCR1T1
ST7FSCR1M1
16 Kbytes
FLASH
16 Kbytes ROM
16 Kbytes
FLASH
User RAM (stack)
bytes
Peripherals
16 Kbytes ROM 16 Kbytes ROM
USB full-speed (7 Ep), TBU, Watchdog timer, ISO7816-3 interface
4.0 to 5.5V
CPU frequency
4 or 8 MHz
Operating temperature
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ST7SCR1U1
768 (128)
Operating supply
Package
ST7SCR1M1
0°C to +70°C
LQFP64
SO24
Doc ID 8951 Rev 6
QFN24
ST7SCR1E4, ST7SCR1R4
Figure 1.
Description
ST7SCR block diagram
OSCIN
4MHz
OSCILLATOR
OSCOUT
PLL
48 MHz
8 MHz
or 4 MHz
DIVIDER
USB
WATCHDOG
ADDRESS AND DATA BUS
USB
DATA
BUFFER
(256 bytes)
USBDP
USBDM
USBVCC
PORT B
PB[7:0]
PORT C
PC[7:0]
CONTROL
VPP
8-BIT CORE
ALU
LVD
RAM
(512 Bytes)
(s)
PROGRAM
MEMORY
(16K Bytes)
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ISO7816 UART
SUPPLY
MANAGER
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LED[3:0]
LED
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PD[7:0]
PORT D
8-BIT TIMER
PA6
PA[5:0]
PORT A
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DC/DC
CONVERTER
DIODE
SELF
CRDVCC
CRDDET
CRDIO
CRDC4
CRDC8
3V/1.8V Vreg
CRDRST
CRDCLK
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Pin description
2
ST7SCR1E4, ST7SCR1R4
Pin description
Figure 2.
64-pin LQFP package pinout
CRDVCC
GND
GNDA
DIODE
SELF1
SELF2
PA5
PA4
NC
NC
LED3
LED2
LED1
VDD
VDDA
USBVcc
NC = Not Connected
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CRDRST
NC
CRDCLK
NC
C4
CRDIO
C8
GND
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
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CRDDET
VDD
WAKUP2/ICCDATA/PA0
WAKUP2/ICCCLK/PA1
WAKUP2/PA2
WAKUP2/PA3
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
OSCIN
OSCOUT
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Figure 3.
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NC
DP
DM
LED0
PA6
VPP
PC7/WAKUP1
PC6/WAKUP1
PC5/WAKUP1
PC4/WAKUP1
PC3/WAKUP1
PC2/WAKUP1
PC1/WAKUP1
PC0/WAKUP1
GND
VDD
24-Pin SO package pinout
SELF
VDD
VDDA
DIODE
GNDA
GND
1
24
2
23
3
22
CRDVCC
4
21
CRDRST
CRDCLK
C4
CRDIO
5
20
USBVcc
DP
6
19
DM
7
18
8
17
LED0
PA6
C8
CRDDET
9
16
VPP
10
15
ICCDATA/WAKUP2/PA0
11
14
ICCCLK/WAKUP2/PA1
12
13
OSCOUT
OSCIN
NC
Doc ID 8951 Rev 6
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ST7SCR1E4, ST7SCR1R4
GND
GNDA
DIODE
SELF
VDD
VDDA
24-lead QFN package pinout
24
23
22
21
20
19
2
17
DP
CRDCLK
3
16
DM
C4
4
15
LED0
CRDIO
5
14
PA6
C8
6
13
GND
7
8
9
10
11
12
OSCOUT
CRDRST
OSCIN
USBVCC
NC
18
ICCCLK/WAKUP2/PA1
1
ICCDATA/WAKUP2/PA0
CRDVCC
CRDDET
Figure 4.
Pin description
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Legend / Abbreviations:
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Type: I = input, O = output, S = supply
In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger
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Output level: HS = 10mA high sink (on N-buffer only)
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Port and control configuration:
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Input:float = floating, wpu = weak pull-up, int = interrupt, ana = analog
Output: OD = open drain, PP = push-pull
Refer to “I/O ports” on page 40 for more details on the software configuration of the I/O
ports.
O
Pin description
2
3
CRDRST
O
CT
X
PP
Output
int
Input
OD
Port / Control
wpu
5
Output
2
Input
SO24
1
Pin name
Type
QFN24
Level
LQFP64
Pin n°
VCARD supplied
Table 3.
X
NC
3
6
CRDCLK
Main
function
(after reset)
Alternate function
Smartcard Reset
Not Connected
O
CT
X
X
Doc ID 8951 Rev 6
Smartcard Clock
11/121
Pin description
Pin description (continued)
4
PP
Output
int
Input
OD
Port / Control
wpu
Output
Input
Pin name
Type
Level
SO24
QFN24
LQFP64
Pin n°
VCARD supplied
Table 3.
ST7SCR1E4, ST7SCR1R4
NC
Main
function
(after reset)
Not Connected
5
4
7
C4
O
6
5
8
CRDIO
I/O CT
7
6
9
C8
O
3
GND
S
9
PB0
O
CT
X
X
Port B0 (1)
10
PB1
O
CT
X
X
Port B1 (1)
11
PB2
O
CT
X
X
Port B2 (1)
B3 (1)
8
CT
X
X
CT
X
X
X
Smartcard C4
X
Smartcard I/O
X
Ground
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PB3
O
CT
X
X
Port
13
PB4
O
CT
X
X
Port B4 (1)
14
PB5
O
CT
X
15
PB6
O
CT
16
PB7
O
CT
10 CRDDET
I
CT
VDD
S
ct
7
18
19
8
11
PA0/WAKUP2/
ICCDATA
20
9
12
PA1/WAKUP2/
ICCCLK
ete
21
PA2/WAKUP2
ol
22
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23
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PA3/WAKUP2
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X
X
so
X
Port B6 (1)
X
X
Port B7 (1)
Ob
X
Port B5 (1)
I/O CT
X
X
X
X
Port A0
Interrupt, In-Circuit
Communication Data Input
I/O CT
X
X
X
X
Port A1
Interrupt, In-Circuit
Communication Clock Input
I/O CT
X
X
X
X
Port A2 (1)
Interrupt
X
Port A3
(1)
Interrupt
(1)
X
I/O CT
X
X
CT
X
X
Port D0
24
PD1
O
CT
X
X
Port D1 (1)
25
PD2
O
CT
X
X
Port D2 (1)
26
PD3
O
CT
X
X
Port D3 (1)
27
PD4
O
CT
X
X
Port D4 (1)
28
PD5
O
CT
X
X
Port D5 (1)
29
PD6
O
CT
X
X
Port D6 (1)
30
PD7
O
CT
X
X
Port D7 (1)
11
14 OSCIN
32
12
15 OSCOUT
33
12/121
VDD
o
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P
Power Supply voltage 4V-5.5V
O
31
c
u
d
Smartcard Detection
PD0
O
)
s
t(
Smartcard C8
12
17
Alternate function
CT
Input/Output Oscillator pins. These pins
connect a 4MHz parallel-resonant crystal, or
an external source to the on-chip oscillator.
CT
S
Power Supply voltage 4V-5.5V
Doc ID 8951 Rev 6
ST7SCR1E4, ST7SCR1R4
Pin description (continued)
34
GND
S
35
PC0/WAKUP1
I
PP
Output
int
Input
OD
Port / Control
wpu
Output
Pin name
Input
Type
Level
SO24
QFN24
LQFP64
Pin n°
VCARD supplied
Table 3.
Pin description
Main
function
(after reset)
Alternate function
Ground
CT
X
X
PC0 (1)
External interrupt
(1)
External interrupt
36
PC1/WAKUP1
I
CT
X
X
PC1
37
PC2/WAKUP1
I
CT
X
X
PC2 (1)
External interrupt
(1)
External interrupt
38
PC3/WAKUP1
I
CT
X
X
PC3
39
PC4/WAKUP1
I
CT
X
X
PC4 (1)
External interrupt
(1)
External interrupt
40
PC5/WAKUP1
I
CT
X
X
PC5
41
PC6/WAKUP1
I
CT
X
X
PC6 (1)
X
PC7 (1)
42
PC7/WAKUP1
43
16 VPP
13
I
14
17 PA6
I
45
15
18 LED0
O
46
16
19 DM
I/O CT
47
17
20 DP
I/O CT
18
21 USBVCC
50
19
22 VDDA
51
20
23 VDD
so
52
CT
HS
)
s
(
ct
u
d
o
Pr
49
o
r
P
External interrupt
External interrupt
l
o
s
S
NC
c
u
d
Flash programming voltage. Must be held
low in normal operating mode.
44
e
t
e
l
e
t
e
S
GND
48
X
CT
O
Must be held low in normal operating mode.
b
O
-
PA6
X
Constant Current Output
USB Data Minus line
USB Data Plus line
Not Connected
3.3 V Output for USB
CT
S
power Supply voltage 4V-5.5V
S
power Supply voltage 4V-5.5V
LED1
O
HS
X
Constant Current Output
LED2
O
HS
X
Constant Current Output
54
LED3
O
HS
X
Constant Current Output
55
NC
Not Connected
56
NC
Not Connected
57
PA4
I/O CT
X
X
X
X
Port A4
58
PA5
I/O CT
X
X
X
X
Port A5
Ob
53
59
21
24 SELF2
O
CT
60
21
24 SELF1
O
CT
61
22
1
S
CT
DIODE
)
s
t(
An External inductance must be connected
to these pins for the step up converter (refer
to Figure 5 to choose the right capacitance)
An External diode must be connected to this
pin for the step up converter (refer to Figure
5 to choose the right component)
Doc ID 8951 Rev 6
13/121
Pin description
Pin description (continued)
63
24
3
GND
S
64
1
4
CRDVCC
O
PP
S
Output
OD
GNDA
Input
int
SO24
2
Port / Control
wpu
QFN24
23
Input
LQFP64
62
Pin name
Output
Level
Type
Pin n°
VCARD supplied
Table 3.
ST7SCR1E4, ST7SCR1R4
Main
function
(after reset)
Alternate function
Ground
1.
CT
X
Smartcard Supply pin
)
s
t(
Keyboard interface
Note:
c
u
d
It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all
VSS and VSSA pins to ground.
Figure 5.
o
r
P
Smartcard interface reference application - 24-pin SO package
e
t
e
VDD
ol
s
b
O
D1
)-
C3
DIODE
s
(
t
c
du
C4
e
t
e
l
o
r
P
C5
C6
CRDVCC
CRDRST
CRDCLK
C4
CRDIO
C8
CRDDET
PA0
PA1
o
s
b
O
GNDA
GND
SELF
VDD
VDDA
USBVcc
DP
VDD
C2
R
D+
D-
DM
LED0
PA6
VPP
OSCOUT
OSCIN
NC
Mandatory values for the external components :
C1 : 4.7 µF 1)
C2 : 100nF 1)
C3 : 1 nF
C4 : 4.7 µF,ESR 0.5 Ohm
C5 : 470 pF
C6 : 100 pF
R : 1.5kOhm
L1 : 10 µH, 2 Ohm
Crystal 4.0 MHz, Impedance max100 Ohm
Cl1, Cl2 2)
D1: BAT42 SHOTTKY
14/121
C1
L1
Doc ID 8951 Rev 6
LED
VDD
CL1
CL2
ST7SCR1E4, ST7SCR1R4
Note:
Pin description
C1 and C2 must be located close to the chip.
Refer to Section 6: Supply, reset and clock management & Section 14.4.3 Crystal resonator
oscillators.
Figure 6.
Smartcard interface reference application - 64-Pin LQFP package
D1
C3
L1
VDD
VDD
C1
C4
C2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
C5
C6
e
t
le
o
s
b
)
s
(
t
C8
-O
)
s
t(
R
LED
D+
D-
c
u
d
VDD
o
r
P
CL1
C7
CL2
c
u
d
Mandatory values for the external components :
C1 : 4.7 µF 1)
C2 : 100nF 1)
C3 : 1 nF
o
r
P
C4 : 4.7 µF,ESR 0.5 Ohm
C5 : 470
C6 : 100
C7 : 100
C8 : 100
ete
l
o
s
Ob
Note:
pF
pF
nF 1)
nF 1)
R : 1.5kOhm
L1 : 10 µH, 2 Ohm
Crystal 4.0 MHz, Impedance max100 Ohm
Cl1, Cl2 2)
D1: BAT42 SHOTTKY
C1, C2, C7 and C8 must be located close to the chip.
Refer to Section 6: Supply, reset and clock management and Section 14.4.3 Crystal
resonator oscillators.
Doc ID 8951 Rev 6
15/121
Register and memory map
3
ST7SCR1E4, ST7SCR1R4
Register and memory map
As shown in Figure 7, the MCU is capable of addressing 64K bytes of memories and I/O
registers.
The available memory locations consist of 40 bytes of register locations, up to 512 bytes of
RAM and up to 16K bytes of user program memory. The RAM space includes up to 128
bytes for the stack from 0100h to 017Fh.
The highest address bytes contain the user reset and interrupt vectors.
IMPORTANT: Memory locations noted “Reserved” must never be accessed. Accessing a
reserved area can have unpredictable effects on the device.
Figure 7.
)
s
t(
Memory map
0000h
HW Registers
(see Table 4)
0040h
003Fh
0040h
RAM
00FFh
0100h
(512 Bytes)
017Fh
0180h
Stack (128 Bytes)
o
s
b
023Fh
0240h
O
)
USB RAM
256 Bytes
033Fh
s
(
t
c
Unused
C000h
du
Program Memory
ro
P
e
t
e
l
o
(16K Bytes)
FFDFh
FFE0h
FFFFh
Interrupt & Reset Vectors
(see Table 11)
s
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O
16/121
o
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Short Addressing
RAM (192 Bytes)
e
t
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c
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Doc ID 8951 Rev 6
023Fh
16-bit Addressing RAM
( 192 Bytes)
ST7SCR1E4, ST7SCR1R4
Table 4.
Hardware register memory map
Address
Register
label
Block
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
CRD
000Eh
Watchdog WDGCR
0011h
0012h
0013h
0014h
Port A
PADR
PADDR
PAOR
PAPUCR
0015h
0016h
0017h
Port B
PBDR
PBOR
PBPUCR
0018h
Port C
0019h
001Ah
001Bh
t
e
l
o
001Ch
001Dh
001Eh
001Fh
Reset
status
CRDCR
CRDSR
CRDCCR
CRDETU1
CRDETU0
CRDGT1
CRDGT0
CRDWT2
CRDWT1
CRDWT0
CRDIER
CRDIPR
CRDTXB
CRDRXB
Register name
Remarks
Smartcard Interface Control Register
Smartcard Interface Status Register
Smartcard Contact Control Register
Smartcard Elementary Time Unit 1
Smartcard Elementary Time Unit 0
Smartcard Guard time 1
Smartcard Guard time 0
Smartcard Character Waiting Time 2
Smartcard Character Waiting Time 1
Smartcard Character Waiting Time 0
Smartcard Interrupt Enable Register
Smartcard Interrupt Pending Register
Smartcard Transmit Buffer Register
Smartcard Receive Buffer Register
00h
80h
xxh
01h
74h
00h
0Ch
00h
25h
80h
00h
00h
00h
00h
Watchdog Control Register
00h
R/W
Port A Data Register
Port A Data Direction Register
Option Register
Pull up Control Register
00h
00h
00h
00h
R/W
R/W
R/W
R/W
Port B Data Register
Option Register
Pull up Control Register
00h
00h
00h
R/W
R/W
R/W
PCDR
Port C Data Register
00h
R/W
Port D
PDDR
PDOR
PDPUCR
Port D Data Register
Option Register
Pull up Control Register
00h
00h
00h
R/W
R/W
R/W
MISC
MISCR1
MISCR2
MISCR3
MISCR4
Miscellaneous Register 1
Miscellaneous Register 2
Miscellaneous Register 3
Miscellaneous Register 4
00h
00h
00h
00h
R/W
R/W
R/W
R/W
e
t
le
o
s
b
O
)
s
(
t
c
du
ro
P
e
s
b
O
Register and memory map
Doc ID 8951 Rev 6
)
s
t(
c
u
d
o
r
P
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
17/121
Register and memory map
Table 4.
Address
Hardware register memory map (continued)
USB
0035h
0036h
TBU
003Eh
USBISTR
USBIMR
USBCTLR
DADDR
USBSR
EPOR
CNT0RXR
CNT0TXR
EP1TXR
CNT1TXR
EP2RXR
CNT2RXR
EP2TXR
CNT2TXR
EP3TXR
CNT3TXR
EP4TXR
CNT4TXR
EP5TXR
CNT5TXR
ERRSR
ITC
Remarks
00h
00h
06h
00h
00h
0xh
00h
00h
00h
00h
00h
0xh
00h
00h
00h
00h
00h
00h
00h
00h
00h
Timer counter value
Timer control status
00h
00h
R/W
R/W
ITSPR0
ITSPR1
ITSPR2
ITSPR3
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
LED_CTRL
LED Control Register
00h
R/W
e
t
le
O
)
s
(
t
c
TBUCV
TBUCSR
Doc ID 8951 Rev 6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
)
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s
b
s
b
O
18/121
Reset
status
Register name
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
Device Address Register
USB Status Register
Endpoint 0 Register
EP 0 Reception Counter Register
EP 0 Transmission Counter Register
EP 1 Transmission Register
EP 1 Transmission Counter Register
EP 2 Reception Register
EP 2 Reception Counter Register
EP 2 Transmission Register
EP 2 Transmission Counter Register
EP 3 Transmission Register
EP 3 Transmission Counter Register
EP 4 Transmission Register
EP 4 Transmission Counter Register
EP 5 Transmission Register
EP 5 Transmission Counter Register
Error Status Register
u
d
o
r
P
e
t
e
l
o
Register
label
Block
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0037h
0038h
0039h
003Ah
ST7SCR1E4, ST7SCR1R4
ST7SCR1E4, ST7SCR1R4
Flash program memory
4
Flash program memory
4.1
Introduction
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a Byte-byByte basis using an external VPP supply.
The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
)
s
t(
c
u
d
Main features
●
Three Flash programming modes:
o
r
P
–
Insertion in a programming tool. In this mode, all sectors including option bytes
can be programmed or erased.
–
ICP (In-Circuit Programming). In this mode, all sectors including option bytes can
be programmed or erased without removing the device from the application board.
–
IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be
programmed or erased without removing the device from the application board
and while the application is running.
e
t
le
o
s
b
O
)
●
ICT (In-Circuit Testing) for downloading and executing user application test patterns in
RAM
●
Read-out protection
●
Register Access Security System (RASS) to prevent accidental programming or
erasing
s
(
t
c
u
d
o
4.3
r
P
Structure
e
t
e
ol
s
b
O
The Flash memory is organized in sectors and can be used for both code and data storage.
Depending on the overall FLASH memory size in the microcontroller device, there are up to
three user sectors (see Table 5). Each of these sectors can be erased independently to
avoid unnecessary erasing of the whole Flash memory when only a partial erasing is
required.
The first two sectors have a fixed size of 4 Kbytes (see Figure 8). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
Sector 0 (F000h-FFFFh).
Table 5.
Sectors available in FLASH devices
Flash Memory Size (bytes)
Available Sectors
4K
Sector 0
8K
Sectors 0,1
> 8K
Sectors 0,1, 2
Doc ID 8951 Rev 6
19/121
Flash program memory
Figure 8.
ST7SCR1E4, ST7SCR1R4
Memory map and sector address
16K USER FLASH MEMORY SIZE
C000h
ex.: user program
8 Kbytes
SECTOR 2
DFFFh
E000h
EFFFh
F000h
FFFFh
4.4
ex.: user data
+ library
4 Kbytes
SECTOR 1
ex.: user system library
4 Kbytes
SECTOR 0
)
s
t(
+ IAP BootLoader
c
u
d
ICP (In-circuit programming)
o
r
P
To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication)
mode by an external controller or programming tool.
e
t
le
o
s
b
Depending on the ICP code downloaded in RAM, Flash memory programming can be fully
customized (number of bytes to program, program locations, or selection serial
communication interface for downloading).
O
)
When using an STMicroelectronics or third-party programming tool that supports ICP and
the specific microcontroller device, the user needs only to implement the ICP hardware
interface on the application board (see Figure 9). For more details on the pin locations, refer
to the device pinout description.
s
(
t
c
u
d
o
ICP needs six signals to be connected to the programming tool. These signals are:
●
r
P
e
●
●
t
e
l
o
●
bs
O
VSS: device power supply ground
VDD: for reset by LVD
OSCIN: to force the clock during power-up
ICCCLK: ICC output serial clock pin
●
ICCDATA: ICC input serial data pin
●
VPP: ICC mode selection and programming voltage.
If ICCCLK or ICCDATA are used for other purposes in the application, a serial resistor has to
be implemented to avoid a conflict in case one of the other devices forces the signal level.
Note:
To develop a custom programming tool, refer to the ST7 FLASH Programming and ICC
Reference Manual which gives full details on the ICC protocol hardware and software.
4.5
IAP (In-application programming)
This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP
mode or by plugging the device in a programming tool).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored, etc.). For example, it is
20/121
Doc ID 8951 Rev 6
ST7SCR1E4, ST7SCR1R4
Flash program memory
possible to download code from the USB interface and program it in the Flash. IAP mode
can be used to program any of the Flash sectors except Sector 0, which is write/erase
protected to allow recovery in case errors occur during the programming operation.
Figure 9.
Typical ICP interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICP PROGRAMMING TOOL CONNECTOR
HE10 CONNECTOR TYPE
9
7
5
3
1
10
8
6
4
2
)
s
t(
c
u
d
APPLICATION BOARD
ICCCLK
ICCDATA
VPP
VDD
VSS
OSCIN
OSCOUT
l
o
s
ST7
4.7kΩ
N
IO
AT
C
Note:
e
t
e
o
r
P
I
PL
AP
CL1
E
TH
CL2
TO
10kΩ
b
O
-
If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal
isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an
ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the
application. If they are used as inputs by the application, isolation such as a serial resistor
has to implemented in case another device forces the signal. Refer to the Programming Tool
documentation for recommended resistor values.
)
s
(
ct
4.6
u
d
o
r
P
e
Program memory read-out protection
t
e
l
o
The read-out protection is enabled through an option bit.
s
b
O
4.7
For Flash devices, when this option is selected, the program and data stored in the Flash
memory are protected against read-out (including a re-write protection). When this
protection is removed by reprogramming the Option Byte, the entire Flash program memory
is first automatically erased and the device can be reprogrammed.
Refer to the Option Byte description for more details.
Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual.
Doc ID 8951 Rev 6
21/121
Flash program memory
4.8
ST7SCR1E4, ST7SCR1R4
Register description
FLASH control/status register (FCSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
0
0
This register is reserved for use by Programming Tool software. It controls the FLASH
programming and erasing operations. For details on customizing FLASH programming
methods and In-Circuit Testing, refer to the ST7 FLASH Programming and ICC Reference
Manual.
)
s
t(
c
u
d
e
t
le
o
s
b
O
)
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22/121
Doc ID 8951 Rev 6
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ST7SCR1E4, ST7SCR1R4
Central processing unit
5
Central processing unit
5.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.
5.2
5.3
Main features
●
Enable executing 63 basic instructions
●
Fast 8-bit by 8-bit multiply
●
17 main addressing modes (with indirect addressing mode)
●
Two 8-bit index registers
●
16-bit stack pointer
●
Low power HALT and WAIT modes
●
Priority maskable hardware interrupts
●
Non-maskable software/hardware interrupts
e
t
le
)
s
t(
c
u
d
o
r
P
o
s
b
CPU registers
O
)
The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are
accessed by specific instructions.
s
(
t
c
Accumulator (A)
u
d
o
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
r
P
e
Index registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas
for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to
indicate that the following instruction refers to the Y register.)
t
e
l
o
O
bs
The Y register is not affected by the interrupt automatic procedures.
Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is
the LSB) and PCH (Program Counter High which is the MSB).
Doc ID 8951 Rev 6
23/121
Central processing unit
ST7SCR1E4, ST7SCR1R4
Figure 10. CPU registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
PCH
15
PCL
8 7
0
)
s
t(
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
0
1 1 I1 H I0 N Z C
c
u
d
CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8 7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
e
t
le
Condition code register (CC)
Reset Value: 111x1xxx
7
)
s
(
ct
1
X = Undefined Value
o
s
b
Read/Write
1
o
r
P
I1
-O
H
I0
0
N
Z
C
The 8-bit Condition Code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
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These bits can be individually tested and/or controlled by specific instructions.
Arithmetic management bits
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Bit 4 = H Half carry.
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This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an
ADD or ADC instructions. It is reset by hardware during the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic
subroutines.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is representative of the result sign of the last
arithmetic, logical or data manipulation. It’s a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
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Doc ID 8951 Rev 6
ST7SCR1E4, ST7SCR1R4
Central processing unit
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
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0: No overflow or underflow has occurred.
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1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
Interrupt Management Bits
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Bit 5,3 = I1, I0 Interrupt
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The combination of the I1 and I0 bits gives the current interrupt software priority.
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Interrupt Software Priority
Level 0 (main)
Level 1
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ct
Level 2
-O
Level 3 (= interrupt disable)
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I1
I0
1
0
0
1
0
0
1
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These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (IxSPR). They can
be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP
instructions.
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See the interrupt management chapter for more details.
Stack Pointer (SP)
Read/Write
Reset Value: 017Fh
15
0
8
0
0
0
0
0
0
7
SP7
1
0
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 11).
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25/121
Central processing unit
ST7SCR1E4, ST7SCR1R4
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD
instruction.
Note:
When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 11.
)
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●
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
●
On return from interrupt, the SP is incremented and the context is popped from the
stack.
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A subroutine call occupies two locations and an interrupt five locations in the stack area.
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Figure 11. Stack manipulation example
CALL
Subroutine
PUSH Y
Interrupt
Event
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SP
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@ 017Fh
RET
or RSP
IRET
O
)
@ 0100h
SP
POP Y
SP
CC
A
Y
CC
A
SP
CC
A
X
X
X
PCH
PCH
PCH
SP
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
Stack Higher Address = 017Fh
Stack Lower Address = 0100h
Doc ID 8951 Rev 6
SP
ST7SCR1E4, ST7SCR1R4
Supply, reset and clock management
6
Supply, reset and clock management
6.1
Clock system
6.1.1
General description
The MCU accepts either a 4 MHz crystal or an external clock signal to drive the internal
oscillator. The internal clock (fCPU) is derived from the internal oscillator frequency (fOSC),
which is 4 MHz.
After reset, the internal clock (fCPU) is provided by the internal oscillator (4 MHz frequency).
)
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To activate the 48-MHz clock for the USB interface, the user must turn on the PLL by setting
the PLL_ON bit in the MISCR4 register. When the PLL is locked, the LOCK bit is set by
hardware.
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The user can then select an internal frequency (fCPU) of either 4 MHz or 8 MHz by
programming the CLK_SEL bit in the MISCR4 register (refer to Section 10: Miscellaneous
registers).
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The PLL provides a signal with a duty cycle of 50%.
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The internal clock signal (fCPU) is also routed to the on-chip peripherals. The CPU clock
signal consists of a square wave with a duty cycle of 50%.
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Figure 12. Clock, reset and supply block diagram
MISCR4
-
t(s
PLL_ CLK_
ON
SEL
-
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4 MHz
(fOSC)
PLL
X 12
-
-
-
-
4 MHz
48 MHz
DIV
48 MHz
LOCK
8 MHz
INTERNAL
CLOCK (fCPU)
USB
The internal oscillator is designed to operate with an AT-cut parallel resonant quartz in the
frequency range specified for fosc. The circuit shown in Figure 14 is recommended when
using a crystal, and Table 6 lists the recommended capacitance. The crystal and associated
components should be mounted as close as possible to the input pins in order to minimize
output distortion and start-up stabilization time. The LOCK bit in the MISCR4 register can
also be used to generate the fCPU directly from fOSC if the PLL and the USB interface are not
active.
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Supply, reset and clock management
Table 6.
ST7SCR1E4, ST7SCR1R4
Recommended values for 4 MHz crystal resonator
20 Ω
56pF
56pF
RSMAX
COSCIN
COSCOUT
25 Ω
47pF
47pF
70 Ω
22pF
22pF
Note:
RSMAX is the equivalent serial resistor of the crystal (see crystal specification).
6.1.2
External clock
An external clock may be applied to the OSCIN input with the OSCOUT pin not connected,
as shown on Figure 13.
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Figure 13. External clock source connections
OSCOUT
OSCIN
NC
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EXTERNAL
CLOCK
Figure 14. Crystal resonator
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6.2
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6.2.2
OSCIN
OSCOUT
COSCIN
COSCOUT
e sequence manager (RSM)
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Reset
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6.2.1
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Introduction
The reset sequence manager has two reset sources:
●
Internal LVD reset (Low Voltage Detection) which includes both a power-on and a
voltage drop reset
●
Internal watchdog reset generated by an internal watchdog counter underflow as
shown in Figure 16.
Functional description
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of 3 phases as shown in Figure 15.
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Doc ID 8951 Rev 6
ST7SCR1E4, ST7SCR1R4
Supply, reset and clock management
1.
A first delay of 30µs + 127 tCPU cycles during which the internal reset is maintained.
2.
A second delay of 512 tCPU cycles after the internal reset is generated. It allows the
oscillator to stabilize and ensures that recovery has taken place from the Reset state.
3.
Reset vector fetch (duration: 2 clock cycles)
Low voltage detector
The low voltage detector generates a reset when VDD=
JRUGT Jump if (C + Z = 0)
Unsigned >
Doc ID 8951 Rev 6
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ST7SCR1E4, ST7SCR1R4
Mnemo
Function/
Example
Description
Dst
Src
JRULE
Jump if (C + Z = 1)
Unsigned
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