ST8024
Smartcard interface
Features
■
Designed to be compatible with the NDS
conditional access system
■
IC card interface
■
3 or 5 V supply for the IC (VDD and GND)
■
Three specifically protected half-duplex bidirectional buffered I/O lines to card contacts
C4, C7 and C8
■
SO-28
DC-DC converter for VCC generation
separately powered from a 5 V ± 20% supply
(VDDP and PGND)
TSSOP28
■
ISO 7816, GSM11.11 and EMV (payment
systems) compatibility
3 or 5 V ± 5 % regulated card supply voltage
(VCC) with appropriate decoupling has the
following capabilities:
– ICC < 80 mA at VDDP = 4 to 6.5 V
– Handles current spikes of 40 nA up to 20
MHz
– Controls rise and fall times
– Filtered overload detection at
approximately 120 mA
■
Supply supervisor for spike-killing during
power-on and power-off and power-on reset
(threshold fixed internally or externally by a
resistor bridge)
■
Built-in debounce on card presence contacts
■
One multiplexed status signal off
■
Thermal and short-circuit protection on all card
contacts
■
Automatic activation and deactivation
sequences; initiated by software or by
hardware in the event of a short-circuit, card
take-off, overheating, VDD or VDDP drop-out
The ST8024 is a complete low cost analog
interface for asynchronous 3 V and 5 V smart
cards. It can be placed between the card and the
microcontroller with few external components to
perform all supply protection and control
functions. ST8024 is a direct replacement of
ST8004.
■
Enhanced ESD protection on card side (> 6 kV)
■
26 MHz integrated crystal oscillator
■
Clock generation for cards up to 20 MHz
(divided by 1, 2, 4 or 8 through CLKDIV1 and
CLKDIV2 signals) with synchronous frequency
changes
■
Non-inverted control of RST via pin RSTIN
■
Table 1.
Description
Main applications are: smartcard readers for settop-box, IC card readers for banking,
identification, pay TV.
Device summary
Order codes
Temperature range
Packages
Packaging
ST8024CDR
- 25 to 85 °C
SO-28 (tape and reel)
1000 parts per reel
ST8024CTR
- 25 to 85 °C
TSSOP28 (tape and reel)
2500 parts per reel
March 2009
Rev 8
1/31
www.st.com
31
Contents
ST8024
Contents
1
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2
Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.1
Without external divider on pin PORADJ . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.2
With an external divider on pin PORADJ . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.3
Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3
Clock circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4
I/O transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5
Inactive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6
Activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.8
Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.9
VCC generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.10
Fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
ST8024
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics over recommended operating condition . . . . . . . . . . . . . . . . . . . . 9
Step-up converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Card supply voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Crystal connection (pins XTAL1 and XTAL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC AND AUX2UC). . . . . . . . . . . . . . . . . 11
Data lines to card reader (pins I/O, AUX1 AND AUX2 with integrated
11 kΩ pull-up resistor to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data lines to microcontroller (pins I/OUC, AUX1UC AND AUX2UC with
integrated 11 kΩ pull-up resistor to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Internal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset output to card reader (pin RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock output to card reader (pin CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5 V / 3 V . . . . . . . . . . . . 14
Card presence inputs (pins PRES and PRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interrupt output (pin OFF NMOS drain with integrated 20 kΩ pull-up resistor to VDD); . . . 14
Protection and limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Card presence indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
List of figures
ST8024
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
4/31
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Definition of output and input transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Activation sequence using RSTIN and CMDVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Activation sequence at t3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Behavior of OFF, CMDVCC, PRES and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Emergency deactivation sequence (card extraction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ST8024
Diagram
1
Diagram
Figure 1.
Block diagram
5/31
Pin configuration
ST8024
2
Pin configuration
Figure 2.
Pin connections
Table 2.
Pin description
Pin n°
Symbol
1
CLKDIV1
Control of CLK frequency
2
CLKDIV2
Control of CLK frequency
3
5V/3V
VCC selection pin
4
PGND
Power ground for step-up converter
5
C1+
External cap. for step-up converter
6
VDDP
Power supply for step-up converter
7
C1-
External cap. step-up converter
8
VUP
Output of step-up converter
9
PRES
Card presence input (active low)
10
PRES
Card presence input (active high)
11
I/O
12
AUX2
Auxiliary line to and from card (C8) (internal 11 kΩ pull-up resistor connected to VCC)
13
AUX1
Auxiliary line to and from card (C4) (internal 11 kΩ pull-up resistor connected to VCC)
14
CGND
Ground for card signal (C5)
15
CLK
Clock to card (C3)
16
RST
Card reset (C2)
17
VCC
Supply voltage for the card (C1)
18
VTHSEL
6/31
Name and function
Data line to and from card (C7) (internal 11 kΩ pull-up resistor connected to VCC)
Deactivation threshold selector pin (under voltage lock-out)
ST8024
Table 2.
Pin configuration
Pin description (continued)
Pin n°
Symbol
Name and function
19
CMDVCC
20
RSTIN
21
VDD
Supply voltage
22
GND
Ground
23
OFF
Interrupt to MCU (active low)
24
XTAL1
Crystal or external clock input
25
XTAL2
Crystal connection (leave this pin open if external clock is used)
26
I/OUC
MCU data I/O line (internal 11 kΩ pull-up resistor connected to VDD)
27
AUX1UC
Non-inverting receiver input (internal 11 kΩ pull-up resistor connected to VDD)
28
AUX2UC
Non-inverting receiver input (internal 11 kΩ pull-up resistor connected to VDD)
Start activation sequence input (active low)
Card reset input from MCU
7/31
Maximum ratings
ST8024
3
Maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
-0.3
7
V
VDD, VDDP Supply voltage
Vn1
Voltage on pins XTAL1, XTAL2, 5V/3V, RSTIN, AUX2UC,
AUX1UC, I/OUC, CLKDIV1, CLKDIV2, PORADJ, CMDVCC,
PRES, PRES and OFF
-0.3
VDD + 0.3
V
Vn2
Voltage on card contact pins I/O, RST, AUX1, AUX2 and CLK
-0.3
VCC + 0.3
V
Vn3
Voltage on pins VUP, S1 and S2
7
V
ESD1
ESD2
TJ(MAX)
TSTG
MIL-STD-883 class 3 on card contact pins, PRES and PRES (1)
(2)
-6
6
kV
MIL-STD-883 class 2 on microcontroller contact pins and
RSTIN (1) (2)
-2
2
kV
150
°C
150
°C
Maximum operating junction temperature
Storage temperature range
-40
1. All card contacts are protected against any short with any other card contact
2. Method 3015 (HBM, 1500 Ω, 100 pF) 3 positive pulses and 3 negative pulses on each pin referenced to ground.
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 4.
Thermal data
Symbol
Parameter
Condition
SO-28
TSSOP28
Unit
RthJA
Thermal resistance junction-ambient temperature
Multilayer test board
(Jedec standard)
56
50
°K/W
Table 5.
Recommended operating conditions
Typ.
Max.
Unit
85
°C
Symbol
TA
8/31
Parameter
Temperature range
Test conditions
Min.
-25
ST8024
4
Electrical characteristics
Electrical characteristics
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to
TA = 25 °C.
Table 6.
Symbol
Electrical characteristics over recommended operating condition
Parameter
VDD
Supply voltage
VDDP
Supply voltage for the
voltage doubler
IDD
IDDP
Test conditions
Min.
Typ.
2.7
VCC = 5V; |ICC| < 80 mA
4.0
VCC = 5V; |ICC| < 20 mA
3.0
5
Max.
Unit
6.5
V
6.5
V
6.5
Card Inactive
1.2
Card Active; fCLK = fXTAL; CL = 30pF
1.5
Inactive mode
0.1
Active mode; fCLK = fXTAL; CL = 30pF; |ICC|
=0
10
VCC = 5V; |ICC| = 80 mA
200
VCC = 3V; |ICC| = 65 mA
100
Supply current
DC-DC converter supply
current
mA
mA
Vth2
Falling threshold voltage
on VDD
no external resistors at pin PORADJ;
VDD level falling
2.35
2.45
2.55
V
VHYS2
Hysteresis of threshold
voltage Vth2
no external resistors at pin PORADJ
50
100
150
mV
Vth(ext)rise
External rising threshold
voltage on VDD
external resistor bridge at pin PORADJ;
VDD level rising
1.25
1.28
1.31
V
Vth(ext)fall
External falling threshold external resistor bridge at pin PORADJ;
voltage on VDD
VDD level falling
1.19
1.22
1.25
V
VHYS(ext)
Hysteresis of threshold
voltage Vth(ext)
external resistor bridge at pin PORADJ
30
60
90
mV
Hysteresis of threshold
ΔVHYS(ext) voltage Vth(ext) variation
with temperature
external resistor bridge at pin PORADJ
0.25
mV/K
Width of internal PowerOn reset pulse
no external resistor at pin PORADJ
4
8
12
tW
external resistor bridge at pin PORADJ
8
16
24
Leakage current on pin
PORADJ
VPORADJ < 0.5 V
-0.1
4
10
IL
VPORADJ > 1.0 V
-1
PTOT
Total power dissipation
Continuous operation; Ta = -25 to 85°C
ms
µA
1
0.56
W
9/31
Electrical characteristics
ST8024
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to
TA = 25 °C.
Table 7.
Symbol
fCLK
Step-up converter
Parameter
Test conditions
Clock frequency
Card active
Output voltage on pin VUP
(average value)
Typ.
2.2
Threshold voltage for step- 5 V card
Vth(vd-vf) up converter to change to
3 V card
voltage follower
VUP(av)
Min.
Max.
Unit
3.2
MHz
5.2
5.8
6.2
3.8
4.1
4.4
VCC = 5 V
5.2
5.7
6.2
VCC = 3 V; VDDP = 3.3 V
3.5
3.9
4.3
V
V
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to
TA = 25 °C (Note 1).
Table 8.
Symbol
CVCC
VCC
VCC
(RIPPLE)
Card supply voltage characteristics
Parameter
External capacitance
on pin VCC
Card supply voltage
(including ripple
voltage)
Ripple voltage on VCC
(Peak to Peak value)
Test conditions
Note 2 and Note 3
Min.
Typ.
80
Max.
Unit
220
nF
Card Inactive; |ICC| = 0 mA 5 and 3V card
-0.1
0
0.1
Card Inactive; |ICC| = 1 mA 5 and 3V card
-0.1
0
0.3
Card Active; |ICC| < 80 mA
5 V card
4.75
5
5.25
Card Active; |ICC| < 65 mA
3 V card
2.85
3
3.15
Card Active; single current
pulse IP =-100 mA; tp=2 µs
5 V card
4.65
5
5.25
Card Active; single current
3 V card
pulse IP =-100 mA; tp =2 µs
2.76
3
3.20
Card active; current pulses, 5 V card
QP = 40 nAs
3 V card
4.65
5
5.25
2.76
3
3.20
Card Active; current pulses 5 V card
QP =40 nAs with
|ICC| < 200mA, tp < 400 ns 3 V card
4.65
5
5.25
2.76
3
3.20
V
fRIPPLE = 20 kHz to 200 MHz
350
VCC = 0 to 5V
80
VCC = 0 to 3V
65
mV
(P-P)
|ICC|
Card supply current
VCC short circuit to GND
SR
10/31
Slew rate
Slew up or down
90
0.08
mA
120
0.15
0.22
V/µs
ST8024
Electrical characteristics
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to
TA = 25 °C.
Table 9.
Symbol
CXTAL1,2
Crystal connection (pins XTAL1 and XTAL2)
Parameter
Test conditions
Min.
Typ.
External capacitance on pins XTAIL1, Depends on type of
XTAIL2
crystal or resonator used
Max.
Unit
15
pF
fXTAL
Crystal frequency
2
26
MHz
fXTAL1
Frequency applied on pin XTAL1
0
26
MHz
VIH
High level input voltage on pin XTAIL1
0.7 VDD
VDD+0.3
V
VIL
Low level input voltage on pin XTAIL1
-0.3
+0.3VDD
V
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to
TA = 25 °C.
Table 10.
Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC AND AUX2UC)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
200
ns
100
ns
Maximum frequency on data lines
1
MHz
Input capacitance on data lines
10
pF
tD(I/O-I/OUC), I/O to I/OUC, I/OUC to I/O falling edge
tD(I/OUC-I/O) delay
tpu
fI/O(MAX)
CI
Active pull-up pulse width
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to
TA = 25 °C.
Table 11.
Symbol
Data lines to card reader (pins I/O, AUX1 AND AUX2 with integrated 11 kΩ pull-up
resistor to VCC
Parameter
Test conditions
NO LOAD
VO(inactive) Output voltage
Inactive mode
IO(inactive) Output current
Inactive mode; pin grounded
VOH
High level output voltage
Min.
0
Typ.
Max.
Unit
0.1
V
IO(inactive)=1mA
0.3
-1
No DC Load
0.9 VCC
VCC+0.1
5 and 3 V cards; IOH < - 40µA
0.75 VCC
VCC+0.1
|IOH| ≥ 10mA
0
0.4
IOL = 1 mA
0
0.2
IOL ≥ 15 mA
VCC-0.4
VCC
mA
V
VOL
Low level output voltage
VIH
High level input voltage
1.5
VCC+0.3
V
VIL
Low level input voltage
0.3
0.8
V
|ILIH|
High level input leakage
current
VIH = VCC
10
µA
|IIL|
Low level input current
VIL = 0 V
600
µA
V
11/31
Electrical characteristics
Table 11.
Symbol
ST8024
Data lines to card reader (pins I/O, AUX1 AND AUX2 with integrated 11 kΩ pull-up
resistor to VCC
Parameter
Test conditions
Min.
Typ.
Max.
Unit
9
11
13
kΩ
RPU
Integrated pull-up resistor
Pull-up resistor to VCC
tT(DI)
Data input transition time
VIL max to VIH min.
1.2
µs
tT(DO)
Data output transition time
VO = 0 to VCC; CL ≤ 80 pF; 10%
to 90%
0.1
µs
IPU
Current when pull-up active
VOH = 0.9VCC; CL = 80 pF
-1
mA
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to
TA = 25 °C.
Table 12.
Symbol
Data lines to microcontroller (pins I/OUC, AUX1UC AND AUX2UC with integrated 11
kΩ pull-up resistor to VDD
Parameter
Test conditions
Min.
Typ.
Max.
Unit
5 and 3 V card; IOH < − 40µA
0.75 VDD
VDD+0.1
No DC Load
0.9 VDD
VDD+0.1
0
0.3
V
High level input voltage
0.7 VDD
VDD+0.3
V
VIL
Low level input voltage
-0.3
0.3 VDD
V
|ILIH|
High level input leakage
current
VIH = VDD
10
µA
|IL|
Low level input current
VIL = 0 V
600
µA
RPU
Internal pull-up resistance to
Pull-up resistor to VDD
VDD
13
kΩ
tT(DI)
Data input transition time
VIL(max) to VIH(min)
1.2
µs
tT(DO)
Data output transition time
VO = 0 to VDD; CL < 30 pF;
10% to 90%
0.1
µs
IPU
Current when pull-up active
VOH = 0.9VDD; CL = 30 pF
VOH
High level output voltage
VOL
Low level output voltage
VIH
IOL = 1 mA
9
11
-1
V
mA
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to
TA = 25 °C.
Table 13.
Symbol
fOSC(INT)
12/31
Internal oscillator
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Inactive mode
55
140
200
kHz
Active mode
2.2
2.7
3.2
MHz
Frequency of internal oscillator
ST8024
Electrical characteristics
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to TA =
25 °C.
Table 14.
Symbol
Reset output to card reader (pin RST)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Output voltage in inactive
mode
IO(inactive) = 1 mA
0
0.3
VO(inactive)
No Load
0
0.1
IO(inactive)
Output current
Inactive mode; pin grounded
0
-1
mA
2
µs
tD(RSTIN-RST) RSTN to RST Delay
VOL
Low level output voltage
VOH
High level output voltage
tR, tF
Rise and fall time
V
RST Enable
IOL = 200 µA
0
0.2
IOL = 20 mA (current limit)
VCC-0.4
VCC
IOH = -200 µA
0.9VCC
VCC
0
0.4
IOH = -20 mA (current limit)
V
CL = 100 pF; VCC = 5 or 3 V
0.1
V
µs
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to
TA = 25 °C.
Table 15.
Clock output to card reader (pin CLK)
Symbol
Parameter
VO(inactive)
Output voltage in inactive mode
IO(inactive)
Output current
Test conditions
Min.
0
0.3
No Load
0
0.1
CLK Inactive mode; pin
grounded
0
-1
IOL = 200 µA
0
0.3
IOL = 70 mA (current
limit)
VCC-0.4
VCC
IOH = -200 µA
0.9VCC
VCC
0
0.4
VOH
High level output voltage
tR, tF
Rise and fall time
CL = 30 pF (Note 4)
Duty factor (except for fXTALS)
CL = 30 pF (Note 4)
45
Slew rate
Slew up or down;
CL = 30 pF
0.2
IOH = -70 mA (current
limit)
Unit
V
Low level output voltage
SR
Max.
IO(inactive) = 1 mA
VOL
δ
Typ.
mA
V
V
16
ns
55
%
V/ns
13/31
Electrical characteristics
ST8024
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to
TA = 25 °C (Note 5)
Table 16.
Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5 V / 3 V
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VIL
Input voltage low
-0.3
0.3VDD
V
VIH
Input voltage high
0.7VDD
VDD
V
|ILIH|
Input leakage current high
VIH = VDD
1
µA
|ILIL|
Input leakage current low
VIL = 0
1
µA
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to TA =
25 °C (Note 6)
Table 17.
Card presence inputs (pins PRES and PRES)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VIL
Input voltage low
-0.3
0.3 VDD
V
VIH
Input voltage high
0.7 VDD
VDD+0.3
V
|ILIH|
Input leakage current high
VIH = VDD
5
µA
|ILIL|
Input leakage current low
VIL = 0
5
µA
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to
TA = 25 °C
Interrupt output (pin OFF NMOS drain with integrated 20 kΩ pull-up resistor to VDD);
Table 18.
Symbol
Parameter
Test conditions
VOL
Low level output voltage
IOL = 2 mA
VOH
High level output voltage
IOH = -15 µA
RPU
Integrated pull-up resistor
20kΩ Pull-up resistor to VDD
Min.
Typ.
0
Max.
Unit
0.3
V
0.75 VDD
16
V
20
24
kΩ
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to
TA = 25 °C.
Table 19.
Protection and limitation
Symbol
Parameter
|ICC(SD)|
Shutdown and limitation current pin
VCC
limitation current pins I/O, AUX1
and AUX2
Max.
Unit
90
120
mA
-15
15
mA
ICLK(lim) limitation current pin CLK
-70
70
mA
IRST(lim) limitation current pin RST
-20
20
mA
II/O(lim)
TSD
14/31
Shut down temperature
Test conditions
Min.
Typ.
150
°C
ST8024
Electrical characteristics
VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to
TA = 25 °C.
Table 20.
Symbol
Timing
Parameter
Test conditions
tACT
Activation time
(See Figure 5)
tDE
Deactivation time
(See Figure 7)
Min.
60
Typ.
Max.
Unit
180
220
µs
80
100
µs
130
µs
t3
Start of the windows for sending
(See Figure 6)
CLK to card
t5
End of the windows for sending
CLK to card
(See Figure 6)
140
µs
tdebounce
Debounce time pins PRES and
PRES
(See Figure 8)
140
µs
Note:
1
All parameters remain within limits but are tested only statistically for the temperature
range. When a parameter is specified as a function of VDD or VCC it means their actual value
at the moment of measurement.
2
To meet these specifications, pin VCC should be decoupled to CGND using two ceramic
multilayer capacitors of low ESR both with values of 100 nF and 100 nF (see Figure 10).
3
Permitted capacitor values are 100 + 100 nF, or 220 nF.
4
Transition time and duty factor definitions are shown in Figure 3; δ = t1/(t1+ t2).
5
Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2
functions see Table 20
6
Pin PRES is active LOW; pin PRES is active HIGH see Figure 8 and Figure 9; PRES has an
integrated 1.25 µA current source to GND. (PRES to VDD); the card is considered present if
at least one of the inputs PRES or PRES is active.
Figure 3.
Definition of output and input transition times
15/31
Functional description
5
ST8024
Functional description
Throughout this document it is assumed that the reader is familiar with ISO7816
terminology.
5.1
Power supply
The supply pins for the IC are VDD and GND. VDD should be in the range of 2.7 to 6.5 V. All
signals interfacing with the system controller are referred to VDD, therefore VDD should also
supply the system controller. All card reader contacts remain inactive during power-on or
power-off.
The internal circuits are maintained in the reset state until VDD reaches Vth2 +Vhys2 and for
the duration of the internal power-on reset pulse, tW (see Figure 4). When VDD falls below
Vth2, an automatic deactivation of the contacts is performed.
A DC-DC converter is incorporated to generate the 5 or 3 V card supply voltage (VCC). The
DC-DC converter should be supplied separately by VDDP and PGND. Due to the possibility
of large transient currents, the two 100 nF capacitors of the DC-DC converter should be
located as near as possible to the IC and have an ESR less than 100 mΩ.
The DC-DC converter functions as a voltage doubler or a voltage follower according to the
respective values of VCC and VDDP (both have thresholds with a hysteresis of 100 mV).
The DC-DC converter function changes as follows:
VCC = 5 V and VDDP > 5.8 V; voltage follower
VCC = 5 V and VDDP < 5.7 V; voltage doubler
VCC = 3 V and VDDP > 4.1 V; voltage follower
VCC = 3 V and VDDP < 4.0 V; voltage doubler.
Supply voltages VDD and VDDP may be applied to the IC in any sequence.
After powering the device, OFF remains LOW until CMDVCC is set HIGH.
During power off, OFF falls LOW when VDD is below the falling threshold voltage.
5.2
Voltage supervisor
5.2.1
Without external divider on pin PORADJ
The voltage supervisor surveys the VDD supply. A defined reset pulse of approximately 8 ms
(tW) is used internally to keep the IC inactive during power-on or power-off of the VDD supply
(see Figure 4).
As long as VDD is less than Vth2 + Vhys2, the IC remains inactive whatever the levels on the
command lines. This state also lasts for the duration of tW after VDD has reached a level
higher than Vth2 + Vhys2. When VDD falls below Vth2, a deactivation sequence of the
contacts is performed.
16/31
ST8024
Functional description
Figure 4.
5.2.2
Voltage supervisor
With an external divider on pin PORADJ
If an external resistor bridge is connected to pin PORADJ (R1 and R2 in Figure 1), then the
following occurs:
– The internal threshold voltage Vth2 is overridden by the external voltage and by the
hysteresis, therefore:
Vth2(ext)(rise) = (1 + R1/R2) x (Vbridge + Vhys(ext)/2)
Vth2(ext)(fall) = (1 + R1/R2) x (Vbridge - Vhys(ext)/2)
where Vbridge = 1.25 V typ. and Vhys(ext) = 60 mV typ.
– The reset pulse width tW is doubled to approximately 16 ms.
Input PORADJ is biased internally with a pull-down current source of 4 µA which is removed
when the voltage on pin PORADJ exceeds 1 V.
This ensures that after detection of the external bridge by the IC during power-on, the input
current on pin PORADJ does not cause inaccuracy of the bridge voltage.
The minimum threshold voltage should be higher than 2 V. The maximum threshold voltage
may be up to VDD.
5.2.3
Application examples
The voltage supervisor is used as power-on reset and as supply dropout detection during a
card session. Supply dropout detection is to ensure that a proper deactivation sequence is
followed before the voltage is too low. For the internal voltage supervisor to function, the
system microcontroller should operate down to 2.35 V to ensure a proper deactivation
sequence. If this is not possible, external resistor values can be chosen to overcome the
problem.
5.3
Clock circuitry
The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from a
crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be fXTAL, 1/2 x fXTAL, 1/4 x fXTAL or 1/8 x fXTAL. Frequency selection
is made via inputs CLKDIV1 and CLKDIV2 (see Table 21).
17/31
Functional description
Table 21.
ST8024
Clock frequency selection (1)
CLKDIV1
CLKDIV2
fCLK
0
0
fXTAL/8
0
1
fXTAL/4
1
1
fXTAL/2
1
0
fXTAL
1. The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum
between changes is needed; the minimum duration of any state of CLK is eight periods of XTAL1.
The frequency change is synchronous, which means that during transition no pulse is
shorter than 45 % of the smallest period, and that the first and last clock pulses about the
instant of change have the correct width.
When changing the frequency dynamically, the change is effective for only eight periods of
XTAL1 after the command. The duty factor of fXTAL depends on the signal present at pin
XTAL1. In order to reach a 45 to 55 % duty factor on pin CLK, the input signal on pin XTAL1
should have a duty factor of 48 to 52 % and transition times of less than 5 % of the input
signal period.
If a crystal is used, the duty factor on pin CLK may be 45 to 55 % depending on the circuit
layout and on the crystal characteristics and frequency. In other cases, the duty factor on pin
CLK is guaranteed between 45 and 55 % of the clock period.
The crystal oscillator runs as soon as the IC is powered up. If the crystal oscillator is used,
or if the clock pulse on pin XTAL1 is permanent, the clock pulse is applied to the card as
shown in the activation sequences shown in Figure 5 and Figure 6
If the signal applied to XTAL1 is controlled by the system microcontroller, the clock pulse will
be applied to the card when it is sent by the system microcontroller (after completion of the
activation sequence).
5.4
I/O transceivers
The three data lines I/O, AUX1 and AUX2 are identical.The idle state is realized by both I/O
and I/OUC lines being pulled HIGH via a 11 kΩ resistor (I/O to VCC and I/OUC to VDD). Pin
I/O is referenced to VCC, and pin I/OUC to VDD, thus allowing operation when VCC is not
equal to VDD. The first side of the transceiver to receive a falling edge becomes the master.
An anti-latch circuit disables the detection of falling edges on the line of the other side, which
then becomes a slave. After a time delay td(edge), an N transistor on the slave side is turned
on, thus transmitting the logic 0 present on the master side. When the master side returns to
logic 1, a P transistor on the slave side is turned on during the time delay tpu and then both
sides return to their idle states. This active pull-up feature ensures fast LOW-to-HIGH
transitions; it is able to deliver more than 1 mA at an output voltage of up to 0.9 VCC into an
80 pF load. At the end of the active pull-up pulse, the output voltage depends only on the
internal pull-up resistor and the load current. The current to and from the card I/O lines is
limited internally to 15 mA and the maximum frequency on these lines is 1 MHz.
18/31
ST8024
5.5
Functional description
Inactive mode
After a power-on reset, the circuit enters the inactive mode. A minimum number of circuits
are active while waiting for the microcontroller to start a session:
– All card contacts are inactive (approximately 200 Ω to GND)
– Pins I/OUC, AUX1UC and AUX2UC are in the high-impedance state (11 kΩ pull-up
resistor to VDD)
– Voltage generators are stopped
– XTAL oscillator is running
– Voltage supervisor is active
– The internal oscillator is running at its low frequency.
5.6
Activation sequence
After power-on and after the internal pulse width delay, the system microcontroller can
check the presence of a card using the signals OFF and CMDVCC as shown in Table 22.
If the card is in the reader (this is the case if PRES or PRES is active), the system
microcontroller can start a card session by pulling CMDVCC LOW. The following sequence
then occurs (see Figure 6):
1. CMDVCC is pulled LOW and the internal oscillator changes to its high frequency (t0).
2. The voltage doubler is started (between t0 and t1).
3. VCC rises from 0 to 5 V (or 3 V) with a controlled slope (t2 = t1 + 1.5 x T) where T is
64 times the period of the internal oscillator (approximately 25 µs).
4. I/O, AUX1 and AUX2 are enabled (t3 = t1 + 4T) (these were pulled LOW until this
moment).
5. CLK is applied to the C3 contact of the card reader (t4).
6. RST is enabled (t5 = t1 + 7T).
The clock may be applied to the card using the following sequence (see Figure 5):
1. Set RSTIN HIGH.
2. Set CMDVCC LOW.
3. Reset RSTIN LOW between t3 and t5; CLK will start at this moment.
4. RST remains LOW until t5, when RST is enabled to be the copy of RSTIN.
5. After t5, RSTIN has no further affect on CLK; this allows a precise count of CLK
pulses before toggling RST.
If the applied clock is not needed, then CMDVCC may be set LOW with RSTIN LOW. In this
case, CLK will start at t3 (minimum 200 ns after the transition on I/O), and after t5, RSTIN
may be set HIGH in order to obtain an Answer To Request (ATR) from the card.
Activation should not be performed with RSTIN held permanently HIGH
Table 22.
Card presence indicator
OFF
CMDVCC
Indication
H
H
Card present
L
H
Card not present
19/31
Functional description
20/31
ST8024
Figure 5.
Activation sequence using RSTIN and CMDVCC
Figure 6.
Activation sequence at t3
ST8024
5.7
Functional description
Active mode
When the activation sequence is completed, the ST8024 will be in its active mode. Data are
exchanged between the card and the microcontroller via the I/O lines.
The ST8024 is designed for cards without VPP (the voltage required to program or erase the
internal non-volatile memory).
5.8
Deactivation sequence
When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit
then executes an automatic deactivation sequence by counting the sequencer back and
finishing in the inactive mode (see Figure 7):
1. RST goes LOW (t10).
2. CLK is held LOW (t12 = t10 + 0.5 x T) where T is 64 times the period of the internal
oscillator (approximately 25 µs).
3. I/O, AUX1 and AUX2 are pulled LOW (t13 = t10 + T).
4. VCC starts to fall towards zero (t14 = t10 + 1.5 x T).
5. The deactivation sequence is complete at tde, when VCC reaches its inactive state.
6. VUP falls to zero (t15 = t10 + 5T) and all card contacts become low-impedance to GND;
I/OUC, AUX1UC and AUX2UC remain at VDD (pulled-up via a 11 kΩ resistor).
7. The internal oscillator returns to its lower frequency.
Figure 7.
5.9
Deactivation sequence
VCC generator
The VCC generator has a capacity to supply up to 80 mA continuously at 5 V and 65 mA at 3
V. An internal overload detector operates at approximately 120 mA. Current samples to the
21/31
Functional description
ST8024
detector are internally filtered, allowing spurious current pulses up to 200 mA with a duration
in the order of µs to be drawn by the card without causing deactivation. The average current
must stay below the specified maximum current value. For reasons of VCC voltage accuracy,
a 100 nF capacitor with an ESR < 100 mΩ should be tied to CGND near to pin VCC, and 100
nF capacitor with the same ESR should be tied to CGND near card reader contact C1.
5.10
Fault detection
The following fault conditions are monitored:
– Short-circuit or high current on VCC
– Removal of a card during a transaction
– VDD dropping
– DC-DC converter operating out of the specified values (VDDP too low or current from
VUP too high)
– Overheating.
– There are two different cases (see Figure 8):
– CMDVCC HIGH outside a card session. Output OFF is LOW if a card is not in the
card reader, and HIGH if a card is in the reader. A voltage drop on the VDD supply is
detected by the supply supervisor, this generates an internal Power-on reset pulse
but does not act upon OFF. No short-circuit or overheating is detected because the
card is not powered-up.
– CMDVCC LOW within a card session. Output OFF goes LOW when a fault condition
is detected. As soon as this occurs, an emergency deactivation is performed
automatically (see Figure 9). When the system controller resets CMDVCC to HIGH it
may sense the OFF level again after completing the deactivation sequence. This
distinguishes between a hardware problem or a card extraction (OFF goes HIGH
again if a card is present).
Depending on the type of card-present switch within the connector (normally-closed or
normally-open) and on the mechanical characteristics of the switch, bouncing may occur on
the PRES signals at card insertion or withdrawal.
There is a debounce feature in the device with an 8 ms typical duration (see Figure 8).
When a card is inserted, output OFF goes HIGH only at the end of the debounce time.
When the card is extracted, an automatic deactivation sequence of the card is performed on
the first true/false transition on PRES or PRES and output OFF goes LOW.
Figure 8.
22/31
Behavior of OFF, CMDVCC, PRES and VCC
ST8024
Functional description
Figure 9.
Emergency deactivation sequence (card extraction)
23/31
Application
6
ST8024
Application
Figure 10. Application diagram
10µF
100nF
+5V
100nF
100nF
(1)
CLKDIV1
1
28
AUX2UC
CLKDIV2
2
27
AUX1UC
5/3V
3
26
I/OUC
PGND
4
25
XTAL2
C1 +
5
24
XTAL1
VDDP
6
23
OFF
C1 -
7
22
GND
VUP
8
21
VDD
PRES
9
20
RSTIN
PRES
10
19
CMDVCC
I/O
11
18
PORADJ
AUX2
12
17
VCC
AUX1
13
16
RST
15
CLK
(1)
CGND
ST8024
14
+3.3 V POWERED
15pF
100nF
MICROCONTROLLER
10µF
(2)
+3.3V
+3.3V
Vdd
(3)
100nF
(4)
R1
R100K
(7)
+3.3V
CARD READER
(normally closed type)
R2
100nF
C5
C1
C6
C2
C7
C3
C8
C4
(5)
(6)
K1
K2
(1) These capacitors must be of the low ESR-type and be placed near the IC (within 100 mm).
(2) ST8024 and the microcontroller must use the same VDD supply.
(3) Make short, straight connections between CGND, C5 and the ground connection to the capacitor.
(4) Mount one low ESR-type 100 nF capacitor close to pin VCC.
(5) Mount one low ESR-type 100 nF capacitor close to C1 contact.
(6) The connection to C3 should be routed as far from C2, C7, C4 and C8 and, if possible, surrounded by
grounded tracks.
(7) Optional resistor bridge for changing the threshold of VDD. If this bridge is not required pin 18 should be
connected to ground.
24/31
ST8024
7
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
25/31
Package mechanical data
ST8024
SO-28 mechanical data
mm.
inch.
Dim.
Min.
Typ.
A
Max.
Min.
Typ.
2.65
Max.
0.104
a1
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.012
C
0.5
0.020
c1
45° (typ.)
D
17.70
18.10
0.697
0.713
E
10.00
10.65
0.393
0.419
e
1.27
0.050
e3
16.51
0.650
F
7.40
7.60
0.291
0.300
L
0.50
1.27
0.020
0.050
S
8° (max.)
0016023
26/31
ST8024
Package mechanical data
TSSOP28 mechanical data
mm.
inch.
Dim.
Min.
Typ.
A
Max.
Min.
Typ.
Max.
1.2
A1
0.05
A2
0.8
b
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0079
D
9.6
9.7
9.8
0.378
0.382
0.386
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
1
0.65 BSC
K
0°
L
0.45
0.60
0.0256 BSC
8°
0°
0.75
0.018
8°
0.024
0.030
0128292B
27/31
Package mechanical data
ST8024
Tape & reel SO-28 mechanical data
mm.
inch.
Dim.
Min.
A
Max.
Min.
330
13.2
Typ.
Max.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
28/31
Typ.
0.504
30.4
0.519
1.197
Ao
10.8
11.0
0.425
0.433
Bo
18.2
18.4
0.716
0.724
Ko
2.9
3.1
0.114
0.122
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
ST8024
Package mechanical data
Tape & reel TSSOP28 mechanical data
mm.
inch.
Dim.
Min.
A
Typ.
Max.
Min.
330
Max.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
Typ.
0.504
22.4
0.519
0.882
Ao
6.8
7
0.268
0.276
Bo
10.1
10.3
0.398
0.406
Ko
1.7
1.9
0.067
0.075
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
29/31
Revision history
ST8024
8
Revision history
Table 23.
Document revision history
Date
Revision
18-Mar-2004
4
Pag. 10, fig. 4, RSTIN ==> CLK.
27-Jun-2006
5
Add package TSSOP28.
13-Dec-2006
6
Removed: the comment point 5 on page 22.
03-Jun-2008
7
Added: Table 1 on page 1.
30-Mar-2009
8
Modified: Figure 10 on page 24.
30/31
Changes
ST8024
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
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