STA016A
MPEG 2.5 LAYER III AUDIO DECODER
SUPPORTING CD-ROM CAPABILITY
PRODUCT PREVIEW
STA016AASTA016AA
1
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FEATURES
Figure 1. Package
SINGLE CHIP MPEG LAYER 3 DECODER
SUPPORTING:
– All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
– All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
– Lower sampling frequencies syntax extension, (not specified by ISO) called MPEG 2.5
DECODES LAYER III STEREO CHANNELS,
DUAL CHANNEL, SINGLE CHANNEL (MONO)
SUPPORTING ALL THE MPEG 1 & 2
SAMPLING FREQUENCIES AND THE
EXTENSION TO MPEG 2.5:48, 44.1,32,
24,22.05, 16, 12,11. 025, 8 KHz
ACCEPTS MPEG 2.5 LAYER III
ELEMENTARY COMPRESSED BITSTREAM
WITH DATA RATE FROM 8 Kbit/s UP TO 320
Kbit/s
BYPASS MODE FOR EXTERNAL AUXILIARY
AUDIO SOURCE
EMBEDDED ISO9660 LAYER FOR FILESYSTEM DECODING (JOLIET)
EMBEDDED CD-ROM DECODER BLOCKS
INCLUDING ECC/EDC CAPABILITY
Table 1. Order Codes
Part Number
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od
r
P
e
FLEXIBLE I2S INPUT INTERFACE FOR EASY
CONNECTION WITH MOST CD-SERVO
DEVICES
EMBEDDED BROWSING COMMAND
INTERPRETER FOR EASY FILE-SYSTEM
BROWSING
CUE-SHEET CAPABILITY UP TO 100
ENTRIES
BROWSER COMMAND INTERPRETER (BCI)
– Parent Dir
– Enter Dir
– Previous Entry
– Next Entry
– Get Record Infos
EASY PROGRAMMABLE GPSO INTERFACE
(MONO/STEREO) FOR ENCODED DATA UP
TO 5Mbit/s
DIGITAL VOLUME
let
o
s
b
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O
u
d
o
Package
r
P
e
STA016A
TQFP64
BASS & TREBLE CONTROL
SERIAL BITSTREAM INPUT INTERFACE
EASY PROGRAMMABLE ADC INPUT
INTERFACE
t
e
l
o
s
b
O
SERIAL PCM OUTPUT INTERFACE (I2S AND
OTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR
OUTPUT PCM CLOCK GENERATION
CRC CHECK AND SYNCHRONISATION
ERROR DETECTION WITH SOFTWARE
INDICATORS
)
(s
t
c
u
)
s
(
ct
TQFP64
I2C CONTROL BUS
LOW POWER 2.4V CMOS TECHNOLOGY
WITH 3.3V TOLERANT AND CAPABLE I/O
FAST FORWARD AND PAUSE CAPABILITIES
ADDITIONAL FEATURES AVAILABLE VIA
SOFTWARE
– MMC and SD card: read and format ia SPI
– MMC an SD cards: write
– Sample Rate Converter for MPEG streams:
from general input frequence to internal
44.1kHz
– Generic features
– Faster browsing, feed forward and rewind capabilities
– long file name support
1.1 APPLICATIONS
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AUDIO CD PLAYERS
MULTIMEDIA PLAYERS
CD-ROM PLAYERS
CAR RADIO PLAYERS
July 2004
This is preliminary information on a new product now in development. Details are subject to change without notice.
REV. 1
1/43
STA016A
2
DESCRIPTION
The STA016A is a single chip MPEG 1, 2 and 2.5 Layer III audio decoder with embedded CDROM decoding
capability. It can be easily connected to most existing CDDSP devices via a software configurable serial link. A
tipical application block diagram is show in Figure 1. The audio sources, for instance could be an external flash
memory.
A useful bypass mode allow using this device also as an audio processor for volume and tone controls.
Figure 2. Typical CD-Player application
CD
M ec h a nic
)
s
(
ct
TUNER M O DULE
OR
A U X . A U D IO
SO UR C E
C D D S P I /F
I2 S O U T
e
t
e
ol
CD D SP
S T A 016
I2 C
)
(s
SDI
MCU
GPSO
ct
u
d
o
CD M O DULE
r
P
e
s
b
O
u
d
o
Pr
D /A
L
R
FL ASH M E M O RY
for
M P 3 f ile s
e n c od e d m e ssa g es
( o p t io n a l)
Table 2. ABSOLUTE MAXIMUM RATINGS
t
e
l
o
Symbol
Parameter
Value
Unit
VDD
Digital Power Supply at 2.5V (nominal)
-0.5 to 3.3
V
VCC
Digital Power Supply at 3.3V (nominal)
-0.5 to 4
V
-0.5 to 3.3
V
-0.5 to VCC +0.5
V
s
b
O
PLL-VCC
VIH/VIL
Analog Supply Voltage at 2.5V (nominal)
Voltage on input pins (3.3V pads)
Tstg
Storage Temperature
-40 to +150
°C
Top
Operative ambient temp
-40 to +85(*)
°C
-40 to 125
°C
Value
Unit
85
°C/W
Tj
Operating Junction Temperature
(*) guarantee by design
Table 3. THERMAL DATA
Symbol
Parameter
Rth j-amb
Thermal resistance Junction to Ambient
2/43
STA016A
3
OVERVIEW
The device can decode/process data coming from three possible sources, as showed in Figure 2:
■ CDDSP serial link: using this input interface, besides MP3 encoded data CD, it's possible to playback
also standard Audio CD using the available volume and tone equalizer features of the device and
allowing the use of only one D/A converter with no external analog switch.
■ SDI input interface: through this input interface it's possible to decode any MP3 bitstream coming, for
instance, from an external flash memory.
■
I2S input interface: this interface can be used to process an external audio source (tuner, for instance)
through the DSP based volume and tone controls:this BYPASS mode can avoid the use of additional
D/A converters or postprocessing units.
)
s
(
ct
3.1 MP3 decoder engine
The MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and MPEG2.5
streams are supported.
Decoded audio data goes through a software volume control and a two-band equalizer blocks before feeding
the output I2S interface. This results in no need for an external audio processor.
u
d
o
Table 4. MPEG Sampling Rates (KHz)
MPEG 1
MPEG 2
48
24
44.1
22.05
32
16
BS_SDI
s
b
O
DREQ
SDI
SYNC
DETECT.
I2S IN
I/F
LRCKI
STB
11.025
8
DESCRAM.
ECC/EDC
SECTOR
BUFFER
SDI
I/F
BCKI
12
CDROM DECODER (C3)
t
e
l
o
BS_BCK
BS_LRCK
du
ro
P
e
CD_LRCK
o
s
b
MPEG 2.5
s
(
t
c
CD_BCK
CDDSP
I/F
let
O
)
Figure 3. Block Diagram
CD_SDI
r
P
e
INPUT SELECTOR
MMDSP
CORE
- ISO9660 + JOLIET
- BCI
- MP3
BCKO
I2S OUT
I/F
PCM OUTPUT
BUFFER
SDO
LRCKO
RQST
SCL
SDA
GPSO_CK
I2C
I/F
I2C
REG BANK
PLL
OSCK
OSC
XTI
XTO
GPSO_SDO
GPSO
I/F
GPSO_REQ
D04AU1565
The basic functions of the device can be fully operated via the I2C bus. Besides that the GPSO interface can be
used to move huge amount of data this fast and flexible interface can achieve transfer rates up to 5 Mbit/s.
The embedded DSP firmware implements all the layers required to decode a standard data CD, as shown in
the Figure 4:
3/43
STA016A
Figure 4. Layers performed by embedded DSP firmware
FRAMES to SECTOR TRANSLATOR
SYNC DETECTOR
DESCRAMBLER
EDC/ECC (C3)
ISO9660 File System Decoding
(with Joliet support)
)
s
(
ct
Browsing Command Interface
u
d
o
r
P
e
The whole CDROM and file-system decoding task is performed by embedded firmware. The application MCU,
basically, must manage CDDSP device according to STA016A requests. Three basic command flows exist:
■ MCU -> STA016A: commands used to handle decoder operation and to ask for specific information like
filename, filelength, sector raw data, etc. This flow will use I2C (GPSO for special operations) interface.
■ STA016A -> MCU: this channel is used to retrieve inquired information and to inform MCU that a
CDDSP specific operation must be performed (like pick-up repositioning). This flow is based on I2C link
plus an additional interrupt signal in order to avoid time consuming polling techniques.
■ MCU -> CDDSP: the CDDSP management is fully up to the application MCU. This architecture allows
maximum flexibility and easy migration from existing CDPlayers to MP3 CDPlayers.
t
e
l
o
let
so
b
O
IODATA13
IODATA14
IODATA15
VSS_7
VDD_5
GPSO_CK
GPSO_SDO
GPSO_REQ
VCC_3
RQST
VSS_9
VDD_6
SCL
P
e
SDA
d
o
r
STB
t
c
u
Figure 5. PIN CONNECTION
VSS_8
)
(s
s
b
O
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
CD_LRCK
1
48
IODATA12
CD_BCK
2
47
IODATA11
CD_SDI
3
46
IODATA10
DREQ
4
45
IODATA9
VDD_1
5
44
IODATA8
VSS_1
6
43
VSS_6
BS_LRCK
7
42
VCC_2
BS_BCK
8
41
PLL_GND
BS_SDI
9
40
FILT0
VDD_2
10
39
PLL_VCC
VSS_2
11
38
FILT1
LRCK1
12
37
VSS_5
BCKI
13
36
VDD_4
SDI
14
35
IODATA7
RESET
15
34
IODATA6
TESTEN
16
33
IODATA5
IODATA4
IODATA3
VSS_4
VDD_3
IODATA2
IODATA1
IODATA0
CLKOUT
VSS_3
VCC_1
SDO
BCKO
LRCKO
OSCK
XTI
4/43
XTO
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D00AU1227
STA016A
Table 5. PIN DESCRIPTION
PIN
Pin Name
Type
Description
Sourde/Dest
CDDSP interface
1
CD_LRCK
I
DSP Interface left/right Clock
From DSP
3
CD_SDI
I
DSP interface serial data
From DSP
2
CD_BCK
I
DSP interface bit clock
From DSP
SDI interface
9
BS_SDI
I
Bitstream interface serial data
From MCU
7
BS_LRCK
I
Bitstream interface left/right Clock
From MCU
8
BS_BCK
I
Bitstream interface clock
From MCU
4
DREQ
O
Bitstream data request
To MCU
u
d
o
PCM IN interface
13
BCKI
I
ADC bit clock
14
SDI
I
ADC serial data
12
LRCKI
I
ADC left/right Clock
)
s
(
ct
From ADC
r
P
e
From ADC
t
e
l
o
PCM OUT interface
20
LRCKO
O
DAC Interface left/right Clock
22
SDO
O
DAC serial data
21
BCKO
O
DAC bit clock
19
OSCK
O
DAC oversampling clock
55
GPSO_CK
I
GPSO bit clock
54
GPSO_SDO
O
56
GPSO_REQ
O
du
26
IODATA0
I/O
GPIODATA0
27
IODATA1
I/O
GPIODATA1
28
IODATA2
I/O
GPIODATA2
IODATA3
I/O
GPIODATA3
IODATA4
I/O
GPIODATA4
IODATA5
I/O
GPIODATA5
34
IODATA6
I/O
GPIODATA6
35
IODATA7
I/O
GPIODATA7
44
IODATA8
I/O
GPIODATA8
45
IODATA9
I/O
GPIODATA9
46
IODATA10
I/O
GPIODATA10
47
IODATA11
I/O
GPIODATA11
48
IODATA12
I/O
GPIODATA12
49
IODATA13
I/O
GPIODATA13
50
IODATA14
I/O
GPIODATA14
51
IODATA15
I/O
GPIODATA15
)-
s
(
t
c
s
b
O
From ADC
To DAC
To DAC
To DAC
To DAC/ADC
GPSO interface
o
s
b
31
32
O
33
e
t
e
l
o
r
P
From MCU
GPSO serial data
To MCU
GPSO request signal
To MCU
GPIO interface
5/43
STA016A
Table 5. PIN DESCRIPTION (continued)
PIN
Pin Name
Type
Description
Sourde/Dest
HANDSHAKE SIGNALS
60
STB
I
Strobe signal
From MCU
59
RQST
O
I2C data signal
To MCU
2
I C LINK
63
SCL
I
I2C clock signal
From MCU
64
SDA
I/O
I2C data signal
To MCU
MISCELLANEOUS
)
s
(
ct
17
XTI
I
Oscillator input
18
XTO
O
Oscillator output
25
CLKOUT
O
Buffered output clock
15
-RESET
I
Reset
16
-TESTEN
I
Reserved for test purpose
40
FILT0
I
PLL external filter
38
FILT1
u
d
o
PLL external filter
t
e
l
o
POWER SUPPLY
39
PLL_VCC
Digital supply (2.5V Power Supply)
41
PLL_GND
5
VDD_1
Digital supply (2.5V Power Supply)
10
VDD_2
Digital supply (2.5V Power Supply)
29
VDD_3
Digital supply (2.5V Power Supply)
36
VDD_4
Digital supply (2.5V Power Supply)
53
VDD_5
Digital supply (2.5V Power Supply)
62
VDD_6
23
VCC_1
42
VCC_2
Ground
)
(s
s
b
O
t
c
u
d
o
r
Digital supply (2.5V Power Supply)
P
e
Digital supply (3.3V Power Supply)
11
t
e
l
o
Digital supply (3.3V Power Supply)
58
6
VCC_3
Digital supply (3.3V Power Supply)
VSS_1
Ground
VSS_2
Ground
24
VSS_3
Ground
30
VSS_4
Ground
37
VSS_5
Ground
43
VSS_6
Ground
52
VSS_7
Ground
57
VSS_8
Ground
61
VSS_9
Ground
6/43
s
b
O
r
P
e
STA016A
4
ELECTRICAL CHARACTERISTCS
(Tamb = 25°C; Rg = 50Ω unless otherwise specified)
Table 6. DC OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
VDD
Power Supply Voltage
2.5 ± 0.25
V
VCC
Power Supply Voltage
3.3 ± 0.3
V
PLL_VCC
Power Supply Voltage
2.5 ± 0.25
V
)
s
(
ct
Table 7. GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
IIL
Low Level Input
Vi = 0V
CurrentWithout pull-up device
-10
IIH
High Level Input
Vi = VDD
CurrentWithout pull-up device
-10
Vesd
Electrostatic Protection
Leakage < 1µA
Typ.
10
r
P
e
t
e
l
o
2000
u
d
o
Max.
10
Unit
µA
Note
1
µA
1
V
2
s
b
O
Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress
on the pin.
Note 2: Human Body Model.
)
(s
Table 8. DC ELECTRICAL CHARACTERISTICS
Symbol
ct
Parameter
Test Condition
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
Vol
Low Level Output Voltage
Voh
High Level Output Voltage
ro
du
P
e
Min.
Typ.
Max.
Unit
0.2*VCC
V
0.8*VCC
V
Iol = Xma
0.4V
0.85*VCC
t
e
l
o
Note
V
1, 2
V
1, 2
Note1: Takes into account 200mV voltage drop in both supply lines.
Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
s
b
O
Table 9.
Symbol
Parameter
Ipu
Pull-up current
Rpu
Equivalent Pull-up Resistance
Test Condition
Vi = 0V; pin numbers 7, 24
and 26
Min.
Typ.
Max.
Unit
Note
-25
-66
-125
µA
1
50
kΩ
Note 1: Min. condition: VDD = 2.7V, 125°C Min process Max. condition: VDD = 3.6V, -20°C Max.
Table 10. POWER DISSIPATION
Symbol
Parameter
PD
Power Dissipation@ VDD = 2.4V
Test Condition
Min.
Typ.
Max.
Unit
Sampling_freq ≤24 kHz
t.b.d.
mW
Sampling_freq ≤32 kHz
t.b.d.
mW
Sampling_freq ≤48 kHz
t.b.d.
mW
Note
7/43
STA016A
5
HOST REGISTERS
The following table gives a description of STA016A register list.
The STA016A device includes 256 I2C registers. In this document, only the user-oriented registers are described. The undocumented registers are reserved or unused. These registers must never be accessed (in
Read or in Write mode). The Read-Only registers must never be written
We can split the data flux in different time periods (see following diagram) meanwhile host registers can be read
or written :
■ DWT : During Whole Time (at any time during process).
■ DEC : During External Config (period between RUN=2 and RUN=1).
■ DBO : During Boot (period between RUN=0 and RUN=2).
■ ABO : After BOot (period after RUN=1).
■ AEC : After External Config (period after RUN=2).
■ EDF : Every Decoded Frame (each time a frame has been decoded).
■ EDB : Every Decoded Block (each time a block has been decoded).
)
s
(
ct
u
d
o
r
P
e
Figure 6.
t
e
l
o
SOFT_RESET = 1
CK_CMD = 0
HR
RUN==0
RUN==2
DBO
RUN==1
t
e
l
o
s
b
O
8/43
O
)
du
ro
P
e
bs
block2
frame1
s
(
t
c
DEC
D01AU1260
block1
frame1
block1
frame2
DWT
ABO
AEC
EDB
EDB
EDF
EDB
time
STA016A
Table 11. REGISTER MAP BY FUNCTION
Register function
VERSION
PLL_AUDIO_CONFIGURATION
PLL_SYSTEM_CONFIGURATION
Hex
Dec
0x00
0
0x01
1
0xD3
Type
When
VERSION
RO
DWT
IDENT
RO
DWT
211
SOFT_VERSION
RO
DWT
0xDC
220
PLL_AUDIO_PEL_192
RW
DEC
0xDD
221
PLL_AUDIO_PEH_192
RW
DEC
0xDE
222
PLL_AUDIO_NDIV_192
RW
DEC
0xDF
223
PLL_AUDIO_XDIV_192
RW
DEC
0xE0
224
PLL_AUDIO_MDIV_192
RW
DEC
0xE1
225
PLL_AUDIO_PEL_176
RW
DEC
0xE2
226
PLL_AUDIO_PEH_176
RW
DEC
0xE3
227
PLL_AUDIO_NDIV_176
0xE4
228
PLL_AUDIO_XDIV_176
0xE5
229
PLL_AUDIO_MDIV_176
0xE6
230
0xE7
DEC
RW
DEC
PLL_SYSTEM_PEL_50
RW
DEC
231
PLL_SYSTEM_PEH_50
RW
DEC
0xE8
232
PLL_SYSTEM_NDIV_50
RW
DEC
0xE9
233
PLL_SYSTEM_XDIV_50
RW
DEC
PLL_SYSTEM_MDIV_50
RW
DEC
PLL_SYSTEM_PEL_42_5
RW
DEC
236
PLL_SYSTEM_PEH_42_5
RW
DEC
0xED
237
PLL_SYSTEM_NDIV_42_5
RW
DEC
0xEE
238
PLL_SYSTEM_XDIV_42_5
RW
DEC
0xEF
239
PLL_SYSTEM_MDIV_42_5
RW
DEC
0x66
102
OUTPUT_CONF
RW
DEC
0x67
103
PCM_DIV
RW
DEC
0x68
104
PCM_CONF
RW
DEC
0x69
105
PCM_CROSS
RW
DEC
GPSO_CONFIGURATION
0x66
102
OUTPUT_CONF
RW
DEC
0x6A
106
GPSO_CONF
RW
DEC
I2Sin_CONFIGURATION
0x5A
90
INPUT_CONF
RW
DEC
0x5B
91
I_AUDIO_CONFIG_1
RW
DEC
0x5C
92
I_AUDIO_CONFIG_2
RW
DEC
0x5D
93
I_AUDIO_CONFIG_3
RW
DEC
e
t
e
l
234
235
o
s
b
O
)
s
(
t
c
du
ro
s
b
O
Pr
RW
0xEC
t
e
l
o
u
d
o
DEC
0xEB
I2Sout_CONFIGURATION
)
s
(
ct
RW
0xEA
P
e
Name
9/43
STA016A
Register function
CDBSA_CONFIGURATION
BSB_CONFIGURATION
CD_CONFIGURATION
Hex
Dec
0x5A
90
0x5B
Type
When
INPUT_CONF
RW
DEC
91
I_AUDIO_CONFIG_1
RW
DEC
0x5C
92
I_AUDIO_CONFIG_2
RW
DEC
0x5D
93
I_AUDIO_CONFIG_3
RW
DEC
0x5E
94
I_AUDIO_CONFIG_4
RW
DEC
0x5F
95
I_AUDIO_CONFIG_5
RW
DEC
0x60
96
I_AUDIO_CONFIG_6
RW
DEC
0x61
97
I_AUDIO_CONFIG_7
RW
DEC
0x62
98
I_AUDIO_CONFIG_8
RW
DEC
0x63
99
I_AUDIO_CONFIG_9
RW
DEC
0x64
100
I_AUDIO_CONFIG_10
RW
0x65
101
I_AUDIO_CONFIG_11
0x59
89
POL_REQ
0x5A
90
INPUT_CONF
0x5B
91
I_AUDIO_CONFIG_1
0x40
64
0x41
65
0x42
66
0x43
67
DEC
RW
DEC
RW
DEC
BASIC_COMMAND
WO
AEC
FAST_FUNCTION_VAL
RW
ABO
REQUIRED_TRACK
RW
ABO
REQUIRED_DIR
RW
ABO
PLAY_MODE
RW
ABO
70
TYPE _CD_EXT_REQ
RO
AEC
71
MINUTE_REQ
RO
AEC
0x48
72
SECOND_REQ
RO
AEC
0x49
73
SECTOR_REQ
RO
AEC
0x4A
74
MINUTE_SPENT
RO
AEC
0x4B
75
SECOND_SPENT
RO
AEC
0x4C
76
SCANNING_TIME
RW
ABO
0x4D
77
PLAY_LIST_INDEX
RW
ABO
0x4E
78
PLAY_LIST_VALUE
RW
ABO
0x47
o
r
P
)-
s
(
t
c
du
10/43
P
e
DEC
DEC
0x46
s
b
O
du
ro
RW
)
s
(
ct
RW
0x44
e
t
e
ol
Name
68
t
e
l
o
s
b
O
STA016A
Register function
Hex
Dec
0x86
134
0x87
Type
When
CD_SONG_INFO_C1
RO
AEC
135
CD_SONG_INFO_C2
RO
AEC
0x88
136
CD_SONG_INFO_C3
RO
AEC
0x89
137
CD_SONG_INFO_C4
RO
AEC
0x8A
138
CD_SONG_INFO_C5
RO
AEC
0x8B
139
CD_SONG_INFO_C6
RO
AEC
0x8C
140
CD_SONG_INFO_C7
RO
AEC
0x8D
141
CD_SONG_INFO_C8
RO
AEC
0x8E
142
CD_SONG_INFO_C9
RO
AEC
0x8F
143
CD_SONG_INFO_C10
RO
AEC
0x90
144
CD_SONG_INFO_C11
RO
0x91
145
CD_SONG_INFO_C12
0x92
146
CD_SONG_INFO_C13
0x93
147
CD_SONG_INFO_C14
0x94
148
CD_SONG_INFO_C15
0x95
149
0x96
150
0x97
151
0x98
152
P
e
AEC
AEC
AEC
RO
AEC
RO
AEC
CD_SONG_INFO_C16
RO
AEC
CD_SONG_INFO_C17
RO
AEC
CD_SONG_INFO_C18
RO
AEC
CD_SONG_INFO_C19
RO
AEC
CD_SONG_INFO_C20
RO
AEC
154
CD_SONG_INFO_C21
RO
AEC
155
CD_SONG_INFO_C22
RO
AEC
0x9C
156
CD_SONG_INFO_C23
RO
AEC
0x9D
157
CD_SONG_INFO_C24
RO
AEC
0x9E
158
CD_SONG_INFO_C25
RO
AEC
0x9F
159
CD_SONG_INFO_C26
RO
AEC
0xA0
160
CD_SONG_INFO_C27
RO
AEC
0xA1
161
CD_SONG_INFO_C28
RO
AEC
0xA2
162
CD_SONG_INFO_C29
RO
AEC
0xA3
163
CD_SONG_INFO_C30
RO
AEC
0xA4
164
CD_SONG_INFO_C31
RO
AEC
0xA5
165
CD_SONG_INFO_C32
RO
AEC
0xA6
166
CD_SONG_TYPE_INFO
RO
AEC
0x9B
o
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P
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)-
s
(
t
c
du
0x9A
s
b
O
du
ro
RO
)
s
(
ct
RO
0x99
e
t
e
ol
Name
153
s
b
O
11/43
STA016A
Register function
Hex
Dec
0xA7
167
0xA8
Type
When
NB_OF_CUR_TRACK
RO
AEC
168
NB_OF_CUR_DIR
RO
AEC
0xA9
169
CD_CUR_STATUS
RO
AEC
0xAA
170
CD_TRACK_FORMAT
RO
AEC
0xAB
171
CD_NB_OF_SUB_DIR
RO
AEC
0xAC
172
CD_NB_OF_SUB_FILE
RO
AEC
0xAD
173
DIRECTORY_LEVEL
RO
AEC
0xAE
174
DIR_IDENTIFIER_B1
RO
AEC
0xAF
175
DIR_IDENTIFIER_B2
RO
AEC
0xB0
176
DIR_IDENTIFIER_B3
RO
AEC
0xB1
177
DIR_IDENTIFIER_B4
RO
0xB2
178
VOL_IDENTIFIER_B1
0xB3
179
VOL_IDENTIFIER_B2
0xB4
180
VOL_IDENTIFIER_B3
0xB5
181
VOL_IDENTIFIER_B4
0xB6
182
0xB7
183
0xB8
184
0xB9
185
12/43
AEC
RO
AEC
RO
AEC
EXTRACT_BYTE_IDX_B1
RW
ABO
EXTRACT_BYTE_IDX_B2
RW
ABO
EXTRACT_BYTE_IDX_B3
RW
ABO
EXTRACT_BYTE_IDX_B4
RW
ABO
EXTRACT_ADR_MODE
RW
ABO
188
CONFIG_MODULE
RW
DEC
16
SOFT_RESET
WO
DWT
0x3A
58
CK_CMD
WO
DBO
0x55
85
DEC_SEL
RW
DEC
0x56
86
RUN
RW
DEC
0x52
82
CRC_IGNORE
RW
ABO
0x53
83
MUTE
RW
ABO
0x57
87
SKIP
RW
ABO
0x58
88
PAUSE
RW
ABO
0x10
o
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)-
s
(
t
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du
s
b
O
P
e
AEC
AEC
0xBC
e
t
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ol
du
ro
RO
)
s
(
ct
RO
0xBA
COMMAND
Name
186
s
b
O
STA016A
Register function
STATUS
BYPASSA_CONFIGURATION
MP3_CONFIGURATION
RESERVED
Hex
Dec
0xCC
204
0xCD
Type
When
STATUS_MODE
RO
EDF
205
STATUS_CHAN_NB
RO
EDF
0xCE
206
STATUS_SF
RO
EDF
0x6F
111
STATUS_FE
RO
EDF
0xD4
212
HEADER_1
RO
EDF
0xD5
213
HEADER_2
RO
EDF
0xD6
214
HEADER_3
RO
EDF
0xD7
215
HEADER_4
RO
EDF
0xD8
216
HEADER_5
RO
EDF
0xD9
217
HEADER_6
RO
EDF
0x70
112
CHAN_NB
RW
0x71
113
SAMPLING_FREQ
0xCB
203
PCMCLK_INPUT
0x52
82
CRC_IGNORE
0x6B
107
ERR_DEC_LEVEL
0x6C
108
0x6D
109
0x70
112
0x71
113
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e
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ol
s
b
O
TONE_CONFIGURATION
P
e
DEC
DEC
DEC
RW
ABO
RO
EDB
ERR_DEC_NB_1
RO
EDB
ERR_DEC_NB_2
RO
EDB
t
e
l
o
s
b
O
RESERVED
RESERVED
RESERVED
115
RESERVED
116
RESERVED
0x75
117
MIX_MODE
RW
ABO
0x76
118
MIX_DLA
RW
ABO
0x77
119
MIX_DLB
RW
ABO
0x78
120
MIX_DRA
RW
ABO
0x79
121
MIX_DRB
RW
ABO
0x7A
122
TONE_ON
RW
ABO
0x7B
123
TONE_FCUTH
RW
ABO
0x7C
124
TONE_FCUTL
RW
ABO
0x7D
125
TONE_GAINH
RW
ABO
0x7E
126
TONE_GAINL
RW
ABO
0x7F
127
TONE_GAIN_ATTEN
RW
ABO
0x74
MIX_CONFIGURATION
114
du
ro
RW
)
s
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RW
)-
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0x72
0x73
Name
o
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P
13/43
STA016A
6
REGISTER DESCRIPTION
6.2 PLL_AUDIO_CONFIGURATION registers
description
6.1 VERSION registers description
6.1.1
b7
6.2.1
VERSION :
b6
b5
b7
b4
b3
b2
b1
b0
PLL_AUDIO_PEL_192 :
b6
b5
b4
b3
b2
b1
b0
Address : 0xDC (220)
Address : 0x00 (0)
Type : RW - DEC
Type : RO - DWT
Software Reset : 58
Software Reset : 0x10
)
s
(
ct
Hardware Reset : 0x10
Description :
Description :
This register must contain a PEL value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
The VERSION register is Read-only and it is used to
identify the IC on the application board.
ofact is the oversampling factor needed by the DAC
(ofac==246 or ofac==384).
6.1.2
Default value at soft reset assume :
– ofact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
1
1
0
0
r
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o
IDENT :
b7
u
d
o
s
b
O
6.2.2
)
(s
Address : 0x01 (1)
b7
Type : RO - DWT
ct
Software Reset : 0xAC
Hardware Reset : 0xAC
du
Description :
o
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P
s
b
O
6.1.3
b7
SOFT_VERSION :
b6
b5
b4
b3
b2
b1
b6
b5
b4
b3
b2
b1
b0
Address : 0xDD (221)
Type : RW - DEC
Software Reset : 187
IDENT is a read-only register and it is used to identify
the IC on an application board. IDENT always has the
value 0xAC.
e
t
e
ol
PLL_AUDIO_PEH_192 :
b0
Address : 0xD3 (211)
Description :
This register must contain a PEH value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
– ofact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
Type : RO - DWT
Software Reset : X
6.2.3
b7
PLL_AUDIO_NDIV_192 :
b6
b5
Description :
The SOFT_VERSION register is Read-only and it is
used to identify the software running on the IC.
Address : 0xDE (222)
Type : RW - DEC
Software Reset : 0
14/43
b4
b3
b2
b1
b0
STA016A
Description :
Address : 0xE1 (225)
This register must contain a NDIV value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Type : RW - DEC
Default value at soft reset assume :
– ofact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
6.2.4
b7
b5
b4
b3
b2
b1
Description :
This register must contain a PEL value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
– fact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
PLL_AUDIO_XDIV_192 :
b6
Software Reset : 54
b0
Address : 0xDF (223)
6.2.7
Type : RW - DEC
Software Reset : 3
b7
b5
Address : 0xE2 (226)
This register must contain a XDIV value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Type : RW - DEC
b7
PLL_AUDIO_MDIV_192 :
b6
b5
b4
Address : 0xE0 (224)
b3
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e
b2
b1
b0
t
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l
o
Type : RW - DEC
bs
Default value at soft reset assume :
– ofact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
PLL_AUDIO_NDIV_176 :
b6
b5
Address : 0xE3 (227)
This register must contain a MDIV value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Type : RW - DEC
6.2.6
b7
PLL_AUDIO_PEL_176 :
b6
b5
b4
b3
b2
b1
b0
b0
s
b
O
Description :
Default value at soft reset assume :
– ofact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
b1
This register must contain a PEH value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
b7
O
b2
Description :
6.2.8
Software Reset : 12
Pr
b3
Software Reset : 118
)
(s
6.2.5
b4
e
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e
ol
Description :
Default value at soft reset assume :
– ofact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
u
d
o
PLL_AUDIO_PEH_176 :
b6
)
s
(
ct
b4
b3
b2
b1
b0
Software Reset : 0
Description :
This register must contain a NDIV value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
– ofact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
15/43
STA016A
6.2.9
b7
PLL_AUDIO_XDIV_176 :
b6
b5
b4
b3
b2
Description :
b1
This register must contain a PEL value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
b0
Address : 0xE4 (228)
Software Reset : 2
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
Description :
6.3.2
Type : RW - DEC
This register must contain a XDIV value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
– ofact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
b7
PLL_SYSTEM_PEH_50 :
b6
b5
b4
b3
b7
b6
b5
b4
b3
b2
b1
Type : RW - DEC
u
d
o
Software Reset : 0
r
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)
(s
t
c
u
Description :
This register must contain a MDIV value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1,2 & 3.
d
o
r
P
e
Default value at soft reset assume :
– ofact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
let
so
Address : 0xE6 (230)
b4
b3
b2
b1
b7
PLL_SYSTEM_NDIV_50 :
b6
b5
b2
b1
b0
Type : RW - DEC
Software Reset : 0
Description :
b0
6.3.4
b7
PLL_SYSTEM_XDIV_50 :
b6
b5
Address : 0xE9 (233)
Type : RW - DEC
Software Reset : 1
16/43
b3
Address : 0xE8 (232)
Type : RW - DEC
Software Reset : 0
b4
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_PEL_50 :
b5
6.3.3
This register must contain a NDIV value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
6.3 PLL_SYSTEM_CONFIGURATION
registers description
b6
s
b
O
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
Software Reset : 8
b7
)
s
(
ct
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o
b0
Type : RW - DEC
6.3.1
b0
This register must contain a PEH value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
Address : 0xE5 (229)
b
O
b1
Address : 0xE7 (231)
Description :
6.2.10 PLL_AUDIO_MDIV_176 :
b2
b4
b3
b2
b1
b0
STA016A
Description :
This register must contain a XDIV value that enables
the system PLL to generate a frequency of 50 MHZ
for the SYSCK. See table 4.
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
6.3.5
b7
b5
b4
b3
b2
This register must contain a PEH value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
6.3.8
PLL_SYSTEM_MDIV_50 :
b6
Description :
b1
6.3.9
b0
b7
Address : 0xEA (234)
Type : RW - DEC
PLL_SYSTEM_NDIV_42_5 :
b6
b5
b4
b3
Type : RW - DEC
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
b7
PLL_SYSTEM_PEL_42_5
b6
b5
b4
Address : 0xE6 (230)
b3
b2
d
o
r
b0
P
e
Type : RW - DEC
o
s
b
Description :
6.3.10 PLL_SYSTEM_XDIV_42_5 :
b7
b6
b5
b4
b3
b2
b1
b0
Software Reset : 1
O
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
b7
s
b
O
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
Type : RW - DEC
This register must contain a PEL value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
6.3.7
This register must contain a NDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Address : 0xE9 (233)
let
Software Reset : 126
t
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l
o
Description :
)
(s
t
c
u
b1
b0
r
P
e
Software Reset : 0
Description :
This register must contain a MDIV value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
)
s
(
ct
b1
u
d
o
Address : 0xE8 (232)
Software Reset : 13
6.3.6
b2
Description :
This register must contain a XDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_PEH_42_5 :
b6
b5
Address : 0xE7 (231)
Type : RW - DEC
b4
b3
b2
b1
b0
6.3.11 PLL_SYSTEM_MDIV_42_5 :
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xEA (234)
Software Reset : 223
17/43
STA016A
Type : RW - DEC
6.4.3
Software Reset : 10
Description :
This register must contain a MDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
b7
b5
b4
b3
b2
b1
b0
b3
b2
b1
b0
0
CO6
CO5
CO4
CO3
CO2
CO1
CO0
Address : 0x68 (104)
Type : RW - DEC
Software Reset : 0
Description :
)
(s
Description :
If set to 1 enable the configurability of the PCMBLOCK Output thanks to following registers, else disable this configurability and take embedded default
configuration for PCM-BLOCK registers.
t
c
u
d
o
r
Note that this embedded default configuration can be
retrieved by user thanks to following setting :
– PCM_DIV = 3;
– PCM_CONF = 0;
– PCM_CROSS = 0;
P
e
t
e
l
o
s
b
O
)
s
(
ct
u
d
o
b5
b4
b3
b2
b1
b0
0
DV5
DV4
DV3
DV2
DV1
DV0
bits mode (16 slots transmitted).
bits mode (18 slots transmitted).
bits mode (20 slots transmitted).
bits mode (24 slots transmitted).
t
e
l
o
Polarity of BCKO :
0 : data are sent on the falling edge & stable
on the rising).
1 : (data are sent on the rising edge & stable
on the falling).
CO3
0 : I2S format is selected
1 : other format is selected
CO4
Polarity of LRCKO :
0 : low->right, high->left).
1 : low->left, high->right so compliant to I2S
format ).
CO5
0 : data are in the last BCKO cycles of
LRCKO (right aligned data).
1 : data are in the first BCKO cycles of
LRCKO (left aligned data).
CO6
0 : the transmission is LS bit first.
1 : the transmission is MS bit first.
PCM_DIV :
b6
r
P
e
Comment
s
b
O
CO2
Software Reset : 0
0
b4
CO[1:0] 0 : 16
1 : 18
2 : 20
3 : 24
Type : RW - DEC
b7
b5
Bit
fields
Address : 0x66 (102)
6.4.2
b6
Table 12. .
OUTPUT_CONF :
b6
b7
If OUTPUT_CONF == 1, configure the I2Sout interface according following table
6.4 I2Sout_CONFIGURATION registers
description
6.4.1
PCM_CONF :
6.4.4
PCM_CROSS :
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
CR1
CR0
Address : 0x67 (103)
Type : RW - DEC
Software Reset : 0
Address : 0x69 (105)
Type : RW - DEC
Description :
Software Reset : 0
If OUTPUT_CONF == 1, configure the divider to generate the bit clock of the I2Sout interface, called
BCK0, from PCMCK. according the following relation
: BCKO = PCMCK / 2 * (PCM_DIV+1)
Description :
18/43
If OUTPUT_CONF == 1, CR[1:0] is used to configure
STA016A
the output crossbar according following table
6.5.2
Table 13. .
CR1
CR0
0
0
Comment
Left channel is mapped on the left
output.
Right channel is mapped on the right
output.
GPSO_CONF :
b7
b6
b5
b4
b3
b2
b1
b0
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
Address : 0x6A (106)
Type : RW - DEC
0
1
Left channel is duplicated on both output
channels.
1
0
Right channel is duplicated on both
output channels.
1
1
Right and left channels are toggled.
Software Reset : 0
Description :
)
s
(
ct
If OUTPUT_CONF == 1, this register configure the
GPSO interface
u
d
o
Table 15. .
6.5 GPSO_CONFIGURATION registers
description
Bit
fields
r
P
e
Comment
CF0
6.5.1
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
0C2
OC1
OC0
)-
Type : RW - DEC
s
(
t
c
Software Reset : 0
du
Description
Table 14. :
e
t
e
l
Bit fields
Comment
OC0
Configuration of gpso :
0 : take embedded default configuration.
1 : configure gpso from register
GPSO_CONF.
so
b
O
OC2
o
r
P
t
e
l
o
s
b
O
CF1
Address : 0x66 (102)
OC1
Polarity of GPSO_CK :
0 : data provided on rising edge & stable on
falling edge
1 : data provided on falling edge & stable on
rising edge
OUTPUT_CONF :
Polarity of GPSO_REQ :
0 : data are valid when GPSO_REQ is high
1 : data are valid when GPSO_REQ is low
CF[7:2]
Reserved : to be set to 0.
6.6 I2Sin_CONFIGURATION registers
description
6.6.1
b7
INPUT_CONF :
b6
b5
b4
b3
b2
b1
b0
Address : 0x5A (90)
Type : RW - DEC
Software Reset : 0
Use of block PCM to generate clocks
(PCMCK, LRCK & BCK):
0 : no use.
1 : use it.
Configuration of PCM block:
0 : take embedded default configuration.
1 : configure PCM block from PCM_DIV
& PCM_CONF registers.
Note that embedded default configuration for GPSO
can be retrieved by user thanks to following setting :
– GPSO_CONF = b00000011;
Note that embedded default configuration for PCM
block is described at previous chapter.
Description :
If set to 1 enable the configurability of the I2Sin Input
thanks to following registers, else disable this configurability and take embedded default configuration for
I2Sin registers.
Note that this embedded default configuration can be
retrieved by user thanks to following setting :
– I_AUDIO_CONFIG_1 = b00000110;
– I_AUDIO_CONFIG_2 = b11100000;
– I_AUDIO_CONFIG_3 = b00000001;
19/43
STA016A
6.6.2
6.6.3
I_AUDIO_CONFIG_1:
I_AUDIO_CONFIG_2 :
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
LR7
LR6
LR5
LR4
LR3
LR2
LR1
LR0
Address : 0x5B (91)
Address : 0x5C (92)
Type : RW - DEC
Type : RW - DEC
Software Reset : 0
Software Reset : 0
Description :
Description :
If INPUT_CONF == 1, this register configure the
I2Sin interface
See I_AUDIO_CONFIG_3 register description..
Table 16. .
6.6.4
b7
Bit
fields
CF0
Comment
0
)
s
(
ct
I_AUDIO_CONFIG_3 :
b6
b5
0
0
b4
b3
u
d
o
b2
r
P
e
0
0
0
b1
b0
LR9
LR8
t
e
l
o
Relative synchro :
0 : synchro with first data bit
1 : synchro one bit before first data bit
Address : 0x5D (93)
Type : RW - DEC
s
b
O
Software Reset : 0
CF1
Data reception configuration :
0 : LSB first
1 : MSB first
CF2
Polarity of bit clock BCK :
0 : data provided on falling edge & stable
on rising edge.
1 : data provided on rising edge & stable
on falling edge
)
(s
Description :
CF3
CF4
t
c
u
od
Polarity of LR clock LRCK :
0 : negative
1 : positive
e
t
e
ol
Pr
If INPUT_CONF == 1, this register is used to configure the phase of the LRCK of the I2Sin.
Table 18.
Bit fields
Comment
LR[4:0]
Position of the data within the LRCK
phase :
- if CF1 = 0 (LSB), value must be set to[31
- SL[9:5] - bit position of the first bit of data
within the LRCK phase].
- if CF1 = 1 (MSB), value must be set to bit
position of the first bit of data within the
LRCK phase.
Note that range of value for this bit
position is [0:31].
LR[9:5]
Length-1 of the data.
Max value is 31.
Start value of LRCK : combined with CF3,
this bit enable user to determine left/right
couple according to the following table.
s
b
O
CF[7:5]
Reserved : to be set to 0.
Table 17.
CF3
CF4
0
0
(data1/data2), (data3/data4),...
1
0
(data0/data1), (data2/data3),...
0
1
(data0/data1), (data2/data3),...
1
1
(data1/data2), (data3/data4),...
20/43
Left/Right couples
LR[15:10]
Reserved : to be set to 0
STA016A
6.7 CDBSA_CONFIGURATION registers
description
Software Reset : 0
6.7.1
If INPUT_CONF == 1, this register is used to configurate CD & BS input interfaces in audio mode
b7
Description :
INPUT_CONF :
b6
b5
b4
b3
b2
b1
b0
Table 19.
Address : 0x5A (90)
Bit
Type : RW - DEC
Software Reset : 0
Description :
If set to 1 enable the configurability of the CD & BS
input interfaces in audio mode thanks to following
registers, else disable this configurability and take
embedded default configuration.
Note that this embedded default configuration can be
retrieved by user thanks to following setting :
– I_AUDIO_CONFIG1 = b00010010;
// clocks in input
// & polarity negative
– I_AUDIO_CONFIG2 = b00110010;
// synchro with first data bit
// data unsigned, MSB first
– I_AUDIO_CONFIG3 = b11001111;
// LRCK phase length is 1
– I_AUDIO_CONFIG4 = b00000011;
// LRCK phase length is 16
– I_AUDIO_CONFIG5 = 0xFF;
// received 16 bits
– I_AUDIO_CONFIG6 = 0xFF;
// received 16 bits
– I_AUDIO_CONFIG7 = 0x00;
// received 16 bits
– I_AUDIO_CONFIG8 = 0x00;
// received 16 bits
– I_AUDIO_CONFIG9 = 16;
// data size is 16
– I_AUDIO_CONFIG10 = 0x00;
// no use because clock in input
– I_AUDIO_CONFIG11 = 0x00;
// no use because clock in input
Comment
CF0
Reserved : to be set to 0
CF1
Reserved : to be set to 1
CF2
Direction of bit clocks CD_BCK & BS_BCK:
0 : input
1 : output
CF3
Polarity of bit clocks CD_BCK & BS_BCK :
0 : data provided on falling edge & stable on
rising edge
1 : data provided on rising edge & stable on
falling edge
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
CF4
Reserved : to be set to 1
CF5
Direction of LR clocks CD_LRCK &
BS_LRCK :
0 : input
1 : output
)
(s
s
b
O
CF6
Polarity of LR clocks CD_LRCK &
BS_LRCK :
0 : left sample corresponds to the low level
phase of LRCK
1 : left sample corresponds to the high level
phase of LRCK
CF7
Reserved : to be set to 0
t
c
u
d
o
r
P
e
t
e
l
o
bs
O
6.7.3
b7
I_AUDIO_CONFIG_2 :
b6
b5
b4
b3
b2
b1
CF15 CF14 CF13 CF12 CF11 CF10 CF9
b0
CF8
Address : 0x5C (92)
Type : RW - DEC
6.7.2
Software Reset : 0
_AUDIO_CONFIG_1 :
b7
b6
b5
b4
b3
b2
b1
b0
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
Description :
If INPUT_CONF == 1, this register is used to configurate CD & BS input interfaces in audio mode
Address : 0x5B (91)
Type : RW - DEC
21/43
STA016A
Table 20. .
Table 21.
Bit
Comment
Bit fields
Comment
CF8
Relative synchro :
0 : synchro with first data bit
1 : synchro one bit before first data bit
LR[5:0]
Length-1 of phase 1 of LR clocks
CD_LRCK & BS_LRCK.
Max value is 31.
CF9
Data reception configuration :
0 : LSB first
1 : MSB first
LR[11:6]
Length-1 of phase 2 of LR clocks
CD_LRCK & BS_LRCK.
Max value is 31.
CF10
Arithmetic type of the reception :
0 : unsigned data
1 : signed data
CF11
Bit to select the reference clock used to
generate BCK if clocks are in output
(CF2=1 & CF5=1). Otherwise this bit is
useless.
0 : SYSCK
1 : PCMCK
CF12
Reserved : to be set to 1
CF13
Reserved : to be set to 1
CF14
Reserved : to be set to 0
CF15
Reserved : to be set to 0
LR[15:12]
6.7.6
I_AUDIO_CONFIG_5:
b6
b5
b4
b3
b2
b1
MA7
MA6
MA5
MA4
MA3
MA2
du
Address : 0x5F (95)
Type : RW - DEC
MA1
b0
MA0
o
r
P
s
b
O
See I_AUDIO_CONFIG_8 register description.
)
(s
b7
b6
b5
b4
b3
b2
b1
b0
LR7
LR6
LR5
LR4
LR3
LR2
LR1
LR0
t
c
u
Address : 0x5D (93)
d
o
r
Type : RW - DEC
Software Reset : 0
P
e
6.7.7
I_AUDIO_CONFIG_6 :
b7
b6
b5
b4
b3
b2
b1
b0
MA1
5
MA1
4
MA1
3
MA1
2
MA1
1
MA1
0
MA9
MA8
Address : 0x60 (96)
Type : RW - DEC
Software Reset : 0
t
e
l
o
Description :
e
t
e
ol
Software Reset : 0
I_AUDIO_CONFIG_3 :
)
s
(
ct
b7
Description :
6.7.4
Reserved : to be set to 0
See I_AUDIO_CONFIG_4 register description..
s
b
O
6.7.5
b7
Description :
See I_AUDIO_CONFIG_8 register description..
I_AUDIO_CONFIG_4 :
b6
b5
b4
b3
b2
LR15 LR14 LR13 LR12 LR11 LR10
b1
b0
LR9
LR8
6.7.8
b7
Address : 0x5E (94)
I_AUDIO_CONFIG_7 :
b6
b5
b4
b3
b2
b1
MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16
Type : RW - DEC
Software Reset : 0
Address : 0x61 (97)
Type : RW - DEC
Description :
Software Reset : 0
If INPUT_CONF == 1, this register is used to configurate LR clocks (CD_LRCK & BS_LRCK) of CD & BS
input interfaces in audio mode.
Description :
22/43
b0
See I_AUDIO_CONFIG_8 register description..
STA016A
6.7.9
b7
I_AUDIO_CONFIG_8 :
b6
b5
b4
6.7.12 II_AUDIO_CONFIG_11 :
b3
b2
b1
b0
MA31 MA30 MA29 MA28 MA27 MA26 MA25 MA24
b7
b6
b5
b4
b3
b2
b1
DV15 DV14 DV13 DV12 DV11 DV10 DV9
b0
DV8
Address : 0x62 (98)
Address : 0x65 (101)
Type : RW - DEC
Type : RW - DEC
Software Reset : 0
Software Reset : 0
Description :
Description :
If INPUT_CONF == 1, those registers are used to
configure the MASK to be appllied to CD_LRCK &
BS_LRCK phase 1 & 2.
– if MAi set to 0, then bit i of both phases is not
received.
– if MAi set to 1, then bit i of both phases is received.
If INPUT_CONF == 1, those registers are used to
create BCK if configurated in output (so if CF2=1 &
CF5=1): then value of DV[15:0] is the divider factor to
be applied to the selected clock (CF11 select either
SYSCLK or PCMCLK) to create BCK.
6.7.10
b6
b5
b4
b3
b2
b1
b0
DL7
DL6
DL5
DL4
DL3
DL2
DL1
DL0
t
e
l
o
s
(
t
c
Software Reset : 0
du
Description :
e
t
e
l
o
s
b
b7
POL_REQ :
b6
b5
b4
b3
b2
b1
b0
Address : 0x59 (89)
Type : WO - DEC
o
r
P
If INPUT_CONF == 1, this register is used to configurate the size of the data to be received by CD & BS
input interfaces in audio mode. Max is 32.
Software Reset : 0
Description :
This register manage the polarity of the data REQ
signal DREQ of the BS input interface.
I_AUDIO_CONFIG_10 :
O
s
b
O
6.8 BSB_CONFIGURATION registers
description
)-
Type : RW - DEC
DV7
r
P
e
6.8.1
Address : 0x63 (99)
b7
u
d
o
Note : value 0 & 1 correspond to a bypass of the dividers.
I_AUDIO_CONFIG_9 :
b7
6.7.11
)
s
(
ct
If set to 0, data are requested when REQ = 0.
b6
b5
b4
b3
b2
b1
b0
DV6
DV5
DV4
DV3
DV2
DV1
DV0
If set to 1, data are requested when REQ = 1.
6.8.2
INPUT_CONF :
Address : 0x64 (100)
Type : RW - DEC
b7
b6
b5
b4
b3
b2
b1
b0
Software Reset : 0
Address : 0x5A (90)
Description :
Type : RW - DEC
See I_AUDIO_CONFIG_11 register description.
Software Reset : 0
Description :
23/43
STA016A
If set to 1 enable the configurability of the BSB input
interfaces in burst mode thanks to following register,
else disable this configurability and take embedded
default configuration.
Table 23. .
Value
Note that this embedded default configuration can be
retrieved by user thanks to following setting :
– I_AUDIO_CONFIG1 = b00000000;// polarity
choice
6.8.3
I_AUDIO_CONFIG_1 :
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
CF0
Address : 0x5B (91)
Type : RW - DEC
Software Reset : 0
stop playing music
2
pause
3
fast forward
4
fast rewind
5
track up
6
track down
9
directory down
10
directory up
11
play specified track
12
set a play-list index
13
edit play list
play cd from beginning
112
start playing music
113
start searching bytes/mute navigation
Bit
Comment
u
d
o
Polarity of bit clock BS_BCK :
0 : data provided on falling edge & stable
on rising edge.
1 : data provided on rising edge & stable
on falling edge.
r
P
e
t
e
l
o
b7
name of file required
128
name of directory required
FAST_FUNCTIONAL_VAL :
b6
b5
b4
b3
b2
b1
b0
Address : 0x41 (65)
Type : RW - ABO
This register specifies the volume of fast function.
For the “fast forward function” it is a number between
1 and 20.
For the “fast rewind function” it is a number of second
BASIC_COMMAND :
b4
6.9.1
ID3 name of album required
127
Description :
6.9 CD_CONFIGURATION registers
description
b5
t
e
l
o
ID3 name of song required
ID3 name of author required
Software Reset : 0
s
b
O
b6
)-
s
(
t
c
Table 22. .
b7
r
P
e
s
b
O
126
If INPUT_CONF == 1, this register is used to configure BSB bit clock
u
d
o
play current dir
15
124
Description :
)
s
(
ct
14
125
CF0
Command
1
b3
b2
b1
b0
6.9.2
REQUIRED_TRACK :
Address : 0x40 (64)
Type : RW - AEC
Software Reset : 0
b7
b6
b5
Address : 0x42 (66)
Type : RW - ABO
Description :
Software Reset : 0
Used for giving to dsp basic cd-player commands
Description :
24/43
b4
b3
b2
b1
b0
STA016A
6.9.5
This specifies the number of track to play.
b7
6.9.3
TYPE_CD_EXT_REQ:
b6
b5
b4
b3
b2
b1
b0
REQUIRED_DIR :
Address : 0x46 (70)
b7
b6
b5
b4
b3
b2
b1
b0
Type : RO - AEC
Software Reset : 0
Address : 0x43 (67)
Type : RW - ABO
Software Reset : 0
Description :
Description :
This register specifies the type of request sent to the
cd module
This register specifies the number of directory to
play.
)
s
(
ct
Table 25. .
u
d
o
Value
Signification
10
application is in pause after EOT or EOD
18
request for a sector
20
begin of track reached
Type : RW - ABO
30
ready to receive a new command
Software Reset : 0
35
dsp ready to run
40
cd application stopped.
66
time spent on track available
112
request for root
120
song information available
6.9.4
b7
PLAY_MODE :
b6
b5
b4
b3
b2
b1
b0
Address : 0x44 (68)
Description :
This register specifies the playing mode
s
(
t
c
Table 24. .
u
d
o
Bit
Mode
r
P
e
[1:0]
s
b
O
t
e
l
o
[3:2]
end of directory:
0: play next directory
1: replay same directory
2: make pause.
other: reserved
end of track:
0: play next track.
1: replay same track.
2: make pause.
other: reserved
4
next track choice:
0: linear mode.
1: random mode.
5
playing time for track:
0: until end of track.
1: scanning mode.
6
end of CD:
0: stop.
1: replay same CD..
)-
r
P
e
t
e
l
o
s
b
O
6.9.6
b7
MINUTE_REQ :
b6
b5
b4
b3
b2
b1
b0
Address : 0x47 (71)
Type : RO - AEC
Software Reset : 0
Description :
This register specifies to the CD module the minute
location requested.
6.9.7
b7
SECOND_REQ :
b6
b5
b4
b3
b2
b1
b0
Address : 0x48 (72)
Type : RO - AEC
Software Reset : 0
25/43
STA016A
Description :
Type : RW - ABO
This register specifies to the CD module the second
location requested.
Software Reset : 0
Description :
6.9.8
b7
SECTOR_REQ :
b6
b5
b4
This register specifies in second (2, decoder skip (n-1) out of n frames. Note that maximum
value for n is 8, and if n==0 or n==1, no frames is
skipped.
6.10.8 PAUSE :
b7
b6
b5
Address : 0x58 (88)
6.10.5 CRC_IGNORE :
b5
b2
Type : RW - ABO
bs
b6
b3
Address : 0x57 (87)
Description :
– When a software reset occurs, register RUN
is reset (value 0) by the dsp (see I).
– When boot routines are finished, the dsp
write inside RUN register the value 2 : this is
the start of the external configuration period
(start of DEC : see I).
– When the external device wants to end the
external configuration period, it must write the
value 1 inside the register RUN: this is the run
command that starts the decoding process
(see I).
b7
b4
For decoders having MUTE abilities (see each decoder configuration), if set to 0 disable the mute of the
decoder, if set to 1 enable the mute of the decoder.
Note that during a MUTE the input stream keeps on
entering.
ct
b1
u
d
o
Address : 0x56 (86)
Type : RW - DEC
b5
Description :
6.10.4 RUN :
b7
b6
b1
b0
Type : RW - ABO
Software Reset : 0
b4
b3
b2
b1
b0
STA016A
Description :
6.11.2 STATUS_CHANS_NB :
For decoders having PAUSE abilities (see each decoder configuration), if set to 0 disable the pause of
the decoder, if set to 1 enable the pause of the decoder. Note that during a PAUSE the input stream is
stopped.
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xCD (205)
Type : RO - EDF
Software Reset : 0
6.11 STATUS registers description
Description :
6.11.1 STATUS_MODE :
b7
b6
b5
b4
This register gives the number of channel currently
decoded.
b3
b2
b1
6.11.3 STATUS_SF :
Address : 0xCC (204)
Type : RO - EDF
b7
Software Reset : 0
b6
b5
Description :
Address : 0xCE (206)
This register give the type of the currently decoded
bitstream according following table
Type : RO - EDF
Mode
0
MP3
1
MP3_25
2
RESERVED
3
RESERVED
4
RESERVED
t
e
l
o
6
7
s
b
O
8
u
d
o
b2
r
P
e
b1
b0
t
e
l
o
This register gives the index of the sampling frequency of the stream currently decoded. Note that sampling frequency indexes are given by table 5
)
(s
t
c
u
d
o
r
P
e
b3
s
b
O
Description :
Value
b4
Software Reset : 0
Table 31. .
5
)
s
(
ct
b0
6.11.4 STATUS_FE :
b7
b6
b5
RESERVED
Address : 0x6F (111)
RESERVED
Type : RO - AEC
BYPASS
Software Reset : 0
b4
b3
b2
b1
b0
RESERVED
9
RESERVED
Description :
10
RESERVED
This register give the status of the synchronization
process according following table.
11
MPG2
12
RESERVED
13
RESERVED
14
RESERVED
15
RESERVED
16
RESERVED
17
RESERVED
18
UNKNOWN
Table 32.
Value
Level
0
Syncrho not started
1
Syncword found
2
Syncword search
3
Syncword hard to find
31/43
STA016A
6.11.5 HEADER _n:
b7
b6
b5
b4
6.12.2 ERR_DEC_NB_1 :
b3
b2
b1
b0
Address : 0xD4 (212) to 0xD9 (217)
b7
b6
b5
b4
b3
b2
b1
b0
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Type : RO - EDF
Address : 0x6C (108)
Software Reset : 0
Type : RO - EDF
Software Reset : 0
Description :
Description :
This register give the nth byte of the header of the
frame currently decoded
See ERR_DEC_NB_2 register description.
b7
b6
b5
b4
)
s
(
ct
6.12.3 ERR_DEC_NB_2 :
6.11.6 PCMCLK_INPUT :
b3
b2
b1
b7
b0
b6
b5
b4
b3
du
b2
b1
ro
ER15 ER14 ER13 ER12 ER11 ER10 ER9
P
e
Address : 0xCB (203)
Type : RW - DEC
Address : 0x6D (109)
Software Reset : 0
Type : RO - EDF
b0
ER8
t
e
l
o
Software Reset : 0
Description :
If set to 1, the PCMCLK pad is configure as input in
order to receive an external reference clock.
6.12 MP3_CONFIGURATION registers
description
6.12.1 ERR_DEC_LEVEL :
d
o
r
P
e
)
(s
t
c
u
s
b
O
Description :
This register give the status of the mp3 decoding process according the error number written in following
table
Table 34.
Event
Comment
ER0 == 1
crc_error
ER1 == 1
cutoff_error
ER2 == 1
big_value_error
ER3 == 1
hufftable_error
ER4 == 1
mod_buf_size_error
ER5 == 1
huffman_decode_error
Description :
ER6 == 1
dynpart_exchange_error
This register give the status of the mp3 decoding process according the error level written in following table.
ER7 == 1
gr_length_error
ER8 == 1
input_bit_available_error
ER9 == 1
ch_length_error
ER10 == 1
head_framelength_error
ER11 == 1
dynpart_length_error
ER12 == 1
block_type_error
b7
b6
b5
b4
t
e
l
o
Address : 0x6B (107)
b3
b2
b1
b0
s
b
O
Type : RO - EDF
Software Reset : 0
Table 33.
Value
32/43
Level
0
No error
1
Warning while decoding
ER13 == 1
head_emphasis_error
2
Error while decoding
ER14 == 1
head_samp_freq_error
3
Fatal error while decoding
ER15 == 1
head_layer_error
STA016A
6.13 MIX_CONFIGURATION registers
description
6.13.4 MIX_DRA:
b7
b6
b5
b4
b3
b2
b1
b0
6.13.1 MIX_MODE:
b7
b6
b5
b4
b3
b2
b1
Address : 0x78 (120)
b0
Type : RW - ABO
Software Reset : 0
Address : 0x75 (117)
Type : RW - ABO
Description :
Software Reset : 2
This register specifies the direct right attenuation (in
dB).
Description :
)
s
(
ct
This register selectes the mode of mix/volume control
6.13.5 MIX_DRB:
Table 35. :
Value
b7
Mode
b6
0
diseable mix/volume control
Address : 0x79(121)
1
volume control
Type : RW - ABO
2
mono to stereo (up-mix)
Software Reset : 0
3
stereo to mono (down-mix)
b5
b4
b3
b2
Address : 0x76 (118)
)
(s
t
c
u
b1
b0
d
o
r
Type : RW - ABO
Software Reset : 0
u
d
o
b2
b1
b0
r
P
e
t
e
l
o
6.14 TONE_CONFIGURATION registers
description
6.14.1 TONE_ON:
P
e
b7
t
e
l
o
Description :
b3
This register specifies the rigth attenuation (in dB) on
left channel.
6.13.2 MIX_DLA:
b6
b4
s
b
O
Description :
b7
b5
This register specifies the direct left attenuation (in
dB).
bs
b6
b5
b4
b3
b2
b1
b0
Address : 0x7A(122)
Type : RW - ABO
Software Reset : 0
O
6.13.3 MIX_DLB:
b7
b6
Description :
b5
b4
b3
b2
b1
b0
This register enables/diseables (1/0) the tone control.
Address : 0x77 (119)
Type : RW - ABO
Software Reset : 0
6.14.2 TONE_FCUTH :
b7
b6
b5
Description :
Address : 0x7B(123)
This register specifies the left attenuation (in dB) on
rigth channel.
Type : RW - ABO
b4
b3
b2
b1
b0
Software Reset : 20
33/43
STA016A
Description :
gain(in Db)=(TONE_GAINH-12)*1.5
This register specifies the high cut frequency: fcut(in
Hz)=(TONE_FCUTH+1)*50.
6.14.5 TONE_GAINL :
b7
6.14.3 TONE_FCUTL :
b7
b6
b5
b4
b3
b2
b1
b6
b5
b4
b3
b2
b1
b0
Address : 0x7E(126)
b0
Type : RW - ABO
Address : 0x7C(124)
Software Reset : 12
Type : RW - ABO
Software Reset : 10
Description :
Description :
This register specifies the gain on high frequencies:
gain (in Db)=(TONE_GAINL-12)*1.5. Value of register from 0 to 24.
This register specifies the low cut frequency: fcut(in
Hz) = (TONE_FCUTL+1)*10
)
s
(
ct
r
P
e
6.14.6 TONE_GAIN_ATTEN :
6.14.4 TONE_GAINH :
b7
b6
b5
b4
b7
b3
b2
b1
b6
b0
let
b5
b4
o
s
b
u
d
o
b3
b2
b1
b0
Address : 0x7F(127)
Address : 0x7D(125)
Type : RW - ABO
O
)
Type : RW - ABO
Software Reset : 0
Software Reset : 12
t(s
Description :
c
u
d
This register specifies the gain on high frequencies:
6.15 TABLES
e
t
e
ol
o
r
P
Description :
This register specifies the attenuation on global spectrum: gain (in dB)=-TONE_GAIN_ATTEN*1.5. Value
of register from 0 to 12.
Table 36. values to configure audio PLL for ofact==256.
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 256*SF.
bs
Register
CRYCK in MHz
10
CRYCK in MHz
14.31818
CRYCK in MHz
14.7456
PLL_AUDIO_PEL_192
42
58
85
PLL_AUDIO_PEH_192
169
187
85
PLL_AUDIO_NDIV_192
0
0
0
PLL_AUDIO_XDIV_192
3
3
0
PLL_AUDIO_MDIV_192
18
12
2
PLL_AUDIO_PEL_176
56
54
0
PLL_AUDIO_PEH_176
16
118
64
PLL_AUDIO_NDIV_176
0
0
0
PLL_AUDIO_XDIV_176
3
2
3
PLL_AUDIO_MDIV_176
17
8
11
O
34/43
STA016A
Table 37. values to configure audio PLL for ofact==384
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 384*SF.
Register
CRYCK in MHz
10
CRYCK in MHz
14.31818
CRYCK in MHz
14.7456
PLL_AUDIO_PEL_192
224
108
0
PLL_AUDIO_PEH_192
190
76
0
PLL_AUDIO_NDIV_192
0
0
0
PLL_AUDIO_XDIV_192
1
1
1
PLL_AUDIO_MDIV_192
13
9
9
PLL_AUDIO_PEL_176
42
54
0
PLL_AUDIO_PEH_176
140
118
PLL_AUDIO_NDIV_176
0
0
PLL_AUDIO_XDIV_176
1
1
u
d
o
PLL_AUDIO_MDIV_176
12
8
48
let
o
s
b
Table 38. values to configure audio PLL for ofact==512.
r
P
e
)
s
(
ct
0
1
8
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 512*SF.
O
)
Register
CRYCK in MHz
10
CRYCK in MHz
14.31818
CRYCK in MHz
14.7456
PLL_AUDIO_PEL_192
42
58
85
169
187
85
0
0
0
1
0
1
18
5
12
56
157
0
PLL_AUDIO_PEH_176
16
157
64
PLL_AUDIO_NDIV_176
0
0
0
PLL_AUDIO_XDIV_176
1
1
1
PLL_AUDIO_MDIV_176
17
11
11
s
(
t
c
du
PLL_AUDIO_PEH_192
PLL_AUDIO_NDIV_192
PLL_AUDIO_XDIV_192
e
t
e
l
PLL_AUDIO_MDIV_192
so
PLL_AUDIO_PEL_176
b
O
o
r
P
35/43
STA016A
Table 39. values to configure system PLL for SYSCK.
This table give values to configure the system PLL according CRYCK so that to generate a SYSCK == 50MHz.
or SYSCK == 42.5MHz.
CRYCK in MHz 10
CRYCK in MHz
14.31818
CRYCK in MHz
14.7456
PLL_SYSTEM_PEL_50
162
0
28
PLL_SYSTEM_PEH_50
11
0
152
PLL_SYSTEM_NDIV_50
0
0
0
PLL_SYSTEM_XDIV_50
1
1
1
PLL_SYSTEM_MDIV_50
19
13
12
PLL_SYSTEM_PEL_42_5
0
126
100
PLL_SYSTEM_PEH_42_5
0
223
PLL_SYSTEM_NDIV_42_5
0
0
PLL_SYSTEM_XDIV_42_5
1
1
PLL_SYSTEM_MDIV_42_5
16
10
Register
Table 40. index of the Sampling Frequency.
)-
Index
t(s
0
c
u
d
1
2
4
5
e
t
e
l
6
36/43
135
ete
Pr
s
b
O
ol
Frequency
48 kHz
44.1 kHz
32 kHz
96 kHz
88.2 kHz
64 kHz
8
24 kHz
9
22.05 kHz
10
16 kHz
12
12 kHz
13
11.025 kHz
14
8 kHz
16
192 kHz
17
176.4 kHz
18
128 kHz
3, 7, 11, 15 or 19
illegal frequency
o
s
b
O
o
r
P
u
d
o
)
s
(
ct
0
1
10
STA016A
6.16 NOTATIONS
ABO
: After BOot (see I).
AEC
: After External Config (see I).
BCK
: Bit ClocK
BSA
: BitStream input interface in Audio mode.
BSB
: BitStream input interface in Burst mode.
BS
: BitStream input interface.
BYPASSA
: decoder BYPASS an Audio stream.
CD
: input interface for CD.
CK
: ClocK.
CRYCK
: CRYstal ClocK provided to the chip by an external crystal.
DBO
: During BOot (see I).
DEC
: During External Config (see I).
DWT
: During Whole Time (see I).
EDB
: Every Decoded Block (see I).
EDF
: Every Decoded Frame (see I).
LRCK
: Left Right ClocK for an I2S interface.
ofact
: oversampling factor for PCMCK (PCMCK == ofact * SF).
PCMCK
: PCM ClocK (can be generated by the audio PLL).
SF
: Sampling Frequency.
SYSCK
: SYStem ClocK (clock of the core, can be generated by the system PLL).
X
: don’t care.
7
)
s
(
ct
u
d
o
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P
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o
)
(s
s
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I/O CELL DESCRIPTION
P
e
t
e
l
o
s
b
O
7.1 TTL Tristate Output Pad Buffer, 3V capable 4mA, with Slew Rate Control
Pin numbers: 4, 18, 20, 21, 22, 25, 54, 56, 59
EN
Z
INPUT PIN
MAX LOAD
Z
100pF
A
D98AU904
7.2 TTL Schmitt Trigger Bidir Pad Buffer, 3V capable, 4mA, with Slew Rate Control
Pin numbers: 1, 2, 3, 7, 8, 9, 19
EN
IO
INPUT PIN
CAPACITANCE
OUTPUT
PIN
MAX
LOAD
IO
TBD
IO
100pF
A
ZI
D98AU905
37/43
STA016A
7.3 TTL Schmitt Trigger Inpud Pad Buffer, 3V capable / Pin numbers:17, 60, 63
A
Z
INPUT PIN
CAPACITANCE
A
TBD
D98AU906
7.4 TTL Inpud Pad Buffer, 3V capable with Pull-Up / Pin numbers:15, 16
Z
A
INPUT PIN
CAPACITANCE
A
TBD
)
s
(
ct
D98AU907
u
d
o
7.5 TTL Schmitt Trigger Bidir Pad Buffer, with Pull-up, 4mA, with slew rate control / 3V capable
r
P
e
Pin numbers: 26, 27, 28, 31, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 51, 64
t
e
l
o
EN
IO
INPUT PIN
A
ZI
CAPACITANCE
s
b
O
IO
D00AU1150
)
(s
OUTPUT
PIN
MAX
LOAD
IO
100pF
TBD
7.6 TTL Input Pad Buffer, 3V capable, with pull down / Pin numbers: 12, 13, 14, 55
A
Z
t
c
u
od
Pr
INPUT PIN
CAPACITANCE
A
TBD
D00AU1222
8
e
t
e
ol
COMMAND PROTOCOL CONFIGURATION
s
b
O
General Information About The Command Protocol
I2C protocol :
CD_module & mmdsp are using an I2C protocol to communicate : CD_module is master of the I2C protocol,
and can access (in read and write mode) host registers of the STA016A to write commands to the mmdsp and
to read request from the mmdsp. It must use following I2C syntax :
device_address, host_register_number, host_register_value
where :
for a write acces, device_address is 0x86.
for a read acces, device_address is 0x87.
Writing a command to mmdsp :
CD_module write its command inside dedicated host registers (mainly H64 to H69), then it must signals the writing of this command to mmdsp by sending the interrupt IT_CMD to the core of mmdsp.
Note that IT_CMD is generated by cd_module threw a falling edge on the input line number 0 of the STA016A
38/43
STA016A
(the INTLINE[0] pin).
8.0.1
Reading a request from mmdsp :
MMDSP write its request inside dedicated host registers (mainly H70 to H78 and H134 to H169), then it signals
to cd_module that it must read a request by sending the interrupt IT_REQ.
Note that IT_REQ interrupt is generated by mmdsp on the IRQB pin of STA016A.
Note also that once it has finished to read the message, cd_module must always acknowledge it by reading
H10.
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
)
00 0 0 0 0 00000000000000000power
00 0000000000000on00000000000000000 0 0 0 0 0 00
s
(
t
00 00 00 00cd00 0 00 00 00 ?00 00 00 00 00 00 00 00 0 0 0 0 0 0
0 00 00 00 00 00 00 00 inserted
c
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0 0 0 0 0 0 0 0 0no0 0 0 0 0 0 0 0 0 0 du
00 0 write 1 in SOFT_RESET 0 ro
00 00 0 0 0 0 0 0 0write
0 0 0 0 0 000 0in0 0 0CK_CMD
0 0 0 0 0 0 0 0 t0 0e
00000P
0 0 00
0 0 0 0 0 IT_REQ
0 0 0 0 0 0l0 e
0 0 0 0 0 0 0 0 0 0 0 0 00
00 00 0 0 0 0 0 0 0 0 0 0 wait
00 00 00 00s003500 00 o
00 in00 00 00H70
00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 000 00 00 00 00 00 00 00 00 00 00with
b
0
O
start
cd-rom application:
00 0 0 0-write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 in H85, then 1 in H86
0
0
0
0
0
0
0
0
0
000000000000000000000000000000000000000000000000000000
)
s
0
0
0
0
0
0
0
0
0
0
(
wait IT_REQ
t
0 0 with
00
c
112
in0 0 H70
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
u 0 000000000000000000000000000000000000
d
00 0 send play_music command : 0
o
r
00 write 112 in H64 00
P
0
00 0 0t0 0e
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0 0000000000000000000send
00 000000000IT_CMD
0000000000000000000 0 0 0 00 0000000 0 0 00
e
l0
0 0 0 cd0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 00 00 00 00 00 00 00 00 ejected?
o
0
s
yes
b
00 00 00 00 00 00 00 00 000000000000000000000000000000000000000000000000 00 00
00
O
000run
00 000000other
00000000000000000000000 00 00
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 0 0 0yes0 0 00000000000000application?
00 0 0 0 0 0 0 0 0 0 0 00 00
pause command : 0
00 00 sendwrite
0
0
0
0
0
0
0
0
0
0
0
0
0
2 in H64
00 00 00 00any00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 0 0 00 00
00 00 00 00 00 00 00 00send
00 00 00 00 00 IT_CMD
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000 0 000 000 000 000 000 000 000command?
no
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00 0 0 0 0 0 0 0 0run0 0 0 0the0 0 0 0other
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00 00
other command :
00 00 00 00 00 00 00 00 00 00application
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 00 000 000 0 0 0 0 0send
write in H64
0 0 0 0 0 0IT_CMD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0return
0 0 0 0 0 0 0 0 0 0 0 00 00 00 00send
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
to
cd?
yes
no
Figure 7. Block diagram for running the CD application.
Hxx: host register
number xx
39/43
STA016A
Figure 8. Block diagram for answer to a sector request from dsp.
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000000000000000000on00000000000000000000 0 0 0 0 0 0
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 0 0 00 00 00000000000000000000000power
00
0 0 0 00 00 00 00 00 00 00 00 00 00 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000
0 0 0 0 0 0 0 0IT_REQ
0 0 0 0 0 0 0 0 0 0 0 occured
0000000000000 0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 00 H70==18
00 00 00 00 00 00 00 00 00 00 000 000 000 000 000 000 000 000 000 000
)
00
00
0
0
s
(
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0
t
00 please check 0 0read
0 0 0 0 0 0 minute
0 0 0 0 000 0 0 0 0in0 0 0H71
0 0 0 0 0 0 00
c
u
with rest of
00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 od
00 documentation
00
00 00read
00 00 00 00 00 00 second
00 00 00 00 00 00 00 00 00 00in00 00 00H72
00 00 00 00 00 00 00 P00r
e0 0 0 0 0
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
read
frame
in
H73
e
00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0o0 0 0 l0 0 0 0 0 0 0 0 0 00
s0 0 0
00 0 0 0 0 0acknowledge
0
0
acknowledge
b
IT_REQ
0 0 0 0 0 0IT_REQ
0 0 0 0 000 0 0 0 0 0 0 0 0 0 0 0 0 00
0 0 0 0 00 0 0 0 0 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0O
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s) 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00
move the pick-up
(
t
0
00 00
according
to
m,s,f
c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000000000000000000000
du
Hxx: host register
number xx
e
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e
ol
s
b
O
40/43
o
r
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STA016A
Figure 9. TQFP64 Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN.
TYP.
MAX.
A
MIN.
TYP.
1.60
0.063
A1
0.05
A2
1.35
B
0.17
C
0.09
D
11.80
12.00
12.20
0.464
0.472
0.480
D1
9.80
10.00
10.20
0.386
0.394
0.401
0.15
0.002
0.006
1.40
1.45
0.053
0.22
0.27
0.0066 0.0086 0.0086
0.055
0.057
0.0035
D3
7.50
0.295
e
0.50
0.0197
E
11.80
12.00
12.20
0.464
0.472
0.480
E1
9.80
10.00
10.20
0.386
0.394
0.401
E3
7.50
L
OUTLINE AND
MECHANICAL DATA
MAX.
0.45
0.75
r
P
e
t
e
l
o
0.0177 0.0236 0.0295
1.00
K
u
d
o
0.295
0.60
L1
)
s
(
ct
0.0393
0˚ (min.), 3.5˚ (min.), 7˚(max.)
ccc
0.080
)
(s
0.0031
s
b
O
TQFP64 (10 x 10 x 1.4mm)
t
c
u
D
d
o
r
D1
A
D3
P
e
let
48
49
A1
33
32
0.08mm ccc
B
Seating Plane
E
E1
E3
B
17
64
1
16
C
e
L
L1
O
o
s
b
A2
K
TQFP64
0051434 E
41/43
STA016A
Table 41. Revision History
Date
Revision
July 2004
1
Description of Changes
First Issue
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STA016A
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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