STA308A

STA308A Multi-channel digital audio processor with DDX™ Features ! 8 channels of 24-bit DDX® ! >100 dB SNR and dynamic range ! Selectable 32 kHz - 192 kHz input sample rates ! Advanced PopFree operation ! 6 channels of DSD/SACD input ! ! Digital gain/attenuation +58 dB to -100 dB in 0.5 dB steps Advanced AM interference frequency switching and noise suppression modes ! I2S output channel mapping function ! Soft volume update ! Independent channel volume and DSP bypass ! Individual channel and master gain/attenuation plus channel trim (-10 dB to +10 dB) ! Channel mapping of any input to any processing/DDX® channel ! Up to 10 independent 32-bit user programmable biquads (EQ) per channel ! DC blocking selectable high-pass filter ! Bass/treble tone control ! Pre and post EQ full 8-channel input mix on all 8 channels ! Dual independent limiters/compressors ! Dynamic range compression or anti-clipping modes ! AutoModes: – 5-band graphic EQ – 32 preset EQ curves (rock, jazz, pop, etc.) – Automatic volume controlled loudness – 5.1 to 2-channel downmix – Simultaneous 5.1- and 2-channel downmix outputs – 3 preset volume curves – 2 preset anti-clipping modes – Preset movie nighttime listening mode – Preset TV channel/commercial AGC mode – 5.1, 2.1 bass management configurations – AM frequency automatic output PWM frequency shifting – 8 preset crossover filters Description ! Individual channel and master soft/hard mute Table 1. ! Automatic zero-detect and invalid input mute ! Automatic invalid input detect mute TQFP64 )- s ( t c u d o e t e ol Pr s b O July 2007 ) s ( ct u d o r P e t e l o s b O ! Selectable per-channel DDX® damped ternary or binary PWM output ! Max power correction for lower full-power THD ! Variable per channel DDX® output delay control ! 192 kHz internal processing sample rate, 24-bit to 36-bit precision The STA308A is a single chip solution for digital audio processing and control in multi-channel applications. It provides output capabilities for DDX® (direct digital amplification). In conjunction with a DDX® power device, it provides highquality, high-efficiency, all digital amplification. The device is extremely versatile, allowing for input of most digital formats including 6.1/7.1channel and 192 kHz, 24-bit DVD-audio, DSD/SACD. In 5.1 application the additional 2 channels can be used for audio line-out or headphone drive. In speaker mode, with 8 channel outputs in parallel, the STA308A can deliver 1 W (maximum). Device summary Order code STA308A Rev 4 Package TQFP64 1/63 www.st.com 63 Contents STA308A Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ) s ( ct u d o r P e 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 I2C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 O 7 2/63 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 s b O 5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ) (s t c u 5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 d o r P e let o s b 6 t e l o 5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Application reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2.1 Configuration register A (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2.2 Configuration register B (0x01) - serial input formats . . . . . . . . . . . . . . 23 7.2.3 Configuration register C (0x02) - serial output formats . . . . . . . . . . . . . 25 7.2.4 Configuration register D (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2.5 Configuration register E (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2.6 Configuration register F (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STA308A Contents 7.2.7 Configuration register G (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2.8 Configuration register H (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2.9 Configuration register I (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.2.10 Master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2.11 Master volume register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2.12 Channel 1 volume (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2.13 Channel 2 volume (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2.14 Channel 3 volume (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2.15 Channel 4 volume (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2.16 Channel 5 volume (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2.17 Channel 6 volume (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2.18 Channel 7 volume (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2.19 Channel 8 volume (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2.20 Channel 1 volume trim, mute, bypass (0x13) . . . . . . . . . . . . . . . . . . . . 33 7.2.21 Channel 2 volume trim, mute, bypass (0x14) . . . . . . . . . . . . . . . . . . . . 33 7.2.22 Channel 3 volume trim, mute, bypass (0x15) . . . . . . . . . . . . . . . . . . . . 33 7.2.23 Channel 4 volume trim, mute, bypass (0x16) . . . . . . . . . . . . . . . . . . . . 34 7.2.24 Channel 5 volume trim, mute, bypass (0x17) . . . . . . . . . . . . . . . . . . . . 34 7.2.25 Channel 6 volume trim, mute, bypass (0x18) . . . . . . . . . . . . . . . . . . . . 34 7.2.26 Channel 7 volume trim, mute, bypass (0x19) . . . . . . . . . . . . . . . . . . . . 34 7.2.27 Channel 8 volume trim, mute, bypass (0x1A) . . . . . . . . . . . . . . . . . . . . 34 7.2.28 Channel input mapping channels 1 and 2 (0x1B) . . . . . . . . . . . . . . . . . 36 7.2.29 Channel input mapping channels 3 and 4 (0x1C) . . . . . . . . . . . . . . . . . 36 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o O bs 7.2.30 Channel input mapping channels 5 and 6 (0x1D) . . . . . . . . . . . . . . . . . 36 7.2.31 Channel input mapping channels 7 and 8 (0x1E) . . . . . . . . . . . . . . . . . 36 7.2.32 AUTO1 - AutoModes EQ, volume, GC (0x1F) . . . . . . . . . . . . . . . . . . . . 37 7.2.33 AUTO2 - AutoModes bass management2 (0x20) . . . . . . . . . . . . . . . . . 38 7.2.34 AUTO3 - AutoMode AM/pre-Scale/bass management scale (0x21) . . . 39 7.2.35 PREEQ - Preset EQ settings (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2.36 AGEQ - graphic EQ 80-Hz band (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2.37 BGEQ - graphic EQ 300-Hz band (0x24) . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2.38 CGEQ - graphic EQ 1-kHz band (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2.39 DGEQ - graphic EQ 3-kHz band (0x26) . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2.40 EGEQ - graphic EQ 8-kHz band (0x27) . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2.41 Biquad internal channel loop-through (0x28) . . . . . . . . . . . . . . . . . . . . . 42 7.2.42 Mix internal channel loop-through (0x29) . . . . . . . . . . . . . . . . . . . . . . . 43 7.2.43 EQ bypass (0x2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3/63 Contents STA308A 7.2.44 Tone control bypass (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2.45 Tone control (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2.46 Channel limiter select channels 1,2,3,4 (0x2D) . . . . . . . . . . . . . . . . . . . 44 7.2.47 Channel limiter select channels 5,6,7,8 (0x2E) . . . . . . . . . . . . . . . . . . . 44 7.2.48 Limiter 1 attack/release rate (0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2.49 Limiter 1 attack/release threshold (0x30) . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2.50 Limiter 2 attack/release rate (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2.51 Limiter 2 attack/release threshold (0x32) . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2.52 Bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2.53 Channel 1 and 2 output timing (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.2.54 Channel 3 and 4 output timing (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.2.55 Channel 5 and 6 output timing (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.2.56 Channel 7 and 8 output timing (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.2.57 Channel I2S output mapping channels 1 and 2 (0x37) . . . . . . . . . . . . . 50 ) s ( ct u d o r P e 2 7.2.58 Channel I S output mapping channels 3 and 4 (0x38) . . . . . . . . . . . . . 50 7.2.59 Channel I2S output mapping channels 5 and 6 (0x39) . . . . . . . . . . . . . 50 I2S t e l o s b O 7.2.60 Channel 7.2.61 Coefficient address register 1 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2.62 Coefficient address register 2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2.63 Coefficient b1 data register, bits 23:16 (0x3D) . . . . . . . . . . . . . . . . . . . . 51 7.2.64 Coefficient b1 data register, bits 15:8 (0x3E) . . . . . . . . . . . . . . . . . . . . . 52 7.2.65 Coefficient b1 data register, bits 7:0 (0x3F) . . . . . . . . . . . . . . . . . . . . . . 52 7.2.66 Coefficient b2 data register, bits 23:16 (0x40) . . . . . . . . . . . . . . . . . . . . 52 output mapping channels 7 and 8 (0x3A) . . . . . . . . . . . . . 51 ) (s t c u d o r P e t e l o bs O 4/63 7.2.67 Coefficient b2 data register, bits 15:8 (0x41) . . . . . . . . . . . . . . . . . . . . . 52 7.2.68 Coefficient b2 data register, bits 7:0 (0x42) . . . . . . . . . . . . . . . . . . . . . . 52 7.2.69 Coefficient a1 data register, bits 23:16 (0x43) . . . . . . . . . . . . . . . . . . . . 52 7.2.70 Coefficient a1 data register, bits 15:8 (0x44) . . . . . . . . . . . . . . . . . . . . . 52 7.2.71 Coefficient a1 data register, bits 7:0 (0x45) . . . . . . . . . . . . . . . . . . . . . . 53 7.2.72 Coefficient a2 data register, bits 23:16 (0x46) . . . . . . . . . . . . . . . . . . . . 53 7.2.73 Coefficient a2 data register, bits 15:8 (0x47) . . . . . . . . . . . . . . . . . . . . . 53 7.2.74 Coefficient a2 data register, bits 7:0 (0x48) . . . . . . . . . . . . . . . . . . . . . . 53 7.2.75 Coefficient b0 data register, bits 23:16 (0x49) . . . . . . . . . . . . . . . . . . . . 53 7.2.76 Coefficient b0 data register, bits 15:8 (0x4A) . . . . . . . . . . . . . . . . . . . . . 53 7.2.77 Coefficient b0 data register, bits 7:0 (0x4B) . . . . . . . . . . . . . . . . . . . . . . 53 7.2.78 Coefficient write control register (0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.3 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.4 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 54 STA308A 8 Contents 7.5 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.6 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.1 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.2 Variable max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.2.1 8.3 Variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3.1 8.4 MPCC1-2 (0x4D, 0x4E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DCC1-2 (0x4F, 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 ) s ( ct PSCorrect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.4.1 PSC1-2: ripple correction value (RCV) (0x51, 0x52) . . . . . . . . . . . . . . . 59 8.4.2 PSC3: correction normalization value (CNV) (0x53) . . . . . . . . . . . . . . . 59 u d o r P e 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 61 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 t e l o ) (s s b O t c u d o r P e t e l o s b O 5/63 List of tables STA308A List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC electrical characteristics: 3.3-V buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 RAM block for biquads, mixing, and bass management. . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 6/63 s b O STA308A List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Channel signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reference schematic for STA308A-based application . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Channel mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 TQFP64 (10 x 10 x 1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . 58 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 7/63 Block diagram 1 STA308A Block diagram Figure 1. Block diagram SCL SA SDA MVO OUT1A/B LRCKI BICKI I2C SERIAL DATA IN SDI12 SDI34 OUT2A/B OUT3A/B OVERSAMPLING SYSTEM CONTROL SDI56 OUT4A/B DDX OUT5A/B OUT6A/B SDI78 OUT7A/B VARIABLE OVERSAMPLING CHANNEL MAPPING VOLUME LIMITING LRCKO SERIAL DATA OUT SYSTEM TIMING PLL PLLB Figure 2. CKOUT P e t e l o 8/63 1x,2x,4x Interp Distortion Compensation bs From Mix#1 Engine Or Previous Channel Biquad#10 Output (CxBLP) PreScale Hard Set to -18dB when AutoMode EQ (AMEQ) du o r P e t e ol EAPD BICKO SDO12 SDO34 SDO56 SDO78 s b O t c u d o r 8 Inputs From I2S ) (s DSD Conversion Interp_Rate O PWDN Channel signal flow 6 Inputs From DSD VARIABLE DOWNSAMPLING POWER DOWN XTI ) s ( ct OUT8A/B TREBLE, BASS, EQ (BIQUADS) High-Pass Filter User Progammable Biquad #1 when High-Pass Bypassed (HPB) DSDE Mapping/ Mix #1 NS Biquad #2 Biquad #3 Biquads B/T C_Con Biquad #4 Biquad #5 Hard Set Coeffecients when AutoMode EQ (AMEQ) Volume Limiter Mix #2 DDX Output PWM Biquad #6 Biquad #7 2x Interp Biquad #8 Hard Set Hard Set Coeffecients when Coeffecients when AutoMode DeEmphasis Bass Management Enabled Crossover (DEMP) (AMBMXE) To Mix#2 Engine Bass Treble User Programmable Biquads #9 and #10 When Tone Bypassed (CxTCB) STA308A Pin connections OUT1_B OUT1_A EAPD VDD GND BICKO NC LRCKO SDO_12 SDO_34 VDD GND NC SDO_56 Pin connection (Top view) PWDN Figure 3. SDO_78 2 Pin connections 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 MVO 1 48 OUT2_A GND 2 47 OUT2_B VDD 3 46 NC GND 4 45 GND NC 5 44 VDD SDI_78 6 43 OUT3_A SDI_56 7 42 OUT3_B SDI_34 8 41 OUT4_A SDI_12 9 40 OUT4_B LRCKI 10 39 OUT5_A BICKI 11 38 OUT5_B VDD 12 37 NC GND 13 36 GND NC 14 RESET 15 PLLB 16 ) s ( ct u d o r P e 35 VDD 34 OUT6_A 33 OUT6_B Pin description Pin Type t c u OUT7_A OUT7_B OUT8_A VDD OUT8_B GND NC CKOUT VDDA GNDA NC FILTER_PLL XTI t e l o STA308APINCON s b O Name Description 5-V tolerant TTL input buffer MVO/DSD_CLK Master volume override/ DSD input clock 5-V tolerant TTL input buffer SDI_78/DSD_6 Input serial data channels 7 & 8/ DSD input channel 6 5-V tolerant TTL input buffer SDI_56/DSD_5 Input serial data channels 5 & 6/ DSD input channel 5 8 5-V tolerant TTL input buffer SDI_34/DSD_4 Input serial data channels 3 & 4/ DSD input channel 4 9 5-V tolerant TTL input buffer SDI_12/DSD_3 Input serial data channels 1 & 2/ DSD input channel 3 10 5-V tolerant TTL input buffer LRCKI/DSD_2 Input left/right clock/ DSD input channel 2 11 5-V tolerant TTL input buffer BICKI/DSD_1 Input serial clock/ DSD input channel 1 15 5-V tolerant TTL schmitt trigger input buffer RESET Global reset 16 CMOS input buffer with pull-down PLL_BYPASS Bypass phase locked loop 1 6 d o r P e let 7 b O SCL SA ) (s Table 2. so SDA 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9/63 Pin connections STA308A Table 2. Pin description (continued) Pin SA Select address (I2C) 18 Bidirectional buffer: 5-V tolerant TTL schmitt trigger input; 3.3-V capable 2mA slew-rate controlled output. SDA Serial data (I2C) 19 5-V tolerant TTL schmitt trigger input buffer SCL Serial clock (I2C) 20 5-V tolerant TTL schmitt trigger input buffer XTI Crystal oscillator input (clock input) 21 Analog pad FILTER_PLL PLL filter 23 Analog ground GNDA PLL ground 24 3.3V analog supply voltage VDDA PLL supply 25 3.3-V capable TTL tristate 4mA output buffer CKOUT 29 3.3-V capable TTL 2mA output buffer OUT8B 30 3.3-V capable TTL 2mA output buffer 31 3.3-V capable TTL 2mA output buffer 32 33 )- u d o r P e Clock output t e l o s b O OUT8A ) s ( ct PWM channel 8 output B PWM channel 8 output A OUT7B PWM channel 7 output B 3.3-V capable TTL 2mA output buffer OUT7A PWM channel 7 output A 3.3-V capable TTL 2mA output buffer OUT6B PWM channel 6 output B 3.3-V capable TTL 2mA output buffer OUT6A PWM channel 6 output A 3.3-V capable TTL 2mA output buffer OUT5B PWM channel 5 output B 39 3.3-V capable TTL 2mA output buffer OUT5A PWM channel 5 output A 40 3.3-V capable TTL 2mA output buffer OUT4B PWM channel 4 output B 41 3.3-V capable TTL 2mA output buffer OUT4A PWM channel 4 output A 42 3.3-V capable TTL 2mA output buffer OUT3B PWM channel 3 output B 43 3.3-V capable TTL 2mA output buffer OUT3A PWM channel 3 output A 47 3.3-V capable TTL 2mA output buffer OUT2B PWM channel 2 output B 38 10/63 Description CMOS input buffer with pull-down s ( t c u d o r P e t e l o O Name 17 34 bs Type STA308A Pin connections Table 2. Pin description (continued) Pin Name Description 48 3.3-V capable TTL 2mA output buffer OUT2A PWM channel 2 output A 49 3.3-V capable TTL 2mA output buffer OUT1B PWM channel 1 output B 50 3.3-V capable TTL 2mA output buffer OUT1A PWM channel 1 output A 51 3.3-V capable TTL 4mA output buffer EAPD Ext. amp power-down 55 3.3-V capable TTL 2mA output buffer BICKO Output serial clock 56 3.3-V capable TTL 2mA output buffer LRCKO Output left/right clock 57 3.3-V capable TTL 2mA output buffer SDO_12 58 3.3-V capable TTL 2mA output buffer SDO_34 62 3.3-V capable TTL 2mA output buffer r P e SDO_56 63 3.3-V capable TTL 2mA output buffer 64 5-V tolerant TTL schmitt trigger input buffer 3,12,28,35, 44,52,59 3.3-V digital supply voltage ) s ( ct u d o Output serial data channels 1&2 s b O t e l o Output serial data channels 3&4 Output serial data channels 5&6 SDO_78 Output serial data channels 7&8 PWDN Device power-down VDD 3.3-V supply 2,4,13,27, Digital ground 36,45,53,60 GND Ground 5, 14, 22, 26,37,46,54, 61 NC Not connected ) (s t c u d o r P e let o s b Type O 11/63 Electrical specification STA308A 3 Electrical specification 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol 3.2 Parameter Unit -0.5 4 V VDDA 3.3-V logic power supply -0.5 4 V Vi Voltage on input pins -0.5 VDD + 0.5 V Vo Voltage on output pins -0.5 VDD + 0.3 V Tstg Storage temperature -40 150 °C Tamb Ambient operating temperature -40 90 °C e t e ol Thermal data Symbol Rthj-amb s b O Parameter )- Table 5. ) s ( ct u d o Pr Min Thermal resistance, junction to ambient s ( t Recommendedc operating condition u d o r P e t e ol Typ Max 85 Unit °C/W Recommended operating condition Symbol s b O Max 3.3-V I/O power supply Thermal data 3.3 Typ VDD Table 4. 12/63 Min Parameter Min Typ Max Unit VDD I/O power supply 3.0 3.6 V VDDA Logic power supply 3.0 3.6 V Tj Operating junction temperature -40 125 °C STA308A 3.4 Electrical specification Electrical specifications The following specifications are valid for VDD = 3.3V ± 0.3V, VDDA = 3.3V ± 0.3V and Tamb = 0 to 70 °C, unless otherwise stated Table 6. General interface electrical specifications Symbol Parameter Conditions Min Typ Max Unit Iil Low-level input no pull-up Vi = 0V 1 (1) µA Iih High-level input no pull-down Vi = VDD 2 µA IOZ Tristate output leakage without pull-up/down Vi = VDD 2 µA Vesd Electrostatic protection (human body model) Leakage < 1µA ) s ( ct 2000 V u d o 1. The leakage currents are generally very small, < 1 nA. The values given here are maximum after an electrostatic stress on the pin. Table 7. r P e DC electrical characteristics: 3.3-V buffers Symbol let Parameter Conditions VIL Low-level input voltage VIH High-level input voltage VILhyst Low-level threshold VIHhyst High-level threshold Vhyst Schmitt trigger hysteresis Vol Low-level output Voh High-level output r P e od O ) t(s uc o s b Min Typ Max Unit 0.8 V 2.0 V Input falling 0.8 1.35 V Input rising 1.3 2.0 V 0.3 0.8 V 0.2 V IoI = 100uA Ioh = -100uA VDD0.2 V Ioh = -2mA 2.4 V t e l o s b O 13/63 Pin description 4 STA308A Pin description Master volume override (MVO) This pin enables the user to bypass the volume control on all channels. When MVO is pulled high, the master volume register is set to 0x00, which corresponds to its full scale setting. The master volume register setting offsets the individual channel volume settings, which default to 0 dB. Serial data in (SDI_12, SDI_34, SDI_56, SDI_78) Audio information enters the device here. Six format choices are available including I2S, left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits. ) s ( ct RESET u d o Driving this pin low turns off the outputs and returns all settings to their defaults. r P e 2 I C bus The SA, SDA and SCL pins operate per the Phillips I2C specification. See Section 5. t e l o Phase locked loop (PLL) s b O The phase locked loop section provides the system timing signals and CKOUT. Clock output (CKOUT) ) (s System synchronization and master clocks are provided by the CKOUT. t c u PWM outputs (OUT1 through OUT8) The PWM outputs provide the input signal for the power devices. d o r External amplifier power-down (EAPD) P e This signal can be used to control the power-down of DDX power devices. t e l o Serial data out (SDO_12, SDO_34, SDO_56, SDO_78) s b O These are the outputs for audio information. Six different formats are available including I2S, left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits. Device power-down (PWDN) Pulling PWDN low begins the power-down sequence which puts the STA308A into a low-power state. EAPD (pin 51) goes low approximately 30 ms later. 14/63 I2C bus operation STA308A I2C bus operation 5 The STA308A supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA308A is always a slave device in all of its communications. 5.1 Communication protocol 5.1.1 Data transition or change ) s ( ct u d o r P e Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition. 5.1.2 t e l o Start condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. 5.1.3 ) (s Stop condition s b O t c u STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA308A and the bus master. 5.1.4 d o r P e Data input t e l o During the data input the STA308A samples the SDA signal on the rising edge of clock SCL. s b O 5.2 For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. Device addressing To start communication between the master and the Omega DDX core, the master must initiate with a start condition. Following this, the master sends 8 bits onto the SDA line (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA308A the I2C interface has two device addresses depending on the SA port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1. The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After a START condition the STA308A identifies on the bus the device 15/63 I2C bus operation STA308A address and if a match is found, it acknowledges the identification on SDA bus during the 9th-bit time. The byte following the device identification byte is the internal space address. 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA308A acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the STA308A again responds with an acknowledgement. 5.3.1 Byte write ) s ( ct In the byte write mode the master sends one data byte, this is acknowledged by the Omega DDX core. The master then terminates the transfer by generating a STOP condition. 5.3.2 u d o Multi-byte write r P e The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer. Figure 4. t e l o Write mode sequence ACK BYTE WRITE DEV-ADDR s b O ACK )- RW START t(s ACK MULTIBYTE WRITE DEV-ADDR uc START P e d o r Figure 5. t e l o s b O DATA IN STOP ACK ACK SUB-ADDR ACK DATA IN DATA IN RW STOP Read mode sequence ACK CURRENT ADDRESS READ DEV-ADDR NO ACK DATA RW START STOP ACK RANDOM ADDRESS READ DEV-ADDR ACK ACK SUB-ADDR RW RW= ACK HIGH START SEQUENTIAL CURRENT READ DEV-ADDR DEV-ADDR START NO ACK DATA RW ACK STOP ACK DATA DATA NO ACK DATA STOP START ACK SEQUENTIAL RANDOM READ DEV-ADDR START 16/63 ACK SUB-ADDR ACK ACK SUB-ADDR RW DEV-ADDR START ACK DATA RW ACK DATA NO ACK DATA STOP +3.3V +3.3V SDATA2 SDATA1 SDATA0 LRCK BICK C157 47PF NPO EIA0603 MVO TEST_MODE VDD3.3_1 GND_1 NC 5 SDI_78 SDI_56 SDI_34 SDI_12 LRCKI BICKI VDD3.3_2 GND_2 NC 14 RESET PLL_BYPASS OUT2_A OUT2_B NC 46 GND_5 VDD3.3_5 OUT3_A OUT3_B OUT4_A OUT4_B OUT5_A OUT5_B NC 37 GND_4 VDD3.3_4 OUT6_A OUT6_B 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 C16 100PF NPO EIA0603 C23 100NF Y5V EIA0603 CH3_A CH3_B CH4_A CH4_B CH5_A CH5_B CH2_A CH2_B GNDA C19 220PF NPO EIA0603 C25 100NF Y5V EIA0603 +3.3V C14 100NF Y5V EIA0603 C22 22UF 6.3VDC EIA3528_B L3 600 ohm@100mhz 1 2 EIA0805 L1 600 ohm@100mhz 1 2 EIA0805 +3.3V C20 100NF Y5V EIA0603 ) s ( ct The PLL filter must be placed as close as possible to the STA308A pins C24 + 100NF Y5V EIA0603 VDDA +3.3V STA308A CH6_A CH6_B EAPD u d o C15 1200PF X7R EIA0603 R15 3.40K 0603 U2 CH1_A CH1_B R6 0 0000-0603 t e l o r P e SDA SCL MCLK C155 1000PF NPO EIA0603 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWDN SDO_78 SDO_56 NC 61 GND_7 VDD3.3_7 SDO_34 SDO_12 LRCKO BICKO NC 54 GND_6 VDD3.3_6 EAPD OUT1_A OUT1_B 1000PF NPO EIA0805 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C147 C145 100NF Y5V EIA0603 +3.3V s b O POWER_ON_RST C6 100NF Y5V EIA0603 C5 100NF Y5V EIA0603 0 0000-0603 R14 s b O t e l o PWRDWN P e C18 100NF Y5V EIA0603 d o r t c u ) (s SA SDA SCL XTI PLL_FILTER VDDA_PLL GNDA_PLL VDD3.3_PLL CKOUT NC 26 GND_3 VDD3.3_3 OUT8_B OUT8_A OUT7_B OUT7_A C12 + 100NF Y5V EIA0603 +3.3V Title STMicroelectr C4 2.2UF 6.3VDC EIA3216_A Figure 6. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 6 +3.3V STA308A Application reference schematic Application reference schematic Reference schematic for STA308A-based application 17/63 Registers STA308A 7 Registers 7.1 Register summary Table 8. Addr Register summary Name D7 D6 D5 COS1 COS0 DSPB D4 D3 D2 D1 D0 Configuration 0x00 CONFA IR1 IR0 MCS2 MCS1 MCS0 0x01 ConfB SAIFB SAI3 SAI2 SAI1 SAI0 0x02 ConfC SAOFB SAO3 SAO2 SAO1 SAO0 0x03 ConfD MPC CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 0x04 ConfE C8BO C7BO C6BO C5BO C4BO C3BO 0x05 ConfF PWMS2 PWMS1 PWMS0 BQL PSL DEMP 0x06 ConfG MPCV DCCV HPE AM2E AME 0x07 ConfH ECLE LDTE BCLE IDE 0x08 ConfI EAPD Volume control 0x09 MMUTE 0x0A Mvol MV7 0x0B C1Vol C1V7 0x0C C2Vol C2V7 0x0D C3Vol 0x0E C4Vol DRC HPB COD SID PWMD SVE ZCE NSBW ro PSCE MMUTE MV4 MV3 MV2 MV1 MV0 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0 c u d C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0 C4V7 C4V6 C4V5 C4V4 C4V3 C4V2 C4V1 C4V0 C5Vol C5V7 C5V6 C5V5 C5V4 C5V3 C5V2 C5V1 C5V0 0x10 C6Vol C6V7 C6V6 C6V5 C6V4 C6V3 C6V2 C6V1 C6V0 0x11 C7Vol C7V7 C7V6 C7V5 C7V4 C7V3 C7V2 C7V1 C7V0 0x12 C8Vol C8V7 C8V6 C8V5 C8V4 C8V3 C8V2 C8V1 C8V0 0x13 C1VTMB C1M C1VBP C1VT4 C1VT3 C1VT2 C1VT1 C1VT0 0x14 C2VTMB C2M C2VBP C2VT4 C2VT3 C2VT2 C2VT1 C2VT0 0x15 C3VTMB C3M C3VBP C3VT4 C3VT3 C3VT2 C3VT1 C3VT0 0x16 C4VTMB C4M C4VBP C4VT4 C4VT3 C4VT2 C4VT1 C4VT0 0x17 C5VTMB C5M C5VBP C5VT4 C5VT3 C5VT2 C5VT1 C5VT0 0x18 C6VTMB C6M C6VBP C6VT4 C6VT3 C6VT2 C6VT1 C6VT0 0x19 C7VTMB C7M C7VBP C7VT4 C7VT3 C7VT2 C7VT1 C7VT0 0x1A C8VTMB C8M C8VBP C8VT4 C8VT3 C8VT2 C8VT1 C8VT0 C1IM2 C1IM1 C1IM0 ro P e let O s b O C1BO MV5 0x0F o s b )- C3V7 MV6 t e l o du C2BO P e ZDE ) s ( ct t(s Input mapping 0x1B 18/63 C12im C2IM2 C2IM1 C2IM0 STA308A Registers Table 8. Register summary (continued) Addr Name D7 D6 D5 D4 D3 D2 D1 D0 0x1C C34im C4IM2 C4IM1 C4IM0 C3IM2 C3IM1 C3IM0 0x1D C56im C6IM2 C6IM1 C6IM0 C5IM2 C5IM1 C5IM0 0x1E C78im C8IM2 C8IM1 C8IM0 C7IM2 C7IM1 C7IM0 AMEQ0 AutoMode 0x1F Auto1 AMDM AMGC2 AMGC1 AMGC0 AMV1 AMV0 AMEQ1 0x20 Auto2 SUB RSS1 FSS AMBMXE AMBMME 0x21 Auto3 AMAM2 AMAM1 AMAM0 AMAME 0x22 PreEQ XO2 0x23 Ageq 0x24 RSS0 CSS1 CSS0 MSA AMPS PEQ2 PEQ1 PEQ0 AGEQ4 AGEQ3 AGEQ2 AGEQ1 AGEQ0 Bgeq BGEQ4 BGEQ3 BGEQ2 0x25 Cgeq CGEQ4 CGEQ3 CGEQ2 0x26 Dgeq 0x27 Egeq EGEQ4 EGEQ3 XO1 XO0 PEQ4 PEQ3 BGEQ0 CGEQ1 CGEQ0 DGEQ4 DGEQ3 ro DGEQ2 DGEQ1 DGEQ0 t e l o EGEQ2 EGEQ1 EGEQ0 C3BLP C2BLP C1BLP Processing loop bs C6BLP du BGEQ1 P e C7BLP ) s ( ct 0x28 BQlp C8BLP 0x29 MXlp C8MXLP C7MXLP C6MXLP C5MXLP C4MXLP C3MXLP C2MXLP C1MXLP O ) Processing pypass s ( t c C5BLP C4BLP 0x2A EQbp C8EQBP C7EQBP C6EQBP C5EQBP C4EQBP C3EQBP C2EQBP C1EQBP 0x2B ToneBP C8TCB u d o Tone control 0x2C Tone r P e TTC3 C7TCB C6TCB C5TCB C4TCB C3TCB C2TCB C1TCB TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0 Dynamics control let O o s b 0x2D C1234ls C4LS1 C4LS0 C3LS1 C3LS0 C2LS1 C2LS0 C1LS1 C1LS0 0x2E C5678ls C8LS1 C8LS0 C7LS1 C7LS0 C6LS1 C6LS0 C5LS1 C5LS0 0x2F L1ar L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0 0x30 L1atrt L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0 0x31 L2ar L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0 0x32 L2atrt L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0 PWM output timing 0x33 C12ot C2OT2 C2OT1 C2OT0 C1OT2 C1OT1 C1OT0 0x34 C34ot C4OT2 C4OT1 C4OT0 C3OT2 C3OT1 C3OT0 0x35 C56ot C6OT2 C6OT1 C6OT0 C5OT2 C5OT1 C5OT0 0x36 C78ot C8OT2 C8OT1 C8OT0 C7OT2 C7OT1 C7OT0 C2OM2 C2OM1 C2OM0 C1OM2 C1OM1 C1OM0 I2S output channel mapping 0x37 C12om 19/63 Registers STA308A Table 8. Addr Register summary (continued) Name D7 D6 D5 D4 D3 D2 D1 D0 0x38 C34om C4OM2 C4OM1 C4OM0 C3OM2 C3OM1 C3OM0 0x39 C56om C6OM2 C6OM1 C6OM0 C5OM2 C5OM1 C5OM0 0x3A C78om C8OM2 C8OM1 C8OM0 C7OM2 C7OM1 C7OM0 CFA9 CFA8 User-defined coefficient RAM 0x3B Cfaddr1 0x3C Cfaddr2 CFA7 CFA6 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0 0x3D B1cf1 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16 0x3E B1cf2 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8 0x3F B1cf3 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0 0x40 B2cf1 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 0x41 B2cf2 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 0x42 B2cf3 C2B7 C2B6 C2B5 C2B4 C2B3 0x43 A1cf1 C3B23 C3B22 C3B21 C3B20 0x44 A1cf2 C3B15 C3B14 C3B13 C3B12 0x45 A1cf3 C3B7 C3B6 C3B5 0x46 A2cf1 C4B23 C4B22 C4B21 0x47 A2cf2 C4B15 C4B14 0x48 A2cf3 C4B7 0x49 B0cf1 C5B23 0x4A B0cf2 0x4B B0cf3 P e 0x4C let o s b O 20/63 ro C5B7 du C2B17 C2B16 C2B9 C2B8 C2B2 C2B1 C2B0 C3B19 C3B18 C3B17 C3B16 C3B11 C3B10 C3B9 C3B8 C3B4 C3B3 C3B2 C3B1 C3B0 C4B20 C4B19 C4B18 C4B17 C4B16 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0 WA W1 ro P e t e l o bs O ) t(s c u d C5B15 ) s ( ct Cfud 0x4D MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8 0x4E MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0 0x4F DCC1 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8 0x50 DCC2 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0 0x51 PSC1 RCV11 RCV10 RCV9 RCV8 RCV7 RCV6 RCV5 RCV4 0x52 PSC2 RCV3 RCV2 RCV1 RCV0 CNV11 CNV10 CNV9 CNV8 0x53 PSC3 CNV7 CNV6 CNV5 CNV4 CNV3 CNV2 CNV1 CNV0 STA308A Registers 7.2 Register description 7.2.1 Configuration register A (0x00) D7 D6 D5 D4 D3 D2 D1 D0 COS1 COS0 DSPB IR1 IR0 MCS2 MCS1 MCS0 1 0 0 0 0 0 1 1 Bit RW RST Name 0 RW 1 MCS0 1 RW 1 MCS1 2 RW 0 MCS2 Description ) s ( ct Master clock select: selects the ratio between the input I2S sample frequency and the input clock. u d o The DDX8000 supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, 192 kHz, and 2.8224 MHz DSD. Therefore the internal clocks are: r P e " 65.536 MHz for 32 kHz " 90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD " 98.304 MHz for 48 kHz, 96 kHz, and 192 kHz t e l o The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). The relationship between the input clock and the input sample rate is determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits determine the PLL factor generating the internal clock and the IRn bits determine the oversampling ratio used internally. ) (s t c u Input sample rate od fs (kHz) MCS[2:0] IR 1XX 011 010 001 000 00 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs 88.2, 96 01 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs 176.4, 192 10 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs DSD 11 2 * fs 4 * fs 6 * fs 8 * fs 10 * fs Pr 32, 44.1, 48 e t e ol s b O s b O Interpolation ratio select Bit RW RST Name 3 RW 0 IR0 4 RW 0 IR1 Description Interpolation ratio select: selects internal interpolation ratio based on input I2S sample frequency The STA308A has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 4 times, 2 times, or 1 time (pass-through). The oversampling ratio of this interpolation is determined by the IR bits. 21/63 Registers STA308A I Input sample rate IR[1,0] 1st stage interpolation ratio Fs (kHz) 00 32 4-times oversampling 00 44.1 4-times oversampling 00 48 4-times oversampling 01 88.2 2-times oversampling 01 96 2-times oversampling 10 176.4 Pass-through 10 192 Pass-through 11 DSD DSD to 176.4 kHz conversion Bit 0 RW RW RST 0 u d o Name DSPB ) s ( ct Description DSP bypass bit: 0: normal operation 1: bypass of biquad and bass/treble functions r P e t e l o Setting the DSPB bit bypasses the biquad function of the Omega DDX core. COS[1,0] 00 ) (s 01 10 t c u 11 d o r P e t e l o s b O 22/63 s b O CKOUT frequency PLL output PLL output / 4 PLL output / 8 PLL output / 16 STA308A 7.2.2 Registers Configuration register B (0x01) - serial input formats D7 Bit D6 RW D5 RST D4 D3 D2 RW 0 SAI0 1 RW 0 SAI1 2 RW 0 SAI2 3 RW 0 SAI3 D0 SAIFB SAI3 SAI2 SAI1 SAI0 0 0 0 0 0 Name 0 D1 Description Serial audio input interface format: determines the interface format of the input serial digital audio interface. ) s ( ct Serial data interface u d o The STA308A audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. STA308A always acts a slave when receiving audio input from standard digital audio components. Serial data for eight channels is provided using 6 input pins: left/right clock LRCKI (pin 10), serial clock BICKI (pin 11), serial data 1 and 2 SDI12 (pin 9), serial data 3 and 4 SDI34 (pin 8), serial data 5 and 6 SDI56 (pin 7), and serial data 7 and 8 SDI78 (pin 6). The SAI/SAIFB register (Configuration Register B, address 0x01) is used to specify the serial data format. The default serial data format is I2S, MSB-first. Available formats are shown in the tables and figure that follow. r P e t e l o Bit 4 Note: RW RW RST 0 )- Name u d o s ( t c SAIFB s b O Description Determines MSB or LSB first for all SAO formats: 0: MSB first 1: LSB first r P e Serial input and output formats are specified separately For example, SAI = 1110 and SAIFB = 1 would specify right-justified 16-bit data, LSB-first. t e l o s b O 23/63 Registers STA308A The table below lists the serial audio input formats supported by STA308A as related to BICKI = 32 * fs, 48 * fs, 64 * fs, where sampling rate, fs = 32, 44.1, 48, 88.2, 96, 176.4, 192 kHz. BICKI SAI [3:0] SAIFB Interface format 1100 X I2S 15-bit data 1110 X Left/right-justified 16-bit data 0100 X I2S 23-bit data 0100 X I2S 20-bit data 1000 X I2S 18-bit data 0100 0 MSB-first I2S 16-bit data 1100 1 LSB-first I2S 16-bit data 0001 X Left-justified 24-bit data 0101 X Left-justified 20-bit data 1001 X Left-justified 18-bit data 1101 X Left-justified 16-bit data 0010 X Right-justified 24-bit data 0110 X 1010 O ) 32 * fs 48 * fs 1110 let o s b O 24/63 64 * fs t e l o bs Right-justified 20-bit data Right-justified 18-bit data Right-justified 16-bit data X I2S 24-bit data 0100 X I2S 20-bit data 1000 X I2S 18-bit data 0000 0 MSB-first I2S 16-bit data 1100 1 LSB-first I2S 16-bit data 0001 X Left-justified 24-bit data 0101 X Left-justified 20-bit data 1001 X Left-justified 18-bit data 1101 X Left-justified 16-bit data 0010 X Right-justified 24-bit data 0110 X Right-justified 20-bit data 1010 X Right-justified 18-bit data 1110 X Right-justified 16-bit data s ( t c P e r P e X 0000 du ro X u d o ) s ( ct STA308A 7.2.3 Registers Configuration register C (0x02) - serial output formats D7 Bit D6 RW D5 RST D4 D3 D2 RW 0 SAO0 1 RW 0 SAO1 2 RW 0 SAO2 3 RW 0 SAO3 D0 SAOFB SAO3 SAO2 SAIO SAO0 0 0 0 0 0 Name 0 D1 Description Serial audio output interface format: determines the interface format of the output serial digital audio interface. ) s ( ct The STA308A features a serial audio output interface that consists of 8 channels. The serial audio output always acts as a slave to the serial audio input interface and, therefore, all output clocks are synchronous with the input clocks. The output sample frequency (fs) is also equivalent to the input sample frequency. In the case of SACD/DSD input, the serial audio output acts as a master with an output sampling frequency of 176.4 kHz. The output serial format can be selected independently from the input format and is done via the SAO and SAOFB bits. u d o r P e Bit 4 RW RW RST 0 BICKI = BICKO t e l o bs Name ) (s SAOFB t c u od r P e 32 * fs t e l o s b O Description Determines MSB or LSB first for all SAO formats: 0: MSB first 1: LSB first SAO[3:0] Interface data format 0111 I2S data 1111 Left/right-justified 16-bit data 1110 I2S data 0001 Left-justified data 1010 Right-justified 24-bit data 1011 Right-justified 20-bit data 1100 Right-justified 18-bit data 1101 Right-justified 16-bit data 0000 I2S data 0001 Left-justified data 0010 Right-justified 24-bit data 0011 Right-justified 20-bit data 0100 Right-justified 18-bit data 0101 Right-justified 16-bit data 48 * fs O 64 * fs 25/63 Registers 7.2.4 STA308A Configuration register D (0x03) D7 D6 D5 D4 D3 D2 D1 D0 MPC CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 1 1 0 0 0 0 1 0 Bit RW RST Name 0 RW 0 OM0 1 RW 1 OM1 Description DDX power output mode: selects configuration of DDX output. ) s ( ct The DDX power output mode selects how the DDX output timing is configured. Different power devices use different output modes. The STA50x recommended use is OM = 10. OM[1,0] Output stage - mode 00 STA50x/STA51xB - drop compensation 01 Discrete output stage - tapered compensation 10 STA50x/STA51xB - full power mode 11 Variable drop compensation (CSZn bits) Bit RST Name 2 RW 0 CSZ0 3 RW 0 CSZ1 4 RW 0 5 RW 0 6 RW ) (s t c u CSZ2 CSZ3 od r P e t e l o s b O RW 1 CSZ4 CSZ[4:0] Compensating pulse size 0 clock period compensating pulse size 00001 1 clock period compensating pulse size … … 11111 31 clock period compensating pulse size 7 RW RW Description Contra size register: when OM[1,0] = 11, this register determines the size of the DDX compensating pulse from 0 clock ticks to 31 clock periods. 00000 Bit r P e t e l o s b O u d o RST 1 Name MPC Description Max power correction: setting of 1 enables STA50x correction for THD reduction near maximum power output. Setting the MPC bit turns on special processing that corrects the STA50x power device at high power. This mode should lower the THD+N of a full STA50x DDX system at maximum power output and slightly below. This mode will only be operational in OM[1,0] = 01. 26/63 STA308A 7.2.5 Registers Configuration register E (0x04) D7 D6 D5 D4 D3 D2 D1 D0 C8BO C7BO C6BO C5BO C4BO C3BO C2BO C1BO 0 0 0 0 0 0 0 0 Bit RW RST Name 0 RW 0 C1BO 1 RW 0 C2BO 2 RW 0 C3BO 3 RW 0 C4BO 4 RW 0 C5BO 5 RW 0 C6BO 6 RW 0 C7BO 7 RW 0 C8BO Description ) s ( ct Channels 1, 2, 3, 4, 5, 6, 7, and 8 binary output mode enable bits. A setting of 0 indicates ordinary DDX tristate output. A setting of 1 indicates binary output mode. u d o r P e t e l o Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel will be considered the positive output and output B is negative inverse. 7.2.6 s b O Configuration register F (0x05) D7 PWMS2 PWMS1 0 0 Bit 0 s b O RW D5 t c u d o r RW P e t e l o ) (s D6 D3 D2 D1 D0 PWMS0 BQL PSL DEMP DRC HPB 0 0 0 0 0 0 RST 0 D4 Name Description High-pass filter bypass bit: setting of one bypasses internal AC coupling digital high-pass filter HPB The STA308A features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage. If HPB = 1, then the filter that the high-pass filter utilizes is made available as userprogrammable biquad#1. Bit 1 RW RW RST 0 Name DRC Description Dynamic range compression/anti-clipping 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. 27/63 Registers STA308A In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level. Bit 2 RW RST RW 0 Name Description De-emphasis: 0: no de-emphasis 1: de-emphasis DEMP By setting this bit to one de-emphasis will implemented on all channels. When this is used it takes the place of biquad #7 in each channel and any coefficients using biquad #1 will be ignored. DSPB (DSP bypass) bit must be set to 0 for de-emphasis to function. Bit 3 RW RST RW 0 Name ) s ( ct Description u d o Post-scale link: 0: each channel uses individual post-scale value 1: each channel uses channel 1 post-scale value PSL r P e Post-Scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster. t e l o Bit 4 RW RST RW 0 Name BQL )- s ( t c s b O Description Biquad link: 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values u d o For ease of use, all channels can use the biquad coefficients loaded into the channel 1 Coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once. r P e t e l o Bit 7:5 s b O 28/63 RW RW PWMS[1:0] RST 00 Name PWMS[2:0] Description PWM speed selection: PWM output speed 000 Normal speed (384 kHz) (all channels 001 Half-speed (192 kHz) (all channels 010 Double-speed (768 kHz) (all channels 011 Normal speed (channels 1-6), double-speed (channels 7-8) 100 Odd speed (341.3 kHz) (all channels) STA308A 7.2.7 Registers Configuration register G (0x06) D7 D6 D5 D4 D3 D2 D1 D0 MPCV DCCV HPE AM2E AME COD SID PWMD 0 0 0 0 0 0 0 0 Bit 0 RW RST RW 0 Name Description PWMD PWM output disable: 0: PWM output normal 1: no PWM output 1 RW 0 SID Serial interface (I2S out) disable: 0: I2S output normal 1: no I2S output 2 RW 0 COD Clock output disable: 0: clock output normal 1: no clock output RW RST Bit 3 RW 0 o s b AME O ) u d o r P e let Name ) s ( ct Description AM mode enable: 0: normal DDX operation. 1: AM reduction mode DDX operation. The STA308A features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to ~83 dB in this mode, which is still greater than the SNR of AM radio. s ( t c Bit 4 u d o r P e t e l o s b O RW RW RST 0 Name Description AM2 mode enable: 0: normal DDX operation. 1: AM2 reduction mode DDX operation. AM2E The STA308A features a 2 DDX processing modes that minimize the amount of noise generated in frequency range of AM radio. This second mode is intended for use when DDX is operating in a device with an AM tuner active. This mode eliminates the noise-shaper. Bit 5 RW RW RST 0 Name HPE Description DDX headphone enable: 0: channels 7 and 8 normal DDX operation 1: channels 7 and 8 headphone operation Channels 7 and 8 can be configured to be processed and output in such a manner that headphones can be driven using and appropriate output device. This signal is a differential 3-wire drive called DDX Headphone. 29/63 Registers STA308A Bit RW 6 RW Bit Name 0 RW 7 7.2.8 RST Distortion compensation variable enable: 0: uses preset DC coefficient. 1: uses DCC coefficient. DCCV RST RW Description Name 0 Description Max power correction variable: 0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient MPCV ) s ( ct Configuration register H (0x07) D7 D6 D5 D4 D3 D2 ECLE LDTE BCLE IDE ZDE SVE 0 1 1 1 1 1 Bit 0 RW RW RST Bit 1 RW 0 NSBW 1 Name s ( t c ZCE u d o r P e u d o ZCE Pr 1 D0 NSBW 0 Description o s b Noise-shaper bandwidth selection: 1: 3rd order NS 0: 4th order NS O ) RST RW e t e l Name D1 Description Zero-crossing volume enable: 1: volume adjustments will only occur at digital zerocrossings 0: volume adjustments will occur immediately The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible. t e l o s b O Bit 2 Bit 3 RW RW RW RW RST 1 Name 1 Soft volume enable: 1: volume adjustments use soft volume 0: volume adjustments occur immediately SVE RST Name ZDE Description Description Zero-detect mute enable: setting of 1 enables the automatic zero-detect mute Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the input data to each processing channel after the channel-mapping block. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. 30/63 STA308A Registers Bit 4 RW RW RST 1 Name Description Invalid input detect mute enable: 1: enable the automatic invalid input detect mute IDE Setting the IDE bit enables this function, which looks at the input I2S data and will automatically mute if the signals are perceived as invalid. Bit 5 RW RW RST 1 Name Description BCLE Binary output mode clock loss detection enable Detects loss of input MCLK in binary mode and will output 50% duty cycle. Bit 6 RW RW RST 1 Name u d o LDTE LRCLK double trigger protection enable r P e Actively prevents double trigger of LRCLK. Bit 7 RW RW RST let Name 0 ) s ( ct Description o s b ECLE Description Auto EAPD on clock loss When active will issue a device power down signal (EAPD) on clock loss detection 7.2.9 O ) Configuration register I (0x08) D7 D5 D4 D3 D2 D1 du EAPD 0 s ( t c D6 D0 PSCE o r P 0 This feature utilizes an ADC on SDI78 that provides power supply ripple information for correction. Registers PSC1, PSC2, PSC3 are utilized in this mode. s b O e t e ol Bit 0 RW Bit 7 RW RW RW RST 0 Name 0 Power supply ripple correction enable: 0: normal operation 1: PSCorrect operation PSCE RST Name EAPD Description Description External amplifier power down: 0: external power stage power down active 1: normal operation 31/63 Registers 7.2.10 STA308A Master mute register (0x09) D7 D6 D5 D4 D3 D2 D1 D0 MMUTE 0 7.2.11 Master volume register (0x0A) D7 D6 D5 D4 D3 D2 D1 MV7 MV6 MV5 MV4 MV3 MV2 MV1 1 1 1 1 1 1 1 D0 MV0 ) s ( ct 1 Note: Value of volume derived from MVOL is dependent on AMV AutoMode volume settings. 7.2.12 Channel 1 volume (0x0B) D7 7.2.13 D6 D3 r P e t e l o D2 D1 D0 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0 0 1 1 0 0 0 0 0 ) (s D6 C2V7 C2V6 0 1 D5 du ct o r P s b O D4 D3 D2 D1 D0 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0 1 0 0 0 0 0 Channel 3 volume (0x0D) e t e l D7 o s b D6 D5 D4 D3 D2 D1 D0 C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0 0 1 1 0 0 0 0 0 Channel 4 volume (0x0E) D7 32/63 D4 Channel 2 volume (0x0C) 7.2.14 7.2.15 D5 C1V7 D7 O u d o D6 D5 D4 D3 D2 D1 D0 C4V7 C4V6 C4V5 C4V4 C4V3 C4V2 C4V1 C4V0 0 1 1 0 0 0 0 0 STA308A 7.2.16 Registers Channel 5 volume (0x0F) D7 7.2.17 D6 D2 D1 D0 C5V6 C5V5 C5V4 C5V3 C5V2 C5V1 C5V0 0 1 1 0 0 0 0 0 D6 D5 D4 D3 D2 D1 C6V7 C6V6 C6V5 C6V4 C6V3 C6V2 C6V1 0 1 1 0 0 0 0 Channel 7 volume (0x11) D7 7.2.19 D6 D5 D4 D3 C7V7 C7V6 C7V5 C7V4 C7V3 0 1 1 0 0 7.2.20 D6 C8V7 C8V6 0 1 D5 (s) C8V5 t c u 1 d o r C7V2 e t e l 0 D0 C6V0 ) s ( ct 0 u d o Pr D2 o s b Channel 8 volume (0x12) D7 D1 D0 C7V1 C7V0 0 0 -O C8V4 C8V3 C8V2 C8V1 C8V0 0 0 0 0 0 D4 D3 D2 D1 D0 Channel 1 volume trim, mute, bypass (0x13) P e D7 let o s b 7.2.22 D3 Channel 6 volume (0x10) 7.2.18 O D4 C5V7 D7 7.2.21 D5 D6 C1M C1VBP 0 0 D5 0 D4 D3 D2 D1 D0 C1VT4 C1VT3 C1VT2 C1VT1 C1VT0 1 0 0 0 0 Channel 2 volume trim, mute, bypass (0x14) D7 D6 C2M C2VBP 0 0 D5 0 D4 D3 D2 D1 D0 C2VT4 C2VT3 C2VT2 C2VT1 C2VT0 1 0 0 0 0 Channel 3 volume trim, mute, bypass (0x15) D7 D6 C3M C3VBP 0 0 D5 0 D4 D3 D2 D1 D0 C3VT4 C3VT3 C3VT2 C3VT1 C3VT0 1 0 0 0 0 33/63 Registers 7.2.23 STA308A Channel 4 volume trim, mute, bypass (0x16) D7 7.2.24 D6 C4M C4VBP 0 0 7.2.25 D6 C5M C5VBP 0 0 D3 D2 D1 D0 C4VT4 C4VT3 C4VT2 C4VT1 C4VT0 1 0 0 0 0 D5 0 D4 D3 D2 D1 D0 C5VT4 C5VT3 C5VT2 C5VT1 C5VT0 1 0 0 0 Channel 6 volume trim, mute, bypass (0x18) D7 7.2.26 D6 C6M C6VBP 0 0 D5 0 D3 D2 C6VT4 C6VT3 C6VT2 1 0 0 e t e l o s b u d o Pr D4 ) s ( ct 0 D1 D0 C6VT1 C6VT0 0 0 Channel 7 volume trim, mute, bypass (0x19) D7 7.2.27 D6 C7M C7VBP 0 0 D5 (s) t c u 0 d o r -O D3 D2 D1 D0 C7VT4 C7VT3 C7VT2 C7VT1 C7VT0 1 0 0 0 0 D4 Channel 8 volume trim, mute, bypass (0x1A) P e D7 let o s b 34/63 0 D4 Channel 5 volume trim, mute, bypass (0x17) D7 O D5 D6 C8M C8VBP 0 0 D5 0 D4 D3 D2 D1 D0 C8VT4 C8VT3 C8VT2 C8VT1 C8VT0 1 0 0 0 0 The volume structure of the STA308A consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. There is also an additional offset for each channel called the channel volume trim. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -78 dB. As an example if C5V = 0xXX or +XXX dB and MV = 0xXX or -XX dB, then the total gain for channel 5 = XX dB. The channel volume trim is adjustable independently on each channel from -10 dB to +10 dB in 1 dB steps. The master mute when set to 1 will mute all channels at once, whereas the individual channel mutes (CnM) will mute only that channel. Both the master mute and the channel mutes provide a "soft mute" with the volume ramping down to mute in 8192 samples from the maximum volume setting at the internal processing rate (~192 kHz). A "hard mute" can be obtained by commanding a value of 0xFF (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel that whose total volume is less than -91 dB will be muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration register H) on a per channel basis as this creates the smoothest possible volume transitions. STA308A Registers When ZCE = 0, volume updates occur immediately. Each channel also contains an individual channel volume bypass. If a particular channel has volume bypassed via the CnVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. Each channel also contains a channel mute. If CnM = 1 a soft mute is performed on that channel. MV[7:0] Volume offset from channel value 0x00 0 dB 0x01 -0.5 dB 0x02 -1 dB … … 0x4C -38 dB … … 0xFE -127 dB 0xFF Hardware channel mute o s b 0x00 +47.5 dB 0x02 ) s ( ct … 0x5F 0x60 u d o 0x61 e t e ol Pr O -O +47 dB … +0.5 dB 0 dB -0.5 dB … -79.5 dB 0xFF bs Volume +48 dB 0x01 0xFE u d o r P e let CnV[7:0] … ) s ( ct Hardware channel mute CnVT[4:0] Volume 0x00 to 0x06 +10 dB 0x07 +9 dB … … 0x0F +1 dB 0x10 0 dB 0x11 -1 dB … … 0x19 -9 dB 0x1A to 0x1F -10 dB 35/63 Registers 7.2.28 STA308A Channel input mapping channels 1 and 2 (0x1B) D7 7.2.29 D6 D5 D4 C2IM2 C2IM1 0 0 D1 D0 C2IM0 C1IM2 C1IM1 C1IM0 1 0 0 0 D6 D5 D4 C4IM2 C4IM1 0 1 D3 D2 D1 D0 C4IM0 C3IM2 C3IM1 C3IM0 1 0 1 Channel input mapping channels 5 and 6 (0x1D) D7 7.2.31 D2 Channel input mapping channels 3 and 4 (0x1C) D7 7.2.30 D3 D6 D5 D4 C6IM2 C6IM1 C6IM0 1 0 1 D3 C5IM2 e t e l 1 o s b u d o Pr D2 ) s ( ct 0 D1 D0 C5IM1 C5IM0 0 0 Channel input mapping channels 7 and 8 (0x1E) D7 D6 C8IM2 D5 (s) C8M1 t c u 1 1 -O D4 D3 D2 D1 D0 C8IM0 C7IM2 C7IM1 C7IM0 1 1 1 0 Each channel received via I2S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing, simplifies output stage designs, and enables the ability to perform crossovers. The default settings of these registers map each I2S input channel to its corresponding processing channel. d o r P e t e l o bs O 36/63 CnIM[2:0] Serial input from 000 Channel 1 001 Channel 2 010 Channel 3 011 Channel 4 100 Channel 5 101 Channel 6 110 Channel 7 111 Channel 8 STA308A 7.2.32 Registers AUTO1 - AutoModes EQ, volume, GC (0x1F) D7 D6 D5 D4 D3 D2 D1 D0 AMDM AMGC2 AMGC1 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0 0 0 0 0 0 0 0 0 Bit 1:0 RW RW RST 0 Name AMEQ[1:0] Description Biquad 2-6 mode is: 00: user programmable 01: preset EQ - PEQ bits 10: graphic EQ - xGEQ bits 11: auto volume controlled loudness curve ) s ( ct By setting AMEQ to any setting other than 00 enables AutoMode EQ, biquads 1-5 are not user programmable. Any coefficient settings for these biquads will be ignored. Also when AutoMode EQ is used the pre-scale value for channels 1-6 becomes hard-set to -18 dB. u d o Bit 3:2 RW RW RST 0 AMV[1:0] )- 6:4 r P e t e l o Bit s b O 7 RW RW s ( t c u d o RW 0 AMGC[2:0] RST 0 r P e Name Name AMDM t e l o Description AutoMode volume mode (MVOL) is: 00: MVOL 0.5 dB 256 steps (standard) 01: MVOL auto curve 30 steps 10: MVOL auto curve 40 steps 11: MVOL auto curve 50 steps s b O AutoMode gain compression/limiters mode is: 000: user programmable GC 001: AC no clipping 010: AC limited clipping (10%) 011: DRC nighttime listening mode 100: DRC TV commercial/channel AGC 101: AC 5.1 no clipping 110: AC 5.1 limited clipping (10%) Description AutoMode 5.1 downmix: 0: normal operation 1: channels 7-8 are 2-channel downmix of channels 1-6 AutoMode downmix setting uses channels 7-8 of Mix#1 engine and therefore these channels of this function are fixed and not allowed to be user set when in this mode. Channels 1-6 must be arranged via channel mapping (registers CnIM) if necessary in the following manner for this operation: Channel 1: left Channel 2: right Channel 3: left surround Channel 4: right surround Channel 5: center Channel 6: LFE. 37/63 Registers 7.2.33 STA308A AUTO2 - AutoModes bass management2 (0x20) D7 D6 D5 D4 D3 D2 D1 D0 SUB RSS1 RSS0 CSS1 CSS0 FSS AMBMXE AMBMME 1 0 0 0 0 0 0 0 Bit 0 RW RW Bit 1 RST 0 RW RW Name AMBMME RST 0 Description 0: AutoMode bass management mix disabled 1: AutoMode bass management mix enabled Name AMBMXE ) s ( ct Description 0: AutoMode bass management crossover disabled 1: AutoMode bass management crossover enabled u d o Setting the AMBMME bit enables the proper mixing to take place for various preset bass management configurations. Setting the AMBMXE bit enables the proper crossover filtering in biquad #7 to take place. The crossover for bass management is always 2nd order (24 dB/oct) and the crossover frequency is determined by register bits PREEQ.XO[2:0]. r P e t e l o All configurations of Dolby Bass Management can be performed in the IC. These different configurations are selected as they would be by the end-user. s b O The AutoMode bass management settings utilize channels 1-6 on the Mix #1 engine, Channels 1-6 biquad #6, and channels 1-2 on the mix #2 engine in configuration #2. These functions cannot be user programmed while the bass management automode is active. ) (s Not all settings are valid as some configurations are unlikely and do not have to be supported by Dolby specification. t c u Automatic crossover settings are provided or custom crossovers can be implemented using the available programmable biquads. d o r Input channels must be mapped using channel-mapping feature in the following manner for bass management to be performed properly. P e t e l o 1: left front s b O 2: right front 3: left rear 4: right rear 5: center 6: LFE Bitfield 38/63 10 01 00 CSS - center speaker size Off Large Small RSS - rear speaker size Off Large Small STA308A Registers Bitfield 1 0 FSS - front speaker size Large Small SUB - subwoofer On Off When AMBMXE = 1, biquad #7 on channels 1-6 are utilized for bass-management crossover filter, this biquad is not user programmable in this mode. The XO settings determine the crossover frequency used, the crossover is 2nd order for both high-pass and low-pass with a -3 dB cross point. Higher order filters can be obtained be programming coefficients in other biquads if desired. It is recommended to use settings of 120-160 Hz when using small, single driver satellite speakers as the frequency response of these speakers normally are limited to this region. 7.2.34 D7 D6 D5 D4 AMAM2 AMAM1 AMAM0 AMAME 0 0 0 0 Bit 0 RW RW Bit 1 RW 4 RW RW AMAM[2:0] ) (s RST 0 t c u RST 0 D3 u d o D2 e t e ol Name AMPS d o r P e t e l o RST 0 RW Bit s b O ) s ( ct AUTO3 - AutoMode AM/pre-Scale/bass management scale (0x21) Pr D1 D0 MSA AMPS 0 0 Description s b O AutoMode pre-scale 0: -18 dB used for pre-scale when AMEQ = 00 1: user defined pre-scale when AMEQ = 00 Name MSA Description Bass management mix scale adjustment 0: -12 dB scaling on satellite channels in Config #1 1: no scaling on satellite channels in Config #1 Name AMAME Description AutoMode AM enable 0: switching frequency determined by PWMS settings 1: switching frequency determined by AMAM settings 48 kHz/96 kHz input Fs 44.1 / 88.2 kHz input Fs 000 0.535 MHz - 0.720 MHz 0.535 MHz - 0.670 MHz 001 0.721 MHz - 0.900 MHz 0.671 MHz - 0.800 MHz 010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz 011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz 100 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz 101 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz 110 1.601 MHz - 1.700 MHz 1.501 MHz - 1.700 MHz 39/63 Registers 7.2.35 STA308A PREEQ - Preset EQ settings (0x22) D7 D6 D5 D4 D3 D2 XO1 XO0 PEQ4 PEQ3 PEQ2 PEQ1 PEQ0 1 0 1 0 0 0 0 0 Bass management crossover frequency 000 70 Hz 001 80 Hz 010 90 Hz 011 100 Hz 100 110 Hz 101 120 Hz 110 140 Hz 111 160 Hz 00000 )- 00010 s ( t c 00011 du 00100 ro 00101 P e 40/63 s b O Rock Soft Rock Jazz Classical Dance Pop 00111 Soft 01000 Hard 01001 Party 01010 Vocal 01011 Hip-Hop 01100 Dialog 01101 Bass-boost #1 01110 Bass-boost #2 01111 Bass-boost #3 10000 Loudness 1 10001 Loudness 2 10010 Loudness 3 10011 Loudness 4 t e l o u d o r P e Flat 00001 00110 ) s ( ct t e l o PEQ[4:0] O D0 XO2 XO[2:0] bs D1 Mode / setting STA308A 7.2.36 Registers 10100 Loudness 5 10101 Loudness 6 10110 Loudness 7 10111 Loudness 8 11000 Loudness 9 11001 Loudness 10 11010 Loudness 11 11011 Loudness 12 11100 Loudness 13 11101 Loudness 14 11110 Loudness 15 11111 Loudness 16 7.2.37 D6 7.2.39 D3 D2 D1 D0 AGEQ4 AGEQ3 AGEQ2 AGEQ1 AGEQ0 0 1 1 1 1 ) (s ct D6 du D5 ro s b O P e D4 D3 D2 D1 D0 BGEQ4 BGEQ3 BGEQ2 BGEQ1 BGEQ0 0 1 1 1 1 CGEQ - graphic EQ 1-kHz band (0x25) t e l o s b O t e l o D4 BGEQ - graphic EQ 300-Hz band (0x24) D7 7.2.38 D5 u d o r P e AGEQ - graphic EQ 80-Hz band (0x23) D7 ) s ( ct D7 D6 D5 D4 D3 D2 D1 D0 CGEQ4 CGEQ3 CGEQ2 CGEQ1 CGEQ0 0 1 1 1 1 DGEQ - graphic EQ 3-kHz band (0x26) D7 D6 D5 D4 D3 D2 D1 D0 DGEQ4 DGEQ3 DGEQ2 DGEQ1 DGEQ0 0 1 1 1 1 41/63 Registers 7.2.40 STA308A EGEQ - graphic EQ 8-kHz band (0x27) D7 D6 D5 D4 D3 D2 D1 D0 EGEQ4 EGEQ3 EGEQ2 EGEQ1 EGEQ0 0 1 1 1 1 xGEQ[4:0] 7.2.41 Boost / cut 11111 +16 11110 +15 11101 +14 … … 10000 +1 01111 0 01110 -1 … … 00001 -14 00000 -15 ) s ( ct u d o r P e t e l o s b O Biquad internal channel loop-through (0x28) D7 D6 C8BLP C7BLP 0 0 ) (s D5 D3 D2 D1 D0 C6BLP D4 C5BLP C4BLP C3BLP C2BLP C1BLP 0 0 0 0 0 0 t c u d o r Each internal processing channel can receive two possible inputs at the input to the biquad block. The input can come either from the output of that channel’s MIX#1 engine or from the output of the bass/treble (Biquad#10) of the previous channel. In this scenario, channel 1 receives channel 8. This enables the use of more than 10 biquads on any given channel at the loss of the number of separate internal processing channels. P e t e l o s b O Bit 7:0 42/63 RW RW RST 0 Name CnBLP Description For n = 1 to 8: 0: input from channel n MIX#1 engine output - normal operation 1: input from channel (n - 1) biquad #10 output - loop operation. STA308A 7.2.42 Registers Mix internal channel loop-through (0x29) D7 D6 D5 D4 D3 D2 D1 D0 C8MXLP C7MXLP C6MXLP C5MXLP C4MXLP C3MXLP C2MXLP C1MXLP 0 0 0 0 0 0 0 0 Each internal processing channel can receive two possible sets of inputs at the inputs to the Mix#1 block. The inputs can come from the outputs of the interpolation block as normally occurs (CnMXLP = 0) or they can come from the outputs of the Mix#2 block. This enables the use of additional filtering after the second mix block at the expense of losing this processing capability on the channel. Bit 7:0 7.2.43 RW RW RST 0 Name For n = 1 to 8: 0: inputs to channel n MIX#1 engine from interpolation outputs - normal operation 1: inputs to channel n MIX#1 engine from MIX#2 engine outputs - loop operation. u d o CnMXLP r P e t e l o EQ bypass (0x2A) D7 D6 ) s ( ct Description D5 s b O D4 D3 D2 D1 D0 C8EQBP C7EQBP C6EQBP C5EQBP C4EQCBP C3EQBP C2EQBP C1EQBP 0 0 0 0 0 0 0 ) (s 0 t c u EQ control can be bypassed on a per channel basis. If EQ control is bypassed on a given channel the prescale and all 10 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combination) are bypassed for that channel. d o r P e Bit let O o s b 7.2.44 7:0 RW RW RST 0 Name Description For n = 1 to 8: 0: perform EQ on channel n - normal operation 1: bypass EQ on channel n. CnEQBP Tone control bypass (0x2B) D7 D6 D5 D4 D3 D2 D1 D0 C8TCB C7TCB C6TCB C5TCB C4TCB C3TCB C2TCB C1TCB 0 0 0 0 0 0 0 0 Tone control (bass/treble) can be bypassed on a per channel basis. If tone control is bypassed on a given channel the two filters that tone control utilizes are made available as user programmable biquads #9 and #10. 43/63 Registers 7.2.45 STA308A Tone control (0x2C) D7 D6 D5 D4 D3 D2 D1 D0 TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0 0 1 1 1 0 1 1 1 This is the tone control boost / cut as a function of BTC and TTC bits. BTC[3:0] / TTC[3:0) Boost / cut 0000 -12 dB 0001 -12 dB … … 0111 -4 dB 0110 -2 dB 0111 0 dB 1000 +2 dB 1001 +4 dB … … 1101 ) (s 1111 let 0 so 7.2.48 s b O t c u +12 dB +12dB D5 D4 D3 D2 D1 D0 C4LS0 C3LS1 C3LS0 C2LS1 C2LS0 C1LS1 C1LS0 0 0 0 0 0 0 0 D6 Channel limiter select channels 5,6,7,8 (0x2E) D7 D6 D5 D4 D3 D2 D1 D0 C8LS1 C8LS0 C7LS1 C7LS0 C6LS1 C6LS0 C5LS1 C5LS0 0 0 0 0 0 0 0 0 Limiter 1 attack/release rate (0x2F) D7 44/63 t e l o d o r P e C4LS1 b O r P e Channel limiter select channels 1,2,3,4 (0x2D) D7 7.2.47 u d o +12 dB 1110 7.2.46 ) s ( ct D6 D5 D4 D3 D2 D1 D0 L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0 0 1 1 0 1 0 1 0 STA308A 7.2.49 Registers Limiter 1 attack/release threshold (0x30) D7 7.2.50 D6 D3 D2 D1 D0 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0 0 1 1 0 1 0 0 1 Limiter 2 attack/release rate (0x31) D6 D5 D4 D3 D2 D1 L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 0 1 1 0 1 0 1 Limiter 2 attack/release threshold (0x32) D7 7.2.52 D4 L1AT3 D7 7.2.51 D5 D6 D5 D4 D2 L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 0 1 1 0 1 0 e t e l L2R0 ) s ( ct 0 u d o Pr D3 D0 D1 D0 L2RT1 L2RT0 0 1 o s b Bit description The STA308A includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in Configuration Register B, bit 7 address 0x02. Each channel can be mapped to either limiter or not mapped, meaning that channel will clip when 0 dBFS is exceeded. Each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then if needed adjust the gain of the mapped channels in unison. O ) s ( t c u d o r P e s b O t e l o The limiter attack thresholds are determined by the LnAT registers. It is recommended in anti-clipping mode to set this to 0 dBFS, which corresponds to the maximum unclipped output power of a DDX amplifier. Since gain can be added digitally within the STA308A it is possible to exceed 0 dBFS or any other LnAT setting, when this occurs, the limiter, when active, will automatically start reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The gain reduction occurs on a peak-detect algorithm. The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The output of the volume/limiter block is passed through a RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the Release Rate register. The gain can never be increased past it's set value and therefore the release will only occur if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound lifeless. 45/63 Registers STA308A In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. Figure 7. Basic limiter and volume flow diagram Limiter RMS Gain/Volume Input Gain Attenuation t e l o Channel has limiting disabled bs 01 Channel is mapped to limiter #1 10 LnA[3:0] du 0001 ete ol s b O 46/63 O ) s ( t c 0000 0100 u d o Channel limiter mapping 00 0011 Saturation r P e CnLS[1,0] 0010 ) s ( ct Output o r P Channel is mapped to limiter #2 Attack rate (dB/ms) 3.1584 (fast) 2.7072 2.2560 1.8048 1.3536 0101 0.9024 0110 0.4512 0111 0.2256 1000 0.1504 1001 0.1123 1010 0.0902 1011 0.0752 1100 0.0645 1101 0.0564 1110 0.0501 1111 0.0451 (slow) STA308A Registers LnR[3:0] Release rate (dB/ms) 0000 0.5116 (fast) 0001 0.1370 0010 0.0744 0011 0.0499 0100 0.0360 0101 0.0299 0110 0.0264 0111 0.0208 1000 0.0198 1001 0.0172 1010 0.0147 1011 0.0137 1100 0.0134 1101 0.0117 1110 0.0110 du 0001 ro 0010 O )- s ( t c 0000 o s b r P e s b O 0.0104 (slow) LnAT[3:0] P e let u d o t e l o 1111 0011 ) s ( ct Anti-clipping (AC) (dB relative to FS) -12 -10 -8 -6 0100 -4 0101 -2 0110 0 0111 +2 1000 +3 1001 +4 1010 +5 1011 +6 1100 +7 1101 +8 1110 +9 1111 +10 47/63 Registers STA308A Anti-clipping (AC) (dB relative to FS) LnRT[3:0] 0000 -∞ 0001 -29 dB 0010 -20 dB 0011 -16 dB 0100 -14 dB 0101 -12 dB 0110 -10 dB 0111 -8 dB 1000 -7 dB 1001 -6 dB 1010 -5 dB 1011 -4 dB 1100 -3 dB 1101 -2 dB -1 dB u d o 0000 e t e ol s b O 48/63 O ) s ( t c LnAT[3:0] 0011 r P e bs 1111 0010 u d o t e l o 1110 0001 ) s ( ct Pr -0 dB Dynamic range compression (DRC) (dB relative to volume) -31 -29 -27 -25 0100 -23 0101 -21 0110 -19 0111 -17 1000 -16 1001 -15 1010 -14 1011 -13 1100 -12 1101 -10 1110 -7 1111 -4 STA308A Registers Dynamic range compression (DRC) (db relative to volume + LnAT) LnRT[3:0] 0000 -∞ 0001 -38 dB 0010 -36 dB 0011 -33 dB 0100 -31 dB 0101 -30 dB 0110 -28 dB 0111 -26 dB 1000 -24 dB 1001 -22 dB 1010 -20 dB 1011 -18 dB 1100 -15 dB 1101 -12 dB -9 dB O ) o r P 1 e t e ol s ( t c du D6 C2OT2 D5 D4 C2OT1 0 D3 D2 D1 D0 C2OT0 C1OT2 C1OT1 C1OT0 0 0 0 0 D2 D1 D0 Channel 3 and 4 output timing (0x34) D7 O 7.2.55 -6 dB Channel 1 and 2 output timing (0x33) D7 bs r P e bs 1111 7.2.54 u d o t e l o 1110 7.2.53 ) s ( ct D6 D5 D4 D3 C4OT2 C4OT1 C4OT0 C3OT2 C3OT1 C3OT0 1 1 0 0 1 0 Channel 5 and 6 output timing (0x35) D7 D6 D5 D4 D2 D1 D0 C6OT2 C6OT1 C6OT0 D3 C5OT2 C5OT1 C5OT0 1 0 1 0 0 1 49/63 Registers 7.2.56 STA308A Channel 7 and 8 output timing (0x36) D7 D6 D5 D4 C8OT2 C8OT1 1 1 D3 D2 D1 D0 C8OT0 C7OT2 C7OT1 C7OT0 1 0 1 1 The centering of the individual channel PWM output periods can be adjusted by the output timing registers. PWM slot settings can be chosen to insure that pulse transitions do not occur at the same time on different channels using the same power device. There are 8 possible settings, the appropriate setting varying based on the application and connections to the DDX power devices. CnOT[2:0] 000 1 001 2 010 3 011 4 100 5 101 6 110 7.2.57 ) (s Pr e t e ol 7.2.59 0 t e l o 8 D5 D4 C2OM1 0 D3 D2 D1 D0 C2OM0 C1OM2 C1OM1 C1OM0 1 0 0 0 Channel I2S output mapping channels 3 and 4 (0x38) D7 D6 D5 D4 D3 D2 D1 D0 C4OM2 C4OM1 C4OM0 C3OM2 C3OM1 C3OM0 0 1 1 0 1 0 Channel I2S output mapping channels 5 and 6 (0x39) D7 50/63 t c u od D6 C2OM2 s b O r P e Channel I2S output mapping channels 1 and 2 (0x37) D7 7.2.58 u d o s b O 7 111 ) s ( ct PWM slot D6 D5 D4 C6OM2 C6OM1 1 0 D3 D2 D1 D0 C6OM0 C5OM2 C5OM1 C5OM0 1 1 0 0 STA308A 7.2.60 Registers Channel I2S output mapping channels 7 and 8 (0x3A) D7 D6 D5 D4 D3 D2 D1 D0 C8OM2 C8M1 C8OM0 C7OM2 C7OM1 C7OM0 1 1 1 1 1 0 Each I2S output channel can receive data from any channel output of the volume block. Which channel a particular I2S output receives is dependent upon that channels CnOM register bits. CnOM[2:0] Serial output from 000 Channel 1 001 Channel 2 010 Channel 3 011 Channel 4 100 Channel 5 101 Channel 6 110 Channel 7 u d o r P e t e l o bs 111 7.2.61 ) s ( ct Channel 8 O ) Coefficient address register 1 (0x3B) D7 s ( t c D6 D5 D4 D3 D2 du 7.2.62 o r P D7 O 7.2.63 D0 CFA9 CFA8 0 0 Coefficient address register 2 (0x3C) e t e ol bs D1 D6 D5 D4 D3 D2 D1 D0 CFA7 CFA6 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0 0 0 0 0 0 0 0 0 Coefficient b1 data register, bits 23:16 (0x3D) D7 D6 D5 D4 D3 D2 D1 D0 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16 0 0 0 0 0 0 0 0 51/63 Registers 7.2.64 7.2.65 STA308A Coefficient b1 data register, bits 15:8 (0x3E) D7 D6 D5 D4 D3 D2 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8 0 0 0 0 0 0 0 0 7.2.67 D6 7.2.70 52/63 D3 D2 D1 C1B5 C1B4 C1B3 C1B2 C1B1 0 0 0 0 0 0 0 Coefficient b2 data register, bits 23:16 (0x40) D6 D5 D4 D3 D2 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 0 0 0 0 0 0 e t e l D4 o s b D3 D2 D0 C1B0 ) s ( ct 0 u d o Pr D7 D1 D0 C2B17 C2B16 0 0 Coefficient b2 data register, bits 15:8 (0x41) D6 D5 (s) -O D1 D0 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8 0 0 0 0 0 0 0 0 t c u Coefficient b2 data register, bits 7:0 (0x42) d o r P e t e l o s b O D4 C1B6 D7 7.2.69 D5 C1B7 D7 7.2.68 D0 Coefficient b1 data register, bits 7:0 (0x3F) D7 7.2.66 D1 D6 D5 D4 D3 D2 D1 D0 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0 0 0 0 0 0 0 0 0 Coefficient a1 data register, bits 23:16 (0x43) D7 D6 D5 D4 D3 D2 D1 D0 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16 0 0 0 0 0 0 0 0 Coefficient a1 data register, bits 15:8 (0x44) D7 D6 D5 D4 D3 D2 D1 D0 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8 0 0 0 0 0 0 0 0 STA308A 7.2.71 Registers Coefficient a1 data register, bits 7:0 (0x45) D7 C3B7 0 D6 7.2.72 C3B6 0 C3B4 0 D3 C3B3 0 D2 C3B2 0 D1 D0 C3B1 0 C3B0 0 D7 D6 D5 D4 D3 D2 D1 D0 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16 0 0 0 0 0 0 0 Coefficient a2 data register, bits 15:8 (0x47) 7.2.74 D6 D5 D4 D3 D2 C4B15 0 C4B14 0 C4B13 0 C4B12 0 C4B11 0 C4B10 0 e t e ol ) s ( ct 0 u d o Pr D7 D1 C4B9 0 D0 C4B8 0 Coefficient a2 data register, bits 7:0 (0x48) D7 D6 C4B7 0 C4B6 0 D5 ) (s C4B5 0 s b O D4 C4B4 0 D3 C4B3 0 D2 C4B2 0 D1 C4B1 0 D0 C4B0 0 t c u 7.2.75 Coefficient b0 data register, bits 23:16 (0x49) D6 D5 D4 D3 D2 D1 D0 C5B23 d o r C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16 0 0 0 0 0 0 0 0 D7 P e let o s b Coefficient b0 data register, bits 15:8 (0x4A) O 7.2.77 C3B5 0 D4 Coefficient a2 data register, bits 23:16 (0x46) 7.2.73 7.2.76 D5 D7 D6 D5 D4 D3 D2 D1 D0 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8 0 0 0 0 0 0 0 0 Coefficient b0 data register, bits 7:0 (0x4B) D7 D6 D5 D4 D3 D2 D1 D0 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0 0 0 0 0 0 0 0 0 53/63 Registers 7.2.78 STA308A Coefficient write control register (0x4C) D7 D6 D5 D4 D3 D2 D1 D0 WA W1 0 0 Coefficients for EQ and Bass Management are handled internally in the STA308A via RAM. Access to this RAM is available to the user via an I2C register interface. A collection of I2C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write of the coefficient(s) to RAM. The following are instructions for reading and writing coefficients. 7.3 1. write top 2-bits of address to I2C register 0x3B 2. write bottom 8-bits of address to I2C register 0x3C 2 r P e 3. read top 8-bits of coefficient in I C address 0x3D 4. read middle 8-bits of coefficient in I2C address 0x3E 5. read bottom 8-bits of coefficient in I2C address 0x3F 1. write top 2-bits of address to I2C register 0x3B 2. write bottom 8-bits of address to I2C register 0x3C 3. read top 8-bits of coefficient in I2C address 0x3D 4. read middle 8-bits of coefficient in I2C address 0x3E 5. read bottom 8-bits of coefficient in I2C address 0x3F 6. read top 8-bits of coefficient b2 in I2C address 0x40 7. read middle 8-bits of coefficient b2 in I2C address 0x41 8. read bottom 8-bits of coefficient b2 in I2C address 0x42 9. read top 8-bits of coefficient a1 in I2C address 0x43 t e l o s b Reading a set of coefficients O from RAM ) s ( t c u d o r P e t e l o s b 10. read middle 8-bits of coefficient a1 in I2C address 0x44 11. read bottom 8-bits of coefficient a1 in I2C address 0x45 12. read top 8-bits of coefficient a2 in I2C address 0x46 13. read middle 8-bits of coefficient a2 in I2C address 0x47 14. read bottom 8-bits of coefficient a2 in I2C address 0x48 15. read top 8-bits of coefficient b0 in I2C address 0x49 16. read middle 8-bits of coefficient b0 in I2C address 0x4A 17. read bottom 8-bits of coefficient b0 in I2C address 0x4B 54/63 u d o Reading a coefficient from RAM 7.4 O ) s ( ct STA308A 7.5 Registers 7.6 Writing a single coefficient to RAM 1. write top 2-bits of address to I2C register 0x3B 2. write bottom 8-bits of address to I2C register 0x3C 3. write top 8-bits of coefficient in I2C address 0x3D 4. write middle 8-bits of coefficient in I2C address 0x3E 5. write bottom 8-bits of coefficient in I2C address 0x3F 6. write 1 to W1 bit in I2C address 0x4C Writing a set of coefficients to RAM 1. write top 2-bits of starting address to I2C register 0x3B 2. write bottom 8-bits of starting address to I2C register 0x3C 3. write top 8-bits of coefficient b1 in I2C address 0x3D 4. write middle 8-bits of coefficient b1 in I2C address 0x3E 5. write bottom 8-bits of coefficient b1 in I2C address 0x3F 6. write top 8-bits of coefficient b2 in I2C address 0x40 7. write middle 8-bits of coefficient b2 in I2C address 0x41 8. write bottom 8-bits of coefficient b2 in I2C address 0x42 9. write top 8-bits of coefficient a1 in I2C address 0x43 ) s ( ct u d o r P e t e l o s b O 10. write middle 8-bits of coefficient a1 in I2C address 0x44 11. write bottom 8-bits of coefficient a1 in I2C address 0x45 ) (s 12. write top 8-bits of coefficient a2 in I2C address 0x46 13. write middle 8-bits of coefficient a2 in I2C address 0x47 t c u 14. write bottom 8-bits of coefficient a2 in I2C address 0x48 d o r 15. write top 8-bits of coefficient b0 in I2C address 0x49 16. write middle 8-bits of coefficient b0 in I2C address 0x4A P e 17. write bottom 8-bits of coefficient b0 in I2C address 0x4B t e l o 18. write 1 to WA bit in I2C address 0x4C s b O The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 10-bit address would specify the address of the biquad b1 coefficient (for example, decimals 0, 5, 10, 15, …, 100, … 395), and the STA308A will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data. 55/63 Equalization and mixing 8 STA308A Equalization and mixing Figure 8. Channel mixer CxMIX1 Channel 1 CxMIX2 Channel 2 CxMIX3 ) s ( ct Channel 3 CxMIX4 Channel x Channel 4 u d o CxMIX5 Channel 5 r P e CxMIX6 Channel 6 t e l o CxMIX7 Channel 7 s b O CxMIX8 Channel 8 8.1 Post-scale ) (s t c u d o r The STA308A provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiply. P e t e l o s b O The scale factor for this multiply is loaded into RAM using the same I2C registers as the biquad coefficients and the bass-management. This post-scale factor can be used in conjunction with an ADC equipped micro-controller to perform power-supply error correction. All channels can use the channel 1 by setting the post-scale link bit. Table 9. 56/63 RAM block for biquads, mixing, and bass management Index Index (decimal) (hex) 0 0x00 1 Coefficient Channel 1 - Biquad 1 Default C1H10 (b1/2) 0x000000 0x01 C1H11 (b2) 0x000000 2 0x02 C1H12 (a1/2) 0x000000 3 0x03 C1H13 (a2) 0x000000 STA308A Equalization and mixing Table 9. RAM block for biquads, mixing, and bass management (continued) Index Index (decimal) (hex) 4 0x04 5 0x05 … 0x400000 Channel 1 - Biquad 2 C1H20 0x000000 … … … … 49 0x31 Channel 1 - Biquad 10 C1HA4 0x400000 50 0x32 Channel 2 - Biquad 1 C2H10 0x000000 51 0x33 C2H11 0x000000 … … … … 99 0x63 Channel 2 - Biquad 10 C2HA4 100 0x64 Channel 3 - Biquad 1 C3H10 … … … … 399 0x18F Channel 8 - Biquad 10 C8HA4 400 0x190 Channel 1 - Pre-Scale 401 0x191 Channel 2 - Pre-Scale 402 0x192 Channel 3 - Pre-Scale … … … 407 0x197 408 0x198 409 0x199 … ete ) s ( ct … 0x4000000 o r P du 0x000000 … 0x400000 C1PreS 0x7FFFFF C2PreS 0x7FFFFF C3PreS 0x7FFFFF … … Channel 8 - Pre-Scale C8PreS 0x7FFFFF Channel 1 - Post-Scale C1PstS 0x7FFFFF Channel 2 - Post-Scale C2PstS 0x7FFFFF du … … … 0x19F Channel 8 - Post-Scale C8PstS 0x7FFFFF 0x1A0 Channel 1 - Mix#1 1 C1MX11 0x7FFFFF 417 0x1A1 Channel 1 - Mix#1 2 C1MX12 0x000000 … … … … … 423 0x1A7 Channel 1 - Mix#1 8 C1MX18 0x000000 424 0x1A8 Channel 2 - Mix#1 1 C2MX11 0x000000 425 0x1A9 Channel 2 - Mix#1 2 C2MX12 0x7FFFFF … … … … … 463 0x1CF Channel 8 - Mix#1 8 C8MX18 0x7FFFFF 464 0x1D0 Channel 1 - Mix#2 1 C1MX21 0x7FFFFF 465 0x1D1 Channel 1 - Mix#2 2 C1MX22 0x000000 … … … … … 471 0x1D7 Channel 1 - Mix#2 8 C1MX28 0x000000 472 0x1D8 Channel 2 - Mix#2 1 C2MX21 0x000000 473 0x1D9 Channel 2 - Mix#2 2 C2MX22 0x7FFFFF … ro P e 416 t e l o O Default C1H14 (b0/2) 415 bs Coefficient )- s b O ol s ( t c 57/63 Equalization and mixing Table 9. STA308A RAM block for biquads, mixing, and bass management (continued) Index Index (decimal) (hex) Coefficient Default … … … … … 527 0x20F Channel 8 - Mix#2 8 C8MX28 0x7FFFFF 8.2 Variable max power correction 8.2.1 MPCC1-2 (0x4D, 0x4E) ) s ( ct u d o MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. D7 D6 D5 D4 D3 D1 D0 t e l o MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8 0 0 1 0 1 1 0 1 D7 D6 MPCC7 MPCC6 1 1 D5 t c u 0 D3 D2 D1 D0 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0 0 0 0 0 0 ) (s MPCC5 s b O D4 d o r 8.3 Variable distortion compensation 8.3.1 DCC1-2 (0x4F, 0x50) P e t e l o s b O DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1. D7 D6 D5 D4 D3 D2 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8 1 1 1 1 0 0 1 1 D7 58/63 r P e D2 D6 D5 D4 D3 D1 D2 D0 D1 D0 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0 0 0 1 1 0 0 1 1 STA308A 8.4 Equalization and mixing PSCorrect registers ADC is used to input ripple data to SDI78. The left channel (7) is used internally. No audio data can therefore be used on these channels. Though all channel mapping and mixing from other inputs to channels 7 and 8 internally are still valid. 8.4.1 PSC1-2: ripple correction value (RCV) (0x51, 0x52) Equivalent to negative maximum ripple peak as a percentage of Vcc (MPR), scaled by the inverse of maximum ripple p-p as percentage of full-scale analog input to ADC. Represented as a 1.11 signed fractional number. D7 D6 RCV11 RCV10 RCV9 RCV8 RCV7 RCV6 RCV5 0 0 0 0 0 0 0 D7 8.4.2 D5 D6 D4 D5 D3 D4 D2 D3 D2 u d o r P e RCV3 RCV2 RCV1 RCV0 CNV11 CNV10 0 0 0 0 1 1 t e l o ) s ( ct D1 D0 RCV4 0 D1 D0 CNV9 CNV8 1 1 PSC3: correction normalization value (CNV) (0x53) s b O Equivalent to 1 / (1+MPR) expressed as a 0.12 unsigned fractional number. D7 D6 CNV7 CNV6 1 1 D5 u d o s ( t c )- CNV5 1 D4 D3 D2 D1 D0 CNV4 CNV3 CNV2 CNV1 CNV0 1 1 1 1 1 r P e t e l o s b O 59/63 Package information 9 STA308A Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 9. TQFP64 (10 x 10 x 1.4mm) mechanical data and package dimensions mm inch DIM. MIN. TYP. MAX. A 0.05 0.006 1.35 1.40 1.45 0.053 B 0.17 0.22 0.27 0.0066 0.0086 0.0106 C 0.09 D 11.80 12.00 12.20 0.464 0.472 0.480 D1 9.80 10.00 10.20 0.386 0.394 0.401 0.055 u d o 0.057 r P e 0.0035 D3 7.50 0.295 e 0.50 0.0197 E 11.80 12.00 12.20 0.464 E1 9.80 10.00 10.20 0.386 7.50 L 0.45 0.472 0.480 0.394 0.401 t e l o s b O 0.295 0.60 )- 0.75 1.00 0.0177 0.0236 0.0295 0.0393 s ( t c K TQFP64 (10 x 10 x 1.4mm) 0˚ (min.), 3.5˚ (min.), 7˚(max.) ccc 0.080 u d o O 0.002 A2 L1 r P e ) s ( ct OUTLINE AND MECHANICAL DATA MAX. 0.063 0.15 E3 0.0031 D D1 A D3 A2 A1 48 33 49 32 0.08mm ccc B Seating Plane E E1 E3 B o s b TYP. 1.60 A1 let MIN. 17 64 1 16 C L L1 e K TQFP64 0051434 E 60/63 STA308A 10 Trademarks and other acknowledgements Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. ECOPACK is a registered trademark of STMicroelectronics. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 61/63 Revision history 11 STA308A Revision history Table 10. Document revision history Date Revision May-2004 1 Initial release. Nov-2005 2 Changed in page 4 value Tamb and Tj. June-2006 3 Changed in Figure 4 and Table 2 the name of the pins 22 and 24. 4 Updated cover page Added chapter 6, Application reference schematic Removed reserved registers from chapter 7 Updated register descriptions in chapter 7 Various minor changes. July-2007 Changes u d o ) s ( ct r P e t e l o ) (s t c u d o r P e t e l o s b O 62/63 s b O STA308A ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. 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