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STA310

STA310

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    LQFP80

  • 描述:

    IC AUDIO DECODER 6+2CH 80-TQFP

  • 数据手册
  • 价格&库存
STA310 数据手册
CD00003411 Rev 1.3 IN APPROVAL PAGE A ft 6+2-Ch. multistandard audio decoder Technical Literature ) s ( ct u d o ra r P e -D t e l o s b O Alternate Identifier(s) ) (s t c u ISO Definition od b O Product Development Specification Public Document Type Technical Literature Document Category Datasheet Dr a so let ft - Confidentiality Level r P e 9622 Dr Key process aft CUSTOM ATTRIBUTES Document Family Original ID Original Repository Status IN APPROVAL Responsible Keywords Technical Literature, 9622, Product Development, Specification, Datasheet, STA310, NOTICE: This document may have been revised since it was printed. Check Document Control System for latest version before using or copying. © Copyright STMicroelectronics. Unauthorized reproduction and communication strictly prohibited. CD00003411 Rev 1.3 IN APPROVAL PAGE B DOCUMENT HISTORY Version Rev 1.3 Release Date Change Qualifier 11-Jun-2013 Properties Changes ft AUTOMATIC OBSOLETE RPN WORKFLOW STARTED ) s ( ct u d o ra r P e -D t e l o t e l o s b O aft ft - P e Dr a d o r Dr ) (s t c u s b O NOTICE: This document may have been revised since it was printed. Check Document Control System for latest version before using or copying. © Copyright STMicroelectronics. Unauthorized reproduction and communication strictly prohibited. CD00003411 Rev 1.3 IN APPROVAL PAGE C DOCUMENT APPROVAL Function Date Camilleri Evelina Document Controller ft User ) s ( ct 12-Jun-2013 u d o ra r P e -D t e l o t e l o s b O aft ft - P e Dr a d o r Dr ) (s t c u s b O NOTICE: This document may have been revised since it was printed. Check Document Control System for latest version before using or copying. © Copyright STMicroelectronics. Unauthorized reproduction and communication strictly prohibited. Document CD00003411 1.3 Revision IN APPROVAL 4 / 93 STA310 6+2-CH. MULTISTANDARD AUDIO DECODER PRELYMINARY DATA ■ ■ ■ ■ ■ ■ ■ ) (s t c u d o r t e l o s b O ■ ■ ■ ■ ■ ■ ■ ■ ■ P e ft ra r P e t e l o -D ■ u d o ■ 2.5V (for core) and 3V (for I/O) power supply. ❚ 3V Capable I/O Pads . True-SPDIF input receiver supporting AES/ EBU, IEC958, S/PDIF. ❚ No external chip required. ❚ Differential or single ended inputs can be decoded. s b O ■ aft ■ ) s ( ct TQFP80 ORDERING NUMBER: STA310 Dr ■ DVD Audio decoder: ❚ Meridian Lossless Packing (MLP), with up to 6 channels, ❚ Uncompressed LPCM with 1-8 channels, ❚ Precision of up to 24 bits and sample rates of between 44.1 kHz and 192 kHz. Dolby Digital (*) decoder: ❚ Decodes 5.1 Dolby Digital Surround. ❚ Output up to 6 channels. downmix modes: 1, 2, 3 or 4 channels. MPEG -1 2- channel audio decoder, layers I and II. MPEG-2 6-channel audio decoder, layer II. ❚ 24 bits decoding precision. MP3 (MPEG layer III) decoder. Accepts MPEG-2 PES stream format for: MPEG-2, MPEG-1, Dolby Digital and linear PCM. Karaoke System. Prologic decoder. Downmix for Dolby Prologic compatible. ❚ A separate (2-ch) PCM output available for simultaneous playing and recording. Bitstream input interface: serial, parallel or SPDIF. SPDIF and IEC-61937 input interface. SPDIF and IEC-61937 output interface. PLL for internal PCM clock generation. frequencies supported: 44.1KHz family (22.05, 88.2, 176.4) and 48KHz family (24, 48, 96, 192). PCM: transparent, downsampling 192 to 96 Khz and 96 to 48kHz. PTS handling control on-chip. No external DRAM required I2C or parallel control bus Embedded Development RAM for customizable software capability. Configurable internal PLLs for system and audio clocks, from an externally provided clock. 80-PIN TQFP package ft - ■ FEATURES Dr a 1 APPLICATIONS ■ High-end audio equipment. ■ DVD consumer players. ■ Set top box. ■ HDTV . ■ Multimedia PC. (*) “Dolby “, “AC-3” and “ProLogic” are trademarks of Dolby Laboratories. DESCRIPTION The STA310 is a fully integrated Audio Decoder capable of decoding all the above listed formats. Encoded input data can be entered either by a serial (I2S or SPDIF) or a parallel interface. A second input data stream (I2S) is available for micro input. The control interface can be either I2C or a parallel 8bit interface. No external DRAM is necessary for a total of 35ms surround delays. June 2003 1/90 This is preliminary information on a new product now in development. Details are subject to change without notice. Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 5 / 93 STA310 2 STA310 AUDIO DECODER PIN DESCRIPTION Pin Number Name Type Function CONTROL INTERFACES 48 IRQB O (1) Interrupt Signal (level), active low 47 SELI2C I (2) Selects the Control Interface (when high: serial interface; when low: parallel interface) I 2C Control Interface 43 SDAI2C I/O (1) 46 SCLKI2C I 53 MAINI2CADR I 2C Serial Data ) s ( ct I 2C Clock I (2) Determines the slave address Host Data u d o ft Parallel Control Interface r P e D0 - D1 - D2 - D3 D4 - D5 - D6 - D7 I/O 12 - 13 - 14 - 15 16 - 18 - 19 - 20 A0 - A1 - A2 - A3 A4 - A5 - A6 - A7 I Host Address 21 DCSB I Chip Select, active low 22 R/W I Read/Write Selection: read access when high, write access when low 35 WAITB 41 SIN ete Pr LRCLKIN ol 42 s b O REQ I Dr a 40 od -D aft s b O Data Acknowledge, active low Clock Input Data, active low ft - DSTRB t e l o Dr t c u First Serial Data Interface (I2S) 37 ) (s O (3) DATA INPUT INTERFACE ra 78 - 79 - 80 - 1 2-3-6-7 I Serial Input Data I Word Clock for the Input O Handshake for the Data Transfer, aconfigurable by the SIN_SETUP register Second Serial Data Interface (I2S) 62 DSTRB2 I Clock Input Data, active low 60 SIN2 I Serial Input Data 61 LRCLKIN2 I Word Clock for the Input 63 REQ2 O Handshake for the Data Transfer, active low PCMCLK I/O Oversampling Clock input for STA310 when generated externally SCLK O Bit Clock for the DAC DATA OUTPUT INTERFACES 69 DAC Interface 67 2/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 6 / 93 STA310 2 STA310 AUDIO DECODER PIN DESCRIPTION (continued) Pin Number Name Type Function 68 LRCLK O Word Clock for the DAC 72 PCM_OUT0 O Data from a Prologic downmix (VCR_L/VCR_R) 73 PCM_OUT1 O Data for the first DAC (Left/Right) 76 PCM_OUT2 O Data for the second DAC (Centre/Sub) 77 PCM_OUT3 O Data for the third DAC (LeftSur/RightSur) IEC958 Interface (S/PDIF) - One Output Port., One Input Ports. I958OUT O S/PDIF Signal 25 SPDP I First differential input of S/P DIF port 24 SPDN I Second differential input of S/P DIF port 26 SPDF I External Filter 28 VDDA I Analog VDD for S/P DIF Input port 29 GNDA I Analog GND for S/P DIF Input port ft 58 t c u od 57 DEEMPH r P e Audio Video Synchronization t e l o Other Signals bs 31 O PTSB CLK O Dr a 59 O ra -D Then high, indicates that the sampling freq. is either 44.1Khz or 22.05Khz. When low, indicates that the sampling frequency is either 32 Khz, 48 Khz, 24 Khz or 16Khz. Dr O s b O aft ) (s SFREQ r P e Indicates if de-emphasis is performed. ft - 54 u d o t e l o STATUS INFORMATION PCM Related Information I Indicates that a PTS has been detected, active low. Master Clock Input Signal. I(2) Reset signal input, active low. TESTB I(2) Reserved pin: to be connected to VDD SMODE I Reserved pin : to be connected to GND 8 RS232RX I 9 RS232TX O 36 RESET 52 49 ) s ( ct RS232 Interface PLLs INTERFACES 64 CLKOUT O System clock output with programmable division ratio 27 PLLAF I External Filter For Audio PLL. 3/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 7 / 93 STA310 2 STA310 AUDIO DECODER PIN DESCRIPTION (continued) Pin Number 30 Name Type PLLSF Function I External Filter For System PLL. Power and Ground 5 - 11 - 23 - 33 39 - 45 - 50 - 56 - 66 - 71 - 75 GND GND Ground 4 - 17 - 34 - 38 44 - 55 - 65 - 74 VDD VDD 2.5V Power Supply 10 - 32 - 51 - 70 VDD3 VDD3 3.3V Power Supply LRCLKIN2 DSTRB2 VDD CLKOUT SCLK s b O REQ2 ra r P e t e l o -D LRCLK PCMCLK VDD3 GND PCM_OUT0 PCM_OUT1 VDD GND PCM_OUT2 PCM_OUT3 D0 D1 PIN CONNECTION (Top view) D2 u d o ft (1) Open Drain (2) Internal Pull-up (3) Tri-State GND Notes ) s ( ct D5 3 VDD 4 GND 5 D6 6 D7 7 ete RS232RX 8 RS232TX 9 ol bs O )- t(s Dr 2 c u d o r P ft - 1 D4 Dr a D3 aft 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 SIN2 59 PTSB 58 I958OUT 57 DEEMPH 56 GND 55 VDD 54 SFREQ 53 MAINI2CADD 52 TESTB 51 VDD3 50 GND 49 SMODE 48 IRQB VDD3 10 GND 11 A0 12 A1 13 A2 14 47 SELI2C A3 15 46 SCLKI2C A4 16 45 GND VDD 17 44 VDD A5 18 43 SDAI2C A6 19 42 REQ A7 20 41 SIN LRCKLIN VDD GND DSTRB WAITB HRSTB VDD GND CLK VDD3 PLLSF VDDA GNDA PLLAF SPDF SPDP SPDN GND DCSB HRWB 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D00AU1225 4/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 8 / 93 STA310 ABSOLUTE MAXIMUM RATINGS Symbol Vdd Vdd3 Parameters Value Unit 2.5V Power Supply Voltage -0.5 to 3.3 V 2.5V Input or Output Voltage -0.5 to (Vdd+0.5) V 3.3V Power Supply Voltage -0.5 to 4 V 3.3V Input or Output Voltage -0.5 to (Vdd+0.5) V ELECTRICAL CHARACTERISTICS (VDD = 3.3V +/-0.3V; Tamb = 0 to 70°C; Rg = 50 Ω unless otherwise specified ) s ( ct DC OPERATING CONDITIONS Symbol Power Supply Voltage Operating Junction Temperature e t e ol -D GENERAL INTERFACE Symbol Parameters Iil Low level input current without pull-up device Vi = 0V Iih High level input current without pull-down device Vi = Vdd Ioz Tri-state output leakage without pull-up/down device Vi = 0V or Vdd I/O Latch-up current VVdd Leakage 0, when the audio parser has detected one synchro word, it waits until it detects n supplementary audio sync words. 59/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 63 / 93 STA310 Description: Bitfield 9.14 Post decoding and pro logic registers PDEC1 Description PL_AB When high, select the auto-balance function (used to track out gin mismatches between Lt and Rt).When low, disable the autobalance function PL_WS When high, enable Wide Surround mode. The wide surround option is provided for users who plan to do further postprocessing of the Pro Logic outputs, and want to fold the lowpass filtering of the surround channel into their downstream processing Lowpass filtering and B-type shelf filtering are both disabled. When low, disable ide surround mode. Post decoder register 7 6 5 VMAX 4 3 2 1 0 DEM DCF DB PVIRT MPEG_DR PL Address: 0x62 Type: R/W Software Reset: NC PL_DWNX Hardware Reset: UND PL When high Pro Logic decoding is forced, when low the ProLogic decoder is automatically enabled when the stream contains the info that it is ProLogic encoded du When set the DC filter is activated.. When reset, it is disabled. When set the de-emphasis filter is activated.. When reset, it is disabled. PL_AB 6 5 4 3 LFE_BYP 1 0 PL_DWNX[2:0] Software Reset: NC Hardware Reset: UND Description: Bitfield Description PL_DWNX [2:0] 0,1,2: Pro Logic disabled 3: 3/0 (L, R, C) three stereo 4: 2/1 (L, R, Ls) phantom 5: 3/1 (L, C, R, Ls) 6: 2/2 (L, R, Ls, Rs) phantom 7: 3/2 (L, C, R, S, S) LFE_BYP 0: LFE channel is clear 1: LFE channel is bypassed Prologic decoder support only 4 sampling frequencies: 48KHz, 44.1KHz, 32KHz, 22.05KHz. If we active prologic with sampling frequency different from those frequencies, the decoder will be automatically disable the prologic call. Pro Logic auto balance 7 2 aft Dr a ft - When high the "double stereo" procedure is enabled. Double stereo is a copy of Left/Right channels on to Left/Right surround channels in order to have a pseudo 5 -channel decoder effect. t e l o 4 -O MPEG_DR When high enable MPEG dynamic range. P e let o s b Dr ) s ( ct DEM 3 r P e -D Description ro 6 Address : 0x65 Type: R/W Bitfield s b O 5 ra 7 This register controls the post decoder operations. DCF u d o Pro Logic Decoder Downmix Description: DB ) s ( ct ft When it has detected (SYNC_LOCK+1) sync words, it sends the data to the decoder. 2 1 0 PL_WS PL_AB OCFG Output Configuration Address : 0x64 Type: R/W 7 Software Reset: NC 6 5 LFE_BYP BOOST Hardware Reset: UND 4 3 2 1 0 OCFG[2:0] Address: 0x66 60/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 64 / 93 STA310 Type: RW The description is provided in the output configuration section. Software Reset: NC This register is used to indicate the output configuration chosen. - LP means Low pass filter Hardware Reset: UND Description: - HP means High pass filter 6 output configurations are provided that redirects bass on subwoofer channel, and applies some filters on channels. conf Meaning OCFG[2:0] Bass management configuration according to the bass direction scheme from Dolby. For configurations 2,3,4 the subwoofer can be output is bit LFE asset to high. For all other configurations, the LFE bit has no effect. All channels are rounded according to the selected output precision, (24b -> 16b, 24 -> 18b.) and scaled (volume control) only. 1 LSW Low frequencies are extracted from the six input channels and redirected to the subwoofer. SUB = LP(L+R+Ls+Rs+C+LFE).Low frequencies are removed from all channels L = HP(L), R = HP(R), C = HP(C), Ls = HP(Ls), Rs = HP(Rs). 2 LLR Low frequencies are extracted from C, LFE, Ls and Rs channels and redirected to left and right channels: C = HP (C), Rs = HP (Rs), Ls = HP(Ls), L = L + LP (C+LFE+Ls+Rs), R = R + LP(C+LFE+Ls+Rs). If subwoofer is output, SUB = LP (LFE+C+Ls+Rs). 3(1) SLP Low frequencies are redirected to the left, right and surround channels or cab be output on the subwoofer. If sub-woofer is output, SUB = LFE, L = L + LP(C), R = R + LP(C), Ls = Ls, Rs = Rs If sub-woofer is not output, L = L + LP(C) + LFE, R = R + LP(C) + LFE, Ls = Ls + LFE, Rs = Rs + LFE. SIMP 5 BYP ra r P e -D t e l o s b O aft ) (s t c u Simplified configuration. Low frequencies are exrtacted from C, Ls, Rs and LFE. If subwoofer is output, SUB = LP(C+Ls+Rs) + LFE, L = L, R = R. If sub-woofer is not output, SUB = LFE, L = L + (C+Ls+Rs), R = R + (C+Ls+Rs). d o r P e u d o Dr 4 ft ALL t e l o BYPASS, All channels are directly routed to PCM outputs. configuration 1 without filters. Channel level, enables boost: if OCFG_num = 2 : 0 : No +12dB boost on left and right channels 1 : +12dB boost on left and right channels Dr a s b O ) s ( ct 0 6 BOOST(1) Description ft - Bitfield When configuration = 3 : If sub-woofer is output : 0 : No +4dB boost on all channels 1 : +4dB boost on all channels If sub-woofer is not output : 0 : No +8dB boost on all channels 1 : +8dB boost on all channels LFE_BYOP 0; LFE channel is clear 1: LFE channel is bypassed Note: 1. In configuration 3 with subwoofer enabled, the output of the subwoofer is 10dB greater than expected. Therefore when using this mode, the subwoofer output level needs to be attenuated 10dB in order to match the subwoofer output levels of other bass management configurations. In general be carefull while using the boost option since it has the potential of causing the woofer output to overload DWSMODE 61/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 65 / 93 STA310 7 6 5 ■ 4 3 2 1 0 ■ Address: 0x70 ■ Type: R/W Software Reset: NC Hardware Reset: UND ■ This register controls the downsampling filter for the LPCM video, LPCM audio modes. When decoding a 96kHz DVD-LPCM stream, it might be necessary to downsample the stream to 48kHz. Value ■ Volume of second channel Mode 7 Automatic (according to bitstream) 1 Force Downsampling 2 Suppress Downsampling 6 r P e 5 4 let -D 0 ) s ( ct u d o VOLUME1 ft Description: If CHAN_IDX = 2, then VOLUME0 can be written with the attenuation that will be applied to Left Surround channel. If CHAN_IDX = 5, then reading VOLUME0 provides the attenuation that is applied to Left channel. If CHAN_IDX = 6, then reading VOLUME0 provides the attenuation that is applied to Center channel. If CHAN_IDX = 7, then reading VOLUME0 provides the attenuation that is applied to Left Surround channel. Other values of CHAN_IDX are reserved. ra Downsampling filter o s b 3 2 1 0 AVol1 Address: 0x63 Type: RWS Software Reset: 0 aft O ) Hardware Reset: UND 6 5 e t e ol o r P 4 Address: 0x4E s b O Type: RWS Software Reset: 0 Hardware Reset: UND 3 AVol0 2 1 0 Dr a 7 du Description: ft - Volume of first channel Dr s ( t c 9.15 Bass redirection registers VOLUME0 Description: This register reads or writes the attenuation that is applied to the channel selected by CHAN_IDX. The volume of the left channel can be set up with a 0.5dB step. ■ If CHAN_IDX = 0, then VOLUME0 can be written with the attenuation that will be applied to Left channel. ■ If CHAN_IDX = 1, then VOLUME0 can be written with the attenuation that will be applied to Center channel. This register reads or writes the attenuation that is applied to the channel selected by CHAN_IDX. The volume of the right channel can be set up with a 0.5dB step. ■ If CHAN_IDX = 0, then VOLUME1 can be written with the attenuation that will be applied to Right channel. ■ If CHAN_IDX = 1, then VOLUME1 can be written with the attenuation that will be applied to Subwoofer channel. ■ If CHAN_IDX = 2, then VOLUME1 can be written with the attenuation that will be applied to Right Surround channel. ■ If CHAN_IDX = 5, then reading VOLUME1 provides the attenuation that is applied to Right channel. ■ If CHAN_IDX = 6, then reading VOLUME1 provides the attenuation that is applied to Subwoofer channel. ■ If CHAN_IDX = 7, then reading VOLUME1 provides the attenuation that is applied to Right Surround channel. ■ Other values of CHAN_IDX are reserved. 62/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 66 / 93 STA310 and CHAN_IDX value is automatically changed to 4. CHAN_IDX Channel Index 7 6 5 4 3 2 Reserved 1 0 9.16 Dolby Digital configuration registers AC3_DECODE_LFE CHAN_IDX Address: 0x67 Decode LFE Type: R/W 7 Software Reset: 4 6 5 4 3 2 1 Hardware Reset: UND 0 Address: 0x68 Type: R/W Description: This register identifies the pair of channels and the type of access: 1 Center and Subwoofer 2 Left surround write and right surround ■ ■ ft Description: t e l o When this register is set to 1, the device decodes LFE channel (if present). write no pair selected du 5 Left and Right read 6 Center and Subwoofer 7 Left surround read and right surround aft 4 Compression mode Dr reserved P e )- s ( t c reserved ro s b O AC3_COMP_MOD 3 none r P e ra Left and Right write comment -D 0 t e l o s b O Access Indicates that volume can be read or written ft - CHAN_I DX value Channel pair Dr a Bitfield u d o Software Reset: NC Hardware Reset: UND ) s ( ct 7 6 5 4 3 2 1 0 Address + 0x69 Type: R/W Software Reset: NC Hardware Reset: UND read To read a volume, the register CHAN_IDX must be set to the appropriate value. The DSP indicates that the attenuation is readable through registers VOLUME0 and VOLUME1 by changing automatically the CHAN_IDX to value 4. To write a volume, the attenuation of the pair of channel should be written in VOLUME0 and VOLUME1 registers. Then the CHAN_IDX register is written to the appropriate value. The attenuation is updated on the next audio block Description: The value of this register defines the compression mode. In custom A mode, the dialog normalization function is not done by the audio decoder, it has to be done by an external analog part. In all other modes the normalization is done by audio decoder. Value Meaning 0 Custom A (Analog) 1 Custom D (Digital) 2 Line Out 3 RF Mode 63/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 67 / 93 STA310 AC3_HDR level signals amplification is maximum. High dynamic range A value of zero disables the low-level amplification. This word is ignored if the compression mode is set to RF mode. 7 6 5 4 3 2 1 0 AC3_RPC Address: 0x6A Type: R/W Repeat count 7 Software Reset: NC 6 5 4 3 2 1 0 Hardware Reset: UND Type: R/W This register corresponds to the Dynamic range scale factor for high level signals, also called cut factor in the Dolby specifications. ft Hardware Reset: UND 6 5 e t e ol Address : 0x6B bs Type: R/W Software Reset: NC O 3 2 ra This register specifies the number of audio blocks to repeat before muting. If this is zero, then blocks are muted until the next frame is decoded AC3_KARAMODE Dr o r P 4 ft - du s b O 1 Karaoke downmix 7 6 5 4 3 2 1 0 0 Dr a Low dynamic range ) (s ct AC3_LDR t e l o When a CRC error is detected, previous blocks can be repeated or muted. aft A value of zero disables the high-level compression. This word is ignored if the compression mode is set to RF mode. r P e Description: -D When HDR = 0xff (cut factor = 1.0), the high level signals reduction is the one given in the stream. u d o Software Reset: NC HDR = 255 * Cut Factor (in decimal), where the cut factor is a fractional number between 0 and 1. It is used to scale the dynamic range control word for high-level signals that would otherwise tend to be reduced. 7 ) s ( ct Address + 0x6C Description: AudioBaseAddress + 0x6D Type: R/W Software Reset: NC Hardware Reset: UND Hardware Reset: UND Description: Description: Downmix mode when a karaoke bit stream is received. This register corresponds to the Dynamic range scale factor for low level signals, also called boost factor in the Dolby specifications. A Karaoke bitstream can be composed of 5 channels, which are: L (left), R (right), M (Music), V1(Vocal 1), V2 (Vocal 2). LDR = 255 * BoostFactor (in decimal), where the boost factor is a fractional number between 0 and 1.0. The boost factor scales the dynamic range control-word for low-level signals that would otherwise tend to be amplified. There are two major modes when receiving a Karaoke bitstream: aware and capable. When LDR = 0xff (boost factor = 1.0), and the low When in 'aware' mode ( KARAMODE = 0), a predefined downmix is applied on all incoming channels. When in 'capable' mode ( KARAMODE = 4, 5, 6, 7), the user can choose to reproduce or not the two in- 64/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 68 / 93 STA310 coming vocal channels, V1 and V2. when in 2/0 output mode or when receiving a “Dual mode” incoming bitstream (example: A disk with 2 different languages on channel 1 and channel 2). In the following table, channel 1 and 2 represent the output channels after downmix performed with AC3_DOWNMIX. An additional mode is added ( AC3_KARAMODE = 3) to allow multi-channel reproduction. In this case, the downmix specified by the AC3_DOWNMIX and AC3_DUALMODE registers is applied. The following table summaries the different modes: Comment Aware Left = L + clev*M + slev*V1, Right = R + clev*M + slev*V2 1 Not used 2 Not used Multicha Consider bitstream as multi-channel: nnel Perform downmix according to DOWNMIX and DUALMODE registers 4 Capable Do not reproduce V1, V2: Left = L + clev*M, Right = R + clev*M 5 ) (s Reproduction V1, V2: Left = L + clev*M + V1, Right = R + clev*M + V2 O Dual downmix 7 6 5 4 ft - 3 2 Output Channel 2 on both output L/R 3 Mix Channel 1 and 2 to monophonic and output on both L/R u d o r P e t e l o 6 ) s ( ct 5 4 3 2 1 0 s b O Dr a o s b AC3_DUALMODE 2 7 slev = Surround Mix Level (value provided in the bitstream). For further information ref. to annex C of ATSC standard “Digital Audio Compression (AC-3)”. let Output Channel 1 on both output L/R Address: 0x6F Type: R/W Software Reset: NC Dr ct r P e 1 Downmix Left = Output Channel, Right = Output Channel, L, R, M, V1, V2 = Input Channels (coded in Dolby Digital karaoke bitstream), clev = Center Mix Level (value provided in the bitstream), u d o Output as Stereo aft Reproduction V2 only: Left = L + clev*M + 0.707*V2, Right = R + clev*M + 0.707V2 7 0 AC3_DOWNMIX Reproduction V1 only: Left = L + clev*M + 0.707*V1, Right = R + clev*M + 0.707V1 6 Description ft 3 Value ra 0 Mode -D Value This register enables Mono downmix when AC3_DOWNMIX = 2 and AC3_DUALMODE = 3. 1 0 Address: 0x6E Type: R/W Hardware Reset: UND Description:. Value Description 0 2/0 Dolby Surround (LT, RT) 1 1/0 (C) 2 2/0 (L, R) 3 3/0 (L, C, R) 4 (L, R, S) 5 3/1 (L, C, R, S) 6 2/2 (L, R, LS, RS - Dolby Phantom Mode 7 3/2 (L, C, R, LS, RS) Note: in notation, 3/2 represents 3 front speakers and 2 surround speakers. Software Reset: NC Hardware Reset: UND AC3_STATUS0 Description This register allows additional downmix to be set 65/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 69 / 93 STA310 Dolby Digital status register 7 6 Not used 5 4 Dolby Digital status register 2 3 fs_cod 2 1 0 7 Bitrate code 6 5 4 3 Bsmod 2 1 0 Bsid AudioBaseAddress + 0x76 Address + 0x78 Type: RO Type: RO Software Reset: NC Software Reset: NC Hardware Reset:UND Hardware Reset:UND Description: Description: This register contains bit stream information extracted from the stream. This register contains bit stream information extracted from the stream. Description Bitfield ft Bitfield ) s ( ct u d o Description r P e Bsid fs_cod Bsmod Bbit stream mode, indicates the type of service t e l o -D Code identifying the sampling frequency 5 4 Reserved 3 Description: s b O 0 Dr a Hardware Reset:UND t e l o )- s ( t c Acmod u d o r P e Software Reset: NC 1 LFE Address: 0x77 Type: RO 2 This register contains bit stream information extracted from the stream. Bitfield Description Acmod Audio coding mode. Indicates which channels are in use. LFE Dolby Digital status register 3 Dr 6 ft - 7 s b O AC3_STATUS3 aft AC3_STATUS1 Dolby Digital status register 1 Bit stream identification, indicates the version of the standard ra Bitrate code Code identifying the bitrate. Bitrate[4..0] = frmsizecod[5..1] Indicates if LFe channel is present in the stream 7 6 5 4 Reserved 3 2 Cmixlevel 1 0 SurMixlevel Address: 0x79 Type: RO Software Reset: NC Hardware Reset: UND Description: This register contains bit stream information extracted from the stream. Bitfield Description Cmixlevel Downmix level of center channel SurMixlevel Downmix level of surround channel AC3_STATUS2 AC3_STATUS4 66/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 70 / 93 STA310 Dolby Digital status register 4 7 6 5 4 Reserved 3 Type: RO 2 1 Software Reset: NC 0 Hardware Reset: UND Dsurmod Copyright Origbs Lancode Address: 0x7A Description: Type: RO This register contains the code indicating the dialog normalization level extracted from the stream. Software Reset: NC Hardware Reset: UND AC3_STATUS7 Dolby Digital status register 7 Description: This register contains bit stream information extracted from the stream. 5 4 Room type 3 2 u d o When at 1, indicates that the stream is an original When at 1, indicates that the stream is protected by copyright Dsurmod In 2/0 mode, indicates if the stream is Dolby surround encoded AC3_STATUS5 5 u d o 4 r P e 3 2 t e l o Address : 0x7B Type: RO s b O Software Reset: NC Hardware Reset: UND s b O 1 0 Dr a Lancode t e l o Hardware Reset: UND ft - 6 Audprodie Description: ) (s ct 0 r P e Software Reset: NC This register contains bit stream information extracted from the stream. Bitfield Dr Dolby Digital status register 5 Type: RO aft Copyright ft Origbs Address: 0x7D ra When at 1, indicates that a language code is provided in the stream ) s ( ct 1 Mix level Description Lancode 7 6 -D Bitfield 7 Description Audprodie Audprodie: if set, indicates that room type and mix level are provided Mix level If audprodie is set, mix level indicates the sound level Room type If audprodie is set, mix level indicates the sound level 9.17 MPEG configuration registers MP_SKIP_LFE Description: Channel skip This register contains the code of the language of the audio service, extracted from the stream. 7 6 5 4 3 2 1 0 Reserved AC3_STATUS6 Address : 0x68 Type: R/W Dolby Digital status register 6 7 6 Reserved 5 4 3 2 1 0 Dialog Normalization (see Dolby specifications) Software Reset: 0x00 Hardware Reset: UND Description: Address:0x7C 67/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 71 / 93 STA310 When this register is set to 1, the LFE channel is skipped. When this register is set to 0 the LFE channel is decoded (if present). Dynamic range control 7 6 5 4 3 2 1 0 DRC MP_PROG_NUMBER Address: 0x6A Program number Type: R/W 6 5 4 3 2 1 0 Reserved Software Reset: 0x00 Prog Hardware Reset: UND Address: 0x69 Type: R/W When bit DRC=1, dynamic range control is enabled. The dynamic range is set according to the data transmitted in the DVD MPEG stream. Software Reset: 0x00 ft Hardware Reset: UND Description: Bitfield ra CRC check off ct MPEG setup dual mode Addres: 0x6E e t e ol Type: R/W 4 du 3 2 o r P Software Reset: 0x00 s b O Hardware Reset: UND 1 2 1 0 Address: 0x6C Type: R/W Software Reset: NC Hardware Reset: UND Description: The MPEG DUAL_MODE is active in downmix mode 1 and 9. When register is set to 1, the CRC in MPEG frame is not checked. When register is set to 0, the CRC in MPEG frame is checked if exists. If a CRC error occurs, the decoder soft mutes the frame (but does not stop). MP_MC_OFF Multi-channel 7 Value 3 0 ft - 5 4 s b O Dr a 6 5 Dr ) (s MP_DUALMODE 6 aft Select program #0 or #1 where 0: L0,R0 in front channels, 1: L2,R2 in front channels 7 t e l o 7 Description u d o r P e MP_CRC_OFF When the stream is in Second Stereo mode, this register specifies which program is played. Prog ) s ( ct Description; -D 7 Description 6 5 4 Reserved DEN 0 Output as Stereo 1 Output Channel 1 on both outputs L/R 2 Output Channel 2 on both outputs L/R Software Reset: NC 3 Mix Channel 1 and 2 to monophonic, and output on both L/R Hardware Reset: UND 3 2 Reserved 1 0 MC Address: 0x6D Type: R/W MP_DRC 68/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 72 / 93 STA310 Description: (KS x RS) by (KS x S) in the above equations. MC Value Description When MC=1, the multi-channel part of the bitstream is not decoded, only the MPEG-1 compatible bitstream is decoded. Bit MC must be set to 1 for an MPEG-1 bitstream. De-normalization: set DEN=0 for MPEG1 signals, and set DEN=1 for MPEG2 multichannel signals When DEN=1, MPEG2 multi-channel signals L, C, R, LS and RS can be de-normalized. The signals must first be inverse-weighted then multiplied by the de-normalization factor. This undoes the attenuation carried out at the encoder side to avoid overload when calculating the compatible signals (see MPEG 13818-3 specifications). 3 2 1 0 o r P ft - du Hardware Reset: UND Dr a In the table below, LO, RO, CO, LsO, RsO represent the output channels after downmix, and L, R, C, LS, RS are the audio channels. s b O LO = (L + KC x C + KS x LS)/ (1 + KC + KS), RO = (R + KC x C + KS x RS)/ (1 + KC + KS) 0x02 3/0 (L, C, R) LO = L + KS x LS, RO = R + KS x RS, CO = C 0x03 2/1 (L, R, S) LO = L + KC x C, RO = R + KC x C, LsO = RsO = KS x (LS + RS ) 0x04 3/1 (L, C, R, S) LO = L, RO = R, CO = C, LsO = RsO = KS x (LS + RS) ) s ( ct u d o r P e 0x06 3/2 (L, C, R, LS, RS) LO = L, RO = R, CO = C, LsO = LS, RsO = RS 0x09 2/0 (Dolby surround LT, RT) LT = (L + 0.707C - 0.707 x 0.5 (LS + RS)) /2.414, RT = (R + 0.707C + 0.707 x 0.5 (LS + RS)) /2.414 o s b aft s ( t c Software Reset: 0x08 e t e ol 2/0 (L, R) = Stereo O ) Address: 0x6F Type: R/W Description: 0x01 -D 4 Dr 5 CO = Kj x L + C + Kr x R + KS (LS + RS) let MPEG downmix 6 1/0 (C) = Mono 0x05 2/2 (L, R, LS, RS) LO = L + KC x C, RO = R + KC x C, LsO = LS, RsO = RS MP_DOWNMIX 7 Comment 0x00 ra DEN Output Mode ft Bitfield The coefficients Kj, KC, Kr, KS, depend on the number of input channels. In the above table, the equations are given for a 5 channels input bitstream. If the input bitstream does not contain five channels (L, C, R, LS, RS), the coefficient “Kj” corresponding to the channel not present is equal to 0. If the MPEG bitstream contains only one surround channel (S), replace (KS x (LS + RS)), (KS x LS and 0x0A 2/0 Karaoke capable: V1 ON, V2 ON Lk = L + 0.707 A1 + 0.707 G, Rk = R + 0.707 A2 + 0.707 G 0x0B 2/0 Karaoke Lk = L + 0.707 A1 + 0.707 G, Capable: V1 ON, Rk = R + 0.707 G V2 OFF 0x0C 2/0 Karaoke Lk = L + 0.707 G, Rk = R + Capable: V1 OFF, 0.707 A2 + 0.707 G V2 ON 0x0D 2/0 Karaoke Lk = L + 0.707 G, Rk = R + Capable: V1 OFF, 0.707 G V2 OFF 0x0E 2/0 Karaoke Lk = L + 0.707 A1 + 0.707 G, Capable: V1 ON, Rk = R + 0.707 A1 + 0.707 G V2 OFF (Dolby Digital like) 0x0F 2/0 Karaoke Lk = L + 0.707 A2 + 0.707 G, Capable: V1 OFF, Rk = R + 0.707 A2 + 0.707 G V2 ON (Dolby Digital like) 0x1A 3/0 Karaoke Lk = L + 0.707 A1, Ck = G, Rk Capable: V1 ON, = R + 0.707 A2 V2 ON 69/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 73 / 93 STA310 0x1B 3/0 Karaoke Lk = L + 0.707 A1, Ck = G, Rk Capable: V1 ON, = R V2 OFF Description: 0x1C 3/0 Karaoke Lk = L, Ck = G, Rk = R + Capable: V1 OFF, 0.707 A2 V2 ON MEX[1:0] Mode Extension MOD[1:0] Mode 0x1D 3/0 Karaoke Lk = L, Ck = G, Rk = R Capable: V1 OFF, V2 OFF PRI Private Bit PAD Padding Bit 0x1E 3/0 Karaoke Lk = L, Ck = G + A1, Rk = R Capable: V1 ON, V2 OFF (Dolby Digital like) SFR[1:0] Sampling Frequency Bitfield Description MPEG status register 2 6 5 ra MP_STATUS0 e t e ol Address: 0x78 5 4 ID LAY[1:0] P 3 2 1 0 du Hardware Reset: UND Description: Protection Bit t e l o LAY[1:0] Layer ID Identifier bs O Description Dr a P e ft - ro s b O SFR[1:0] 5 4 PAD PRI Description EMP[1:0] Emphasis rate index OCB Original/Copy Bit C Copyright MPEG status register 3 7 6 CEN[1:0] MPEG status register 1 6 Bitfield MP_STATUS3 MP_STATUS1 7 Description: Dr s ( t c Software Reset: UND P EMP[1:0] Hardware Reset: UND )- Bit rate index OCB 0 Software Reset: UND BRI[3:0] Type: RO Bitfield C 1 Type: RO Address : 0x76 BRI[3:0] 2 aft 6 Pr 3 -D MPEG status register 0 u d o 4 ft 7 not used 7 ) s ( ct MP_STATUS2 0x1F 3/0 Karaoke Lk = L, Ck = G + A2, Rk = R Capable: V1 OFF, V2 ON (Dolby Digital like) 3 2 MOD[1:0] 1 0 MEX[1:0] 5 4 SUR[1:0] 3 2 LFE AMX 1 0 DEM[1:0] Address : 0x79 Type: RO Software Reset: UND Hardware Reset: UND Address: 0x77 Type: RO Software Reset: UND Hardware Reset: UND 70/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 74 / 93 STA310 Description: Bitfield 9.18 Pink noise generation registers PN_DOWNMIX Description DEM[1:0] Dematrix procedure AMX Audio mix LFE LFE SUR[1:0] Surround CEN[1:0] Centre Pink noise downmix 7 6 5 4 3 2 1 0 RS LS LFE C R L Address: 0x6F Type: R/W Software Reset: NC MP_STATUS4 Hardware Reset: UND ) s ( ct MPEG status register 4 EXT 5 4 NML[2:0] 3 2 1 0 MFS MLY CIB CIS Bitfield L Address: 0x7A aft ) (s Bitfield Description CIS Copyright ID Start CIB Copyright ID Bit MLY Multi-lingual Layer MFS Multi-lingual FS NML[2:0] Number of Multi-lingual Channels r P e Dr ft - u d o Extension bitstream present MP_STATUS5 MPEG status register 5 7 ct 6 5 4 Dr a s b O s b O LFE t e l o 1: Right channel contains pink noise 0: Right channel is forced to zero -D C Description: EXT r P e t e l o R Hardware Reset: UND 3 2 1 u d o Description 1: Left channel contains pink noise 0: Left channel is forced to zero Type: RO Software Reset: UND ft 6 ra 7 Description: 1: Center channel contains pink noise 0: Center channel is forced to zero 1: LFE channel contains pink noise 0: LFE channel is forced to zero LS 1: Left surround channel contain pink noise 0: Left surround channel is forced to zero RS 1: Right surround channel contains pink zero 0: Right surround channel is forced to zero After this processing, the OCFG stage is applied on these channels. OCFG must be configured to 0 and attenuation on all channels must be set to 10dB attenuation. The other values must not be used because low frequency extraction must not be done when generating pink noise. 0 Address: 0x7B Pink noise selection is made through the SEL and DECODSEL registers. Type: RO 9.19 PCM beep-tone registers PCM_BTONE Software Reset: UND PCM beep tone frequency STREAM- Hardware Reset: UND 7 6 5 4 3 2 1 0 Description: The number of extended ancillary data bytes is contained in this register Address: 0x68 71/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 75 / 93 STA310 Type: R/W Address: 0x82 Software Reset: 0 Type: R/W Hardware Reset: UND Reset value: 0xFF Description: Description: The value in this register sets the PCM beep tone frequency according to the formula: This register has the same function KAR_MCh0VOL for the right music channel. as Beep_tone_frequency = (Fs/2)/(Register_value+1) KAR_KEYCONT Key control (Pitch Shift) ON/OFF 9.20 Karaoke registers This section describes the registers which select the karaoke effects, for example: volume, chorus, echo, reverb and mute. Any change to these registers must be signalled to the DSP by writing 1 to the register. 7 6 5 4 3 ft Reserved Address: 0x83 Reset value: 0 KAR_MCh0VOL -D t e l o Music channel 0 (L) volume 1 0 PSHIFT u d o r P e ra Type: R/W ) s ( ct 2 Description:. 6 5 4 3 2 1 0 value Reset value: 0xFF du Key value Dr a This register contains the scaling factor applied to the left channel of the music input. It specifies a fractional multiplication factor whose value varies from 0 to 1.0: e t e ol Music Left channel = original music left channel scale_factor. bs O Bitfield Value 7 6 5 4 3 2 1 0 KEYVALUE Address: 0x84 Type: R/W Reset value: 0x00 Description 0x00: Scale factor 0 = left channel mute 0x7F: Scale factor 0.5 = half restitution of left channel 0xFF: Scale factor 1.0 = full restitution of left channel 5 The pitch shift can be changed from -3.5 to 3.5 tones, in steps of 1/4 tone. This register sets the number of tones according to the following table: 4 3 -1/ -1/ -3/ -1 4 2 4 KEYVAL 0 UE (decimal) Music channel 1 (R) volume 6 Description: Key control (tone) KAR_MCh1VOL 7 0: pitch shift disabled, 1: pitch shift enabled KAR_KEYVALUE ft - o r P PSHIFT Description Dr s ( t c Type: R/W Description; Bitfield )- Address: 0x81 s b O aft 7 2 1 1 2 3 -2.49 -3.5 1.1 1.3 1.5 1.9 6 4 8 3 4 5 6 7 8 9 0 value 72/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 76 / 93 STA310 Key 1/4 1/2 3/4 control (tone) 1 1.16 1.34 1.58 1.93 2.49 3.5 KAR_MMUTE Music channel mute KEYVAL 10 11 12 13 14 UE (decimal) 15 16 17 7 18 19 6 5 4 3 2 1 Reserved 0 MUTE Address: 0x87 KAR_VCANCEL Type: R/W Voice cancellation ON/OFF Reset value:0 6 5 4 3 2 1 Reserved 0 VCANCEL This register mutes the music channel. Address: 0x85 Bitfield Type: R/W Reset value: 0 ra Voice channel 0 (L) volume 0: voice cancellation off, 1: voice cancellation on bs 7 3 Type: R/W e t e ol Reset value: 0x0 bs Description: 2 u d o 1 Bitfield 2 1 0 Value Type: R/W 0 Reset value: 0xFF LEVEL[2:0] Pr When the voice cancellation is enabled by the KAR_VCANCEL register, KAR_VVALUE specifies the extent of the voice cancellation according to the following table: O 3 aft s ( t c Dr a Address: 0x86 4 Dr 4 5 Address: 0x88 ft - 5 Reserved 6 O ) Degree of voice cancellation 6 r P e t e l o -D Description KAR_VVALUE 7 0: not muted, 1: muted KAR_VCh0VOL Bitfield u d o Description MUTE Description: VCANCELL ) s ( ct Description: ft 7 Description: This register has the same function as KAR_MCh0VOL for the left voice channel instead of the left music channel. KAR_VCh1VOL Voice channel 1 (R) volume 7 6 5 4 3 2 1 0 Value Description LEVEL[2:0] 0: cut-band filter with 40dB attenuation at 700Hz 1: cut-band filter with 35dB attenuation at 700Hz 2: cut-band filter with 32dB attenuation at 700Hz 3: cut-band filter with 27dB attenuation at 700Hz 4: cut-band filter with 23dB attenuation at 700Hz Address: 0x89 Type: R/W Reset value: 0xFF Description: This register has the same function as KAR_MCh0VOL for the right voice channel instead of the left music channel. 73/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 77 / 93 STA310 KAR_DUET Description: Duet ON/OFF switch 7 6 5 Bitfield 4 3 2 1 0 Reserved VOICEEFF Selecte the voice effects: 0: No effect is applied to the voice input 1: Echo is applied to the voice inputs, tuned by registers KAR_VDELAY and KAR_VBAL 2: Chorus is applied to the voice inputs, tuned by registers KAR_VDELAY and KAR_VBAL 3: Reverb is applied to the voice inputs, tuned by register KAR_VDELAY. DUET Address: 0x8A Type: R/W Reset value: 0 Description: MIX ft Description 0: duet off and 1: duet on u d o r P e ra DUET ) s ( ct Voice channel mixing: 0: No mix, voice is output on centre channelt 1: Mix music and voice channels into music channel. The value in this register sets the duet function on or off. When selected, the duet function is configured by register KAR_DUETTHRESH. Bitfield Description KAR_VDELAY t e l o -D Programmable delay/decay music effects KAR_DUETTHRESH 7 Duet threshold control 6 5 4 3 2 1 Value Dr Dr a O 0 Description: When the Duet function is enabled by the KAR_DUET register, this register specifies the amplitude of the voice line below which the voice is cancelled. If the amplitude of the voice line is below this threshold, the recorded voice is played instead. The value of DUETTHRESHOLD ranges from 0 to 255, full scale signal. bs 1 Reset value: 0x0 ft - e t e ol Pr 2 Type: R/W s ( t c u d o Description: 3 Address: 0x8D Address + 0x8B Reset delay: 0 4 O ) DUETTHRESHOLD[7:0] Type: R/W bs 0 5 aft 7 6 The value in this register specifies the delay used for voice input effects. The delay can be set in the range from 0 to 2048/Fs seconds (where Fs is the sampling frequency in KHz). ‘desired time delay’ = ( 2048 / Fs) * ( Value / 256) which gives: KAR_VDELAY value = (Fs / 8) * ’desired time delay For reverberation effects, this register gives the decay factor,which can vary within the range 0 to 1.0. KAR_VOICE KAR_VBAL Selection of voice effects Programmable mix for echo and chorus effects 7 6 5 Reserved 4 3 2 1 0 MIX VOICEEFF[1:0 ] Address: 0x8C 7 6 5 4 3 2 1 0 BALANCE[7:0] Address: 0x8E Type: R/W Type: R/W Reset delay: 0x0 Reset value: 0x3F 74/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 78 / 93 STA310 Description: KAR_MODE This register sets the balance between the original sound and its delayed version for the echo and chorus effects according to the formula. echo (or chorus) output = original_sound * (1 - balance) + delayed_sound * balance Operating mode selection where balance = Balance[7:0] / 255 where balance can vary in the range of 0 to 1. A balance limit of 0.5 is recommended. BALANCE[7:0] = balance * 255. 7 6 5 4 3 2 Reserved 1 0 KAR_MODE[1:0] Address + 0x91 Type: R/W Reset value: 0x01 ) s ( ct KAR_VMUTE Description: Voice channel mute This register specifies the working mode of the Karaoke module. 6 5 4 3 2 1 0 Reserved MUTE Bitfield ra t e l o -D Type: R/W Reset value: 0x00 bs -O This register mutes the voice channel: ’0’ means not muted and ’1’ means muted. Pr 4 Reserved e t e ol Address: 0x90 bs Type: R/W Reset value: 0x01 O 3 2 1 0 PLAY Dr a 5 11: Total Software reset. The program is reset and the registers values are changed back to their reset default values. ft - u d o Mute of voice and music 10: Partial Software reset. This resets the internal DSP program but keep the register configuration as it was before the partial reset. When the partial reset is finished, KAR_MODE[1:0] is automatically set to ’01’. Dr KAR_PLAY ) s ( ct 01: Karaoke processor running. aft Description: 6 r P e KAR_MODE 00: Karaoke processor in waiting mode. [1:0] This is the default mode after a hardware reset, total or partial software reset. This mode is used to programme all the registers at first initialization. Address: 0x8F 7 u d o Description ft 7 KAR_DIN_CTL Control of voice channel 7 6 5 4 3 2 1 Reserv JUSTIF DELAY WS_P CLK_P WS[1:0] ed OL OL Description: This register mutes the voice and the music channels simultaneously: PLAY = ’0’ means muted and ’1’ means playing. The registers and KAR_VMUTE have priority for muting. 0 DINEN Address: 0x92 Type: R/W Reset Value: 0x00 Description: This register specifies the input format for configuring 75/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 79 / 93 STA310 the handling of the second input. This register sets the sampling frequency, Fs, of the incoming PCM stream. Description DINEN DIN enable: 0: disabled, 1: enabled WS[1:0] PCM precision: 00: 16-bit mode, 01: 18-bit mode, 10: 20-bit mode, 11: 24-bit mode CLK_POL 0: Data and WS change on clockalling edge 1: Data and WS change on clockising edge DELAY JUSTIF 0: Left padded, 1: Right padded 8 5 4 3 1 0 u d o 5 Dr a 4 Reserved 3 2 17 18 - ) s ( ct u d o 19 4 let 3 2 1 0 MODE[6;0] Reset Value: 0x00 Description; This register specifies the input format for configuring the handling of the second input. Description 0: 16 1: 16 2: 32 MODE 3: 32 [6:0] 4: 32 5: 32 6: 32 7: 32 slots mode slots mode, LSB first slots mode, left aligned slots mode, right aligned slots mode, I2S mode slots mode, sign extended slots mode, 8-bit data slots mode16-bit data Channel swap: 0: Left channel first, 1: Right channel firs 9.22 Linear PCM (DVD audio) registers LPCMA_DOWNMIX Sampling frequency of voice channel 6 5 o s b SWAP 9.21 Second serial input registers SFREQ2 7 14 15 16 r P e 6 Bitfield This register loads the new Karaoke configuration into the internal registers when UPDATE is set to ’1’. When the bit is reset to ’0’ the system continues in the configuration last loaded. s b O - 192 176.4 128 -O ft - e t e ol Pr 9 Dr ) s ( ct Address: 0x93 Description: 7 Type: R/W UPDATE Reset Value: 0 13 6 Address: 0x95 2 Reserved Type: R/W 5 Selection of input data format -D 6 4 aft 7 3 CANINPUT_MODE SWAP Change active Karaoke functions 2 Value 10 11 12 (decimal) 7 KAR_UPDATE 1 Fs (KHz) 16 - 12 11.02 8 5 0: Left data word = WS low, right data word = WS high 1: Left data word = WS high, right data word = WS low 0: First bit of data occurs on transition of WS 1: First bit of data occurs with 1 clock cycle delay (I2S compatible) 24 22.05 Value 0 (decimal) ft WS_POL Fs (KHz) 48 44.1 32 - 96 88.2 64 - ra Bitfield Description: 1 0 Value Downmix 7 6 5 4 Reserved 3 2 1 0 Value Address: 0x94 Type: RO Address: 0x6F Reset Value: 0 Type: R/W Software Reset: NC 76/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 80 / 93 STA310 Hardware Reset: UND Description: This register sets the phase coefficients for channels mixing to Lmix. The input signal is inverted when PH_xL = ’0’ and non-inverted when ’1’. Description;:. Value Description 0 Downmix not applied 1 Force downmix 2/0 LPCMA_DM_COEFT_1 Downmix phase coefficients 1 2 Downmix 2/0 is applied if the flags down_mix_code_validity AND stereo_playback_mode are both ’0’ in the bitstream 7 6 PH_0R The notation, 2/0 represents 2 front speakers and no surround speakers. 5 4 Address: 0x98 Type: R/W Downsampling 192 to 96KHz Hardware Reset: UND 3 2 1 Reserved ra 4 0 )- od s b O s b O Value Dr a t e l o Bitfield ft - This register selects whether downsampling is used for input streams requiring sampling frequencies of 192KHz or 176.4KHz. When ’automatic’ is selected, register is automatically updated to correspond to the new output frequency. r P e 00: Automatic (if Fs = 192KHz or 176.4KHz) 01: Automatic (if Fs = 192KHz or 176.4KHz) 10: No downsampling 0 5 4 7 6 5 4 3 2 1 0 COEF_0L Address: 0x99 Type: R/W Hardware Reset: UND Description: This register sets the mixing gain for Lf to Lmix. See the note after register Downmix phase coefficients 0 6 Downmix gain coefficients 2 Software Reset: NC Description LPCMA_DM_COEFT_0 7 LPCMA_DM_COEFT_2 Dr t(s uc u d o aft Type: R/W Description: ) s ( ct This register sets the phase coefficients for channels mixing to Rmix. The input signal is inverted when PH_xR = ’0’ and non-inverted when ’1’. Address : 0x70 Hardware Reset: UND 0 t e l o Description: Value Software Reset: NC 1 r P e -D 5 ft Software Reset: NC 6 2 0 PH_2R PH_3R PH_4R PH_5R Reserved LPCMA_FORCE_DWS 7 3 LPCMA_DM_COEFT_3 3 2 1 0 PH_1L PH_2L PH_3L PH_4L PH_5L Reserved Downmix gain coefficients 3 7 6 5 4 3 2 1 0 COEF_0R Address : 0x97 Type: R/W Address : 0x9A Software Reset: NC Type: R/W Hardware Reset: UND Software Reset: NC 77/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 81 / 93 STA310 Hardware Reset: UND Software Reset: NC Hardware Reset: UND Description: This register sets the mixing gain for Lf to Rmix. See the note after register Description: This register sets the mixing gain for C to Lmix. See the note after register . LPCMA_DM_COEFT_4 Downmix gain coefficients 4 7 6 5 4 3 LPCMA_DM_COEFT_7 2 1 Downmix gain coefficients 7 0 COEF_1L 7 6 5 4 Address: 0x9B Address: 0x9E Type: R/W ft Software Reset: NC Hardware Reset: UND ra Hardware Reset: UND LPCMA_DM_COEFT_5 Downmix gain coefficients 5 4 3 )- s ( t c 2 1 u d o COEF_1R Hardware Reset: UND s b O Description: -D This register sets the mixing gain for C to Rmix. See the note after register LPCMA_DM_COEFT_8 Downmix gain coefficients 8 0 ft - e t e ol Software Reset: NC Pr s b O Dr a Address: 0x9C Type: R/W u d o t e l o Description: Dr 5 0 aft This register sets the mixing gain for Rf to Lmix. See the note after register LPCMA_DM_COEFT_13. 1 r P e Software Reset: NC Description: 6 ) s ( ct 2 COEF_2R Type: R/W 7 3 7 6 5 4 3 2 1 0 COEF_3L Address: 0x9F Type: R/W Software Reset: NC Hardware Reset: UND This register sets the mixing gain for Rf to Rmix. Description: See the note after register This register sets the mixing gain for Ls / S to Lmix. See the note after register LPCMA_DM_COEFT_13. LPCMA_DM_COEFT_9 LPCMA_DM_COEFT_6 Downmix gain coefficients 9 Downmix gain coefficients 6 7 7 6 5 4 3 2 1 6 5 4 0 3 2 1 0 COEF_3R COEF_2L Address : 0xA0 Type: R/W Address: 0x9D Type: R/W Software Reset: NC 78/90 Copyright STMicroelectronics Company Internal Unauthorized reproduction and communication strictly prohibited Document CD00003411 1.3 Revision IN APPROVAL 82 / 93 STA310 Hardware Reset: UND LPCMA_DM_COEFT_13 Downmix gain coefficients 13 Description: 7 This register sets the mixing gain for Ls / S to Rmix. See the note after register 5 4 4 3 2 1 0 Address: 0xA4 Type: R/W Downmix gain coefficients 10 6 5 COEF_5R LPCMA_DM_COEFT_10 7 6 3 Software Reset: NC 2 1 Hardware Reset: UND 0 COEF_4L ) s ( ct Description: Address : 0xA1 Type: R/W This register sets the mixing gain for LFE to Rmix u d o Note: For DVD audio, the real coefficient value, alpha[x], applied to channel x is calculated with the following formulae: ft Software Reset: NC r P e ra Hardware Reset: UND alpha[x] = 2-(COEF_xL/30) 0
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