STA321MP
Scalable digital microphone processor
Datasheet - production data
Description
74)3
PP[PP
Features
• 8 digital processing channels each 24-bits
– 6 channels of PDM input
– 2 additional virtual channels
• >100 dB SNR and dynamic range
• Digital gain/attenuation 58 dB to -100 dB in
0.5 dB steps
• Soft volume update
• Individual channel and master level control
• Up to 10 independent 32-bit userprogrammable biquads (EQ) per channel
• Bass/treble tone control
• Pre- and post-EQ full 8-channel input mix on all
8 channels
• Dual independent limiters/compressors
• Dynamic range compression or anti-clipping
modes
• Individual channel and master soft/hard mute
• 3 I²S data outputs
The STA321MP is a PDM, high-performance,
multichannel processor with ultra-low quiescent
current. It is designed for general-purpose digital
microphone applications. The device is fully
digital and is comprised of three main sections.
The first section is the PDM input interface which
can accept up to six serial digital inputs. The
second section is a high-quality audio processor
allowing flexible channel mixing/muxing and
provides up to 10 biquads for general sound
equalization and voice enhancement with
independent volume control. The last block is the
I²S output interface which streams out the
processed digital audio. The output interface can
also be programmed for flexible channel
mapping. The device offers some of the most
commonly required audio enhancements such as
programmable voice tuning and equalization,
limiter/compressor for improved voice quality,
multiband selection for customizable microphone
usage, and configurable wind-noise rejection. The
embedded digital processor allows the
microphone processing to be offloaded from the
main CPU or SoC to the device.
Table 1. Device summary
Order code
Package
Packaging
STA321MPLTR
TQFP64
Tape and reel
• I²S data output channel mapping function
• Independent channel volume and DSP bypass
• Channel mapping of any input to any
processing channel
Applications
• Tablets
• Gaming
• Audio conference sets
• Legacy microphone-equipped devices
June 2016
This is information on a product in full production.
DocID022647 Rev 6
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www.st.com
Contents
STA321MP
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
I2C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1
Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.2
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.3
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.1
Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.2
Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Application reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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7.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2.1
Configuration register A (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2.2
Configuration register C (0x02) - serial output formats . . . . . . . . . . . . . 20
7.2.3
Configuration register E (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2.4
Configuration register F (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2.5
Configuration register G (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2.6
Configuration register H (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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STA321MP
Contents
7.2.7
Configuration register I (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2.8
Master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.9
Master volume register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.10
Channel 1 volume (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.11
Channel 2 volume (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.12
Channel 3 volume (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.13
Channel 4 volume (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.14
Channel 5 volume (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2.15
Channel 6 volume (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2.16
Channel 7 volume (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2.17
Channel 8 volume (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2.18
Channel 1 volume trim, mute, bypass (0x13) . . . . . . . . . . . . . . . . . . . . 27
7.2.19
Channel 2 volume trim, mute, bypass (0x14) . . . . . . . . . . . . . . . . . . . . 27
7.2.20
Channel 3 volume trim, mute, bypass (0x15) . . . . . . . . . . . . . . . . . . . . 27
7.2.21
Channel 4 volume trim, mute, bypass (0x16) . . . . . . . . . . . . . . . . . . . . 28
7.2.22
Channel 5 volume trim, mute, bypass (0x17) . . . . . . . . . . . . . . . . . . . . 28
7.2.23
Channel 6 volume trim, mute, bypass (0x18) . . . . . . . . . . . . . . . . . . . . 28
7.2.24
Channel 7 volume trim, mute, bypass (0x19) . . . . . . . . . . . . . . . . . . . . 28
7.2.25
Channel 8 volume trim, mute, bypass (0x1A) . . . . . . . . . . . . . . . . . . . . 28
7.2.26
Channel input mapping channels 1 and 2 (0x1B) . . . . . . . . . . . . . . . . . 30
7.2.27
Channel input mapping channels 3 and 4 (0x1C) . . . . . . . . . . . . . . . . . 30
7.2.28
Channel input mapping channels 5 and 6 (0x1D) . . . . . . . . . . . . . . . . . 30
7.2.29
Channel input mapping channels 7 and 8 (0x1E) . . . . . . . . . . . . . . . . . 30
7.2.30
Biquad internal channel loop-through (0x28) . . . . . . . . . . . . . . . . . . . . . 31
7.2.31
Mix internal channel loop-through (0x29) . . . . . . . . . . . . . . . . . . . . . . . 31
7.2.32
EQ bypass (0x2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2.33
Tone control bypass (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2.34
Tone control (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.35
Channel 1 and 2 output timing (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.36
Channel 3 and 4 output timing (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.37
Channel 5 and 6 output timing (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.38
Channel 7 and 8 output timing (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.39
Channel I2S output mapping channels 1 and 2 (0x37) . . . . . . . . . . . . . 34
7.2.40
Channel I2S output mapping channels 3 and 4 (0x38) . . . . . . . . . . . . . 34
7.2.41
Channel I2S output mapping channels 5 and 6 (0x39) . . . . . . . . . . . . . 34
7.2.42
Channel I2S output mapping channels 7 and 8 (0x3A) . . . . . . . . . . . . . 35
7.2.43
Coefficient address register 1 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Contents
8
STA321MP
7.2.44
Coefficient address register 2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.45
Coefficient b1 data register, bits 23:16 (0x3D) . . . . . . . . . . . . . . . . . . . . 35
7.2.46
Coefficient b1 data register, bits 15:8 (0x3E) . . . . . . . . . . . . . . . . . . . . . 36
7.2.47
Coefficient b1 data register, bits 7:0 (0x3F) . . . . . . . . . . . . . . . . . . . . . . 36
7.2.48
Coefficient b2 data register, bits 23:16 (0x40) . . . . . . . . . . . . . . . . . . . . 36
7.2.49
Coefficient b2 data register, bits 15:8 (0x41) . . . . . . . . . . . . . . . . . . . . . 36
7.2.50
Coefficient b2 data register, bits 7:0 (0x42) . . . . . . . . . . . . . . . . . . . . . . 36
7.2.51
Coefficient a1 data register, bits 23:16 (0x43) . . . . . . . . . . . . . . . . . . . . 36
7.2.52
Coefficient a1 data register, bits 15:8 (0x44) . . . . . . . . . . . . . . . . . . . . . 36
7.2.53
Coefficient a1 data register, bits 7:0 (0x45) . . . . . . . . . . . . . . . . . . . . . . 37
7.2.54
Coefficient a2 data register, bits 23:16 (0x46) . . . . . . . . . . . . . . . . . . . . 37
7.2.55
Coefficient a2 data register, bits 15:8 (0x47) . . . . . . . . . . . . . . . . . . . . . 37
7.2.56
Coefficient a2 data register, bits 7:0 (0x48) . . . . . . . . . . . . . . . . . . . . . . 37
7.2.57
Coefficient b0 data register, bits 23:16 (0x49) . . . . . . . . . . . . . . . . . . . . 37
7.2.58
Coefficient b0 data register, bits 15:8 (0x4A) . . . . . . . . . . . . . . . . . . . . . 37
7.2.59
Coefficient b0 data register, bits 7:0 (0x4B) . . . . . . . . . . . . . . . . . . . . . . 37
7.2.60
Coefficient write control register (0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3
Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.4
Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5
Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.6
Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1
Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.2
Variable max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.2.1
8.3
Variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.3.1
8.4
9
4/47
DCC1-2 (0x4F, 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.1
10
MPCC1-2 (0x4D, 0x4E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TQFP64 (10 mm x 10 mm x 1.4 mm) package information . . . . . . . . . . . 45
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DocID022647 Rev 6
STA321MP
1
Block diagram
Block diagram
Figure 1. Block diagram
));
Figure 2. Channel signal flow
DocID022647 Rev 6
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47
Pin connections
2
STA321MP
Pin connections
6/47
($3'
287$
287%
*1'
9''
1&
/5&.2
%,.2
6'2B
9''
6'2B
*1'
1&
6'2B
6'2B
3:'1
Figure 3. Pin connections (top view)
3'0B&/.
287$
*1'
287%
9''
1&
*1'
*1'
1&
9''
3'0,1B
287$
3'0,1B
287%
3'0,1B
287$
3'0,1B
287%
3'0,1B
287$
3'0,1B
287%
9''
1&
*1'
*1'
1&
9''
5(6(7
287$
3//%
287%
*1'
287%
287$
287%
287$
1&
9''
9''
*1'$
&.287
;7,
1&
6&/
1&
6$
6'$
74)3
DocID022647 Rev 6
STA321MP
Pin connections
Table 2. Pin description
Pin
number
Type
Name
Description
1
PDM_CLK
PDM I/F CLK
6
PDMIN_6
PDM input channel 6
7
PDMIN_5
PDM input channel 5
PDMIN_4
PDM input channel 4
9
PDMIN_3
PDM input channel 3
10
PDMIN_2
PDM input channel 2
11
PDMIN_1
PDM input channel 1
RESET
Global reset
PLLB
Bypass phase-locked loop
SA
Connect to GND
SDA
Serial data (I2C)
SCL
Serial clock (I2C)
XTI
Crystal oscillator input (clock input)
GNDA
PLL ground
8
15
16
17
18
19
20
5-V tolerant TTL input buffer
5-V tolerant TTL Schmitt trigger input buffer
CMOS input buffer with pull-down
Bidirectional buffer: 5-V tolerant TTL Schmitt
trigger input; 3.3-V capable 2 mA slew-rate
controlled output
5-V tolerant TTL Schmitt trigger input buffer
23
Analog ground
25
3.3-V capable TTL tristate 4 mA output buffer CKOUT
29
OUT8B
PWM channel 8 output B
30
OUT8A
PWM channel 8 output A
31
OUT7B
PWM channel 7 output B
32
OUT7A
PWM channel 7 output A
33
OUT6B
PWM channel 6 output B
34
OUT6A
PWM channel 6 output A
38
OUT5B
PWM channel 5 output B
OUT5A
PWM channel 5 output A
OUT4B
PWM channel 4 output B
41
OUT4A
PWM channel 4 output A
42
OUT3B
PWM channel 3 output B
43
OUT3A
PWM channel 3 output A
47
OUT2B
PWM channel 2 output B
48
OUT2A
PWM channel 2 output A
49
OUT1B
PWM channel 1 output B
50
OUT1A
PWM channel 1 output A
39
40
3.3-V capable TTL 2 mA output buffer
Clock output
51
3.3-V capable TTL 4 mA output buffer
EAPD
Ext. amp power-down
55
3.3-V capable TTL 2 mA output buffer
BICKO
Output serial clock
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Pin connections
STA321MP
Table 2. Pin description (continued)
Pin
number
Type
Name
Description
56
LRCKO
Output left/right clock
57
SDO_12
Output serial data channels 1 and 2
SDO_34
Output serial data channels 3 and 4
62
SDO_56
Output serial data channels 5 and 6
63
SDO_78
Output serial data channels 7 and 8
PWDN
Device power-down
3, 12, 24,
28, 35, 3.3-V digital supply voltage
44, 52, 59
VDD3
3.3-V supply
2, 4, 13,
27, 36, Digital ground
45, 53, 60
GND
Ground
14, 21,
22, 26,
37, 46,
54, 61, 63
NC
Not connected
58
64
8/47
3.3-V capable TTL 2 mA output buffer
5-V tolerant TTL Schmitt trigger input buffer
DocID022647 Rev 6
STA321MP
Electrical characteristics
3
Electrical characteristics
3.1
Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol
3.2
Parameter
Min
Typ
Max
VDD
3.3-V I/O power supply
-0.5
4
VDDA
3.3-V logic power supply
-0.5
4
Vi
Voltage on input pins
-0.5
VDD + 0.5
Vo
Voltage on output pins
-0.5
Tstg
Storage temperature
-40
150
Tamb
Ambient operating temperature
-40
90
—
Unit
V
VDD + 0.3
°C
Thermal data
Table 4. Thermal data
Symbol
Rthj-case
3.3
Parameter
Thermal resistance, junction-case (thermal pad)
Min
—
Typ
—
Max
1.5
Unit
°C/W
Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
Parameter
Min
VDD
I/O power supply
3.0
VDDA
Logic power supply
3.0
Tj
Operating junction temperature
-40
DocID022647 Rev 6
Typ
Max
3.6
—
3.6
125
Unit
V
°C
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47
Electrical characteristics
3.4
STA321MP
Electrical specifications
The following specifications are valid for VDD = 3.3 V ± 0.3 V, VDDA = 3.3 V ± 0.3 V and
Tamb = 0 to 70 °C, unless otherwise stated
Table 6. General interface electrical specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Iil
Low-level input no pull-up
Vi = 0 V
1 (1)
Iih
High-level input no
pull-down
Vi = VDD
2
IOZ
Tristate output leakage
without pull-up/down
Vi = VDD
Vesd
Electrostatic protection
(human body model)
Leakage < 1μA
—
Unit
μA
2
2000
V
1. The leakage currents are generally very small, < 1 nA. The values given here are maximum after an
electrostatic stress on the pin.
Table 7. DC electrical characteristics: 3.3-V buffers
Symbol
10/47
Parameter
Conditions
Min
Typ
Max
VIL
Low-level input voltage
VIH
High-level input voltage
VILhyst
Low-level threshold
Input falling
0.8
1.35
VIHhyst
High-level threshold
Input rising
1.3
2.0
Vhyst
Schmitt trigger hysteresis
Vol
Low-level output
Voh
High-level output
Unit
0.8
2.0
0.3
IoI = 100 µA
0.8
0.2
Ioh = -100 µA
VDD0.2
Ioh = -2 mA
2.4
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V
STA321MP
4
Pin description
Pin description
PDM interface clock (PDM_CLK)
The clock to the PDM interface is provided on this pin and is used by the device to sample
the digital microphone data. This clock must be used to clock both the interface and the
microphones. The clock frequency must not exceed the upper limit of the microphone’s
specific clock frequency (please refer to the datasheet of the specific microphone used).
PDM input channels (PDMIN_1/6)
Audio information enters the device through the PDM input channels. These input pins
receive the digital output signal from the microphones.
RESET
Driving this pin low turns off the outputs and returns all settings to their defaults.
I2C bus
The SDA and SCL pins operate per the Phillips I2C specification. See Section 5: I2C bus
operation.
Phase-locked loop (PLL)
The phase-locked loop section provides the system timing signals and CKOUT.
Clock output (CKOUT)
System synchronization and master clocks are provided by CKOUT. This clock can be
conveniently divided and then used to clock both the PDM interface and the microphones.
Please refer to Figure 6.
PWM outputs (OUT1 through OUT8)
The PWM outputs provide the input signal for the power devices.
Serial data out (SDO_12, SDO_34, SDO_56, SDO_78)
These are the outputs for audio information. Six different formats are available including I2S,
left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
Device power-down (PWDN)
Pulling PWDN low begins the power-down sequence which puts the STA321MP into a
low-power state. EAPD (pin 51) goes low approximately 30 ms later.
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I2C bus operation
5
STA321MP
I2C bus operation
The STA321MP supports the I2C protocol via the input ports SCL and SDA_IN (master to
slave) and the output port SDA_OUT (slave to master).
This protocol defines any device that sends data to the bus as a transmitter and any device
that reads data as a receiver.
The device that controls the data transfer is known as the master and the other is called the
slave. The master always starts the transfer and provides the serial clock for
synchronization. The STA321MP is a slave device in all of its communications.
5.1
Communication protocol
5.1.1
Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a START or STOP condition.
5.1.2
Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
5.1.3
Stop condition
STOP is identified by a low to high transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A STOP condition terminates communication between
STA321MP and the bus master.
5.1.4
Data input
During data input, the STA321MP samples the SDA signal on the rising edge of the SCL
clock.
For correct device operation, the SDA signal must be stable during the rising edge of the
clock and the data can change only when the SCL line is low.
5.2
Device addressing
To start communication between the master and the Omega FFX core, the master must
initiate with a start condition. Following this, the master sends 8 bits to the SDA line (MSB
first) corresponding to the device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus
definition. In the STA321MP the I2C interface has two device addresses depending on the
SA port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1.
The 8th bit (LSB) identifies a read or write operation RW, this bit is set to 1 in read mode and
0 for write mode. After a START condition the STA321MP identifies on the bus the device
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I2C bus operation
STA321MP
address and if a match is found, it acknowledges the identification on the SDA bus during
the 9th-bit time. The byte following the device identification byte is the internal space
address.
5.3
Write operation
Following the START condition, the master sends a device select code with the RW bit set
to 0. The STA321MP acknowledges this and then waits for the byte of the internal address.
After receiving the internal byte address the STA321MP again responds with an
acknowledgment.
5.3.1
Byte write
In byte write mode, the master sends one data byte, which is acknowledged by the FFX
core. The master then terminates the transfer by generating a STOP condition.
5.3.2
Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
Figure 4. Write mode sequence
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