STA32613TR

STA326 2.1-channel high-efficiency digital audio system Datasheet - production data  Bass/treble tone control  Dual independent programmable limiters/compressors ) s t(  Automodes – 32 preset EQ curves – 15 preset crossover settings – Auto volume-controlled loudness – 3 preset volume curves – 2 preset anti-clipping modes – Preset nighttime listening mode – Preset TV AGC c u d PowerSO-36 with exposed pad up e t le o r P o s b  Input and output channel mapping  AM noise-reduction and PWM frequency-shifting modes Features O )  Wide supply voltage range (10 V - 36 V)  Three power output configurations – 2 x 40 W + 1 x 80 W – 2 x 80 W – 1 x 160 W  Auto zero detect and invalid input detect muting t(s uc d o r  Software volume update and muting  Selectable DDX® ternary or binary PWM output + variable PWM speeds  PowerSO-36 package (exposed pad up (EPU))  Selectable de-emphasis  2.1 channels of 24-bit DDX®  Post-EQ user-programmable mix with default 2.1 bass-management settings eP t e l o  100-dB SNR and dynamic range  Variable max power correction for lower fullpower THD  32 kHz to 192 kHz input sample rates s b O  Digital gain/attenuation +48 dB to -80 dB in 0.5-dB steps  Four output routing configurations  Four 28-bit user-programmable biquads (EQ) per channel  Selectable clock input ratio  I2C control  96 kHz internal processing sample rate, 24 to 28-bit precision  2-channel I2S input data interface  Video application supports 576 * fs input mode  Individual channel and master gain/attenuation  Individual channel and master soft/hard mute  Individual channel volume and EQ bypass Table 1. Device summary Order code Package Packaging STA32613TR PowerSO-36 EPU Tape and reel January 2016 This is information on a product in full production. DocID11531 Rev 9 1/64 www.st.com Contents STA326 Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 EQ processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 Output configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Package pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ) s t( c u d o r P Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 General interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 DC electrical specifications (3.3 V buffers) . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Power electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 e t le o s b O ) 4 Power supply and control sequencing . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 s ( t c u d o r P e 6.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 t e l o bs O 7 2/64 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3.1 DDX® power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3.2 DDX® variable compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . 29 7.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DocID11531 Rev 9 STA326 Contents 7.7 7.8 7.9 Volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.7.1 Master controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.7.2 Channel controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.7.3 Volume description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Automode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.8.1 Automodes EQ, volume, GC (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . 38 7.8.2 Automode AM/prescale/bass management scale (addr 0x0C) . . . . . . . 39 7.8.3 Preset EQ settings (addr 0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ) s t( 7.9.1 Channel 1 configuration (addr 0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.9.2 Channel 2 configuration (addr 0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.9.3 Channel 3 configuration (addr 0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 c u d Tone control (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.11 Dynamics control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 e t le 7.11.1 Limiter 1 attack/release threshold (addr 0x12) . . . . . . . . . . . . . . . . . . . 44 7.11.2 Limiter 1 attack/release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . . 44 7.11.3 Limiter 2 attack/release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . . 44 7.11.4 Limiter 2 attack/release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . . 44 7.11.5 Dynamics control description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.11.6 Anti-clipping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 o s b O ) s ( t c u d o 7.11.7 8 Dynamic range compression mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 r P e User programmable processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.1 t e l o EQ - biquad equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2 Prescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.3 Postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.4 Mix/bass management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.5 Calculating 24-bit signed fractional numbers from a dB value . . . . . . . . . 50 8.6 User-defined coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 bs O o r P 7.10 8.6.1 Coefficient address register 1 (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . 50 8.6.2 Coefficient b1data register bits 23:16 (addr 0x17) . . . . . . . . . . . . . . . . . 50 8.6.3 Coefficient b1data register bits 15:8 (addr 0x18) . . . . . . . . . . . . . . . . . . 50 8.6.4 Coefficient b1data register bits 7:0 (addr 0x19) . . . . . . . . . . . . . . . . . . . 50 8.6.5 Coefficient b2 data register bits 23:16 (addr 0x1A) . . . . . . . . . . . . . . . . 50 8.6.6 Coefficient b2 data register bits 15:8 (addr 0x1B) . . . . . . . . . . . . . . . . . 51 8.6.7 Coefficient b2 data register bits 7:0 (addr 0x1C) . . . . . . . . . . . . . . . . . . 51 DocID11531 Rev 9 3/64 64 Contents STA326 8.6.8 Coefficient a1 data register bits 23:16 (addr 0x1D) . . . . . . . . . . . . . . . . 51 8.6.9 Coefficient a1 data register bits 15:8 (addr 0x1E) . . . . . . . . . . . . . . . . . 51 8.6.10 Coefficient a1 data register bits 7:0 (addr 0x1F) . . . . . . . . . . . . . . . . . . 51 8.6.11 Coefficient a2 data register bits 23:16 (addr 0x20) . . . . . . . . . . . . . . . . 51 8.6.12 Coefficient a2 data register bits 15:8 (addr 0x21) . . . . . . . . . . . . . . . . . 51 8.6.13 Coefficient a2 data register bits 7:0 (addr 0x22) . . . . . . . . . . . . . . . . . . 51 8.6.14 Coefficient b0 data register bits 23:16 (addr 0x23) . . . . . . . . . . . . . . . . 52 8.6.15 Coefficient b0 data register bits 15:8 (addr 0x24) . . . . . . . . . . . . . . . . . 52 8.6.16 Coefficient b0 data register bits 7:0 (addr 0x25) . . . . . . . . . . . . . . . . . . 52 8.6.17 Coefficient write control register (addr 0x26) . . . . . . . . . . . . . . . . . . . . . 52 ) s t( c u d 8.7 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.8 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.9 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.10 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.11 Variable max power correction (addr 0x27, 0x28) . . . . . . . . . . . . . . . . . . 56 8.12 Fault detect recovery (addr 0x2B, 0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.13 Status (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 e t le o r P o s b O ) 9 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 s ( t c 10.1 11 u d o PowerSO-36 EPU package information . . . . . . . . . . . . . . . . . . . . . . . . . . 61 r P e Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 t e l o s b O 4/64 DocID11531 Rev 9 STA326 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 IR and MCS settings for input sample rate and clock rate . . . . . . . . . . . . . . . . . . . . . . . . . 24 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Supported serial audio input formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial input data timing characteristics (fs = 32 to 192 kHz). . . . . . . . . . . . . . . . . . . . . . . . 28 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DDX® power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DDX® output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DDX® compensating pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Postscale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Zero detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Miami mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Output configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Output configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Binary clock loss detection enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Auto-EAPD on clock loss enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Software power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Master volume offset as a function of MV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Channel volume as a function of CxV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Automode EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e s b O t e l o DocID11531 Rev 9 5/64 64 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. STA326 Automode volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Automode gain compression/limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AMPS - Automode auto prescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Automode AM switching enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Automode AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Automode crossover setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Crossover frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Preset EQ selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Channel limiter mapping selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Channel PWM output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Tone control boost/cut selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Limiter attack/release rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Limiter attack/release threshold selection (AC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Limiter attack/release threshold selection (DRC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 RAM block for biquads, mixing, and scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 TWARN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PLLUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PowerSO-36 EPU package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 ) s t( c u d e t le o s b O ) s ( t c u d o r P e t e l o s b O 6/64 DocID11531 Rev 9 o r P STA326 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Channel signal flow diagram through the digital core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Channel signal flow through the EQ block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output power-stage configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Channel separation vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 THD vs. output power - single ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 THD vs. output power - BTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 THD vs. frequency - BTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I2C write procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 General serial input and output formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Serial input data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Biquad filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Mix/bass management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Application circuit for 2.0-channel (2 BTL) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Application circuit for 2.1-channel (2 single-ended + 1 BTL) configuration. . . . . . . . . . . . . 58 Application circuit for mono-channel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PowerSO-36 EPU package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O DocID11531 Rev 9 7/64 64 Description 1 STA326 Description The STA326 comprises digital audio processing, digital amplifier control and DDX® power output stage to create a high-power single-chip DDX® solution for high-quality, high-efficiency, all-digital amplification. The STA326 power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half-bridges and a single full-bridge to give up to 2 x 40 W plus 1 x 80 W of power output. Two channels can be provided by two full-bridges to give up to 2 x 80 W of power. The IC can also be configured as a single parallel full-bridge capable of high-current operation and 1 x 160 W output. ) s t( Also provided in the STA326 is a full assortment of digital processing features. This includes up to four programmable 28-bit biquads (EQ) per channel and bass/treble tone control. Automodes enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. This includes auto volume loudness, preset volume curves, preset EQ settings and new advanced AM radio-interference reduction modes. c u d e t le o r P The serial audio data input interface accepts all possible formats, including the popular I2S format. o s b Three channels of DDX® processing are provided. This high-quality conversion from PCM audio to patented DDX® 3-state PWM switching provides over 100 dB of SNR and dynamic range. O ) s ( t c Figure 1. Block diagram u d o r P e t e l o s b O Figure 2. Channel signal flow diagram through the digital core 8/64 DocID11531 Rev 9 STA326 1.1 Description EQ processing Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ processing block. In this block, up to four user-defined biquads can be applied to each of the two channels. Prescaling, DC-blocking, high-pass, de-emphasis, bass, and tone control filters can also be applied based on various configuration parameter settings. The entire EQ block can be bypassed for all channels simultaneously by setting the DSPB bit to 1. And the CxEQBP bits can be used to bypass the EQ function on a per channel basis. Figure 3 shows the internal signal flow through the EQ block. ) s t( Figure 3. Channel signal flow through the EQ block c u d e t le 1.2 Output configurations o r P o s b O ) Figure 4. Output power-stage configurations s ( t c u d o 2-channel (full-bridge) configuration, register bits OCFG[1:0] = 00 r P e t e l o s b O 2.1-channel configuration, register bits OCFG[1:0] = 01 1-channel mono-parallel configuration, register bits OCFG[1:0] = 11 The setup register is Configuration register F (addr 0x05) on page 34 DocID11531 Rev 9 9/64 64 Pin out STA326 2 Pin out 2.1 Package pins Figure 5. Pin connections VCC_SIGN VSS VDD GND BICKI LRCKI SDI VDDA GNDA XTI PLL_FILTER RESERVED SDA SCL RESET CONFIG VL VDD_REG 2.2 1 Ob 10/64 e t le o s b SUB_GND N.C. OUT2B VCC2B N.C. GND2B GND2A VCC2A OUT2A OUT1B VCC1B GND1B GND1A N.C. VCC1A OUT1A GND_CLEAN GND_REG s ( t c Pr u d o Type o r P Table 2. Pin list Name Description SUB_GND Substrate ground 2 N.C. N.C. Not connected 3 O OUT2B Output half bridge 2B 4 I/O VCC2B Positive supply 5 N.C. N.C. Not connected 6 I/O GND2B Negative supply 7 I/O GND2A Negative supply 8 I/O VCC2A Positive supply 9 O OUT2A Output half bridge 2A 10 O OUT1B Output half bridge 1B 11 I/O VCC1B Positive supply 12 I/O GND1B Negative supply 13 I/O. GND1A Negative supply 14 N.C. N.C. Not connected DocID11531 Rev 9 ) s t( c u d I/O e t e l o s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 O ) Pin list Number 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 STA326 Pin out Table 2. Pin list Number Type Name Description 15 I/O VCC1A Positive supply 16 O OUT1A Output half bridge 1A 17 I/O GND_CLEAN Logical ground 18 I/O GND_REG Regulated ground 19 I/O VDD_REG Logic supply 20 I/O VL Logic supply 21 I CONFIG Logic levels 22 I RESET Reset 23 I SCL I2C serial clock 24 I/O SDA I2C serial data 25 RES RESERVED This pin must be connected to GND 26 I PLL_FILTER Connection to PLL filter 27 I XTI PLL input clock 28 I/O GNDA 29 I/O VDDA 30 I SDI 31 I/O 32 I 33 I/O 35 36 e t e o r P o s b Analog ground Analog supply, nominally 3.3 V -O I2S serial data channels 1 & 2 I2S left/right clock, I2S serial clock GND Digital ground VDD Digital supply, nominally 3.3 V I/O VSS 5 V regulator referred to + I/O VCC_SIGN 5 V regulator referred to ground I/O Pr c u d BICKI uc od 34 ) s t( LRCKI e t le ) s t( l o s Ob DocID11531 Rev 9 11/64 64 Pin out 2.3 STA326 Pin description OUT1A, 1B, 2A and 2B (pins 16, 10, 9 and 3) Output half bridge PWM outputs 1A, 1B, 2A and 2B provide the input signals to the speakers. CONFIG (pin 21) The configuration input pin is normally connected to ground. Using the mono high power BTL configuration requires the CONFIG input pin to be shorted to VDD_REG. RESET (pin 22) ) s t( Driving RESET low sets all outputs low and returns all register settings to their default (reset) values. The reset is asynchronous to the internal clock. c u d I2C signals (pins 23 and 24) o r P The SDA (I2C Data) and SCL (I2C Clock) pins operate according to the I2C specification (Chapter 6 on page 19 gives more information). Fast-mode (400 kB/s) I2C communication is supported. GNDA and VDDA (pins 28 and 29) e t le o s b This is the 3.3 V analog supply for the phase locked loop. It must be well decoupled and filtered for good noise immunity since the audio performance of the device depends upon the PLL circuit. O ) s ( t c CLK (pin 27) This is the master clock in used by the digital core. The master clock must be an integer multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz (256 * fs) for a 48 kHz sample rate; it is the default setting at power-up. Care must be taken to provide the device with the nominal system clock frequency; over-clocking the device may result in anomalous operation, such as inability to communicate. u d o r P e t e l o FILTER_PLL (pin 26) s b O This is the connection for external filter components for the PLL loop compensation. The schematic diagram in Figure 21 on page 57 shows the recommended circuit. BICKI (pin 32) The serial or bit clock input is for framing each data bit. The bit clock frequency is typically 64 * fs using I2S serial format. SDI_12 (pin 30) This is the serial data input where PCM audio information enters the device. Six format choices are available including I2S, left or right justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits. LRCKI (pin 31) The left/right clock input is for data word framing. The clock frequency is at the input sample rate, fs. 12/64 DocID11531 Rev 9 STA326 3 Electrical specifications Electrical specifications Table 3. Absolute maximum ratings Symbol Parameter Value Unit VDD33 3.3 V I/O power supply (pins VDDA, VDD) -0.5 to 4 V Vi Voltage on input pins -0.5 to (VDD33 + 0.5) V Vo Voltage on output pins -0.5 to (VDD33 + 0.5) V Tstg Storage temperature -40 to +150 C Tamb Ambient operating temperature -20 to +85 DC supply voltage (pins nA, nB) 40 Maximum voltage on VL (pin 20) 5.5 VMAX Table 4. Thermal data Symbol e t le Parameter ) s t( C c u d o r P Min Typ V V Max Unit Rthj-case Thermal resistance junction to case (thermal pad) - - 2.5 C/W Tj-SD Thermal shut-down junction temperature - 150 - C TWARN Thermal warning temperature - 130 - C Th-SD Thermal shut-down hysteresis - 25 - C ) s t( c u d so b O - Table 5. Recommended operating conditions Symbol VDD33 Tj e t e Parameter o r P Value Unit I/O power supply 3.0 to 3.6 V Operating junction temperature -20 to +125 C l General interface specifications o s 3.1 Ob Operating conditions VDD33 = 3.3 V ±0.3 V, Tamb = 25° C unless otherwise specified Table 6. General interface electrical characteristics Symbol Parameter Test Condition (1) Min. Typ. Max. Unit - - 1 A Vi = VDD33 (1) - - 2 A IOZ 3-state output leakage without Vi = VDD33 (1) pull-up/down - - 2 A Vesd Electrostatic protection (human-body model) 2000 - - V Iil Low level input no pull-up Vi = 0 V Iih High level input no pull-down Leakage current < 1 A 1. The leakage currents are generally very small (< 1 nA). The values given here are the maximum values after an electrostatic stress on the pin. DocID11531 Rev 9 13/64 64 Electrical specifications 3.2 STA326 DC electrical specifications (3.3 V buffers) Operating conditions VDD33 = 3.3 V ±0.3 V, Tamb = 25° C unless otherwise specified Table 7. DC electrical specifications Symbol 3.3 Parameter Test condition Min. Typ. Max. Unit VIL Low level input voltage - - - 0.8 V VIH High level input voltage - 2.0 - - V Vhyst Schmitt trigger hysteresis - 0.4 - - V Vol Low level output IoI = 2 mA - - 0.15 V Voh High level output Ioh = -2 mA VDD33 - 0.15 - V ) s t( c u d Power electrical specifications o r P Operating conditions VDD33 = 3.3 V ±0.3 V, VL = 3.3 V, = 30 V, Tamb = 25° C unless otherwise specified. e t le o s b Table 8. Power electrical characteristics Symbol 14/64 Min. Typ. Max. Unit Power Pchannel/Nchannel MOSFET RdsON Id = 1A - 200 270 m Idss Power Pchannel/Nchannel leakage Idss = 35 V - - 50 A gN Power Pchannel RdsON matching Id = 1 A 95 - - % Power Nchannel RdsON matching Id = 1 A 95 - - % Dt_s Low current dead time (static) See test circuits, Figure 6 and Figure 7 - 10 20 ns td ON Turn-on delay time Resistive load - - 100 ns td OFF Turn-off delay time Resistive load - - 100 ns tr Rise time Resistive load, Figure 6 and Figure 7 - - 25 ns tf Fall time Resistive load, Figure 6 and Figure 7 - - 25 ns Supply voltage - 10 - 36 V VL Low logical state voltage VL VL = 3.3 V 0.8 - - V VH High logical state voltage VH VL = 3.3 V - - 1.7 V I-PWRDN Supply current from in PWRDN Pin PWRDN = 0 V - - 3 mA I-hiz Supply current from in 3-state = 30 V, 3-state - 22 - mA s ( t c u d o r P e let O O ) Test conditions RdsON gP o s b Parameter DocID11531 Rev 9 STA326 Electrical specifications Table 8. Power electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit I Supply current from in operation (both channel switching) Input pulse width = 50% duty, switching frequency = 384 kHz, no LC filters 80 - mA Iout-sh Overcurrent protection threshold (short circuit current limit) - 4.5 6 - A VUV Undervoltage protection threshold - - 7 - tpw-min Output minimum pulse width No load 70 Po Output power (refer to test circuit THD = 10% RL = 4  = 21 V RL = 8  = 36 V - Po Output power (refer to test circuit THD = 1% RL = 4  = 21 V RL = 8  = 36 V - P e et l o s b O - uc d o r 50 80 40 62 ) s t( V 150 ns - W - W Figure 6. Test circuit 1 ) s t( OUTxY (3/4) c u d Low current dead time = MAX(DTr, DTf) e t le (1/2) (1/4) o r P + t DTr Duty cycle = 50% DTf M58 o s b OUTxY INxY R8W M57 O + - V67 vdc = /2 gnd Figure 7. Test circuit 2 High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 Rload=4 OUTA INA Iout=1.5A M57 Q3 DTout(B) L67 10 C69 470nF L68 10 C71 470nF C70 470nF DTin(B) OUTB INB Iout=1.5A Q4 Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure DocID11531 Rev 9 M64 M63 D06AU1651 15/64 64 Power supply and control sequencing 4 STA326 Power supply and control sequencing The recommended power-on/off sequences are shown in Figure 8 and Figure 9. Figure 8. Power-on sequence ) s t( c u d e t le o r P o s b O ) Note: 1. TR = minimum time between XTI master clock stable and Reset removal: 1 msec 2. TC = minimum time between Reset removal and I2C program, sequence start: 1msec s ( t c 3. A stable clock means: fmax - fmin < 1 MHz 4. No specific VCC and VDD_Dig turn−on sequence is required u d o r P e Figure 9. Power-off sequence t e l o s b O 5. No specific VCC and VDD_Dig turn−off sequence is required 6. This sequence ensures a pop-free turn-off 16/64 DocID11531 Rev 9 STA326 5 Characterization curves Characterization curves Figure 10. Channel separation vs. frequency ) s t( c u d e t le o r P o s b O ) s ( t c Figure 11. THD vs. output power - single ended u d o r P e t e l o s b O DocID11531 Rev 9 17/64 64 Characterization curves STA326 Figure 12. THD vs. output power - BTL ) s t( c u d e t le o s b O ) o r P Figure 13. THD vs. frequency - BTL s ( t c u d o r P e t e l o s b O 18/64 DocID11531 Rev 9 I2C bus specification STA326 I2C bus specification 6 The STA326 supports the I2C protocol. This protocol defines any device that sends data on to the I2C bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA326 is always a slave device in all of its communications. 6.1 Communication protocol ) s t( Data transition or change c u d Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition. Start condition o r P START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. e t le o s b Stop condition O ) STOP is identified by a low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA326 and the bus master. Data input s ( t c u d o During the data input the STA326 samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. t addressing Device e l o 6.2 bs O r P e To start communication between the master and the STA326, the master must initiate with a start condition. Following this, the master sends 8 bits (MSB first) onto the SDA line corresponding to the device select address and read or write mode. The 7 MSBs are the device address identifiers, corresponding to the I2C bus definition. The STA326 device address is 0x34. The 8th bit (LSB) identifies read or write operation, RW. This bit is set to 1 in read mode and 0 for write mode. After a START condition the STA326 identifies the device address on the bus. If a match is found, it acknowledges the identification on the SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address. DocID11531 Rev 9 19/64 64 I2C bus specification 6.3 STA326 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA326 acknowledges this and then the master writes the internal address byte. After receiving the internal byte address the STA326 again responds with an acknowledgement. Figure 14. I2C write procedure ) s t( c u d Byte write e t le o r P In the byte write mode the master sends one data byte. This is acknowledged by the STA326. The master then terminates the transfer by generating a STOP condition. o s b Multi-byte write The multi-byte write modes can start from any internal address. Sequential data byte writes will be written to sequential addresses within the STA326. O ) The master generating a STOP condition terminates the transfer. 6.4 s ( t c Read operation u d o r P e t ole Figure 15. I2C read procedure s b O Current address byte read Following the START condition the master sends a device select code with the RW bit set to 1. The STA326 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. 20/64 DocID11531 Rev 9 I2C bus specification STA326 Current address multi-byte read The multi-byte read modes can start from any internal address. Sequential data bytes will be read from sequential addresses within the STA326. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer. Random address byte read Following the START condition the master sends a device select code with the RW bit set to 0. The STA326 acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA326 again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA326 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. ) s t( c u d Random address multi-byte read o r P The multi-byte read modes could start from any internal address. Sequential data bytes will be read from sequential addresses within the STA326. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer. e t le o s b O ) s ( t c u d o r P e t e l o s b O DocID11531 Rev 9 21/64 64 Register description 7 STA326 Register description You must not reprogram the register bits marked “Reserved”. It is important that these bits keep their default reset values. Table 9. Register summary Address Name D7 D6 D5 D4 D3 D2 D1 D0 0x00 CONFA FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0 0x01 CONFB C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0 0x02 CONFC Reserved CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 0x03 CONFD MME ZDE DRC BQL PSL DSPB DEMP 0x04 CONFE SVE ZCE Reserved PWMS AME Reserved MPC 0x05 CONFF EAPD PWDN ECLE 0x06 MMUTE Reserved Reserved Reserved Reserved Reserved Reserved Reserved MMUTE 0x07 MVOL MV7 MV6 MV5 MV4 0x08 C1VOL C1V7 C1V6 C1V5 C1V4 0x09 C2VOL C2V7 C2V6 C2V5 C2V4 0x0A C3VOL C3V7 C3V6 C3V5 C3V4 0x0B AUTO1 AMPS Reserved AMGC1 0x0C AUTO2 XO3 XO2 0x0D AUTO3 Reserved Reserved Reserved PEQ4 0x0E C1CFG C1OM1 0x1F C2CFG C2OM1 0x10 C3CFG 0x11 XO1 eP OCFG1 MPCV OCFG0 t e l o MV1 MV0 C1V2 C1V1 C1V0 C2V3 C2V2 C2V1 C2V0 C3V3 C3V2 C3V1 C3V0 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0 XO1 AMAM2 AMAM1 AMAM0 AMAME PEQ3 PEQ2 PEQ1 PEQ0 bs MV3 ro IDE HPB MV2 O ) s ( t c du Reserved BCLE c u d ) s t( OM0 C1V3 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VBP Reserved Reserved TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0 L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0 0x13 let L1ATRT L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0 0x14 L2AR L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0 0x15 L2ATRT L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0 0x16 CFADDR2 CFA7 CFA6 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0 0x17 B1CF1 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16 0x18 B1CF2 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8 0x19 B1CF3 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0 0x1A B2CF1 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16 0x1B B2CF2 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8 0x1C B2CF3 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0 0x1D A1CF1 C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16 0x12 TONE o s b O 22/64 L1AR ro eP DocID11531 Rev 9 STA326 Register description Table 9. Register summary (continued) Address Name D7 D6 D5 D4 D3 D2 D1 D0 0x1E A1CF2 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8 0x1F A1CF3 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0 0x20 A2CF1 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16 0x21 A2CF2 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8 0x22 A2CF3 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0 0x23 B0CF1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16 0x24 B0CF2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8 0x25 B0CF3 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 0x26 CFUD Reserved Reserved Reserved Reserved RA R1 WA 0x27 MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 0x28 MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 0x29 Reserved 1 1 1 1 0 0 0x2A Reserved 0 0 1 1 0 0x2B FDRC1 FDRC15 FDRC14 FDRC13 FDRC12 0x2C FDRC2 FDRC7 FDRC6 FDRC5 0x2D Status PLLUL e t le so od Pr W1 MPCC8 MPCC1 MPCC0 1 1 1 1 FDRC11 FDRC10 FDRC9 FDRC8 FDRC3 FDRC2 FDRC1 FDRC0 Reserved Reserved Reserved Reserved Reserved FAULT TWARN Ob FDRC4 ) s A (addr 0x00) Configuration register ( t c u d o r P e t ole 7.1 0 uc ) s t( C5B0 D7 D6 D5 D4 D3 D2 D1 D0 FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0 0 1 1 0 0 0 1 1 Table 10. Master clock select Bit O bs R/W RST Name Description Master clock select: Selects the ratio between the input 0 RW 1 MCS0 I2S sample frequency and the input clock. 1 RW 1 MCS1 - 2 RW 0 MCS2 - The STA326 will support sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192 kHz. Therefore the internal clock will be:  32.768 MHz for 32 kHz  45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz  49.152 MHz for 48 kHz, 96 kHz, and 192 kHz The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). The correlation between the input clock and the input sample rate is determined by the status of the MCSx bits and the IR (input rate) register bits. The MCSx DocID11531 Rev 9 23/64 64 Register description STA326 bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally. Table 11. IR and MCS settings for input sample rate and clock rate MCS[2:0] Input sample rate IR fs (kHz) 000 001 010 011 100 101 32, 44.1, 48 00 768 fs 512 fs 384 fs 256 fs 128 fs 576 fs 88.2, 96 01 384 fs 256 fs 192 fs 128 fs 64 fs - 176.4, 192 1X 384 fs 256 fs 192 fs 128 fs 64 fs - Table 12. Interpolation ratio select Bit 4:3 R/W RST RW 00 Name ) s t( c u d Description o r P Interpolation ratio select: selects internal interpolation ratio based on input I2S sample frequency IR[1:0] e t le The STA326 has variable interpolation (re-sampling) settings such that internal processing and DDX® output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a downsample by a factor of 2. o s b The IR bits determine the re-sampling ratio of this interpolation. O ) Table 13. IR bit settings as a function of input sample rate t(s Input sample rate fs (kHz) uc 32 2 times oversampling 00 2 times oversampling 00 2 times oversampling 01 Pass-through 01 Pass-through 176.4 10 Downsampling by 2 192 10 Downsampling by 2 48 88.2 e t le 96 Ob 1st stage interpolation ratio 00 od 44.1 so IR[1,0] Pr Table 14. Thermal warning recovery bypass Bit 5 R/W RST RW 1 Name TWRB Description Thermal warning recovery bypass: 0: thermal warning recovery enabled 1: thermal warning recovery disabled If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery will determine if the adjustment is removed when thermal warning is negative. If TWRB = 0 and TWAB = 0, then when a thermal warning disappears the gain adjustment determined by the thermal warning postscale (default = -3 dB) will be removed and the gain will be added back to the system. If TWRB = 1 and TWAB = 0, then when a thermal warning 24/64 DocID11531 Rev 9 STA326 Register description disappears the thermal warning postscale gain adjustment will remain until TWRB is changed to zero or the device is reset. Table 15. Thermal warning adjustment bypass Bit 6 R/W RW RST 1 Name Description Thermal warning adjustment bypass: 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled TWAB The on-chip STA326 power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period greater than 400 ms, the power control block will force an adjustment to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning volume adjustment is applied, whether the gain is reapplied when TWARN is de-asserted is dependent on the TWRB bit. ) s t( o r P Table 16. Fault detect recovery bypass Bit 7 R/W RW RST 0 e t e Name c u d Description l o s Fault detector recovery bypass: 0: fault detector recovery enabled 1: fault detector recovery disabled FDRB b O - The DDX® power block can provide feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either overcurrent or thermal). When FAULT is asserted (set to 0), the power control block will attempt a recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power output block to begin recovery). It holds it at 0 for period of time in the range of 0.1 ms to 1 s as defined by the fault-detect recovery constant register (FDRC registers 0x29 to 0x2A), then toggle it back to 1. This sequence is repeated as log as the fault indication exists. This feature is enabled by default but can be bypassed by setting the FDRB control bit to 1. ) s t( c u d e t le o r P o s b O DocID11531 Rev 9 25/64 64 Register description 7.2 STA326 Configuration register B (addr 0x01) D7 D6 D5 D4 D3 D2 D1 D0 C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0 1 0 0 0 0 0 0 0 This register configures the serial data interface Table 17. Serial audio input interface format Bit R/W RST Name Description 3:0 RW 0000 SAI[3:0] Serial audio input interface format: determines the interface format of the input serial digital audio interface (see below). 4 RW 0 SAIFB Data format: 0: MSB first1: LSB first ) s t( c u d o r P The STA326 serial audio input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA326 always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 31), serial clock BICKI (pin 32), and serial data SDI (pin 30). e t le o s b SAI[3:0] and SAIFB are used to specify the serial data format. The default format is I2S, MSB-first. Available formats are shown below in Figure 16 and the tables that follow. O ) Figure 16. General serial input and output formats s ( t c u d o r P e t e l o s b O Table 18 lists the serial audio input formats supported by STA326 when BICKI = 32 * fs, 48 * fs and 64 * fs, where the sampling rate fs = 32, 44.1, 48, 88.2, 96, 176.4 or 192 kHz. 26/64 DocID11531 Rev 9 STA326 Register description Table 18. Supported serial audio input formats BICKI 32 * fs 48 * fs 64 * fs SAI [3:0] SAIFB 1100 X I2S 15-bit data 1110 X Left/right justified 16-bit data 0100 X I2S 23-bit data 0100 X I2S 20-bit data 1000 X I2S 18-bit data 0100 0 MSB first I2S 16-bit data 1100 1 LSB first I2S 16-bit data 0001 X Left-justified 24-bit data 0101 X Left-justified 20-bit data 1001 X Left-justified 18-bit data 1101 X Left-justified 16-bit data 0010 X Right-justified 24-bit data 0110 X Right-justified 20-bit data 1010 X 1110 X 0000 X o s b ) s ( 0100 X -O I2S 24-bit data I2S 20-bit data MSB first I2S 16-bit data 1 LSB first I2S 16-bit data 0001 X Left-justified 24-bit data 0101 X Left-justified 20-bit data 1001 X Left-justified 18-bit data 1101 X Left-justified 16-bit data 0010 X Right-justified 24-bit data 0110 X Right-justified 20-bit data 1010 X Right-justified 18-bit data 1110 X Right-justified 16-bit data od 1100 Ob Right-justified 16-bit data 0 t c u Pr c u d Right-justified 18-bit data I2S 18-bit data 0000 l o s e t le ) s t( o r P X 1000 e t e Interface format For example, SAI = 1110 and SAIFB = 1 would specify right-justified 16-bit data, LSB-first. DocID11531 Rev 9 27/64 64 Register description STA326 Table 19. Serial input data timing characteristics (fs = 32 to 192 kHz) Parameter in Figure 17 Value BICKI frequency (slave mode) 12.5 MHz max. BICKI pulse width low (T0) (slave mode) 40 ns min. BICKI pulse width high (T1) (slave mode) 40 ns min. BICKI active to LRCKI edge delay (T2) 20 ns min. BICKI active to LRCKI edge delay (T3) 20 ns min. SDI valid to BICKI active setup (T4) 20 ns min. BICKI active to SDI hold time (T5) 20 ns min. c u d Figure 17. Serial input data timing e t le ) s t( o r P o s b O ) Table 20. Delay serial clock enable Bit 5 Ob R/W Name uc od 0 r P e Bit t(s RST RW let so R/W DSCKE Description Delay serial clock enable: 0: no serial clock delay 1: serial clock delay by 1 core clock cycle to tolerate anomalies in some I2S master devices Table 21. Channel input mapping RST Name Description 6 RW 0 C1IM 0: processing channel 1 receives left I2S input 1: processing channel 1 receives right I2S input 7 RW 1 C2IM 0: processing channel 2 receives left I2S input 1: processing channel 2 receives right I2S input Each channel received via I2S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I2S input channel to its corresponding processing channel. 28/64 DocID11531 Rev 9 STA326 7.3 Register description Configuration register C (addr 0x02) D7 D6 D5 D4 D3 D2 D1 D0 Reserved CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 1 1 0 0 0 0 1 0 DDX® power output mode 7.3.1 Table 22. DDX® power output mode Bit 1:0 R/W RST RW 10 Name Description DDX® power output mode: Selects configuration of DDX® output OM[1:0] ) s t( c u d The DDX® power output mode selects how the DDX® output timing is configured. Different power devices can use different output modes. The recommended use is OM = 10. When OM = 11 the CSZ bits determine the size of the DDX® compensating pulse. e t le Table 23. DDX® output modes so OM[1,0] 00 b O Not used 01 o r P Output stage - mode Not used ) s ( 10 ct 11 u d o Recommended Variable compensation DDX® variable compensating pulse size 7.3.2 r P e The DDX® variable compensating pulse size is intended to adapt to different power stage ICs. Contact ST for support when deciding this function. t e l o O bs Table 24. DDX® compensating pulse CSZ[4:0] Compensating pulse size 00000 0 clock period compensating pulse size 00001 1 clock period compensating pulse size … … 10000 16 clock period compensating pulse size … … 11111 31 clock period compensating pulse size DocID11531 Rev 9 29/64 64 Register description 7.4 STA326 Configuration register D (addr 0x03) D7 D6 D5 D4 D3 D2 D1 D0 MME ZDE DRC BQL PSL DSPB DEMP HPB 0 1 0 0 0 0 0 0 Table 25. High-pass filter bypass Bit 0 R/W RW RST 0 Name Description High-pass filter bypass bit. 0: AC coupling high pass filter enabled 1: AC coupling high pass filter disabled HPB ) s t( c u d The STA326 features an internal digital high-pass filter for the purpose of DC Blocking. The purpose of this filter is to prevent DC signals from passing through a DDX® amplifier. DC signals can cause speaker damage. Table 26. De-emphasis Bit 1 R/W RW RST e t le 0 Name o r P Description De-emphasis: 0: no de-emphasis 1: de-emphasis o s b DEMP O ) By setting this bit to 1, the de-emphasis will be implemented on all channels. DSPB, bit D2 of CONFD (configuration register D), must be set to 0 for de-emphasis to function. s ( t c Bit e t le 2 o s b du o r P R/W RW RST 0 Table 27. DSP bypass Name Description DSP bypass bit: 0: normal Operation 1: bypass of EQ and mixing functionality DSPB Setting the DSPB bit bypasses all the EQ and mixing functionality of the STA326 core. O Table 28. Postscale link Bit 3 R/W RW RST 0 Name PSL Description Postscale link: 0: each channel uses individual postscale value 1: each channel uses channel 1 postscale value Postscale functionality is an attenuation placed after the volume control and directly before the conversion to PWM. Postscale can also be used to limit the maximum modulation index and therefore the peak current. A setting of 1 in the PSL register will result in the use of the value stored in channel 1 postscale for all three internal channels. 30/64 DocID11531 Rev 9 STA326 Register description Table 29. Biquad coefficient link Bit 4 R/W RW RST 0 Name Description Biquad link: 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values BQL For ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once. ) s t( Table 30. Dynamic range compression/anti-clipping bit Bit 5 R/W RW RST 0 Name Description c u d Dynamic range compression/anti-clipping 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode DRC e t le o r P Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level. o s b O ) Table 31. Zero detect mute enable Bit 6 R/W s ( t c RST u d o RW 1 Name ZDE Description Zero detect mute enable: setting of 1 enables the automatic zero-detect mute r P e Setting the ZDE bit enables the zero-detect automatic mute. When ZDE = 1, the zero detect circuit looks at the input data to each processing channel after the channel-mapping block. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. s b O t e l o Bit 7 Table 32. Miami mode enable R/W RW RST 0 Name MME Description Miami mode enable: 0: sub mix into left/right disabled 1: sub mix into left/right enabled DocID11531 Rev 9 31/64 64 Register description 7.5 STA326 Configuration register E (addr 0x04) D7 D6 D5 D4 D3 D2 D1 D0 SVE ZCE Reserved PWMS AME Reserved MPC MPCV 1 1 0 0 0 0 1 0 Table 33. Max power correction variable Bit 0 R/W RW RST 0 Name Description Max power correction variable: 0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient MPCV ) s t( By enabling MPC and setting MPCV = 1, the max power correction becomes variable. By adjusting the MPCC registers (address 0x27, 0x28) it becomes possible to adjust the THD at maximum unclipped power to a lower value for a particular application. o r P Table 34. Max power correction Bit 1 R/W RW RST 1 e t e Name c u d Description l o s Max power correction: 0: MPC disabled 1: MPC enabled MPC b O - Setting the MPC bit corrects the DDX® power device at high power. This mode lowers the THD+N of a full DDX® system at maximum power output and slightly below. Bit 3 so e t le Ob Pr RW uc od R/W ) s t( RST 0 Table 35. AM mode enable Name Description AM mode enable: 0: normal DDX® operation. 1: AM reduction mode DDX® operation. AME The STA326 features a DDX® processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when DDX® is operating in a device with an active AM tuner. The SNR of the DDX® processing is reduced to approximately 83 dB in this mode, which is still greater than the SNR of AM radio. Table 36. PWM speed mode Bit 4 32/64 R/W RW RST 0 Name PWMS Description PWM output speed selection: 0: normal speed (384 kHz) all channels 1: odd speed (341.3 kHz) all channels DocID11531 Rev 9 STA326 Register description Table 37. Zero-crossing volume enable Bit 6 R/W RW RST 1 Name Description Zero-crossing volume enable: 1: volume adjustments will only occur at digital zerocrossings 0: volume adjustments will occur immediately ZCE The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible. ) s t( Table 38. Soft volume update enable Bit 7 R/W RW RST 1 Name Description c u d Soft volume enable: 1: volume adjustments will use soft volume 0: volume adjustments will occur immediately SVE e t le o r P The STA326 includes a soft volume algorithm that will step through the intermediate volume values at a predetermined rate when a volume change occurs. By setting SVE = 0 this can be bypassed and volume changes will jump from old to new value directly. This feature is only available if individual channel volume bypass bit is set to 0. o s b O ) s ( t c u d o r P e t e l o s b O DocID11531 Rev 9 33/64 64 Register description 7.6 STA326 Configuration register F (addr 0x05) D7 D6 D5 D4 D3 D2 D1 D0 EAPD PWDN ECLE Reserved BCLE IDE OCFG1 OCFG0 0 1 0 1 1 1 0 0 Table 39. Output configuration selection Bit 1:0 R/W RST RW Name 00 OCFG[1:0] Description Output configuration selection 00: 2-channel (full-bridge) power, 1-channel DDX® is default Table 40. Output configuration selection OCFG[1:0] 01 2 (half-bridge) and 1 (full-bridge) on-board power: 1A  1A binary 2A  1B binary 3A/3B  2A/2B binary 10 Reserved 11 1 channel mono-parallel: 3A  1A/1B 3B  2A/2B e t e Ob 2 o s b O ) s ( t c u d o l o s o r P 00 2 channel (full-bridge) power, 1 channel DDX®: 1A/1B  1A/1B 2A/2B  2A/2B Bit c u d Output power configuration e t le ) s t( Pr R/W RW Table 41. Invalid input detect mute enable RST 1 Name Description Invalid input detect auto-mute enable: 0: disabled 1: enabled IDE Setting the IDE bit enables this function, which looks at the input I2S data and clocking and will automatically mute all outputs if the signals are perceived as invalid. Table 42. Binary clock loss detection enable Bit 3 R/W RW RST 1 Name BCLE Description Binary output mode clock loss detection enable 0: disabled 1: enabled Detects loss of input MCLK in binary mode and will output 50% duty cycle to prevent audible artifacts when input clocking is lost. 34/64 DocID11531 Rev 9 STA326 Register description Table 43. Auto-EAPD on clock loss enable Bit 5 R/W RW RST 0 Name Description Auto EAPD on clock loss 0: disabled 1: enabled ECLE When ECLE is active, it issues a power device power down signal (EAPD) on clock loss detection. Table 44. Software power down Bit 6 R/W RW RST 1 Name ) s t( Description c u d Software power down: 0: power down mode: initiates a power-down sequence which results in a soft mute of all channels and finally asserts EAPD circa 260 ms later 1: normal operation PWDN e t le o r P Table 45. External amplifier power down Bit 7 R/W RW RST o s b 0 Name Description External amplifier power down: 0: external power stage power down active 1: normal operation O ) EAPD s ( t c EAPD is used to actively power down a connected DDX® power device. This register has to be written to 1 at start-up to enable the DDX® power device for normal operation. u d o r P e t e l o s b O DocID11531 Rev 9 35/64 64 Register description STA326 7.7 Volume control 7.7.1 Master controls Master mute register (addr 0x06) D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved MMUTE 0 0 0 1 0 0 0 0 Master volume register (addr 0x07) D7 D6 D5 D4 D3 D2 D1 MV7 MV6 MV5 MV4 MV3 MV2 MV1 1 1 1 1 1 1 1 uc ) s t( d o r D0 MV0 1 Note: Value of volume derived from MVOL is dependent on AMV Automode volume settings. 7.7.2 Channel controls Channel 1 volume (addr 0x08) D7 D6 D5 D4 C1V7 C1V6 C1V5 C1V4 0 1 1 0 ) (s Channel 2 volume (addr 0x09) D7 D6 C2V7 C2V6 ct u d o 0 r P e 1 P e et l o s Ob D3 D2 D1 D0 C1V3 C1V2 C1V1 C1V0 0 0 0 0 D5 D4 D3 D2 D1 D0 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0 1 0 0 0 0 0 Channel 3 volume (addr 0x0A) s b O t e l o 7.7.3 D7 D6 D5 D4 D3 D2 D1 D0 C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0 0 1 1 0 0 0 0 0 Volume description The volume structure of the STA326 consists of individual volume registers for each of the three channels and a master volume register, and individual channel volume trim registers. The channel volume settings are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels. These values are normally set at the initialization of the IC and not changed. The individual channel volumes are adjustable in 0.5-dB steps from +48 dB to -80 dB. The master volume control is normally mapped to the master volume of the system. The values of these two settings are summed to find the actual gain/volume value for any given channel. When set to 1, the master mute will mute all channels, whereas the individual channel mutes (CxM) will mute only that channel. Both the master mute and the channel mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 kHz). A “hard mute” can be obtained by programming the value 0xFF to any channel volume register or 36/64 DocID11531 Rev 9 STA326 Register description the master volume register. When volume offsets are provided via the master volume register any channel whose total volume is less than -100 dB will be muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration register E) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE = 0, volume updates will occur immediately. The STA326 also features a soft-volume update function that will ramp the volume between intermediate values when the value is updated, when SVE = 1 (configuration register E). This feature can be disabled by setting SVE = 0. Each channel also contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. Also, master soft-mute will not affect the channel if CxVBP = 1. ) s t( c u d Each channel also contains a channel mute. If CxM = 1 a soft mute is performed on that channel o r P Table 46. Master volume offset as a function of MV[7:0] MV[7:0] Volume offset from channel value 00000000 (0x00) 0 dB 00000001 (0x01) -0.5 dB 00000010 (0x02) -1 dB … … 01001100 (0x4C) -38 dB … u d o 11111111 (0xFF) r P e s b O t e l o o s b O ) s ( t c … 11111110 (0xFE) e t le -127 dB Hard master mute Table 47. Channel volume as a function of CxV[7:0] CxV[7:0] Volume 00000000 (0x00) +48 dB 00000001 (0x01) +47.5 dB 00000010 (0x02) +47dB … … 01100001 (0x5F) +0.5 dB 01100000 (0x60) 0 dB 01011111 (0x61) -0.5 dB … … 11111110 (0xFE) -79.5 dB 11111111 (0xFF) Hard channel mute DocID11531 Rev 9 37/64 64 Register description STA326 7.8 Automode registers 7.8.1 Automodes EQ, volume, GC (addr 0x0B) D7 D6 D5 D4 D3 D2 D1 D0 AMPS Reserved AMGC1 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0 1 0 0 0 0 0 0 0 Table 48. Automode EQ AMEQ[1,0] Mode (biquad 1-4) 00 User programmable 01 Preset EQ - PEQ bits 10 Auto volume controlled loudness curve 11 Not used ) s t( c u d o r P By setting AMEQ to any setting other than 00 enables Automode EQ where biquads 1-4 are not user programmable. Any coefficient settings for these biquads are ignored. Also when Automode EQ is used the prescale value for channels 1-2 becomes hard-set to -18 dB. e t le o s b Table 49. Automode volume AMV[1,0] O ) 00 MVOL 0.5 dB 256 steps (standard) t(s 01 MVOL auto curve 30 steps uc 10 11 Ob 00 od r P e let so Mode (MVOL) MVOL auto curve 40 steps MVOL auto curve 50 steps Table 50. Automode gain compression/limiters AMGC[1:0] Mode User programmable GC 01 AC no clipping 10 AC limited clipping (10%) 11 DRC nighttime listening mode Table 51. AMPS - Automode auto prescale Bit 7 38/64 R/W RW RST 1 Name AMPS Description Automode prescale 0: -18 dB used for prescale when AMEQ neq 00 1: user-defined prescale when AMEQ neq 00 DocID11531 Rev 9 STA326 7.8.2 Register description Automode AM/prescale/bass management scale (addr 0x0C) D7 D6 D5 D4 D3 D2 D1 D0 XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME 0 0 0 0 0 0 0 0 Table 52. Automode AM switching enable Bit R/W RST Name Description 0 RW 0 AMAME Automode AM enable 0: switching frequency determined by PWMS setting 1: switching frequency determined by AMAM settings 3:1 RW 000 AMAM[2:0] AM switching frequency setting 000: default n ) s t( c u d Table 53. Automode AM switching frequency selection AMAM[2:0] 48 kHz/96 kHz input fs o r P 44.1 kHz/88.2 kHz input fs e t le 000 0.535 MHz -0.720 MHz 001 0.721 MHz -0.900 MHz 010 0.901 MHz -1.100 MHz 011 1.101 MHz -1.300 MHz 1.001 MHz -1.180 MHz 100 1.301 MHz -1.480 MHz 1.181 MHz -1.340 MHz o s b O ) s ( t c 101 110 0.535 MHz -0.670 MHz 0.671 MHz -0.800 MHz 0.801 MHz -1.000 MHz 1.481 MHz -1.600 MHz 1.341 MHz -1.500 MHz 1.601 MHz -1.700 MHz 1.501 MHz - 1.700 MHz u d o When DDX® is used concurrently with an AM radio tuner, it is advisable to use the AMAM bits to automatically adjust the output PWM switching rate dependent upon the specific radio frequency that the tuner is receiving. The values used in AMAM are also dependent upon the sample rate determined by the ADC used. r P e s b O t e l o Bit 7:4 Table 54. Automode crossover setting R/W RW RST 0 Name Description Automode crossover frequency selection 000: user-defined crossover coefficients are used Otherwise: preset coefficients for the crossover setting desired XO[3:0] Table 55. Crossover frequency selection XO[2:0] Bass management - Crossover frequency 0000 User 0001 80 Hz 0010 100 Hz 0011 120 Hz DocID11531 Rev 9 39/64 64 Register description STA326 Table 55. Crossover frequency selection (continued) XO[2:0] 7.8.3 Bass management - Crossover frequency 0100 140 Hz 0101 160 Hz 0110 180 Hz 0111 200 Hz 1000 220 Hz 1001 240 Hz 1010 260 Hz 1011 280 Hz 1100 300 Hz 1101 320 Hz 1110 340 Hz 1111 360 Hz ) s t( c u d Preset EQ settings (addr 0x0D) D7 D6 D5 D4 Reserved Reserved Reserved PEQ4 0 0 0 0 e t le o s b O ) s ( t c D3 D2 D1 D0 PEQ3 PEQ2 PEQ1 PEQ0 0 0 0 0 Table 56. Preset EQ selection PEQ[4:0] 00000 00001 e t e 00010 ol s b O 40/64 Pr u d o Flat Rock Soft rock 00011 Jazz 00100 Classical 00101 Dance 00110 Pop 00111 Soft 01000 Hard 01001 Party 01010 Vocal 01011 Hip-hop 01100 Dialog 01101 Bass-boost #1 01110 Bass-boost #2 01111 Bass-boost #3 DocID11531 Rev 9 o r P Setting STA326 Register description Table 56. Preset EQ selection (continued) PEQ[4:0] Setting 10000 Loudness 1 (least boost) 10001 Loudness 2 10010 Loudness 3 10011 Loudness 4 10100 Loudness 5 10101 Loudness 6 10110 Loudness 7 10111 Loudness 8 11000 Loudness 9 11001 Loudness 10 11010 Loudness 11 11011 Loudness 12 11100 Loudness 13 11101 Loudness 14 11110 Loudness 15 11111 Loudness 16 (most boost) ) s t( c u d e t le o s b O ) s ( t c 7.9 Channel configuration registers 7.9.1 Channel 1 configuration (addr 0x0E) O 7.9.3 D7 u d o D6 D5 D4 D3 D2 D1 D0 C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB 0 0 0 0 0 0 0 0 r P e let o s b 7.9.2 o r P Channel 2 configuration (addr 0x0F) D7 D6 D5 D4 D3 D2 D1 D0 C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB 0 1 0 0 0 0 0 0 Channel 3 configuration (addr 0x10) D7 D6 D5 D4 D3 D2 D1 D0 C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VBP Reserved Reserved 1 0 0 0 0 0 0 0 EQ control can be bypassed on a per channel basis. If EQ control is bypassed on a given channel the prescale and all 9 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combination) are bypassed for that channel. DocID11531 Rev 9 41/64 64 Register description STA326 CxEQBP   0: perform EQ on channel X - normal operation 1: bypass EQ on channel X Tone control (bass/treble) can be bypassed on a per channel basis. If tone control is bypassed on a given channel the two filters that tone control utilizes are bypassed. CxTCB   0: perform tone control on channel X - (default operation) 1: bypass tone control on channel X Each channel can be configured to output either the patented DDX® PWM data or standard binary PWM encoded data. By setting the CxBO bit to 1, each channel can be individually controlled to be in binary operation mode. ) s t( c u d Also, there is the capability to map each channel independently onto any of the two limiters available within the STA326 or even not map it to any limiter at all (default mode). o r P Table 57. Channel limiter mapping selection e t le CxLS[1,0] Channel limiter mapping 00 Channel has limiting disabled 01 Channel is mapped to limiter #1 10 Channel is mapped to limiter #2 o s b O ) s ( t c Each PWM output channel can receive data from any channel output of the volume block. Which channel a particular PWM output receives is dependent upon that channel’s CxOM register bits. u d o r P e Table 58. Channel PWM output mapping CxOM[1:0] let 00 o s b O 42/64 01 PWM output from Channel 1 Channel 2 10 Channel 3 11 Not used DocID11531 Rev 9 STA326 7.10 Register description Tone control (addr 0x11) D7 D6 D5 D4 D3 D2 D1 D0 TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0 0 1 1 1 0 1 1 1 Table 59. Tone control boost/cut selection BTC[3:0]/TTC[3:0] Boost/Cut 0000 -12 dB 0001 -12 dB … … 0111 -4 dB 0110 -2 dB 0111 0 dB 1000 +2 dB 1001 +4 dB … … 1101 +12 dB 1110 +12 dB ) s t( c u d e t le o r P o s b O ) 1111 +12 dB s ( t c u d o r P e t e l o s b O DocID11531 Rev 9 43/64 64 Register description STA326 7.11 Dynamics control 7.11.1 Limiter 1 attack/release threshold (addr 0x12) 7.11.2 7.11.3 7.11.4 7.11.5 D7 D6 D5 D4 D3 D2 D1 D0 L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0 0 1 1 0 1 0 1 0 Limiter 1 attack/release threshold (addr 0x13) D7 D6 D5 D4 D3 D2 D1 L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 0 1 1 0 1 0 0 D7 D6 D5 D4 D3 L2A2 L2A1 L2A0 L2R3 L2R2 0 1 1 0 1 0 ro D2 l o s P e et ) s t( c u d Limiter 2 attack/release rate (addr 0x14) L2A3 D0 L1RT0 1 D1 D0 L2R1 L2R0 1 0 Limiter 2 attack/release threshold (addr 0x15) D7 D6 D5 L2AT3 L2AT2 L2AT1 0 1 1 Ob D4 L2AT0 )- 0 D3 D2 D1 D0 L2RT3 L2RT2 L2RT1 L2RT0 1 0 0 1 s ( t c Dynamics control description u d o The STA326 includes 2 independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode, or to actively reduce the dynamic range for a better listening environment (such as a night-time listening mode, which is often needed for DVDs.) The two modes are selected via the DRC bit in configuration register D (bit 5, address 0x03). Each channel can be mapped to Limiter1, Limiter2, or not mapped. r P e t e l o s b O If a channel is not mapped, that channel will clip normally when 0 dBFS is exceeded. Each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then if needed adjust the gain of the mapped channels in unison. The limiter attack thresholds are determined by the LxAT registers. When the attack threshold has been exceeded, the limiter, when active, will automatically start reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The gain reduction occurs on a peak-detect algorithm. The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is increased at a rate dependent upon the release rate register. The gain can never be increased past its set value and therefore the release will only occur if the limiter has already reduced the gain. The 44/64 DocID11531 Rev 9 STA326 Register description release threshold value can be used to set what is effectively a minimum dynamic range. This is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”. In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. Figure 18. Basic limiter and volume flow diagram ) s t( c u d e t le o r P o s b Table 60. Limiter attack/release rate selection dB/ms 0000 3.1584 0001 2.7072 0001 0.1370 2.2560 0010 0.0744 1.8048 0011 0.0499 0100 1.3536 0100 0.0360 0101 0.9024 0101 0.0299 0110 0.4512 0110 0.0264 0111 0.2256 0111 0.0208 1000 0.1504 1000 0.0198 1001 0.1123 1001 0.0172 1010 0.0902 1010 0.0147 1011 0.0752 1011 0.0137 1100 0.0645 1100 0.0134 1101 0.0564 1101 0.0117 1110 0.0501 1110 0.0110 1111 0.0451 1111 0.0104 du ro eP let Fast dB/ms 0.5116 0011 O s ( t c Release rate LxR[3:0] 0000 0010 o s b O ) Attack rate LxA[3:0] Slow DocID11531 Rev 9 45/64 64 Register description 7.11.6 STA326 Anti-clipping mode Table 61. Limiter attack/release threshold selection (AC mode) Attack threshold (AC) LxAT[3:0] dB relative to FS dB relative to FS 0000 -12 0000 - 0001 -10 0001 -29 dB 0010 -8 0010 -20 dB 0011 -6 0011 -16 dB 0100 -4 0100 -14 dB 0101 -2 0101 -12 dB 0110 0 0110 -10 dB 0111 +2 0111 -8 dB 1000 +3 1000 -7 dB 1001 +4 1001 1010 +5 1010 1011 +6 1100 +7 1101 +8 1110 +9 1111 +10 e t e ol 1011 bs O ) s ( t c -6 dB -5 dB -4 dB -3 dB 1101 -2 dB 1110 -1 dB 1111 -0 dB r P e t e l o s b O DocID11531 Rev 9 ) s t( c u d o r P 1100 u d o 46/64 Release threshold (AC) LxRT[3:0] STA326 7.11.7 Register description Dynamic range compression mode Table 62. Limiter attack/release threshold selection (DRC mode) Attack threshold (DRC) LxAT[3:0] Release threshold (DRC) dB relative to volume LxRT[3:0] db relative to volume + LxAT 0000 -31 0000 - 0001 -29 0001 -38 dB 0010 -27 0010 -36 dB 0011 -25 0011 -33 dB 0100 -23 0100 -31 dB 0101 -21 0101 -30 dB 0110 -19 0110 -28 dB 0111 -17 0111 -26 dB 1000 -16 1000 -24 dB 1001 -15 1001 1010 -14 1010 1011 -13 1100 -12 1101 -10 1110 -7 1111 -4 ol e t e 1011 bs O ) s ( t c ) s t( c u d o r P -22 dB -20 dB -18 dB 1100 -15 dB 1101 -12 dB 1110 -9 dB 1111 -6 dB u d o r P e t e l o s b O DocID11531 Rev 9 47/64 64 User programmable processing STA326 8 User programmable processing 8.1 EQ - biquad equation The biquads use the equation that follows. This is depicted in Figure 19 below. Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n - 1] + b2X[n - 2] - 2(a1/2)Y[n - 1] - a2Y[n - 2] = b0X[n] + b1X[n - 1] + b2X[n - 2] - a1Y[n - 1] - a2Y[n - 2] where Y[n] represents the output and X[n] represents the input. Multipliers are 28-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0.9999998808). ) s t( Coefficients stored in the user-defined coefficient RAM are referenced in the following manner:  CxHy0 = b1/2  CxHy1 = b2  CxHy2 = -a1/2  CxHy3 = -a2  CxHy4 = b0/2 c u d e t le o r P o s b The x represents the channel and the y the biquad number. For example C3H41 is the b0/2 coefficient in the fourth biquad for channel 3 O ) Figure 19. Biquad filter s ( t c u d o r P e 8.2 s b O t e l o Prescale 8.3 The prescale block which precedes the first biquad is used for attenuation when filters are designed that boost frequencies above 0 dBFS. This is a single 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default, all prescale factors are set to 0x7FFFFF. Postscale The STA326 provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiplier. The scale factor for this multiplier is loaded into RAM using the same I2C registers as the biquad coefficients and the mix. All channels can use the same settings as channel 1 by setting the postscale link bit. 48/64 DocID11531 Rev 9 STA326 8.4 User programmable processing Mix/bass management The STA326 provides a post EQ mixing block per channel. Each channel has 2 mixing coefficients, which are each 24-bit signed fractional multipliers, that correspond to the 2 channels of input to the mixing block. These coefficients are accessible via the user controlled coefficient RAM described below. The mix coefficients are expressed as 24-bit signed; fractional numbers in the range +1.0 (8388607) to -1.0 (-8388608) are used to provide three channels of output from two channels of filtered input. Figure 20. Mix/bass management block diagram ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e After a mix is achieved, STA326 also provides the capability to implement crossover filters on all channels corresponding to 2.1 bass management solution. Channels 1 and 2 use a first-order high-pass filter and channel 3 uses a second-order low-pass filter corresponding to the setting of the XO bits of I2C register 0x0C. If XO = 000, user specified crossover filters are used. s b O t e l o By default these coefficients correspond to pass-through. However, the user can write these coefficients in a similar way as the EQ biquads. When user-defined setting is selected, the user can only write 2nd order crossover filters. This output is then passed on to the volume/limiter block. DocID11531 Rev 9 49/64 64 User programmable processing 8.5 STA326 Calculating 24-bit signed fractional numbers from a dB value The prescale, mixing, and postscale functions of the STA326 use 24-bit signed fractional multipliers to attenuate signals. These attenuations can also invert the phase and therefore range in value from -1 to +1. It is possible to calculate the coefficient to utilize for a given negative dB value (attenuation) via the equations below.  Non-inverting phase numbers 0 to +1:  Coefficient = round(8388607 * 10(dB / 20))  Inverting phase numbers 0 to -1:  Coefficient = 16777216 - round(8388607 * 10(dB / 20)) As can be seen by the preceding equations, the value for positive phase 0 dB is 0x7FFFFF and the value for negative phase 0 dB is 0x800000. ) s t( 8.6 User-defined coefficient RAM 8.6.1 Coefficient address register 1 (addr 0x16) 8.6.2 D7 D6 D5 D4 CFA7 CFA6 CFA5 CFA4 0 0 0 0 8.6.3 D7 D6 C1B23 C1B22 e t le so 8.6.5 50/64 D3 D2 D1 D0 CFA3 CFA2 CFA1 CFA0 0 0 0 0 o s b O ) du s ( t c 0 o r P D4 D3 D2 D1 D0 C1B21 D5 C1B20 C1B19 C1B18 C1B17 C1B16 0 0 0 0 0 0 Coefficient b1data register bits 15:8 (addr 0x18) D7 8.6.4 e t le o r P Coefficient b1data register bits 23:16 (addr 0x17) 0 Ob c u d D6 D5 D4 D3 D2 D1 D0 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8 0 0 0 0 0 0 0 0 Coefficient b1data register bits 7:0 (addr 0x19) D7 D6 D5 D4 D3 D2 D1 D0 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0 0 0 0 0 0 0 0 0 Coefficient b2 data register bits 23:16 (addr 0x1A) D7 D6 D5 D4 D3 D2 D1 D0 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16 0 0 0 0 0 0 0 0 DocID11531 Rev 9 STA326 8.6.6 User programmable processing 8.6.7 Coefficient b2 data register bits 15:8 (addr 0x1B) D7 D6 D5 D4 D3 D2 D1 D0 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8 0 0 0 0 0 0 0 0 8.6.8 Coefficient b2 data register bits 7:0 (addr 0x1C) D7 D6 D5 D4 D3 D2 D1 D0 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0 0 0 0 0 0 0 0 0 8.6.9 Coefficient a1 data register bits 23:16 (addr 0x1D) D7 D6 D5 D4 D3 D2 C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 0 0 0 0 0 0 8.6.10 C3B16 0 0 D6 D5 D4 D3 D2 D1 D0 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8 0 0 0 0 0 0 0 0 ) s t( -O Coefficient a1 data register bits 7:0 (addr 0x1F) 0 8.6.11 uc D6 od C3B6 Pr 0 D5 D4 D3 D2 D1 D0 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0 0 0 0 0 0 0 Coefficient a2 data register bits 23:16 (addr 0x20) e t le so 8.6.13 D0 C3B17 D7 C3B7 8.6.12 o s b o r P c u d D1 C3B15 D7 Ob e t le Coefficient a1 data register bits 15:8 (addr 0x1E) ) s t( D7 D6 D5 D4 D3 D2 D1 D0 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16 0 0 0 0 0 0 0 0 Coefficient a2 data register bits 15:8 (addr 0x21) D7 D6 D5 D4 D3 D2 D1 D0 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8 0 0 0 0 0 0 0 0 Coefficient a2 data register bits 7:0 (addr 0x22) D7 D6 D5 D4 D3 D2 D1 D0 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0 0 0 0 0 0 0 0 0 DocID11531 Rev 9 51/64 64 User programmable processing 8.6.14 STA326 8.6.15 Coefficient b0 data register bits 23:16 (addr 0x23) D7 D6 D5 D4 D3 D2 D1 D0 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16 0 0 0 0 0 0 0 0 8.6.16 Coefficient b0 data register bits 15:8 (addr 0x24) D7 D6 D5 D4 D3 D2 D1 D0 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8 0 0 0 0 0 0 0 0 8.6.17 Coefficient b0 data register bits 7:0 (addr 0x25) D7 D6 D5 D4 D3 D2 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 0 0 0 0 0 0 e t le Coefficient write control register (addr 0x26) D7 D6 D5 D4 Reserved Reserved Reserved Reserved 0 0 0 0 ) (s so Ob o r P c u d ) s t( D1 D0 C5B1 C5B0 0 0 D3 D2 D1 D0 RA R1 WA W1 0 0 0 0 Coefficients for EQ, mix and scaling are handled internally in the STA326 via RAM. Access to this RAM is available to the user via an I2C register interface. A collection of I2C registers are dedicated to this function. First register contains the coefficient base address, five sets of three registers store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the read or write of the coefficient (s) to RAM. The following are instructions for reading and writing coefficients. t c u d o r P e et l o s Ob 52/64 DocID11531 Rev 9 STA326 8.7 User programmable processing Reading a coefficient from RAM      8.8 Reading a set of coefficients from RAM       write 8 bits of address to I2C register 0x16 write 1 to bit RA (D3) of I2C register 0x26 read top 8 bits of coefficient in I2C address 0x17 read middle 8 bits of coefficient in I2C address 0x18 read bottom 8 bits of coefficient in I2C address 0x19 read top 8 bits of coefficient b2 in I2C address 0x1A            read middle 8 bits of coefficient b2 in I2C address 0x1B read bottom 8 bits of coefficient b2 in I2C address 0x1C read top 8 bits of coefficient a1 in I2C address 0x1D read middle 8 bits of coefficient a1 in I2C address 0x1E read bottom 8 bits of coefficient a1 in I2C address 0x1F read top 8 bits of coefficient a2 in I2C address 0x20 read middle 8 bits of coefficient a2 in I2C address 0x21 read bottom 8 bits of coefficient a2 in I2C address 0x22 read top 8 bits of coefficient b0 in I2C address 0x23 read middle 8 bits of coefficient b0 in I2C address 0x24 read bottom 8 bits of coefficient b0 in I2C address 0x25 e t le ) s t( c u d o r P o s b O ) s ( t c u d o r P e t Writing a single coefficient to RAM e l o 8.9 bs O write 8 bits of address to I2C register 0x16 write 1 to bit R1 (D2) of I2C register 0x26 read top 8 bits of coefficient in I2C address 0x17 read middle 8 bits of coefficient in I2C address 0x18 read bottom 8 bits of coefficient in I2C address 0x19      write 8 bits of address to I2C register 0x16 write top 8 bits of coefficient in I2C address 0x17 write middle 8 bits of coefficient in I2C address 0x18 write bottom 8 bits of coefficient in I2C address 0x19 write 1 to W1 bit in I2C address 0x26 DocID11531 Rev 9 53/64 64 User programmable processing 8.10 STA326 Writing a set of coefficients to RAM write 8 bits of starting address to I2C register 0x16 write top 8 bits of coefficient b1 in I2C address 0x17 write middle 8 bits of coefficient b1 in I2C address 0x18 write bottom 8 bits of coefficient b1 in I2C address 0x19 write top 8 bits of coefficient b2 in I2C address 0x1A write middle 8 bits of coefficient b2 in I2C address 0x1B write bottom 8 bits of coefficient b2 in I2C address 0x1C write top 8 bits of coefficient a1 in I2C address 0x1D write middle 8 bits of coefficient a1 in I2C address 0x1E write bottom 8 bits of coefficient a1 in I2C address 0x1F write top 8 bits of coefficient a2 in I2C address 0x20 write middle 8 bits of coefficient a2 in I2C address 0x21 write bottom 8 bits of coefficient a2 in I2C address 0x22 write top 8 bits of coefficient b0 in I2C address 0x23 write middle 8 bits of coefficient b0 in I2C address 0x24 write bottom 8 bits of coefficient b0 in I2C address 0x25 write 1 to WA bit in I2C address 0x26                  e t le ) s t( c u d o r P o s b The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 8-bit address would specify the address of the biquad b1 coefficient (for example 0, 5, 10, 15, …, 45 decimal), and the STA326 will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data. O ) s ( t c u d o r P e Index (decimal) let 0 o s b O 54/64 1 Table 63. RAM block for biquads, mixing, and scaling Index (Hex) Description Coefficient Default 0x00 C1H10 (b1/2) 0x000000 0x01 C1H11 (b2) 0x000000 C1H12 (a1/2) 0x000000 2 0x02 Channel 1 - Biquad 1 3 0x03 C1H13 (a2) 0x000000 4 0x04 C1H14 (b0/2) 0x400000 5 0x05 Channel 1 - Biquad 2 C1H20 0x000000 … … … … … 19 0x13 Channel 1 - Biquad 4 C1H44 0x400000 20 0x14 C2H10 0x000000 21 0x15 C2H11 0x000000 … … … … … 39 0x27 Channel 2 - Biquad 4 C2H44 0x400000 Channel 2 - Biquad 1 DocID11531 Rev 9 STA326 User programmable processing Table 63. RAM block for biquads, mixing, and scaling (continued) Index (decimal) Index (Hex) 40 0x28 41 0x29 42 0x2A 43 Coefficient Default C12H0 (b1/2) 0x000000 C12H1 (b2) 0x000000 C12H2 (a1/2) 0x000000 0x2B C12H3 (a2) 0x000000 44 0x2C C12H4 (b0/2) 0x400000 45 0x2D C12L0 (b1/2) 0x000000 46 0x2E C12L1 (b2) 0x000000 47 0x2F C12L2 (a1/2) 0x000000 48 0x30 C12L3 (a2) 49 0x31 C12L4 (b0/2) 50 0x32 Channel 1 - Prescale 51 0x33 Channel 2 - Prescale 52 0x34 Channel 1 - Postscale 53 0x35 Channel 2 - Postscale 54 0x36 55 0x37 56 0x38 57 0x39 58 0x3A High-pass 2nd order filter for XO = 000 Low-pass 2nd order filter for XO = 000 uc od Pr ) s t( 0x000000 0x400000 C1PreS 0x7FFFFF C2PreS 0x7FFFFF C1PstS 0x7FFFFF C2PstS 0x7FFFFF Channel 3 - Postscale C3PstS 0x7FFFFF Thermal warning - Postscale TWPstS 0x5A9DF7 Channel 1 - Mix 1 C1MX1 0x7FFFFF Channel 1 - Mix 2 C1MX2 0x000000 Channel 2 - Mix 1 C2MX1 0x000000 Channel 2 - Mix 2 C2MX2 0x7FFFFF 0x3C Channel 3 - Mix 1 C3MX1 0x400000 0x3D Channel 3 - Mix 2 C3MX2 0x400000 62 0x3E Unused - - 63 0x3F Unused - - 60 61 e t e 0x3B Pr e t le so ) (s ct u d o 59 l o s Description Ob Ob DocID11531 Rev 9 55/64 64 User programmable processing 8.11 STA326 Variable max power correction (addr 0x27, 0x28) D7 D6 D5 D4 D3 D2 D1 D0 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8 0 0 1 0 1 1 0 1 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0 1 1 0 0 0 0 0 0 MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. 8.12 ) s t( Fault detect recovery (addr 0x2B, 0x2C) uc D7 D6 D5 D4 D3 D2 D1 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 0 0 0 0 0 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 0 0 0 0 0 1 od r P e FDRC2 1 D0 FDRC8 0 0 FDRC1 FDRC0 0 0 t e l o FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the output TRISTATE will be immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C specifies approximately 1 ms. 8.13 D7 so D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Reserved Reserved FAULT TWARN 0 0 0 0 0 0 0 d o r 0 eP let t c u D6 PLLUL Ob ) (s Status (addr 0x2D) s b O Table 64. TWARN D0 Thermal warning 0 Thermal warning condition 1 Normal operation Table 65. FAULT D1 IC fault 0 IC fault condition 1 Normal operation Table 66. PLLUL D7 56/64 PLL unlocked 0 Normal operation 1 PLL unlocked DocID11531 Rev 9 Applications STA326 9 Figure 21. Application circuit for 2.0-channel (2 BTL) configuration ) s ( ct u d o r P e t e l o DocID11531 Rev 9 ) (s s b O t c u d o r P e t e l o s b O Applications 57/64 ) s ( ct Applications 58/64 Figure 22. Application circuit for 2.1-channel (2 single-ended + 1 BTL) configuration u d o r P e t e l o DocID11531 Rev 9 ) (s s b O t c u d o r P e t e l o s b O STA326 STA326 Figure 23. Application circuit for mono-channel configuration ) s ( ct u d o r P e t e l o DocID11531 Rev 9 ) (s s b O t c u d o r P e t e l o s b O Applications 59/64 Package mechanical data 10 STA326 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. ) s t( c u d e t le o s b O ) s ( t c u d o r P e t e l o s b O 60/64 DocID11531 Rev 9 o r P STA326 10.1 Package mechanical data PowerSO-36 EPU package information Figure 24. PowerSO-36 EPU package outline ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O DocID11531 Rev 9 61/64 64 Package mechanical data STA326 Table 67. PowerSO-36 EPU package mechanical data mm. inch. Symbol Min. Typ. Max. Min. Typ. Max. A 3.25 - 3.43 0.128 - 0.135 A2 3.10 - 3.20 0.122 - 0.126 A4 0.80 - 1.00 0.031 - 0.039 A5 - 0.20 - - 0.008 - a1 0.03 - -0.04 0.001 - -0.002 b 0.22 - 0.38 0.009 - c 0.23 - 0.32 0.009 - D 15.80 - 16.00 0.622 - D1 9.40 - 9.80 0.370 - D2 - 1.00 - - 0.039 - E 13.90 - 14.50 0.547 - 0.571 E1 10.90 - 11.10 0.429 - 0.437 E2 - - 2.90 e t e o r P 0.386 - - 0.114 E3 5.80 - 6.20 0.228 - 0.244 E4 2.90 - 3.20 0.114 - 0.126 e - 0.65 - - 0.026 - e3 - 11.05 - - 0.435 - G 0 - 0.08 0 - 0.003 15.50 - 15.90 0.610 - 0.626 - - 1.10 - - 0.043 L 0.80 - 1.10 0.031 - 0.043 M 2.25 - 2.60 0.089 - 0.102 N - - 10 degrees - - 10 degrees R - 0.6 - - 0.024 - s - - 8 degrees - - 8 degrees ro H eP h t e l o bs O 62/64 bs O ) s ( t c du ol DocID11531 Rev 9 ) s t( 0.015 c u d 0.013 0.630 STA326 11 Revision history Revision history Table 68. Document revision history Date Revision Jul-2005 1 Initial release May-2006 2 Changed from preliminary data to maturity. 3 Datasheet remade Updated Features on cover page Updated Chapter 1: Description on page 8 Updated Chapter 2: Pin out on page 10 Updated Chapter 3: Electrical specifications on page 13 Added Chapter 5: Characterization curves on page 17 Updated Table 9: Register summary on page 22 with bit names used in register description Updated reset values in register bit map tables in Chapter 7: Register description on page 22 Updated Chapter 9: Applications on page 57 Updated Chapter 10: Package mechanical data on page 60 03-Nov-2010 Changes ) s t( c u d e t le o r P o s b 27-Apr-2011 4 Added CONFIG pin description to Section 2.3: Pin description on page 12 Added Section 4: Power supply and control sequencing on page 16 19-Jan-2012 5 Updated Section 6.2: Device addressing 6 Updated pin names in Figure 5 and Table 2 Updated pin name to VDD_REG in CONFIG (pin 21) on page 12 Updated Figure 21: Application circuit for 2.0-channel (2 BTL) configuration Added Figure 22: Application circuit for 2.1-channel (2 single-ended + 1 BTL) configuration Added Figure 23: Application circuit for mono-channel configuration 04-Feb-2013 13-Feb-2014 u d o 7 Updated order code Table 1 on page 1 8 Modified value of R5 to 3K9 in Figure 21: Application circuit for 2.0-channel (2 BTL) configuration and Figure 23: Application circuit for mono-channel configuration 9 Updated registers 0x29, 0x2A, and 0x2D in Table 9: Register summary Updated Section 4: Power supply and control sequencing Added sample rates to text in Configuration register A (addr 0x00) Updated bit D7 in Configuration register C (addr 0x02) Updated text concerning DSPB bit in Configuration register D (addr 0x03) Updated bit D4 in Master mute register (addr 0x06) Updated bit D6 in Channel 2 configuration (addr 0x0F) Updated bit D7 in Channel 3 configuration (addr 0x10) Updated Section 8.2: Prescale Corrected name of bits in Coefficient a1 data register bits 23:16 (addr 0x1D) Added Section 8.13: Status (addr 0x2D) bs O 25-Jan-2016 s ( t c r P e t e l o 18-Jun-2015 O ) DocID11531 Rev 9 63/64 64 STA326 ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. t e l o s b O Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 64/64 DocID11531 Rev 9