STA333BW13TR

STA333BW 2.1 channel 40 W high-efficiency digital audio system Sound Terminal® Datasheet - production data  Dynamic range compression (DRC) or anticlipping mode  Audio presets: – 15 preset crossover filters – 5 preset anticlipping modes – Preset night-time listening mode  Individual channel soft/hard mute  Independent channel volume and DSP bypass  I²S input data interface PowerSSO-36 with exposed pad down (EPD)  Input and output channel mapping  Automatic invalid input-detect mute  Up to 5 user-programmable biquads/channel  Three coefficients banks for EQ presets storing with fast recall via I²C interface Features  Wide-range supply voltage, 4.5 V to 21.5 V  Three power output configurations: – 2 channels of ternary PWM (2 x 20 W into 8  at 18 V) + PWM output – 2 channels of ternary PWM (2 x 20 W into 8  at 18 V) + ternary stereo line-out – 2.1 channels of binary PWM (left, right, LFE) (2 x 9 W into 4  +1 x 20 W into 8  at 18 V)  FFX with 100-dB SNR and dynamic range  Bass/treble tones and de-emphasis control  Selectable high-pass filter for DC blocking  Advanced AM interference frequency switching and noise suppression modes  Sub channel mix into left and right channels  Selectable high- or low-bandwidth noise-shaping topologies  Selectable clock input ratio  96 kHz internal processing sample rate  Scalable FFX modulation index  Selectable 32- to 192-kHz input sample rates  Thermal overload and short-circuit protection technology  I²C control with selectable device address  Video apps: 576 x fS input mode supported  Digital gain/attenuation +48 dB to -80 dB with 0.5-dB/step resolution  Pin and SW compatible with STA335BW, STA339BW, STA339BWS, STA559BW and STA559BWS  Soft volume update with programmable ratio  Individual channel and master gain/attenuation Table 1. Device summary Order code Package Packaging STA333BW13TR PowerSSO-36 EPD Tape and reel February 2014 This is information on a product in full production. DocID13773 Rev 5 1/68 www.st.com Contents STA333BW Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 4 2.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 12 3.5 Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 13 3.6 Power-on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0.1 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0.2 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0.3 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 I²C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 6.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4.1 2/68 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DocID13773 Rev 5 STA333BW 7 Contents 6.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 7.2 7.3 Configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 23 7.1.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 41 7.2.1 Mute / line output configuration register (addr 0x06) . . . . . . . . . . . . . . . 42 7.2.2 Master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2.3 Channel 1 volume (addr 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2.4 Channel 2 volume (addr 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2.5 Channel 3 / line output volume (addr 0x0A) . . . . . . . . . . . . . . . . . . . . . 43 Audio preset registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . 44 7.3.1 Audio preset register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.3.2 Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.4 Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 46 7.5 Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.6 Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 48 7.7 7.6.1 Limiter 1 attack / release rate (addr 0x12) . . . . . . . . . . . . . . . . . . . . . . . 48 7.6.2 Limiter 1 attack / release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . 48 7.6.3 Limiter 2 attack / release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . 49 7.6.4 Limiter 2 attack / release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . 49 7.6.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 54 7.7.1 Coefficient address register (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . . 54 7.7.2 Coefficient b1 data register bits (addr 0x17 - 0x19) . . . . . . . . . . . . . . . . 54 7.7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C) . . . . . . . . . . . . . . . 54 7.7.4 Coefficient a1 data register bits (addr 0x1D - 0x1F) . . . . . . . . . . . . . . . 54 7.7.5 Coefficient a2 data register bits (addr 0x20 - 0x22) . . . . . . . . . . . . . . . . 55 7.7.6 Coefficient b0 data register bits (addr 0x23 - 0x25) . . . . . . . . . . . . . . . . 55 DocID13773 Rev 5 3/68 68 Contents 8 STA333BW 7.7.7 Coefficient read / write control register (addr 0x26) . . . . . . . . . . . . . . . . 55 7.7.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.8 Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 60 7.9 Distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . . . . . . . . 60 7.10 Fault detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 60 7.11 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.1 Applications schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.2 PLL filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4/68 DocID13773 Rev 5 STA333BW List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-off sequence for pop-free turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Timing diagram for SAI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Left and right processing, section 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Left and right processing, section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.0 channels (OCFG = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.1 channels (OCFG = 01) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.1 channels (OCFG = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Output configuration for stereo BTL mode (RL = 8  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PowerSSO-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 DocID13773 Rev 5 5/68 68 List of tables STA333BW List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. 6/68 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Timing parameters for slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial audio input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 26 Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 27 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FFX compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Overcurrent warning bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Postscale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Dynamic range compression / anticlipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DocID13773 Rev 5 STA333BW Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. List of tables IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Master volume offset as a function of MVOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Channel volume as a function of CxVOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Audio preset gain compression / limiters selection for AMGC[3:2] = 00. . . . . . . . . . . . . . . 44 AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Audio preset AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Volume bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Tone control boost / cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter attack rate vs LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Limiter release rate vs LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Limiter attack threshold vs LxAT bits (AC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Limiter release threshold vs LxRT bits (AC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Limiter attack threshold vs LxAT bits (DRC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Limiter release threshold vs LxRT bits (DRC mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 RAM block for biquads, mixing, scaling, bass management. . . . . . . . . . . . . . . . . . . . . . . . 57 Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 DocID13773 Rev 5 7/68 68 Description 1 STA333BW Description The STA333BW is an integrated solution of digital audio processing, digital amplifier controls and power output stages to create a high-power single-chip FFX digital amplifier with high-quality and high-efficiency. Three channels of FFX processing are provided. The FFX processor implements the ternary, binary and binary differential processing capabilities of the full FFX processor. The STA333BW is part of the Sound Terminal® family that provides full digital audio streaming to the speakers and offers cost effectiveness, low power dissipation and sound enrichment. The power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. For example, 2.1 channels can be provided by two half-bridges and a single full-bridge, supplying up to 2 x 9 W + 1 x 20 W of output power or two channels can be provided by two full-bridges, supplying up to 2 x 20 W of output power. The IC can also be configured as 2.1 channels with 2 x 20 W supplied by the device plus a drive for an external FFX power amplifier, such as STA533WF or STA515W. The serial audio data input interface accepts all possible formats, including the popular I²S format. The high-quality conversion from PCM audio to FFX PWM switching provides over 100 dB of SNR and of dynamic range. Also provided in the STA333BW are a full assortment of digital processing features. This includes up to 5 programmable biquads (EQ) per channel. Available presets enable a time-to-market advantage by substantially reducing the amount of software development needed for functions such as audio preset volume loudness, preset volume curves and preset EQ settings. There are also new advanced AM radio interference reduction modes. The DRC dynamically equalizes the system to provide a linear frequency speaker response regardless of output power level. Figure 1. Block diagram I²C Protection current / thermal I²S interface Volume control Channel 1A Logic Power control Channel 1B FFX Channel 2A Regulators Channel 2B PLL Bias Digital DSP 8/68 Power DocID13773 Rev 5 STA333BW Pin connections 2 Pin connections 2.1 Connection diagram Figure 2. Pin connection PowerSSO-36 (top view) GND_SUB 1 36 VDD_DIG SA 2 35 GND_DIG TEST_MODE 3 34 SCL VSS 4 33 SDA VCC_REG 5 32 INT_LINE OUT2B 6 31 RESET GND2 7 30 SDI VCC2 8 29 LRCKI OUT2A 9 28 BICKI OUT1B 10 27 XTI VCC1 11 26 GND_PLL GND1 12 25 FILTER_PLL OUT1A 13 24 VDD_PLL GND_REG 14 23 PWRDN VDD 15 22 GND_DIG CONFIG 16 21 VDD_DIG OUT3B / FFX3B 17 20 TWARN / OUT4A OUT3A / FFX3A 18 19 EAPD / OUT4B EP, exposed pad (device ground) D05AU1638 2.2 Pin description Table 2. Pin description Pin Type Name Description 1 GND GND_SUB Substrate ground 2 I SA I²C select address (pull-down) 3 I TEST_MODE This pin must be connected to ground (pull-down) 4 I/O VSS Internal reference at VCC - 3.3 V 5 I/O VCC_REG Internal VCC reference 6 O OUT2B Output half-bridge channel 2B 7 GND GND2 Power negative supply 8 Power VCC2 Power positive supply 9 O OUT2A Output half-bridge channel 2A 10 O OUT1B Output half-bridge channel 1B DocID13773 Rev 5 9/68 68 Pin connections STA333BW Table 2. Pin description (continued) Pin 10/68 Type Name Description 11 Power VCC1 Power positive supply 12 GND GND1 Power negative supply 13 O OUT1A Output half-bridge channel 1A 14 GND GND_REG Internal ground reference 15 Power VDD Internal 3.3 V reference voltage 16 I CONFIG Parallel mode command 17 O OUT3B / FFX3B PWM out channel 3B / external bridge driver 18 O OUT3A / FFX3A PWM out channel 3A / external bridge driver 19 O EAPD / OUT4B Power down for external bridge / PWM out channel 4B 20 I/O TWARN / OUT4A Thermal warning from external bridge (pull-up when input) / PWM out channel 4A 21 Power VDD_DIG Digital supply voltage 22 GND GND_DIG Digital ground 23 I PWRDN Power down (pull-up) 24 Power VDD_PLL Positive supply for PLL 25 I FILTER_PLL Connection to PLL filter 26 GND GND_PLL Negative supply for PLL 27 I XTI PLL input clock 28 I BICKI I²S serial clock 29 I LRCKI I²S left / right clock 30 I SDI I²SI²S serial data channels 1 and 2 31 I RESET Reset (pull-up) 32 O INT_LINE Fault interrupt 33 I/O SDA I²C serial data 34 I SCL I²C serial clock 35 GND GND_DIG Digital ground 36 Power VDD_DIG Digital supply voltage - - EP Exposed pad for PCB heatsink, to be connected to GND DocID13773 Rev 5 STA333BW Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Typ Max Unit VCC Power supply voltage (pins VCCx) -0.3 - 24 V VDD Digital supply voltage (pins VDD_DIG) -0.3 - 4.0 V VDD PLL supply voltage (pin VDD_PLL) -0.3 - 4.0 V Top Operating junction temperature -20 - 150 °C Tstg Storage temperature -40 - 150 °C Warning: 3.2 Min Stresses beyond those listed in Table 3 above may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended operating conditions” are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, power supplies with nominal values rated within the recommended operating conditions, may experience some rising beyond the maximum operating conditions for a short time when no or very low current is sinked (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded. Thermal data Table 4. Thermal data Parameter Min Typ Max Unit Rth j-case Thermal resistance junction-case (thermal pad) - - 1.5 °C/W Tth-sdj Thermal shut-down junction temperature - 150 - °C Tth-w Thermal warning temperature - 130 - °C Tth-sdh Thermal shut-down hysteresis - 20 - °C - 24 - °C/W Rth j-amb Thermal resistance junction-ambient (1) 1. See Chapter 9: Package thermal characteristics on page 64 for details. DocID13773 Rev 5 11/68 68 Electrical specifications 3.3 STA333BW Recommended operating conditions Table 5. Recommended operating condition Symbol 3.4 Parameter Min Typ Max Unit VCC Power supply voltage (VCCxA, VCCxB) 4.5 - 21.5 V VDD_DIG Digital supply voltage 2.7 3.3 3.6 V VDD_PLL PLL supply voltage 2.7 3.3 3.6 V Tamb Ambient temperature -20 - 70 °C Electrical specifications for the digital section The specifications given in this section are valid for Tamb = 25 °C unless otherwise specified. Table 6. Electrical specifications - digital section Symbol 12/68 Parameter Conditions Min Typ Max Unit Iil Low level input current without pull-up/down device Vi = 0 V - - 1 µA Iih High level input current without pull-up/down device Vi = VDD_DIG = 3.6 V - - 1 µA Vil Low level input voltage - - - Vih High level input voltage - Vol Low level output voltage Iol = 2 mA Voh High level output voltage Ioh = 2 mA Rpu Equivalent pull-up/down resistance - DocID13773 Rev 5 0.8 * VDD_DIG - 0.8 * VDD_DIG - 0.2 * VDD_DIG 0.4 * VDD_DIG V V V - - V 50 - k STA333BW 3.5 Electrical specifications Electrical specifications for the power section The specifications given in this section are valid for the operating conditions: VCC = 18 V, f = 1 kHz, fsw = 384 kHz, Tamb = 25 °C and RL = 8 , unless otherwise specified. Table 7. Electrical specifications - power section Symbol Parameter Conditions Min Typ Max THD = 1% - 16 - THD = 10% - 20 - THD = 1%, RL= 4  - 7 - THD = 10%, RL= 4  - 9 - Output power BTL Unit W Po Output power SE W RdsON Power P-channel or N-channel MOSFET ld = 0.75 A - - 250 m gP Power P-channel RdsON matching ld = 0.75 A - 100 - % gN Power N-channel RdsON matching ld = 0.75 A - 100 - % Idss Power P-channel / N-channel leakage VCC = 20 V - - 1 A tr Rise time - - 10 ns tf Fall time Resistive load, see Figure 3 below - - 10 ns Supply current from VCC in power down PWRDN = 0 - 0.3 - A Supply current from VCC in operation PWRDN = 1 - 15 - mA IVDD Supply current FFX processing Internal clock = 49.152 MHz - 55 - mA ILIM Overcurrent limit (1) 2.2 3.0 - A ISCP Short -circuit protection RL = 0  2.7 3.6 - A VUVP Undervoltage protection - - - 4.3 V tmin Output minimum pulse width No load 20 40 60 ns DR Dynamic range - - 100 - dB Signal to noise ratio, ternary mode A-Weighted - 100 - dB Signal to noise ratio binary mode - - 90 - dB Total harmonic distortion + noise FFX stereo mode, Po = 1 W f = 1 kHz - 0.2 - % Crosstalk FFX stereo mode, OUT1A  FFX1B -> OUT1B  FFX2A -> OUT2A  FFX2B -> OUT2B  FFX3A -> OUT3A  FFX3B -> OUT3B  FFX4A -> OUT4A  FFX4B -> OUT4B Default modulation:  FFX1A / 1B configured as ternary  FFX2A / 2B configured as ternary  FFX3A / 3B configured as lineout ternary  FFX4A / 4B configured as lineout ternary On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this configuration, volume control or EQ have no effect on channels 3 and 4. In this configuration the PWM slot phase is the following as shown in Figure 16. Figure 16. 2.0 channels (OCFG = 00) PWM slots OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B DocID13773 Rev 5 37/68 68 Register description STA333BW 2.1 channels, two half-bridges + one full-bridge (OCFG = 01) Mapping:  FFX1A -> OUT1A  FFX2A -> OUT1B  FFX3A -> OUT2A  FFX3B -> OUT2B  FFX1A -> OUT3A  FFX1B -> OUT3B  FFX2A -> OUT4A  FFX2B -> OUT4B Modulation:  FFX1A / 1B configured as binary  FFX2A / 2B configured as binary  FFX3A / 3B configured as binary  FFX4A / 4B configured as binary In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3 / OUT4 channels the channel 1 and channel 2 PWM are replicated. In this configuration the PWM slot phase is the following as shown in Figure 17. Figure 17. 2.1 channels (OCFG = 01) PWM slots OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B 38/68 DocID13773 Rev 5 STA333BW Register description 2.1 channels, two full-bridges + one external full-bridge (OCFG = 10) Mapping:  FFX1A -> OUT1A  FFX1B -> OUT1B  FFX2A -> OUT2A  FFX2B -> OUT2B  FFX3A -> OUT3A  FFX3B -> OUT3B  EAPD -> OUT4A  TWARN -> OUT4B Default modulation:  FFX1A / 1B configured as ternary  FFX2A / 2B configured as ternary  FFX3A / 3B configured as ternary  FFX4A / 4B is not used In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the external bridge control signals are muxed. In this configuration the PWM slot phase is the following as shown in Figure 18. Figure 18. 2.1 channels (OCFG = 10) PWM slots OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B DocID13773 Rev 5 39/68 68 Register description STA333BW Invalid input detect mute enable Table 45. Invalid input detect mute enable Bit 2 R/W R/W RST 1 Name Description 0: disables the automatic invalid input detect mute 1: enables the automatic invalid input detect mute IDE Setting the IDE bit enables this function, which looks at the input I²S data and automatically mutes if the signals are perceived as invalid. Binary output mode clock loss detection Table 46. Binary output mode clock loss detection Bit 3 R/W R/W RST 1 Name Description 0: binary output mode clock loss detection disabled 1: binary output mode clock loss detection enable BCLE Detects loss of input MCLK in binary mode and will output 50% duty cycle. LRCK double trigger protection Table 47. LRCK double trigger protection Bit 4 R/W R/W RST 1 Name Description 0: LRCLK double trigger protection disabled 1: LRCLK double trigger protection enabled LDTE LDTE, when enabled, prevents double trigger of LRCLK on instable I²S input. Auto EAPD on clock loss Table 48. Auto EAPD on clock loss Bit 5 R/W R/W RST 0 Name Description 0: auto EAPD on clock loss not enabled 1: auto EAPD on clock loss ECLE When active, issues a power device power down signal (EAPD) on clock loss detection. IC power down Table 49. IC power down Bit 6 40/68 R/W R/W RST 1 Name PWDN Description 0: IC power down low-power condition 1: IC normal operation DocID13773 Rev 5 STA333BW Register description The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power-stage, then the master clock to all internal hardware expect the I²C block is gated. This places the IC in a very low power consumption state. External amplifier power down Table 50. External amplifier power down Bit 7 R/W R/W RST 0 Name EAPD Description 0: external power stage power down active 1: normal operation The EAPD register directly disables / enables the internal power circuitry. When EAPD = 0, the internal power section is placed in a low-power state (disabled). This register also controls the FFX4B / EAPD output pin when OCFG = 10. 7.2 Volume control registers (addr 0x06 - 0x0A) The volume structure of the STA333BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -80 dB. As an example if C3VOL = 0x00 or +48 dB and MVOL = 0x18 or -12 dB, then the total gain for channel 3 = +36 dB. The channel mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 kHz). A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) in any channel volume register. When volume offsets are provided via the master volume register any channel whose total volume is less than -80 dB is muted. All changes in volume take place at zero-crossings when ZCE = 1 (Configuration register E (addr 0x04)) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE = 0, volume updates occur immediately. DocID13773 Rev 5 41/68 68 Register description 7.2.1 STA333BW Mute / line output configuration register (addr 0x06) D7 D6 D5 D4 D3 D2 D1 D0 LOC1 LOC0 Reserved Reserved C3M C2M C1M Reserved 0 0 0 0 0 0 0 0 Table 51. Line output configuration LOC[1:0] Line output configuration 00 Line output fixed - no volume, no EQ 01 Line output variable - channel 3 volume effects line output, no EQ 10 Line output variable with EQ - channel 3 volume effects line output Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs. 7.2.2 Master volume register (addr 0x07) D7 D6 D5 D4 D3 D2 D1 D0 MVOL7 MVOL6 MVOL5 MVOL4 MVOL3 MVOL2 MVOL1 MVOL0 1 1 1 1 1 1 1 1 Table 52. Master volume offset as a function of MVOL MVOL[7:0] 7.2.3 7.2.4 42/68 Volume offset from channel value 00000000 (0x00) 0 dB 00000001 (0x01) -0.5 dB 00000010 (0x02) -1 dB … … 01001100 (0x4C) -38 dB … … 11111110 (0xFE) -127.5 dB 11111111 (0xFF) Default mute, not to be used during operation Channel 1 volume (addr 0x08) D7 D6 D5 D4 D3 D2 D1 D0 C1VOL7 C1VOL6 C1VOL5 C1VOL4 C1VOL3 C1VOL2 C1VOL1 C1VOL0 0 1 1 0 0 0 0 0 Channel 2 volume (addr 0x09) D7 D6 D5 D4 D3 D2 D1 D0 C2VOL7 C2VOL6 C2VOL5 C2VOL4 C2VOL3 C2VOL2 C2VOL1 C2VOL0 0 1 1 0 0 0 0 0 DocID13773 Rev 5 STA333BW 7.2.5 Register description Channel 3 / line output volume (addr 0x0A) D7 D6 D5 D4 D3 D2 D1 D0 C3VOL7 C3VOL6 C3VOL5 C3VOL4 C3VOL3 C3VOL2 C3VOL1 C3VOL0 0 1 1 0 0 0 0 0 Table 53. Channel volume as a function of CxVOL CxVOL[7:0] Volume 00000000 (0x00) +48 dB 00000001 (0x01) +47.5 dB 00000010 (0x02) +47 dB … … 01011111 (0x5F) +0.5 dB 01100000 (0x60) 0 dB 01100001 (0x61) -0.5 dB … … 11010111 (0xD7) -59.5 dB 11011000 (0xD8) -60 dB 11011001 (0xD9) -61 dB 11011010 (0xDA) -62 dB … … 11101100 (0xEC) -80 dB 11101101 (0xED) Hard channel mute … … 11111111 (0xFF) Hard channel mute DocID13773 Rev 5 43/68 68 Register description STA333BW 7.3 Audio preset registers (addr 0x0B and 0x0C) 7.3.1 Audio preset register 1 (addr 0x0B) D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved AMGC[1] AMGC[0] Reserved Reserved Reserved Reserved 1 0 0 0 0 0 0 0 Using AMGC[1:0] bits, attack and release thresholds and rates are automatically configured to properly fit application specific configurations. They are defined below in Table 54. Table 54. Audio preset gain compression / limiters selection for AMGC[3:2] = 00 AMGC[1:0] 7.3.2 Mode 00 User programmable GC 01 AC no clipping 2.1 10 AC limited clipping (10%) 2.1 11 DRC night-time listening mode 2.1 Audio preset register 2 (addr 0x0C) D7 D6 D5 D4 D3 D2 D1 D0 XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME 0 0 0 0 0 0 0 0 AM interference frequency switching Table 55. AM interference frequency switching bits Bit 0 R/W RST R/W 0 Name AMAME Description Audio preset AM enable 0: switching frequency determined by PWMS setting 1: switching frequency determined by AMAM settings Table 56. Audio preset AM switching frequency selection AMAM[2:0] 44/68 48 kHz / 96 kHz input fs 44.1 kHz / 88.2 kHz input fs 000 0.535 MHz - 0.720 MHz 0.535 MHz - 0.670 MHz 001 0.721 MHz - 0.900 MHz 0.671 MHz - 0.800 MHz 010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz 011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz 100 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz 101 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz 110 1.601 MHz - 1.700 MHz 1.501 MHz - 1.700 MHz DocID13773 Rev 5 STA333BW Register description Bass management crossover Table 57. Bass management crossover Bit R/W RST Name 4 R/W 0 XO0 5 R/W 0 XO1 6 R/W 0 XO2 7 R/W 0 XO3 Description Selects the bass-management crossover frequency. A 1st-order hign-pass filter (channels 1 and 2) or a 2nd-order low-pass filter (channel 3) at the selected frequency is performed. Table 58. Bass management crossover frequency XO[3:0] Crossover frequency 0000 User-defined (Section 7.7.8 on page 56) 0001 80 Hz 0010 100 Hz 0011 120 Hz 0100 140 Hz 0101 160 Hz 0110 180 Hz 0111 200 Hz 1000 220 Hz 1001 240 Hz 1010 260 Hz 1011 280 Hz 1100 300 Hz 1101 320 Hz 1110 340 Hz 1111 360 Hz DocID13773 Rev 5 45/68 68 Register description 7.4 STA333BW Channel configuration registers (addr 0x0E - 0x10) D7 D6 D5 D4 D3 D2 D1 D0 C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VPB C1EQBP C1TCB 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VPB C2EQBP C2TCB 0 1 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VPB Reserved Reserved 1 0 0 0 0 0 0 0 Tone control bypass Tone control (bass / treble) can be bypassed on a per channel basis for channels 1 and 2. Table 59. Tone control bypass CxTCB Mode 0 Perform tone control on channel x - normal operation 1 Bypass tone control on channel x EQ bypass EQ control can be bypassed on a per channel basis for channels 1 and 2. If EQ control is bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel. Table 60. EQ bypass CxEQBP Mode 0 Perform EQ on channel x - normal operation 1 Bypass EQ on channel x Volume bypass Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting has no effect on that channel. Table 61. Volume bypass register CxVBP 46/68 Mode 0 Normal volume operations 1 Volume is by-passed DocID13773 Rev 5 STA333BW Register description Binary output enable registers Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is negative inverse. Table 62. Binary output enable registers CxBO Mode 0 FFX output operation 1 Binary output Limiter select Limiter selection can be made on a per-channel basis according to the channel limiter select bits. . Table 63. Channel limiter mapping as a function of CxLS bits CxLS[1:0] Channel limiter mapping 00 Channel has limiting disabled 01 Channel is mapped to limiter #1 10 Channel is mapped to limiter #2 Output mapping Output mapping can be performed on a per channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs. . Table 64. Channel output mapping as a function of CxOM bits CxOM[1:0] Channel x output source from 00 Channel1 01 Channel 2 10 Channel 3 DocID13773 Rev 5 47/68 68 Register description 7.5 STA333BW Tone control register (addr 0x11) D7 D6 D5 D4 D3 D2 D1 D0 TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0 0 1 1 1 0 1 1 1 Tone control Table 65. Tone control boost / cut as a function of BTC and TTC bits BTC[3:0], TTC[3:0] Boost / Cut 0000 -12 dB 0001 -12 dB 0010 -10 dB … … 0101 -4 dB 0110 -2 dB 0111 0 dB 1000 +2 dB 1001 +4 dB … … 1100 +10 dB 1101 +12 dB 1110 +12 dB 1111 +12 dB 7.6 Dynamic control registers (addr 0x12 - 0x15) 7.6.1 Limiter 1 attack / release rate (addr 0x12) 7.6.2 48/68 D7 D6 D5 D4 D3 D2 D1 D0 L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0 0 1 1 0 1 0 1 0 Limiter 1 attack / release threshold (addr 0x13) D7 D6 D5 D4 D3 D2 D1 D0 L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0 0 1 1 0 1 0 0 1 DocID13773 Rev 5 STA333BW 7.6.3 7.6.4 7.6.5 Register description Limiter 2 attack / release rate (addr 0x14) D7 D6 D5 D4 D3 D2 D1 D0 L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0 0 1 1 0 1 0 1 0 Limiter 2 attack / release threshold (addr 0x15) D7 D6 D5 D4 D3 D2 D1 D0 L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0 0 1 1 0 1 0 0 1 Description The STA333BW includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anticlipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in Configuration register E (addr 0x04) on page 31. Each channel can be mapped to either limiter or not mapped, meaning that channel will clip when 0 dBFS is exceeded. Each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels in unison. Figure 19. Basic limiter and volume flow diagram LIMITER GAIN / VOLUME INPUT RMS + GAIN ATTENUATION SATURATION OUTPUT The limiter attack thresholds are determined by the LxAT registers. It is recommended in anticlipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of a FFX amplifier. Since gain can be added digitally within the STA333BW it is possible to exceed 0 dBfs or any other LxAT setting, when this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. Gain reduction occurs on a peak-detect algorithm. The limiter release thresholds are determined by the LxRT registers. The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The output of the volume / limiter block is passed through a RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the Release Rate register. The gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already DocID13773 Rev 5 49/68 68 Register description STA333BW reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over limiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”. In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. Table 66. Limiter attack rate vs LxA bits LxA[3:0] 50/68 Attack Rate dB/ms 0000 3.1584 0001 2.7072 0010 2.2560 0011 1.8048 0100 1.3536 0101 0.9024 0110 0.4512 0111 0.2256 1000 0.1504 1001 0.1123 1010 0.0902 1011 0.0752 1100 0.0645 1101 0.0564 1110 0.0501 1111 0.0451 Fast Slow DocID13773 Rev 5 STA333BW Register description Table 67. Limiter release rate vs LxR bits LxR[3:0] Release Rate dB/ms 0000 0.5116 0001 0.1370 0010 0.0744 0011 0.0499 0100 0.0360 0101 0.0299 0110 0.0264 0111 0.0208 1000 0.0198 1001 0.0172 1010 0.0147 1011 0.0137 1100 0.0134 1101 0.0117 1110 0.0110 1111 0.0104 Fast Slow Anticlipping mode Table 68. Limiter attack threshold vs LxAT bits (AC mode) LxAT[3:0] AC (dB relative to fs) 0000 -12 0001 -10 0010 -8 0011 -6 0100 -4 0101 -2 0110 0 0111 +2 1000 +3 1001 +4 1010 +5 1011 +6 1100 +7 1101 +8 DocID13773 Rev 5 51/68 68 Register description STA333BW Table 68. Limiter attack threshold vs LxAT bits (AC mode) (continued) LxAT[3:0] AC (dB relative to fs) 1110 +9 1111 +10 Table 69. Limiter release threshold vs LxRT bits (AC mode) LxRT[3:0] AC (dB relative to fs) 0000 - 0001 -29 0010 -20 0011 -16 0100 -14 0101 -12 0110 -10 0111 -8 1000 -7 1001 -6 1010 -5 1011 -4 1100 -3 1101 -2 1110 -1 1111 -0 Dynamic range compression mode Table 70. Limiter attack threshold vs LxAT bits (DRC mode) LxAT[3:0] 52/68 DRC (dB relative to Volume) 0000 -31 0001 -29 0010 -27 0011 -25 0100 -23 0101 -21 0110 -19 0111 -17 1000 -16 DocID13773 Rev 5 STA333BW Register description Table 70. Limiter attack threshold vs LxAT bits (DRC mode) (continued) LxAT[3:0] DRC (dB relative to Volume) 1001 -15 1010 -14 1011 -13 1100 -12 1101 -10 1110 -7 1111 -4 Table 71. Limiter release threshold vs LxRT bits (DRC mode) LxRT[3:0] DRC (db relative to Volume + LxAT) 0000 - 0001 -38 0010 -36 0011 -33 0100 -31 0101 -30 0110 -28 0111 -26 1000 -24 1001 -22 1010 -20 1011 -18 1100 -15 1101 -12 1110 -9 1111 -6 DocID13773 Rev 5 53/68 68 Register description STA333BW 7.7 User-defined coefficient control registers (addr 0x16 - 0x26) 7.7.1 Coefficient address register (addr 0x16) 7.7.2 7.7.3 7.7.4 54/68 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved CFA5 CFA4 CFA3 CFA2 CFA1 CFA0 0 0 0 0 0 0 0 0 Coefficient b1 data register bits (addr 0x17 - 0x19) D7 D6 D5 D4 D3 D2 D1 D0 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0 0 0 0 0 0 0 0 0 Coefficient b2 data register bits (addr 0x1A - 0x1C) D7 D6 D5 D4 D3 D2 D1 D0 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0 0 0 0 0 0 0 0 0 Coefficient a1 data register bits (addr 0x1D - 0x1F) D7 D6 D5 D4 D3 D2 D1 D0 C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0 0 0 0 0 0 0 0 0 DocID13773 Rev 5 STA333BW 7.7.5 7.7.6 7.7.7 Register description Coefficient a2 data register bits (addr 0x20 - 0x22) D7 D6 D5 D4 D3 D2 D1 D0 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0 0 0 0 0 0 0 0 0 Coefficient b0 data register bits (addr 0x23 - 0x25) D7 D6 D5 D4 D3 D2 D1 D0 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0 0 0 0 0 0 0 0 0 Coefficient read / write control register (addr 0x26) D7 D6 D3 D2 D1 D0 Reserved D5 D4 RA R1 WA W1 0 0 0 0 0 DocID13773 Rev 5 55/68 68 Register description 7.7.8 STA333BW Description Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA333BW via RAM. Access to this RAM is available to the user via an I²C register interface. A collection of I²C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the read / write of the coefficient(s) to/from RAM. Note: The read write operation on RAM coefficients works only if RLCKI (pin29) is switching and stable (ref. Table 8, tLRJT timing) and PLL must be locked (ref bit D7 reg 0x2D). Reading a coefficient from RAM 1. Write 6-bits of address to I²C register 0x16. 2. Write 1 to R1 bit in I²C address 0x26. 3. Read top 8-bits of coefficient in I²C address 0x17. 4. Read middle 8-bits of coefficient in I²C address 0x18. 5. Read bottom 8-bits of coefficient in I²C address 0x19. Reading a set of coefficients from RAM 1. Write 6-bits of address to I²C register 0x16. 2. Write 1 to RA bit in I²C address 0x26. 3. Read top 8-bits of coefficient in I²C address 0x17. 4. Read middle 8-bits of coefficient in I²C address 0x18. 5. Read bottom 8-bits of coefficient in I²C address 0x19. 6. Read top 8-bits of coefficient b2 in I²C address 0x1A. 7. Read middle 8-bits of coefficient b2 in I²C address 0x1B. 8. Read bottom 8-bits of coefficient b2 in I²C address 0x1C. 9. Read top 8-bits of coefficient a1 in I²C address 0x1D. 10. Read middle 8-bits of coefficient a1 in I²C address 0x1E. 11. Read bottom 8-bits of coefficient a1 in I²C address 0x1F. 12. Read top 8-bits of coefficient a2 in I²C address 0x20. 13. Read middle 8-bits of coefficient a2 in I²C address 0x21. 14. Read bottom 8-bits of coefficient a2 in I²C address 0x22. 15. Read top 8-bits of coefficient b0 in I²C address 0x23. 16. Read middle 8-bits of coefficient b0 in I²C address 0x24. 17. Read bottom 8-bits of coefficient b0 in I²C address 0x25. Writing a single coefficient to RAM 56/68 1. Write 6-bits of address to I²C register 0x16. 2. Write top 8-bits of coefficient in I²C address 0x17. 3. Write middle 8-bits of coefficient in I²C address 0x18. 4. Write bottom 8-bits of coefficient in I²C address 0x19. 5. Write 1 to W1 bit in I²C address 0x26. DocID13773 Rev 5 STA333BW Register description Writing a set of coefficients to RAM 1. Write 6-bits of starting address to I²C register 0x16. 2. Write top 8-bits of coefficient b1 in I²C address 0x17. 3. Write middle 8-bits of coefficient b1 in I²C address 0x18. 4. Write bottom 8-bits of coefficient b1 in I²C address 0x19. 5. Write top 8-bits of coefficient b2 in I²C address 0x1A. 6. Write middle 8-bits of coefficient b2 in I²C address 0x1B. 7. Write bottom 8-bits of coefficient b2 in I²C address 0x1C. 8. Write top 8-bits of coefficient a1 in I²C address 0x1D. 9. Write middle 8-bits of coefficient a1 in I²C address 0x1E. 10. Write bottom 8-bits of coefficient a1 in I²C address 0x1F. 11. Write top 8-bits of coefficient a2 in I²C address 0x20. 12. Write middle 8-bits of coefficient a2 in I²C address 0x21. 13. Write bottom 8-bits of coefficient a2 in I²C address 0x22. 14. Write top 8-bits of coefficient b0 in I²C address 0x23. 15. Write middle 8-bits of coefficient b0 in I²C address 0x24. 16. Write bottom 8-bits of coefficient b0 in I²C address 0x25. 17. Write 1 to WA bit in I²C address 0x26. The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the STA333BW generates the RAM addresses as offsets from this base value to write the complete set of coefficient data. Table 72. RAM block for biquads, mixing, scaling, bass management Index (Decimal) Index (Hex) Description Coefficient Default 0 0x00 C1H10(b1/2) 0x000000 1 0x01 C1H11(b2) 0x000000 2 0x02 C1H12(a1/2) 0x000000 3 0x03 C1H13(a2) 0x000000 4 0x04 C1H14(b0/2) 0x400000 5 0x05 Channel 1 - Biquad 2 C1H20 0x000000 … … … … … 19 0x13 Channel 1 - Biquad 4 C1H44 0x400000 20 0x14 C2H10 0x000000 C2H11 0x000000 Channel 1 - Biquad 1 Channel 2 - Biquad 1 21 0x15 … … … … … 39 0x27 Channel 2 - Biquad 4 C2H44 0x400000 DocID13773 Rev 5 57/68 68 Register description STA333BW Table 72. RAM block for biquads, mixing, scaling, bass management (continued) Index (Decimal) Index (Hex) 40 0x28 41 0x29 42 0x2A 43 0x2B 44 Description Coefficient Default C12H0(b1/2) 0x000000 C12H1(b2) 0x000000 C12H2(a1/2) 0x000000 C12H3(a2) 0x000000 0x2C C12H4(b0/2) 0x400000 45 0x2D C3H0(b1/2) 0x000000 46 0x2E C3H1(b2) 0x000000 47 0x2F C3H2(a1/2) 0x000000 48 0x30 C3H3(a2) 0x000000 49 0x31 C3H4(b0/2) 0x400000 50 0x32 Channel 1 - Prescale C1PreS 0x7FFFFF 51 0x33 Channel 2 - Prescale C2PreS 0x7FFFFF 52 0x34 Channel 1 - Postscale C1PstS 0x7FFFFF 53 0x35 Channel 2 - Postscale C2PstS 0x7FFFFF 54 0x36 Channel 3 - Postscale C3PstS 0x7FFFFF 55 0x37 TWARN / OC - Limit TWOCL 0x5A9DF7 56 0x38 Channel 1 - Mix 1 C1MX1 0x7FFFFF 57 0x39 Channel 1 - Mix 2 C1MX2 0x000000 58 0x3A Channel 2 - Mix 1 C2MX1 0x000000 59 0x3B Channel 2 - Mix 2 C2MX2 0x7FFFFF 60 0x3C Channel 3 - Mix 1 C3MX1 0x400000 61 0x3D Channel 3 - Mix 2 C3MX2 0x400000 62 0x3E Unused - - 63 0x3F Unused - - Channel 1 / 2 - Biquad 5 or 8 for XO = 000 High-pass 2nd order filter for XO 000 Channel 3 - Biquad for XO = 000 Low-pass 2nd order filter for XO 000 User-defined EQ The STA333BW can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation: Y[n] = 2 * (b0 / 2) * X[n] + 2 * (b1 / 2) * X[n-1] + b2 * X[n-2] - 2 * (a1 / 2) * Y[n-1] - a2 * Y[n-2] = b0 * X[n] + b1 * X[n-1] + b2 * X[n-2] - a1 * Y[n-1] - a2 * Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0.9999998808). 58/68 DocID13773 Rev 5 STA333BW Register description Coefficients stored in the user defined coefficient RAM are referenced in the following manner: CxHy0 = b1 / 2 CxHy1 = b2 CxHy2 = -a1 / 2 CxHy3 = -a2 CxHy4 = b0 / 2 where x represents the channel and the y the biquad number. For example, C2H41 is the b2 coefficient in the fourth biquad for channel 2. Crossover and biquad #8 Additionally, the STA333BW can be programmed for a high-pass filter (processing channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bassmanagement crossover when the XO setting is 000 (user-defined). Both of these filters when defined by the user (rather than using the preset crossover filters) are second order filters that use the biquad equation given above. They are loaded into the C12H0-4 and C3Hy0-4 areas of RAM noted in Table 72, addresses 0x28 to 0x31. By default, all user-defined filters are pass-through where all coefficients are set to 0, except the b0 / 2 coefficient which is set to 0x400000 (representing 0.5) Prescale The STA333BW provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM. All channels can use the channel-1 prescale factor by setting the Biquad link bit. By default, all prescale factors (RAM addresses 0x32 to 0x33) are set to 0x7FFFFF. Postscale The STA333BW provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This postscaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM. This postscale factor can be used in conjunction with an ADC equipped micro-controller to perform power-supply error correction. All channels can use the channel-1 postscale factor by setting the postscale link bit. By default, all postscale factors (RAM addresses 0x34 to 0x36) are set to 0x7FFFFF. When line output is being used, channel-3 postscale affects both channels 3 and 4. Thermal warning and overcurrent adjustment (TWOCL) The STA333BW provides a simple mechanism for reacting to overcurrent or thermal warning detection in the power block. When the warning occurs, the TWOCL value is used to provide output attenuation clipping on all channels. The amount of attenuation to be applied in this situation can be adjusted by modifying the overcurrent and thermal warning limiting value (RAM addr 0x37). By default, the overcurrent postscale adjustment factor is set to 0x5A9DF7 (that is, -3 dB). Once the limiting is applied, it remains until the device is reset or according to the TWRB and OCRB settings. DocID13773 Rev 5 59/68 68 Register description 7.8 STA333BW Variable max power correction registers (addr 0x27 - 0x28) D7 D6 D5 D4 D3 D2 D1 D0 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8 0 0 0 1 1 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0 1 1 0 0 0 0 0 0 MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. 7.9 Distortion compensation registers (addr 0x29 - 0x2A) D7 D6 D5 D4 D3 D2 D1 D0 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8 1 1 1 1 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0 0 0 1 1 0 0 1 1 DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1. 7.10 Fault detect recovery constant registers (addr 0x2B - 0x2C) D7 D6 D5 D4 D3 D2 D1 D0 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0 0 0 0 0 1 1 0 0 FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the TRISTATE output is immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C gives approximately 0.1 ms. Note: 60/68 0x0000 is a reserved value for these registers. DocID13773 Rev 5 STA333BW 7.11 Register description Device status register (addr 0x2D) D7 D6 D5 D4 D3 D2 D1 D0 PLLUL FAULT UVFAULT Reserved OCFAULT OCWARN TFAULT TWARN This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked. Table 73. Status register bits Bit R/W RST Name Description 0: PLL locked 7 R - PLLUL 6 R - FAULT 0: fault detected on power bridge 1: normal operation 5 R - UVFAULT 0: VCCxX internally detected < undervoltage threshold 4 R - Reserved - 3 R - OCFAULT 0: overcurrent fault detected 2 R - OCWARN 0: overcurrent warning 1 R - TFAULT 0: thermal fault, junction temperature over limit 0 R - TWARN 0: thermal warning, junction temperature is close to the fault condition 1: PLL not locked DocID13773 Rev 5 61/68 68 Applications STA333BW 8 Applications 8.1 Applications schematic Figure 21 below shows the typical applications schematic for STA333BW. Special attention has to be paid to the layout of the PCB. All the decoupling capacitors have to be placed as close as possible to the device to limit spikes on all the supplies. 8.2 PLL filter circuit It is recommended to use the above circuit and values for the PLL loop filter to achieve the best performance from the device in general applications. Note that the ground of this filter circuit has to be connected to the ground of the PLL without any resistive path. Concerning the component values, it must be taken into account that the greater the filter bandwidth, the less is the lock time but the higher is the PLL output jitter. 8.3 Typical output configuration Figure 20 shows the typical output configuration used for BTL stereo mode. Please contact STMicroelectronics for other recommended output configurations. Figure 20. Output configuration for stereo BTL mode (RL = 8  22 µH OUT1A 100 nF 100 nF 22R 6R2 470 nF Left 100 nF 330 pF 6R2 100 nF 22 µH OUT1B 22 µH OUT2A 100 nF 100 nF 22R 6R2 470 nF Right 100 nF 330 pF 6R2 100 nF 22 µH OUT2B 62/68 DocID13773 Rev 5 STA333BW Figure 21. Applications circuit 3V3 STA333BW U4 1 C14 2 + 3 100µF 25V C18 C21 1µF 25V 100nF OU T2B 4 5 6 7 8 DocID13773 Rev 5 C23 C29 100nF OU T2A 9 100nF Vc c OU T1B 10 11 12 C31 1µF 25V OU T1A C32 100nF 13 14 15 16 17 18 GN D_SU B SA TEST_MOD E VSS VCC_REG OU T2B GN D2 VCC2 OU T2A OU T1B Vc c1 GN D1 OU T1A GN D_REG VDD CONFIG VDD_DIG GN D_DI G SC L SD A IN T_LI NE R ESET SDI LR CKI BI CKI XTI GND_PLL FILTER_PLL VDD_PLL PW RD N GN D_DI G VDD_DIG OUT3B / FFX3B TWARN / OUT4A OUT3A / FFX3A EAPD / OUT4B 36 C13 35 100nF 34 33 32 SC L R11 SD A 10K IN TL 31 30 29 28 27 R ESET DATA BI CKI XTI C30 25 100nF 24 R35 2R2 3V3 23 PW DN 22 C33 21 100nF 19 1nF LR CKI 26 20 C22 R14 2K2 3V3 R36 0 C36 4. 7nF C35 680pF Applications 63/68 Package thermal characteristics 9 STA333BW Package thermal characteristics Using a double-layer PCB the thermal resistance, junction to ambient, with 2 copper ground areas of 3 x 3 cm2 and with 16 via holes is 24 °C/W in natural air convection. The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. Thus, the maximum estimated dissipated power for the STA333BW is: 2 x 20 W @ 8 , 18 V Pd max is approximately 4 W 2 x 9 W + 1 x 20 W @ 4 , 8 ,18 V Pd max is approximately 5 W Figure 22 shows the power derating curve for the PowerSSO-36 package on PCBs with copper areas of 2 x 2 cm2 and 3 x 3 cm2. Figure 22. PowerSSO-36 power derating curve Pd (W) 8 7 Copper Area 3x3 cm and via holes 6 5 STA333BW STA339BW PSSO36 PowerSSO- 4 3 Copper Area 2x2 cm and via holes 2 1 0 0 20 40 60 80 100 Tamb ( °C) 64/68 DocID13773 Rev 5 120 140 160 STA333BW 10 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 23 below shows the package outline and Table 74 gives the dimensions. Table 74. PowerSSO-36 EPD dimensions Dimensions in mm Dimensions in inches Symbol Min Typ Max Min Typ Max A 2.15 - 2.47 0.085 - 0.097 A2 2.15 - 2.40 0.085 - 0.094 a1 0.00 - 0.10 0.00 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees L 0.60 - 1.00 0.024 - 0.039 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 6.50 - 7.10 0.256 - 0.280 DocID13773 Rev 5 65/68 68 h x 45° Package mechanical data 66/68 Figure 23. PowerSSO-36 EPD outline drawing DocID13773 Rev 5 STA333BW STA333BW 11 Revision history Revision history Table 75. Document revision history Date Revision 11-Apr-2006 1 Initial release. 2 Added: Electrical specifications, digital section Power on sequence Processing data path Application Improved: Pin description Absolute maximum ratings Recommended operative conditions Output configuration Device status register 3 Updated presentation Document status updated to Datasheet Modified layout of chapter Chapter 1: Description Removed master mute from Section 7.2 on page 41 Improved presentation of applications circuit in Figure 21 on page 63 18-Sep-2013 4 Added Section 4 on page 16 Modified Note:: The read write operation on RAM coefficients works only if RLCKI (pin29) is switching and stable (ref. Table 8, tLRJT timing) and PLL must be locked (ref bit D7 reg 0x2D). on page 56 Updated Company information appearing on last page of document 13-Feb-2014 5 Updated order code Table 1 on page 1 26-Jul-2007 26-Jan-2011 Changes DocID13773 Rev 5 67/68 68 STA333BW Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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