STA333SML

STA333SML 2-channel microless high-efficiency digital audio system Sound Terminal® Datasheet - production data Applications  LCDs  DVDs  Cradles  Digital speakers  Wireless-speaker cradles CSP 5 x 6 array Description The STA333SML is an integrated circuit comprising digital audio processing, digital amplifier control and an FFX power output stage to create a high-power, single-chip FFX solution for all-digital amplification with high quality and high efficiency. Features  Wide-range supply voltage (4.5 V - 18 V)  2 channels of ternary PWM (stereo mode) The STA333SML power section consists of four independent half-bridge stages. Two channels can be provided by two full bridges, providing up to 10 W + 10 W of power.  2 channels of 24-bit FFXTM  100 dB SNR and dynamic range  Digital gain +24dB Also featured in the STA333SML are new advanced modes for AM radio interference reduction. The serial audio data input interface accepts the popular I²S format. Two channels of FFXTM processing are provided.  Sample rates (fs) from 32 to 48 kHz  Fixed MCLK at 256 x fs  Automatic zero-detect mute  Automatic invalid input detect mute The STA333SML is part of the Sound Terminal® family that provides full digital audio streaming to the speaker, offering cost effectiveness, lowpower dissipation and sound enrichment.  Short-circuit detection at startup (Out-VCC, Out-Gnd, Out 1b-Out 2a)  2-channel I²S input data interface  2 Hz DC cut filter (input)  96 kHz internal processing sample rate, 24-bit precision  Embedded thermal-overload and short-circuit protection Table 1. Device summary Order code Package Packaging STA333SML CSP 5x6 array Tube STA333SMLTR CSP 5x6 array Tape and reel March 2014 This is information on a product in full production. DocID025317 Rev 2 1/17 www.st.com Contents STA333SML Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.4 Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.5 Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.6 Power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.8 Serial audio interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.8.1 3.9 4 2/17 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 5 Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DocID025317 Rev 2 STA333SML 1 Block diagram Block diagram Figure 1. Block diagram Protection current/thermal I²S interface Volume control Channel 1A Power control Logic Channel 1B FFX Channel 2A Regulators Channel 2B PLL Bias Digital DSP Power DocID025317 Rev 2 3/17 17 Pin description STA333SML 2 Pin description 2.1 Pinout Figure 2. Pin connections (package top view) 1 2 3 4 5 GND 1 OUT1 A NC VD D R E G SDI B GND 1 VCC1 NC LRCKI VD D _ D IG C OUT1 B VCC1 G ND REG BICK I G ND _ D IG D OUT2 A VCC2 VCCRE INTLINE E GND 2 VCC2 NC PWDN VD D _ P L L F GND 2 OUT2 B NC VSS GND _ P L L A 4/17 DocID025317 Rev 2 X TI STA333SML 2.2 Pin description Pin list Table 2. Pin description Pin n° Name Description Pad information I/O pins B4 LRCKI I²S Left/Right clock C4 BICKI I²S serial clock A5 SDI I²S serial data channels 1 & 2 D5 XTI Master clock input E4 PWDN D4 INTLINE -’0’ = power-down; ‘1’=normal operation -’0’ = power bridge in fault; ‘1’=normal operation Power output pins A2 OUT1A Positive output 1 C1 OUT1B Negative output 1 D1 OUT2A Positive output 2 F2 OUT2B Negative output 2 Power supplies (preliminary) B2/C2 VCC1 Positive supply (upper MOSFET) to left H-bridge P output E2/D2 VCC2 Positive supply (upper MOSFET) to right H-bridge P output A1/B1 GND1 Negative supply (lower MOSFET) to left H-bridge P output E1/F1 GND2 Negative supply (lower MOSFET) to right H-bridge P output D3 VCCREG Reference voltage to VCC C3 GNDREG Reference voltage to ground A4 VDDREG Reference voltage to 3.3 V F4 VSS Reference voltage to VCC - 3.3 V B5 VDD_DIG Digital supply C5 GND_DIG Digital ground E5 VDD_PLL PLL supply F5 GND_PLL PLL ground A3, B3, E3, F3 NC These pins are output pins that must be externally filtered. Do not connect these pins to external supply voltage. Not connected DocID025317 Rev 2 5/17 17 Electrical specifications STA333SML 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Typ. Max. Unit VCC Analog supply voltage (pins VCCx) -0.3 - 20 V VDD Digital supply voltage (pins VDD_DIG) -0.3 - 4.0 V Logic input interface -0.3 - 4.0 V 0 - 150 °C -40 - 150 °C IL Top Operating junction temperature Tstg Storage temperature Warning: 3.2 Min. Stresses beyond those listed in Table 3: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Table 5: Recommended operating conditions are not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. In the real application, a power supply with nominal value rated within the limits of the recommended operating conditions may rise beyond the maximum operating conditions for a short time when no or very low current is sunk (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded. Thermal data Table 4. Thermal data Symbol Parameter RTh(j-case) Thermal resistance junction to ambient 6/17 Min. Typ. Max. Unit - 51.5 140 150 160 °C °C/W Tsd Thermal-shutdown junction temperature Tw Thermal-warning temperature - 130 - °C Thsd Thermal-shutdown hysteresis 18 20 22 °C DocID025317 Rev 2 STA333SML 3.3 Electrical specifications Recommended operating conditions Table 5. Recommended operating conditions Symbol 3.4 Parameter Min. Typ. Max. Unit VCC Analog supply voltage (VCCx) 4.5 - 18 V VDD Digital supply voltage (VDD_DIG) 3.0 3.3 3.6 V IL Logic input interface 3.0 3.3 3.6 V Tamb Ambient temperature 0 - 70 °C Min. Typ. Max. Unit Electrical specifications - digital section Table 6. Electrical characteristics for digital section Symbol Iil Parameter Conditions Input current, no pull-up or pull-down resistor Vi = 0 V - - ±10 µA Vi = VDD = 3.6 V - - ±10 µA Vil Low-level input voltage - - - 0.2 * VDD V Vih High-level input voltage - 0.8 * VDD - - V Vol Low-level output voltage Iol = 2 mA - - 0.4 * VDD V Voh High-level output voltage Ioh = 2 mA 0.8 * VDD - - V Ipu Pull-up current - 25 66 125 µA Rpu Equivalent pull-up resistance - - 50 - k Iih DocID025317 Rev 2 7/17 17 Electrical specifications 3.5 STA333SML Electrical specifications - power section The specifications in Table 7 below are given for the conditions VCC = 13 V, VDD = 3.3 V, fSW = 384 kHz, Tamb = 25 °C and RL = 8 , unless otherwise specified. Table 7. Electrical specifications for power section Symbol Po RdsON Parameter Conditions Min. Typ. Max. THD = 1% - 8 - THD = 10% - 10 - ld = 1 A - 106 - - 10 µA Output power BTL W Power Pchannel/N-channel MOSFET (total bridge) m ldss Power PVCC = 18 V channel/N-channel leakage gP Power P-channel RdsON matching ld = 1 A 95 - - % gN Power N-channel RdsON matching ld = 1 A 95 - - % ILDT Low-current dead time (static) Resistive load, refer to Figure 4 - 5 10 ns IHDT High-current dead time (dynamic) Refer to Figure 5 - 10 20 ns tr Rise time Resistive load, refer to Figure 4 - 8 10 ns tf Fall time Resistive load, refer to Figure 4 - 8 10 ns Supply voltage - 4.5 - 18 V Supply current from VCC in power down PWRDN = 0 30 60 200 µA Supply current from VCC in operation PCM input signal = -60 dBFS Switching frequency = 384 kHz No LC filters - 30 50 mA 10 30 50 mA 8 11 25 mA VCC IVCC Supply current for FFX Internal clock = 49.152 MHz IVDD_DIG processing (reference only) Supply current in standby Av_DIG 8/17 Unit - Digital Gain 24 ISCP Short-circuit protection High-impedance output VOVP Overvoltage protection threshold VUVP Undervoltage protection threshold - tmin Output minimum pulse width No load (1) 2.7 3.8 dBFS 5.0 22.9 DocID025317 Rev 2 A V - 3.5 4.3 V 20 30 60 ns STA333SML Electrical specifications Table 7. Electrical specifications for power section (continued) Symbol THD+N DR Parameter Conditions Min. Typ. Max. Unit Total harmonic distortion and noise FFX stereo mode, Po = 1 W, f = 1 kHz - 0.05 0.2 % Dynamic range - - 100 - dB Signal to noise ratio in ternary mode A-weighted - 100 - SNR dB Signal to noise ratio in binary mode A-weighted - 90 - - 80 - dB PSRR FFX stereo mode, < 5 kHz, Power supply rejection ratio VRIPPLE = 1 V RMS audio input = dither only XTALK Crosstalk FFX stereo mode, < 5 kHz, One channel driven at 1 W the other channel measured - 80 - dB Peak efficiency in FFX mode Po = 2 x 10 W into 8  - 90 - %  1. The ISCP current limit data is for 1 channel of BTL configuration, thus, 2 * ISCP drives the 2-channel BTL configuration. DocID025317 Rev 2 9/17 17 Electrical specifications 3.6 STA333SML Power-off sequence The power-off sequence shown in Figure 3 below ensures a pop-free turn-off. Figure 3. Power-off sequence No specific VCC and VDD_DIG turn-off sequence is required VCC Don’t care Don’t care VDD_DIG XTI 3.7 Don’tcare Don’t care Testing Figure 4. Test circuit OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 + - V67 = vdc = Vcc/2 gnd D03AU1458 Figure 5. Current deadtime test circuit High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q2 Q1 INA L67 22μ Q3 C69 470nF DTin(B) INB Iout=4A Lout = 1.5 A C71 470nF C70 470nF Q4 Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure 10/17 M64 OUTB L68 22μ Iout=4A Lout = 1.5 A M57 DTout(B) Rload=8Ω OUTA DocID025317 Rev 2 M63 D03AU1517 STA333SML Electrical specifications 3.8 Serial audio interface description 3.8.1 Serial audio interface protocols The STA333SML serial audio input was designed to interface with standard digital audio components and to accept I²S formats. The STA333SML always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin B4), serial clock BICKI (pin C4), and serial data SDI (pin A5). The available formats are shown in Figure 6, Figure 7 and Figure 8. Figure 6. I²S -16 fs 16 Clks 16 Clks LRCKI Right Channel Left Channel BICKI SDI 14 14 0 8 0 8 Figure 7. I²S - 24fs 24 Clks 24 Clks LRCKI Right Channel Left Channel BICKI SDI 22 11 19 7 0 0 0 15 22 11 19 11 0 0 0 15 Figure 8. I²S - 32fs 32 Clks 32 Clks LRCKI Right Channel Left Channel BICKI SDI 23 8 19 4 15 0 0 0 DocID025317 Rev 2 23 8 19 4 15 0 0 0 11/17 17 Electrical specifications 3.9 STA333SML Application information Figure 9. Application diagram 12/17 DocID025317 Rev 2 STA333SML 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. The STA333SML comes in a CSP 5x6 array package. Figure 10 below shows the package outline and gives the dimensions. Figure 10. CSP 5x6 array outline drawing 7224730_I DocID025317 Rev 2 13/17 17 Package mechanical data STA333SML Table 8. CSP 5x6 array package dimensions mm Symbol Min. Typ. Max. A 0.585 0.65 0.715 A1 0.210 0.25 0.29 A2 0.38 0.4 0.42 b 0.265 0.315 0.365 D 2.52 2.57 2.62 D1 E 2 3.19 E1 3.29 2.5 e 0.45 0.5 0.55 se 0.2 0.25 0.3 fD 0.277 0.285 0.293 fE 0.362 0.370 0.378 ccc 14/17 3.24 0.08 DocID025317 Rev 2 STA333SML 4.1 Package mechanical data Soldering information Figure 11. Recommended soldering reflow profile for mounting on PCB Table 9. Recommended soldering reflow values for mounting on PCB Profile Typ. Max. Temp. gradient in preheat (T = 70 - 180 °C) 0.9 °C/s 3 °C/s Temp.gradient (T = 200 - 225 °C) 2 °C/s 3 °C/s Peak temp. in reflow 240 - 245 °C 260 °C Time above 220 °C 60 s 90 s -2 to -3 °C -6 °C Temp. gradient in cooling Time from 50 to 220 °C 160 to 220 s DocID025317 Rev 2 15/17 17 Revision history 5 STA333SML Revision history Table 10. Document revision history 16/17 Date Revision Changes 15-Oct-2013 1 Initial release. 26-Mar-2014 2 Updated: Figure 1 on page 3 and Figure 2 on page 4 DocID025317 Rev 2 STA333SML Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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