STA333SMLTR

STA333ML 2-channel microless high-efficiency digital audio system Sound Terminal ® Datasheet - production data  Wireless speaker cradles Description The STA333ML is a single die embedding digital audio processing and high-efficiency power amplification, capable of operating without the aid of an external microcontroller. PowerSSO-36 with exposed pad down (EPD) The STA333ML is part of the Sound Terminal® family that provides full digital audio streaming to the speakers and offers cost effectiveness, low power dissipation and sound enrichment. Features  Wide supply voltage range (4.5 - 20 V)  2 x 20 W into 8 at VCC = 18 V The STA333ML combines a unique 24-bit DDX® digital class-D ternary modulator together with an extremely low RdsON stereo power DMOS stage. The latter is capable of a total output power of 2 x 20 W with outstanding performance in terms of efficiency (>90%), THD, SNR and EMI.  PowerSSO-36 exposed pad package  2 channels of 24-bit DDX®  100-dB SNR and dynamic range  Selectable 32 kHz to 48 kHz input sample rates The microless feature allows its use in low-cost applications (cradles, digital speakers, audio terminals) where no microcontroller is needed.  Automatic zero-detect mute  Automatic invalid input detect mute  2-channel I2S input data interface  Selectable clock input ratio (256 or 364 * fs)  Max power correction for lower full power  96 kHz internal processing sample rate, 24-bit precision  Embedded thermal overload and short-circuit protection  Filterless configuration option The serial audio data interface accepts the universally used I2S format. Basic features, such as the oversampling clock, gain, and I2S format, can be set using a minimal number of selection pins. The STA333ML is self-protected against thermal overload, overcurrent, short-circuit and overvoltage conditions. The fault condition is also signalled on an external pin (INT_LINE) for specific requirements. Applications  LCDs  DVDs  Cradles  Digital speakers Table 1. Device summary Order code Package Packaging STA333ML13TR PowerSSO-36 EPD Tape and reel March 2019 This is information on a product in full production. DocID13177 Rev 8 1/23 www.st.com Contents STA333ML Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 5 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.4 Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.5 Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.6 Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 Fade-in/out feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 Oversampling selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.6 Gain selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.7 Power-down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 Applications schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 PLL filter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/23 DocID13177 Rev 8 STA333ML 9 Contents Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DocID13177 Rev 8 3/23 23 Block diagram 1 STA333ML Block diagram Figure 1. Block diagram Protection current/thermal I 2S interface Volume control Channel 1A Logic Power control Channel 1B DDX Channel 2A Regulators Channel 2B PLL Bias 4/23 DocID13177 Rev 8 STA333ML 2 Pin description Pin description Figure 2. Pin connections (top view) GND_SUB 1 36 VDD_DIG FMT 2 35 GND_DIG TEST_MODE 3 34 GAIN VSS_REG 4 33 ONSEL VCC_REG 5 32 INT_LINE OUT2B 6 31 RESET GND2 7 30 SDI VCC2 8 29 LRCKI OUT2A 9 28 BICKI OUT1B 10 27 XTI VCC1 11 26 GND_PLL GND1 12 25 FILTER_PLL OUT1A 13 24 VDD_PLL GND_REG 14 23 PWRDN 22 GND_DIG EP, exposed pad (device ground) VDD_REG 15 CONFIG 16 21 VDD_DIG N.C. 17 20 N.C. N.C. 18 19 N.C. Table 2. Pin description Pin Name Type Description 1 GND_SUB Gnd 2 FMT In Serial format: 0: I2S format 1: left justified 3 TEST_MODE In This pin must be connected to GROUND 4 VSS_REG Analog Internal reference at VCC - 3.3 V 5 VCC_REG Analog Internal VCC reference 6 OUT2B Out Output half bridge 2B 7 GND2 Gnd Power negative supply 8 VCC2 Power Power positive supply 9 OUT2A Out Output half bridge 2A 10 OUT1B Out Output half bridge 1B Substrate ground DocID13177 Rev 8 5/23 23 Pin description STA333ML Table 2. Pin description (continued) 6/23 Pin Name Type Description 11 VCC1 Power Power positive supply 12 GND1 Gnd Power negative supply 13 OUT1A Out Output half-bridge 1A 14 GND_REG Analog Internal ground reference 15 VDD_REG Analog Internal 3.3 V reference voltage 16 CONFIG In Configuration mode, must be connected to ground 17 N.C. - Not connected 18 N.C. - Not connected 19 N.C. - Not connected 20 N.C. - Not connected 21 VDD_DIG Power 22 GND_DIG Gnd 23 PWRDN In 24 VDD_PLL Power Positive supply for PLL 25 FILTER_PLL In Connection to PLL filter 26 GND_PLL Gnd Negative supply for PLL 27 XTI In PLL input clock, 256 * fs or 384 * fs 28 BICKI In I2S serial clock 29 LRCKI In I2S left/right clock 30 SDI In I2S serial data channel 31 RESET In Reset 32 INT_LINE Out 33 ONSEL In Oversampling selector: 0: 256 * fs 1: 384 * fs 34 GAIN In Gain selector: 0: 0 dBFs 1: 24 dBFs 35 GND_DIG Gnd Digital ground 36 VDD_DIG Power Digital supply - EP - Positive supply digital Digital ground Power-down: 0: low-power mode 1: normal operation Fault interrupt Exposed pad for PCB heatsink, to be connected to ground plane DocID13177 Rev 8 STA333ML Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol VCC VL 3.2 Parameter Power supply voltage (pins VCC1, VCC2) Logic input interface Min. Typ. Max. Unit - - 23 V -0.3 - 4 V VDD Digital supply (pin VDD_DIG) - - 4 V Top Operating junction temperature 0 - 150 °C Tstg Storage temperature -40 - 150 °C Min. Typ. Max. Unit - 1.5 2 °C/W Thermal data Table 4. Thermal data Symbol Parameter RTh(j-case) Thermal resistance junction to case (thermal pad) 3.3 Tsd Thermal shutdown junction temperature 140 - 150 °C Thsd Thermal shutdown hysteresis 18 20 22 °C Recommended operating condition Table 5. Recommended operating condition Symbol Min. Typ. Max. Unit Power supply voltage (pins VCC1, VCC2) 4.5 - 20.0 V Logic input interface 2.7 3.3 3.6 V VDD Digital supply (pin VDD_DIG) 2.7 3.3 3.6 V Tamb Ambient temperature 0 - 70 °C VCC VL Parameter DocID13177 Rev 8 7/23 23 Electrical specifications 3.4 STA333ML Electrical specifications - digital section Table 6. Electrical specifications for digital section Symbol Parameter Iil Input current without bias device Iih 3.5 Conditions Min. Typ. Max. Unit Vi = 0 V -10 - 10 µA Vi = VDD = 3.6 V -10 - 10 µA Vil Low-level input voltage - - - 0.2 * VDD V Vih High-level input voltage - 0.8 * VDD - - V Vol Low-level output voltage Iol = 2 mA - - 0.4 * VDD V Voh High-level output voltage Ioh = 2 mA 0.8 * VDD - - V Ipu Pull-up/down current - -25 66 125 µA Rpu Equivalent pull-up/down resistance - - 50 - k Electrical specifications - power section The specifications given here are with the operating conditions: VCC = 18 V, VDD = 3.3 V, fsw = 384 kHz, Tamb = 25 °C, RL = 8  unless otherwise specified Table 7. Electrical specifications for power section Symbol Min. Typ. Max. THD = 1% - 16 - THD = 10% - 20 - On resistance of power P-channel/N-channel ld = 1 A MOSFET (total bridge) - 180 250 m ldss Power P-channel/N-channel leakage current - - - 10 A gP Power P-channel RdsON matching ld = 1 A 95 - - % gN Power N-channel RdsON matching ld = 1 A 95 - - % ILDT Low current dead time (static) Resistive load Figure 4 - 5 10 ns IHDT High current dead time Load = 1.5 A (Figure 5) (dynamic) - 10 20 ns Rise time - 8 10 ns Po RdsON tr 8/23 Parameter Conditions Output power BTL Unit W Resistive load Figure 4 DocID13177 Rev 8 STA333ML Electrical specifications Table 7. Electrical specifications for power section (continued) Symbol tf Parameter Conditions Min. Typ. Max. Unit - 8 10 ns 0.03 0.06 0.2 mA - 30 50 mA Fall time Resistive load Figure 4 Supply current from VCC in power down PWRDN = 0 Supply current from VCC in operation PCM Input signal = -60 dBFs. Switching frequency = 384 kHz No LC filters Supply current DDX processing (reference only) Internal clock = 49.152 MHz 10 30 50 mA Supply current in standby - 8 11 25 mA ISCP short-circuit protection Hi-Z output 2.7 3.8 5.0 A UVL Undervoltage protection threshold - - 3.5 4.3 V tmin Output minimum pulse No load width 20 30 60 ns DR Dynamic range - - 100 - dB Signal-to-noise ratio A-weighted - 100 - dB THD+N Total harmonic distortion + noise Po = 1 W, f = 1 kHz - 0.05 0.2 % PSRR DDX stereo,