STA350BW
2.1-channel high-efficiency digital audio system
Sound Terminal®
Datasheet - production data
EQ-DRC for DRC based on filtered signals
Dedicated LFE processing for bass boosting
with 0.125 dB/step resolution
Audio presets:
– 15 preset crossover filters
– 5 preset anti-clipping modes
– Preset nighttime listening mode
Individual channel and master soft/hard mute
PowerSSO-36
Independent channel volume and DSP bypass
with exposed pad down (EPD)
Automatic zero-detect mute
Automatic invalid input-detect mute
I2S input data interface
Features
Input and output channel mapping
Wide-range supply voltage
– 5 V to 26 V (operating range)
– 30 V (absolute maximum rating)
Up to 8 user-programmable biquads per
channel
Four power output configurations
– 2 channels of ternary PWM (stereo mode)
(2 x 50 W into 6 at 25 V)
– 3 channels - left, right using binary and LFE
using ternary PWM (2.1 mode) (2 x 18 W +
1 x 40 W into 2 x 4 , 1 x 8 at 25 V)
– 2 channels of ternary PWM (2 x 50 W) +
stereo lineout ternary
– 1 channel of ternary PWM as mono-BTL
(1 x 90 W into 3 at 24.5 V)
FFX™ 100 dB SNR and dynamic range
3 coefficient banks for EQ presets storing with
fast recall via I2C interface
Extended coefficient dynamic up to -4..4 for
easy implementation of high shelf filters
Bass/treble tones and de-emphasis control
Selectable high-pass filter for DC blocking
Advanced AM interference frequency
switching and noise suppression modes
Selectable high or low bandwidth
noise-shaping topologies
Selectable clock input ratio
I2C control with selectable device address
96 kHz internal processing sample rate with
quantization error noise shaping for very low
cutoff frequency filters
Digital gain/attenuation +42 dB to -80 dB with
0.125 dB/step resolution
Thermal overload and short-circuit protection
embedded
Soft-volume update with programmable ratio
Video apps: 576 x Fs input mode supported
Individual channel and master gain/attenuation
Fully compatible with STA339BW and
STA339BWS
Selectable 32 to 192 kHz input sample rates
Two independent DRCs configurable as a
dual-band anti-clipper (B2DRC) or independent
limiters/compressors
September 2013
This is information on a product in full production.
DocID018572 Rev 4
1/88
www.st.com
Contents
STA350BW
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1
2
3
4
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 15
3.5
Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 16
Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Mono parallel BTL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.0.1
Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.0.2
Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.0.3
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6
Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7
I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1
2/88
Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.1
Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.2
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.3
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.3
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3.1
Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3.2
Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DocID018572 Rev 4
STA350BW
Contents
7.4
8
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.4.1
Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.4.2
Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.4.3
Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.4.4
Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.4.5
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4.6
Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.1
8.2
8.3
8.4
8.5
Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1.1
Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1.2
Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.1.3
Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.1.4
Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.1.5
Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.2.1
Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.2.2
Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.2.3
Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.2.4
Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2.5
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.3.1
FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.3.2
FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.3.3
Overcurrent warning detect adjustment bypass . . . . . . . . . . . . . . . . . . 41
Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.4.1
High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.4.2
De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.4.3
DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.4.4
Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.4.5
Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.4.6
Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 42
8.4.7
Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.4.8
Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.5.1
Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Contents
STA350BW
8.6
8.7
8.8
8.9
8.10
8.5.2
Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.5.3
Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.5.4
AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.5.5
PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.5.6
Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . 44
8.5.7
Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.5.8
Soft-volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.6.1
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.6.2
Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.6.3
Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 52
8.6.4
LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.6.5
Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.6.6
IC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.6.7
External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 53
8.7.1
Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.7.2
Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.7.3
Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.7.4
Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.7.5
Channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Audio preset registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . 55
8.8.1
Audio preset register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.8.2
Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.8.3
AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.8.4
Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 57
8.9.1
Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.9.2
EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.9.3
Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.9.4
Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.9.5
Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.9.6
Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.10.1
8.11
4/88
Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 59
DocID018572 Rev 4
STA350BW
Contents
8.12
8.11.1
Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.11.2
Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.11.3
Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.11.4
Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.11.5
Limiter 1 extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . . 63
8.11.6
Limiter 1 extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . . 63
8.11.7
Limiter 2 extended attack threshold (addr 0x34) . . . . . . . . . . . . . . . . . . 64
8.11.8
Limiter 2 extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . . 64
User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 64
8.12.1
Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.12.2
Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.12.3
Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.12.4
Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.12.5
Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.12.6
Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.12.7
Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.12.8
Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.12.9
Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.12.10 Coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.12.11 Coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.12.12 Coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.12.13 Coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.12.14 Coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.12.15 Coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.12.16 Coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.12.18 User-defined EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.12.19 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.12.20 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.12.21 Overcurrent post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8.13
Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 71
8.14
Variable distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . 71
8.15
Fault detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 72
8.16
Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.17
EQ coefficients and DRC configuration register (addr 0x31) . . . . . . . . . . 73
8.18
Extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . . 74
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Contents
STA350BW
8.18.1
Dual-band DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.18.2
EQ DRC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.18.3
Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.18.4
Extended attack rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.18.5
Extended BIQUAD selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.19
EQ soft-volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . . 77
8.20
DRC RMS filter coefficients (addr 0x39-0x3E) . . . . . . . . . . . . . . . . . . . . . 78
8.21
Extra volume resolution configuration registers (address 0x3F) . . . . . . . 79
8.22
Quantization error noise correction (address 0x48) . . . . . . . . . . . . . . . . . 80
8.23
Extended coefficient range up to -4...4 (address 0x49, 0x4A) . . . . . . . . . 81
8.24
Miscellaneous registers (address 0x4B, 0x4C) . . . . . . . . . . . . . . . . . . . . 82
8.24.1
Rate powerdown enable (RPDNEN) bit (address 0x4B, bit D7) . . . . . . 82
8.24.2
Noise-shaping on DC cut filter enable (NSHHPEN) bit
(address 0x4B, bit D6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.24.3
Bridge immediate off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . . . 82
8.24.4
Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2) . . . . . . . 83
8.24.5
Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C,
bit D4, D3, D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6/88
DocID018572 Rev 4
STA350BW
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Demonstration board, 2.0 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Mono parallel BTL schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
THD+N vs. output power (VCC = 25 V, load = 6 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
THD+N vs. output power (VCC = 18 V, load = 8 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output power vs. VCC (load = 6 W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output power vs. VCC (load = 8 W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Efficiency vs. output power (VCC = 25 V, load = 6 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Efficiency vs. output power (VCC = 25 V, load = 8 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
THD+N vs. output power (VCC = 25 V, load = 3 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output power vs. VCC (load = 3 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Efficiency vs. output power (VCC = 26 V, load = 3 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Efficiency vs. output power (VCC = 18 V, load = 3 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Timing diagram for SAI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Left and right processing - part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Processing - part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.0 channels (OCFG = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.1 channels (OCFG = 01) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.1 channels (OCFG = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
B2DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
EQDRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Extra resolution volume scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Biquad filter structure with quantization error noise-shaping . . . . . . . . . . . . . . . . . . . . . . . 81
Double-layer PCB with 2 copper ground areas and 24 via holes . . . . . . . . . . . . . . . . . . . 84
PowerSSO-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
DocID018572 Rev 4
7/88
88
List of tables
STA350BW
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
8/88
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timing parameters for slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Serial audio input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 37
Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 38
Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FFX compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Overcurrent warning bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Post-scale link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Soft-volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DocID018572 Rev 4
STA350BW
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
List of tables
IC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Master volume offset as a function of MV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Channel volume as a function of CxV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Audio preset gain compression/limiters selection for AMGC[3:2] = 00. . . . . . . . . . . . . . . . 55
AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Audio preset AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . 59
Limiter attack rate as a function of LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Limiter release rate as a function of LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Limiter attack threshold as a function of LxAT bits (AC-mode). . . . . . . . . . . . . . . . . . . . . . 62
Limiter release threshold as a function of LxRT bits (AC-mode) . . . . . . . . . . . . . . . . . . . . 62
Limiter attack threshold as a function of LxAT bits (DRC -mode) . . . . . . . . . . . . . . . . . . . . 63
Limiter release threshold as a as a function of LxRT bits (DRC-mode) . . . . . . . . . . . . . . . 63
RAM block for biquads, mixing, scaling and bass management. . . . . . . . . . . . . . . . . . . . . 70
Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
EQ RAM select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Anti-clipping and DRC preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Anti-clipping selection for AMGC[3:2] = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Biquad filter settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DocID018572 Rev 4
9/88
88
Description
1
STA350BW
Description
The STA350BW is an integrated solution of digital audio processing, digital amplifier control,
and FFX-power output stage, thereby creating a high-power single-chip FFX™ solution
comprising high-quality, high-efficiency, and all-digital amplification.
The STA350BW is based on an FFX (fully flexible amplification) processor, a proprietary
technology from STMicroelectronics. FFX is the evolution and the enlargement of ST’s
ternary technology: the new processor can be configured to work in ternary, binary, binary
differential and phase-shift PWM modulation schemes.
The STA350BW contains the ternary, binary and binary differential implementations, a
subset of the full capability of the FFX processor.
The STA350BW is part of the Sound Terminal® family that provides full digital audio
streaming to the speaker, offering cost effectiveness, low power dissipation and sound
enrichment.
The STA350BW power section consists of four independent half-bridges. These can be
configured via digital control to operate in different modes. 2.1 channels can be provided by
two half-bridges and a single full-bridge, providing up to 2 x 18 W + 1 x 40 W of music output
power, by using standard 4 and 8 speakers. Two channels can be provided by two fullbridges, providing up to 2 x 50 W of music power, by using standard 6 speaker or
2 x 40 W by using 8 speakers at 25 V. The IC can also be configured as 2.1 channels with
2 x 40 W provided by the device and external power for FFX power drive. If configured as
mono-BTL, the latter is capable of providing up to 1 x 90 W on a standard 3 load or
1 x 75 W by using a 4 setting the supply voltage at 25 V. Please refer to the package
thermal characteristics and application suggestions for more details.
Also provided in the STA350BW are a full assortment of digital processing features. This
includes up to 8 programmable biquads (EQ) per channel. Special digital signal processing
techniques are available in order to manage low-frequency quantization noise in case of
very low frequency cutoff filter thresholds. The coefficient range -4..4 allows the easy
implementation of high shelf filters. Available presets allow the advantage of earlier time-tomarket by substantially reducing the amount of software development needed for certain
functions. This includes audio preset volume loudness, preset volume curves and preset EQ
settings. There are also new advanced AM radio interference reduction modes. Dual-band
DRC dynamically equalizes the system to provide speaker linear frequency response
regardless of output power level. This feature independently processes the two bands,
controlling dynamically the output power level in each band and so providing better sound
clarity.
The serial audio data input interface accepts all possible formats, including the popular I2S
format. Three channels of FFX processing are provided. This high-quality conversion from
PCM audio to FFX PWM switching waveform provides over 100 dB SNR and dynamic
range.
10/88
DocID018572 Rev 4
STA350BW
1.1
Description
Block diagram
Figure 1. Block diagram
2
I C
Pro tection
curre nt/the rm al
2
I S
in terfa ce
C han nel
1A
Pow er
co ntro l
Vo lu me
control
Log ic
C hann el
1B
FFX
Ch anne l
2A
R egulat ors
C hann el
2B
PLL
Bias
D ig ita l DSP
Po wer
DocID018572 Rev 4
AM045167v1
11/88
88
Pin connections
STA350BW
2
Pin connections
2.1
Connection diagram
Figure 2. Pin connection PowerSSO-36 (top view)
GND_SUB
1
36
VDD_DIG
SA
2
35
GND_DIG
TEST_MODE
3
34
SCL
VSS
4
33
SDA
VCC_REG
5
32
INT_LINE
OUT2B
6
31
RESET
GND2
7
30
SDI
VCC2
8
29
LRCKI
OUT2A
9
28
BICKI
OUT1B
10
27
XTI
VCC1
11
26
GND_PLL
GND1
12
25
FILTER_PLL
OUT1A
13
24
VDD_PLL
GND_REG
14
23
PWRDN
VDD
15
22
GND_DIG
CONFIG
16
21
VDD_DIG
OUT3B/FFX3B
17
20
TWARN/OUT4A
OUT3A/FFX3A
18
19
EAPD/OUT4B
D05AU1638
2.2
AM045168v1
Pin description
Table 1. Pin description
Pin
12/88
Type
Name
Description
1
GND
GND_SUB
Substrate ground
2
I
SA
I2C select address (pull-down)
3
I
TEST_MODE
This pin must be connected to ground (pull-down)
4
I/O
VSS
Internal reference at Vcc-3.3 V
5
I/O
VCC_REG
Internal Vcc reference
6
O
OUT2B
Output half-bridge 2B
7
GND
GND2
Power negative supply
8
Power
VCC2
Power positive supply
9
O
OUT2A
Output half-bridge 2A
10
O
OUT1B
Output half-bridge 1B
DocID018572 Rev 4
STA350BW
Pin connections
Table 1. Pin description (continued)
Pin
Type
Name
Description
11
Power
VCC1
Power positive supply
12
GND
GND1
Power negative supply
13
O
OUT1A
Output half-bridge 1A
14
GND
GND_REG
Internal ground reference
15
Power
VDD
Internal 3.3 V reference voltage
16
I
CONFIG
Parallel mode command
17
O
OUT3B/FFX3B
PWM out CH3B / external bridge driver
18
O
OUT3A/FFX3A
PWM out CH3A / external bridge driver
19
O
EAPD/OUT4B
Power-down for external bridge / PWM out CH4B
20
I/O
TWARN/OUT4A
Thermal warning from external bridge (pull-up when input)
/ PWM out CH4A
21
Power
VDD_DIG
Digital supply voltage
22
GND
GND_DIG
Digital ground
23
I
PWRDN
Power down (pull-up)
24
Power
VDD_PLL
Positive supply for PLL
25
I
FILTER_PLL
Connection to PLL filter
26
GND
GND_PLL
Negative supply for PLL
27
I
XTI
PLL input clock
28
I
BICKI
I2S serial clock
29
I
LRCKI
I2S left/right clock
30
I
SDI
I2S serial data channels 1 and 2
31
I
RESET
Reset (pull-up)
32
O
INT_LINE
Fault interrupt
33
I/O
SDA
I2C serial data
34
I
SCL
I2C serial clock
35
GND
GND_DIG
Digital ground
36
Power
VDD_DIG
Digital supply voltage
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88
Electrical specifications
STA350BW
3
Electrical specifications
3.1
Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol
Max
Unit
-0.3
30
V
VDD_DIG Digital supply voltage
-0.3
4
V
VDD_PLL PLL supply voltage
-0.3
4
Vcc
Parameter
Power supply voltage (VCCxA, VCCxB)
Typ
Top
Operating junction temperature
-20
150
°C
Tstg
Storage temperature
-40
150
°C
Warning:
3.2
Min
Stresses beyond those listed in Table 2 above may cause
permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any
other conditions beyond those indicated under
“Recommended operating conditions” are not implied.
Exposure to AMR conditions for extended periods may affect
device reliability. In the real application, power supplies with
nominal values rated within the recommended operating
conditions may rise beyond the maximum operating
conditions for a short time when no or very low current is
sunk (amplifier in mute state). In this case the reliability of the
device is guaranteed, provided that the absolute maximum
ratings are not exceeded.
Thermal data
Table 3. Thermal data
Symbol
Parameter
Min
Max
Unit
1.5
°C/W
Rth j-case
Thermal resistance junction-case (thermal pad)
Tth-sdj
Thermal shutdown junction temperature
150
°C
Tth-w
Thermal warning temperature
130
°C
Tth-sdh
Thermal shutdown hysteresis
20
°C
Rth j-amb
Thermal resistance junction-ambient
(1)
1. See Section 9: Package thermal characteristics on page 84 for details.
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Typ
DocID018572 Rev 4
STA350BW
3.3
Electrical specifications
Recommended operating conditions
Table 4. Recommended operating conditions
Symbol
Vcc
Min
Power supply voltage (VCCxA, VCCxB)
Typ
5
Max
Unit
26
V
VDD_DIG Digital supply voltage
2.7
3.3
3.6
V
VDD_PLL PLL supply voltage
2.7
3.3
3.6
V
+85
°C
Typ
Max
Unit
Tamb
3.4
Parameter
Ambient temperature
-20
Electrical specifications for the digital section
Table 5. Electrical specifications - digital section
Symbol
Parameter
Conditions
Min
Iil
Low-level input current without
pull-up/down device
Vi = 0 V
1
5
µA
Iih
High-level input current without
pull-up/down device
Vi = VDD_DIG
= 3.6 V
1
5
µA
Vil
Low-level input voltage
Vih
High-level input voltage
Vol
Low-level output voltage
Iol=2 mA
Voh
High-level output voltage
Ioh=2 mA
Ipu
Pull-up/down current
Rpu
Equivalent pull-up/down
resistance
0.2 *
VDD_DIG
0.8 *
V
VDD_DIG
DocID018572 Rev 4
0.4 *
VDD_DIG
0.8 *
V
V
VDD_DIG
25
V
66
50
125
µA
k
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88
Electrical specifications
3.5
STA350BW
Electrical specifications for the power section
The specifications given in this section are valid for the operating conditions: VCC = 24 V,
f = 1 kHz, fsw = 384 kHz, Tamb = 25° C and RL = 8 , unless otherwise specified.
Table 6. Electrical specifications - power section
Symbol
Parameter
Conditions
Min
Typ
Continuous output power, BTL, ternary
mode
THD = 1%
27
THD = 10%
36
Continuous output power SE, binary
mode, RL = 4
THD = 1%
12
THD = 10%
15.5
Power Pchannel/Nchannel MOSFET
(total bridge)
ld = 1.5 A
180
Power Pchannel/Nchannel leakage
VCC = 20 V
Max
Unit
W
Po
RdsON
Idss
W
load(1)
ILDT
Low current dead time (static)
Resistive
IHDT
High current dead time (dynamic)
I load(1) = 1.5 A
tr
tf
Vcc
Ivcc
Rise time
Fall time
250
m
10
A
8
15
ns
15
30
ns
Resistive
load(1)
10
18
ns
Resistive
load(1)
10
18
ns
26
V
Supply voltage operating voltage
5
A
Supply current from Vcc in power-down
PWRDN = 0
1
Supply current from Vcc in operation
PCM input signal
= -60 dBfs,
Switching frequency
= 384 kHz,
No LC filters
52
60
mA
55
70
mA
4.0
A
Ivdd
Supply current FFX processing (reference Internal clock =
only)
49.152 MHz
Ilim
Overcurrent limit
Isc
Short-circuit protection
UVL
Undervoltage protection
OVP
Overvoltage protection
tmin
Output minimum pulse width
DR
Dynamic range
Signal-to-noise ratio, ternary mode
(2)
3.0
3.8
Hi-Z output
4.0
5.0
A
4.3
No load
A-Weighted
V
29
V
100
ns
100
dB
100
dB
90
dB
0.09
%
SNR
Signal-to-noise ratio binary mode
THD+N
16/88
Total harmonic distortion + noise
FFX stereo mode,
Po = 1 W
f = 1 kHz
DocID018572 Rev 4
STA350BW
Electrical specifications
Table 6. Electrical specifications - power section (continued)
Symbol
XTALK
PSRR
Parameter
Conditions
Min
Typ
Max
Unit
Crosstalk
FFX stereo mode,
OUT1B
FFX2A -> OUT2A
FFX2B -> OUT2B
FFX3A -> OUT3A
FFX3B -> OUT3B
FFX4A -> OUT4A
FFX4B -> OUT4B
FFX1A/1B configured as ternary
FFX2A/2B configured as ternary
FFX3A/3B configured as lineout ternary
FFX4A/4B configured as lineout ternary
On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On
channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this
configuration, neither volume control nor EQ has any effect on channels 3 and 4.
In this configuration the PWM slot phase is the following as shown in Figure 26.
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STA350BW
Register description
Figure 26. 2.0 channels (OCFG = 00) PWM slots
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
AM045190v1
2.1 channels, two half-bridges + one full-bridge (OCFG = 01)
FFX1A -> OUT1A
FFX2A -> OUT1B
FFX3A -> OUT2A
FFX3B -> OUT2B
FFX1A -> OUT3A
FFX1B -> OUT3B
FFX2A -> OUT4A
FFX2B -> OUT4B
FFX1A/1B configured as binary
FFX2A/2B configured as binary
FFX3A/3B configured as binary
FFX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3/OUT4
channels the channel 1 and channel 2 PWM are replicated.
In this configuration the PWM slot phase is the following as shown in Figure 27.
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88
Register description
STA350BW
Figure 27. 2.1 channels (OCFG = 01) PWM slots
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
AM045191v1
2.1 channels, two full-bridge + one external full-bridge (OCFG = 10)
FFX1A -> OUT1A
FFX1B -> OUT1B
FFX2A -> OUT2A
FFX2B -> OUT2B
FFX3A -> OUT3A
FFX3B -> OUT3B
EAPD -> OUT4A
TWARN -> OUT4B
FFX1A/1B configured as ternary
FFX2A/2B configured as ternary
FFX3A/3B configured as ternary
FFX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the
external bridge control signals are muxed.
In this configuration the PWM slot phase is the following as shown in Figure 28.
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DocID018572 Rev 4
STA350BW
Register description
Figure 28. 2.1 channels (OCFG = 10) PWM slots
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
AM045192v1
DocID018572 Rev 4
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88
Register description
8.6.2
STA350BW
Invalid input detect mute enable
Table 45. Invalid input detect mute enable
Bit
R/W
RST
Name
2
R/W
1
IDE
Description
Setting of 1 enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I2S data and automatically
mutes if the signals are perceived as invalid.
8.6.3
Binary output mode clock loss detection
Table 46. Binary output mode clock loss detection
Bit
R/W
RST
Name
3
R/W
1
BCLE
Description
Binary output mode clock loss detection enable
The BCLE bit detects loss of input MCLK in binary mode and will output 50% duty cycle.
8.6.4
LRCK double trigger protection
Table 47. LRCK double trigger protection
Bit
R/W
RST
Name
4
R/W
1
LDTE
Description
LRCLK double trigger protection enable
The LDTE bit actively prevents double triggering of the LRCLK.
8.6.5
Auto EAPD on clock loss
Table 48. Auto EAPD on clock loss
Bit
R/W
RST
Name
5
R/W
0
ECLE
Description
Auto EAPD on clock loss
When active, the ECLE bit issues a power device power-down signal (EAPD) on clock loss
detection.
8.6.6
IC power-down
Table 49. IC power-down
Bit
R/W
RST
Name
7
R/W
1
PWDN
Description
0: IC power-down low-power condition
1: IC normal operation
The PWDN register is used to place the IC in a low-power state. When PWDN is written
as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
52/88
DocID018572 Rev 4
STA350BW
Register description
to power down the power-stage, then the master clock to all internal hardware except the
I2C block is gated. This places the IC in a very low power consumption state.
8.6.7
External amplifier power-down
Table 50. External amplifier power-down
Bit
R/W
RST
Name
7
R/W
0
EAPD
Description
0: External power stage power down active
1: Normal operation
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled). This
register also controls the FFX4B/EAPD output pin when OCFG = 10.
8.7
Volume control registers (addr 0x06 - 0x0A)
8.7.1
Mute/line output configuration register
D7
D6
D5
D4
D3
D2
D1
D0
LOC1
LOC0
Reserved
Reserved
C3M
C2M
C1M
MMUTE
0
0
0
0
0
0
0
0
Table 51. Line output configuration
LOC[1:0]
Line output configuration
00
Line output fixed - no volume, no EQ
01
Line output variable - CH3 volume effects line output, no EQ
10
Line output variable with EQ - CH3 volume effects line output
Line output is only active when OCFG = 00. In this case LOC determines the line output
configuration. The source of the line output is always the channel 1 and 2 inputs.
8.7.2
8.7.3
Master volume register
D7
D6
D5
D4
D3
D2
D1
D0
MV7
MV6
MV5
MV4
MV3
MV2
MV1
MV0
1
1
1
1
1
1
1
1
Channel 1 volume
D7
D6
D5
D4
D3
D2
D1
D0
C1V7
C1V6
C1V5
C1V4
C1V3
C1V2
C1V1
C1V0
0
1
1
0
0
0
0
0
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88
Register description
8.7.4
8.7.5
STA350BW
Channel 2 volume
D7
D6
D5
D4
D3
D2
D1
D0
C2V7
C2V6
C2V5
C2V4
C2V3
C2V2
C2V1
C2V0
0
1
1
0
0
0
0
0
Channel 3 / line output volume
D7
D6
D5
D4
D3
D2
D1
D0
C3V7
C3V6
C3V5
C3V4
C3V3
C3V2
C3V1
C3V0
0
1
1
0
0
0
0
0
The volume structure of the STA350BW consists of individual volume registers for each
channel and a master volume register that provides an offset to each channels volume
setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB
to -80 dB.
As an example if C3V = 0x00 or +48 dB and MV = 0x18 or -12 dB, then the total gain for
channel 3 = +36 dB.
The master mute, when set to 1, mutes all channels at once, whereas the individual channel
mute (CxM) mutes only that channel. Both the master mute and the channel mutes provide
a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum
volume setting at the internal processing rate (approximately 96 kHz).
A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) to
any channel volume register or the master volume register. When volume offsets are
provided via the master volume register, any channel whose total volume is less than -80 dB
is muted.
All changes in volume take place at zero-crossings when ZCE = 1 (Configuration register E
(addr 0x04)) on a per channel basis as this creates the smoothest possible volume
transitions. When ZCE = 0, volume updates occur immediately.
Table 52. Master volume offset as a function of MV[7:0]
54/88
MV[7:0]
Volume offset from channel value
00000000 (0x00)
0 dB
00000001 (0x01)
-0.5 dB
00000010 (0x02)
-1 dB
…
…
01001100 (0x4C)
-38 dB
…
…
11111110 (0xFE)
-127.5 dB
11111111 (0xFF)
Hard master mute
DocID018572 Rev 4
STA350BW
Register description
Table 53. Channel volume as a function of CxV[7:0]
CxV[7:0]
Volume
00000000 (0x00)
+48 dB
00000001 (0x01)
+47.5 dB
00000010 (0x02)
+47 dB
…
…
01011111 (0x5F)
+0.5 dB
01100000 (0x60)
0 dB
01100001 (0x61)
-0.5 dB
…
…
11010111 (0xD7)
-59.5 dB
11011000 (0xD8)
-60 dB
11011001 (0xD9)
-61 dB
11011010 (0xDA)
-62 dB
…
…
11101100 (0xEC)
-80 dB
11101101 (0xED)
Hard channel mute
…
…
11111111 (0xFF)
Hard channel mute
8.8
Audio preset registers (addr 0x0B and 0x0C)
8.8.1
Audio preset register 1 (addr 0x0B)
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Reserved
AMGC[1]
AMGC[0]
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured
to properly fit application specific configurations. AMGC[3:2] is defined in register EQ
coefficients and DRC configuration register (addr 0x31) on page 73.
The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2].
When this value is 00, then bits AMGC[1:0] are defined below in Table 54.
Table 54. Audio preset gain compression/limiters selection for AMGC[3:2] = 00
AMGC[1:0]
Mode
00
User-programmable GC
01
AC no clipping 2.1
10
AC limited clipping (10%) 2.1
11
DRC nighttime listening mode 2.1
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88
Register description
8.8.2
8.8.3
STA350BW
Audio preset register 2 (addr 0x0C)
D7
D6
D5
D4
D3
D2
D1
D0
XO3
XO2
XO1
XO0
AMAM2
AMAM1
AMAM0
AMAME
0
0
0
0
0
0
0
0
AM interference frequency switching
Table 55. AM interference frequency switching bits
Bit
R/W
RST
Name
Description
0
R/W
0
AMAME
Audio preset AM enable
0: switching frequency determined by PWMS setting
1: switching frequency determined by AMAM settings
Table 56. Audio preset AM switching frequency selection
8.8.4
AMAM[2:0]
48 kHz/96 kHz input fs
44.1 kHz/88.2 kHz input fs
000
0.535 MHz - 0.720 MHz
0.535 MHz - 0.670 MHz
001
0.721 MHz - 0.900 MHz
0.671 MHz - 0.800 MHz
010
0.901 MHz - 1.100 MHz
0.801 MHz - 1.000 MHz
011
1.101 MHz - 1.300 MHz
1.001 MHz - 1.180 MHz
100
1.301 MHz - 1.480 MHz
1.181 MHz - 1.340 MHz
101
1.481 MHz - 1.600 MHz
1.341 MHz - 1.500 MHz
110
1.601 MHz - 1.700 MHz
1.501 MHz - 1.700 MHz
Bass management crossover
Table 57. Bass management crossover
Bit
R/W
RST
Name
4
R/W
0
XO0
5
R/W
0
XO1
6
R/W
0
XO2
7
R/W
0
XO3
Description
Selects the bass-management crossover frequency.
A 1st-order hign-pass filter (channels 1 and 2) or a
2nd-order low-pass filter (channel 3) at the selected
frequency is performed.
Table 58. Bass management crossover frequency
XO[3:0]
56/88
Crossover frequency
0000
User-defined
0001
80 Hz
0010
100 Hz
0011
120 Hz
DocID018572 Rev 4
STA350BW
Register description
Table 58. Bass management crossover frequency (continued)
XO[3:0]
8.9
8.9.1
Crossover frequency
0100
140 Hz
0101
160 Hz
0110
180 Hz
0111
200 Hz
1000
220 Hz
1001
240 Hz
1010
260 Hz
1011
280 Hz
1100
300 Hz
1101
320 Hz
1110
340 Hz
1111
360 Hz
Channel configuration registers (addr 0x0E - 0x10)
D7
D6
D5
D4
D3
D2
D1
D0
C1OM1
C1OM0
C1LS1
C1LS0
C1BO
C1VPB
C1EQBP
C1TCB
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
C2OM1
C2OM0
C2LS1
C2LS0
C2BO
C2VPB
C2EQBP
C2TCB
0
1
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
C3OM1
C3OM0
C3LS1
C3LS0
C3BO
C3VPB
Reserved
Reserved
1
0
0
0
0
0
0
0
Tone control bypass
Tone control (bass/treble) can be bypassed on a per-channel basis for channels 1 and 2.
Table 59. Tone control bypass
CxTCB
8.9.2
Mode
0
Perform tone control on channel x - normal operation
1
Bypass tone control on channel x
EQ bypass
EQ control can be bypassed on a per-channel basis for channels 1 and 2. If EQ control is
bypassed on a given channel, the prescale and all filters (high-pass, biquads, de-emphasis,
bass, treble in any combination) are bypassed for that channel.
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88
Register description
STA350BW
Table 60. EQ bypass
CxEQBP
8.9.3
Mode
0
Perform EQ on channel x - normal operation
1
Bypass EQ on channel x
Volume bypass
Each channel contains an individual channel volume bypass. If a particular channel has
volume bypassed via the CxVBP = 1 register then only the channel volume setting for that
particular channel affects the volume setting, the master volume setting will not affect that
channel.
8.9.4
Binary output enable registers
Each individual channel output can be set to output a binary PWM stream. In this mode
output A of a channel is considered the positive output and output B is the negative inverse.
Table 61. Binary output enable registers
CxBO
8.9.5
Mode
0
FFX 3-state output - normal operation
1
Binary output
Limiter select
Limiter selection can be made on a per-channel basis according to the channel limiter select
bits.
.
Table 62. Channel limiter mapping as a function of CxLS bits
CxLS[1:0]
8.9.6
Channel limiter mapping
00
Channel has limiting disabled
01
Channel is mapped to limiter #1
10
Channel is mapped to limiter #2
Output mapping
Output mapping can be performed on a per channel basis according to the CxOM channel
output mapping bits. Each input into the output configuration engine can receive data from
any of the three processing channel outputs.
.
Table 63. Channel output mapping as a function of CxOM bits
CxOM[1:0]
58/88
Channel x output source from
00
Channel1
01
Channel 2
10
Channel 3
DocID018572 Rev 4
STA350BW
8.10
8.10.1
Register description
Tone control register (addr 0x11)
D7
D6
D5
D4
D3
D2
D1
D0
TTC3
TTC2
TTC1
TTC0
BTC3
BTC2
BTC1
BTC0
0
1
1
1
0
1
1
1
Tone control
Table 64. Tone control boost/cut as a function of BTC and TTC bits
BTC[3:0]/TTC[3:0]
Boost/Cut
0000
-12 dB
0001
-12 dB
…
…
0111
-4 dB
0110
-2 dB
0111
0 dB
1000
+2 dB
1001
+4 dB
…
…
1101
+12 dB
1110
+12 dB
1111
+12 dB
8.11
Dynamic control registers (addr 0x12 - 0x15)
8.11.1
Limiter 1 attack/release rate
8.11.2
8.11.3
D7
D6
D5
D4
D3
D2
D1
D0
L1A3
L1A2
L1A1
L1A0
L1R3
L1R2
L1R1
L1R0
0
1
1
0
1
0
1
0
Limiter 1 attack/release threshold
D7
D6
D5
D4
D3
D2
D1
D0
L1AT3
L1AT2
L1AT1
L1AT0
L1RT3
L1RT2
L1RT1
L1RT0
0
1
1
0
1
0
0
1
Limiter 2 attack/release rate
D7
D6
D5
D4
D3
D2
D1
D0
L2A3
L2A2
L2A1
L2A0
L2R3
L2R2
L2R1
L2R0
0
1
1
0
1
0
1
0
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88
Register description
8.11.4
STA350BW
Limiter 2 attack/release threshold
D7
D6
D5
D4
D3
D2
D1
D0
L2AT3
L2AT2
L2AT1
L2AT0
L2RT3
L2RT2
L2RT1
L2RT0
0
1
1
0
1
0
0
1
The STA350BW includes two independent limiter blocks. The purpose of the limiters is to
automatically reduce the dynamic range of a recording to prevent the outputs from clipping
in anti-clipping mode or to actively reduce the dynamic range for a better listening
environment such as a night-time listening mode which is often needed for DVDs. The two
modes are selected via the DRC bit in Configuration register E (addr 0x04) on page 43.
Each channel can be mapped to either limiter or not mapped, meaning that the channel will
clip when 0 dBfs is exceeded. Each limiter looks at the present value of each channel that is
mapped to it, selects the maximum absolute value of all these channels, performs the
limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels
in unison.
The limiter attack thresholds are determined by the LxAT registers if EATHx[7] bits are set
to 0 else the thresholds are determined by EATHx[6:0] . It is recommended in anti-clipping
mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of an
FFX amplifier. Since gain can be added digitally within the STA350BW, it is possible to
exceed 0 dBfs or any other LxAT setting. When this occurs, the limiter, when active,
automatically starts reducing the gain. The rate at which the gain is reduced when the attack
threshold is exceeded is dependent upon the attack rate register setting for that limiter. Gain
reduction occurs on a peak-detect algorithm. Setting the EATHx[7] bits to 1 selects the
anti-clipping mode.
The limiter release thresholds are determined by the LxRT registers if ERTHx[7] bits are set
to 0, else the thresholds are determined by ERTHx[6:0]. Setting the ERTHx[7] bits to 1
automatically selects the anti-clipping mode. The release of the limiter, when the gain is
again increased, is dependent on an RMS-detect algorithm. The output of the volume/limiter
block is passed through an RMS filter. The output of this filter is compared to the release
threshold, determined by the Release Threshold register. When the RMS filter output falls
below the release threshold, the gain is again increased at a rate dependent upon the
Release Rate register. The gain can never be increased past its set value and, therefore,
the release only occurs if the limiter has already reduced the gain. The release threshold
value can be used to set what is effectively a minimum dynamic range, this is helpful as
overlimiting can reduce the dynamic range to virtually zero and cause program material to
sound “lifeless”.
In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode,
the attack threshold is set relative to the maximum volume setting of the channels mapped
to that limiter and the release threshold is set relative to the maximum volume setting plus
the attack threshold.
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STA350BW
Register description
Figure 29. Basic limiter and volume flow diagram
RMS
LIMITER
GAIN / VOLUME
INPUT
+
GAIN
OUTPUT
SATURATION
ATTENUATION
AM045193v1
Table 65. Limiter attack rate as a function of
LxA bits
LxA[3:0]
Attack rate dB/ms
0000
3.1584
Fast
Table 66. Limiter release rate as a function
of LxR bits
LxR[3:0]
Release rate dB/ms
0000
0.5116
0001
0.1370
0001
2.7072
0010
2.2560
0010
0.0744
0011
1.8048
0011
0.0499
0100
1.3536
0100
0.0360
0101
0.9024
0101
0.0299
0110
0.4512
0110
0.0264
0111
0.2256
0111
0.0208
1000
0.1504
1000
0.0198
1001
0.1123
1001
0.0172
1010
0.0902
1010
0.0147
1011
0.0752
1011
0.0137
1100
0.0645
1100
0.0134
1101
0.0564
1101
0.0117
1110
0.0501
1110
0.0110
1111
0.0451
1111
0.0104
Slow
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Fast
Slow
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88
Register description
STA350BW
Anti-clipping mode
Table 67. Limiter attack threshold as a
function of LxAT bits (AC-mode)
Table 68. Limiter release threshold as a
function of LxRT bits (AC-mode)
LxAT[3:0]
AC (dB relative to fs)
LxRT[3:0]
AC (dB relative to fs)
0000
-12
0000
-
0001
-10
0001
-29 dB
0010
-8
0010
-20 dB
0011
-6
0011
-16 dB
0100
-4
0100
-14 dB
0101
-2
0101
-12 dB
0110
0
0110
-10 dB
0111
+2
0111
-8 dB
1000
+3
1000
-7 dB
1001
+4
1001
-6 dB
1010
+5
1010
-5 dB
1011
+6
1011
-4 dB
1100
+7
1100
-3 dB
1101
+8
1101
-2 dB
1110
+9
1110
-1 dB
1111
+10
1111
-0 dB
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STA350BW
Register description
Dynamic range compression mode
Table 69. Limiter attack threshold as a
function of LxAT bits (DRC -mode)
Table 70. Limiter release threshold as a as
a function of LxRT bits (DRC-mode)
LxAT[3:0]
DRC (dB relative to Volume)
LxRT[3:0]
DRC (db relative to Volume +
LxAT)
0000
-31
0000
-
0001
-29
0001
-38 dB
0010
-27
0010
-36 dB
0011
-25
0011
-33 dB
0100
-23
0100
-31 dB
0101
-21
0101
-30 dB
0110
-19
0110
-28 dB
0111
-17
0111
-26 dB
1000
-16
1000
-24 dB
1001
-15
1001
-22 dB
1010
-14
1010
-20 dB
1011
-13
1011
-18 dB
1100
-12
1100
-15 dB
1101
-10
1101
-12 dB
1110
-7
1110
-9 dB
1111
-4
1111
-6 dB
8.11.5
Limiter 1 extended attack threshold (addr 0x32)
D7
D6
D5
D4
D3
D2
D1
D0
EATHEN1
EATH1[6]
EATH1[5]
EATH1[4]
EATH1[3]
EATH1[2]
EATH1[1]
EATH1[0]
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
The extended attack threshold value is determined as follows:
attack threshold = -12 + EATH1 / 4
8.11.6
Limiter 1 extended release threshold (addr 0x33)
D7
D6
D5
D4
D3
D2
D1
D0
ERTHEN1
ERTH1[6]
ERTH1[5]
ERTH1[4]
ERTH1[3]
ERTH1[2]
ERTH1[1]
ERTH1[0]
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
The extended release threshold value is determined as follows:
release threshold = -12 + ERTH1 / 4
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88
Register description
8.11.7
STA350BW
Limiter 2 extended attack threshold (addr 0x34)
D7
D6
D5
D4
D3
D2
D1
D0
EATHEN2
EATH2[6]
EATH2[5]
EATH2[4]
EATH2[3]
EATH2[2]
EATH2[1]
EATH2[0]
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
The extended attack threshold value is determined as follows:
attack threshold = -12 + EATH2 / 4
8.11.8
Limiter 2 extended release threshold (addr 0x35)
D7
D6
D5
D4
D3
D2
D1
D0
ERTHEN2
ERTH2[6]
ERTH2[5]
ERTH2[4]
ERTH2[3]
ERTH2[2]
ERTH2[1]
ERTH2[0]
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
The extended release threshold value is determined as follows:
release threshold = -12 + ERTH2 / 4
Note:
Attack/release threshold step is 0.125 dB in the range -12 dB to 0 dB.
8.12
User-defined coefficient control registers (addr 0x16 - 0x26)
8.12.1
Coefficient address register
D7
8.12.2
8.12.3
8.12.4
64/88
D6
D5
D4
D3
D2
D1
D0
CFA5
CFA4
CFA3
CFA2
CFA1
CFA0
0
0
0
0
0
0
Coefficient b1 data register bits 23:16
D7
D6
D5
D4
D3
D2
D1
D0
C1B23
C1B22
C1B21
C1B20
C1B19
C1B18
C1B17
C1B16
0
0
0
0
0
0
0
0
Coefficient b1 data register bits 15:8
D7
D6
D5
D4
D3
D2
D1
D0
C1B15
C1B14
C1B13
C1B12
C1B11
C1B10
C1B9
C1B8
0
0
0
0
0
0
0
0
Coefficient b1 data register bits 7:0
D7
D6
D5
D4
D3
D2
D1
D0
C1B7
C1B6
C1B5
C1B4
C1B3
C1B2
C1B1
C1B0
0
0
0
0
0
0
0
0
DocID018572 Rev 4
STA350BW
8.12.5
8.12.6
8.12.7
8.12.8
8.12.9
8.12.10
8.12.11
Register description
Coefficient b2 data register bits 23:16
D7
D6
D5
D4
D3
D2
D1
D0
C2B23
C2B22
C2B21
C2B20
C2B19
C2B18
C2B17
C2B16
0
0
0
0
0
0
0
0
Coefficient b2 data register bits 15:8
D7
D6
D5
D4
D3
D2
D1
D0
C2B15
C2B14
C2B13
C2B12
C2B11
C2B10
C2B9
C2B8
0
0
0
0
0
0
0
0
Coefficient b2 data register bits 7:0
D7
D6
D5
D4
D3
D2
D1
D0
C2B7
C2B6
C2B5
C2B4
C2B3
C2B2
C2B1
C2B0
0
0
0
0
0
0
0
0
Coefficient a1 data register bits 23:16
D7
D6
D5
D4
D3
D2
D1
D0
C1B23
C1B22
C1B21
C1B20
C1B19
C1B18
C1B17
C1B16
0
0
0
0
0
0
0
0
Coefficient a1 data register bits 15:8
D7
D6
D5
D4
D3
D2
D1
D0
C3B15
C3B14
C3B13
C3B12
C3B11
C3B10
C3B9
C3B8
0
0
0
0
0
0
0
0
Coefficient a1 data register bits 7:0
D7
D6
D5
D4
D3
D2
D1
D0
C3B7
C3B6
C3B5
C3B4
C3B3
C3B2
C3B1
C3B0
0
0
0
0
0
0
0
0
Coefficient a2 data register bits 23:16
D7
D6
D5
D4
D3
D2
D1
D0
C4B23
C4B22
C4B21
C4B20
C4B19
C4B18
C4B17
C4B16
0
0
0
0
0
0
0
0
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88
Register description
8.12.12
8.12.13
8.12.14
8.12.15
8.12.16
8.12.17
STA350BW
Coefficient a2 data register bits 15:8
D7
D6
D5
D4
D3
D2
D1
D0
C4B15
C4B14
C4B13
C4B12
C4B11
C4B10
C4B9
C4B8
0
0
0
0
0
0
0
0
Coefficient a2 data register bits 7:0
D7
D6
D5
D4
D3
D2
D1
D0
C4B7
C4B6
C4B5
C4B4
C4B3
C4B2
C4B1
C4B0
0
0
0
0
0
0
0
0
Coefficient b0 data register bits 23:16
D7
D6
D5
D4
D3
D2
D1
D0
C5B23
C5B22
C5B21
C5B20
C5B19
C5B18
C5B17
C5B16
0
0
0
0
0
0
0
0
Coefficient b0 data register bits 15:8
D7
D6
D5
D4
D3
D2
D1
D0
C5B15
C5B14
C5B13
C5B12
C5B11
C5B10
C5B9
C5B8
0
0
0
0
0
0
0
0
Coefficient b0 data register bits 7:0
D7
D6
D5
D4
D3
D2
D1
D0
C5B7
C5B6
C5B5
C5B4
C5B3
C5B2
C5B1
C5B0
0
0
0
0
0
0
0
0
Coefficient write/read control register
D7
D6
D3
D2
D1
D0
Reserved
D5
D4
RA
R1
WA
W1
0
0
0
0
0
Coefficients for user-defined EQ, mixing, scaling, and bass management are handled
internally in the STA350BW via RAM. Access to this RAM is available to the user via an I2C
register interface. A collection of I2C registers are dedicated to this function. One contains a
coefficient base address, five sets of three store the values of the 24-bit coefficients to be
written or that were read, and one contains bits used to control the write/read of the
coefficient(s) to/from RAM.
Three different RAM banks are embedded in the STA350BW. The three banks are managed
in paging mode using EQCFG register bits. They can be used to store different EQ settings.
For speaker frequency compensation, a sampling frequency independent EQ must be
implemented. Computing three different coefficients set for 32 kHz, 44.1kHz, 48 kHz and
downloading them into the three RAM banks, it is possible to select the suitable RAM block
depending on the incoming frequency with a simple I2C write operation in register 0x31.
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STA350BW
Register description
For example, in case of different input sources (different sampling rates), the three different
sets of coefficients can be downloaded once at startup, and during normal play it is possible
to switch among the three RAM blocks allowing faster operation, without any additional
download from the microcontroller.
To write the coefficients in a particular RAM bank, this bank must be selected first, writing
bit 0 and bit 1 in register 0x31. Then the write procedure below can be used.
Note that as soon as a RAM bank is selected, the EQ settings are automatically switched to
the coefficients stored in the active RAM block.
Note:
The read write operation on RAM coefficients works only if RLCKI (pin29) is switching and
stable (ref. Table 7, tLRJT timing) and PLL must be locked (ref bit D7 reg 0x2D).
Reading a coefficient from RAM
1.
Select the RAM block with register 0x31 bit 1, bit 0.
2.
Write 6 bits of address to I2C register 0x16.
3.
Write 1 to R1 bit in I2C address 0x26.
4.
Read top 8 bits of coefficient in I2C address 0x17.
5.
Read middle 8 bits of coefficient in I2C address 0x18.
6.
Read bottom 8 bits of coefficient in I2C address 0x19.
Reading a set of coefficients from RAM
1.
Select the RAM block with register 0x31 bit1, bit0.
2.
Write 6 bits of address to I2C register 0x16.
3.
Write 1 to RA bit in I2C address 0x26.
4.
Read top 8 bits of coefficient in I2C address 0x17.
5.
Read middle 8 bits of coefficient in I2C address 0x18.
6.
Read bottom 8 bits of coefficient in I2C address 0x19.
7.
Read top 8 bits of coefficient b2 in I2C address 0x1A.
8.
Read middle 8 bits of coefficient b2 in I2C address 0x1B.
9.
Read bottom 8 bits of coefficient b2 in I2C address 0x1C.
10. Read top 8 bits of coefficient a1 in I2C address 0x1D.
11. Read middle 8 bits of coefficient a1 in I2C address 0x1E.
12. Read bottom 8 bits of coefficient a1 in I2C address 0x1F.
13. Read top 8 bits of coefficient a2 in I2C address 0x20.
14. Read middle 8 bits of coefficient a2 in I2C address 0x21.
15. Read bottom 8 bits of coefficient a2 in I2C address 0x22.
16. Read top 8 bits of coefficient b0 in I2C address 0x23.
17. Read middle 8 bits of coefficient b0 in I2C address 0x24.
18. Read bottom 8 bits of coefficient b0 in I2C address 0x25.
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88
Register description
STA350BW
Writing a single coefficient to RAM
1.
Select the RAM block with register 0x31 bit1, bit0.
2.
Write 6 bits of address to I2C register 0x16.
3.
Write top 8 bits of coefficient in I2C address 0x17.
4.
Write middle 8 bits of coefficient in I2C address 0x18.
5.
Write bottom 8 bits of coefficient in I2C address 0x19.
6.
Write 1 to the W1 bit in I2C address 0x26.
Writing a set of coefficients to RAM
1.
Select the RAM block with register 0x31 bit1, bit0.
2.
Write 6 bits of starting address to I2C register 0x16.
3.
Write top 8 bits of coefficient b1 in I2C address 0x17.
4.
Write middle 8 bits of coefficient b1 in I2C address 0x18.
5.
Write bottom 8 bits of coefficient b1 in I2C address 0x19.
6.
Write top 8 bits of coefficient b2 in I2C address 0x1A.
7.
Write middle 8 bits of coefficient b2 in I2C address 0x1B.
8.
Write bottom 8 bits of coefficient b2 in I2C address 0x1C.
9.
Write top 8 bits of coefficient a1 in I2C address 0x1D.
10. Write middle 8 bits of coefficient a1 in I2C address 0x1E.
11. Write bottom 8 bits of coefficient a1 in I2C address 0x1F.
12. Write top 8 bits of coefficient a2 in I2C address 0x20.
13. Write middle 8 bits of coefficient a2 in I2C address 0x21.
14. Write bottom 8 bits of coefficient a2 in I2C address 0x22.
15. Write top 8 bits of coefficient b0 in I2C address 0x23.
16. Write middle 8 bits of coefficient b0 in I2C address 0x24.
17. Write bottom 8 bits of coefficient b0 in I2C address 0x25.
18. Write 1 to the WA bit in I2C address 0x26.
The mechanism for writing a set of coefficients to RAM provides a method of updating the
five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible
unpleasant acoustic side-effects. When using this technique, the 6-bit address specifies the
address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the
STA350BW generates the RAM addresses as offsets from this base value to write the
complete set of coefficient data.
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STA350BW
8.12.18
Register description
User-defined EQ
The STA350BW can be programmed for four EQ filters (biquads) per each of the two input
channels. The biquads use the following equation:
Y[n] = 2 * (b0 / 2) * X[n] + 2 * (b1 / 2) * X[n-1] + b2 * X[n-2] - 2 * (a1 / 2) * Y[n-1] - a2 * Y[n-2]
= b0 * X[n] + b1 * X[n-1] + b2 * X[n-2] - a1 * Y[n-1] - a2 * Y[n-2]
where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed
fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF
(0.9999998808).
Coefficients stored in the user-defined coefficient RAM are referenced in the following
manner:
CxHy0 = b1 / 2
CxHy1 = b2
CxHy2 = -a1 / 2
CxHy3 = -a2
CxHy4 = b0 / 2
where x represents the channel and the y the biquad number. For example, C2H41 is the b2
coefficient in the fourth biquad for channel 2.
Additionally, the STA350BW can be programmed for a high-pass filter (processing
channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bassmanagement crossover when the XO setting is 000 (user-defined). Both of these filters
when defined by the user (rather than using the preset crossover filters) are second order
filters that use the biquad equation given above. They are loaded into the C12H0-4 and
C3Hy0-4 areas of RAM noted in Table 71.
By default, all user-defined filters are pass-through where all coefficients are set to 0, except
the b0/2 coefficient which is set to 0x400000 (representing 0.5).
8.12.19
Pre-scale
The STA350BW provides a multiplication for each input channel for the purpose of scaling
the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed
fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor
for this multiplication is loaded into RAM using the same I2C registers as the biquad
coefficients and the bass-management. All channels can use the channel-1 pre-scale factor
by setting the Biquad link bit. By default, all pre-scale factors are set to 0x7FFFFF.
8.12.20
Post-scale
The STA350BW provides one additional multiplication after the last interpolation stage and
the distortion compensation on each channel. This post-scaling is accomplished by using a
24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The
scale factor for this multiplication is loaded into RAM using the same I2C registers as the
biquad coefficients and the bass-management. This post-scale factor can be used in
conjunction with an ADC equipped microcontroller to perform power-supply error correction.
All channels can use the channel-1 post-scale factor by setting the post-scale link bit. By
DocID018572 Rev 4
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88
Register description
STA350BW
default, all post-scale factors are set to 0x7FFFFF. When line output is being used,
channel-3 post-scale will affect both channels 3 and 4.
8.12.21
Overcurrent post-scale
The STA350BW provides a simple mechanism for reacting to overcurrent detection in the
power block. When the ocwarn input is asserted, the overcurrent post-scale value is used in
place of the normal post-scale value to provide output attenuation on all channels. The
default setting provides 3 dB of output attenuation when ocwarn is asserted.
The amount of attenuation to be applied in this situation can be adjusted by modifying the
Overcurrent Post-scale value. As with the normal post-scale, this scaling value is a 24-bit
signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default,
the overcurrent post-scale factor is set to 0x5A9DF7. Once the overcurrent attenuation is
applied, it remains until the device is reset.
Table 71. RAM block for biquads, mixing, scaling and bass management
Index (decimal)
Index (hex)
Coefficient
Default
0
0x00
C1H10(b1/2)
0x000000
1
0x01
C1H11(b2)
0x000000
2
0x02
C1H12(a1/2)
0x000000
3
0x03
C1H13(a2)
0x000000
4
0x04
C1H14(b0/2)
0x400000
5
0x05
Channel 1 - Biquad 2
C1H20
0x000000
…
…
…
…
…
19
0x13
Channel 1 - Biquad 4
C1H44
0x400000
20
0x14
C2H10
0x000000
C2H11
0x000000
Channel 1 - Biquad 1
Channel 2 - Biquad 1
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21
0x15
…
…
…
…
…
39
0x27
Channel 2 - Biquad 4
C2H44
0x400000
40
0x28
C12H0(b1/2)
0x000000
C12H1(b2)
0x000000
C12H2(a1/2)
0x000000
C12H3(a2)
0x000000
C12H4(b0/2)
0x400000
C3H0(b1/2)
0x000000
C3H1(b2)
0x000000
C3H2(a1/2)
0x000000
C3H3(a2)
0x000000
C3H4(b0/2)
0x400000
41
0x29
42
0x2A
43
0x2B
44
0x2C
45
0x2D
Channel 1/2 - Biquad 5
for XO = 000
Hi-pass 2nd Order filter
for XO000
Channel 3 - Biquad
for XO = 000
Low-pass 2nd Order filter
for XO000
46
0x2E
47
0x2F
48
0x30
49
0x31
50
0x32
Channel 1 - Pre-Scale
C1PreS
0x7FFFFF
51
0x33
Channel 2 - Pre-Scale
C2PreS
0x7FFFFF
DocID018572 Rev 4
STA350BW
Register description
Table 71. RAM block for biquads, mixing, scaling and bass management (continued)
Index (decimal)
Index (hex)
Coefficient
Default
52
0x34
Channel 1 - Post-Scale
C1PstS
0x7FFFFF
53
0x35
Channel 2 - Post-Scale
C2PstS
0x7FFFFF
54
0x36
Channel 3 - Post-Scale
C3PstS
0x7FFFFF
55
0x37
TWARN/OC - Limit
TWOCL
0x5A9DF7
56
0x38
Channel 1 - Mix 1
C1MX1
0x7FFFFF
57
0x39
Channel 1 - Mix 2
C1MX2
0x000000
58
0x3A
Channel 2 - Mix 1
C2MX1
0x000000
59
0x3B
Channel 2 - Mix 2
C2MX2
0x7FFFFF
60
0x3C
Channel 3 - Mix 1
C3MX1
0x400000
61
0x3D
Channel 3 - Mix 2
C3MX2
0x400000
62
0x3E
UNUSED
63
0x3F
UNUSED
8.13
Variable max power correction registers (addr 0x27 - 0x28)
D7
D6
D5
D4
D3
D2
D1
D0
MPCC15
MPCC14
MPCC13
MPCC12
MPCC11
MPCC10
MPCC9
MPCC8
0
0
0
1
1
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
MPCC7
MPCC6
MPCC5
MPCC4
MPCC3
MPCC2
MPCC1
MPCC0
1
1
0
0
0
0
0
0
The MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This
coefficient is used in place of the default coefficient when MPCV = 1.
8.14
Variable distortion compensation registers (addr 0x29 0x2A)
D7
D6
D5
D4
D3
D2
D1
D0
DCC15
DCC14
DCC13
DCC12
DCC11
DCC10
DCC9
DCC8
1
1
1
1
0
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
DCC7
DCC6
DCC5
DCC4
DCC3
DCC2
DCC1
DCC0
0
0
1
1
0
0
1
1
The DCC bits determine the 16 MSBs of the distortion compensation coefficient. This
coefficient is used in place of the default coefficient when DCCV = 1.
DocID018572 Rev 4
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88
Register description
8.15
STA350BW
Fault detect recovery constant registers (addr 0x2B - 0x2C)
D7
D6
D5
D4
D3
D2
D1
D0
FDRC15
FDRC14
FDRC13
FDRC12
FDRC11
FDRC10
FDRC9
FDRC8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
FDRC7
FDRC6
FDRC5
FDRC4
FDRC3
FDRC2
FDRC1
FDRC0
0
0
0
0
1
1
0
0
The FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted,
the TRISTATE output is immediately asserted low and held low for the time period specified
by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The
default value of 0x000C gives approximately 0.1 ms.
8.16
Device status register (addr 0x2D)
D7
D6
D5
D4
D3
D2
D1
D0
PLLUL
FAULT
UVFAULT
OVFAULT
OCFAULT
OCWARN
TFAULT
TWARN
This read-only register provides fault and thermal-warning status information from the power
control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault
or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.
Table 72. Status register bits
72/88
Bit
R/W
RST
Name
Description
7
R
-
PLLUL
6
R
-
FAULT
5
R
-
UVFAULT
0: VCCxX internally detected
< undervoltage threshold
4
R
-
OVFAULT
0: VCCxX internally detected
> overvoltage threshold
3
R
-
OCFAULT
0: overcurrent fault detected
2
R
-
OCWARN
0: overcurrent warning
1
R
-
TFAULT
0: thermal fault, junction temperature over limit
detection
0
R
-
TWARN
0: thermal warning, junction temperature is close to
the fault condition
0: PLL locked
1: PLL not locked
0: fault detected on power bridge
1: normal operation
DocID018572 Rev 4
STA350BW
8.17
Register description
EQ coefficients and DRC configuration register (addr 0x31)
D7
D6
D5
D4
D3
D2
D1
D0
XOB
Reserved
Reserved
AMGC[3]
AMGC[2]
Reserved
SEL[1]
SEL[0]
0
0
0
0
0
0
0
0
Table 73. EQ RAM select
SEL[1:0]
EQ RAM bank selected
00/11
Bank 0 activated
01
Bank 1 activated
10
Bank 2 activated
Bits AMGC[3:2] change the behavior of the bits AMGC[1:0] as given in Table 74 below.
Table 74. Anti-clipping and DRC preset
AMGC[3:2]
Anti clipping and DRC preset selected
00
DRC/Anti-clipping behavior described in Table 54 on page 55 (default).
01
DRC/Anti-clipping behavior is described Table 75 on page 73
10/11
Reserved, do not use
When AMGC[3:2] = 01 then the bits 1:0 are defined as given here in Table 75.
Table 75. Anti-clipping selection for AMGC[3:2] = 01
AMGC[1:0]
Mode
00
AC0, stereo anticlipping 0 dB limiter
01
AC1, stereo anticlipping +1.25 dB limiter
10
AC2, stereo anticlipping +2 dB limiter
11
Reserved do not use
The AC0, AC1, AC2 settings are designed for the loudspeaker protection function, limiting
at the minimum any audio artifacts introduced by typical anti-clipping/DRC algorithms. More
detailed information is available in the applications notes “Configurable output power rate
using STA335BW” and “STA335BWS vs STA335BW”.
The XOB bit can be used to bypass the crossover filters. Logic 1 means that the function is
not active. In this case, the high-pass crossover filter works as a pass-through on the data
path (b0 = 1, all the other coefficients at logic 0) while the low-pass filter is configured to
have zero signal on channel-3 data processing (all the coefficients are at logic 0).
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88
Register description
8.18
STA350BW
Extended configuration register (addr 0x36)
D7
D6
D5
D4
D3
D2
D1
D0
Mdrc[1]
Mdrc[0]
PS48DB
XAR1
XAR2
BQ5
BQ6
BQ7
0
0
0
0
0
0
0
0
The extended configuration register provides access to B2DRC and biquad 5, 6 and 7.
8.18.1
Dual-band DRC
The STA350BW device provide a dual-band DRC (B2DRC) on the left and right channels
data path, as depicted in Figure 30. Dual-band DRC is activated by setting MDRC[1:0] = 1x.
Figure 30. B2DRC scheme
CH1
Volume
L
Limiter
And
Vol
DRC1
+
Pass
B2DRC XO
Filter
Hi-pass
filter
CH3
-
Volume
CH2
Limiter
And
Vol
DRC2
DRC1
Volume
+
R
Pass XO
2DRC
BFilter
Hi-pass
filter
CH3
Volume
Limiter
And
Vol
DRC2
AM045194v1
The low frequency information (LFE) is extracted from left and right channels, removing the
high frequencies using a programmable Biquad filter, and then computing the difference
with the original signal. Limiter 1 (DRC1) is then used to control Left/Right high-frequency
amplitude of the components, while limiter 2 (DRC2) is used to control the low-frequency
components (see Chapter 8.11).
The cutoff frequency of the high-pass filters can be user-defined, XO[3:0] = 0, or selected
from the pre-defined values.
DRC1 and DRC2 are then used to independently limit L/R high frequencies and LFE
channels amplitude (see Chapter 8.11) as well as their volume control. To be noted that, in
this configuration, the dedicated channel 3 volume control can actually act as a bass boost
enhancer as well (0.5 dB/step resolution).
The processed LFE channel is then recombined with the L and R channels in order to
reconstruct the 2.0 output signal.
Sub-band decomposition
The sub-band decomposition for B2DRC can be configured specifying the cutoff frequency.
The cutoff frequency can be programmed in two ways, using XO bits in register 0x0C, or
using the “user programmable” mode (coefficients stored in RAM addresses 0x28 to 0x31).
74/88
DocID018572 Rev 4
STA350BW
Register description
For the user programmable mode, use the formulas below to compute the high-pass filters:
b0 = (1 + alpha) / 2
a0 = 1
b1 = -(1 + alpha) / 2
a1 = -alpha
b2 = 0
a2 = 0
where alpha = (1-sin(0))/cos(0), and 0 is the cutoff frequency.
A first-order filter is suggested to guarantee that for every 0 the corresponding low-pass
filter obtained as the difference (as shown in Figure 30) will have a symmetric (relative to HP
filter) frequency response, and the corresponding recombination after the DRC has low
ripple. Second-order filters can be used as well, but in this case the filter shape must be
carefully chosen to provide good low-pass response and minimum ripple recombination. For
second-order filters it is not possible to give a closed formula to get the best coefficients, but
empirical adjustment should be done.
DRC settings
The DRC blocks used by B2DRC are the same as those described in Chapter 8.11. B2DRC
configure automatically the DRC blocks in anticlipping mode. Attack and release thresholds
can be selected using registers 0x32, 0x33, 0x34, 0x35, while attack and release rates are
configured by registers 0x12 and 0x14.
Band downmixing
The low-frequency band is down-mixed to the left and right channels at the B2DRC output.
Channel volume can be used to weight the bands recombination to fine-tune the overall
frequency response.
8.18.2
EQ DRC mode
Setting MDRC = 01, it is possible to add a programmable biquad (the XO biquad at RAM
addresses 0x28 to 0x2C is used for this purpose) to the Limiter/compressor measure path
(side chain). Using EQDRC the peak detector input can be shaped in frequency using the
programmable biquad. For example if a +2 dB bass boost is applied (using a low shelf filter
for example), the effect is that the EQDRC output will limit bass frequencies to -2 dB below
the selected attack threshold.
Generally speaking, if the biquad boosts frequency f with an amount of X dB, the level of a
compressed sine wave at the output will be TH - X, where TH is the selected attack
threshold.
Note:
EQDRC works only if the biquad frequency response magnitude is 0 dB for every
frequency.
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88
Register description
STA350BW
Figure 31. EQDRC scheme
EQDRC
ATTENUATION
Channel In
BIQUAD
PEAK
ATTENUATION
DETECTOR
CLACULATOR
Standard DRC
ATTENUATION
Channel In
PEAK
ATTENUATION
DETECTOR
CLACULATOR
AM045195v1
8.18.3
Extended post-scale range
PS48DB
Mode
0
Post-scale value is applied as defined in coefficient RAM
1
Post-scale value is applied with +48 dB offset with respect to the
coefficient RAM value
Post-scale is an attenuation by default. When PS48DB is set to 1, a 48-dB offset is applied
to the coefficient RAM value, so post-scale can act as a gain too.
8.18.4
Extended attack rate
The attack rate shown in Table 65 can be extended to provide up to an 8 dB/ms attack rate
on both limiters.
XAR1
Mode
0
Limiter1 attack rate is configured using Table 65
1
Limiter1 attack rate is 8 dB/ms
XAR2
76/88
Mode
0
Limiter2 attack rate is configured using Table 65
1
Limiter2 attack rate is 8 dB/ms
DocID018572 Rev 4
STA350BW
8.18.5
Register description
Extended BIQUAD selector
De-emphasis filter as well as bass and treble controls can be configured as user-defined
filters when the equalization coefficients link is activated (BQL = 1) and the corresponding
BQx bit is set to 1.
BQ5
Mode
0
Pre-set de-emphasis filter selected
1
User-defined biquad 5 coefficients are selected
BQ6
Mode
0
Pre-set bass filter selected as per Table 64
1
User-defined biquad 6 coefficients are selected
BQ7
Mode
0
Pre-set treble filter selected as per Table 64
1
User-defined biquad 7 coefficients are selected
When filters from 5th to 7th are configured as user-programmable, the corresponding
coefficients are stored respectively in addresses 0x20-0x24 (BQ5), 0x25-0x29 (BQ6), 0x2A0x2E (BQ7) as in Table 71.
Note:
BQx bits are ignored if BQL = 0 or if DEMP = 1 (relevant for BQ5) or CxTCB = 1 (relevant for
BQ6 and BQ7).
8.19
EQ soft-volume configuration registers (addr 0x37 - 0x38)
D7
D6
0
0
D7
D6
0
0
D5
D4
D3
D2
D1
D0
SVUPE
SVUP[4]
SVUP[3]
SVUP[2]
SVUP[1]
SVUP[0]
0
0
0
0
0
0
D5
D4
D3
D2
D1
D0
SVDWE
SVDW4]
SVDW[3]
SVDW[2]
SVDW[1]
SVDW[0]
0
0
0
0
0
0
The soft-volume update has a fixed rate by default. Using register 0x37 and 0x38 it is
possible to override the default behavior allowing different volume change rates.
It is also possible to independently define the fade-in (volume is increased) and fade-out
(volume is decreased) rates according to the desired behavior.
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88
Register description
STA350BW
SVUPE
Mode
0
When volume is increased, use the default rate
1
When volume is increased, use the rates defined by SVUP[4:0]
When SVUPE = 1 the fade-in rate is defined by the SVUP[4:0] bits according to the
following formula:
Fade-in rate = 48 / (N + 1) dB/ms
where N is the SVUP[4:0] value.
SVDWE
Mode
0
When volume is decreased, use the default rate
1
When volume is decreased, use the rates defined by SVDW[4:0]
When SVDWE = 1 the fade-out rate is defined by the SVDW[4:0] bits according to the
following formula:
Fade-in rate = 48 / (N + 1) dB/ms
where N is the SVDW[4:0] value.
Note:
For fade-out rates greater than 6 dB/msec it is suggested to disable the CPWMEN bit
(Section 8.24.4 ) and ZCE bit (Section 8.5.7) in order to avoid any audible pop noise.
8.20
DRC RMS filter coefficients (addr 0x39-0x3E)
78/88
D7
D6
D5
D4
D3
D2
D1
D0
R_C0[23]
R_C0[22]
R_C0[21]
R_C0[20]
R_C0[19]
R_C0[18]
R_C0[17]
R_C0[16]
0
0
0
0
0
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
R_C0[15]
R_C0[14]
R_C0[13]
R_C0[12]
R_C0[11]
R_C0[10]
R_C0[9]
R_C0[8]
1
1
1
0
1
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R_C0[7]
R_C0[6]
R_C0[5]
R_C0[4]
R_C0[3]
R_C0[2]
R_C0[1]
R_C0[0]
1
1
1
1
1
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
R_C1[23]
R_C1[22]
R_C1[21]
R_C1[20]
R_C1[19]
R_C1[18]
R_C1[17]
R_C1[16]
0
1
1
1
1
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R_C1[15]
R_C1[14]
R_C1[13]
R_C1[12]
R_C1[11]
R_C1[10]
R_C1[9]
R_C1[8]
1
1
0
0
0
0
0
0
DocID018572 Rev 4
STA350BW
Register description
D7
D6
D5
D4
D3
D2
D1
D0
R_C1[7]
R_C1[6]
R_C1[5]
R_C1[4]
R_C1[3]
R_C1[2]
R_C1[1]
R_C1[0]
0
0
1
0
0
1
1
0
Signal level detection in DRC algorithm is computed using the following formula:
y(t) = c0 * abs(x(t)) + c1 * y(t-1)
where x(t) represents the audio signal applied to the limiter, and y(t) the measured level.
8.21
Extra volume resolution configuration registers (address
0x3F)
D7
D6
D5
D4
D3
D2
D1
D0
VRESEN
VRESTG
C3VR[1]
C3VR[0]
C2VR[1]
C2VR[0]
C1VR[1]
C1VR[0]
0
0
0
0
0
0
0
0
The extra volume resolution allows fine volume tuning by steps of 0.125dB.
The feature is enabled when VRESEN=1 , as depicted in Figure 32. The overall channel
volume in this case will be CxVol+CxVR (in dB). On top of the total volume range from
-80 dB to +48 dB, this extra volume resolution works in a volume range from -80 dB to +42
dB. For volumes greater than +42 dB, this function must not be selected.
Figure 32. Extra resolution volume scheme
Audio Data In
CxVOL
Soft
Volume
0
X
Audio Data Out
1
X
VRESEN
1
0
VRESTG
MVOL or CxVOL’event
CxVR
AM045196v1
If VRESEN = 0 the channel volume will be defined only by the CxVol registers.
Fine-tuning steps can be set according to the following table for channels 1, 2, 3:
DocID018572 Rev 4
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88
Register description
STA350BW
CxVR
Mode
00
0 dB
01
-0.125dB
10
-0.25dB
11
-0.375dB
Two different behaviors can be configured by the VRESTG bit:
8.22
If VRESTG=’0’ the CxVR contribution will be applied immediately after the
corresponding I2C bits are written.
If VRESTG=’1’ the CxVR bits will be effective on channel volume only after the
corresponding CxVol register or master volume register is written (even to the previous
values).
VRESEN
VRESTG
Mode
0
0
Extra Volume Resolution disabled
0
1
Extra Volume Resolution disabled
1
0
Volume fine-tuning enabled and applied immediately.
1
1
Volume fine-tuning enabled and applied when master or
channel volume is updated
Quantization error noise correction (address 0x48)
D7
NSHXEN
0
D6
D5
D4
D3
D2
D1
D0
NSHB7EN NSHB6EN NSHB5EN NSHB4EN NSHB3EN NSHB2EN NSHB1EN
0
0
0
0
0
0
0
A special feature inside the digital processing block is available. In case of poles positioned
at very low frequencies, biquad filters can generate some audible quantization noise or
unwanted DC level. In order to avoid this kind of effect, a quantization noise-shaping
capability can be used. The filter structure including this special feature, relative to each
biquad, is shown in Figure 33.
By default, this capability is not activated to maintain backward compatibility with all the
previous Sound Terminal products. The new feature can be enabled independently for each
biquad using the I2C registers. The D7 bit, when set, is responsible for activating this
function on the crossover filter while the other bits address any specific biquads according to
the previous table. Channels 1 and 2 share the same settings. Bit D7 is effective also for
channel 3 if the relative OCFG is used.
80/88
DocID018572 Rev 4
STA350BW
Register description
Figure 33. Biquad filter structure with quantization error noise-shaping
In(t)
b0
z-1
-
+
Q
Out(t)
z-1
z-1
b1
a1
z-1
z-1
b2
a2
AM045197v1
8.23
Extended coefficient range up to -4...4 (address 0x49, 0x4A)
D7
CXTB4[1]
D6
CXTB4[0]
D5
D4
D3
D2
D1
CXTB3[1]
CXTB3[0]
CX_B2[1]
CXTB2[0]
CXTB1[1]
D0
CXTB1[0]
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
CXTB7[1]
CXTB7[0]
CXTB6[1]
CXTB6[0]
CXTB5[1]
0
0
0
0
0
Reserved
Reserved
0
0
CXTB5[0]
0
Biquads from 1 to 7 have in the STA350BW the possibility to extend the coefficient range
from [-1,1) to [-4..4). This allows the realization of high shelf filters that may require a
coefficients dynamic greater in absolute value than 1.
Three ranges are available, [-1;1) [-2;2) [-4;4). By default the extended range is not
activated to maintain backward compatibility with all the previous Sound Terminal products.
Each biquad has its independent setting according to the following table:
Table 76. Biquad filter settings
CEXT_Bx[1]
CEXT_Bx[0]
0
0
[-1;1)
0
1
[-2;2)
1
0
[-4;4)
1
1
Reserved
DocID018572 Rev 4
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88
Register description
STA350BW
In this case the user can decide, for each filter stage, the right coefficients range. Note that
for a given biquad the same range will be applied to Left and Right (Channel 1 and Channel
2).
The crossover biquad does not have the availability of this feature, maintaining the [-1;1)
range unchanged.
8.24
Miscellaneous registers (address 0x4B, 0x4C)
D7
RPDNEN
D6
NSHHPEN
D5
BRIDGOFF
D4
Reserved
D3
Reserved
D2
CPWMEN
D1
Reserved
D0
Reserved
0
0
0
0
0
1
0
0
D7
D6
D5
D4
D3
D2
D1
D0
PNDLSL[2]
PNDLSL[1]
PNDLSL[0]
0
0
0
Reserved
0
8.24.1
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Rate powerdown enable (RPDNEN) bit (address 0x4B, bit D7)
In the STA350BW, by default, the power-down pin and I2C power-down act on mute
commands to perform the fadeout. This default can be changed so that the fadeout can be
started using the master volume. The RPDNEN bit, when set, activates this feature.
8.24.2
Noise-shaping on DC cut filter enable (NSHHPEN) bit (address 0x4B,
bit D6)
Following the description in Section 8.22, this bit, when set, enables the noise-shaping
technique on the DC cutoff filter. Channels 1 and 2 share the same settings.
8.24.3
Bridge immediate off (BRIDGOFF) bit (address 0x4B, bit D5)
A fadeout procedure is started in the STA350BW once the PWDN function is enabled.
Independently from the fadeout time, after 13 million clock cycles (PLL internal frequency)
the bridge is put in powerdown (tristate mode). There is also the possibility to change this
behavior so that the power bridge will be switched off immediately after the PWDN pin is tied
to ground, without therefore waiting for the 13 million clock cycles. The BRIDGOFF bit,
when set, activates this function. Obviously the immediate power-down will generate a pop
noise at the output. therefore this procedure must be used only in case pop noise is not
relevant in the application. Note that this feature works only for hardware PWDN assertion
and not for a powerdown applied through the I2C interface. Refer to Section 8.24.5 in order
to program a different number of clock cycles.
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8.24.4
Register description
Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2)
This bit, when set, activates a mute output in case the volume will reach a value lower than
-76 dBFS.
8.24.5
Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4,
D3, D2)
As per Section 8.24.3, the assertion of PWDN activates a counter that, by default, after 13
million clock cycles puts the power bridge in tristate mode, independently from the fadeout
time. Using these registers it is possible to program this counter according to the following
table:
PNDLSL[2]
PNDLSL[1]
PNDLSL[2]
Fade out time
0
0
0
Default time (13M clock cycles)
0
0
1
Default time divided by 2
0
1
0
Default time divided by 4
0
1
1
Default time divided by 8
1
0
0
Default time divided by 16
1
0
1
Default time divided by 32
1
1
0
Default time divided by 64
1
1
1
Default time divided by 128
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Package thermal characteristics
9
STA350BW
Package thermal characteristics
Using a four-layer PCB the thermal resistance junction-to-ambient with 2 copper ground
areas of 6 x 4 cm2 and with 24 via holes (see Figure 34) is 17 °C/W in natural air
convection.
The dissipated power within the device depends primarily on the supply voltage, load
impedance and output modulation level.
Thus, the maximum estimated dissipated power for the STA350BW is:
2 x 40 W @ 8 , 25.5 V
Pd max ~ 8 W
2 x 17 W + 1 x 35 W @ 4 , 8 ,25 V
Pd max < 7 W
Figure 34. Double-layer PCB with 2 copper ground areas and 24 via holes
AM045200v1
Figure 35 shows the power derating curve for the PowerSSO-36 slug-down package on
PCBs with copper areas of 5 x 4 cm2 and 6 x 4cm2.
Figure 35. PowerSSO-36 power derating curve
Pd (W)
8
7
Copper Area 6x4 cm
6
and 24 via holes
5
STA350BW
STA350BW
Power-SSO36
4
3
Copper Area 5x4 cm
2
and 20 via holes
1
0
0
20
40
60
80
100
120
140
160
Tamb ( °C)
AM045201v1
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Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 77. PowerSSO-36 EPD dimensions
Dimensions in mm
Dimensions in inches
Symbol
Min
Typ
Max
Min
Typ
Max
A
2.15
-
2.47
0.085
-
0.097
A2
2.15
-
2.40
0.085
-
0.094
a1
0.00
-
0.10
0.00
-
0.004
b
0.18
-
0.36
0.007
-
0.014
c
0.23
-
0.32
0.009
-
0.013
D
10.10
-
10.50
0.398
-
0.413
E
7.40
-
7.60
0.291
-
0.299
e
-
0.5
-
-
0.020
-
e3
-
8.5
-
-
0.335
-
F
-
2.3
-
-
0.091
-
G
-
-
0.10
-
-
0.004
H
10.10
-
10.50
0.398
-
0.413
h
-
-
0.40
-
-
0.016
k
0
-
8 degrees
0
-
8 degrees
L
0.60
-
1.00
0.024
-
0.039
M
-
4.30
-
-
0.169
-
N
-
-
10 degrees
-
-
10 degrees
O
-
1.20
-
-
0.047
-
Q
-
0.80
-
-
0.031
-
S
-
2.90
-
-
0.114
-
T
-
3.65
-
-
0.144
-
U
-
1.00
-
-
0.039
-
X
4.10
-
4.70
0.161
-
0.185
Y
6.50
-
7.10
0.256
-
0.280
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h x 45°
Package mechanical data
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Figure 36. PowerSSO-36 EPD outline drawing
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11
Revision history
Revision history
Table 78. Document revision history
Date
Revision
11-Mar-2011
1
Initial release.
20-Apr-2011
2
Updated Figure 4: Demonstration board, 2.0 channels
Added Figure 5: Mono parallel BTL schematic
13-Apr-2012
3
Updated min. and typ. values for Isc in Table 6: Electrical
specifications - power section
4
Added Section 5 on page 25
Modified Note:: The read write operation on RAM coefficients works
only if RLCKI (pin29) is switching and stable (ref. Table 7, tLRJT
timing) and PLL must be locked (ref bit D7 reg 0x2D).
Updated Company information appearing on last page of document
20-Sep-2013
Changes
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