STA50013TR

STA500 30V 3.5A QUAD POWER HALF BRIDGE ■ ■ MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION MULTIPOWER BCD TECHNOLOGY 200mΩ RdsON COMPLEMENTARY DMOS OUTPUT STAGE ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O ■ CMOS COMPATIBLE LOGIC INPUTS ■ THERMAL PROTECTION ■ THERMAL WARNING OUTPUT ■ OVERVOLTAGE, UNDERVOLTAGE PROTECTION PowerSO36 ORDERING NUMBER: STA500 current capability. DESCRIPTION The device is particulary designed to make the output stage of a stereo All-Digital High Efficiency (DDX™) amplifier capable to deliver 30 + 30W output power on 8Ω load and 60W on 8Ω load in bridge BTL configuration or mono 60W on 4Ω load. The input pins have threshold proportional to Ibias pin voltage. STA500 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half AUDIO APPLICATION CIRCUIT (Dual BTL) +VCC VCC1A IN1A 29 VL 23 CONFIG 24 M3 IN1A +3.3V R57 10K PWRDN PWRDN 25 R59 10K FAULT 27 C58 100nF TH_WAR 26 17 16 M2 PROTECTIONS & LOGIC TRI-STATE M5 TH_WAR 28 IN1B 30 C58 100nF C53 100nF C60 100nF 21 VDD 22 VSS 33 VSS 34 VCCSIGN IN2A IN2A GND-Reg GND-Clean IN2B GND1A 12 VCC1B REGULATORS 13 GND1B 7 VCC2A IN2B GNDSUB 8 9 M15 31 20 19 M16 32 1 C32 1µF GND2A 4 VCC2B OUT2B OUT2B M14 5 8Ω C21 100nF C110 100nF C109 330pF R103 6 C33 1µF 3 R100 6 C99 100nF C23 470nF C101 100nF L113 22µH OUT2A 6 R98 6 L19 22µH OUT2A 2 R63 20 OUT1B OUT1B M4 35 36 C20 100nF C52 330pF C31 1µF 11 C55 1000µF L18 22µH OUT1A 14 M17 VCCSIGN C30 1µF OUT1A 10 IN1B VDD 15 R104 20 R102 6 C107 100nF C108 470nF C106 100nF 8Ω C111 100nF L112 22µH GND2B D00AU1148B Rev. 7 January 2006 1/11 STA500 PIN FUNCTION N° Pin Description 1 GND-SUB 35 ; 36 Vcc Sign 15 Vcc1A Positive Supply 12 Vcc1B Positive Supply 7 Vcc2A Positive Supply 4 Vcc2B Positive Supply Substrate ground Signal Positive supply ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 14 GND1A Negative Supply 13 GND1B Negative Supply 6 GND2A Negative Supply 5 GND2B Negative Supply 16 ; 17 OUT1A Output half bridge 1A 10 ; 11 OUT1B Output half bridge 1B 8;9 OUT2A Output half bridge 2A 2;3 OUT2B Output half bridge 2B 29 IN1A Input of half bridge 1A 30 IN1B Input of half bridge 1B 31 IN2A Input of half bridge 2A 32 IN2B Input of half bridge 2B 21 ; 22 Vdd 5V Regulator referred to ground 33 ; 34 Vss 5V Regulator referred to +Vcc 25 PWRDN 26 TRI-STATE 27 FAULT 24 CONFIG Configuration setting pin 28 TH-WAR Thermal warning advisor (Open Collector Output) 19 GND-clean 23 IBIAS 18 NC 20 GND-Reg 2/11 Stand-by pin (Control input) Hi-Z pin (Control input) Fault pin advisor (Open Collector Output) Logical ground High logical state setting voltage Not connected Ground for Vdd regulator STA500 FUNCTIONAL PIN STATUS PIN NAME Logical value IC -STATUS FAULT 0 Fault detected (Short circuit, or Thermal ..) FAULT (*) 1 Normal Operation TRI-STATE 0 All powers in Hi-Z state TRI-STATE 1 Normal operation PWRDN 0 Low absorpion ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O PWRDN 1 Normal operation THWAR 0 Temperature of the IC =130°C THWAR(*) 1 Normal operation CONFIG 0 Normal Operation CONFIG(**) 1 OUT1A=OUT1B ; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B) (*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. (**:) To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) PIN CONNECTION GND-SUB 1 36 VCCSign OUT2B 2 35 VCCSign OUT2B 3 34 VSS VCC2B 4 33 VSS GND2B 5 32 IN2B GND2A 6 31 IN2A VCC2A 7 30 IN1B OUT2A 8 29 IN1A OUT2A 9 28 TH_WAR OUT1B 10 27 FAULT OUT1B 11 26 TRI-STATE VCC1B 12 25 PWRDN GND1B 13 24 CONFIG GND1A 14 23 IBIAS VCC1A 15 22 VDD OUT1A 16 21 VDD OUT1A 17 20 GND-Reg N.C. 18 19 GND-Clean D00AU1133 3/11 STA500 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCE DC Supply Voltage (Pin 4,7,12,15) 40 V Vmax Maximum Voltage on pins (23 to 32) 5.5 V Operating Temperature Range Top Tstg, Tj Storage and Junction Temperature 0 to 70 °C -40 to 150 °C THERMAL DATA Symbol Parameter Min. Typ. Max. Unit 2.5 °C/W TjSD Thermal shut-down junction temperature 150 Twarn Thermal warning temperature 130 ) s ( t thSD Thermal shut-down hysteresis 25 °C Tj-case Thermal Resistance Junction to Case (thermal pad) c u d ELECTRICAL CHARACTERISTCS (Ibias = 3.3V; Vcc = 28V; Tamb = 25°C unless otherwise specified) Symbol Parameter so Test conditions RdsON Power Pchannel/Nchannel MOSFET RdsON Id=1A; Idss Power Pchannel/Nchannel leakage Idss Vcc=35V gN Power Pchannel RdsON Matching (*) gP Power Nchannel RdsON Matching (*) u d o Pr Dt_s Low current Dead Time (static) Dt_d s b O td OFF tr Id=1A (t s) s b O Typ. Max. Unit 200 270 mΩ 50 µA 95 % 95 % High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8Ω Id = 3.5A; see fig. 3 50 ns Turn-on delay time Resistive load 100 ns Resistive load 100 ns o r P e Turn-off delay time c u d t e l o VCC e t le o s b O - o r P Min. ) s t( ns Rise time tf VIN-H Id=1A b O c u d °C 20 e t e ol td ON )- s ( t c e t e l o r P °C Fall time see test circuit no.1; see fig. 1 10 Resistive load; as fig. 1 25 ns Resistive load; as fig. 1 25 ns VOV V Supply voltage operating voltage 9 High level input voltage Ibias/2 +300mV V VIN-L Low level input voltage IIN-H Hi level Input current Pin voltage=Ibias 1 µA IIN-L Low level input current Pin voltage = 0.3V 1 µA Ibias = 3.3V 35 IPWRDN-H Hi level PWRDN pin input current Ibias/2 -300mV VL Low logical state voltage VL (pin PWRDN, TRISTATE) (note 1) Ibias = 3.3V VH High logical state voltage VH (pin PWRDN, TRISTATE) (note 1) Ibias = 3.3V 4/11 µA 0.8 1.7 V V V STA500 ELECTRICAL CHARACTERISTCS (continued) (Ibias = 3.3V; Vcc = 28V; Tamb = 25°C unless otherwise specified) Symbol Parameter IVCC- Supply current from Vcc in Power Down PWRDN IFAULT IVCC-hiz IVCC Test conditions Output Current pins FAULT -TH-WARN when FAULT CONDITIONS Min. Typ. PWRDN = 0 Max. Unit 3 mA Vpin = 3.3V 1 mA Supply current from Vcc in Tristate Tri-state=0 22 mA Supply current from Vcc in operation (both channel switching) Input pulse width = 50% Duty; Switching Frequency = 384Khz; No LC filters; 80 mA ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O IOUT-SH Overcurrent Protection Threshold (short circuit current limit) (note 2) 3.5 6 8 A VOV Overvoltage protection threshold 30 35 40 V VUV Undervoltage protection threshold 150 ns tpw_min Output minimum pulse width 7 No Load 70 V Notes: 1. The following table explains the VL, VH variation with Ibias Ibias VLmax VHmin Unit 2.7 0.7 1.5 V 3.3 0.8 1.7 V 5 0.85 1.85 V Note 2: If used in single BTL configuration, the device may be not short circuit protected LOGIC TRUTH TABLE (see fig. 2) TRI-STATE INxA INxB Q1 Q2 Q3 Q4 OUTPUT MODE 0 X X OFF OFF OFF OFF Hi-Z 1 0 0 OFF OFF ON ON DUMP 1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used 5/11 STA500 Figure 1. Test Circuit. OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 V67 = vdc = Vcc/2 + - gnd D03AU1458 Figure 2. +VCC Q1 Q2 OUTxA INxA OUTxB Q3 INxB Q4 GND D00AU1134 Figure 3. High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 Rload=8Ω OUTxA INxA Iout=3.5A M57 Q3 DTout(B) L67 22µ C69 470nF L68 22µ C71 470nF C70 470nF DTin(B) OUTxB INxB Iout=3.5A Q4 Duty cycle A and B: Fixed to have DC output current of 3.5A in the direction shown in figure 6/11 M64 M63 D00AU1162 STA500 Figure 4. Typical Quad Half Bridge Configuration +VCC VCC1P IN1A 29 IBIAS 23 CONFIG 24 PWRDN 25 M3 IN1A +3.3V PWRDN R57 10K R59 10K C58 100nF FAULT 27 26 15 L11 22µH 17 16 M2 PROTECTIONS & LOGIC TRI-STATE M5 OUTPL OUTPL 14 PGND1P 12 VCC1N 11 R61 5K C51 1µF R41 20 C41 330pF C71 100nF R51 6 C81 100nF C61 100nF R62 5K C31 820µF C21 2200µF C91 1µF ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O TH_WAR TH_WAR 28 IN1B 30 VDD 21 VDD 22 VSS 33 VSS 34 10 OUTNL IN1B C58 100nF C53 100nF C60 100nF IN2A GND-Reg GND-Clean IN2B M4 REGULATORS 13 7 PGND1N VCC2P R63 5K L12 22µH R42 20 C42 330pF C72 100nF R52 6 C82 100nF IN2B GNDSUB 9 36 M15 31 20 19 M16 OUTPR OUTPR 6 PGND2P 4 VCC2N 3 2 32 1 L13 22µH 8 35 C52 1µF 5 C43 330pF PGND2N D03AU1474 C73 100nF R53 6 C83 100nF C62 100nF OUTNR OUTNR M14 R43 20 C44 330pF R66 5K R67 5K L14 22µH R44 20 R64 5K R65 5K M17 VCCSIGN VCCSIGN IN2A OUTNL C74 100nF R54 6 C84 100nF R68 5K C32 820µF C92 1µF C33 820µF C93 1µF C34 820µF C94 1µF Note: The diagran showed below, have been obtained using the demonstration board described in the application Note AN1456 (STA304 + STA500 Digital Audioprocessor evolution board evaluating manual - Jan 2002), refer to the schematic shown in fig. 1). For the Quad Half Bridge Configuration (fig. 4), refers to the application note AN1661 (STA308 Half Bridge Board - March 2003) 7/11 STA500 Figure 5. Distortion vs Output Power (STA304A+STA500) Figure 7. Output Power vs Supply Voltage (STA304A+STA500) 50 10 Pout (W) 45 5 Vcc=30V Rl=80hm f=1KHz 2 40 STA500 4 ohm load filter 22uH+ 0.47uF diff+ 0.1uF common mode 35 1 30 0.5 THD = 10% 25 % 20 0.2 THD = 1% 15 0.1 10 0.05 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 5 Eq. 0.02 0 +12 0.01 700m 1 2 3 4 5 6 7 8 9 10 20 30 +12.5 +13 +13.5 +14 +14.5 +15 +15.5 +16 +16.5 +17 +17.5 +18 Vdc 40 50 Vsupply (V) W Figure 6. Tolal Power Dissipation & Efficiency vs Output Power Figure 8. Output Power vs Supply Voltage (STA304A+STA500) 50 90 7 80 6 Pout (W) 45 Pdiss 60 4 STA304A+STA500 1channel Vcc=25V Rl=8ohm F=1KHz 50 40 Efficiency 3 2 30 1 20 0 0 5 10 15 Pout (W) 8/11 20 25 30 Rload = 8 ohm f = 1KHz 40 5 THD = 10% 35 Pdiss (W) Eff (%) 70 30 25 THD = 1% 20 15 10 5 +12 +13 +14 +15 +16 +17 +18 +19 +20 +21 Vcc (V) +22 +23 +24 +25 +26 +27 +28 STA500 DIM. mm MIN. TYP. A a1 inch MAX. MIN. TYP. 3.60 MAX. 0.1417 0.10 0.30 3.30 0.1299 a3 0 0.10 0.0039 b 0.22 0.38 0.0087 0.0150 c 0.23 0.32 0.0091 0.0126 a2 0.0039 OUTLINE AND MECHANICAL DATA 0.0118 D 15.80 16.00 0.6220 0.6299 D1 9.40 9.80 0.3701 0.3858 E 13.90 14.5 0.5472 0.5709 E1 10.90 11.10 0.4291 0.4370 2.90 0.1142 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O E2 E3 5.80 e e3 0.2283 0 H 15.50 h 0.8 0.2441 0.0256 11.05 G L 6.20 0.65 0.4350 0.10 0.0039 15.90 0.6102 0.6260 1.10 0.0433 1.10 0.0315 N 10˚ (max) s 8˚ (max) 0.0433 PowerSO-36 Note: “D and E1” do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006”) - Critical dimensions are "a3", "E" and "G". 0096119 C 9/11 STA500 Table 1. Revision History Date Revision Description of Changes July 2003 6 First Issue January 2006 7 Modified in the Electrical Characteristics table (page 4) the values of VIN-H, VIN-L, VL & VH parameters. Modified the notes 1( page 5). ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 10/11 STA500 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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