STA501A

STA501A 45V 3.5A DOUBLE POWER HALF BRIDGE 1 FEATURES Figure 1. Package ■ MULTIPOWER BCD TECHNOLOGY ■ MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION ) s ( t c u d o s) r ( P t c e u t 2 DESCRIPTION e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o s b O ■ 200mΩ RdsON COMPLEMENTARY DMOS OUTPUT STAGE ■ CMOS COMPATIBLE LOGIC INPUTS ■ THERMAL PROTECTION ■ THERMAL WARNING OUTPUT ■ UNDER VOLTAGE PROTECTION PowerSO36 Table 1. Order Codes Part Number Package STA501A Power SO36 (SLUG UP) The device is particularly designed to make the output stage of a mono All-Digital High Efficiency (DDX™) amplifier capable to deliver 50W @ THD = 10% at Vcc 30V output power on 8Ω load. The input pins have threshold proportional to VL pin voltage. STA501A is a monolithic dual half bridge stage in Multipower BCD Technology. Figure 2. Audio Application Ciruit +3.3V PWRDN R57 10K R59 10K 23 24 PWRDN 25 FAULT 27 26 PROTECTIONS & LOGIC 15 N.C. 7 N.C. 29 N.C. 30 N.C. TRI-STATE C58 100nF TH_WAR C58 100nF VL N.C. C53 100nF C60 100nF TH_WAR 28 18 N.C. VDD 21 17 N.C. VDD 22 VSS 33 VSS 34 12 VCCA VCCSIGN INA GND-Reg GND-Clean 35 36 M15 31 100nF 8 9 OUTA 13 GNDA C110 100nF C109 330pF R103 6 GNDSUB L113 22µH 14 20 19 4 M16 32 2 1 N.C. 10 N.C. 11 OUTB OUTB M14 5 R104 20 VCCB 3 INB INB +VCC C32 1µF OUTA M17 VCCSIGN INA REGULATORS C33 1µF R102 6 C55 1000µF C107 100nF C108 470nF C106 100nF C111 100nF L112 22µH GNDB 100nF 6 D04AU1557A November 2004 Rev. 1 1/9 STA501A Table 2. PIN FUNCTION N° Pin Description 1 GND-SUB Substrate ground 2;3 OUTB Output half bridge 4 Vcc Positive Supply 5 GND Negative Supply 6 GND Negative Supply 7 N.C. Not Connected 8;9 OUTA 10 ; 11 N.C. Not Connected 12 Vcc Positive Supply 13 GND Negative Supply 14 GND Negative Supply 15 N.C. Not Connected 16 ; 17 N.C. Not Connected 18 N.C. Not connected 19 GND-clean Logical ground 20 GND-Reg Ground for regulator Vdd 21 ; 22 Vdd 5V Regulator referred to ground 23 VL High logical state setting voltage 24 N.C. 25 PWRDN 26 TRI-STATE 27 FAULT 28 TH-WAR 29 N.C. Not Connected 30 N.C. Not Connected 31 INA Input of half bridge 32 INB Input of half bridge 33 ; 34 Vss 5V Regulator referred to +Vcc 35 ; 36 Vcc Sign ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs O 2/9 Output half bridge Not Connected Stand-by pin High-Z pin Fault pin advisor Thermal warning advisor Signal Positive Supply STA501A Figure 3. FUNCTIONAL PIN STATUS PIN NAME Logical value IC -STATUS FAULT 0 Fault detected (Short circuit, or Thermal ..) FAULT * 1 Normal Operation TRI-STATE 0 All powers in High-Z state TRI-STATE 1 Normal operation PWRDN 0 Low absorpion PWRDN 1 Normal operation THWAR 0 Temperature of the IC =130C THWAR* 1 Normal operation ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs * : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. Figure 4. PIN CONNECTION O VCCSign 36 1 GND-SUB VCCSign 35 2 OUTB VSS 34 3 OUTB VSS 33 4 VCC INB 32 5 GND INA 31 6 GND N.C. 30 7 N.C. N.C. 29 8 OUTA TH_WAR 28 9 OUTA FAULT 27 10 N.C TRI-STATE 26 11 N.C. PWRDN 25 12 VCC N.C 24 13 GND VL 23 14 N.C. VDD 22 15 VCC VDD 21 16 N.C. GND-Reg 20 17 N.C. GND-Clean 19 18 N.C. D04AU1558 3/9 STA501A Table 3. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Pin 4,7,12,15) 45 V Vmax Maximum Voltage on pins 23 to 32 5.5 V 0 to 70 °C -40 to 150 °C Top Tstg, Tj Operating Temperature Range Storage and Junction Temperature Table 4. THERMAL DATA ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs Symbol Tj-case Parameter Min. Typ. Thermal Resistance Junction to Case (thermal pad) Max. Unit 2.5 °C/W TjSD Thermal shut-down junction temperature 150 °C Twarn Thermal warning temperature 130 °C thSD Thermal shut-down hysteresis 25 °C Table 5. ELECTRICAL CHARACTERISTCS (VL = 3.3V; Vcc = 30V; Tamb = 25°C unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit 200 270 mΩ 50 µA RdsON Power Pchannel/Nchannel MOSFET RdsON Id=1A Idss Power Pchannel/Nchannel leakage Idss Vcc=35V gN Power Pchannel RdsON Matching Id=1A 95 % gP Power Nchannel RdsON Matching Id=1A 95 % Dt_s Low current Dead Time (static) see test circuit no.1; see fig. 5 Dt_d 20 ns High current Dead Time (dinamic) L=22µH; C = 470nF; RL = 8 Ω Id=3.5A; see fig. 7 50 ns td ON Turn-on delay time Resistive load 100 ns td OFF Turn-off delay time Resistive load 100 ns tr Rise time Resistive load 25 ns tf Fall time Resistive load; as fig. 5 25 ns 40 V VL/2 +300mV V O VCC Supply voltage operating voltage VIN-High High level input voltage VIN-Low Low level input voltage IIN-H High level Input current 4/9 10 10 VL/2 300mV Pin voltage = VL V 1 µA STA501A Table 5. ELECTRICAL CHARACTERISTCS (continued) Symbol IIN-L Parameter Test conditions Low level input current IPWRDN-H High level PWRDN pin input current Min. Typ. Max. Unit Pin voltage = 0.3V 1 µA VL3.3V 35 µA VLow Low logical state voltage VLow VL = 3.3V (pin PWRDN, TRISTATE) (note 1) VHigh High logical state voltage VHigh VL = 3.3V (pin PWRDN, TRISTATE) (note 1) 0.8 V 1.7 V ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs IVCCPWRDN Supply Current from Vcc in Power Down IFAULT Output Current pins FAULT -TH-WARN when FAULT CONDITIONS PWRDN = 0 3 mA Vpin = 3.3V 1 mA Supply current from Vcc in Tristate Vcc=30V; Tri-state=0 22 mA IVCC Supply current from Vcc in operation (both channel switching) Input pulse width = 50% Duty; Switching Frequency = 384Khz; No LC filters; 50 mA Iout-sh Overcurrent protection threshold (short circuit current limit) IVCC-hiz VUV 3.5 Undervoltage protection threshold tpw-min Output minimum pulse width 6 8 A 7 No Load 70 V 150 ns Table 6. VL VLow min VHigh max Unit 2.7 0.7 1.5 V 3.3 0.8 1.7 V 5 0.85 1.85 V Notes: 1. The following table explains the VLow, VHigh variation with VL Table 7. LOGIC TRUTH (see fig. 6) TRI-STATE INA INB Q1 Q2 Q3 Q4 OUTPUT MODE 0 x x OFF OFF OFF OFF Hi-Z 1 0 0 OFF OFF ON ON DUMP 1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used O 5/9 STA501A Figure 5. Test Circuit. OUTY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs t DTr Duty cycle = 50% DTf M58 OUTY INY R 8Ω M57 + - V67 = vdc = Vcc/2 gnd D02AU1448 Figure 6. +VCC Q1 Q2 OUTA INA OUTB Q3 INB Q4 GND D02AU1450 Figure 7. High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A O Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 Rload=8Ω OUTA INA Iout=3.5A M57 Q3 DTout(B) L67 22µ C69 470nF L68 22µ C71 470nF C70 470nF DTin(B) OUTB INB Iout=3.5A Q4 Duty cycle A and B: Fixed to have DC output current of 3.5A in the direction shown in figure 6/9 M64 M63 D02AU1451 STA501A Figure 8. PowerSO36 (SLUG UP) Mechanical Data & Package Dimensions DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s MIN. 3.25 3.1 0.8 mm TYP. MAX. 3.43 3.2 1 MIN. 0.128 0.122 0.031 -0.040 0.38 0.32 16 9.8 0.0011 0.008 0.009 0.622 0.37 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.2 0.030 0.22 0.23 15.8 9.4 inch TYP. MAX. 0.135 0.126 0.039 OUTLINE AND MECHANICAL DATA 0.008 -0.0015 0.015 0.012 0.630 0.38 ) s ( t c u d o s) r ( P t c e u t e l rod o s P b PowerSO36 (SLUG UP) e O t e l ) o s s ( t c Ob u od s) r ( P t e uc t e l od o s Pr b O ete l o bs 1 13.9 10.9 5.8 2.9 0.039 0.228 0.114 0.65 11.05 0 15.5 0.8 0.57 0.437 0.114 0.244 1.259 0.026 0.435 0.075 15.9 1.1 1.1 10˚ 8˚ 0 0.61 0.031 0.003 0.625 0.043 0.043 10˚ 8˚ (1) “D and E1” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”) (2) No intrusion allowed inwards the leads. O 7183931 D 7/9 STA501A Table 8. Revision History Date Revision November 2004 1 Description of Changes First Issue ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs O 8/9 STA501A ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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