STA50513TR

STA505 40V 3.5A QUAD POWER HALF BRIDGE 1 FEATURES Figure 1. Package ■ MULTIPOWER BCD TECHNOLOGY ■ MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION ■ 200mΩ RdsON COMPLEMENTARY DMOS OUTPUT STAGE ■ CMOS COMPATIBLE LOGIC INPUTS ■ THERMAL PROTECTION ■ THERMAL WARNING OUTPUT ■ UNDER VOLTAGE PROTECTION Table 1. Order Codes u d o Part Number Package r P e STA505 PowerSO36 STA50513TR in Tape & Reel t e l o current capability. 2 ) s ( ct PowerSO36 DESCRIPTION The device is particularly designed to make the output stage of a stereo All-Digital High Efficiency (DDX™) amplifier capable to deliver 50 + 50W @ THD = 10% at Vcc 30V output power on 8Ω load and 80W @ THD = 10% at Vcc 36V on 8Ω load in single BTL configuration. The input pins have threshold proportional to VL pin voltage. STA505 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half ) (s t c u s b O Figure 2. Audio Application Circuit (Dual BTL)Pin Description d o r P e IN1A 29 VL 23 CONFIG 24 PWRDN PWRDN 25 R59 10K FAULT 27 IN1A +3.3V t e l o bs O R57 10K C58 100nF TH_WAR 26 C53 100nF C60 100nF PROTECTIONS & LOGIC TRI-STATE M5 TH_WAR 28 IN1B 30 VDD 21 VDD 22 VSS 33 VSS 34 VCCSIGN IN2A GND-Reg GND-Clean IN2B GND1A 12 VCC1B REGULATORS 13 GND1B 7 VCC2A IN2B GNDSUB 8 M15 31 20 M16 1 C32 1µF GND2A 4 VCC2B OUT2B OUT2B M14 5 8Ω C21 100nF C110 100nF C109 330pF R103 6 C33 1µF 3 R100 6 C99 100nF C23 470nF C101 100nF L113 22µH OUT2A 6 R98 6 L19 22µH OUT2A 2 32 R63 20 OUT1B OUT1B M4 9 19 C20 100nF C52 330pF C31 1µF 11 C55 1000µF L18 22µH OUT1A 14 10 35 36 C30 1µF OUT1A M17 VCCSIGN IN2A 17 M2 +VCC VCC1A 15 16 IN1B C58 100nF M3 R104 20 R102 6 C107 100nF C108 470nF C106 100nF 8Ω C111 100nF L112 22µH GND2B D00AU1148B February 2006 Rev. 11 1/10 STA505 Table 2. Pin Function N° Pin Description 1 GND-SUB 2;3 OUT2B Output half bridge 2B 4 Vcc2B Positive Supply 5 GND2B Negative Supply 6 GND2A Negative Supply 7 Vcc2A Positive Supply 8;9 OUT2A Output half bridge 2A 10 ; 11 OUT1B Output half bridge 1B 12 Vcc1B Positive Supply 13 GND1B Negative Supply 14 GND1A Negative Supply 15 Vcc1A Positive Supply 16 ; 17 OUT1A Output half bridge 1A 18 NC Not connected 19 GND-clean Logical ground 20 GND-Reg Ground for regulator Vdd 21 ; 22 Vdd 5V Regulator referred to ground 23 VL High logical state setting voltage 24 CONFIG 29 IN1A 25 PWRDN Substrate ground u d o r P e t e l o ) (s t c u d o r Configuration pin P e t e l o s b O ) s ( ct Input of half bridge 1A Stand-by pin 26 TRI-STATE 27 FAULT 28 TH-WAR 29 IN1A Input of half bridge 1A 30 IN1B Input of half bridge 1B 31 IN2A Input of half bridge 2A 32 IN2B Input of half bridge 2B 33 ; 34 Vss 5V Regulator referred to +Vcc 35 ; 36 Vcc Sign 2/10 Hi-Z pin Fault pin advisor Thermal warning advisor Signal Positive Supply s b O STA505 Table 3. Functional Pin Status PIN NAME Logical value IC -STATUS FAULT 0 Fault detected (Short circuit, or Thermal ..) FAULT (*) 1 Normal Operation TRI-STATE 0 All powers in Hi-Z state TRI-STATE 1 Normal operation PWRDN 0 Low absorpion PWRDN 1 Normal operation THWAR 0 Temperature of the IC =130C THWAR(*) 1 Normal operation CONFIG 0 Normal Operation CONFIG(**) 1 OUT1A=OUT1B ; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B) Figure 3. Pin Connection ) (s s b O GND-SUB 2 OUT2B d o r 3 OUT2B 36 VCCSign 35 VSS 34 33 t c u 4 VCC2B P e 32 5 GND2B 31 6 GND2A IN1B 30 7 VCC2A IN1A 29 8 OUT2A VSS O r P e 1 VCCSign IN2B bs u d o t e l o (*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. (**): To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) t e l o ) s ( ct IN2A TH_WAR 28 9 OUT2A FAULT 27 10 OUT1B TRI-STATE 26 11 OUT1B PWRDN 25 12 VCC1B CONFIG 24 13 GND1B VL 23 14 GND1A VDD 22 15 VCC1A VDD 21 16 OUT1A GND-Reg 20 17 OUT1A GND-Clean 19 18 N.C. D01AU1273 3/10 STA505 Table 4. Absolute Maximum Ratings Symbol Parameter Value Unit VCC DC Supply Voltage (Pin 4,7,12,15) 40 V Vmax Maximum Voltage on pins 23 to 32 5.5 V Operating Temperature Range -40 to 90 °C Storage and Junction Temperature -40 to 150 °C Top Tstg, Tj Table 5. Thermal Data Symbol Parameter Min. Typ. Thermal Resistance Junction to Case (thermal pad) Tj-case TjSD Thermal shut-down junction temperature 150 Twarn Thermal warning temperature 130 thSD Thermal shut-down hysteresis 25 e t e ol ) s ( ct Max. Unit 2.5 °C/W du o r P °C °C °C Table 6. Electrical Characteristcs (VL = 3.3V; Vcc = 30V; Tamb = 25°C; fsw = 384Khz; unless otherwise specified) Symbol Parameter bs Test conditions Min. O ) Typ. Max. Unit 200 270 mΩ 50 µA RdsON Power Pchannel/Nchannel MOSFET RdsON Id=1A; Idss Power Pchannel/Nchannel leakage Idss Vcc=35V gN Power Pchannel RdsON Matching Id=1A 95 % gP Power Nchannel RdsON Matching 95 % s ( t c u d o r P e Id=1A Dt_s Low current Dead Time (static) Dt_d High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8 Ω Id=3.5A; see fig. 3 t e l o bs td ON see test circuit no.1; see fig. 1 10 20 ns 50 ns Turn-on delay time Resistive load 100 ns Turn-off delay time Resistive load 100 ns tr Rise time Resistive load; as fig.1; 25 ns tf Fall time Resistive load; as fig. 1; 25 ns 36 V VL/2 +300mV V O td OFF VCC Supply voltage operating voltage 10 VIN-High High level input voltage VIN-Low Low level input voltage IIN-H High level Input current Pin voltage = VL 1 µA IIN-L Low level input current Pin voltage = 0.3V 1 µA 4/10 VL/2 300mV V STA505 Symbol Parameter Test conditions Min. IPWRDN-H High level PWRDN pin input current Low logical state voltage VLow VL = 3.3V (pin PWRDN, TRISTATE) (note 1) VHigh High logical state voltage VHigh VL = 3.3V (pin PWRDN, TRISTATE) (note 1) Supply current from Vcc in Power Down IFAULT Output Current pins FAULT -TH-WARN when FAULT CONDITIONS IVCC-hiz IVCC IVCC-q VUV tpw-min Max. Unit µA 35 VLow IVCCPWRDN Typ. 0.8 V PWRDN = 0 1.7 V 3 mA ) s ( ct Vpin = 3.3V 1 Supply current from Vcc in Tristate Tri-state=0 22 Supply current from Vcc in operation both channel switching) Input pulse width = 50% Duty; Switching Frequency = 384KHz; No LC filters; 50 du 6 8 e t e ol Isc (short circuit current limit) (note 2) 3.5 Undervoltage protection threshold Output minimum pulse width Table 7. No Load ) (s s b O mA o r P mA A 7 70 mA V 150 ns t c u Notes: 1. The following table explains the VLow, VHigh variation with VL d o r VL VLow min VHigh max 2.7 0.7 1.5 V 3.3 0.8 1.7 V 1.85 V 5 t e l o P e 0.85 Unit s b O Note 2: See relevant Application Note AN1994 Table 8. Logic Truth Table (see fig. 5) TRI-STATE INxA INxB Q1 Q2 Q3 Q4 OUTPUT MODE 0 x x OFF OFF OFF OFF Hi-Z 1 0 0 OFF OFF ON ON DUMP 1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used 5/10 STA505 Figure 4. Test Circuit. OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc ) s ( ct t DTr Duty cycle = 50% DTf M58 OUTxY INxY M57 + - D03AU1458 s b O Figure 5. ) (s +VCC t c u Q1 od r P e o s b Figure 6. O Q2 OUTxA OUTxB Q3 let r P e V67 = vdc = Vcc/2 t e l o gnd INxA INxB Q4 GND D00AU1134 High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 Iout=4.5A M57 Q3 DTout(B) Rload=8Ω OUTxA INxA L67 22µ C69 470nF L68 22µ C71 470nF C70 470nF M64 DTin(B) OUTxB INxB Iout=4.5A Q4 Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure 6/10 u d o R 8Ω M63 D00AU1162A STA505 Figure 7. Typical Single BTL Configuration to Obtain 80W @ THD 10%, RL = 8Ω, VCC = 36V (note 1) VL +3.3V GND-Clean GND-Reg 100nF X7R 10K 23 18 N.C. 22µH 100nF VDD VDD CONFIG TH_WAR TH_WAR PWRDN nPWRDN FAULT 10K IN1A IN1B IN1A IN2A IN2B IN1B VSS VSS 100nF X7R 16 20 11 10 21 VCCSIGN 100nF X7R VCCSIGN Add. GNDSUB OUT1A 100nF FILM OUT1A 22Ω 1/2W OUT1B OUT1B 6.2 1/2W OUT2A 22 9 24 OUT2A 330pF 8 6.2 1/2W OUT2B 28 3 25 15 26 29 12 30 7 31 4 VCC1B 2200µF 63V VCC2A VCC2B r P e t e l o GND1B 13 GND2A 36 6 1 5 s b O GND2B ) (s u d o +36V 1µF X7R 14 35 ) s ( ct +36V 1µF X7R GND1A 34 8Ω 22µH VCC1A 32 33 100nF X7R 470nF FILM 100nF X7R 100nF FILM OUT2B 2 27 TRI-STATE 100nF 17 19 D01AU1274 Note: 1. "A PWM modulator as driver is needed . In particular, this result is performed using the STA30X+STA50X demo board". t c u Figure 8. Typical Quad Half Bridge Configuration IN1A 29 VL 23 CONFIG 24 PWRDN 25 od M3 IN1A +3.3V PWRDN R57 10K e t e l R59 10K C58 100nF so TH_WAR b O C58 100nF FAULT 27 26 Pr PROTECTIONS & LOGIC TRI-STATE TH_WAR 28 IN1B 30 VDD 21 VDD 22 VSS 33 VSS 34 M5 C60 100nF VCCSIGN IN2A GND-Reg GND-Clean IN2B OUTPL OUTPL 14 PGND1P 12 VCC1N 11 C51 1µF REGULATORS 13 7 C41 330pF PGND1N VCC2P C71 100nF R51 6 C81 100nF C61 100nF OUTNL OUTNL M4 R41 20 R42 20 C42 330pF C72 100nF R52 6 C82 100nF IN2B GNDSUB 9 36 M15 31 20 19 M16 1 OUTPR 6 PGND2P 4 VCC2N 3 2 32 OUTPR C52 1µF 5 C43 330pF PGND2N D03AU1474 C73 100nF R53 6 C83 100nF C62 100nF OUTNR OUTNR M14 R43 20 C44 330pF R66 5K R67 5K L14 22µH R44 20 R64 5K R65 5K L13 22µH 8 35 R62 5K R63 5K L12 22µH M17 VCCSIGN IN2A 16 R61 5K L11 22µH 17 10 IN1B C53 100nF M2 +VCC VCC1P 15 C74 100nF R54 6 C84 100nF R68 5K C21 2200µF C31 820µF C91 1µF 4Ω C32 820µF C92 1µF 4Ω C33 820µF C93 1µF 4Ω C34 820µF C94 1µF 4Ω For more information refer to the application notes AN1456 and AN1661 7/10 STA505 Figure 9. Power SO36 (Slug up) Mechanical Data & Package Dimensions DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s MIN. 3.25 3.1 0.8 mm TYP. MAX. 3.43 3.2 1 MIN. 0.128 0.122 0.031 -0.040 0.38 0.32 16 9.8 0.0011 0.008 0.009 0.622 0.37 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.2 inch TYP. MAX. 0.135 0.126 0.039 OUTLINE AND MECHANICAL DATA 0.008 0.030 0.22 0.23 15.8 9.4 1 -0.0015 0.015 0.012 0.630 0.38 ) s ( ct 0.039 13.9 10.9 5.8 2.9 0.228 0.114 0.65 11.05 0 15.5 0.026 0.435 0.075 15.9 1.1 1.1 10˚ 8˚ 0.8 0.57 0.437 0.114 0.244 1.259 0 0.61 0.031 0.003 0.625 0.043 0.043 10˚ 8˚ ) (s (1) “D and E1” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”) (2) No intrusion allowed inwards the leads. u d o r P e t e l o s b PowerSO36 (SLUG UP) O t c u d o r P e t e l o s b O 7183931 D 8/10 STA505 Table 9. Revision History Date Revision Description of Changes December 2003 8 First Issue in EDOCS DMS June 2004 9 Note 2: See relevant Application Note AN1994 November 2004 10 Changed Vcc in Electrical Characteristics from 9 min to 10 min February 2006 11 Changed Top value on Table 4. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 9/10 STA505 ) s ( ct u d o r P e t e l o Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ) (s s b O Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. t c u d o r UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. P e t e l o UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. s b O Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 10/10